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-rw-r--r--linux/drivers/media/dvb/b2c2/Kconfig2
-rw-r--r--linux/drivers/media/dvb/b2c2/flexcop-fe-tuner.c48
-rw-r--r--linux/drivers/media/dvb/frontends/Kconfig5
-rw-r--r--linux/drivers/media/dvb/frontends/Makefile1
-rw-r--r--linux/drivers/media/dvb/frontends/itd1000.c408
-rw-r--r--linux/drivers/media/dvb/frontends/itd1000.h42
-rw-r--r--linux/drivers/media/dvb/frontends/itd1000_priv.h88
-rw-r--r--linux/drivers/media/dvb/frontends/s5h1420.c542
-rw-r--r--linux/drivers/media/dvb/frontends/s5h1420.h62
-rw-r--r--linux/drivers/media/dvb/frontends/s5h1420_priv.h380
-rw-r--r--linux/drivers/media/dvb/ttpci/budget.c1
11 files changed, 1369 insertions, 210 deletions
diff --git a/linux/drivers/media/dvb/b2c2/Kconfig b/linux/drivers/media/dvb/b2c2/Kconfig
index 8193d88d1..6ec5afba1 100644
--- a/linux/drivers/media/dvb/b2c2/Kconfig
+++ b/linux/drivers/media/dvb/b2c2/Kconfig
@@ -10,6 +10,8 @@ config DVB_B2C2_FLEXCOP
select DVB_BCM3510 if !DVB_FE_CUSTOMISE
select DVB_LGDT330X if !DVB_FE_CUSTOMISE
select TUNER_SIMPLE if !DVB_FE_CUSTOMISE
+ select DVB_S5H1420 if !DVB_FE_CUSTOMISE
+ select DVB_TUNER_ITD1000 if !DVB_FE_CUSTOMISE
select DVB_ISL6421 if !DVB_FE_CUSTOMISE
select DVB_CX24123 if !DVB_FE_CUSTOMISE
help
diff --git a/linux/drivers/media/dvb/b2c2/flexcop-fe-tuner.c b/linux/drivers/media/dvb/b2c2/flexcop-fe-tuner.c
index 6759c3ad2..04989b7a1 100644
--- a/linux/drivers/media/dvb/b2c2/flexcop-fe-tuner.c
+++ b/linux/drivers/media/dvb/b2c2/flexcop-fe-tuner.c
@@ -19,6 +19,9 @@
#include "dvb-pll.h"
#include "tuner-simple.h"
+#include "s5h1420.h"
+#include "itd1000.h"
+
#include "cx24123.h"
#include "cx24113.h"
@@ -482,6 +485,18 @@ static struct stv0297_config alps_tdee4_stv0297_config = {
};
+/* SkyStar2 rev2.7 (a/u) */
+static struct s5h1420_config skystar2_rev2_7_s5h1420_config = {
+ .demod_address = 0x53,
+ .invert = 1,
+ .repeated_start_workaround = 1,
+};
+
+static struct itd1000_config skystar2_rev2_7_itd1000_config = {
+ .i2c_address = 0x61,
+};
+
+/* SkyStar2 rev2.8 */
static struct cx24123_config skystar2_rev2_8_cx24123_config = {
.demod_address = 0x55,
.dont_use_pll = 1,
@@ -500,6 +515,39 @@ int flexcop_frontend_init(struct flexcop_device *fc)
struct i2c_adapter *i2c = &fc->fc_i2c_adap[0].i2c_adap;
struct i2c_adapter *i2c_tuner;
+ /* enable no_base_addr - no repeated start when reading */
+ fc->fc_i2c_adap[0].no_base_addr = 1;
+ fc->fe = dvb_attach(s5h1420_attach, &skystar2_rev2_7_s5h1420_config, i2c);
+ if (fc->fe != NULL) {
+ flexcop_ibi_value r108;
+ i2c_tuner = s5h1420_get_tuner_i2c_adapter(fc->fe);
+ ops = &fc->fe->ops;
+
+ fc->fe_sleep = ops->sleep;
+ ops->sleep = flexcop_sleep;
+
+ fc->dev_type = FC_SKY_REV27;
+
+ /* enable no_base_addr - no repeated start when reading */
+ fc->fc_i2c_adap[2].no_base_addr = 1;
+ if (dvb_attach(isl6421_attach, fc->fe, &fc->fc_i2c_adap[2].i2c_adap, 0x08, 1, 1) == NULL)
+ err("ISL6421 could NOT be attached");
+ else
+ info("ISL6421 successfully attached");
+
+ /* the ITD1000 requires a lower i2c clock - it slows down the stuff for everyone - but is it a problem ? */
+ r108.raw = 0x00000506;
+ fc->write_ibi_reg(fc, tw_sm_c_108, r108);
+ if (i2c_tuner) {
+ if (dvb_attach(itd1000_attach, fc->fe, i2c_tuner, &skystar2_rev2_7_itd1000_config) == NULL)
+ err("ITD1000 could NOT be attached");
+ else
+ info("ITD1000 successfully attached");
+ }
+ goto fe_found;
+ }
+ fc->fc_i2c_adap[0].no_base_addr = 0; /* for the next devices we need it again */
+
/* try the sky v2.8 (cx24123, isl6421) */
fc->fe = dvb_attach(cx24123_attach,
&skystar2_rev2_8_cx24123_config, i2c);
diff --git a/linux/drivers/media/dvb/frontends/Kconfig b/linux/drivers/media/dvb/frontends/Kconfig
index 0209644f2..4284a3092 100644
--- a/linux/drivers/media/dvb/frontends/Kconfig
+++ b/linux/drivers/media/dvb/frontends/Kconfig
@@ -369,6 +369,11 @@ config DVB_TUNER_XC5000
This device is only used inside a SiP called togther with a
demodulator for now.
+config DVB_TUNER_ITD1000
+ tristate "Integrant ITD1000 Zero IF tuner for DVB-S/DSS"
+ depends on DVB_CORE && I2C
+ default m if DVB_FE_CUSTOMISE
+
comment "Miscellaneous devices"
depends on DVB_CORE
diff --git a/linux/drivers/media/dvb/frontends/Makefile b/linux/drivers/media/dvb/frontends/Makefile
index 23304b377..129367886 100644
--- a/linux/drivers/media/dvb/frontends/Makefile
+++ b/linux/drivers/media/dvb/frontends/Makefile
@@ -52,3 +52,4 @@ obj-$(CONFIG_DVB_TUA6100) += tua6100.o
obj-$(CONFIG_DVB_TUNER_MT2131) += mt2131.o
obj-$(CONFIG_DVB_S5H1409) += s5h1409.o
obj-$(CONFIG_DVB_TUNER_XC5000) += xc5000.o
+obj-$(CONFIG_DVB_TUNER_ITD1000) += itd1000.o
diff --git a/linux/drivers/media/dvb/frontends/itd1000.c b/linux/drivers/media/dvb/frontends/itd1000.c
new file mode 100644
index 000000000..abcd0ddae
--- /dev/null
+++ b/linux/drivers/media/dvb/frontends/itd1000.c
@@ -0,0 +1,408 @@
+/*
+ * Driver for the Integrant ITD1000 "Zero-IF Tuner IC for Direct Broadcast Satellite"
+ *
+ * Copyright (c) 2007-8 Patrick Boettcher <pb@linuxtv.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ *
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.=
+ */
+
+#include <linux/module.h>
+#include <linux/moduleparam.h>
+#include <linux/delay.h>
+#include <linux/dvb/frontend.h>
+#include <linux/i2c.h>
+
+#include "dvb_frontend.h"
+
+#include "itd1000.h"
+#include "itd1000_priv.h"
+
+static int debug;
+module_param(debug, int, 0644);
+MODULE_PARM_DESC(debug, "Turn on/off debugging (default:off).");
+
+#define deb(args...) do { \
+ if (debug) { \
+ printk(KERN_DEBUG "ITD1000: " args);\
+ printk("\n"); \
+ } \
+} while (0)
+
+#define warn(args...) do { \
+ printk(KERN_WARNING "ITD1000: " args); \
+ printk("\n"); \
+} while (0)
+
+#define info(args...) do { \
+ printk(KERN_INFO "ITD1000: " args); \
+ printk("\n"); \
+} while (0)
+
+/* don't write more than one byte with flexcop behind */
+static int itd1000_write_regs(struct itd1000_state *state, u8 reg, u8 v[], u8 len)
+{
+ u8 buf[1+len];
+ struct i2c_msg msg = {
+ .addr = state->cfg->i2c_address, .flags = 0, .buf = buf, .len = len+1
+ };
+ buf[0] = reg;
+ memcpy(&buf[1], v, len);
+
+ /* deb("wr %02x: %02x", reg, v[0]); */
+
+ if (i2c_transfer(state->i2c, &msg, 1) != 1) {
+ printk(KERN_WARNING "itd1000 I2C write failed\n");
+ return -EREMOTEIO;
+ }
+ return 0;
+}
+
+static int itd1000_read_reg(struct itd1000_state *state, u8 reg)
+{
+ u8 val;
+ struct i2c_msg msg[2] = {
+ { .addr = state->cfg->i2c_address, .flags = 0, .buf = &reg, .len = 1 },
+ { .addr = state->cfg->i2c_address, .flags = I2C_M_RD, .buf = &val, .len = 1 },
+ };
+
+ /* ugly flexcop workaround */
+ itd1000_write_regs(state, (reg - 1) & 0xff, &state->shadow[(reg - 1) & 0xff], 1);
+
+ if (i2c_transfer(state->i2c, msg, 2) != 2) {
+ warn("itd1000 I2C read failed");
+ return -EREMOTEIO;
+ }
+ return val;
+}
+
+static inline int itd1000_write_reg(struct itd1000_state *state, u8 r, u8 v)
+{
+ int ret = itd1000_write_regs(state, r, &v, 1);
+ state->shadow[r] = v;
+ return ret;
+}
+
+#if 0
+static void reg_dump(struct itd1000_state *state)
+{
+ int i;
+ for (i = 0x65; i < 0x9c; i++)
+ printk(KERN_DEBUG "ITD: %02x: %02x\n", i, itd1000_read_reg(state, i));
+}
+#endif
+
+static struct {
+ u32 symbol_rate;
+ u8 pgaext : 4; /* PLLFH */
+ u8 bbgvmin : 4; /* BBGVMIN */
+} itd1000_lpf_pga[] = {
+ { 0, 0x8, 0x3 },
+ { 5200000, 0x8, 0x3 },
+ { 12200000, 0x4, 0x3 },
+ { 15400000, 0x2, 0x3 },
+ { 19800000, 0x2, 0x3 },
+ { 21500000, 0x2, 0x3 },
+ { 24500000, 0x2, 0x3 },
+ { 28400000, 0x2, 0x3 },
+ { 33400000, 0x2, 0x3 },
+ { 34400000, 0x1, 0x4 },
+ { 34400000, 0x1, 0x4 },
+ { 38400000, 0x1, 0x4 },
+ { 38400000, 0x1, 0x4 },
+ { 40400000, 0x1, 0x4 },
+ { 45400000, 0x1, 0x4 },
+};
+
+static void itd1000_set_lpf_bw(struct itd1000_state *state, u32 symbol_rate)
+{
+ u8 i;
+ u8 con1 = itd1000_read_reg(state, CON1) & 0xfd;
+ u8 pllfh = itd1000_read_reg(state, PLLFH) & 0x0f;
+ u8 bbgvmin = itd1000_read_reg(state, BBGVMIN) & 0xf0;
+ u8 bw = itd1000_read_reg(state, BW) & 0xf0;
+
+ deb("symbol_rate = %d", symbol_rate);
+
+ /* not sure what is that ? - starting to download the table */
+ itd1000_write_reg(state, CON1, con1 | (1 << 1));
+
+ for (i = 0; i < ARRAY_SIZE(itd1000_lpf_pga); i++)
+ if (symbol_rate < itd1000_lpf_pga[i].symbol_rate) {
+ deb("symrate: index: %d pgaext: %x, bbgvmin: %x", i, itd1000_lpf_pga[i].pgaext, itd1000_lpf_pga[i].bbgvmin);
+ itd1000_write_reg(state, PLLFH, pllfh | (itd1000_lpf_pga[i].pgaext << 4));
+ itd1000_write_reg(state, BBGVMIN, bbgvmin | (itd1000_lpf_pga[i].bbgvmin));
+ itd1000_write_reg(state, BW, bw | (i & 0x0f));
+ break;
+ }
+
+ itd1000_write_reg(state, CON1, con1 | (0 << 1));
+}
+
+static struct {
+ u8 vcorg;
+ u32 fmax_rg;
+} itd1000_vcorg[] = {
+ { 1, 920000 },
+ { 2, 971000 },
+ { 3, 1031000 },
+ { 4, 1091000 },
+ { 5, 1171000 },
+ { 6, 1281000 },
+ { 7, 1381000 },
+ { 8, 500000 }, /* this is intentional. */
+ { 9, 1451000 },
+ { 10, 1531000 },
+ { 11, 1631000 },
+ { 12, 1741000 },
+ { 13, 1891000 },
+ { 14, 2071000 },
+ { 15, 2250000 },
+};
+
+static void itd1000_set_vco(struct itd1000_state *state, u32 freq_khz)
+{
+ u8 i;
+ u8 gvbb_i2c = itd1000_read_reg(state, GVBB_I2C) & 0xbf;
+ u8 vco_chp1_i2c = itd1000_read_reg(state, VCO_CHP1_I2C) & 0x0f;
+ u8 adcout;
+
+ /* reserved bit again (reset ?) */
+ itd1000_write_reg(state, GVBB_I2C, gvbb_i2c | (1 << 6));
+
+ for (i = 0; i < ARRAY_SIZE(itd1000_vcorg); i++) {
+ if (freq_khz < itd1000_vcorg[i].fmax_rg) {
+ itd1000_write_reg(state, VCO_CHP1_I2C, vco_chp1_i2c | (itd1000_vcorg[i].vcorg << 4));
+ msleep(1);
+
+ adcout = itd1000_read_reg(state, PLLLOCK) & 0x0f;
+
+ deb("VCO: %dkHz: %d -> ADCOUT: %d %02x", freq_khz, itd1000_vcorg[i].vcorg, adcout, vco_chp1_i2c);
+
+ if (adcout > 13) {
+ if (!(itd1000_vcorg[i].vcorg == 7 || itd1000_vcorg[i].vcorg == 15))
+ itd1000_write_reg(state, VCO_CHP1_I2C, vco_chp1_i2c | ((itd1000_vcorg[i].vcorg + 1) << 4));
+ } else if (adcout < 2) {
+ if (!(itd1000_vcorg[i].vcorg == 1 || itd1000_vcorg[i].vcorg == 9))
+ itd1000_write_reg(state, VCO_CHP1_I2C, vco_chp1_i2c | ((itd1000_vcorg[i].vcorg - 1) << 4));
+ }
+ break;
+ }
+ }
+}
+
+struct {
+ u32 freq;
+ u8 values[10]; /* RFTR, RFST1 - RFST9 */
+} itd1000_fre_values[] = {
+ { 1075000, { 0x59, 0x1d, 0x1c, 0x17, 0x16, 0x0f, 0x0e, 0x0c, 0x0b, 0x0a } },
+ { 1250000, { 0x89, 0x1e, 0x1d, 0x17, 0x15, 0x0f, 0x0e, 0x0c, 0x0b, 0x0a } },
+ { 1450000, { 0x89, 0x1e, 0x1d, 0x17, 0x15, 0x0f, 0x0e, 0x0c, 0x0b, 0x0a } },
+ { 1650000, { 0x69, 0x1e, 0x1d, 0x17, 0x15, 0x0f, 0x0e, 0x0c, 0x0b, 0x0a } },
+ { 1750000, { 0x69, 0x1e, 0x17, 0x15, 0x14, 0x0f, 0x0e, 0x0c, 0x0b, 0x0a } },
+ { 1850000, { 0x69, 0x1d, 0x17, 0x16, 0x14, 0x0f, 0x0e, 0x0d, 0x0b, 0x0a } },
+ { 1900000, { 0x69, 0x1d, 0x17, 0x15, 0x14, 0x0f, 0x0e, 0x0d, 0x0b, 0x0a } },
+ { 1950000, { 0x69, 0x1d, 0x17, 0x16, 0x14, 0x13, 0x0e, 0x0d, 0x0b, 0x0a } },
+ { 2050000, { 0x69, 0x1e, 0x1d, 0x17, 0x16, 0x14, 0x13, 0x0e, 0x0b, 0x0a } },
+ { 2150000, { 0x69, 0x1d, 0x1c, 0x17, 0x15, 0x14, 0x13, 0x0f, 0x0e, 0x0b } }
+};
+
+
+#define FREF 16
+
+static void itd1000_set_lo(struct itd1000_state *state, u32 freq_khz)
+{
+ int i, j;
+ u32 plln, pllf;
+ u64 tmp;
+
+ plln = (freq_khz * 1000) / 2 / FREF;
+
+ /* Compute the factional part times 1000 */
+ tmp = plln % 1000000;
+ plln /= 1000000;
+
+ tmp *= 1048576;
+ do_div(tmp, 1000000);
+ pllf = (u32) tmp;
+
+ state->frequency = ((plln * 1000) + (pllf * 1000)/1048576) * 2*FREF;
+ deb("frequency: %dkHz (wanted) %dkHz (set), PLLF = %d, PLLN = %d", freq_khz, state->frequency, pllf, plln);
+
+ itd1000_write_reg(state, PLLNH, 0x80); /* PLLNH */;
+ itd1000_write_reg(state, PLLNL, plln & 0xff);
+ itd1000_write_reg(state, PLLFH, (itd1000_read_reg(state, PLLFH) & 0xf0) | ((pllf >> 16) & 0x0f));
+ itd1000_write_reg(state, PLLFM, (pllf >> 8) & 0xff);
+ itd1000_write_reg(state, PLLFL, (pllf >> 0) & 0xff);
+
+ for (i = 0; i < ARRAY_SIZE(itd1000_fre_values); i++) {
+ if (freq_khz <= itd1000_fre_values[i].freq) {
+ deb("fre_values: %d", i);
+ itd1000_write_reg(state, RFTR, itd1000_fre_values[i].values[0]);
+ for (j = 0; j < 9; j++)
+ itd1000_write_reg(state, RFST1+j, itd1000_fre_values[i].values[j+1]);
+ break;
+ }
+ }
+
+ itd1000_set_vco(state, freq_khz);
+}
+
+static int itd1000_set_parameters(struct dvb_frontend *fe, struct dvb_frontend_parameters *p)
+{
+ struct itd1000_state *state = fe->tuner_priv;
+ u8 pllcon1;
+
+ itd1000_set_lo(state, p->frequency);
+ itd1000_set_lpf_bw(state, p->u.qpsk.symbol_rate);
+
+ pllcon1 = itd1000_read_reg(state, PLLCON1) & 0x7f;
+ itd1000_write_reg(state, PLLCON1, pllcon1 | (1 << 7));
+ itd1000_write_reg(state, PLLCON1, pllcon1);
+
+ return 0;
+}
+
+static int itd1000_get_frequency(struct dvb_frontend *fe, u32 *frequency)
+{
+ struct itd1000_state *state = fe->tuner_priv;
+ *frequency = state->frequency;
+ return 0;
+}
+
+static int itd1000_get_bandwidth(struct dvb_frontend *fe, u32 *bandwidth)
+{
+ return 0;
+}
+
+static u8 itd1000_init_tab[][2] = {
+ { PLLCON1, 0x65 }, /* Register does not change */
+ { PLLNH, 0x80 }, /* Bits [7:6] do not change */
+ { RESERVED_0X6D, 0x3b },
+ { VCO_CHP2_I2C, 0x12 },
+ { 0x72, 0xf9 }, /* No such regsister defined */
+ { RESERVED_0X73, 0xff },
+ { RESERVED_0X74, 0xb2 },
+ { RESERVED_0X75, 0xc7 },
+ { EXTGVBBRF, 0xf0 },
+ { DIVAGCCK, 0x80 },
+ { BBTR, 0xa0 },
+ { RESERVED_0X7E, 0x4f },
+ { 0x82, 0x88 }, /* No such regsister defined */
+ { 0x83, 0x80 }, /* No such regsister defined */
+ { 0x84, 0x80 }, /* No such regsister defined */
+ { RESERVED_0X85, 0x74 },
+ { RESERVED_0X86, 0xff },
+ { RESERVED_0X88, 0x02 },
+ { RESERVED_0X89, 0x16 },
+ { RFST0, 0x1f },
+ { RESERVED_0X94, 0x66 },
+ { RESERVED_0X95, 0x66 },
+ { RESERVED_0X96, 0x77 },
+ { RESERVED_0X97, 0x99 },
+ { RESERVED_0X98, 0xff },
+ { RESERVED_0X99, 0xfc },
+ { RESERVED_0X9A, 0xba },
+ { RESERVED_0X9B, 0xaa },
+};
+
+static u8 itd1000_reinit_tab[][2] = {
+ { VCO_CHP1_I2C, 0x8a },
+ { BW, 0x87 },
+ { GVBB_I2C, 0x03 },
+ { BBGVMIN, 0x03 },
+ { CON1, 0x2e },
+};
+
+
+static int itd1000_init(struct dvb_frontend *fe)
+{
+ struct itd1000_state *state = fe->tuner_priv;
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(itd1000_init_tab); i++)
+ itd1000_write_reg(state, itd1000_init_tab[i][0], itd1000_init_tab[i][1]);
+
+ for (i = 0; i < ARRAY_SIZE(itd1000_reinit_tab); i++)
+ itd1000_write_reg(state, itd1000_reinit_tab[i][0], itd1000_reinit_tab[i][1]);
+
+ return 0;
+}
+
+static int itd1000_sleep(struct dvb_frontend *fe)
+{
+ return 0;
+}
+
+static int itd1000_release(struct dvb_frontend *fe)
+{
+ kfree(fe->tuner_priv);
+ fe->tuner_priv = NULL;
+ return 0;
+}
+
+static const struct dvb_tuner_ops itd1000_tuner_ops = {
+ .info = {
+ .name = "Integrant ITD1000",
+ .frequency_min = 950000,
+ .frequency_max = 2150000,
+ .frequency_step = 125, /* kHz for QPSK frontends */
+ },
+
+ .release = itd1000_release,
+
+ .init = itd1000_init,
+ .sleep = itd1000_sleep,
+
+ .set_params = itd1000_set_parameters,
+ .get_frequency = itd1000_get_frequency,
+ .get_bandwidth = itd1000_get_bandwidth
+};
+
+
+struct dvb_frontend *itd1000_attach(struct dvb_frontend *fe, struct i2c_adapter *i2c, struct itd1000_config *cfg)
+{
+ struct itd1000_state *state = NULL;
+ u8 i = 0;
+
+ state = kzalloc(sizeof(struct itd1000_state), GFP_KERNEL);
+ if (state == NULL)
+ return NULL;
+
+ state->cfg = cfg;
+ state->i2c = i2c;
+
+ i = itd1000_read_reg(state, 0);
+ if (i != 0) {
+ kfree(state);
+ return NULL;
+ }
+ info("successfully identified (ID: %d)", i);
+
+ memset(state->shadow, 0xff, sizeof(state->shadow));
+ for (i = 0x65; i < 0x9c; i++)
+ state->shadow[i] = itd1000_read_reg(state, i);
+
+ memcpy(&fe->ops.tuner_ops, &itd1000_tuner_ops, sizeof(struct dvb_tuner_ops));
+
+ fe->tuner_priv = state;
+
+ return fe;
+}
+EXPORT_SYMBOL(itd1000_attach);
+
+MODULE_AUTHOR("Patrick Boettcher <pb@linuxtv.org>");
+MODULE_DESCRIPTION("Integrant ITD1000 driver");
+MODULE_LICENSE("GPL");
diff --git a/linux/drivers/media/dvb/frontends/itd1000.h b/linux/drivers/media/dvb/frontends/itd1000.h
new file mode 100644
index 000000000..5e18df071
--- /dev/null
+++ b/linux/drivers/media/dvb/frontends/itd1000.h
@@ -0,0 +1,42 @@
+/*
+ * Driver for the Integrant ITD1000 "Zero-IF Tuner IC for Direct Broadcast Satellite"
+ *
+ * Copyright (c) 2007 Patrick Boettcher <pb@linuxtv.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ *
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.=
+ */
+
+#ifndef ITD1000_H
+#define ITD1000_H
+
+struct dvb_frontend;
+struct i2c_adapter;
+
+struct itd1000_config {
+ u8 i2c_address;
+};
+
+#if defined(CONFIG_DVB_TUNER_ITD1000) || (defined(CONFIG_DVB_TUNER_ITD1000_MODULE) && defined(MODULE))
+extern struct dvb_frontend *itd1000_attach(struct dvb_frontend *fe, struct i2c_adapter *i2c, struct itd1000_config *cfg);
+#else
+static inline struct dvb_frontend *itd1000_attach(struct dvb_frontend *fe, struct i2c_adapter *i2c, struct itd1000_config *cfg)
+{
+ printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
+ return NULL;
+}
+#endif
+
+#endif
diff --git a/linux/drivers/media/dvb/frontends/itd1000_priv.h b/linux/drivers/media/dvb/frontends/itd1000_priv.h
new file mode 100644
index 000000000..8cdc54e57
--- /dev/null
+++ b/linux/drivers/media/dvb/frontends/itd1000_priv.h
@@ -0,0 +1,88 @@
+/*
+ * Driver for the Integrant ITD1000 "Zero-IF Tuner IC for Direct Broadcast Satellite"
+ *
+ * Copyright (c) 2007 Patrick Boettcher <pb@linuxtv.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ *
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.=
+ */
+
+#ifndef ITD1000_PRIV_H
+#define ITD1000_PRIV_H
+
+struct itd1000_state {
+ struct itd1000_config *cfg;
+ struct i2c_adapter *i2c;
+
+ u32 frequency; /* contains the value resulting from the LO-setting */
+
+ /* ugly workaround for flexcop's incapable i2c-controller
+ * FIXME, if possible
+ */
+ u8 shadow[255];
+};
+
+enum itd1000_register {
+ VCO_CHP1 = 0x65,
+ VCO_CHP2,
+ PLLCON1,
+ PLLNH,
+ PLLNL,
+ PLLFH,
+ PLLFM,
+ PLLFL,
+ RESERVED_0X6D,
+ PLLLOCK,
+ VCO_CHP2_I2C,
+ VCO_CHP1_I2C,
+ BW,
+ RESERVED_0X73 = 0x73,
+ RESERVED_0X74,
+ RESERVED_0X75,
+ GVBB,
+ GVRF,
+ GVBB_I2C,
+ EXTGVBBRF,
+ DIVAGCCK,
+ BBTR,
+ RFTR,
+ BBGVMIN,
+ RESERVED_0X7E,
+ RESERVED_0X85 = 0x85,
+ RESERVED_0X86,
+ CON1,
+ RESERVED_0X88,
+ RESERVED_0X89,
+ RFST0,
+ RFST1,
+ RFST2,
+ RFST3,
+ RFST4,
+ RFST5,
+ RFST6,
+ RFST7,
+ RFST8,
+ RFST9,
+ RESERVED_0X94,
+ RESERVED_0X95,
+ RESERVED_0X96,
+ RESERVED_0X97,
+ RESERVED_0X98,
+ RESERVED_0X99,
+ RESERVED_0X9A,
+ RESERVED_0X9B,
+};
+
+#endif
diff --git a/linux/drivers/media/dvb/frontends/s5h1420.c b/linux/drivers/media/dvb/frontends/s5h1420.c
index 1e2d602d3..4f4f8f918 100644
--- a/linux/drivers/media/dvb/frontends/s5h1420.c
+++ b/linux/drivers/media/dvb/frontends/s5h1420.c
@@ -1,24 +1,26 @@
/*
-Driver for Samsung S5H1420 QPSK Demodulator
-
-Copyright (C) 2005 Andrew de Quincey <adq_dvb@lidskialf.net>
-
-This program is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2 of the License, or
-(at your option) any later version.
-
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with this program; if not, write to the Free Software
-Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
-
-*/
+ * Driver for
+ * Samsung S5H1420 and
+ * PnpNetwork PN1010 QPSK Demodulator
+ *
+ * Copyright (C) 2005 Andrew de Quincey <adq_dvb@lidskialf.net>
+ * Copyright (C) 2005-8 Patrick Boettcher <pb@linuxtv.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ *
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
#include <linux/kernel.h>
#include <linux/module.h>
@@ -29,23 +31,35 @@ Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
#include <linux/jiffies.h>
#include <asm/div64.h>
-#include "dvb_frontend.h"
-#include "s5h1420.h"
+#include <linux/i2c.h>
+#include "dvb_frontend.h"
+#include "s5h1420.h"
+#include "s5h1420_priv.h"
#define TONE_FREQ 22000
struct s5h1420_state {
struct i2c_adapter* i2c;
const struct s5h1420_config* config;
+
struct dvb_frontend frontend;
+ struct i2c_adapter tuner_i2c_adapter;
+
+ u8 CON_1_val;
u8 postlocked:1;
u32 fclk;
u32 tunedfreq;
fe_code_rate_t fec_inner;
u32 symbol_rate;
+
+ /* FIXME: ugly workaround for flexcop's incapable i2c-controller
+ * it does not support repeated-start, workaround: write addr-1
+ * and then read
+ */
+ u8 shadow[255];
};
static u32 s5h1420_getsymbolrate(struct s5h1420_state* state);
@@ -54,43 +68,65 @@ static int s5h1420_get_tune_settings(struct dvb_frontend* fe,
static int debug;
-#define dprintk if (debug) printk
+module_param(debug, int, 0644);
+MODULE_PARM_DESC(debug, "enable debugging");
+
+#define dprintk(x...) do { \
+ if (debug) \
+ printk(KERN_DEBUG "S5H1420: " x); \
+} while (0)
+
+static u8 s5h1420_readreg(struct s5h1420_state *state, u8 reg)
+{
+ int ret;
+ u8 b[2];
+ struct i2c_msg msg[] = {
+ { .addr = state->config->demod_address, .flags = 0, .buf = b, .len = 2 },
+ { .addr = state->config->demod_address, .flags = 0, .buf = &reg, .len = 1 },
+ { .addr = state->config->demod_address, .flags = I2C_M_RD, .buf = b, .len = 1 },
+ };
+
+ b[0] = (reg - 1) & 0xff;
+ b[1] = state->shadow[(reg - 1) & 0xff];
+
+ if (state->config->repeated_start_workaround) {
+ ret = i2c_transfer(state->i2c, msg, 3);
+ if (ret != 3)
+ return ret;
+ } else {
+ ret = i2c_transfer(state->i2c, &msg[1], 2);
+ if (ret != 2)
+ return ret;
+ }
+
+ /* dprintk("rd(%02x): %02x %02x\n", state->config->demod_address, reg, b[0]); */
+
+ return b[0];
+}
static int s5h1420_writereg (struct s5h1420_state* state, u8 reg, u8 data)
{
- u8 buf [] = { reg, data };
+ u8 buf[] = { reg, data };
struct i2c_msg msg = { .addr = state->config->demod_address, .flags = 0, .buf = buf, .len = 2 };
int err;
- if ((err = i2c_transfer (state->i2c, &msg, 1)) != 1) {
- dprintk ("%s: writereg error (err == %i, reg == 0x%02x, data == 0x%02x)\n", __func__, err, reg, data);
+ /* dprintk("wr(%02x): %02x %02x\n", state->config->demod_address, reg, data); */
+ err = i2c_transfer(state->i2c, &msg, 1);
+ if (err != 1) {
+ dprintk("%s: writereg error (err == %i, reg == 0x%02x, data == 0x%02x)\n", __func__, err, reg, data);
return -EREMOTEIO;
}
+ state->shadow[reg] = data;
return 0;
}
-static u8 s5h1420_readreg (struct s5h1420_state* state, u8 reg)
-{
- int ret;
- u8 b0 [] = { reg };
- u8 b1 [] = { 0 };
- struct i2c_msg msg1 = { .addr = state->config->demod_address, .flags = 0, .buf = b0, .len = 1 };
- struct i2c_msg msg2 = { .addr = state->config->demod_address, .flags = I2C_M_RD, .buf = b1, .len = 1 };
-
- if ((ret = i2c_transfer (state->i2c, &msg1, 1)) != 1)
- return ret;
-
- if ((ret = i2c_transfer (state->i2c, &msg2, 1)) != 1)
- return ret;
-
- return b1[0];
-}
-
static int s5h1420_set_voltage (struct dvb_frontend* fe, fe_sec_voltage_t voltage)
{
struct s5h1420_state* state = fe->demodulator_priv;
+ dprintk("enter %s\n", __func__);
+
switch(voltage) {
case SEC_VOLTAGE_13:
s5h1420_writereg(state, 0x3c,
@@ -106,6 +142,7 @@ static int s5h1420_set_voltage (struct dvb_frontend* fe, fe_sec_voltage_t voltag
break;
}
+ dprintk("leave %s\n", __func__);
return 0;
}
@@ -113,6 +150,7 @@ static int s5h1420_set_tone (struct dvb_frontend* fe, fe_sec_tone_mode_t tone)
{
struct s5h1420_state* state = fe->demodulator_priv;
+ dprintk("enter %s\n", __func__);
switch(tone) {
case SEC_TONE_ON:
s5h1420_writereg(state, 0x3b,
@@ -124,6 +162,7 @@ static int s5h1420_set_tone (struct dvb_frontend* fe, fe_sec_tone_mode_t tone)
(s5h1420_readreg(state, 0x3b) & 0x74) | 0x01);
break;
}
+ dprintk("leave %s\n", __func__);
return 0;
}
@@ -137,6 +176,7 @@ static int s5h1420_send_master_cmd (struct dvb_frontend* fe,
unsigned long timeout;
int result = 0;
+ dprintk("enter %s\n", __func__);
if (cmd->msg_len > 8)
return -EINVAL;
@@ -168,6 +208,7 @@ static int s5h1420_send_master_cmd (struct dvb_frontend* fe,
/* restore original settings */
s5h1420_writereg(state, 0x3b, val);
msleep(15);
+ dprintk("leave %s\n", __func__);
return result;
}
@@ -289,6 +330,8 @@ static int s5h1420_read_status(struct dvb_frontend* fe, fe_status_t* status)
struct s5h1420_state* state = fe->demodulator_priv;
u8 val;
+ dprintk("enter %s\n", __func__);
+
if (status == NULL)
return -EINVAL;
@@ -297,13 +340,13 @@ static int s5h1420_read_status(struct dvb_frontend* fe, fe_status_t* status)
/* fix for FEC 5/6 inversion issue - if it doesn't quite lock, invert
the inversion, wait a bit and check again */
- if (*status == (FE_HAS_SIGNAL|FE_HAS_CARRIER|FE_HAS_VITERBI)) {
- val = s5h1420_readreg(state, 0x32);
+ if (*status == (FE_HAS_SIGNAL | FE_HAS_CARRIER | FE_HAS_VITERBI)) {
+ val = s5h1420_readreg(state, Vit10);
if ((val & 0x07) == 0x03) {
if (val & 0x08)
- s5h1420_writereg(state, 0x31, 0x13);
+ s5h1420_writereg(state, Vit09, 0x13);
else
- s5h1420_writereg(state, 0x31, 0x1b);
+ s5h1420_writereg(state, Vit09, 0x1b);
/* wait a bit then update lock status */
mdelay(200);
@@ -312,68 +355,77 @@ static int s5h1420_read_status(struct dvb_frontend* fe, fe_status_t* status)
}
/* perform post lock setup */
- if ((*status & FE_HAS_LOCK) && (!state->postlocked)) {
+ if ((*status & FE_HAS_LOCK) && !state->postlocked) {
/* calculate the data rate */
u32 tmp = s5h1420_getsymbolrate(state);
- switch(s5h1420_readreg(state, 0x32) & 0x07) {
- case 0:
- tmp = (tmp * 2 * 1) / 2;
- break;
-
- case 1:
- tmp = (tmp * 2 * 2) / 3;
- break;
-
- case 2:
- tmp = (tmp * 2 * 3) / 4;
- break;
-
- case 3:
- tmp = (tmp * 2 * 5) / 6;
- break;
-
- case 4:
- tmp = (tmp * 2 * 6) / 7;
- break;
-
- case 5:
- tmp = (tmp * 2 * 7) / 8;
- break;
+ switch (s5h1420_readreg(state, Vit10) & 0x07) {
+ case 0: tmp = (tmp * 2 * 1) / 2; break;
+ case 1: tmp = (tmp * 2 * 2) / 3; break;
+ case 2: tmp = (tmp * 2 * 3) / 4; break;
+ case 3: tmp = (tmp * 2 * 5) / 6; break;
+ case 4: tmp = (tmp * 2 * 6) / 7; break;
+ case 5: tmp = (tmp * 2 * 7) / 8; break;
}
+
if (tmp == 0) {
- printk("s5h1420: avoided division by 0\n");
+ printk(KERN_ERR "s5h1420: avoided division by 0\n");
tmp = 1;
}
tmp = state->fclk / tmp;
+
/* set the MPEG_CLK_INTL for the calculated data rate */
- if (tmp < 4)
+ if (tmp < 2)
val = 0x00;
- else if (tmp < 8)
+ else if (tmp < 5)
val = 0x01;
- else if (tmp < 12)
+ else if (tmp < 9)
val = 0x02;
- else if (tmp < 16)
+ else if (tmp < 13)
val = 0x03;
- else if (tmp < 24)
+ else if (tmp < 17)
val = 0x04;
- else if (tmp < 32)
+ else if (tmp < 25)
val = 0x05;
- else
+ else if (tmp < 33)
val = 0x06;
- s5h1420_writereg(state, 0x22, val);
-
- /* DC freeze */
- s5h1420_writereg(state, 0x1f, s5h1420_readreg(state, 0x1f) | 0x01);
-
- /* kicker disable + remove DC offset */
- s5h1420_writereg(state, 0x05, s5h1420_readreg(state, 0x05) & 0x6f);
+ else
+ val = 0x07;
+ dprintk("for MPEG_CLK_INTL %d %x\n", tmp, val);
+
+ s5h1420_writereg(state, FEC01, 0x18);
+ s5h1420_writereg(state, FEC01, 0x10);
+ s5h1420_writereg(state, FEC01, val);
+
+ /* Enable "MPEG_Out" */
+ val = s5h1420_readreg(state, Mpeg02);
+ s5h1420_writereg(state, Mpeg02, val | (1 << 6));
+
+ /* kicker disable */
+ val = s5h1420_readreg(state, QPSK01) & 0x7f;
+ s5h1420_writereg(state, QPSK01, val);
+
+ /* DC freeze TODO it was never activated by default or it can stay activated */
+#if 0
+ val = s5h1420_readreg(state, 0x1f);
+ s5h1420_writereg(state, 0x1f, val | 0x01);
+#endif
+
+ if (s5h1420_getsymbolrate(state) >= 20000000) {
+ s5h1420_writereg(state, Loop04, 0x8a);
+ s5h1420_writereg(state, Loop05, 0x6a);
+ } else {
+ s5h1420_writereg(state, Loop04, 0x58);
+ s5h1420_writereg(state, Loop05, 0x27);
+ }
/* post-lock processing has been done! */
state->postlocked = 1;
}
+ dprintk("leave %s\n", __func__);
+
return 0;
}
@@ -414,6 +466,7 @@ static int s5h1420_read_ucblocks(struct dvb_frontend* fe, u32* ucblocks)
static void s5h1420_reset(struct s5h1420_state* state)
{
+ dprintk("%s\n", __func__);
s5h1420_writereg (state, 0x01, 0x08);
s5h1420_writereg (state, 0x01, 0x00);
udelay(10);
@@ -422,54 +475,79 @@ static void s5h1420_reset(struct s5h1420_state* state)
static void s5h1420_setsymbolrate(struct s5h1420_state* state,
struct dvb_frontend_parameters *p)
{
+ u8 v;
u64 val;
+ dprintk("enter %s\n", __func__);
+
val = ((u64) p->u.qpsk.symbol_rate / 1000ULL) * (1ULL<<24);
- if (p->u.qpsk.symbol_rate <= 21000000) {
+ if (p->u.qpsk.symbol_rate < 29000000)
val *= 2;
- }
do_div(val, (state->fclk / 1000));
- s5h1420_writereg(state, 0x09, s5h1420_readreg(state, 0x09) & 0x7f);
- s5h1420_writereg(state, 0x11, val >> 16);
- s5h1420_writereg(state, 0x12, val >> 8);
- s5h1420_writereg(state, 0x13, val & 0xff);
- s5h1420_writereg(state, 0x09, s5h1420_readreg(state, 0x09) | 0x80);
+ dprintk("symbol rate register: %06llx\n", val);
+
+ v = s5h1420_readreg(state, Loop01);
+ s5h1420_writereg(state, Loop01, v & 0x7f);
+ s5h1420_writereg(state, Tnco01, val >> 16);
+ s5h1420_writereg(state, Tnco02, val >> 8);
+ s5h1420_writereg(state, Tnco03, val & 0xff);
+ s5h1420_writereg(state, Loop01, v | 0x80);
+ dprintk("leave %s\n", __func__);
}
static u32 s5h1420_getsymbolrate(struct s5h1420_state* state)
{
+#if 0
+ /* TODO getsymbolrate gives strange values - something is wrong with
+ * configuring the read
+ */
+
u64 val = 0;
+ u8 v;
int sampling = 2;
- if (s5h1420_readreg(state, 0x05) & 0x2)
- sampling = 1;
+ v = s5h1420_readreg(state, QPSK02);
+ s5h1420_writereg(state, QPSK02, v | 0x08);
+ val = s5h1420_readreg(state, Tnco01) << 16;
+ val |= s5h1420_readreg(state, Tnco02) << 8;
+ val |= s5h1420_readreg(state, Tnco03);
+ s5h1420_writereg(state, QPSK02, v & 0xf7);
- s5h1420_writereg(state, 0x06, s5h1420_readreg(state, 0x06) | 0x08);
- val = s5h1420_readreg(state, 0x11) << 16;
- val |= s5h1420_readreg(state, 0x12) << 8;
- val |= s5h1420_readreg(state, 0x13);
- s5h1420_writereg(state, 0x06, s5h1420_readreg(state, 0x06) & 0xf7);
+ dprintk("get_symbolrate: raw: %x\n", val);
- val *= (state->fclk / 1000ULL);
- do_div(val, ((1<<24) * sampling));
+ val *= (state->fclk / 1000);
+ if (s5h1420_readreg(state, QPSK01) & 0x2)
+ do_div(val, 1 << 24);
+ else
+ do_div(val, 1 << 25);
+ dprintk("get_symbolrate: %d\n", (u32) (val * 1000ULL));
return (u32) (val * 1000ULL);
+#endif
+ return state->symbol_rate;
}
static void s5h1420_setfreqoffset(struct s5h1420_state* state, int freqoffset)
{
int val;
+ u8 v;
+
+ dprintk("enter %s\n", __func__);
/* remember freqoffset is in kHz, but the chip wants the offset in Hz, so
* divide fclk by 1000000 to get the correct value. */
val = -(int) ((freqoffset * (1<<24)) / (state->fclk / 1000000));
- s5h1420_writereg(state, 0x09, s5h1420_readreg(state, 0x09) & 0xbf);
- s5h1420_writereg(state, 0x0e, val >> 16);
- s5h1420_writereg(state, 0x0f, val >> 8);
- s5h1420_writereg(state, 0x10, val & 0xff);
- s5h1420_writereg(state, 0x09, s5h1420_readreg(state, 0x09) | 0x40);
+ dprintk("phase rotator/freqoffset: %d %06x\n", freqoffset, val);
+
+ v = s5h1420_readreg(state, Loop01);
+ s5h1420_writereg(state, Loop01, v & 0xbf);
+ s5h1420_writereg(state, Pnco01, val >> 16);
+ s5h1420_writereg(state, Pnco02, val >> 8);
+ s5h1420_writereg(state, Pnco03, val & 0xff);
+ s5h1420_writereg(state, Loop01, v | 0x40);
+ dprintk("leave %s\n", __func__);
}
static int s5h1420_getfreqoffset(struct s5h1420_state* state)
@@ -496,52 +574,53 @@ static void s5h1420_setfec_inversion(struct s5h1420_state* state,
struct dvb_frontend_parameters *p)
{
u8 inversion = 0;
+ u8 vit08, vit09;
+
+ dprintk("enter %s\n", __func__);
- if (p->inversion == INVERSION_OFF) {
+ if (p->inversion == INVERSION_OFF)
inversion = state->config->invert ? 0x08 : 0;
- } else if (p->inversion == INVERSION_ON) {
+ else if (p->inversion == INVERSION_ON)
inversion = state->config->invert ? 0 : 0x08;
- }
if ((p->u.qpsk.fec_inner == FEC_AUTO) || (p->inversion == INVERSION_AUTO)) {
- s5h1420_writereg(state, 0x30, 0x3f);
- s5h1420_writereg(state, 0x31, 0x00 | inversion);
+ vit08 = 0x3f;
+ vit09 = 0;
} else {
switch(p->u.qpsk.fec_inner) {
case FEC_1_2:
- s5h1420_writereg(state, 0x30, 0x01);
- s5h1420_writereg(state, 0x31, 0x10 | inversion);
+ vit08 = 0x01; vit09 = 0x10;
break;
case FEC_2_3:
- s5h1420_writereg(state, 0x30, 0x02);
- s5h1420_writereg(state, 0x31, 0x11 | inversion);
+ vit08 = 0x02; vit09 = 0x11;
break;
case FEC_3_4:
- s5h1420_writereg(state, 0x30, 0x04);
- s5h1420_writereg(state, 0x31, 0x12 | inversion);
+ vit08 = 0x04; vit09 = 0x12;
break;
case FEC_5_6:
- s5h1420_writereg(state, 0x30, 0x08);
- s5h1420_writereg(state, 0x31, 0x13 | inversion);
+ vit08 = 0x08; vit09 = 0x13;
break;
case FEC_6_7:
- s5h1420_writereg(state, 0x30, 0x10);
- s5h1420_writereg(state, 0x31, 0x14 | inversion);
+ vit08 = 0x10; vit09 = 0x14;
break;
case FEC_7_8:
- s5h1420_writereg(state, 0x30, 0x20);
- s5h1420_writereg(state, 0x31, 0x15 | inversion);
+ vit08 = 0x20; vit09 = 0x15;
break;
default:
return;
}
}
+ vit09 |= inversion;
+ dprintk("fec: %02x %02x\n", vit08, vit09);
+ s5h1420_writereg(state, Vit08, vit08);
+ s5h1420_writereg(state, Vit09, vit09);
+ dprintk("leave %s\n", __func__);
}
static fe_code_rate_t s5h1420_getfec(struct s5h1420_state* state)
@@ -583,16 +662,19 @@ static int s5h1420_set_frontend(struct dvb_frontend* fe,
struct s5h1420_state* state = fe->demodulator_priv;
int frequency_delta;
struct dvb_frontend_tune_settings fesettings;
+ uint8_t clock_settting;
+
+ dprintk("enter %s\n", __func__);
/* check if we should do a fast-tune */
memcpy(&fesettings.parameters, p, sizeof(struct dvb_frontend_parameters));
s5h1420_get_tune_settings(fe, &fesettings);
frequency_delta = p->frequency - state->tunedfreq;
if ((frequency_delta > -fesettings.max_drift) &&
- (frequency_delta < fesettings.max_drift) &&
- (frequency_delta != 0) &&
- (state->fec_inner == p->u.qpsk.fec_inner) &&
- (state->symbol_rate == p->u.qpsk.symbol_rate)) {
+ (frequency_delta < fesettings.max_drift) &&
+ (frequency_delta != 0) &&
+ (state->fec_inner == p->u.qpsk.fec_inner) &&
+ (state->symbol_rate == p->u.qpsk.symbol_rate)) {
if (fe->ops.tuner_ops.set_params) {
fe->ops.tuner_ops.set_params(fe, p);
@@ -606,54 +688,93 @@ static int s5h1420_set_frontend(struct dvb_frontend* fe,
} else {
s5h1420_setfreqoffset(state, 0);
}
+ dprintk("simple tune\n");
return 0;
}
+ dprintk("tuning demod\n");
/* first of all, software reset */
s5h1420_reset(state);
/* set s5h1420 fclk PLL according to desired symbol rate */
- if (p->u.qpsk.symbol_rate > 28000000) {
- state->fclk = 88000000;
- s5h1420_writereg(state, 0x03, 0x50);
- s5h1420_writereg(state, 0x04, 0x40);
- s5h1420_writereg(state, 0x05, 0xae);
- } else if (p->u.qpsk.symbol_rate > 21000000) {
+ if (p->u.qpsk.symbol_rate > 33000000)
+ state->fclk = 80000000;
+ else if (p->u.qpsk.symbol_rate > 28500000)
state->fclk = 59000000;
- s5h1420_writereg(state, 0x03, 0x33);
- s5h1420_writereg(state, 0x04, 0x40);
- s5h1420_writereg(state, 0x05, 0xae);
- } else {
+ else if (p->u.qpsk.symbol_rate > 25000000)
+ state->fclk = 86000000;
+ else if (p->u.qpsk.symbol_rate > 1900000)
state->fclk = 88000000;
- s5h1420_writereg(state, 0x03, 0x50);
- s5h1420_writereg(state, 0x04, 0x40);
- s5h1420_writereg(state, 0x05, 0xac);
+ else
+ state->fclk = 44000000;
+
+ /* Clock */
+ switch (state->fclk) {
+ default:
+ case 88000000:
+ clock_settting = 80;
+ break;
+ case 86000000:
+ clock_settting = 78;
+ break;
+ case 80000000:
+ clock_settting = 72;
+ break;
+ case 59000000:
+ clock_settting = 51;
+ break;
+ case 44000000:
+ clock_settting = 36;
+ break;
}
+ dprintk("pll01: %d, ToneFreq: %d\n", state->fclk/1000000 - 8, (state->fclk + (TONE_FREQ * 32) - 1) / (TONE_FREQ * 32));
+ s5h1420_writereg(state, PLL01, state->fclk/1000000 - 8);
+ s5h1420_writereg(state, PLL02, 0x40);
+ s5h1420_writereg(state, DiS01, (state->fclk + (TONE_FREQ * 32) - 1) / (TONE_FREQ * 32));
- /* set misc registers */
- s5h1420_writereg(state, 0x02, 0x00);
- s5h1420_writereg(state, 0x06, 0x00);
- s5h1420_writereg(state, 0x07, 0xb0);
- s5h1420_writereg(state, 0x0a, 0xe7);
- s5h1420_writereg(state, 0x0b, 0x78);
- s5h1420_writereg(state, 0x0c, 0x48);
- s5h1420_writereg(state, 0x0d, 0x6b);
- s5h1420_writereg(state, 0x2e, 0x8e);
- s5h1420_writereg(state, 0x35, 0x33);
- s5h1420_writereg(state, 0x38, 0x01);
- s5h1420_writereg(state, 0x39, 0x7d);
- s5h1420_writereg(state, 0x3a, (state->fclk + (TONE_FREQ * 32) - 1) / (TONE_FREQ * 32));
- s5h1420_writereg(state, 0x3c, 0x00);
- s5h1420_writereg(state, 0x45, 0x61);
- s5h1420_writereg(state, 0x46, 0x1d);
+ /* TODO DC offset removal, config parameter ? */
+ if (p->u.qpsk.symbol_rate > 29000000)
+ s5h1420_writereg(state, QPSK01, 0xae | 0x10);
+ else
+ s5h1420_writereg(state, QPSK01, 0xac | 0x10);
- /* start QPSK */
- s5h1420_writereg(state, 0x05, s5h1420_readreg(state, 0x05) | 1);
+ /* set misc registers */
+ s5h1420_writereg(state, CON_1, 0x00);
+ s5h1420_writereg(state, QPSK02, 0x00);
+ s5h1420_writereg(state, Pre01, 0xb0);
+
+ s5h1420_writereg(state, Loop01, 0xF0);
+ s5h1420_writereg(state, Loop02, 0x2a); /* e7 for s5h1420 */
+ s5h1420_writereg(state, Loop03, 0x79); /* 78 for s5h1420 */
+ if (p->u.qpsk.symbol_rate > 20000000)
+ s5h1420_writereg(state, Loop04, 0x79);
+ else
+ s5h1420_writereg(state, Loop04, 0x58);
+ s5h1420_writereg(state, Loop05, 0x6b);
+
+ if (p->u.qpsk.symbol_rate >= 8000000)
+ s5h1420_writereg(state, Post01, (0 << 6) | 0x10);
+ else if (p->u.qpsk.symbol_rate >= 4000000)
+ s5h1420_writereg(state, Post01, (1 << 6) | 0x10);
+ else
+ s5h1420_writereg(state, Post01, (3 << 6) | 0x10);
+
+ s5h1420_writereg(state, Monitor12, 0x00); /* unfreeze DC compensation */
+
+ s5h1420_writereg(state, Sync01, 0x33);
+ s5h1420_writereg(state, Mpeg01, state->config->cdclk_polarity);
+ s5h1420_writereg(state, Mpeg02, 0x3d); /* Parallel output more, disabled -> enabled later */
+ s5h1420_writereg(state, Err01, 0x03); /* 0x1d for s5h1420 */
+
+ s5h1420_writereg(state, Vit06, 0x6e); /* 0x8e for s5h1420 */
+ s5h1420_writereg(state, DiS03, 0x00);
+ s5h1420_writereg(state, Rf01, 0x61); /* Tuner i2c address - for the gate controller */
/* set tuner PLL */
if (fe->ops.tuner_ops.set_params) {
fe->ops.tuner_ops.set_params(fe, p);
- if (fe->ops.i2c_gate_ctrl) fe->ops.i2c_gate_ctrl(fe, 0);
+ if (fe->ops.i2c_gate_ctrl)
+ fe->ops.i2c_gate_ctrl(fe, 0);
s5h1420_setfreqoffset(state, 0);
}
@@ -661,10 +782,15 @@ static int s5h1420_set_frontend(struct dvb_frontend* fe,
s5h1420_setsymbolrate(state, p);
s5h1420_setfec_inversion(state, p);
+ /* start QPSK */
+ s5h1420_writereg(state, QPSK01, s5h1420_readreg(state, QPSK01) | 1);
+
state->fec_inner = p->u.qpsk.fec_inner;
state->symbol_rate = p->u.qpsk.symbol_rate;
state->postlocked = 0;
state->tunedfreq = p->frequency;
+
+ dprintk("leave %s\n", __func__);
return 0;
}
@@ -717,11 +843,10 @@ static int s5h1420_i2c_gate_ctrl(struct dvb_frontend* fe, int enable)
{
struct s5h1420_state* state = fe->demodulator_priv;
- if (enable) {
- return s5h1420_writereg (state, 0x02, s5h1420_readreg(state,0x02) | 1);
- } else {
- return s5h1420_writereg (state, 0x02, s5h1420_readreg(state,0x02) & 0xfe);
- }
+ if (enable)
+ return s5h1420_writereg(state, 0x02, state->CON_1_val | 1);
+ else
+ return s5h1420_writereg(state, 0x02, state->CON_1_val & 0xfe);
}
static int s5h1420_init (struct dvb_frontend* fe)
@@ -729,7 +854,8 @@ static int s5h1420_init (struct dvb_frontend* fe)
struct s5h1420_state* state = fe->demodulator_priv;
/* disable power down and do reset */
- s5h1420_writereg(state, 0x02, 0x10);
+ state->CON_1_val = 0x10;
+ s5h1420_writereg(state, 0x02, state->CON_1_val);
msleep(10);
s5h1420_reset(state);
@@ -739,26 +865,60 @@ static int s5h1420_init (struct dvb_frontend* fe)
static int s5h1420_sleep(struct dvb_frontend* fe)
{
struct s5h1420_state* state = fe->demodulator_priv;
-
- return s5h1420_writereg(state, 0x02, 0x12);
+ state->CON_1_val = 0x12;
+ return s5h1420_writereg(state, 0x02, state->CON_1_val);
}
static void s5h1420_release(struct dvb_frontend* fe)
{
struct s5h1420_state* state = fe->demodulator_priv;
+ i2c_del_adapter(&state->tuner_i2c_adapter);
kfree(state);
}
-static struct dvb_frontend_ops s5h1420_ops;
+static u32 s5h1420_tuner_i2c_func(struct i2c_adapter *adapter)
+{
+ return I2C_FUNC_I2C;
+}
+
+static int s5h1420_tuner_i2c_tuner_xfer(struct i2c_adapter *i2c_adap, struct i2c_msg msg[], int num)
+{
+ struct s5h1420_state *state = i2c_get_adapdata(i2c_adap);
+ struct i2c_msg m[1 + num];
+ u8 tx_open[2] = { CON_1, state->CON_1_val | 1 }; /* repeater stops once there was a stop condition */
+
+ memset(m, 0, sizeof(struct i2c_msg) * (1 + num));
+
+ m[0].addr = state->config->demod_address;
+ m[0].buf = tx_open;
+ m[0].len = 2;
+
+ memcpy(&m[1], msg, sizeof(struct i2c_msg) * num);
-struct dvb_frontend* s5h1420_attach(const struct s5h1420_config* config,
- struct i2c_adapter* i2c)
+ return i2c_transfer(state->i2c, m, 1+num) == 1 + num ? num : -EIO;
+}
+
+static struct i2c_algorithm s5h1420_tuner_i2c_algo = {
+ .master_xfer = s5h1420_tuner_i2c_tuner_xfer,
+ .functionality = s5h1420_tuner_i2c_func,
+};
+
+struct i2c_adapter *s5h1420_get_tuner_i2c_adapter(struct dvb_frontend *fe)
{
- struct s5h1420_state* state = NULL;
- u8 identity;
+ struct s5h1420_state *state = fe->demodulator_priv;
+ return &state->tuner_i2c_adapter;
+}
+EXPORT_SYMBOL(s5h1420_get_tuner_i2c_adapter);
+
+static struct dvb_frontend_ops s5h1420_ops;
+struct dvb_frontend *s5h1420_attach(const struct s5h1420_config *config,
+ struct i2c_adapter *i2c)
+{
/* allocate memory for the internal state */
- state = kmalloc(sizeof(struct s5h1420_state), GFP_KERNEL);
+ struct s5h1420_state *state = kzalloc(sizeof(struct s5h1420_state), GFP_KERNEL);
+ u8 i;
+
if (state == NULL)
goto error;
@@ -772,24 +932,42 @@ struct dvb_frontend* s5h1420_attach(const struct s5h1420_config* config,
state->symbol_rate = 0;
/* check if the demod is there + identify it */
- identity = s5h1420_readreg(state, 0x00);
- if (identity != 0x03)
+ i = s5h1420_readreg(state, ID01);
+ if (i != 0x03)
goto error;
+ memset(state->shadow, 0xff, sizeof(state->shadow));
+
+ for (i = 0; i < 0x50; i++)
+ state->shadow[i] = s5h1420_readreg(state, i);
+
/* create dvb_frontend */
memcpy(&state->frontend.ops, &s5h1420_ops, sizeof(struct dvb_frontend_ops));
state->frontend.demodulator_priv = state;
+
+ /* create tuner i2c adapter */
+ strncpy(state->tuner_i2c_adapter.name, "S5H1420-PN1010 tuner I2C bus", I2C_NAME_SIZE);
+ state->tuner_i2c_adapter.class = I2C_CLASS_TV_DIGITAL,
+ state->tuner_i2c_adapter.algo = &s5h1420_tuner_i2c_algo;
+ state->tuner_i2c_adapter.algo_data = NULL;
+ i2c_set_adapdata(&state->tuner_i2c_adapter, state);
+ if (i2c_add_adapter(&state->tuner_i2c_adapter) < 0) {
+ printk(KERN_ERR "S5H1420/PN1010: tuner i2c bus could not be initialized\n");
+ goto error;
+ }
+
return &state->frontend;
error:
kfree(state);
return NULL;
}
+EXPORT_SYMBOL(s5h1420_attach);
static struct dvb_frontend_ops s5h1420_ops = {
.info = {
- .name = "Samsung S5H1420 DVB-S",
+ .name = "Samsung S5H1420/PnpNetwork PN1010 DVB-S",
.type = FE_QPSK,
.frequency_min = 950000,
.frequency_max = 2150000,
@@ -826,10 +1004,6 @@ static struct dvb_frontend_ops s5h1420_ops = {
.set_voltage = s5h1420_set_voltage,
};
-module_param(debug, int, 0644);
-
-MODULE_DESCRIPTION("Samsung S5H1420 DVB-S Demodulator driver");
-MODULE_AUTHOR("Andrew de Quincey");
+MODULE_DESCRIPTION("Samsung S5H1420/PnpNetwork PN1010 DVB-S Demodulator driver");
+MODULE_AUTHOR("Andrew de Quincey, Patrick Boettcher");
MODULE_LICENSE("GPL");
-
-EXPORT_SYMBOL(s5h1420_attach);
diff --git a/linux/drivers/media/dvb/frontends/s5h1420.h b/linux/drivers/media/dvb/frontends/s5h1420.h
index 2cc785012..4c913f142 100644
--- a/linux/drivers/media/dvb/frontends/s5h1420.h
+++ b/linux/drivers/media/dvb/frontends/s5h1420.h
@@ -1,25 +1,26 @@
/*
- Driver for S5H1420 QPSK Demodulators
-
- Copyright (C) 2005 Andrew de Quincey <adq_dvb@lidskialf.net>
-
- This program is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 2 of the License, or
- (at your option) any later version.
-
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software
- Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
-
-*/
-
+ * Driver for
+ * Samsung S5H1420 and
+ * PnpNetwork PN1010 QPSK Demodulator
+ *
+ * Copyright (C) 2005 Andrew de Quincey <adq_dvb@lidskialf.net>
+ * Copyright (C) 2005-8 Patrick Boettcher <pb@linuxtv.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ *
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
#ifndef S5H1420_H
#define S5H1420_H
@@ -31,19 +32,28 @@ struct s5h1420_config
u8 demod_address;
/* does the inversion require inversion? */
- u8 invert:1;
+ u8 invert : 1;
+
+ u8 repeated_start_workaround : 1;
+ u8 cdclk_polarity : 1; /* 1 == falling edge, 0 == raising edge */
};
#if defined(CONFIG_DVB_S5H1420) || (defined(CONFIG_DVB_S5H1420_MODULE) && defined(MODULE))
-extern struct dvb_frontend* s5h1420_attach(const struct s5h1420_config* config,
- struct i2c_adapter* i2c);
+extern struct dvb_frontend *s5h1420_attach(const struct s5h1420_config *config,
+ struct i2c_adapter *i2c);
+extern struct i2c_adapter *s5h1420_get_tuner_i2c_adapter(struct dvb_frontend *fe);
#else
-static inline struct dvb_frontend* s5h1420_attach(const struct s5h1420_config* config,
- struct i2c_adapter* i2c)
+static inline struct dvb_frontend *s5h1420_attach(const struct s5h1420_config *config,
+ struct i2c_adapter *i2c)
{
printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
return NULL;
}
+
+static inline struct i2c_adapter *s5h1420_get_tuner_i2c_adapter(struct dvb_frontend *fe)
+{
+ return NULL;
+}
#endif // CONFIG_DVB_S5H1420
#endif // S5H1420_H
diff --git a/linux/drivers/media/dvb/frontends/s5h1420_priv.h b/linux/drivers/media/dvb/frontends/s5h1420_priv.h
new file mode 100644
index 000000000..7962bbfb6
--- /dev/null
+++ b/linux/drivers/media/dvb/frontends/s5h1420_priv.h
@@ -0,0 +1,380 @@
+/*
+ * Driver for
+ * Samsung S5H1420 and
+ * PnpNetwork PN1010 QPSK Demodulator
+ *
+ * Copyright (C) 2005 Andrew de Quincey <adq_dvb@lidskialf.net>
+ * Copyright (C) 2005 Patrick Boettcher <pb@linuxtv.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the Free
+ * Software Foundation; either version 2 of the License, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the
+ *
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc., 675 Mass
+ * Ave, Cambridge, MA 02139, USA.
+ */
+#ifndef S5H1420_PRIV
+#define S5H1420_PRIV
+
+#include <asm/types.h>
+
+enum s5h1420_register {
+ ID01 = 0x00,
+ CON_0 = 0x01,
+ CON_1 = 0x02,
+ PLL01 = 0x03,
+ PLL02 = 0x04,
+ QPSK01 = 0x05,
+ QPSK02 = 0x06,
+ Pre01 = 0x07,
+ Post01 = 0x08,
+ Loop01 = 0x09,
+ Loop02 = 0x0a,
+ Loop03 = 0x0b,
+ Loop04 = 0x0c,
+ Loop05 = 0x0d,
+ Pnco01 = 0x0e,
+ Pnco02 = 0x0f,
+ Pnco03 = 0x10,
+ Tnco01 = 0x11,
+ Tnco02 = 0x12,
+ Tnco03 = 0x13,
+ Monitor01 = 0x14,
+ Monitor02 = 0x15,
+ Monitor03 = 0x16,
+ Monitor04 = 0x17,
+ Monitor05 = 0x18,
+ Monitor06 = 0x19,
+ Monitor07 = 0x1a,
+ Monitor12 = 0x1f,
+
+ FEC01 = 0x22,
+ Soft01 = 0x23,
+ Soft02 = 0x24,
+ Soft03 = 0x25,
+ Soft04 = 0x26,
+ Soft05 = 0x27,
+ Soft06 = 0x28,
+ Vit01 = 0x29,
+ Vit02 = 0x2a,
+ Vit03 = 0x2b,
+ Vit04 = 0x2c,
+ Vit05 = 0x2d,
+ Vit06 = 0x2e,
+ Vit07 = 0x2f,
+ Vit08 = 0x30,
+ Vit09 = 0x31,
+ Vit10 = 0x32,
+ Vit11 = 0x33,
+ Vit12 = 0x34,
+ Sync01 = 0x35,
+ Sync02 = 0x36,
+ Rs01 = 0x37,
+ Mpeg01 = 0x38,
+ Mpeg02 = 0x39,
+ DiS01 = 0x3a,
+ DiS02 = 0x3b,
+ DiS03 = 0x3c,
+ DiS04 = 0x3d,
+ DiS05 = 0x3e,
+ DiS06 = 0x3f,
+ DiS07 = 0x40,
+ DiS08 = 0x41,
+ DiS09 = 0x42,
+ DiS10 = 0x43,
+ DiS11 = 0x44,
+ Rf01 = 0x45,
+ Err01 = 0x46,
+ Err02 = 0x47,
+ Err03 = 0x48,
+ Err04 = 0x49,
+};
+
+#if 0
+
+regsiter mapping follows
+
+/* ID01 */
+#define PN1010_ID 7, 0
+
+/* CON_0 */
+#define QPSK_ONLY 4, 4
+#define SOFT_RST 3, 3 /* System soft reset mode (active high) [1] Enable [0] Disable */
+#define CLK_MODE 2, 2
+#define BPSK_QPSK 1, 1
+#define DSS_DVB 0, 0 /* DSS/DVB mode selection [1] DSS [0] DVB */
+
+/* CON_1 */
+#define ADC_SPD 6, 6
+#define PLL_OEN 5, 5
+#define SER_SEL 4, 4
+#define XTAL_OEN 3, 3
+#define Q_TEST 2, 2
+#define PWR_DN 1, 1 /* Power down mode [1] Power down enable, [0] Power down disable */
+#define I2C_RPT 0, 0 /* I2C repeater control [1] I2C repeater enable, [0] I2C repeater disable.
+ * Note: The master should be set this bit to "1" in order to interface with the tuner.
+ * When the master is not communicated with the tuner, this bit should be set to "0" */
+
+/* PLL programming information
+ * Fout = ((M+8)*Fin)/((P+2)*2^S), Fin = 4 MHz */
+/* PLL01 */
+#define M 7, 0
+
+/* PLL02 */
+#define P 5, 0
+#define S 7, 6
+
+/* QPSK01 */
+#define KICK_EN 7, 7 /* [1] PLL Kicker enable [0] Disable */
+#define ROLL_OFF 6, 6
+#define SCALE_EN 5, 5
+#define DC_EN 4, 4 /* DC offset remove [1] Enable [0] Disable */
+#define VMODE 3, 3
+#define TGL_MSB 2, 2
+#define MODE_QPSK 1, 1 /* QPSK operation mode [1] 1 sampling/1 symbol [0] 2 sampling/1 symbol */
+#define Q_SRESET_N 0, 0 /* QPSK start signal [1] Start [0] Idle */
+
+/* QPSK02 */
+#define DUMP_ACC 3, 3 /* Dump phase loop filter & timing loop filter accumulator [0 and then 1]
+ * The read operation enabled, when user set DUMP_ACC "0" and then "1". */
+#define DC_WIN 2, 0 /* Window position from MSB (0 <= DC_WIN <= 7) */
+
+/* AGC Controls */
+/* Pre01 */
+#define PRE_TH 4, 0 /* PRE-AGC threshold */
+#define INV_PULSE 7, 7 /* PWM signal is reversed [1] PWM signal active low [0] PWM signal active high */
+
+/* Post01 */
+#define RRC_SCALE 7, 6
+#define POST_TH 5, 0 /* POST-AGC threshold */
+
+/* Loop Controls */
+/* Loop01 */
+#define WT_TNCO 7, 7 /* Write TNCO center frequency [0 and then 1] The write operation enabled, when user set WT_TNCO "0" and then "1" */
+#define WT_PNCO 6, 6 /* Write PNCO center frequency [0 and then 1] The write operation enabled, when user set WT_PNCO "0" and then "1" */
+
+/* Loop02 */
+#define LOOP_OUT 7, 7 /* Loop filter monitoring selection [1] Loop filter accumulator + NCO [0] Loop filter accumulator */
+#define KICK_VAL 6, 4 /* The value that gets injected into the accumulator when a "kick" is needed. */
+#define KICK_MUL 3, 0 /* The number of bits KICK_VAL is up-shifted (2^N) before it is injected into the accumulator. */
+
+/* Loop03 */
+#define IGA_PLF 7, 4 /* Phase loop, integral gain (2^IGA_PLF) in the acquisition mode */
+#define PGA_PLF 3, 0 /* Phase loop, proportional gain (2^PGA_PLF) in the acquisition mode (default +8 added) */
+
+/* Loop04 */
+#define IGT_PLF 7, 4 /* Integral gain in the tracking mode */
+#define PGT_PLF 3, 0 /* Phase loop, proportional gain in the tracking mode (default +8 added) */
+
+/* Loop 05 */
+#define IG_TLF 7, 4 /* Timing loop, integral gain */
+#define PG_TLF 3, 0 /* Timing loop, proportional gain (default +8 added) */
+
+/* NCO controls
+ * LOOP_OUT [1] Read PLF accumulator + PNCO, LOOP_OUT [0] Read PLF accumulator */
+/* Pnco01 */
+#define PNCO0 7, 0
+/* Pnco02 */
+#define PNCO1 7, 0
+/* Pnco03 */
+#define PNCO2 7, 0
+
+/* LOOP_OUT [1], Read TLF accumulator + TNCO, LOOP_OUT [0], Read TLF accumulator */
+/* Tnco01 */
+#define TNCO0 7, 0
+/* Tnco02 */
+#define TNCO1 7, 0
+/* Tnco03 */
+#define TNCO2 7, 0
+
+/* Monitor01 */
+#define A_SCL 3, 3
+#define TLOCK 1, 1 /* Timing loop lock (Symbol sync) [1] Timing loop has locked [0] Timing loop has not locked */
+#define PLOCK 0, 0 /* Phase loop lock (Carrier sync) [1] Phase loop has locked [0] Phase loop has not locked */
+
+/* Monitor02 */
+#define PRE_LEVEL 7, 0 /* PRE-AGC gain level */
+
+/* Monitor03 */
+#define POST_LEVEL 7, 0 /* POST-AGC gain level */
+
+/* Monitor04 */
+#define DC_I_LEVEL 7, 0 /* DC offset of I samples */
+
+/* Monitor05 */
+#define DC_Q_LEVEL 7, 0 /* DC offset of Q samples */
+
+/* Monitor06 */
+#define PLOCK_CNT 7, 0
+
+/* Monitor07 */
+#define TLOCK_CNT 7, 0
+
+/* Monitor12 */
+#define QPSK_OUT 6, 1 /* QPSK output monitoring */
+#define DC_FREEZE 0, 0 /* [1] Do not update DC_OFFSET */
+
+/* FEC Block */
+/* FEC01 */
+#define DERAND_BPAS 6, 6
+#define RS_BPAS 5, 5
+#define FEC_SRST_CNTL 4, 4
+#define FEC_SRESET 3, 3
+#define MPEG_CLK_INTL 2, 0
+ /* Tmp=(FMClk/FSR) x (1 / (2xCR)); FMClk: System Clock Frequency, FSR: Symbol Rate, CR: Code Rate
+ * 0: 1 < Tmp <= 2, 4: 13 < Tmp <= 17,
+ * 1: 2 < Tmp <= 5, 5: 17 < Tmp <= 25,
+ * 2: 5 < Tmp <= 9, 6: 25 < Tmp <= 33,
+ * 3: 9 < Tmp <= 13, 7: 33 < Tmp */
+
+/* Soft01 */
+#define ST_VAL_R12 2, 0
+#define STEP_R12 5, 3
+#define STEP_R23 5, 3
+#define STEP_R34 5, 3
+#define STEP_R56 5, 3
+#define STEP_R67 5, 3
+#define STEP_R78 5, 3
+/* Soft02 */
+#define ST_VAL_R23 7, 0
+/* Soft03 */
+#define ST_VAL_R34 7, 0
+/* Soft04 */
+#define ST_VAL_R56 7, 0
+/* Soft05 */
+#define ST_VAL_R67 7, 0
+/* Soft06 */
+#define ST_VAL_R78 7, 0
+
+/* Vit01 */
+#define RENORM_R12 7, 0
+/* Vit02 */
+#define RENORM_R23 7, 0
+/* Vit03 */
+#define RENORM_R34 7, 0
+/* Vit04 */
+#define RENORM_R56 7, 0
+/* Vit05 */
+#define RENORM_R67 7, 0
+/* Vit06 */
+#define RENORM_R78 7, 0
+/* Vit07 */
+#define RENORM_PRD 7, 0
+
+/* Vit08 */
+#define VIT_IN_SR78 7, 7
+#define VIT_IN_SR34 6, 6
+#define VIT_SR78 5, 5
+#define VIT_SR67 4, 4
+#define VIT_SR56 3, 3
+#define VIT_SR34 2, 2
+#define VIT_SR23 1, 1 /* .... */
+#define VIT_SR12 0, 0 /* Include CR 1/2 in search */
+
+/* Vit09 */
+#define PARM_FIX 4, 4 /* Parameter fix mode: [1] Known parameter [0] Unknown parameter */
+#define VIT_INV_SPECPARM_FIX 3, 3 /* Initial spectrum information */
+#define VIT_FR 2, 0 /* Start synchronization search at code rate as follows */
+ #define VIT_CR_12 0x00
+ #define VIT_CR_23 0x01
+ #define VIT_CR_34 0x02
+ #define VIT_CR_56 0x03
+ #define VIT_CR_67 0x04
+ #define VIT_CR_78 0x05
+
+/* Vit10 */
+#define INV_SPEC_STS 3, 3 /* Spectrum information monitoring [1] Inv spectrum [0] Not inv spectrum */
+#define VIT_CR 2, 0 /* Viterbi decoder current code rate [0] R=1/2 [1] R=2/3 [2] R=3/4 [3] R=5/6 [4] R=6/7 [5] R=7/8 */
+
+/* Vit11 */
+#define VIT_CER 7, 0
+
+/* Vit12 */
+#define RENORM_RAT 7, 0
+
+/* Sync01 */
+#define SYNC_MISS_TH 7, 4 /* Sync byte detector?s miss threshold */
+#define SYNC_HIT_TH 3, 0 /* Sync byte detector?s hit threshold This value should be greater than 2 */
+
+/* Sync02 */
+#define BYTE_SYNC 5, 5 /* [1] Acquire byte sync [0] Not acquire byte sync */
+#define SYNC_BYTE_STS 4, 2
+#define VIT_SRCH_STS 1, 1
+#define VIT_SYNC 0, 0 /* [1] Viterbi decoder is in sync [0] Viterbi decoder is out of sync */
+
+/* Rs01 */
+#define RS_ERR 3, 0
+#define PKT_ERR 4, 4
+
+/* Mpeg01 */
+#define ERR_POL 3, 3 /* Packet error polarity [1] Active low [0] Active high */
+#define SYNC_POL 2, 2 /* Sync polarity [1] Active low [0] Active high */
+#define VALID_POL 1, 1 /* Data valid polarity [1] Active low [0] Active high */
+#define CDCLK_POL 0, 0 /* CDCLK polarity [1] Falling edge event [0] Rising edge event */
+
+/* Mpeg02 */
+#define MPEG_OEN 6, 6
+#define DOUT_CONT 5, 5
+#define ERR_CONT 4, 4
+#define CLK_CONT 3, 3 /* Clock continuous mode [1] Continuous clock, [0] Clock is enable during payload data transfer */
+#define ENVELOPE 2, 2
+#define SER_PAR 1, 1 /* Serial / Parallel mode [1] Serial mode, [0] Parallel mode */
+#define DSS_SYNC 0, 0 /* DSS sync mode [1] Output sync, [0] No output sync */
+
+/* DiS01 */
+#define TONE_FREQ 7, 0 /* Tone frequency ratio ftone = fclk / (TONE_FREQ x 32) */
+
+/* DiS02 */
+#define RCV_EN 7, 7 /* DiSEqC receive enable mode [1] Receive enable [0] Receive disable */
+#define DIS_LENGTH 6, 4 /* Message length */
+#define DIS_RDY 3, 3 /* Data Transfer ready / finish [1] Ready [0] Finish */
+#define SWITCH_CON 2, 2 /* Satellite switch in tone burst mode [1] Satellite B [0] Satellite A */
+#define LNB_CON 1, 0 /* LNB control mode, [0] Continuous mode, [1] Tone burst mode, [2] DiSEqC mode, [3] Reserved */
+
+/* DiS03 */
+#define OLF_N 2, 2 /* [1] Disable [0] OLF (active low) */
+#define LNB_DN 1, 1 /* [1] LNB down [0] Disable (active high) */
+#define V18_13V 0, 0 /* 13V/18V select register (0=13V, 1=18V) */
+
+/* DiS04 .. DiS11*/
+#define LNB_MESGE0 7, 0
+#define LNB_MESGE1 7, 0
+#define LNB_MESGE2 7, 0
+#define LNB_MESGE3 7, 0
+#define LNB_MESGE4 7, 0
+#define LNB_MESGE5 7, 0
+#define LNB_MESGE6 7, 0
+#define LNB_MESGE7 7, 0
+
+/* Rf01 */
+#define SLAVE_ADDR 6, 0 /* RF tuner slave Address (SOC VERSION) */
+
+/* Err01 */
+#define ALARM_MODE 4, 4
+#define ERR_CNT_PRD 3, 2
+#define ERR_SRC 1, 0 /* Error monitoring source */
+ #define QPSK_BIT_ERRORS 0x0
+ #define VITERBI_BIT_ERRORS 0x1
+ #define VITERBI_BYTE_ERRORS 0x2
+ #define PACKET_ERRORS 0x3
+
+/* Err02 */
+#define ERR_CNT_L 7, 0 /* Error counter value register (LSB 8 bits) */
+
+/* Err03 */
+#define ERR_CNT_H 7, 0 /* Error counter value register (MSB 8 bits) */
+
+/* Err04 */
+#define PARITY_ERR 7, 0 /* Error flag for DiSEqC receive data */
+
+#endif
+
+#endif
diff --git a/linux/drivers/media/dvb/ttpci/budget.c b/linux/drivers/media/dvb/ttpci/budget.c
index 829576dc2..e36c32528 100644
--- a/linux/drivers/media/dvb/ttpci/budget.c
+++ b/linux/drivers/media/dvb/ttpci/budget.c
@@ -358,6 +358,7 @@ static int s5h1420_tuner_set_params(struct dvb_frontend* fe, struct dvb_frontend
static struct s5h1420_config s5h1420_config = {
.demod_address = 0x53,
.invert = 1,
+ .cdclk_polarity = 1,
};
static struct tda10086_config tda10086_config = {
generated by cgit v1.2.3 (git 2.25.1) at 2025-01-23 17:30:26 +0000