1 files changed, 440 insertions, 0 deletions

diff --git a/linux/drivers/media/common/saa7146_vbi.c b/linux/drivers/media/common/saa7146_vbi.c
new file mode 100644
index 000000000..4a8528295
--- /dev/null
+++ b/linux/drivers/media/common/saa7146_vbi.c
@@ -0,0 +1,440 @@
+#include "saa7146.h"
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,51)
+	#define KBUILD_MODNAME "saa7146"
+#endif
+
+static int vbi_pixel_to_capture = 720 * 2;
+
+int vbi_workaround(struct saa7146_dev *dev)
+{
+        u32          *cpu;
+        dma_addr_t   dma_addr;
+	
+	int i, index;
+
+	DECLARE_WAITQUEUE(wait, current);
+	
+	DEB_VBI(("dev:%p",dev));
+	
+	/* once again, a bug in the saa7146: the brs acquisition
+	   is buggy and especially the BXO-counter does not work
+	   as specified. there is this workaround, but please
+	   don't let me explain it. ;-) */
+
+	if(0 != dev->ext->vbi) {
+		dev->ext->vbi(dev);
+	}
+
+	cpu = pci_alloc_consistent(dev->pci, 4096, &dma_addr);
+	if (NULL == cpu)
+		return -ENOMEM;
+
+	/* setup some basic programming, just for the workaround */
+	saa7146_write(dev, BASE_EVEN3,	dma_addr);
+	saa7146_write(dev, BASE_ODD3,	dma_addr+vbi_pixel_to_capture);
+	saa7146_write(dev, PROT_ADDR3,	dma_addr+4096);
+	saa7146_write(dev, PITCH3, 	vbi_pixel_to_capture);
+	saa7146_write(dev, BASE_PAGE3,	0x0);
+	saa7146_write(dev, NUM_LINE_BYTE3, (2<<16)|((vbi_pixel_to_capture)<<0));
+	saa7146_write(dev, MC2, MASK_04|MASK_20);
+
+
+	/* we have to do the workaround two times to be sure that
+	   everything is ok */
+	for(i = 0; i < 2; i++) {
+
+		/* indicate to the irq handler that we do the workaround */
+		saa7146_write(dev, MC2, MASK_31|MASK_15);
+
+		saa7146_write(dev, NUM_LINE_BYTE3, (1<<16)|(2<<0));
+		saa7146_write(dev, MC2, MASK_04|MASK_20);
+	
+		index = 0;
+
+		/* load brs-control register */
+		dev->rps1[index++] = CMD_WR_REG | (1 << 8) | (BRS_CTRL/4);
+		/* BXO = 1h, BRS to outbound */
+		dev->rps1[index++]=0xc000008c;   
+		/* wait for vbi_a */
+		dev->rps1[index++] = CMD_PAUSE | MASK_10;
+		/* upload brs */
+		dev->rps1[index++] = CMD_UPLOAD | MASK_08;
+		/* load brs-control register */
+		dev->rps1[index++] = CMD_WR_REG | (1 << 8) | (BRS_CTRL/4);
+		/* BYO = 1, BXO = NQBIL (=1728 for PAL, for NTSC this is 858*2) - NumByte3 (=1440) = 288 */
+		dev->rps1[index++] = ((1728-(vbi_pixel_to_capture)) << 7) | MASK_19;
+		/* wait for brs_done */
+		dev->rps1[index++] = CMD_PAUSE | MASK_08;
+		/* upload brs */
+		dev->rps1[index++] = CMD_UPLOAD | MASK_08;
+		/* load video-dma3 NumLines3 and NumBytes3 */
+		dev->rps1[index++] = CMD_WR_REG | (1 << 8) | (NUM_LINE_BYTE3/4);
+		/* dev->vbi_count*2 lines, 720 pixel (= 1440 Bytes) */
+		dev->rps1[index++]= (2 << 16) | (vbi_pixel_to_capture);
+		/* load brs-control register */
+		dev->rps1[index++] = CMD_WR_REG | (1 << 8) | (BRS_CTRL/4);
+		/* Set BRS right: note: this is an experimental value for BXO (=> PAL!) */
+		dev->rps1[index++] = (540 << 7) | (5 << 19);  // 5 == vbi_start  
+		/* wait for brs_done */
+		dev->rps1[index++] = CMD_PAUSE | MASK_08;
+		/* upload brs and video-dma3*/
+		dev->rps1[index++] = CMD_UPLOAD | MASK_08 | MASK_04;
+		/* load mc2 register: enable dma3 */
+		dev->rps1[index++] = CMD_WR_REG | (1 << 8) | (MC1/4);
+		dev->rps1[index++] = MASK_20 | MASK_04;
+		/* generate interrupt */
+		dev->rps1[index++] = CMD_INTERRUPT;
+		/* stop rps1 */
+		dev->rps1[index++] = CMD_STOP;
+	
+		/* enable rps1 irqs */
+		IER_ENABLE(dev,MASK_28);
+
+		/* prepare to wait to be woken up by the irq-handler */
+		add_wait_queue(&dev->vbi_wq, &wait);
+		current->state = TASK_INTERRUPTIBLE;
+
+		/* start rps1 to enable workaround */
+		saa7146_write(dev, RPS_ADDR1, virt_to_bus(&dev->rps1[ 0]));
+		saa7146_write(dev, MC1, (MASK_13 | MASK_29));	
+		
+		schedule();
+
+		DEB_VBI(("brs bug workaround %d/1.\n",i));
+	
+		remove_wait_queue(&dev->vbi_wq, &wait);
+		current->state = TASK_RUNNING;
+
+		/* disable rps1 irqs */
+		IER_DISABLE(dev,MASK_28);
+
+		/* stop video-dma3 */
+		saa7146_write(dev, MC1, MASK_20);
+
+		if(signal_pending(current)) {
+		
+			DEB_VBI(("aborted.\n"));
+
+			/* stop rps1 for sure */
+			saa7146_write(dev, MC1, MASK_29);
+
+			pci_free_consistent(dev->pci, 4096, cpu, dma_addr);
+			return -EINTR;
+		}
+	}
+
+	pci_free_consistent(dev->pci, 4096, cpu, dma_addr);
+	return 0;
+}
+
+void saa7146_set_vbi_capture(struct saa7146_dev *dev, struct saa7146_buf *buf, struct saa7146_buf *next)
+{
+	struct saa7146_video_dma vdma3;
+
+	int count = 0;
+	unsigned long e_wait = dev->current_hps_sync == SAA7146_HPS_SYNC_PORT_A ? CMD_E_FID_A : CMD_E_FID_B;
+	unsigned long o_wait = dev->current_hps_sync == SAA7146_HPS_SYNC_PORT_A ? CMD_O_FID_A : CMD_O_FID_B;
+
+/*
+	vdma3.base_even	= (u32)dev->ov_fb.base+2048*70;
+	vdma3.base_odd	= (u32)dev->ov_fb.base;
+	vdma3.prot_addr	= (u32)dev->ov_fb.base+2048*164;
+	vdma3.pitch	= 2048;
+	vdma3.base_page	= 0;
+	vdma3.num_line_byte = (64<<16)|((vbi_pixel_to_capture)<<0); // set above!
+*/
+	vdma3.base_even	= buf->pt[2].offset;
+	vdma3.base_odd	= buf->pt[2].offset + 16 * vbi_pixel_to_capture;
+	vdma3.prot_addr	= buf->pt[2].offset + 16 * 2 * vbi_pixel_to_capture;
+	vdma3.pitch	= vbi_pixel_to_capture;
+	vdma3.base_page	= buf->pt[2].dma | ME1;
+	vdma3.num_line_byte = (16 << 16) | vbi_pixel_to_capture;
+	saa7146_write_out_dma(dev, 3, &vdma3);
+
+	/* write beginning of rps-program */
+	count = 0;
+
+	/* wait for o_fid_a/b / e_fid_a/b toggle only if bit 1 is not set */
+
+	/* we don't wait here for the first field anymore. this is different from the video
+	   capture and might cause that the first buffer is only half filled (with only
+	   one field). but since this is some sort of streaming data, this is not that negative.
+	   but by doing this, we can use the whole engine from video-buf.c... */
+	
+/*
+	dev->rps1[ count++ ] = CMD_PAUSE | CMD_OAN | CMD_SIG1 | e_wait;
+	dev->rps1[ count++ ] = CMD_PAUSE | CMD_OAN | CMD_SIG1 | o_wait;
+*/
+	/* set bit 1 */
+	dev->rps1[ count++ ] = CMD_WR_REG | (1 << 8) | (MC2/4); 	
+	dev->rps1[ count++ ] = MASK_28 | MASK_12;
+	
+	/* turn on video-dma3 */
+	dev->rps1[ count++ ] = CMD_WR_REG_MASK | (MC1/4);		
+	dev->rps1[ count++ ] = MASK_04 | MASK_20;	    		/* => mask */
+	dev->rps1[ count++ ] = MASK_04 | MASK_20;			/* => values */
+	
+	/* wait for o_fid_a/b / e_fid_a/b toggle */
+	dev->rps1[ count++ ] = CMD_PAUSE | o_wait;
+	dev->rps1[ count++ ] = CMD_PAUSE | e_wait;
+
+	/* generate interrupt */
+	dev->rps1[ count++ ] = CMD_INTERRUPT;					
+
+	/* stop */
+	dev->rps1[ count++ ] = CMD_STOP;					
+
+	/* enable rps1 irqs */
+	IER_ENABLE(dev, MASK_28);
+
+	/* write the address of the rps-program */
+	saa7146_write(dev, RPS_ADDR1, virt_to_bus(&dev->rps1[ 0]));
+
+	/* turn on rps */
+	saa7146_write(dev, MC1, (MASK_13 | MASK_29));	
+}
+
+static int buffer_activate(struct saa7146_dev *dev,
+			   struct saa7146_buf *buf,
+			   struct saa7146_buf *next)
+{
+	buf->vb.state = STATE_ACTIVE;
+
+	DEB_VBI(("dev:%p, buf:%p, next:%p\n",dev,buf,next));
+	saa7146_set_vbi_capture(dev,buf,next);
+
+	mod_timer(&dev->vbi_q.timeout, jiffies+BUFFER_TIMEOUT);
+	return 0;
+}
+
+static int buffer_prepare(struct file *file, struct videobuf_buffer *vb)
+{
+	struct saa7146_fh *fh = file->private_data;
+	struct saa7146_dev *dev = fh->dev;
+	struct saa7146_buf *buf = (struct saa7146_buf *)vb;
+
+	int err = 0;
+	int lines, llength, size;
+
+	lines   = 16 * 2 ; /* 2 fields */
+	llength = vbi_pixel_to_capture;
+	size = lines * llength;
+
+	DEB_VBI(("vb:%p\n",vb));
+	
+	if (0 != buf->vb.baddr  &&  buf->vb.bsize < size) {
+		DEB_VBI(("size mismatch.\n"));
+		return -EINVAL;
+	}
+	
+	if (buf->vb.size != size)
+		saa7146_dma_free(dev,buf);
+
+	if (STATE_NEEDS_INIT == buf->vb.state) {
+		buf->vb.width  = llength;
+		buf->vb.height = lines;
+		buf->vb.size   = size;
+
+		saa7146_pgtable_free(dev->pci, &buf->pt[2]);
+		saa7146_pgtable_alloc(dev->pci, &buf->pt[2]);
+
+		err = videobuf_iolock(dev->pci,&buf->vb);
+		if (err)
+			goto oops;
+		saa7146_pgtable_build_single(dev->pci, &buf->pt[2], buf->vb.dma.sglist, buf->vb.dma.sglen);
+	}
+	buf->vb.state = STATE_PREPARED;
+	buf->activate = buffer_activate;
+
+	return 0;
+
+ oops:
+	DEB_VBI(("error out.\n"));
+	saa7146_dma_free(dev,buf);
+
+	return err;
+}
+static int
+buffer_setup(struct file *file, int *count, int *size)
+{
+	struct saa7146_fh *fh = file->private_data;
+	struct saa7146_dev *dev = fh->dev;
+
+	int llength,lines;
+	
+	lines   = 16 * 2 ; /* 2 fields */
+	llength = vbi_pixel_to_capture;
+
+	*size = lines * llength;
+	*count = 2;
+
+	DEB_VBI(("count:%d, size:%d\n",*count,*size));
+
+	return 0;
+}
+
+static void buffer_queue(struct file *file, struct videobuf_buffer *vb)
+{
+	struct saa7146_fh *fh = file->private_data;
+	struct saa7146_dev *dev = fh->dev;
+	struct saa7146_buf *buf = (struct saa7146_buf *)vb;
+	
+	DEB_VBI(("vb:%p\n",vb));
+	saa7146_buffer_queue(dev,&dev->vbi_q,buf);
+}
+
+static void buffer_release(struct file *file, struct videobuf_buffer *vb)
+{
+	struct saa7146_fh *fh   = file->private_data;
+	struct saa7146_dev *dev = fh->dev;
+	struct saa7146_buf *buf = (struct saa7146_buf *)vb;
+	
+	DEB_VBI(("vb:%p\n",vb));
+	saa7146_dma_free(dev,buf);
+}
+
+struct videobuf_queue_ops vbi_qops = {
+	.buf_setup    = buffer_setup,
+	.buf_prepare  = buffer_prepare,
+	.buf_queue    = buffer_queue,
+	.buf_release  = buffer_release,
+};
+
+/* ------------------------------------------------------------------ */
+
+void vbi_stop(struct saa7146_fh *fh)
+{
+	struct saa7146_dev *dev = fh->dev;
+	unsigned long flags;
+	DEB_VBI(("dev:%p, fh:%p\n",dev, fh));
+	
+	spin_lock_irqsave(&dev->slock,flags);
+
+	/* disable rps1  */
+	saa7146_write(dev, MC1, MASK_29);
+
+	/* disable rps1 irqs */
+	IER_DISABLE(dev, MASK_28);
+
+	/* shut down dma 3 transfers */
+	saa7146_write(dev, MC1, MASK_20);
+
+	dev->vbi_streaming = NULL;
+	spin_unlock_irqrestore(&dev->slock, flags);
+}
+
+void vbi_read_timeout(unsigned long data)
+{
+	struct saa7146_fh *fh = (struct saa7146_fh *)data;
+	struct saa7146_dev *dev = fh->dev;
+	
+	DEB_VBI(("dev:%p, fh:%p\n",dev, fh));
+
+	vbi_stop(fh);
+}
+
+void vbi_init(struct saa7146_dev *dev)
+{
+	INIT_LIST_HEAD(&dev->vbi_q.queue);
+
+	init_timer(&dev->vbi_q.timeout);
+	dev->vbi_q.timeout.function = saa7146_buffer_timeout;
+	dev->vbi_q.timeout.data     = (unsigned long)(&dev->vbi_q);
+	dev->vbi_q.dev              = dev;
+
+	init_waitqueue_head(&dev->vbi_wq);
+}
+
+void vbi_open(struct saa7146_dev *dev, struct saa7146_fh *fh)
+{
+	memset(&fh->vbi_fmt,0,sizeof(fh->vbi_fmt));
+
+	fh->vbi_fmt.sampling_rate	= 27000000;
+	fh->vbi_fmt.offset		= 248; /* todo */ 
+	fh->vbi_fmt.samples_per_line	= vbi_pixel_to_capture;
+	fh->vbi_fmt.sample_format	= V4L2_PIX_FMT_GREY;
+
+	/* fixme: this only works for PAL */
+	fh->vbi_fmt.start[0] = 5;
+	fh->vbi_fmt.count[0] = 16;
+	fh->vbi_fmt.start[1] = 312;
+	fh->vbi_fmt.count[1] = 16;
+
+	videobuf_queue_init(&fh->vbi_q, &vbi_qops,
+			    dev->pci, &dev->slock,
+			    V4L2_BUF_TYPE_VBI_CAPTURE,
+			    sizeof(struct saa7146_buf));
+	init_MUTEX(&fh->vbi_q.lock);
+
+	init_timer(&fh->vbi_read_timeout);
+	fh->vbi_read_timeout.function = vbi_read_timeout;
+	fh->vbi_read_timeout.data = (unsigned long)fh;
+
+	vbi_workaround(dev);
+}
+
+void vbi_close(struct saa7146_dev *dev, struct saa7146_fh *fh, struct file *file)
+{
+	if( fh == dev->vbi_streaming ) {
+		vbi_stop(fh);
+	}
+}
+
+void vbi_irq_done(struct saa7146_dev *dev, unsigned long status)
+{
+	spin_lock(&dev->slock);
+
+	if (dev->vbi_q.curr) {
+		DEB_VBI(("dev:%p, curr:%p\n",dev,dev->vbi_q.curr));
+		/* this must be += 2, one count for each field */
+		dev->vbi_fieldcount+=2;
+		dev->vbi_q.curr->vb.field_count = dev->vbi_fieldcount;
+		saa7146_buffer_finish(dev,&dev->vbi_q,STATE_DONE);
+	} else {
+		DEB_VBI(("dev:%p\n",dev));
+	}
+	saa7146_buffer_next(dev,&dev->vbi_q,1);
+
+	spin_unlock(&dev->slock);
+}
+
+static ssize_t vbi_read(struct file *file, char *data, size_t count, loff_t *ppos)
+{
+	struct saa7146_fh *fh = file->private_data;
+	struct saa7146_dev *dev = fh->dev;
+	ssize_t ret = 0;
+
+	DEB_VBI(("dev:%p, fh:%p\n",dev,fh));
+	
+	if( NULL == dev->vbi_streaming ) {
+		// fixme: check if dma3 is available
+		// fixme: activate vbi engine here if necessary. (really?)
+		dev->vbi_streaming = fh;
+	}
+
+	if( fh != dev->vbi_streaming ) {
+		DEB_VBI(("open %p is already using vbi capture.",dev->vbi_streaming));
+		return -EBUSY;
+	}
+
+	mod_timer(&fh->vbi_read_timeout, jiffies+BUFFER_TIMEOUT);
+	ret = videobuf_read_stream(file, &fh->vbi_q, data, count, ppos, 1);
+/*
+	printk("BASE_ODD3:      0x%08x\n", saa7146_read(dev, BASE_ODD3));
+	printk("BASE_EVEN3:     0x%08x\n", saa7146_read(dev, BASE_EVEN3));
+	printk("PROT_ADDR3:     0x%08x\n", saa7146_read(dev, PROT_ADDR3));
+	printk("PITCH3:         0x%08x\n", saa7146_read(dev, PITCH3));
+	printk("BASE_PAGE3:     0x%08x\n", saa7146_read(dev, BASE_PAGE3));
+	printk("NUM_LINE_BYTE3: 0x%08x\n", saa7146_read(dev, NUM_LINE_BYTE3));
+	printk("BRS_CTRL:       0x%08x\n", saa7146_read(dev, BRS_CTRL));
+*/
+	return ret;
+}
+
+struct saa7146_use_ops saa7146_vbi_uops = {
+	.init 		= vbi_init,
+	.open 		= vbi_open,
+	.release 	= vbi_close,
+	.irq_done 	= vbi_irq_done,
+	.read 		= vbi_read,
+};