diff options
Diffstat (limited to 'linux/drivers/media/dvb/b2c2/flexcop-reg.h')
| -rw-r--r-- | linux/drivers/media/dvb/b2c2/flexcop-reg.h | 102 |
1 files changed, 51 insertions, 51 deletions
diff --git a/linux/drivers/media/dvb/b2c2/flexcop-reg.h b/linux/drivers/media/dvb/b2c2/flexcop-reg.h index 0a7637792..41835c528 100644 --- a/linux/drivers/media/dvb/b2c2/flexcop-reg.h +++ b/linux/drivers/media/dvb/b2c2/flexcop-reg.h @@ -2,7 +2,7 @@ * This file is part of linux driver the digital TV devices equipped with B2C2 FlexcopII(b)/III * * flexcop-reg.h - register abstraction for FlexCopII, FlexCopIIb and FlexCopIII - * + * * see flexcop.c for copyright information. */ #ifndef __FLEXCOP_REG_H__ @@ -39,7 +39,7 @@ extern const char *flexcop_device_names[]; /* flexcop_ibi_reg - a huge union representing the register structure */ typedef union { u32 raw; - + /* DMA 0x000 to 0x01c * DMA1 0x000 to 0x00c * DMA2 0x010 to 0x01c @@ -52,8 +52,8 @@ typedef union { struct { u32 DMA_maxpackets : 8; /* (remapped) PCI DMA1 Packet Count Interrupt. This variable - is able to be read and written while bit(1) of register - 0x00c (remap_enable) is set. This variable represents + is able to be read and written while bit(1) of register + 0x00c (remap_enable) is set. This variable represents the number of packets that will be transmitted to the PCI host using PCI DMA1 before an interrupt to the PCI is asserted. This functionality may be enabled using bit(20) @@ -74,7 +74,7 @@ typedef union { } dma_0x4_write; struct { - u32 unused : 2; + u32 unused : 2; u32 dma_cur_addr :30; /* current physical host memory address pointer for DMA */ } dma_0x8; @@ -83,7 +83,7 @@ typedef union { u32 remap_enable : 1; /* remap enable for 0x0x4(7:0) */ u32 dma_address1 :30; /* Physical/virtual address 1 on DMA */ } dma_0xc; - + /* Two-wire Serial Master and Clock 0x100-0x110 */ struct { // u32 slave_transmitter : 1; /* ???*/ @@ -91,15 +91,15 @@ typedef union { u32 reserved1 : 1; u32 baseaddr : 8; /* address of the location of the read/write operation */ u32 data1_reg : 8; /* first byte in two-line serial read/write operation */ - u32 working_start : 1; /* when doing a write operation this indicator is 0 when ready + u32 working_start : 1; /* when doing a write operation this indicator is 0 when ready * set to 1 when doing a write operation */ u32 twoWS_rw : 1; /* read/write indicator (1 = read, 0 write) */ u32 total_bytes : 2; /* number of data bytes in each two-line serial transaction (0 = 1 byte, 11 = 4byte)*/ u32 twoWS_port_reg : 2; /* port selection: 01 - Front End/Demod, 10 - EEPROM, 11 - Tuner */ - u32 no_base_addr_ack_error : 1; /* writing: write-req: frame is produced w/o baseaddr, read-req: read-cycles w/o - * preceding address assignment write frame + u32 no_base_addr_ack_error : 1; /* writing: write-req: frame is produced w/o baseaddr, read-req: read-cycles w/o + * preceding address assignment write frame * ACK_ERROR = 1 when no ACK from slave in the last transaction */ - u32 st_done : 1; /* indicator for transaction is done */ + u32 st_done : 1; /* indicator for transaction is done */ } tw_sm_c_100; struct { @@ -111,11 +111,11 @@ typedef union { u32 unused : 6; } tw_sm_c_104; -/* Clock. The register allows the FCIII to convert an incoming Master clock +/* Clock. The register allows the FCIII to convert an incoming Master clock * (MCLK) signal into a lower frequency clock through the use of a LowCounter * (TLO) and a High- Counter (THI). The time counts for THI and TLO are * measured in MCLK; each count represents 4 MCLK input clock cycles. - * + * * The default output for port #1 is set for Front End Demod communication. (0x108) * The default output for port #2 is set for EEPROM communication. (0x10c) * The default output for port #3 is set for Tuner communication. (0x110) @@ -126,21 +126,21 @@ typedef union { u32 tlo1 : 5; /* Tlo for port #1 (def: 11100b; 28) */ u32 reserved2 :19; } tw_sm_c_108; - + struct { u32 thi1 : 6; /* Thi for port #2 (def: 111001b; 57) */ u32 reserved1 : 2; u32 tlo1 : 5; /* Tlo for port #2 (def: 11100b; 28) */ u32 reserved2 :19; } tw_sm_c_10c; - + struct { u32 thi1 : 6; /* Thi for port #3 (def: 111001b; 57) */ u32 reserved1 : 2; u32 tlo1 : 5; /* Tlo for port #3 (def: 11100b; 28) */ u32 reserved2 :19; } tw_sm_c_110; - + /* LNB Switch Frequency 0x200 * Clock that creates the LNB switch tone. The default is set to have a fixed * low output (not oscillating) to the LNB_CTL line. @@ -161,7 +161,7 @@ typedef union { u32 ACPI3_sig : 1; /* turn of power of the complete satelite receiver board (except FCIII) */ u32 LNB_L_H_sig : 1; /* low or high voltage for LNB. (0 = low, 1 = high) */ u32 Per_reset_sig : 1; /* misc. init reset (default: 1), to reset set to low and back to high */ - u32 reserved :20; + u32 reserved :20; u32 Rev_N_sig_revision_hi : 4;/* 0xc in case of FCIII */ u32 Rev_N_sig_reserved1 : 2; u32 Rev_N_sig_caps : 1; /* if 1, FCIII has 32 PID- and MAC-filters and is capable of IP multicast */ @@ -175,17 +175,17 @@ typedef union { u32 Stream2_filter_sig : 1; /* Stream2 PID filtering */ u32 PCR_filter_sig : 1; /* PCR PID filter */ u32 PMT_filter_sig : 1; /* PMT PID filter */ - + u32 EMM_filter_sig : 1; /* EMM PID filter */ u32 ECM_filter_sig : 1; /* ECM PID filter */ u32 Null_filter_sig : 1; /* Filters null packets, PID=0x1fff. */ u32 Mask_filter_sig : 1; /* mask PID filter */ - + u32 WAN_Enable_sig : 1; /* WAN output line through V8 memory space is activated. */ u32 WAN_CA_Enable_sig : 1; /* not in FCIII */ u32 CA_Enable_sig : 1; /* not in FCIII */ u32 SMC_Enable_sig : 1; /* CI stream data (CAI) goes directly to the smart card intf (opposed IBI 0x600 or SC-cmd buf). */ - + u32 Per_CA_Enable_sig : 1; /* not in FCIII */ u32 Multi2_Enable_sig : 1; /* ? */ u32 MAC_filter_Mode_sig : 1; /* (MAC_filter_enable) Globally enables MAC filters for Net PID filteres. */ @@ -193,24 +193,24 @@ typedef union { examine and process packets according to all other (individual) PID filtering controls. If it a zero, no packet processing of any kind will take place. All data from the tuner will be thrown away. */ - - u32 DMA1_IRQ_Enable_sig : 1; /* When set, a DWORD counter is enabled on PCI DMA1 that asserts the PCI + + u32 DMA1_IRQ_Enable_sig : 1; /* When set, a DWORD counter is enabled on PCI DMA1 that asserts the PCI * interrupt after the specified count for filling the buffer. */ - u32 DMA1_Timer_Enable_sig : 1; /* When set, a timer is enabled on PCI DMA1 that asserts the PCI interrupt + u32 DMA1_Timer_Enable_sig : 1; /* When set, a timer is enabled on PCI DMA1 that asserts the PCI interrupt after a specified amount of time. */ u32 DMA2_IRQ_Enable_sig : 1; /* same as DMA1_IRQ_Enable_sig but for DMA2 */ u32 DMA2_Timer_Enable_sig : 1; /* same as DMA1_Timer_Enable_sig but for DMA2 */ - + u32 DMA1_Size_IRQ_Enable_sig : 1; /* When set, a packet count detector is enabled on PCI DMA1 that asserts the PCI interrupt. */ u32 DMA2_Size_IRQ_Enable_sig : 1; /* When set, a packet count detector is enabled on PCI DMA2 that asserts the PCI interrupt. */ u32 Mailbox_from_V8_Enable_sig: 1; /* When set, writes to the mailbox register produce an interrupt to the PCI host to indicate that mailbox data is available. */ - u32 unused : 9; + u32 unused : 9; } ctrl_208; /* General status. When a PCI interrupt occurs, this register is read to - * discover the reason for the interrupt. + * discover the reason for the interrupt. */ struct { u32 DMA1_IRQ_Status : 1; /* When set(1) the DMA1 counter had generated an IRQ. Read Only. */ @@ -230,9 +230,9 @@ typedef union { /* Software reset register */ struct { - u32 reset_blocks : 8; /* Enabled when Block_reset_enable = 0xB2 and 0x208 bits 15:8 = 0x00. - Each bit location represents a 0x100 block of registers. Writing - a one in a bit location resets that block of registers and the logic + u32 reset_blocks : 8; /* Enabled when Block_reset_enable = 0xB2 and 0x208 bits 15:8 = 0x00. + Each bit location represents a 0x100 block of registers. Writing + a one in a bit location resets that block of registers and the logic that it controls. */ u32 Block_reset_enable : 8; /* This variable is set to 0xB2 when the register is written. */ u32 Special_controls :16; /* Asserts Reset_V8 => 0xC258; Turns on pci encryption => 0xC25A; @@ -241,10 +241,10 @@ typedef union { } sw_reset_210; struct { - u32 vuart_oe_sig : 1; /* When clear, the V8 processor has sole control of the serial UART - (RS-232 Smart Card interface). When set, the IBI interface + u32 vuart_oe_sig : 1; /* When clear, the V8 processor has sole control of the serial UART + (RS-232 Smart Card interface). When set, the IBI interface defined by register 0x600 controls the serial UART. */ - u32 v2WS_oe_sig : 1; /* When clear, the V8 processor has direct control of the Two-line + u32 v2WS_oe_sig : 1; /* When clear, the V8 processor has direct control of the Two-line Serial Master EEPROM target. When set, the Two-line Serial Master EEPROM target interface is controlled by IBI register 0x100. */ u32 halt_V8_sig : 1; /* When set, contiguous wait states are applied to the V8-space @@ -257,7 +257,7 @@ typedef union { stream into parallel data before downstream processing otherwise interprets the data. */ u32 unused1 : 3; - u32 polarity_PS_CLK_sig: 1; /* This signal is used to invert the input polarity of the tranport + u32 polarity_PS_CLK_sig: 1; /* This signal is used to invert the input polarity of the tranport stream CLOCK signal before any processing occurs on the transport stream within FlexCop3. */ u32 polarity_PS_VALID_sig: 1; /* This signal is used to invert the input polarity of the tranport @@ -271,7 +271,7 @@ typedef union { stream within FlexCop3. */ u32 unused2 :20; } misc_214; - + /* Mailbox from V8 to host */ struct { u32 Mailbox_from_V8 :32; /* When this register is written by either the V8 processor or by an @@ -279,14 +279,14 @@ typedef union { that mailbox data is available. Reading register 20c will clear the IRQ. */ } mbox_v8_to_host_218; - + /* Mailbox from host to v8 Mailbox_to_V8 * Mailbox_to_V8 mailbox storage register * used to send messages from PCI to V8. Writing to this register will send an * IRQ to the V8. Then it can read the data from here. Reading this register * will clear the IRQ. If the V8 is halted and bit 31 of this register is set, * then this register is used instead as a direct interface to access the - * V8space memory. + * V8space memory. */ struct { u32 sysramaccess_data : 8; /* Data byte written or read from the specified address in V8 SysRAM. */ @@ -321,7 +321,7 @@ typedef union { u32 PMT_trans : 1; /* When set, Tables/CAI translation will take place for these packets. */ u32 reserved : 2; } pid_filter_304; - + struct { u32 EMM_PID :13; /* EMM PID filter value. Primary use is Entitlement Management Messaging for conditional access-related data. */ @@ -343,22 +343,22 @@ typedef union { u32 Group_mask :13; /* Mask value used in logical "and" equation that defines group filtering */ u32 unused2 : 3; } pid_filter_30c_ext_ind_0_7; - + struct { u32 net_master_read :17; u32 unused :15; } pid_filter_30c_ext_ind_1; - + struct { u32 net_master_write :17; u32 unused :15; } pid_filter_30c_ext_ind_2; - + struct { u32 next_net_master_write :17; u32 unused :15; } pid_filter_30c_ext_ind_3; - + struct { u32 unused1 : 1; u32 state_write :10; @@ -366,12 +366,12 @@ typedef union { u32 stack_read :10; u32 reserved2 : 5; /* default: 00100 */ } pid_filter_30c_ext_ind_4; - + struct { u32 stack_cnt :10; u32 unused :22; } pid_filter_30c_ext_ind_5; - + struct { u32 pid_fsm_save_reg0 : 2; u32 pid_fsm_save_reg1 : 2; @@ -390,9 +390,9 @@ typedef union { representing one of 32 internal PIDn registers as well as its corresponding internal MAC_lown register. */ u32 extra_index_reg : 3; /* This vector is used to select between sets of debug signals routed to register 0x30c. */ - u32 AB_select : 1; /* Used in conjunction with 0x31c. read/write to the MAC_highA or MAC_highB register + u32 AB_select : 1; /* Used in conjunction with 0x31c. read/write to the MAC_highA or MAC_highB register 0=MAC_highB register, 1=MAC_highA */ - u32 pass_alltables : 1; /* 1=Net packets are not filtered against the Network Table ID found in register 0x400. + u32 pass_alltables : 1; /* 1=Net packets are not filtered against the Network Table ID found in register 0x400. All types of networks (DVB, ATSC, ISDB) are passed. */ u32 unused :22; } index_reg_310; @@ -448,7 +448,7 @@ typedef union { u32 MAC3 : 8; u32 MAC6 : 8; } mac_address_418; - + struct { u32 MAC7 : 8; u32 MAC8 : 8; @@ -492,7 +492,7 @@ typedef union { u32 pi_wait_n : 1; u32 pi_busy_n : 1; } pi_608; - + struct { u32 PID :13; u32 key_enable : 1; @@ -540,7 +540,7 @@ typedef union { u32 reserved2 : 6; u32 cao_cnt : 4; } cao_buf_reg_70c; - + struct { u32 media_read :11; u32 reserved1 : 5; @@ -646,13 +646,13 @@ typedef enum { dma2_014 = 0x014, dma2_018 = 0x018, dma2_01c = 0x01c, - + tw_sm_c_100 = 0x100, tw_sm_c_104 = 0x104, tw_sm_c_108 = 0x108, tw_sm_c_10c = 0x10c, tw_sm_c_110 = 0x110, - + lnb_switch_freq_200 = 0x200, misc_204 = 0x204, ctrl_208 = 0x208, @@ -676,12 +676,12 @@ typedef enum { card_id_40c = 0x40c, mac_address_418 = 0x418, mac_address_41c = 0x41c, - + ci_600 = 0x600, pi_604 = 0x604, pi_608 = 0x608, dvb_reg_60c = 0x60c, - + sram_ctrl_reg_700 = 0x700, net_buf_reg_704 = 0x704, cai_buf_reg_708 = 0x708, |