diff options
Diffstat (limited to 'linux/drivers/media/video/cx18/cx18-io.c')
| -rw-r--r-- | linux/drivers/media/video/cx18/cx18-io.c | 39 |
1 files changed, 26 insertions, 13 deletions
diff --git a/linux/drivers/media/video/cx18/cx18-io.c b/linux/drivers/media/video/cx18/cx18-io.c index 31be5e868..0ad8dea3e 100644 --- a/linux/drivers/media/video/cx18/cx18-io.c +++ b/linux/drivers/media/video/cx18/cx18-io.c @@ -31,10 +31,10 @@ void cx18_log_statistics(struct cx18 *cx) if (!(cx18_debug & CX18_DBGFLG_INFO)) return; - for (i = 0; i <= CX18_MAX_MMIO_RETRIES; i++) + for (i = 0; i <= CX18_MAX_MMIO_WR_RETRIES; i++) CX18_DEBUG_INFO("retried_write[%d] = %d\n", i, atomic_read(&cx->mmio_stats.retried_write[i])); - for (i = 0; i <= CX18_MAX_MMIO_RETRIES; i++) + for (i = 0; i <= CX18_MAX_MMIO_RD_RETRIES; i++) CX18_DEBUG_INFO("retried_read[%d] = %d\n", i, atomic_read(&cx->mmio_stats.retried_read[i])); return; @@ -43,7 +43,7 @@ void cx18_log_statistics(struct cx18 *cx) void cx18_raw_writel_retry(struct cx18 *cx, u32 val, void __iomem *addr) { int i; - for (i = 0; i < CX18_MAX_MMIO_RETRIES; i++) { + for (i = 0; i < CX18_MAX_MMIO_WR_RETRIES; i++) { cx18_raw_writel_noretry(cx, val, addr); if (val == cx18_raw_readl_noretry(cx, addr)) break; @@ -55,7 +55,7 @@ u32 cx18_raw_readl_retry(struct cx18 *cx, const void __iomem *addr) { int i; u32 val; - for (i = 0; i < CX18_MAX_MMIO_RETRIES; i++) { + for (i = 0; i < CX18_MAX_MMIO_RD_RETRIES; i++) { val = cx18_raw_readl_noretry(cx, addr); if (val != 0xffffffff) /* PCI bus read error */ break; @@ -68,7 +68,7 @@ u16 cx18_raw_readw_retry(struct cx18 *cx, const void __iomem *addr) { int i; u16 val; - for (i = 0; i < CX18_MAX_MMIO_RETRIES; i++) { + for (i = 0; i < CX18_MAX_MMIO_RD_RETRIES; i++) { val = cx18_raw_readw_noretry(cx, addr); if (val != 0xffff) /* PCI bus read error */ break; @@ -80,7 +80,7 @@ u16 cx18_raw_readw_retry(struct cx18 *cx, const void __iomem *addr) void cx18_writel_retry(struct cx18 *cx, u32 val, void __iomem *addr) { int i; - for (i = 0; i < CX18_MAX_MMIO_RETRIES; i++) { + for (i = 0; i < CX18_MAX_MMIO_WR_RETRIES; i++) { cx18_writel_noretry(cx, val, addr); if (val == cx18_readl_noretry(cx, addr)) break; @@ -88,10 +88,23 @@ void cx18_writel_retry(struct cx18 *cx, u32 val, void __iomem *addr) cx18_log_write_retries(cx, i, addr); } +void _cx18_writel_expect(struct cx18 *cx, u32 val, void __iomem *addr, + u32 eval, u32 mask) +{ + int i; + eval &= mask; + for (i = 0; i < CX18_MAX_MMIO_WR_RETRIES; i++) { + cx18_writel_noretry(cx, val, addr); + if (eval == (cx18_readl_noretry(cx, addr) & mask)) + break; + } + cx18_log_write_retries(cx, i, addr); +} + void cx18_writew_retry(struct cx18 *cx, u16 val, void __iomem *addr) { int i; - for (i = 0; i < CX18_MAX_MMIO_RETRIES; i++) { + for (i = 0; i < CX18_MAX_MMIO_WR_RETRIES; i++) { cx18_writew_noretry(cx, val, addr); if (val == cx18_readw_noretry(cx, addr)) break; @@ -102,7 +115,7 @@ void cx18_writew_retry(struct cx18 *cx, u16 val, void __iomem *addr) void cx18_writeb_retry(struct cx18 *cx, u8 val, void __iomem *addr) { int i; - for (i = 0; i < CX18_MAX_MMIO_RETRIES; i++) { + for (i = 0; i < CX18_MAX_MMIO_WR_RETRIES; i++) { cx18_writeb_noretry(cx, val, addr); if (val == cx18_readb_noretry(cx, addr)) break; @@ -114,7 +127,7 @@ u32 cx18_readl_retry(struct cx18 *cx, const void __iomem *addr) { int i; u32 val; - for (i = 0; i < CX18_MAX_MMIO_RETRIES; i++) { + for (i = 0; i < CX18_MAX_MMIO_RD_RETRIES; i++) { val = cx18_readl_noretry(cx, addr); if (val != 0xffffffff) /* PCI bus read error */ break; @@ -127,7 +140,7 @@ u16 cx18_readw_retry(struct cx18 *cx, const void __iomem *addr) { int i; u16 val; - for (i = 0; i < CX18_MAX_MMIO_RETRIES; i++) { + for (i = 0; i < CX18_MAX_MMIO_RD_RETRIES; i++) { val = cx18_readw_noretry(cx, addr); if (val != 0xffff) /* PCI bus read error */ break; @@ -140,7 +153,7 @@ u8 cx18_readb_retry(struct cx18 *cx, const void __iomem *addr) { int i; u8 val; - for (i = 0; i < CX18_MAX_MMIO_RETRIES; i++) { + for (i = 0; i < CX18_MAX_MMIO_RD_RETRIES; i++) { val = cx18_readb_noretry(cx, addr); if (val != 0xff) /* PCI bus read error */ break; @@ -218,7 +231,7 @@ void cx18_memset_io(struct cx18 *cx, void __iomem *addr, int val, size_t count) void cx18_sw1_irq_enable(struct cx18 *cx, u32 val) { u32 r; - cx18_write_reg_noretry(cx, val, SW1_INT_STATUS); + cx18_write_reg_expect(cx, val, SW1_INT_STATUS, ~val, val); r = cx18_read_reg(cx, SW1_INT_ENABLE_PCI); cx18_write_reg(cx, r | val, SW1_INT_ENABLE_PCI); } @@ -233,7 +246,7 @@ void cx18_sw1_irq_disable(struct cx18 *cx, u32 val) void cx18_sw2_irq_enable(struct cx18 *cx, u32 val) { u32 r; - cx18_write_reg_noretry(cx, val, SW2_INT_STATUS); + cx18_write_reg_expect(cx, val, SW2_INT_STATUS, ~val, val); r = cx18_read_reg(cx, SW2_INT_ENABLE_PCI); cx18_write_reg(cx, r | val, SW2_INT_ENABLE_PCI); } |