From aac29554759ba1097551414afc35ed9fa13056c2 Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Sat, 26 Apr 2008 13:13:56 -0300 Subject: From: Mauro Carvalho Chehab Move tuners to common/tuners There were several issues in the past, caused by the hybrid tuner design, since now, the same tuner can be used by drivers/media/dvb and drivers/media/video. This patch moves those common tuners into a common dir. It also moves saa7146 driver into drivers/media/video, where other hybrid drivers are placed. Kconfig items were rearranged, to split V4L/DVB core from their drivers. Signed-off-by: Mauro Carvalho Chehab --- linux/drivers/media/common/tuners/mt20xx.c | 706 +++++++++ linux/drivers/media/common/tuners/mt20xx.h | 37 + .../drivers/media/common/tuners/tda18271-common.c | 734 +++++++++ linux/drivers/media/common/tuners/tda18271-fe.c | 1154 ++++++++++++++ linux/drivers/media/common/tuners/tda18271-maps.c | 1313 ++++++++++++++++ linux/drivers/media/common/tuners/tda18271-priv.h | 229 +++ linux/drivers/media/common/tuners/tda18271.h | 99 ++ linux/drivers/media/common/tuners/tda827x.c | 853 ++++++++++ linux/drivers/media/common/tuners/tda827x.h | 69 + linux/drivers/media/common/tuners/tda8290.c | 833 ++++++++++ linux/drivers/media/common/tuners/tda8290.h | 57 + linux/drivers/media/common/tuners/tda9887.c | 728 +++++++++ linux/drivers/media/common/tuners/tda9887.h | 38 + linux/drivers/media/common/tuners/tea5761.c | 330 ++++ linux/drivers/media/common/tuners/tea5761.h | 47 + linux/drivers/media/common/tuners/tea5767.c | 525 +++++++ linux/drivers/media/common/tuners/tea5767.h | 66 + linux/drivers/media/common/tuners/tuner-i2c.h | 173 ++ linux/drivers/media/common/tuners/tuner-simple.c | 1136 ++++++++++++++ linux/drivers/media/common/tuners/tuner-simple.h | 39 + linux/drivers/media/common/tuners/tuner-types.c | 1653 ++++++++++++++++++++ .../media/common/tuners/tuner-xc2028-types.h | 153 ++ linux/drivers/media/common/tuners/tuner-xc2028.c | 1274 +++++++++++++++ linux/drivers/media/common/tuners/tuner-xc2028.h | 63 + linux/drivers/media/common/tuners/xc5000.c | 983 ++++++++++++ linux/drivers/media/common/tuners/xc5000.h | 63 + linux/drivers/media/common/tuners/xc5000_priv.h | 36 + 27 files changed, 13391 insertions(+) create mode 100644 linux/drivers/media/common/tuners/mt20xx.c create mode 100644 linux/drivers/media/common/tuners/mt20xx.h create mode 100644 linux/drivers/media/common/tuners/tda18271-common.c create mode 100644 linux/drivers/media/common/tuners/tda18271-fe.c create mode 100644 linux/drivers/media/common/tuners/tda18271-maps.c create mode 100644 linux/drivers/media/common/tuners/tda18271-priv.h create mode 100644 linux/drivers/media/common/tuners/tda18271.h create mode 100644 linux/drivers/media/common/tuners/tda827x.c create mode 100644 linux/drivers/media/common/tuners/tda827x.h create mode 100644 linux/drivers/media/common/tuners/tda8290.c create mode 100644 linux/drivers/media/common/tuners/tda8290.h create mode 100644 linux/drivers/media/common/tuners/tda9887.c create mode 100644 linux/drivers/media/common/tuners/tda9887.h create mode 100644 linux/drivers/media/common/tuners/tea5761.c create mode 100644 linux/drivers/media/common/tuners/tea5761.h create mode 100644 linux/drivers/media/common/tuners/tea5767.c create mode 100644 linux/drivers/media/common/tuners/tea5767.h create mode 100644 linux/drivers/media/common/tuners/tuner-i2c.h create mode 100644 linux/drivers/media/common/tuners/tuner-simple.c create mode 100644 linux/drivers/media/common/tuners/tuner-simple.h create mode 100644 linux/drivers/media/common/tuners/tuner-types.c create mode 100644 linux/drivers/media/common/tuners/tuner-xc2028-types.h create mode 100644 linux/drivers/media/common/tuners/tuner-xc2028.c create mode 100644 linux/drivers/media/common/tuners/tuner-xc2028.h create mode 100644 linux/drivers/media/common/tuners/xc5000.c create mode 100644 linux/drivers/media/common/tuners/xc5000.h create mode 100644 linux/drivers/media/common/tuners/xc5000_priv.h (limited to 'linux/drivers/media/common/tuners') diff --git a/linux/drivers/media/common/tuners/mt20xx.c b/linux/drivers/media/common/tuners/mt20xx.c new file mode 100644 index 000000000..d2c281aeb --- /dev/null +++ b/linux/drivers/media/common/tuners/mt20xx.c @@ -0,0 +1,706 @@ +/* + * i2c tv tuner chip device driver + * controls microtune tuners, mt2032 + mt2050 at the moment. + * + * This "mt20xx" module was split apart from the original "tuner" module. + */ +#include +#include +#include "compat.h" +#include +#include "tuner-i2c.h" +#include "mt20xx.h" +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0) +#include "i2c-compat.h" +#endif + +static int debug; +module_param(debug, int, 0644); +MODULE_PARM_DESC(debug, "enable verbose debug messages"); + +/* ---------------------------------------------------------------------- */ + +static unsigned int optimize_vco = 1; +module_param(optimize_vco, int, 0644); + +static unsigned int tv_antenna = 1; +module_param(tv_antenna, int, 0644); + +static unsigned int radio_antenna; +module_param(radio_antenna, int, 0644); + +/* ---------------------------------------------------------------------- */ + +#define MT2032 0x04 +#define MT2030 0x06 +#define MT2040 0x07 +#define MT2050 0x42 + +static char *microtune_part[] = { + [ MT2030 ] = "MT2030", + [ MT2032 ] = "MT2032", + [ MT2040 ] = "MT2040", + [ MT2050 ] = "MT2050", +}; + +struct microtune_priv { + struct tuner_i2c_props i2c_props; + + unsigned int xogc; + //unsigned int radio_if2; + + u32 frequency; +}; + +static int microtune_release(struct dvb_frontend *fe) +{ + kfree(fe->tuner_priv); + fe->tuner_priv = NULL; + + return 0; +} + +static int microtune_get_frequency(struct dvb_frontend *fe, u32 *frequency) +{ + struct microtune_priv *priv = fe->tuner_priv; + *frequency = priv->frequency; + return 0; +} + +// IsSpurInBand()? +static int mt2032_spurcheck(struct dvb_frontend *fe, + int f1, int f2, int spectrum_from,int spectrum_to) +{ + struct microtune_priv *priv = fe->tuner_priv; + int n1=1,n2,f; + + f1=f1/1000; //scale to kHz to avoid 32bit overflows + f2=f2/1000; + spectrum_from/=1000; + spectrum_to/=1000; + + tuner_dbg("spurcheck f1=%d f2=%d from=%d to=%d\n", + f1,f2,spectrum_from,spectrum_to); + + do { + n2=-n1; + f=n1*(f1-f2); + do { + n2--; + f=f-f2; + tuner_dbg("spurtest n1=%d n2=%d ftest=%d\n",n1,n2,f); + + if( (f>spectrum_from) && (f(f2-spectrum_to)) || (n2>-5)); + n1++; + } while (n1<5); + + return 1; +} + +static int mt2032_compute_freq(struct dvb_frontend *fe, + unsigned int rfin, + unsigned int if1, unsigned int if2, + unsigned int spectrum_from, + unsigned int spectrum_to, + unsigned char *buf, + int *ret_sel, + unsigned int xogc) //all in Hz +{ + struct microtune_priv *priv = fe->tuner_priv; + unsigned int fref,lo1,lo1n,lo1a,s,sel,lo1freq, desired_lo1, + desired_lo2,lo2,lo2n,lo2a,lo2num,lo2freq; + + fref= 5250 *1000; //5.25MHz + desired_lo1=rfin+if1; + + lo1=(2*(desired_lo1/1000)+(fref/1000)) / (2*fref/1000); + lo1n=lo1/8; + lo1a=lo1-(lo1n*8); + + s=rfin/1000/1000+1090; + + if(optimize_vco) { + if(s>1890) sel=0; + else if(s>1720) sel=1; + else if(s>1530) sel=2; + else if(s>1370) sel=3; + else sel=4; // >1090 + } + else { + if(s>1790) sel=0; // <1958 + else if(s>1617) sel=1; + else if(s>1449) sel=2; + else if(s>1291) sel=3; + else sel=4; // >1090 + } + *ret_sel=sel; + + lo1freq=(lo1a+8*lo1n)*fref; + + tuner_dbg("mt2032: rfin=%d lo1=%d lo1n=%d lo1a=%d sel=%d, lo1freq=%d\n", + rfin,lo1,lo1n,lo1a,sel,lo1freq); + + desired_lo2=lo1freq-rfin-if2; + lo2=(desired_lo2)/fref; + lo2n=lo2/8; + lo2a=lo2-(lo2n*8); + lo2num=((desired_lo2/1000)%(fref/1000))* 3780/(fref/1000); //scale to fit in 32bit arith + lo2freq=(lo2a+8*lo2n)*fref + lo2num*(fref/1000)/3780*1000; + + tuner_dbg("mt2032: rfin=%d lo2=%d lo2n=%d lo2a=%d num=%d lo2freq=%d\n", + rfin,lo2,lo2n,lo2a,lo2num,lo2freq); + + if(lo1a<0 || lo1a>7 || lo1n<17 ||lo1n>48 || lo2a<0 ||lo2a >7 ||lo2n<17 || lo2n>30) { + tuner_info("mt2032: frequency parameters out of range: %d %d %d %d\n", + lo1a, lo1n, lo2a,lo2n); + return(-1); + } + + mt2032_spurcheck(fe, lo1freq, desired_lo2, spectrum_from, spectrum_to); + // should recalculate lo1 (one step up/down) + + // set up MT2032 register map for transfer over i2c + buf[0]=lo1n-1; + buf[1]=lo1a | (sel<<4); + buf[2]=0x86; // LOGC + buf[3]=0x0f; //reserved + buf[4]=0x1f; + buf[5]=(lo2n-1) | (lo2a<<5); + if(rfin >400*1000*1000) + buf[6]=0xe4; + else + buf[6]=0xf4; // set PKEN per rev 1.2 + buf[7]=8+xogc; + buf[8]=0xc3; //reserved + buf[9]=0x4e; //reserved + buf[10]=0xec; //reserved + buf[11]=(lo2num&0xff); + buf[12]=(lo2num>>8) |0x80; // Lo2RST + + return 0; +} + +static int mt2032_check_lo_lock(struct dvb_frontend *fe) +{ + struct microtune_priv *priv = fe->tuner_priv; + int try,lock=0; + unsigned char buf[2]; + + for(try=0;try<10;try++) { + buf[0]=0x0e; + tuner_i2c_xfer_send(&priv->i2c_props,buf,1); + tuner_i2c_xfer_recv(&priv->i2c_props,buf,1); + tuner_dbg("mt2032 Reg.E=0x%02x\n",buf[0]); + lock=buf[0] &0x06; + + if (lock==6) + break; + + tuner_dbg("mt2032: pll wait 1ms for lock (0x%2x)\n",buf[0]); + udelay(1000); + } + return lock; +} + +static int mt2032_optimize_vco(struct dvb_frontend *fe,int sel,int lock) +{ + struct microtune_priv *priv = fe->tuner_priv; + unsigned char buf[2]; + int tad1; + + buf[0]=0x0f; + tuner_i2c_xfer_send(&priv->i2c_props,buf,1); + tuner_i2c_xfer_recv(&priv->i2c_props,buf,1); + tuner_dbg("mt2032 Reg.F=0x%02x\n",buf[0]); + tad1=buf[0]&0x07; + + if(tad1 ==0) return lock; + if(tad1 ==1) return lock; + + if(tad1==2) { + if(sel==0) + return lock; + else sel--; + } + else { + if(sel<4) + sel++; + else + return lock; + } + + tuner_dbg("mt2032 optimize_vco: sel=%d\n",sel); + + buf[0]=0x0f; + buf[1]=sel; + tuner_i2c_xfer_send(&priv->i2c_props,buf,2); + lock=mt2032_check_lo_lock(fe); + return lock; +} + + +static void mt2032_set_if_freq(struct dvb_frontend *fe, unsigned int rfin, + unsigned int if1, unsigned int if2, + unsigned int from, unsigned int to) +{ + unsigned char buf[21]; + int lint_try,ret,sel,lock=0; + struct microtune_priv *priv = fe->tuner_priv; + + tuner_dbg("mt2032_set_if_freq rfin=%d if1=%d if2=%d from=%d to=%d\n", + rfin,if1,if2,from,to); + + buf[0]=0; + ret=tuner_i2c_xfer_send(&priv->i2c_props,buf,1); + tuner_i2c_xfer_recv(&priv->i2c_props,buf,21); + + buf[0]=0; + ret=mt2032_compute_freq(fe,rfin,if1,if2,from,to,&buf[1],&sel,priv->xogc); + if (ret<0) + return; + + // send only the relevant registers per Rev. 1.2 + buf[0]=0; + ret=tuner_i2c_xfer_send(&priv->i2c_props,buf,4); + buf[5]=5; + ret=tuner_i2c_xfer_send(&priv->i2c_props,buf+5,4); + buf[11]=11; + ret=tuner_i2c_xfer_send(&priv->i2c_props,buf+11,3); + if(ret!=3) + tuner_warn("i2c i/o error: rc == %d (should be 3)\n",ret); + + // wait for PLLs to lock (per manual), retry LINT if not. + for(lint_try=0; lint_try<2; lint_try++) { + lock=mt2032_check_lo_lock(fe); + + if(optimize_vco) + lock=mt2032_optimize_vco(fe,sel,lock); + if(lock==6) break; + + tuner_dbg("mt2032: re-init PLLs by LINT\n"); + buf[0]=7; + buf[1]=0x80 +8+priv->xogc; // set LINT to re-init PLLs + tuner_i2c_xfer_send(&priv->i2c_props,buf,2); + mdelay(10); + buf[1]=8+priv->xogc; + tuner_i2c_xfer_send(&priv->i2c_props,buf,2); + } + + if (lock!=6) + tuner_warn("MT2032 Fatal Error: PLLs didn't lock.\n"); + + buf[0]=2; + buf[1]=0x20; // LOGC for optimal phase noise + ret=tuner_i2c_xfer_send(&priv->i2c_props,buf,2); + if (ret!=2) + tuner_warn("i2c i/o error: rc == %d (should be 2)\n",ret); +} + + +static int mt2032_set_tv_freq(struct dvb_frontend *fe, + struct analog_parameters *params) +{ + int if2,from,to; + + // signal bandwidth and picture carrier + if (params->std & V4L2_STD_525_60) { + // NTSC + from = 40750*1000; + to = 46750*1000; + if2 = 45750*1000; + } else { + // PAL + from = 32900*1000; + to = 39900*1000; + if2 = 38900*1000; + } + + mt2032_set_if_freq(fe, params->frequency*62500, + 1090*1000*1000, if2, from, to); + + return 0; +} + +static int mt2032_set_radio_freq(struct dvb_frontend *fe, + struct analog_parameters *params) +{ + struct microtune_priv *priv = fe->tuner_priv; + int if2; + + if (params->std & V4L2_STD_525_60) { + tuner_dbg("pinnacle ntsc\n"); + if2 = 41300 * 1000; + } else { + tuner_dbg("pinnacle pal\n"); + if2 = 33300 * 1000; + } + + // per Manual for FM tuning: first if center freq. 1085 MHz + mt2032_set_if_freq(fe, params->frequency * 125 / 2, + 1085*1000*1000,if2,if2,if2); + + return 0; +} + +static int mt2032_set_params(struct dvb_frontend *fe, + struct analog_parameters *params) +{ + struct microtune_priv *priv = fe->tuner_priv; + int ret = -EINVAL; + + switch (params->mode) { + case V4L2_TUNER_RADIO: + ret = mt2032_set_radio_freq(fe, params); + priv->frequency = params->frequency * 125 / 2; + break; + case V4L2_TUNER_ANALOG_TV: + case V4L2_TUNER_DIGITAL_TV: + ret = mt2032_set_tv_freq(fe, params); + priv->frequency = params->frequency * 62500; + break; + } + + return ret; +} + +static struct dvb_tuner_ops mt2032_tuner_ops = { +#if 0 + .info = { + .name = "MT2032", + .frequency_min = , + .frequency_max = , + .frequency_step = , + }, +#endif + .set_analog_params = mt2032_set_params, + .release = microtune_release, + .get_frequency = microtune_get_frequency, +}; + +// Initialization as described in "MT203x Programming Procedures", Rev 1.2, Feb.2001 +static int mt2032_init(struct dvb_frontend *fe) +{ + struct microtune_priv *priv = fe->tuner_priv; + unsigned char buf[21]; + int ret,xogc,xok=0; + + // Initialize Registers per spec. + buf[1]=2; // Index to register 2 + buf[2]=0xff; + buf[3]=0x0f; + buf[4]=0x1f; + ret=tuner_i2c_xfer_send(&priv->i2c_props,buf+1,4); + + buf[5]=6; // Index register 6 + buf[6]=0xe4; + buf[7]=0x8f; + buf[8]=0xc3; + buf[9]=0x4e; + buf[10]=0xec; + ret=tuner_i2c_xfer_send(&priv->i2c_props,buf+5,6); + + buf[12]=13; // Index register 13 + buf[13]=0x32; + ret=tuner_i2c_xfer_send(&priv->i2c_props,buf+12,2); + + // Adjust XOGC (register 7), wait for XOK + xogc=7; + do { + tuner_dbg("mt2032: xogc = 0x%02x\n",xogc&0x07); + mdelay(10); + buf[0]=0x0e; + tuner_i2c_xfer_send(&priv->i2c_props,buf,1); + tuner_i2c_xfer_recv(&priv->i2c_props,buf,1); + xok=buf[0]&0x01; + tuner_dbg("mt2032: xok = 0x%02x\n",xok); + if (xok == 1) break; + + xogc--; + tuner_dbg("mt2032: xogc = 0x%02x\n",xogc&0x07); + if (xogc == 3) { + xogc=4; // min. 4 per spec + break; + } + buf[0]=0x07; + buf[1]=0x88 + xogc; + ret=tuner_i2c_xfer_send(&priv->i2c_props,buf,2); + if (ret!=2) + tuner_warn("i2c i/o error: rc == %d (should be 2)\n",ret); + } while (xok != 1 ); + priv->xogc=xogc; + + memcpy(&fe->ops.tuner_ops, &mt2032_tuner_ops, sizeof(struct dvb_tuner_ops)); + + return(1); +} + +static void mt2050_set_antenna(struct dvb_frontend *fe, unsigned char antenna) +{ + struct microtune_priv *priv = fe->tuner_priv; + unsigned char buf[2]; + int ret; + + buf[0] = 6; + buf[1] = antenna ? 0x11 : 0x10; + ret=tuner_i2c_xfer_send(&priv->i2c_props,buf,2); + tuner_dbg("mt2050: enabled antenna connector %d\n", antenna); +} + +static void mt2050_set_if_freq(struct dvb_frontend *fe,unsigned int freq, unsigned int if2) +{ + struct microtune_priv *priv = fe->tuner_priv; + unsigned int if1=1218*1000*1000; + unsigned int f_lo1,f_lo2,lo1,lo2,f_lo1_modulo,f_lo2_modulo,num1,num2,div1a,div1b,div2a,div2b; + int ret; + unsigned char buf[6]; + + tuner_dbg("mt2050_set_if_freq freq=%d if1=%d if2=%d\n", + freq,if1,if2); + + f_lo1=freq+if1; + f_lo1=(f_lo1/1000000)*1000000; + + f_lo2=f_lo1-freq-if2; + f_lo2=(f_lo2/50000)*50000; + + lo1=f_lo1/4000000; + lo2=f_lo2/4000000; + + f_lo1_modulo= f_lo1-(lo1*4000000); + f_lo2_modulo= f_lo2-(lo2*4000000); + + num1=4*f_lo1_modulo/4000000; + num2=4096*(f_lo2_modulo/1000)/4000; + + // todo spurchecks + + div1a=(lo1/12)-1; + div1b=lo1-(div1a+1)*12; + + div2a=(lo2/8)-1; + div2b=lo2-(div2a+1)*8; + + if (debug > 1) { + tuner_dbg("lo1 lo2 = %d %d\n", lo1, lo2); + tuner_dbg("num1 num2 div1a div1b div2a div2b= %x %x %x %x %x %x\n", + num1,num2,div1a,div1b,div2a,div2b); + } + + buf[0]=1; + buf[1]= 4*div1b + num1; + if(freq<275*1000*1000) buf[1] = buf[1]|0x80; + + buf[2]=div1a; + buf[3]=32*div2b + num2/256; + buf[4]=num2-(num2/256)*256; + buf[5]=div2a; + if(num2!=0) buf[5]=buf[5]|0x40; + + if (debug > 1) { + int i; + tuner_dbg("bufs is: "); + for(i=0;i<6;i++) + printk("%x ",buf[i]); + printk("\n"); + } + + ret=tuner_i2c_xfer_send(&priv->i2c_props,buf,6); + if (ret!=6) + tuner_warn("i2c i/o error: rc == %d (should be 6)\n",ret); +} + +static int mt2050_set_tv_freq(struct dvb_frontend *fe, + struct analog_parameters *params) +{ + unsigned int if2; + + if (params->std & V4L2_STD_525_60) { + // NTSC + if2 = 45750*1000; + } else { + // PAL + if2 = 38900*1000; + } + if (V4L2_TUNER_DIGITAL_TV == params->mode) { + // DVB (pinnacle 300i) + if2 = 36150*1000; + } + mt2050_set_if_freq(fe, params->frequency*62500, if2); + mt2050_set_antenna(fe, tv_antenna); + + return 0; +} + +static int mt2050_set_radio_freq(struct dvb_frontend *fe, + struct analog_parameters *params) +{ + struct microtune_priv *priv = fe->tuner_priv; + int if2; + + if (params->std & V4L2_STD_525_60) { + tuner_dbg("pinnacle ntsc\n"); + if2 = 41300 * 1000; + } else { + tuner_dbg("pinnacle pal\n"); + if2 = 33300 * 1000; + } + + mt2050_set_if_freq(fe, params->frequency * 125 / 2, if2); + mt2050_set_antenna(fe, radio_antenna); + + return 0; +} + +static int mt2050_set_params(struct dvb_frontend *fe, + struct analog_parameters *params) +{ + struct microtune_priv *priv = fe->tuner_priv; + int ret = -EINVAL; + + switch (params->mode) { + case V4L2_TUNER_RADIO: + ret = mt2050_set_radio_freq(fe, params); + priv->frequency = params->frequency * 125 / 2; + break; + case V4L2_TUNER_ANALOG_TV: + case V4L2_TUNER_DIGITAL_TV: + ret = mt2050_set_tv_freq(fe, params); + priv->frequency = params->frequency * 62500; + break; + } + + return ret; +} + +static struct dvb_tuner_ops mt2050_tuner_ops = { +#if 0 + .info = { + .name = "MT2050", + .frequency_min = , + .frequency_max = , + .frequency_step = , + }, +#endif + .set_analog_params = mt2050_set_params, + .release = microtune_release, + .get_frequency = microtune_get_frequency, +}; + +static int mt2050_init(struct dvb_frontend *fe) +{ + struct microtune_priv *priv = fe->tuner_priv; + unsigned char buf[2]; + int ret; + + buf[0]=6; + buf[1]=0x10; + ret=tuner_i2c_xfer_send(&priv->i2c_props,buf,2); // power + + buf[0]=0x0f; + buf[1]=0x0f; + ret=tuner_i2c_xfer_send(&priv->i2c_props,buf,2); // m1lo + + buf[0]=0x0d; + ret=tuner_i2c_xfer_send(&priv->i2c_props,buf,1); + tuner_i2c_xfer_recv(&priv->i2c_props,buf,1); + + tuner_dbg("mt2050: sro is %x\n",buf[0]); + + memcpy(&fe->ops.tuner_ops, &mt2050_tuner_ops, sizeof(struct dvb_tuner_ops)); + + return 0; +} + +struct dvb_frontend *microtune_attach(struct dvb_frontend *fe, + struct i2c_adapter* i2c_adap, + u8 i2c_addr) +{ + struct microtune_priv *priv = NULL; + char *name; + unsigned char buf[21]; + int company_code; + + priv = kzalloc(sizeof(struct microtune_priv), GFP_KERNEL); + if (priv == NULL) + return NULL; + fe->tuner_priv = priv; + + priv->i2c_props.addr = i2c_addr; + priv->i2c_props.adap = i2c_adap; + priv->i2c_props.name = "mt20xx"; + + //priv->radio_if2 = 10700 * 1000; /* 10.7MHz - FM radio */ + + memset(buf,0,sizeof(buf)); + + name = "unknown"; + + tuner_i2c_xfer_send(&priv->i2c_props,buf,1); + tuner_i2c_xfer_recv(&priv->i2c_props,buf,21); + if (debug) { + int i; + tuner_dbg("MT20xx hexdump:"); + for(i=0;i<21;i++) { + printk(" %02x",buf[i]); + if(((i+1)%8)==0) printk(" "); + } + printk("\n"); + } + company_code = buf[0x11] << 8 | buf[0x12]; + tuner_info("microtune: companycode=%04x part=%02x rev=%02x\n", + company_code,buf[0x13],buf[0x14]); + +#if 0 + /* seems to cause more problems than it solves ... */ + switch (company_code) { + case 0x30bf: + case 0x3cbf: + case 0x3dbf: + case 0x4d54: + case 0x8e81: + case 0x8e91: + /* ok (?) */ + break; + default: + tuner_warn("tuner: microtune: unknown companycode\n"); + return 0; + } +#endif + + if (buf[0x13] < ARRAY_SIZE(microtune_part) && + NULL != microtune_part[buf[0x13]]) + name = microtune_part[buf[0x13]]; + switch (buf[0x13]) { + case MT2032: + mt2032_init(fe); + break; + case MT2050: + mt2050_init(fe); + break; + default: + tuner_info("microtune %s found, not (yet?) supported, sorry :-/\n", + name); + return NULL; + } + + strlcpy(fe->ops.tuner_ops.info.name, name, + sizeof(fe->ops.tuner_ops.info.name)); + tuner_info("microtune %s found, OK\n",name); + return fe; +} + +EXPORT_SYMBOL_GPL(microtune_attach); + +MODULE_DESCRIPTION("Microtune tuner driver"); +MODULE_AUTHOR("Ralph Metzler, Gerd Knorr, Gunther Mayer"); +MODULE_LICENSE("GPL"); + +/* + * Overrides for Emacs so that we follow Linus's tabbing style. + * --------------------------------------------------------------------------- + * Local variables: + * c-basic-offset: 8 + * End: + */ diff --git a/linux/drivers/media/common/tuners/mt20xx.h b/linux/drivers/media/common/tuners/mt20xx.h new file mode 100644 index 000000000..aa848e14c --- /dev/null +++ b/linux/drivers/media/common/tuners/mt20xx.h @@ -0,0 +1,37 @@ +/* + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. +*/ + +#ifndef __MT20XX_H__ +#define __MT20XX_H__ + +#include +#include "dvb_frontend.h" + +#if defined(CONFIG_TUNER_MT20XX) || (defined(CONFIG_TUNER_MT20XX_MODULE) && defined(MODULE)) +extern struct dvb_frontend *microtune_attach(struct dvb_frontend *fe, + struct i2c_adapter* i2c_adap, + u8 i2c_addr); +#else +static inline struct dvb_frontend *microtune_attach(struct dvb_frontend *fe, + struct i2c_adapter* i2c_adap, + u8 i2c_addr) +{ + printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__); + return NULL; +} +#endif + +#endif /* __MT20XX_H__ */ diff --git a/linux/drivers/media/common/tuners/tda18271-common.c b/linux/drivers/media/common/tuners/tda18271-common.c new file mode 100644 index 000000000..43c0bec83 --- /dev/null +++ b/linux/drivers/media/common/tuners/tda18271-common.c @@ -0,0 +1,734 @@ +/* + tda18271-common.c - driver for the Philips / NXP TDA18271 silicon tuner + + Copyright (C) 2007, 2008 Michael Krufky + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. +*/ + +#include "tda18271-priv.h" + +static int tda18271_i2c_gate_ctrl(struct dvb_frontend *fe, int enable) +{ + struct tda18271_priv *priv = fe->tuner_priv; + enum tda18271_i2c_gate gate; + int ret = 0; + + switch (priv->gate) { + case TDA18271_GATE_DIGITAL: + case TDA18271_GATE_ANALOG: + gate = priv->gate; + break; + case TDA18271_GATE_AUTO: + default: + switch (priv->mode) { + case TDA18271_DIGITAL: + gate = TDA18271_GATE_DIGITAL; + break; + case TDA18271_ANALOG: + default: + gate = TDA18271_GATE_ANALOG; + break; + } + } + + switch (gate) { + case TDA18271_GATE_ANALOG: + if (fe->ops.analog_ops.i2c_gate_ctrl) + ret = fe->ops.analog_ops.i2c_gate_ctrl(fe, enable); + break; + case TDA18271_GATE_DIGITAL: + if (fe->ops.i2c_gate_ctrl) + ret = fe->ops.i2c_gate_ctrl(fe, enable); + break; + default: + ret = -EINVAL; + break; + } + + return ret; +}; + +/*---------------------------------------------------------------------*/ + +static void tda18271_dump_regs(struct dvb_frontend *fe, int extended) +{ + struct tda18271_priv *priv = fe->tuner_priv; + unsigned char *regs = priv->tda18271_regs; + + tda_reg("=== TDA18271 REG DUMP ===\n"); + tda_reg("ID_BYTE = 0x%02x\n", 0xff & regs[R_ID]); + tda_reg("THERMO_BYTE = 0x%02x\n", 0xff & regs[R_TM]); + tda_reg("POWER_LEVEL_BYTE = 0x%02x\n", 0xff & regs[R_PL]); + tda_reg("EASY_PROG_BYTE_1 = 0x%02x\n", 0xff & regs[R_EP1]); + tda_reg("EASY_PROG_BYTE_2 = 0x%02x\n", 0xff & regs[R_EP2]); + tda_reg("EASY_PROG_BYTE_3 = 0x%02x\n", 0xff & regs[R_EP3]); + tda_reg("EASY_PROG_BYTE_4 = 0x%02x\n", 0xff & regs[R_EP4]); + tda_reg("EASY_PROG_BYTE_5 = 0x%02x\n", 0xff & regs[R_EP5]); + tda_reg("CAL_POST_DIV_BYTE = 0x%02x\n", 0xff & regs[R_CPD]); + tda_reg("CAL_DIV_BYTE_1 = 0x%02x\n", 0xff & regs[R_CD1]); + tda_reg("CAL_DIV_BYTE_2 = 0x%02x\n", 0xff & regs[R_CD2]); + tda_reg("CAL_DIV_BYTE_3 = 0x%02x\n", 0xff & regs[R_CD3]); + tda_reg("MAIN_POST_DIV_BYTE = 0x%02x\n", 0xff & regs[R_MPD]); + tda_reg("MAIN_DIV_BYTE_1 = 0x%02x\n", 0xff & regs[R_MD1]); + tda_reg("MAIN_DIV_BYTE_2 = 0x%02x\n", 0xff & regs[R_MD2]); + tda_reg("MAIN_DIV_BYTE_3 = 0x%02x\n", 0xff & regs[R_MD3]); + + /* only dump extended regs if DBG_ADV is set */ + if (!(tda18271_debug & DBG_ADV)) + return; + + /* W indicates write-only registers. + * Register dump for write-only registers shows last value written. */ + + tda_reg("EXTENDED_BYTE_1 = 0x%02x\n", 0xff & regs[R_EB1]); + tda_reg("EXTENDED_BYTE_2 = 0x%02x\n", 0xff & regs[R_EB2]); + tda_reg("EXTENDED_BYTE_3 = 0x%02x\n", 0xff & regs[R_EB3]); + tda_reg("EXTENDED_BYTE_4 = 0x%02x\n", 0xff & regs[R_EB4]); + tda_reg("EXTENDED_BYTE_5 = 0x%02x\n", 0xff & regs[R_EB5]); + tda_reg("EXTENDED_BYTE_6 = 0x%02x\n", 0xff & regs[R_EB6]); + tda_reg("EXTENDED_BYTE_7 = 0x%02x\n", 0xff & regs[R_EB7]); + tda_reg("EXTENDED_BYTE_8 = 0x%02x\n", 0xff & regs[R_EB8]); + tda_reg("EXTENDED_BYTE_9 W = 0x%02x\n", 0xff & regs[R_EB9]); + tda_reg("EXTENDED_BYTE_10 = 0x%02x\n", 0xff & regs[R_EB10]); + tda_reg("EXTENDED_BYTE_11 = 0x%02x\n", 0xff & regs[R_EB11]); + tda_reg("EXTENDED_BYTE_12 = 0x%02x\n", 0xff & regs[R_EB12]); + tda_reg("EXTENDED_BYTE_13 = 0x%02x\n", 0xff & regs[R_EB13]); + tda_reg("EXTENDED_BYTE_14 = 0x%02x\n", 0xff & regs[R_EB14]); + tda_reg("EXTENDED_BYTE_15 = 0x%02x\n", 0xff & regs[R_EB15]); + tda_reg("EXTENDED_BYTE_16 W = 0x%02x\n", 0xff & regs[R_EB16]); + tda_reg("EXTENDED_BYTE_17 W = 0x%02x\n", 0xff & regs[R_EB17]); + tda_reg("EXTENDED_BYTE_18 = 0x%02x\n", 0xff & regs[R_EB18]); + tda_reg("EXTENDED_BYTE_19 W = 0x%02x\n", 0xff & regs[R_EB19]); + tda_reg("EXTENDED_BYTE_20 W = 0x%02x\n", 0xff & regs[R_EB20]); + tda_reg("EXTENDED_BYTE_21 = 0x%02x\n", 0xff & regs[R_EB21]); + tda_reg("EXTENDED_BYTE_22 = 0x%02x\n", 0xff & regs[R_EB22]); + tda_reg("EXTENDED_BYTE_23 = 0x%02x\n", 0xff & regs[R_EB23]); +} + +int tda18271_read_regs(struct dvb_frontend *fe) +{ + struct tda18271_priv *priv = fe->tuner_priv; + unsigned char *regs = priv->tda18271_regs; + unsigned char buf = 0x00; + int ret; + struct i2c_msg msg[] = { + { .addr = priv->i2c_props.addr, .flags = 0, + .buf = &buf, .len = 1 }, + { .addr = priv->i2c_props.addr, .flags = I2C_M_RD, + .buf = regs, .len = 16 } + }; + + tda18271_i2c_gate_ctrl(fe, 1); + + /* read all registers */ + ret = i2c_transfer(priv->i2c_props.adap, msg, 2); + + tda18271_i2c_gate_ctrl(fe, 0); + + if (ret != 2) + tda_err("ERROR: i2c_transfer returned: %d\n", ret); + + if (tda18271_debug & DBG_REG) + tda18271_dump_regs(fe, 0); + + return (ret == 2 ? 0 : ret); +} + +int tda18271_read_extended(struct dvb_frontend *fe) +{ + struct tda18271_priv *priv = fe->tuner_priv; + unsigned char *regs = priv->tda18271_regs; + unsigned char regdump[TDA18271_NUM_REGS]; + unsigned char buf = 0x00; + int ret, i; + struct i2c_msg msg[] = { + { .addr = priv->i2c_props.addr, .flags = 0, + .buf = &buf, .len = 1 }, + { .addr = priv->i2c_props.addr, .flags = I2C_M_RD, + .buf = regdump, .len = TDA18271_NUM_REGS } + }; + + tda18271_i2c_gate_ctrl(fe, 1); + + /* read all registers */ + ret = i2c_transfer(priv->i2c_props.adap, msg, 2); + + tda18271_i2c_gate_ctrl(fe, 0); + + if (ret != 2) + tda_err("ERROR: i2c_transfer returned: %d\n", ret); + + for (i = 0; i < TDA18271_NUM_REGS; i++) { + /* don't update write-only registers */ + if ((i != R_EB9) && + (i != R_EB16) && + (i != R_EB17) && + (i != R_EB19) && + (i != R_EB20)) + regs[i] = regdump[i]; + } + + if (tda18271_debug & DBG_REG) + tda18271_dump_regs(fe, 1); + + return (ret == 2 ? 0 : ret); +} + +int tda18271_write_regs(struct dvb_frontend *fe, int idx, int len) +{ + struct tda18271_priv *priv = fe->tuner_priv; + unsigned char *regs = priv->tda18271_regs; + unsigned char buf[TDA18271_NUM_REGS + 1]; + struct i2c_msg msg = { .addr = priv->i2c_props.addr, .flags = 0, + .buf = buf, .len = len + 1 }; + int i, ret; + + BUG_ON((len == 0) || (idx + len > sizeof(buf))); + + buf[0] = idx; + for (i = 1; i <= len; i++) + buf[i] = regs[idx - 1 + i]; + + tda18271_i2c_gate_ctrl(fe, 1); + + /* write registers */ + ret = i2c_transfer(priv->i2c_props.adap, &msg, 1); + + tda18271_i2c_gate_ctrl(fe, 0); + + if (ret != 1) + tda_err("ERROR: i2c_transfer returned: %d\n", ret); + + return (ret == 1 ? 0 : ret); +} + +/*---------------------------------------------------------------------*/ + +int tda18271_charge_pump_source(struct dvb_frontend *fe, + enum tda18271_pll pll, int force) +{ + struct tda18271_priv *priv = fe->tuner_priv; + unsigned char *regs = priv->tda18271_regs; + + int r_cp = (pll == TDA18271_CAL_PLL) ? R_EB7 : R_EB4; + + regs[r_cp] &= ~0x20; + regs[r_cp] |= ((force & 1) << 5); + tda18271_write_regs(fe, r_cp, 1); + + return 0; +} + +int tda18271_init_regs(struct dvb_frontend *fe) +{ + struct tda18271_priv *priv = fe->tuner_priv; + unsigned char *regs = priv->tda18271_regs; + + tda_dbg("initializing registers for device @ %d-%04x\n", + i2c_adapter_id(priv->i2c_props.adap), + priv->i2c_props.addr); + + /* initialize registers */ + switch (priv->id) { + case TDA18271HDC1: + regs[R_ID] = 0x83; + break; + case TDA18271HDC2: + regs[R_ID] = 0x84; + break; + }; + + regs[R_TM] = 0x08; + regs[R_PL] = 0x80; + regs[R_EP1] = 0xc6; + regs[R_EP2] = 0xdf; + regs[R_EP3] = 0x16; + regs[R_EP4] = 0x60; + regs[R_EP5] = 0x80; + regs[R_CPD] = 0x80; + regs[R_CD1] = 0x00; + regs[R_CD2] = 0x00; + regs[R_CD3] = 0x00; + regs[R_MPD] = 0x00; + regs[R_MD1] = 0x00; + regs[R_MD2] = 0x00; + regs[R_MD3] = 0x00; + + switch (priv->id) { + case TDA18271HDC1: + regs[R_EB1] = 0xff; + break; + case TDA18271HDC2: + regs[R_EB1] = 0xfc; + break; + }; + + regs[R_EB2] = 0x01; + regs[R_EB3] = 0x84; + regs[R_EB4] = 0x41; + regs[R_EB5] = 0x01; + regs[R_EB6] = 0x84; + regs[R_EB7] = 0x40; + regs[R_EB8] = 0x07; + regs[R_EB9] = 0x00; + regs[R_EB10] = 0x00; + regs[R_EB11] = 0x96; + + switch (priv->id) { + case TDA18271HDC1: + regs[R_EB12] = 0x0f; + break; + case TDA18271HDC2: + regs[R_EB12] = 0x33; + break; + }; + + regs[R_EB13] = 0xc1; + regs[R_EB14] = 0x00; + regs[R_EB15] = 0x8f; + regs[R_EB16] = 0x00; + regs[R_EB17] = 0x00; + + switch (priv->id) { + case TDA18271HDC1: + regs[R_EB18] = 0x00; + break; + case TDA18271HDC2: + regs[R_EB18] = 0x8c; + break; + }; + + regs[R_EB19] = 0x00; + regs[R_EB20] = 0x20; + + switch (priv->id) { + case TDA18271HDC1: + regs[R_EB21] = 0x33; + break; + case TDA18271HDC2: + regs[R_EB21] = 0xb3; + break; + }; + + regs[R_EB22] = 0x48; + regs[R_EB23] = 0xb0; + + if (priv->small_i2c) { + tda18271_write_regs(fe, 0x00, 0x10); + tda18271_write_regs(fe, 0x10, 0x10); + tda18271_write_regs(fe, 0x20, 0x07); + } else + tda18271_write_regs(fe, 0x00, TDA18271_NUM_REGS); + + /* setup agc1 gain */ + regs[R_EB17] = 0x00; + tda18271_write_regs(fe, R_EB17, 1); + regs[R_EB17] = 0x03; + tda18271_write_regs(fe, R_EB17, 1); + regs[R_EB17] = 0x43; + tda18271_write_regs(fe, R_EB17, 1); + regs[R_EB17] = 0x4c; + tda18271_write_regs(fe, R_EB17, 1); + + /* setup agc2 gain */ + if ((priv->id) == TDA18271HDC1) { + regs[R_EB20] = 0xa0; + tda18271_write_regs(fe, R_EB20, 1); + regs[R_EB20] = 0xa7; + tda18271_write_regs(fe, R_EB20, 1); + regs[R_EB20] = 0xe7; + tda18271_write_regs(fe, R_EB20, 1); + regs[R_EB20] = 0xec; + tda18271_write_regs(fe, R_EB20, 1); + } + + /* image rejection calibration */ + + /* low-band */ + regs[R_EP3] = 0x1f; + regs[R_EP4] = 0x66; + regs[R_EP5] = 0x81; + regs[R_CPD] = 0xcc; + regs[R_CD1] = 0x6c; + regs[R_CD2] = 0x00; + regs[R_CD3] = 0x00; + regs[R_MPD] = 0xcd; + regs[R_MD1] = 0x77; + regs[R_MD2] = 0x08; + regs[R_MD3] = 0x00; + + tda18271_write_regs(fe, R_EP3, 11); + + if ((priv->id) == TDA18271HDC2) { + /* main pll cp source on */ + tda18271_charge_pump_source(fe, TDA18271_MAIN_PLL, 1); + msleep(1); + + /* main pll cp source off */ + tda18271_charge_pump_source(fe, TDA18271_MAIN_PLL, 0); + } + + msleep(5); /* pll locking */ + + /* launch detector */ +#if 0 + regs[R_EP1] = 0xc6; /* already set */ +#endif + tda18271_write_regs(fe, R_EP1, 1); + msleep(5); /* wanted low measurement */ + +#if 0 + regs[R_EP3] = 0x1f; /* already set */ + regs[R_EP4] = 0x66; /* already set */ +#endif + regs[R_EP5] = 0x85; + regs[R_CPD] = 0xcb; + regs[R_CD1] = 0x66; + regs[R_CD2] = 0x70; +#if 0 + regs[R_CD3] = 0x00; /* already set */ +#endif + + tda18271_write_regs(fe, R_EP3, 7); + msleep(5); /* pll locking */ + + /* launch optimization algorithm */ +#if 0 + regs[R_EP2] = 0xdf; /* already set */ +#endif + tda18271_write_regs(fe, R_EP2, 1); + msleep(30); /* image low optimization completion */ + + /* mid-band */ +#if 0 + regs[R_EP3] = 0x1f; /* already set */ + regs[R_EP4] = 0x66; /* already set */ +#endif + regs[R_EP5] = 0x82; + regs[R_CPD] = 0xa8; +#if 0 + regs[R_CD1] = 0x66; /* already set */ +#endif + regs[R_CD2] = 0x00; +#if 0 + regs[R_CD3] = 0x00; /* already set */ +#endif + regs[R_MPD] = 0xa9; + regs[R_MD1] = 0x73; + regs[R_MD2] = 0x1a; +#if 0 + regs[R_MD3] = 0x00; /* already set */ +#endif + + tda18271_write_regs(fe, R_EP3, 11); + msleep(5); /* pll locking */ + + /* launch detector */ +#if 0 + regs[R_EP1] = 0xc6; /* already set */ +#endif + tda18271_write_regs(fe, R_EP1, 1); + msleep(5); /* wanted mid measurement */ + +#if 0 + regs[R_EP3] = 0x1f; /* already set */ + regs[R_EP4] = 0x66; /* already set */ +#endif + regs[R_EP5] = 0x86; + regs[R_CPD] = 0xa8; + regs[R_CD1] = 0x66; + regs[R_CD2] = 0xa0; +#if 0 + regs[R_CD3] = 0x00; /* already set */ +#endif + + tda18271_write_regs(fe, R_EP3, 7); + msleep(5); /* pll locking */ + + /* launch optimization algorithm */ +#if 0 + regs[R_EP2] = 0xdf; /* already set */ +#endif + tda18271_write_regs(fe, R_EP2, 1); + msleep(30); /* image mid optimization completion */ + + /* high-band */ +#if 0 + regs[R_EP3] = 0x1f; /* already set */ + regs[R_EP4] = 0x66; /* already set */ +#endif + regs[R_EP5] = 0x83; + regs[R_CPD] = 0x98; + regs[R_CD1] = 0x65; + regs[R_CD2] = 0x00; +#if 0 + regs[R_CD3] = 0x00; /* already set */ +#endif + regs[R_MPD] = 0x99; + regs[R_MD1] = 0x71; + regs[R_MD2] = 0xcd; +#if 0 + regs[R_MD3] = 0x00; /* already set */ +#endif + + tda18271_write_regs(fe, R_EP3, 11); + msleep(5); /* pll locking */ + + /* launch detector */ +#if 0 + regs[R_EP1] = 0xc6; /* already set */ +#endif + tda18271_write_regs(fe, R_EP1, 1); + msleep(5); /* wanted high measurement */ + +#if 0 + regs[R_EP3] = 0x1f; /* already set */ + regs[R_EP4] = 0x66; /* already set */ +#endif + regs[R_EP5] = 0x87; +#if 0 + regs[R_CPD] = 0x98; /* already set */ +#endif + regs[R_CD1] = 0x65; + regs[R_CD2] = 0x50; +#if 0 + regs[R_CD3] = 0x00; /* already set */ +#endif + + tda18271_write_regs(fe, R_EP3, 7); + msleep(5); /* pll locking */ + + /* launch optimization algorithm */ +#if 0 + regs[R_EP2] = 0xdf; /* already set */ +#endif + tda18271_write_regs(fe, R_EP2, 1); + msleep(30); /* image high optimization completion */ + + /* return to normal mode */ + regs[R_EP4] = 0x64; + tda18271_write_regs(fe, R_EP4, 1); + + /* synchronize */ +#if 0 + regs[R_EP1] = 0xc6; /* already set */ +#endif + tda18271_write_regs(fe, R_EP1, 1); + + return 0; +} + +/*---------------------------------------------------------------------*/ + +/* + * Standby modes, EP3 [7:5] + * + * | SM || SM_LT || SM_XT || mode description + * |=====\\=======\\=======\\=================================== + * | 0 || 0 || 0 || normal mode + * |-----||-------||-------||----------------------------------- + * | || || || standby mode w/ slave tuner output + * | 1 || 0 || 0 || & loop thru & xtal oscillator on + * |-----||-------||-------||----------------------------------- + * | 1 || 1 || 0 || standby mode w/ xtal oscillator on + * |-----||-------||-------||----------------------------------- + * | 1 || 1 || 1 || power off + * + */ + +int tda18271_set_standby_mode(struct dvb_frontend *fe, + int sm, int sm_lt, int sm_xt) +{ + struct tda18271_priv *priv = fe->tuner_priv; + unsigned char *regs = priv->tda18271_regs; + + tda_dbg("sm = %d, sm_lt = %d, sm_xt = %d\n", sm, sm_lt, sm_xt); + + regs[R_EP3] &= ~0xe0; /* clear sm, sm_lt, sm_xt */ + regs[R_EP3] |= sm ? (1 << 7) : 0 | + sm_lt ? (1 << 6) : 0 | + sm_xt ? (1 << 5) : 0; + + tda18271_write_regs(fe, R_EP3, 1); + + return 0; +} + +/*---------------------------------------------------------------------*/ + +int tda18271_calc_main_pll(struct dvb_frontend *fe, u32 freq) +{ + /* sets main post divider & divider bytes, but does not write them */ + struct tda18271_priv *priv = fe->tuner_priv; + unsigned char *regs = priv->tda18271_regs; + u8 d, pd; + u32 div; + + int ret = tda18271_lookup_pll_map(fe, MAIN_PLL, &freq, &pd, &d); + if (ret < 0) + goto fail; + + regs[R_MPD] = (0x77 & pd); + + switch (priv->mode) { + case TDA18271_ANALOG: + regs[R_MPD] &= ~0x08; + break; + case TDA18271_DIGITAL: + regs[R_MPD] |= 0x08; + break; + } + + div = ((d * (freq / 1000)) << 7) / 125; + + regs[R_MD1] = 0x7f & (div >> 16); + regs[R_MD2] = 0xff & (div >> 8); + regs[R_MD3] = 0xff & div; +fail: + return ret; +} + +int tda18271_calc_cal_pll(struct dvb_frontend *fe, u32 freq) +{ + /* sets cal post divider & divider bytes, but does not write them */ + struct tda18271_priv *priv = fe->tuner_priv; + unsigned char *regs = priv->tda18271_regs; + u8 d, pd; + u32 div; + + int ret = tda18271_lookup_pll_map(fe, CAL_PLL, &freq, &pd, &d); + if (ret < 0) + goto fail; + + regs[R_CPD] = pd; + + div = ((d * (freq / 1000)) << 7) / 125; + + regs[R_CD1] = 0x7f & (div >> 16); + regs[R_CD2] = 0xff & (div >> 8); + regs[R_CD3] = 0xff & div; +fail: + return ret; +} + +/*---------------------------------------------------------------------*/ + +int tda18271_calc_bp_filter(struct dvb_frontend *fe, u32 *freq) +{ + /* sets bp filter bits, but does not write them */ + struct tda18271_priv *priv = fe->tuner_priv; + unsigned char *regs = priv->tda18271_regs; + u8 val; + + int ret = tda18271_lookup_map(fe, BP_FILTER, freq, &val); + if (ret < 0) + goto fail; + + regs[R_EP1] &= ~0x07; /* clear bp filter bits */ + regs[R_EP1] |= (0x07 & val); +fail: + return ret; +} + +int tda18271_calc_km(struct dvb_frontend *fe, u32 *freq) +{ + /* sets K & M bits, but does not write them */ + struct tda18271_priv *priv = fe->tuner_priv; + unsigned char *regs = priv->tda18271_regs; + u8 val; + + int ret = tda18271_lookup_map(fe, RF_CAL_KMCO, freq, &val); + if (ret < 0) + goto fail; + + regs[R_EB13] &= ~0x7c; /* clear k & m bits */ + regs[R_EB13] |= (0x7c & val); +fail: + return ret; +} + +int tda18271_calc_rf_band(struct dvb_frontend *fe, u32 *freq) +{ + /* sets rf band bits, but does not write them */ + struct tda18271_priv *priv = fe->tuner_priv; + unsigned char *regs = priv->tda18271_regs; + u8 val; + + int ret = tda18271_lookup_map(fe, RF_BAND, freq, &val); + if (ret < 0) + goto fail; + + regs[R_EP2] &= ~0xe0; /* clear rf band bits */ + regs[R_EP2] |= (0xe0 & (val << 5)); +fail: + return ret; +} + +int tda18271_calc_gain_taper(struct dvb_frontend *fe, u32 *freq) +{ + /* sets gain taper bits, but does not write them */ + struct tda18271_priv *priv = fe->tuner_priv; + unsigned char *regs = priv->tda18271_regs; + u8 val; + + int ret = tda18271_lookup_map(fe, GAIN_TAPER, freq, &val); + if (ret < 0) + goto fail; + + regs[R_EP2] &= ~0x1f; /* clear gain taper bits */ + regs[R_EP2] |= (0x1f & val); +fail: + return ret; +} + +int tda18271_calc_ir_measure(struct dvb_frontend *fe, u32 *freq) +{ + /* sets IR Meas bits, but does not write them */ + struct tda18271_priv *priv = fe->tuner_priv; + unsigned char *regs = priv->tda18271_regs; + u8 val; + + int ret = tda18271_lookup_map(fe, IR_MEASURE, freq, &val); + if (ret < 0) + goto fail; + + regs[R_EP5] &= ~0x07; + regs[R_EP5] |= (0x07 & val); +fail: + return ret; +} + +int tda18271_calc_rf_cal(struct dvb_frontend *fe, u32 *freq) +{ + /* sets rf cal byte (RFC_Cprog), but does not write it */ + struct tda18271_priv *priv = fe->tuner_priv; + unsigned char *regs = priv->tda18271_regs; + u8 val; + + tda18271_lookup_map(fe, RF_CAL, freq, &val); + + regs[R_EB14] = val; + + return 0; +} + +/* + * Overrides for Emacs so that we follow Linus's tabbing style. + * --------------------------------------------------------------------------- + * Local variables: + * c-basic-offset: 8 + * End: + */ diff --git a/linux/drivers/media/common/tuners/tda18271-fe.c b/linux/drivers/media/common/tuners/tda18271-fe.c new file mode 100644 index 000000000..355c37a42 --- /dev/null +++ b/linux/drivers/media/common/tuners/tda18271-fe.c @@ -0,0 +1,1154 @@ +/* + tda18271-fe.c - driver for the Philips / NXP TDA18271 silicon tuner + + Copyright (C) 2007, 2008 Michael Krufky + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. +*/ + +#include +#include "compat.h" +#include +#include "tda18271-priv.h" + +int tda18271_debug; +module_param_named(debug, tda18271_debug, int, 0644); +MODULE_PARM_DESC(debug, "set debug level " + "(info=1, map=2, reg=4, adv=8, cal=16 (or-able))"); + +static int tda18271_cal_on_startup; +module_param_named(cal, tda18271_cal_on_startup, int, 0644); +MODULE_PARM_DESC(cal, "perform RF tracking filter calibration on startup"); + +static DEFINE_MUTEX(tda18271_list_mutex); +static LIST_HEAD(hybrid_tuner_instance_list); + +/*---------------------------------------------------------------------*/ + +static inline int charge_pump_source(struct dvb_frontend *fe, int force) +{ + struct tda18271_priv *priv = fe->tuner_priv; + return tda18271_charge_pump_source(fe, + (priv->role == TDA18271_SLAVE) ? + TDA18271_CAL_PLL : + TDA18271_MAIN_PLL, force); +} + +static int tda18271_channel_configuration(struct dvb_frontend *fe, + struct tda18271_std_map_item *map, + u32 freq, u32 bw) +{ + struct tda18271_priv *priv = fe->tuner_priv; + unsigned char *regs = priv->tda18271_regs; + u32 N; + + /* update TV broadcast parameters */ + + /* set standard */ + regs[R_EP3] &= ~0x1f; /* clear std bits */ + regs[R_EP3] |= (map->agc_mode << 3) | map->std; + + /* set rfagc to high speed mode */ + regs[R_EP3] &= ~0x04; + + /* set cal mode to normal */ + regs[R_EP4] &= ~0x03; + + /* update IF output level & IF notch frequency */ + regs[R_EP4] &= ~0x1c; /* clear if level bits */ + regs[R_EP4] |= (map->if_lvl << 2); + + switch (priv->mode) { + case TDA18271_ANALOG: + regs[R_MPD] &= ~0x80; /* IF notch = 0 */ + break; + case TDA18271_DIGITAL: + regs[R_MPD] |= 0x80; /* IF notch = 1 */ + break; + } + + /* update FM_RFn */ + regs[R_EP4] &= ~0x80; + regs[R_EP4] |= map->fm_rfn << 7; + + /* update rf top / if top */ + regs[R_EB22] = 0x00; + regs[R_EB22] |= map->rfagc_top; + tda18271_write_regs(fe, R_EB22, 1); + + /* --------------------------------------------------------------- */ + + /* disable Power Level Indicator */ + regs[R_EP1] |= 0x40; + + /* frequency dependent parameters */ + + tda18271_calc_ir_measure(fe, &freq); + + tda18271_calc_bp_filter(fe, &freq); + + tda18271_calc_rf_band(fe, &freq); + + tda18271_calc_gain_taper(fe, &freq); + + /* --------------------------------------------------------------- */ + + /* dual tuner and agc1 extra configuration */ + + switch (priv->role) { + case TDA18271_MASTER: + regs[R_EB1] |= 0x04; /* main vco */ + break; + case TDA18271_SLAVE: + regs[R_EB1] &= ~0x04; /* cal vco */ + break; + } + + /* agc1 always active */ + regs[R_EB1] &= ~0x02; + + /* agc1 has priority on agc2 */ + regs[R_EB1] &= ~0x01; + + tda18271_write_regs(fe, R_EB1, 1); + + /* --------------------------------------------------------------- */ + + N = map->if_freq * 1000 + freq; + + switch (priv->role) { + case TDA18271_MASTER: + tda18271_calc_main_pll(fe, N); + tda18271_write_regs(fe, R_MPD, 4); + break; + case TDA18271_SLAVE: + tda18271_calc_cal_pll(fe, N); + tda18271_write_regs(fe, R_CPD, 4); + + regs[R_MPD] = regs[R_CPD] & 0x7f; + tda18271_write_regs(fe, R_MPD, 1); + break; + } + + tda18271_write_regs(fe, R_TM, 7); + + /* force charge pump source */ + charge_pump_source(fe, 1); + + msleep(1); + + /* return pll to normal operation */ + charge_pump_source(fe, 0); + + msleep(20); + + /* set rfagc to normal speed mode */ + if (map->fm_rfn) + regs[R_EP3] &= ~0x04; + else + regs[R_EP3] |= 0x04; + tda18271_write_regs(fe, R_EP3, 1); + + return 0; +} + +static int tda18271_read_thermometer(struct dvb_frontend *fe) +{ + struct tda18271_priv *priv = fe->tuner_priv; + unsigned char *regs = priv->tda18271_regs; + int tm; + + /* switch thermometer on */ + regs[R_TM] |= 0x10; + tda18271_write_regs(fe, R_TM, 1); + + /* read thermometer info */ + tda18271_read_regs(fe); + + if ((((regs[R_TM] & 0x0f) == 0x00) && ((regs[R_TM] & 0x20) == 0x20)) || + (((regs[R_TM] & 0x0f) == 0x08) && ((regs[R_TM] & 0x20) == 0x00))) { + + if ((regs[R_TM] & 0x20) == 0x20) + regs[R_TM] &= ~0x20; + else + regs[R_TM] |= 0x20; + + tda18271_write_regs(fe, R_TM, 1); + + msleep(10); /* temperature sensing */ + + /* read thermometer info */ + tda18271_read_regs(fe); + } + + tm = tda18271_lookup_thermometer(fe); + + /* switch thermometer off */ + regs[R_TM] &= ~0x10; + tda18271_write_regs(fe, R_TM, 1); + + /* set CAL mode to normal */ + regs[R_EP4] &= ~0x03; + tda18271_write_regs(fe, R_EP4, 1); + + return tm; +} + +/* ------------------------------------------------------------------ */ + +static int tda18271c2_rf_tracking_filters_correction(struct dvb_frontend *fe, + u32 freq) +{ + struct tda18271_priv *priv = fe->tuner_priv; + struct tda18271_rf_tracking_filter_cal *map = priv->rf_cal_state; + unsigned char *regs = priv->tda18271_regs; + int tm_current, rfcal_comp, approx, i; + u8 dc_over_dt, rf_tab; + + /* power up */ + tda18271_set_standby_mode(fe, 0, 0, 0); + + /* read die current temperature */ + tm_current = tda18271_read_thermometer(fe); + + /* frequency dependent parameters */ + + tda18271_calc_rf_cal(fe, &freq); + rf_tab = regs[R_EB14]; + + i = tda18271_lookup_rf_band(fe, &freq, NULL); + if (i < 0) + return -EINVAL; + + if ((0 == map[i].rf3) || (freq / 1000 < map[i].rf2)) { + approx = map[i].rf_a1 * + (freq / 1000 - map[i].rf1) + map[i].rf_b1 + rf_tab; + } else { + approx = map[i].rf_a2 * + (freq / 1000 - map[i].rf2) + map[i].rf_b2 + rf_tab; + } + + if (approx < 0) + approx = 0; + if (approx > 255) + approx = 255; + + tda18271_lookup_map(fe, RF_CAL_DC_OVER_DT, &freq, &dc_over_dt); + + /* calculate temperature compensation */ + rfcal_comp = dc_over_dt * (tm_current - priv->tm_rfcal); + + regs[R_EB14] = approx + rfcal_comp; + tda18271_write_regs(fe, R_EB14, 1); + + return 0; +} + +static int tda18271_por(struct dvb_frontend *fe) +{ + struct tda18271_priv *priv = fe->tuner_priv; + unsigned char *regs = priv->tda18271_regs; + + /* power up detector 1 */ + regs[R_EB12] &= ~0x20; + tda18271_write_regs(fe, R_EB12, 1); + + regs[R_EB18] &= ~0x80; /* turn agc1 loop on */ + regs[R_EB18] &= ~0x03; /* set agc1_gain to 6 dB */ + tda18271_write_regs(fe, R_EB18, 1); + + regs[R_EB21] |= 0x03; /* set agc2_gain to -6 dB */ + + /* POR mode */ + tda18271_set_standby_mode(fe, 1, 0, 0); + + /* disable 1.5 MHz low pass filter */ + regs[R_EB23] &= ~0x04; /* forcelp_fc2_en = 0 */ + regs[R_EB23] &= ~0x02; /* XXX: lp_fc[2] = 0 */ + tda18271_write_regs(fe, R_EB21, 3); + + return 0; +} + +static int tda18271_calibrate_rf(struct dvb_frontend *fe, u32 freq) +{ + struct tda18271_priv *priv = fe->tuner_priv; + unsigned char *regs = priv->tda18271_regs; + u32 N; + + /* set CAL mode to normal */ + regs[R_EP4] &= ~0x03; + tda18271_write_regs(fe, R_EP4, 1); + + /* switch off agc1 */ + regs[R_EP3] |= 0x40; /* sm_lt = 1 */ + + regs[R_EB18] |= 0x03; /* set agc1_gain to 15 dB */ + tda18271_write_regs(fe, R_EB18, 1); + + /* frequency dependent parameters */ + + tda18271_calc_bp_filter(fe, &freq); + tda18271_calc_gain_taper(fe, &freq); + tda18271_calc_rf_band(fe, &freq); + tda18271_calc_km(fe, &freq); + + tda18271_write_regs(fe, R_EP1, 3); + tda18271_write_regs(fe, R_EB13, 1); + + /* main pll charge pump source */ + tda18271_charge_pump_source(fe, TDA18271_MAIN_PLL, 1); + + /* cal pll charge pump source */ + tda18271_charge_pump_source(fe, TDA18271_CAL_PLL, 1); + + /* force dcdc converter to 0 V */ + regs[R_EB14] = 0x00; + tda18271_write_regs(fe, R_EB14, 1); + + /* disable plls lock */ + regs[R_EB20] &= ~0x20; + tda18271_write_regs(fe, R_EB20, 1); + + /* set CAL mode to RF tracking filter calibration */ + regs[R_EP4] |= 0x03; + tda18271_write_regs(fe, R_EP4, 2); + + /* --------------------------------------------------------------- */ + + /* set the internal calibration signal */ + N = freq; + + tda18271_calc_cal_pll(fe, N); + tda18271_write_regs(fe, R_CPD, 4); + + /* downconvert internal calibration */ + N += 1000000; + + tda18271_calc_main_pll(fe, N); + tda18271_write_regs(fe, R_MPD, 4); + + msleep(5); + + tda18271_write_regs(fe, R_EP2, 1); + tda18271_write_regs(fe, R_EP1, 1); + tda18271_write_regs(fe, R_EP2, 1); + tda18271_write_regs(fe, R_EP1, 1); + + /* --------------------------------------------------------------- */ + + /* normal operation for the main pll */ + tda18271_charge_pump_source(fe, TDA18271_MAIN_PLL, 0); + + /* normal operation for the cal pll */ + tda18271_charge_pump_source(fe, TDA18271_CAL_PLL, 0); + + msleep(10); /* plls locking */ + + /* launch the rf tracking filters calibration */ + regs[R_EB20] |= 0x20; + tda18271_write_regs(fe, R_EB20, 1); + + msleep(60); /* calibration */ + + /* --------------------------------------------------------------- */ + + /* set CAL mode to normal */ + regs[R_EP4] &= ~0x03; + + /* switch on agc1 */ + regs[R_EP3] &= ~0x40; /* sm_lt = 0 */ + + regs[R_EB18] &= ~0x03; /* set agc1_gain to 6 dB */ + tda18271_write_regs(fe, R_EB18, 1); + + tda18271_write_regs(fe, R_EP3, 2); + + /* synchronization */ + tda18271_write_regs(fe, R_EP1, 1); + + /* get calibration result */ + tda18271_read_extended(fe); + + return regs[R_EB14]; +} + +static int tda18271_powerscan(struct dvb_frontend *fe, + u32 *freq_in, u32 *freq_out) +{ + struct tda18271_priv *priv = fe->tuner_priv; + unsigned char *regs = priv->tda18271_regs; + int sgn, bcal, count, wait; + u8 cid_target; + u16 count_limit; + u32 freq; + + freq = *freq_in; + + tda18271_calc_rf_band(fe, &freq); + tda18271_calc_rf_cal(fe, &freq); + tda18271_calc_gain_taper(fe, &freq); + tda18271_lookup_cid_target(fe, &freq, &cid_target, &count_limit); + + tda18271_write_regs(fe, R_EP2, 1); + tda18271_write_regs(fe, R_EB14, 1); + + /* downconvert frequency */ + freq += 1000000; + + tda18271_calc_main_pll(fe, freq); + tda18271_write_regs(fe, R_MPD, 4); + + msleep(5); /* pll locking */ + + /* detection mode */ + regs[R_EP4] &= ~0x03; + regs[R_EP4] |= 0x01; + tda18271_write_regs(fe, R_EP4, 1); + + /* launch power detection measurement */ + tda18271_write_regs(fe, R_EP2, 1); + + /* read power detection info, stored in EB10 */ + tda18271_read_extended(fe); + + /* algorithm initialization */ + sgn = 1; + *freq_out = *freq_in; + bcal = 0; + count = 0; + wait = false; + + while ((regs[R_EB10] & 0x3f) < cid_target) { + /* downconvert updated freq to 1 MHz */ + freq = *freq_in + (sgn * count) + 1000000; + + tda18271_calc_main_pll(fe, freq); + tda18271_write_regs(fe, R_MPD, 4); + + if (wait) { + msleep(5); /* pll locking */ + wait = false; + } else + udelay(100); /* pll locking */ + + /* launch power detection measurement */ + tda18271_write_regs(fe, R_EP2, 1); + + /* read power detection info, stored in EB10 */ + tda18271_read_extended(fe); + + count += 200; + + if (count <= count_limit) + continue; + + if (sgn <= 0) + break; + + sgn = -1 * sgn; + count = 200; + wait = true; + } + + if ((regs[R_EB10] & 0x3f) >= cid_target) { + bcal = 1; + *freq_out = freq - 1000000; + } else + bcal = 0; + + tda_cal("bcal = %d, freq_in = %d, freq_out = %d (freq = %d)\n", + bcal, *freq_in, *freq_out, freq); + + return bcal; +} + +static int tda18271_powerscan_init(struct dvb_frontend *fe) +{ + struct tda18271_priv *priv = fe->tuner_priv; + unsigned char *regs = priv->tda18271_regs; + + /* set standard to digital */ + regs[R_EP3] &= ~0x1f; /* clear std bits */ + regs[R_EP3] |= 0x12; + + /* set cal mode to normal */ + regs[R_EP4] &= ~0x03; + + /* update IF output level & IF notch frequency */ + regs[R_EP4] &= ~0x1c; /* clear if level bits */ + + tda18271_write_regs(fe, R_EP3, 2); + + regs[R_EB18] &= ~0x03; /* set agc1_gain to 6 dB */ + tda18271_write_regs(fe, R_EB18, 1); + + regs[R_EB21] &= ~0x03; /* set agc2_gain to -15 dB */ + + /* 1.5 MHz low pass filter */ + regs[R_EB23] |= 0x04; /* forcelp_fc2_en = 1 */ + regs[R_EB23] |= 0x02; /* lp_fc[2] = 1 */ + + tda18271_write_regs(fe, R_EB21, 3); + + return 0; +} + +static int tda18271_rf_tracking_filters_init(struct dvb_frontend *fe, u32 freq) +{ + struct tda18271_priv *priv = fe->tuner_priv; + struct tda18271_rf_tracking_filter_cal *map = priv->rf_cal_state; + unsigned char *regs = priv->tda18271_regs; + int bcal, rf, i; +#define RF1 0 +#define RF2 1 +#define RF3 2 + u32 rf_default[3]; + u32 rf_freq[3]; + u8 prog_cal[3]; + u8 prog_tab[3]; + + i = tda18271_lookup_rf_band(fe, &freq, NULL); + + if (i < 0) + return i; + + rf_default[RF1] = 1000 * map[i].rf1_def; + rf_default[RF2] = 1000 * map[i].rf2_def; + rf_default[RF3] = 1000 * map[i].rf3_def; + + for (rf = RF1; rf <= RF3; rf++) { + if (0 == rf_default[rf]) + return 0; + tda_cal("freq = %d, rf = %d\n", freq, rf); + + /* look for optimized calibration frequency */ + bcal = tda18271_powerscan(fe, &rf_default[rf], &rf_freq[rf]); + + tda18271_calc_rf_cal(fe, &rf_freq[rf]); + prog_tab[rf] = regs[R_EB14]; + + if (1 == bcal) + prog_cal[rf] = tda18271_calibrate_rf(fe, rf_freq[rf]); + else + prog_cal[rf] = prog_tab[rf]; + + switch (rf) { + case RF1: + map[i].rf_a1 = 0; + map[i].rf_b1 = prog_cal[RF1] - prog_tab[RF1]; + map[i].rf1 = rf_freq[RF1] / 1000; + break; + case RF2: + map[i].rf_a1 = (prog_cal[RF2] - prog_tab[RF2] - + prog_cal[RF1] + prog_tab[RF1]) / + ((rf_freq[RF2] - rf_freq[RF1]) / 1000); + map[i].rf2 = rf_freq[RF2] / 1000; + break; + case RF3: + map[i].rf_a2 = (prog_cal[RF3] - prog_tab[RF3] - + prog_cal[RF2] + prog_tab[RF2]) / + ((rf_freq[RF3] - rf_freq[RF2]) / 1000); + map[i].rf_b2 = prog_cal[RF2] - prog_tab[RF2]; + map[i].rf3 = rf_freq[RF3] / 1000; + break; + default: + BUG(); + } + } + + return 0; +} + +static int tda18271_calc_rf_filter_curve(struct dvb_frontend *fe) +{ + struct tda18271_priv *priv = fe->tuner_priv; + unsigned int i; + + tda_info("tda18271: performing RF tracking filter calibration\n"); + + /* wait for die temperature stabilization */ + msleep(200); + + tda18271_powerscan_init(fe); + + /* rf band calibration */ + for (i = 0; priv->rf_cal_state[i].rfmax != 0; i++) + tda18271_rf_tracking_filters_init(fe, 1000 * + priv->rf_cal_state[i].rfmax); + + priv->tm_rfcal = tda18271_read_thermometer(fe); + + return 0; +} + +/* ------------------------------------------------------------------ */ + +static int tda18271c2_rf_cal_init(struct dvb_frontend *fe) +{ + struct tda18271_priv *priv = fe->tuner_priv; + unsigned char *regs = priv->tda18271_regs; + + /* test RF_CAL_OK to see if we need init */ + if ((regs[R_EP1] & 0x10) == 0) + priv->cal_initialized = false; + + if (priv->cal_initialized) + return 0; + + tda18271_calc_rf_filter_curve(fe); + + tda18271_por(fe); + + tda_info("tda18271: RF tracking filter calibration complete\n"); + + priv->cal_initialized = true; + + return 0; +} + +static int tda18271c1_rf_tracking_filter_calibration(struct dvb_frontend *fe, + u32 freq, u32 bw) +{ + struct tda18271_priv *priv = fe->tuner_priv; + unsigned char *regs = priv->tda18271_regs; + u32 N = 0; + + /* calculate bp filter */ + tda18271_calc_bp_filter(fe, &freq); + tda18271_write_regs(fe, R_EP1, 1); + + regs[R_EB4] &= 0x07; + regs[R_EB4] |= 0x60; + tda18271_write_regs(fe, R_EB4, 1); + + regs[R_EB7] = 0x60; + tda18271_write_regs(fe, R_EB7, 1); + + regs[R_EB14] = 0x00; + tda18271_write_regs(fe, R_EB14, 1); + + regs[R_EB20] = 0xcc; + tda18271_write_regs(fe, R_EB20, 1); + + /* set cal mode to RF tracking filter calibration */ + regs[R_EP4] |= 0x03; + + /* calculate cal pll */ + + switch (priv->mode) { + case TDA18271_ANALOG: + N = freq - 1250000; + break; + case TDA18271_DIGITAL: + N = freq + bw / 2; + break; + } + + tda18271_calc_cal_pll(fe, N); + + /* calculate main pll */ + + switch (priv->mode) { + case TDA18271_ANALOG: + N = freq - 250000; + break; + case TDA18271_DIGITAL: + N = freq + bw / 2 + 1000000; + break; + } + + tda18271_calc_main_pll(fe, N); + + tda18271_write_regs(fe, R_EP3, 11); + msleep(5); /* RF tracking filter calibration initialization */ + + /* search for K,M,CO for RF calibration */ + tda18271_calc_km(fe, &freq); + tda18271_write_regs(fe, R_EB13, 1); + + /* search for rf band */ + tda18271_calc_rf_band(fe, &freq); + + /* search for gain taper */ + tda18271_calc_gain_taper(fe, &freq); + + tda18271_write_regs(fe, R_EP2, 1); + tda18271_write_regs(fe, R_EP1, 1); + tda18271_write_regs(fe, R_EP2, 1); + tda18271_write_regs(fe, R_EP1, 1); + + regs[R_EB4] &= 0x07; + regs[R_EB4] |= 0x40; + tda18271_write_regs(fe, R_EB4, 1); + + regs[R_EB7] = 0x40; + tda18271_write_regs(fe, R_EB7, 1); + msleep(10); /* pll locking */ + + regs[R_EB20] = 0xec; + tda18271_write_regs(fe, R_EB20, 1); + msleep(60); /* RF tracking filter calibration completion */ + + regs[R_EP4] &= ~0x03; /* set cal mode to normal */ + tda18271_write_regs(fe, R_EP4, 1); + + tda18271_write_regs(fe, R_EP1, 1); + + /* RF tracking filter correction for VHF_Low band */ + if (0 == tda18271_calc_rf_cal(fe, &freq)) + tda18271_write_regs(fe, R_EB14, 1); + + return 0; +} + +/* ------------------------------------------------------------------ */ + +static int tda18271_ir_cal_init(struct dvb_frontend *fe) +{ + struct tda18271_priv *priv = fe->tuner_priv; + unsigned char *regs = priv->tda18271_regs; + + tda18271_read_regs(fe); + + /* test IR_CAL_OK to see if we need init */ + if ((regs[R_EP1] & 0x08) == 0) + tda18271_init_regs(fe); + + return 0; +} + +static int tda18271_init(struct dvb_frontend *fe) +{ + struct tda18271_priv *priv = fe->tuner_priv; + + mutex_lock(&priv->lock); + + /* power up */ + tda18271_set_standby_mode(fe, 0, 0, 0); + + /* initialization */ + tda18271_ir_cal_init(fe); + + if (priv->id == TDA18271HDC2) + tda18271c2_rf_cal_init(fe); + + mutex_unlock(&priv->lock); + + return 0; +} + +static int tda18271_tune(struct dvb_frontend *fe, + struct tda18271_std_map_item *map, u32 freq, u32 bw) +{ + struct tda18271_priv *priv = fe->tuner_priv; + + tda_dbg("freq = %d, ifc = %d, bw = %d, agc_mode = %d, std = %d\n", + freq, map->if_freq, bw, map->agc_mode, map->std); + + tda18271_init(fe); + + mutex_lock(&priv->lock); + + switch (priv->id) { + case TDA18271HDC1: + tda18271c1_rf_tracking_filter_calibration(fe, freq, bw); + break; + case TDA18271HDC2: + tda18271c2_rf_tracking_filters_correction(fe, freq); + break; + } + tda18271_channel_configuration(fe, map, freq, bw); + + mutex_unlock(&priv->lock); + + return 0; +} + +/* ------------------------------------------------------------------ */ + +static int tda18271_set_params(struct dvb_frontend *fe, + struct dvb_frontend_parameters *params) +{ + struct tda18271_priv *priv = fe->tuner_priv; + struct tda18271_std_map *std_map = &priv->std; + struct tda18271_std_map_item *map; + int ret; + u32 bw, freq = params->frequency; + + priv->mode = TDA18271_DIGITAL; + + if (fe->ops.info.type == FE_ATSC) { + switch (params->u.vsb.modulation) { + case VSB_8: + case VSB_16: + map = &std_map->atsc_6; + break; + case QAM_64: + case QAM_256: + map = &std_map->qam_6; + break; + default: + tda_warn("modulation not set!\n"); + return -EINVAL; + } +#if 0 /* keep */ + /* userspace request is already center adjusted */ + freq += 1750000; /* Adjust to center (+1.75MHZ) */ +#endif + bw = 6000000; + } else if (fe->ops.info.type == FE_OFDM) { + switch (params->u.ofdm.bandwidth) { + case BANDWIDTH_6_MHZ: + bw = 6000000; + map = &std_map->dvbt_6; + break; + case BANDWIDTH_7_MHZ: + bw = 7000000; + map = &std_map->dvbt_7; + break; + case BANDWIDTH_8_MHZ: + bw = 8000000; + map = &std_map->dvbt_8; + break; + default: + tda_warn("bandwidth not set!\n"); + return -EINVAL; + } + } else { + tda_warn("modulation type not supported!\n"); + return -EINVAL; + } + + /* When tuning digital, the analog demod must be tri-stated */ + if (fe->ops.analog_ops.standby) + fe->ops.analog_ops.standby(fe); + + ret = tda18271_tune(fe, map, freq, bw); + + if (ret < 0) + goto fail; + + priv->frequency = freq; + priv->bandwidth = (fe->ops.info.type == FE_OFDM) ? + params->u.ofdm.bandwidth : 0; +fail: + return ret; +} + +static int tda18271_set_analog_params(struct dvb_frontend *fe, + struct analog_parameters *params) +{ + struct tda18271_priv *priv = fe->tuner_priv; + struct tda18271_std_map *std_map = &priv->std; + struct tda18271_std_map_item *map; + char *mode; + int ret; + u32 freq = params->frequency * 62500; + + priv->mode = TDA18271_ANALOG; + + if (params->mode == V4L2_TUNER_RADIO) { + freq = freq / 1000; + map = &std_map->fm_radio; + mode = "fm"; + } else if (params->std & V4L2_STD_MN) { + map = &std_map->atv_mn; + mode = "MN"; + } else if (params->std & V4L2_STD_B) { + map = &std_map->atv_b; + mode = "B"; + } else if (params->std & V4L2_STD_GH) { + map = &std_map->atv_gh; + mode = "GH"; + } else if (params->std & V4L2_STD_PAL_I) { + map = &std_map->atv_i; + mode = "I"; + } else if (params->std & V4L2_STD_DK) { + map = &std_map->atv_dk; + mode = "DK"; + } else if (params->std & V4L2_STD_SECAM_L) { + map = &std_map->atv_l; + mode = "L"; + } else if (params->std & V4L2_STD_SECAM_LC) { + map = &std_map->atv_lc; + mode = "L'"; + } else { + map = &std_map->atv_i; + mode = "xx"; + } + + tda_dbg("setting tda18271 to system %s\n", mode); + + ret = tda18271_tune(fe, map, freq, 0); + + if (ret < 0) + goto fail; + + priv->frequency = freq; + priv->bandwidth = 0; +fail: + return ret; +} + +static int tda18271_sleep(struct dvb_frontend *fe) +{ + struct tda18271_priv *priv = fe->tuner_priv; + + mutex_lock(&priv->lock); + + /* standby mode w/ slave tuner output + * & loop thru & xtal oscillator on */ + tda18271_set_standby_mode(fe, 1, 0, 0); + + mutex_unlock(&priv->lock); + + return 0; +} + +static int tda18271_release(struct dvb_frontend *fe) +{ + struct tda18271_priv *priv = fe->tuner_priv; + + mutex_lock(&tda18271_list_mutex); + + if (priv) + hybrid_tuner_release_state(priv); + + mutex_unlock(&tda18271_list_mutex); + + fe->tuner_priv = NULL; + + return 0; +} + +static int tda18271_get_frequency(struct dvb_frontend *fe, u32 *frequency) +{ + struct tda18271_priv *priv = fe->tuner_priv; + *frequency = priv->frequency; + return 0; +} + +static int tda18271_get_bandwidth(struct dvb_frontend *fe, u32 *bandwidth) +{ + struct tda18271_priv *priv = fe->tuner_priv; + *bandwidth = priv->bandwidth; + return 0; +} + +/* ------------------------------------------------------------------ */ + +#define tda18271_update_std(std_cfg, name) do { \ + if (map->std_cfg.if_freq + \ + map->std_cfg.agc_mode + map->std_cfg.std + \ + map->std_cfg.if_lvl + map->std_cfg.rfagc_top > 0) { \ + tda_dbg("Using custom std config for %s\n", name); \ + memcpy(&std->std_cfg, &map->std_cfg, \ + sizeof(struct tda18271_std_map_item)); \ + } } while (0) + +#define tda18271_dump_std_item(std_cfg, name) do { \ + tda_dbg("(%s) if_freq = %d, agc_mode = %d, std = %d, " \ + "if_lvl = %d, rfagc_top = 0x%02x\n", \ + name, std->std_cfg.if_freq, \ + std->std_cfg.agc_mode, std->std_cfg.std, \ + std->std_cfg.if_lvl, std->std_cfg.rfagc_top); \ + } while (0) + +static int tda18271_dump_std_map(struct dvb_frontend *fe) +{ + struct tda18271_priv *priv = fe->tuner_priv; + struct tda18271_std_map *std = &priv->std; + + tda_dbg("========== STANDARD MAP SETTINGS ==========\n"); + tda18271_dump_std_item(fm_radio, " fm "); + tda18271_dump_std_item(atv_b, "atv b "); + tda18271_dump_std_item(atv_dk, "atv dk"); + tda18271_dump_std_item(atv_gh, "atv gh"); + tda18271_dump_std_item(atv_i, "atv i "); + tda18271_dump_std_item(atv_l, "atv l "); + tda18271_dump_std_item(atv_lc, "atv l'"); + tda18271_dump_std_item(atv_mn, "atv mn"); + tda18271_dump_std_item(atsc_6, "atsc 6"); + tda18271_dump_std_item(dvbt_6, "dvbt 6"); + tda18271_dump_std_item(dvbt_7, "dvbt 7"); + tda18271_dump_std_item(dvbt_8, "dvbt 8"); + tda18271_dump_std_item(qam_6, "qam 6 "); + tda18271_dump_std_item(qam_8, "qam 8 "); + + return 0; +} + +static int tda18271_update_std_map(struct dvb_frontend *fe, + struct tda18271_std_map *map) +{ + struct tda18271_priv *priv = fe->tuner_priv; + struct tda18271_std_map *std = &priv->std; + + if (!map) + return -EINVAL; + + tda18271_update_std(fm_radio, "fm"); + tda18271_update_std(atv_b, "atv b"); + tda18271_update_std(atv_dk, "atv dk"); + tda18271_update_std(atv_gh, "atv gh"); + tda18271_update_std(atv_i, "atv i"); + tda18271_update_std(atv_l, "atv l"); + tda18271_update_std(atv_lc, "atv l'"); + tda18271_update_std(atv_mn, "atv mn"); + tda18271_update_std(atsc_6, "atsc 6"); + tda18271_update_std(dvbt_6, "dvbt 6"); + tda18271_update_std(dvbt_7, "dvbt 7"); + tda18271_update_std(dvbt_8, "dvbt 8"); + tda18271_update_std(qam_6, "qam 6"); + tda18271_update_std(qam_8, "qam 8"); + + return 0; +} + +static int tda18271_get_id(struct dvb_frontend *fe) +{ + struct tda18271_priv *priv = fe->tuner_priv; + unsigned char *regs = priv->tda18271_regs; + char *name; + int ret = 0; + + mutex_lock(&priv->lock); + tda18271_read_regs(fe); + mutex_unlock(&priv->lock); + + switch (regs[R_ID] & 0x7f) { + case 3: + name = "TDA18271HD/C1"; + priv->id = TDA18271HDC1; + break; + case 4: + name = "TDA18271HD/C2"; + priv->id = TDA18271HDC2; + break; + default: + name = "Unknown device"; + ret = -EINVAL; + break; + } + + tda_info("%s detected @ %d-%04x%s\n", name, + i2c_adapter_id(priv->i2c_props.adap), + priv->i2c_props.addr, + (0 == ret) ? "" : ", device not supported."); + + return ret; +} + +static struct dvb_tuner_ops tda18271_tuner_ops = { + .info = { + .name = "NXP TDA18271HD", + .frequency_min = 45000000, + .frequency_max = 864000000, + .frequency_step = 62500 + }, + .init = tda18271_init, + .sleep = tda18271_sleep, + .set_params = tda18271_set_params, + .set_analog_params = tda18271_set_analog_params, + .release = tda18271_release, + .get_frequency = tda18271_get_frequency, + .get_bandwidth = tda18271_get_bandwidth, +}; + +struct dvb_frontend *tda18271_attach(struct dvb_frontend *fe, u8 addr, + struct i2c_adapter *i2c, + struct tda18271_config *cfg) +{ + struct tda18271_priv *priv = NULL; + int instance; + + mutex_lock(&tda18271_list_mutex); + + instance = hybrid_tuner_request_state(struct tda18271_priv, priv, + hybrid_tuner_instance_list, + i2c, addr, "tda18271"); + switch (instance) { + case 0: + goto fail; + break; + case 1: + /* new tuner instance */ + priv->gate = (cfg) ? cfg->gate : TDA18271_GATE_AUTO; + priv->role = (cfg) ? cfg->role : TDA18271_MASTER; + priv->cal_initialized = false; + mutex_init(&priv->lock); + + fe->tuner_priv = priv; + + if (cfg) + priv->small_i2c = cfg->small_i2c; + + if (tda18271_get_id(fe) < 0) + goto fail; + + if (tda18271_assign_map_layout(fe) < 0) + goto fail; + + mutex_lock(&priv->lock); + tda18271_init_regs(fe); + + if ((tda18271_cal_on_startup) && (priv->id == TDA18271HDC2)) + tda18271c2_rf_cal_init(fe); + + mutex_unlock(&priv->lock); + break; + default: + /* existing tuner instance */ + fe->tuner_priv = priv; + + /* allow dvb driver to override i2c gate setting */ + if ((cfg) && (cfg->gate != TDA18271_GATE_ANALOG)) + priv->gate = cfg->gate; + break; + } + + /* override default std map with values in config struct */ + if ((cfg) && (cfg->std_map)) + tda18271_update_std_map(fe, cfg->std_map); + + mutex_unlock(&tda18271_list_mutex); + + memcpy(&fe->ops.tuner_ops, &tda18271_tuner_ops, + sizeof(struct dvb_tuner_ops)); + + if (tda18271_debug & (DBG_MAP | DBG_ADV)) + tda18271_dump_std_map(fe); + + return fe; +fail: + mutex_unlock(&tda18271_list_mutex); + + tda18271_release(fe); + return NULL; +} +EXPORT_SYMBOL_GPL(tda18271_attach); +MODULE_DESCRIPTION("NXP TDA18271HD analog / digital tuner driver"); +MODULE_AUTHOR("Michael Krufky "); +MODULE_LICENSE("GPL"); +MODULE_VERSION("0.3"); + +/* + * Overrides for Emacs so that we follow Linus's tabbing style. + * --------------------------------------------------------------------------- + * Local variables: + * c-basic-offset: 8 + * End: + */ diff --git a/linux/drivers/media/common/tuners/tda18271-maps.c b/linux/drivers/media/common/tuners/tda18271-maps.c new file mode 100644 index 000000000..83e756196 --- /dev/null +++ b/linux/drivers/media/common/tuners/tda18271-maps.c @@ -0,0 +1,1313 @@ +/* + tda18271-tables.c - driver for the Philips / NXP TDA18271 silicon tuner + + Copyright (C) 2007, 2008 Michael Krufky + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. +*/ + +#include "tda18271-priv.h" + +struct tda18271_pll_map { + u32 lomax; + u8 pd; /* post div */ + u8 d; /* div */ +}; + +struct tda18271_map { + u32 rfmax; + u8 val; +}; + +/*---------------------------------------------------------------------*/ + +static struct tda18271_pll_map tda18271c1_main_pll[] = { + { .lomax = 32000, .pd = 0x5f, .d = 0xf0 }, + { .lomax = 35000, .pd = 0x5e, .d = 0xe0 }, + { .lomax = 37000, .pd = 0x5d, .d = 0xd0 }, + { .lomax = 41000, .pd = 0x5c, .d = 0xc0 }, + { .lomax = 44000, .pd = 0x5b, .d = 0xb0 }, + { .lomax = 49000, .pd = 0x5a, .d = 0xa0 }, + { .lomax = 54000, .pd = 0x59, .d = 0x90 }, + { .lomax = 61000, .pd = 0x58, .d = 0x80 }, + { .lomax = 65000, .pd = 0x4f, .d = 0x78 }, + { .lomax = 70000, .pd = 0x4e, .d = 0x70 }, + { .lomax = 75000, .pd = 0x4d, .d = 0x68 }, + { .lomax = 82000, .pd = 0x4c, .d = 0x60 }, + { .lomax = 89000, .pd = 0x4b, .d = 0x58 }, + { .lomax = 98000, .pd = 0x4a, .d = 0x50 }, + { .lomax = 109000, .pd = 0x49, .d = 0x48 }, + { .lomax = 123000, .pd = 0x48, .d = 0x40 }, + { .lomax = 131000, .pd = 0x3f, .d = 0x3c }, + { .lomax = 141000, .pd = 0x3e, .d = 0x38 }, + { .lomax = 151000, .pd = 0x3d, .d = 0x34 }, + { .lomax = 164000, .pd = 0x3c, .d = 0x30 }, + { .lomax = 179000, .pd = 0x3b, .d = 0x2c }, + { .lomax = 197000, .pd = 0x3a, .d = 0x28 }, + { .lomax = 219000, .pd = 0x39, .d = 0x24 }, + { .lomax = 246000, .pd = 0x38, .d = 0x20 }, + { .lomax = 263000, .pd = 0x2f, .d = 0x1e }, + { .lomax = 282000, .pd = 0x2e, .d = 0x1c }, + { .lomax = 303000, .pd = 0x2d, .d = 0x1a }, + { .lomax = 329000, .pd = 0x2c, .d = 0x18 }, + { .lomax = 359000, .pd = 0x2b, .d = 0x16 }, + { .lomax = 395000, .pd = 0x2a, .d = 0x14 }, + { .lomax = 438000, .pd = 0x29, .d = 0x12 }, + { .lomax = 493000, .pd = 0x28, .d = 0x10 }, + { .lomax = 526000, .pd = 0x1f, .d = 0x0f }, + { .lomax = 564000, .pd = 0x1e, .d = 0x0e }, + { .lomax = 607000, .pd = 0x1d, .d = 0x0d }, + { .lomax = 658000, .pd = 0x1c, .d = 0x0c }, + { .lomax = 718000, .pd = 0x1b, .d = 0x0b }, + { .lomax = 790000, .pd = 0x1a, .d = 0x0a }, + { .lomax = 877000, .pd = 0x19, .d = 0x09 }, + { .lomax = 987000, .pd = 0x18, .d = 0x08 }, + { .lomax = 0, .pd = 0x00, .d = 0x00 }, /* end */ +}; + +static struct tda18271_pll_map tda18271c2_main_pll[] = { + { .lomax = 33125, .pd = 0x57, .d = 0xf0 }, + { .lomax = 35500, .pd = 0x56, .d = 0xe0 }, + { .lomax = 38188, .pd = 0x55, .d = 0xd0 }, + { .lomax = 41375, .pd = 0x54, .d = 0xc0 }, + { .lomax = 45125, .pd = 0x53, .d = 0xb0 }, + { .lomax = 49688, .pd = 0x52, .d = 0xa0 }, + { .lomax = 55188, .pd = 0x51, .d = 0x90 }, + { .lomax = 62125, .pd = 0x50, .d = 0x80 }, + { .lomax = 66250, .pd = 0x47, .d = 0x78 }, + { .lomax = 71000, .pd = 0x46, .d = 0x70 }, + { .lomax = 76375, .pd = 0x45, .d = 0x68 }, + { .lomax = 82750, .pd = 0x44, .d = 0x60 }, + { .lomax = 90250, .pd = 0x43, .d = 0x58 }, + { .lomax = 99375, .pd = 0x42, .d = 0x50 }, + { .lomax = 110375, .pd = 0x41, .d = 0x48 }, + { .lomax = 124250, .pd = 0x40, .d = 0x40 }, + { .lomax = 132500, .pd = 0x37, .d = 0x3c }, + { .lomax = 142000, .pd = 0x36, .d = 0x38 }, + { .lomax = 152750, .pd = 0x35, .d = 0x34 }, + { .lomax = 165500, .pd = 0x34, .d = 0x30 }, + { .lomax = 180500, .pd = 0x33, .d = 0x2c }, + { .lomax = 198750, .pd = 0x32, .d = 0x28 }, + { .lomax = 220750, .pd = 0x31, .d = 0x24 }, + { .lomax = 248500, .pd = 0x30, .d = 0x20 }, + { .lomax = 265000, .pd = 0x27, .d = 0x1e }, + { .lomax = 284000, .pd = 0x26, .d = 0x1c }, + { .lomax = 305500, .pd = 0x25, .d = 0x1a }, + { .lomax = 331000, .pd = 0x24, .d = 0x18 }, + { .lomax = 361000, .pd = 0x23, .d = 0x16 }, + { .lomax = 397500, .pd = 0x22, .d = 0x14 }, + { .lomax = 441500, .pd = 0x21, .d = 0x12 }, + { .lomax = 497000, .pd = 0x20, .d = 0x10 }, + { .lomax = 530000, .pd = 0x17, .d = 0x0f }, + { .lomax = 568000, .pd = 0x16, .d = 0x0e }, + { .lomax = 611000, .pd = 0x15, .d = 0x0d }, + { .lomax = 662000, .pd = 0x14, .d = 0x0c }, + { .lomax = 722000, .pd = 0x13, .d = 0x0b }, + { .lomax = 795000, .pd = 0x12, .d = 0x0a }, + { .lomax = 883000, .pd = 0x11, .d = 0x09 }, + { .lomax = 994000, .pd = 0x10, .d = 0x08 }, + { .lomax = 0, .pd = 0x00, .d = 0x00 }, /* end */ +}; + +static struct tda18271_pll_map tda18271c1_cal_pll[] = { + { .lomax = 33000, .pd = 0xdd, .d = 0xd0 }, + { .lomax = 36000, .pd = 0xdc, .d = 0xc0 }, + { .lomax = 40000, .pd = 0xdb, .d = 0xb0 }, + { .lomax = 44000, .pd = 0xda, .d = 0xa0 }, + { .lomax = 49000, .pd = 0xd9, .d = 0x90 }, + { .lomax = 55000, .pd = 0xd8, .d = 0x80 }, + { .lomax = 63000, .pd = 0xd3, .d = 0x70 }, + { .lomax = 67000, .pd = 0xcd, .d = 0x68 }, + { .lomax = 73000, .pd = 0xcc, .d = 0x60 }, + { .lomax = 80000, .pd = 0xcb, .d = 0x58 }, + { .lomax = 88000, .pd = 0xca, .d = 0x50 }, + { .lomax = 98000, .pd = 0xc9, .d = 0x48 }, + { .lomax = 110000, .pd = 0xc8, .d = 0x40 }, + { .lomax = 126000, .pd = 0xc3, .d = 0x38 }, + { .lomax = 135000, .pd = 0xbd, .d = 0x34 }, + { .lomax = 147000, .pd = 0xbc, .d = 0x30 }, + { .lomax = 160000, .pd = 0xbb, .d = 0x2c }, + { .lomax = 176000, .pd = 0xba, .d = 0x28 }, + { .lomax = 196000, .pd = 0xb9, .d = 0x24 }, + { .lomax = 220000, .pd = 0xb8, .d = 0x20 }, + { .lomax = 252000, .pd = 0xb3, .d = 0x1c }, + { .lomax = 271000, .pd = 0xad, .d = 0x1a }, + { .lomax = 294000, .pd = 0xac, .d = 0x18 }, + { .lomax = 321000, .pd = 0xab, .d = 0x16 }, + { .lomax = 353000, .pd = 0xaa, .d = 0x14 }, + { .lomax = 392000, .pd = 0xa9, .d = 0x12 }, + { .lomax = 441000, .pd = 0xa8, .d = 0x10 }, + { .lomax = 505000, .pd = 0xa3, .d = 0x0e }, + { .lomax = 543000, .pd = 0x9d, .d = 0x0d }, + { .lomax = 589000, .pd = 0x9c, .d = 0x0c }, + { .lomax = 642000, .pd = 0x9b, .d = 0x0b }, + { .lomax = 707000, .pd = 0x9a, .d = 0x0a }, + { .lomax = 785000, .pd = 0x99, .d = 0x09 }, + { .lomax = 883000, .pd = 0x98, .d = 0x08 }, + { .lomax = 1010000, .pd = 0x93, .d = 0x07 }, + { .lomax = 0, .pd = 0x00, .d = 0x00 }, /* end */ +}; + +static struct tda18271_pll_map tda18271c2_cal_pll[] = { + { .lomax = 33813, .pd = 0xdd, .d = 0xd0 }, + { .lomax = 36625, .pd = 0xdc, .d = 0xc0 }, + { .lomax = 39938, .pd = 0xdb, .d = 0xb0 }, + { .lomax = 43938, .pd = 0xda, .d = 0xa0 }, + { .lomax = 48813, .pd = 0xd9, .d = 0x90 }, + { .lomax = 54938, .pd = 0xd8, .d = 0x80 }, + { .lomax = 62813, .pd = 0xd3, .d = 0x70 }, + { .lomax = 67625, .pd = 0xcd, .d = 0x68 }, + { .lomax = 73250, .pd = 0xcc, .d = 0x60 }, + { .lomax = 79875, .pd = 0xcb, .d = 0x58 }, + { .lomax = 87875, .pd = 0xca, .d = 0x50 }, + { .lomax = 97625, .pd = 0xc9, .d = 0x48 }, + { .lomax = 109875, .pd = 0xc8, .d = 0x40 }, + { .lomax = 125625, .pd = 0xc3, .d = 0x38 }, + { .lomax = 135250, .pd = 0xbd, .d = 0x34 }, + { .lomax = 146500, .pd = 0xbc, .d = 0x30 }, + { .lomax = 159750, .pd = 0xbb, .d = 0x2c }, + { .lomax = 175750, .pd = 0xba, .d = 0x28 }, + { .lomax = 195250, .pd = 0xb9, .d = 0x24 }, + { .lomax = 219750, .pd = 0xb8, .d = 0x20 }, + { .lomax = 251250, .pd = 0xb3, .d = 0x1c }, + { .lomax = 270500, .pd = 0xad, .d = 0x1a }, + { .lomax = 293000, .pd = 0xac, .d = 0x18 }, + { .lomax = 319500, .pd = 0xab, .d = 0x16 }, + { .lomax = 351500, .pd = 0xaa, .d = 0x14 }, + { .lomax = 390500, .pd = 0xa9, .d = 0x12 }, + { .lomax = 439500, .pd = 0xa8, .d = 0x10 }, + { .lomax = 502500, .pd = 0xa3, .d = 0x0e }, + { .lomax = 541000, .pd = 0x9d, .d = 0x0d }, + { .lomax = 586000, .pd = 0x9c, .d = 0x0c }, + { .lomax = 639000, .pd = 0x9b, .d = 0x0b }, + { .lomax = 703000, .pd = 0x9a, .d = 0x0a }, + { .lomax = 781000, .pd = 0x99, .d = 0x09 }, + { .lomax = 879000, .pd = 0x98, .d = 0x08 }, + { .lomax = 0, .pd = 0x00, .d = 0x00 }, /* end */ +}; + +static struct tda18271_map tda18271_bp_filter[] = { + { .rfmax = 62000, .val = 0x00 }, + { .rfmax = 84000, .val = 0x01 }, + { .rfmax = 100000, .val = 0x02 }, + { .rfmax = 140000, .val = 0x03 }, + { .rfmax = 170000, .val = 0x04 }, + { .rfmax = 180000, .val = 0x05 }, + { .rfmax = 865000, .val = 0x06 }, + { .rfmax = 0, .val = 0x00 }, /* end */ +}; + +static struct tda18271_map tda18271c1_km[] = { + { .rfmax = 61100, .val = 0x74 }, + { .rfmax = 350000, .val = 0x40 }, + { .rfmax = 720000, .val = 0x30 }, + { .rfmax = 865000, .val = 0x40 }, + { .rfmax = 0, .val = 0x00 }, /* end */ +}; + +static struct tda18271_map tda18271c2_km[] = { + { .rfmax = 47900, .val = 0x38 }, + { .rfmax = 61100, .val = 0x44 }, + { .rfmax = 350000, .val = 0x30 }, + { .rfmax = 720000, .val = 0x24 }, + { .rfmax = 865000, .val = 0x3c }, + { .rfmax = 0, .val = 0x00 }, /* end */ +}; + +static struct tda18271_map tda18271_rf_band[] = { + { .rfmax = 47900, .val = 0x00 }, + { .rfmax = 61100, .val = 0x01 }, +/* { .rfmax = 152600, .val = 0x02 }, */ + { .rfmax = 121200, .val = 0x02 }, + { .rfmax = 164700, .val = 0x03 }, + { .rfmax = 203500, .val = 0x04 }, + { .rfmax = 457800, .val = 0x05 }, + { .rfmax = 865000, .val = 0x06 }, + { .rfmax = 0, .val = 0x00 }, /* end */ +}; + +static struct tda18271_map tda18271_gain_taper[] = { + { .rfmax = 45400, .val = 0x1f }, + { .rfmax = 45800, .val = 0x1e }, + { .rfmax = 46200, .val = 0x1d }, + { .rfmax = 46700, .val = 0x1c }, + { .rfmax = 47100, .val = 0x1b }, + { .rfmax = 47500, .val = 0x1a }, + { .rfmax = 47900, .val = 0x19 }, + { .rfmax = 49600, .val = 0x17 }, + { .rfmax = 51200, .val = 0x16 }, + { .rfmax = 52900, .val = 0x15 }, + { .rfmax = 54500, .val = 0x14 }, + { .rfmax = 56200, .val = 0x13 }, + { .rfmax = 57800, .val = 0x12 }, + { .rfmax = 59500, .val = 0x11 }, + { .rfmax = 61100, .val = 0x10 }, + { .rfmax = 67600, .val = 0x0d }, + { .rfmax = 74200, .val = 0x0c }, + { .rfmax = 80700, .val = 0x0b }, + { .rfmax = 87200, .val = 0x0a }, + { .rfmax = 93800, .val = 0x09 }, + { .rfmax = 100300, .val = 0x08 }, + { .rfmax = 106900, .val = 0x07 }, + { .rfmax = 113400, .val = 0x06 }, + { .rfmax = 119900, .val = 0x05 }, + { .rfmax = 126500, .val = 0x04 }, + { .rfmax = 133000, .val = 0x03 }, + { .rfmax = 139500, .val = 0x02 }, + { .rfmax = 146100, .val = 0x01 }, + { .rfmax = 152600, .val = 0x00 }, + { .rfmax = 154300, .val = 0x1f }, + { .rfmax = 156100, .val = 0x1e }, + { .rfmax = 157800, .val = 0x1d }, + { .rfmax = 159500, .val = 0x1c }, + { .rfmax = 161200, .val = 0x1b }, + { .rfmax = 163000, .val = 0x1a }, + { .rfmax = 164700, .val = 0x19 }, + { .rfmax = 170200, .val = 0x17 }, + { .rfmax = 175800, .val = 0x16 }, + { .rfmax = 181300, .val = 0x15 }, + { .rfmax = 186900, .val = 0x14 }, + { .rfmax = 192400, .val = 0x13 }, + { .rfmax = 198000, .val = 0x12 }, + { .rfmax = 203500, .val = 0x11 }, + { .rfmax = 216200, .val = 0x14 }, + { .rfmax = 228900, .val = 0x13 }, + { .rfmax = 241600, .val = 0x12 }, + { .rfmax = 254400, .val = 0x11 }, + { .rfmax = 267100, .val = 0x10 }, + { .rfmax = 279800, .val = 0x0f }, + { .rfmax = 292500, .val = 0x0e }, + { .rfmax = 305200, .val = 0x0d }, + { .rfmax = 317900, .val = 0x0c }, + { .rfmax = 330700, .val = 0x0b }, + { .rfmax = 343400, .val = 0x0a }, + { .rfmax = 356100, .val = 0x09 }, + { .rfmax = 368800, .val = 0x08 }, + { .rfmax = 381500, .val = 0x07 }, + { .rfmax = 394200, .val = 0x06 }, + { .rfmax = 406900, .val = 0x05 }, + { .rfmax = 419700, .val = 0x04 }, + { .rfmax = 432400, .val = 0x03 }, + { .rfmax = 445100, .val = 0x02 }, + { .rfmax = 457800, .val = 0x01 }, + { .rfmax = 476300, .val = 0x19 }, + { .rfmax = 494800, .val = 0x18 }, + { .rfmax = 513300, .val = 0x17 }, + { .rfmax = 531800, .val = 0x16 }, + { .rfmax = 550300, .val = 0x15 }, + { .rfmax = 568900, .val = 0x14 }, + { .rfmax = 587400, .val = 0x13 }, + { .rfmax = 605900, .val = 0x12 }, + { .rfmax = 624400, .val = 0x11 }, + { .rfmax = 642900, .val = 0x10 }, + { .rfmax = 661400, .val = 0x0f }, + { .rfmax = 679900, .val = 0x0e }, + { .rfmax = 698400, .val = 0x0d }, + { .rfmax = 716900, .val = 0x0c }, + { .rfmax = 735400, .val = 0x0b }, + { .rfmax = 753900, .val = 0x0a }, + { .rfmax = 772500, .val = 0x09 }, + { .rfmax = 791000, .val = 0x08 }, + { .rfmax = 809500, .val = 0x07 }, + { .rfmax = 828000, .val = 0x06 }, + { .rfmax = 846500, .val = 0x05 }, + { .rfmax = 865000, .val = 0x04 }, + { .rfmax = 0, .val = 0x00 }, /* end */ +}; + +static struct tda18271_map tda18271c1_rf_cal[] = { + { .rfmax = 41000, .val = 0x1e }, + { .rfmax = 43000, .val = 0x30 }, + { .rfmax = 45000, .val = 0x43 }, + { .rfmax = 46000, .val = 0x4d }, + { .rfmax = 47000, .val = 0x54 }, + { .rfmax = 47900, .val = 0x64 }, + { .rfmax = 49100, .val = 0x20 }, + { .rfmax = 50000, .val = 0x22 }, + { .rfmax = 51000, .val = 0x2a }, + { .rfmax = 53000, .val = 0x32 }, + { .rfmax = 55000, .val = 0x35 }, + { .rfmax = 56000, .val = 0x3c }, + { .rfmax = 57000, .val = 0x3f }, + { .rfmax = 58000, .val = 0x48 }, + { .rfmax = 59000, .val = 0x4d }, + { .rfmax = 60000, .val = 0x58 }, + { .rfmax = 61100, .val = 0x5f }, + { .rfmax = 0, .val = 0x00 }, /* end */ +}; + +static struct tda18271_map tda18271c2_rf_cal[] = { + { .rfmax = 41000, .val = 0x0f }, + { .rfmax = 43000, .val = 0x1c }, + { .rfmax = 45000, .val = 0x2f }, + { .rfmax = 46000, .val = 0x39 }, + { .rfmax = 47000, .val = 0x40 }, + { .rfmax = 47900, .val = 0x50 }, + { .rfmax = 49100, .val = 0x16 }, + { .rfmax = 50000, .val = 0x18 }, + { .rfmax = 51000, .val = 0x20 }, + { .rfmax = 53000, .val = 0x28 }, + { .rfmax = 55000, .val = 0x2b }, + { .rfmax = 56000, .val = 0x32 }, + { .rfmax = 57000, .val = 0x35 }, + { .rfmax = 58000, .val = 0x3e }, + { .rfmax = 59000, .val = 0x43 }, + { .rfmax = 60000, .val = 0x4e }, + { .rfmax = 61100, .val = 0x55 }, + { .rfmax = 63000, .val = 0x0f }, + { .rfmax = 64000, .val = 0x11 }, + { .rfmax = 65000, .val = 0x12 }, + { .rfmax = 66000, .val = 0x15 }, + { .rfmax = 67000, .val = 0x16 }, + { .rfmax = 68000, .val = 0x17 }, + { .rfmax = 70000, .val = 0x19 }, + { .rfmax = 71000, .val = 0x1c }, + { .rfmax = 72000, .val = 0x1d }, + { .rfmax = 73000, .val = 0x1f }, + { .rfmax = 74000, .val = 0x20 }, + { .rfmax = 75000, .val = 0x21 }, + { .rfmax = 76000, .val = 0x24 }, + { .rfmax = 77000, .val = 0x25 }, + { .rfmax = 78000, .val = 0x27 }, + { .rfmax = 80000, .val = 0x28 }, + { .rfmax = 81000, .val = 0x29 }, + { .rfmax = 82000, .val = 0x2d }, + { .rfmax = 83000, .val = 0x2e }, + { .rfmax = 84000, .val = 0x2f }, + { .rfmax = 85000, .val = 0x31 }, + { .rfmax = 86000, .val = 0x33 }, + { .rfmax = 87000, .val = 0x34 }, + { .rfmax = 88000, .val = 0x35 }, + { .rfmax = 89000, .val = 0x37 }, + { .rfmax = 90000, .val = 0x38 }, + { .rfmax = 91000, .val = 0x39 }, + { .rfmax = 93000, .val = 0x3c }, + { .rfmax = 94000, .val = 0x3e }, + { .rfmax = 95000, .val = 0x3f }, + { .rfmax = 96000, .val = 0x40 }, + { .rfmax = 97000, .val = 0x42 }, + { .rfmax = 99000, .val = 0x45 }, + { .rfmax = 100000, .val = 0x46 }, + { .rfmax = 102000, .val = 0x48 }, + { .rfmax = 103000, .val = 0x4a }, + { .rfmax = 105000, .val = 0x4d }, + { .rfmax = 106000, .val = 0x4e }, + { .rfmax = 107000, .val = 0x50 }, + { .rfmax = 108000, .val = 0x51 }, + { .rfmax = 110000, .val = 0x54 }, + { .rfmax = 111000, .val = 0x56 }, + { .rfmax = 112000, .val = 0x57 }, + { .rfmax = 113000, .val = 0x58 }, + { .rfmax = 114000, .val = 0x59 }, + { .rfmax = 115000, .val = 0x5c }, + { .rfmax = 116000, .val = 0x5d }, + { .rfmax = 117000, .val = 0x5f }, + { .rfmax = 119000, .val = 0x60 }, + { .rfmax = 120000, .val = 0x64 }, + { .rfmax = 121000, .val = 0x65 }, + { .rfmax = 122000, .val = 0x66 }, + { .rfmax = 123000, .val = 0x68 }, + { .rfmax = 124000, .val = 0x69 }, + { .rfmax = 125000, .val = 0x6c }, + { .rfmax = 126000, .val = 0x6d }, + { .rfmax = 127000, .val = 0x6e }, + { .rfmax = 128000, .val = 0x70 }, + { .rfmax = 129000, .val = 0x71 }, + { .rfmax = 130000, .val = 0x75 }, + { .rfmax = 131000, .val = 0x77 }, + { .rfmax = 132000, .val = 0x78 }, + { .rfmax = 133000, .val = 0x7b }, + { .rfmax = 134000, .val = 0x7e }, + { .rfmax = 135000, .val = 0x81 }, + { .rfmax = 136000, .val = 0x82 }, + { .rfmax = 137000, .val = 0x87 }, + { .rfmax = 138000, .val = 0x88 }, + { .rfmax = 139000, .val = 0x8d }, + { .rfmax = 140000, .val = 0x8e }, + { .rfmax = 141000, .val = 0x91 }, + { .rfmax = 142000, .val = 0x95 }, + { .rfmax = 143000, .val = 0x9a }, + { .rfmax = 144000, .val = 0x9d }, + { .rfmax = 145000, .val = 0xa1 }, + { .rfmax = 146000, .val = 0xa2 }, + { .rfmax = 147000, .val = 0xa4 }, + { .rfmax = 148000, .val = 0xa9 }, + { .rfmax = 149000, .val = 0xae }, + { .rfmax = 150000, .val = 0xb0 }, + { .rfmax = 151000, .val = 0xb1 }, + { .rfmax = 152000, .val = 0xb7 }, + { .rfmax = 153000, .val = 0xbd }, + { .rfmax = 154000, .val = 0x20 }, + { .rfmax = 155000, .val = 0x22 }, + { .rfmax = 156000, .val = 0x24 }, + { .rfmax = 157000, .val = 0x25 }, + { .rfmax = 158000, .val = 0x27 }, + { .rfmax = 159000, .val = 0x29 }, + { .rfmax = 160000, .val = 0x2c }, + { .rfmax = 161000, .val = 0x2d }, + { .rfmax = 163000, .val = 0x2e }, + { .rfmax = 164000, .val = 0x2f }, + { .rfmax = 165000, .val = 0x30 }, + { .rfmax = 166000, .val = 0x11 }, + { .rfmax = 167000, .val = 0x12 }, + { .rfmax = 168000, .val = 0x13 }, + { .rfmax = 169000, .val = 0x14 }, + { .rfmax = 170000, .val = 0x15 }, + { .rfmax = 172000, .val = 0x16 }, + { .rfmax = 173000, .val = 0x17 }, + { .rfmax = 174000, .val = 0x18 }, + { .rfmax = 175000, .val = 0x1a }, + { .rfmax = 176000, .val = 0x1b }, + { .rfmax = 178000, .val = 0x1d }, + { .rfmax = 179000, .val = 0x1e }, + { .rfmax = 180000, .val = 0x1f }, + { .rfmax = 181000, .val = 0x20 }, + { .rfmax = 182000, .val = 0x21 }, + { .rfmax = 183000, .val = 0x22 }, + { .rfmax = 184000, .val = 0x24 }, + { .rfmax = 185000, .val = 0x25 }, + { .rfmax = 186000, .val = 0x26 }, + { .rfmax = 187000, .val = 0x27 }, + { .rfmax = 188000, .val = 0x29 }, + { .rfmax = 189000, .val = 0x2a }, + { .rfmax = 190000, .val = 0x2c }, + { .rfmax = 191000, .val = 0x2d }, + { .rfmax = 192000, .val = 0x2e }, + { .rfmax = 193000, .val = 0x2f }, + { .rfmax = 194000, .val = 0x30 }, + { .rfmax = 195000, .val = 0x33 }, + { .rfmax = 196000, .val = 0x35 }, + { .rfmax = 198000, .val = 0x36 }, + { .rfmax = 200000, .val = 0x38 }, + { .rfmax = 201000, .val = 0x3c }, + { .rfmax = 202000, .val = 0x3d }, + { .rfmax = 203500, .val = 0x3e }, + { .rfmax = 206000, .val = 0x0e }, + { .rfmax = 208000, .val = 0x0f }, + { .rfmax = 212000, .val = 0x10 }, + { .rfmax = 216000, .val = 0x11 }, + { .rfmax = 217000, .val = 0x12 }, + { .rfmax = 218000, .val = 0x13 }, + { .rfmax = 220000, .val = 0x14 }, + { .rfmax = 222000, .val = 0x15 }, + { .rfmax = 225000, .val = 0x16 }, + { .rfmax = 228000, .val = 0x17 }, + { .rfmax = 231000, .val = 0x18 }, + { .rfmax = 234000, .val = 0x19 }, + { .rfmax = 235000, .val = 0x1a }, + { .rfmax = 236000, .val = 0x1b }, + { .rfmax = 237000, .val = 0x1c }, + { .rfmax = 240000, .val = 0x1d }, + { .rfmax = 242000, .val = 0x1f }, + { .rfmax = 247000, .val = 0x20 }, + { .rfmax = 249000, .val = 0x21 }, + { .rfmax = 252000, .val = 0x22 }, + { .rfmax = 253000, .val = 0x23 }, + { .rfmax = 254000, .val = 0x24 }, + { .rfmax = 256000, .val = 0x25 }, + { .rfmax = 259000, .val = 0x26 }, + { .rfmax = 262000, .val = 0x27 }, + { .rfmax = 264000, .val = 0x28 }, + { .rfmax = 267000, .val = 0x29 }, + { .rfmax = 269000, .val = 0x2a }, + { .rfmax = 271000, .val = 0x2b }, + { .rfmax = 273000, .val = 0x2c }, + { .rfmax = 275000, .val = 0x2d }, + { .rfmax = 277000, .val = 0x2e }, + { .rfmax = 279000, .val = 0x2f }, + { .rfmax = 282000, .val = 0x30 }, + { .rfmax = 284000, .val = 0x31 }, + { .rfmax = 286000, .val = 0x32 }, + { .rfmax = 287000, .val = 0x33 }, + { .rfmax = 290000, .val = 0x34 }, + { .rfmax = 293000, .val = 0x35 }, + { .rfmax = 295000, .val = 0x36 }, + { .rfmax = 297000, .val = 0x37 }, + { .rfmax = 300000, .val = 0x38 }, + { .rfmax = 303000, .val = 0x39 }, + { .rfmax = 305000, .val = 0x3a }, + { .rfmax = 306000, .val = 0x3b }, + { .rfmax = 307000, .val = 0x3c }, + { .rfmax = 310000, .val = 0x3d }, + { .rfmax = 312000, .val = 0x3e }, + { .rfmax = 315000, .val = 0x3f }, + { .rfmax = 318000, .val = 0x40 }, + { .rfmax = 320000, .val = 0x41 }, + { .rfmax = 323000, .val = 0x42 }, + { .rfmax = 324000, .val = 0x43 }, + { .rfmax = 325000, .val = 0x44 }, + { .rfmax = 327000, .val = 0x45 }, + { .rfmax = 331000, .val = 0x46 }, + { .rfmax = 334000, .val = 0x47 }, + { .rfmax = 337000, .val = 0x48 }, + { .rfmax = 339000, .val = 0x49 }, + { .rfmax = 340000, .val = 0x4a }, + { .rfmax = 341000, .val = 0x4b }, + { .rfmax = 343000, .val = 0x4c }, + { .rfmax = 345000, .val = 0x4d }, + { .rfmax = 349000, .val = 0x4e }, + { .rfmax = 352000, .val = 0x4f }, + { .rfmax = 353000, .val = 0x50 }, + { .rfmax = 355000, .val = 0x51 }, + { .rfmax = 357000, .val = 0x52 }, + { .rfmax = 359000, .val = 0x53 }, + { .rfmax = 361000, .val = 0x54 }, + { .rfmax = 362000, .val = 0x55 }, + { .rfmax = 364000, .val = 0x56 }, + { .rfmax = 368000, .val = 0x57 }, + { .rfmax = 370000, .val = 0x58 }, + { .rfmax = 372000, .val = 0x59 }, + { .rfmax = 375000, .val = 0x5a }, + { .rfmax = 376000, .val = 0x5b }, + { .rfmax = 377000, .val = 0x5c }, + { .rfmax = 379000, .val = 0x5d }, + { .rfmax = 382000, .val = 0x5e }, + { .rfmax = 384000, .val = 0x5f }, + { .rfmax = 385000, .val = 0x60 }, + { .rfmax = 386000, .val = 0x61 }, + { .rfmax = 388000, .val = 0x62 }, + { .rfmax = 390000, .val = 0x63 }, + { .rfmax = 393000, .val = 0x64 }, + { .rfmax = 394000, .val = 0x65 }, + { .rfmax = 396000, .val = 0x66 }, + { .rfmax = 397000, .val = 0x67 }, + { .rfmax = 398000, .val = 0x68 }, + { .rfmax = 400000, .val = 0x69 }, + { .rfmax = 402000, .val = 0x6a }, + { .rfmax = 403000, .val = 0x6b }, + { .rfmax = 407000, .val = 0x6c }, + { .rfmax = 408000, .val = 0x6d }, + { .rfmax = 409000, .val = 0x6e }, + { .rfmax = 410000, .val = 0x6f }, + { .rfmax = 411000, .val = 0x70 }, + { .rfmax = 412000, .val = 0x71 }, + { .rfmax = 413000, .val = 0x72 }, + { .rfmax = 414000, .val = 0x73 }, + { .rfmax = 417000, .val = 0x74 }, + { .rfmax = 418000, .val = 0x75 }, + { .rfmax = 420000, .val = 0x76 }, + { .rfmax = 422000, .val = 0x77 }, + { .rfmax = 423000, .val = 0x78 }, + { .rfmax = 424000, .val = 0x79 }, + { .rfmax = 427000, .val = 0x7a }, + { .rfmax = 428000, .val = 0x7b }, + { .rfmax = 429000, .val = 0x7d }, + { .rfmax = 432000, .val = 0x7f }, + { .rfmax = 434000, .val = 0x80 }, + { .rfmax = 435000, .val = 0x81 }, + { .rfmax = 436000, .val = 0x83 }, + { .rfmax = 437000, .val = 0x84 }, + { .rfmax = 438000, .val = 0x85 }, + { .rfmax = 439000, .val = 0x86 }, + { .rfmax = 440000, .val = 0x87 }, + { .rfmax = 441000, .val = 0x88 }, + { .rfmax = 442000, .val = 0x89 }, + { .rfmax = 445000, .val = 0x8a }, + { .rfmax = 446000, .val = 0x8b }, + { .rfmax = 447000, .val = 0x8c }, + { .rfmax = 448000, .val = 0x8e }, + { .rfmax = 449000, .val = 0x8f }, + { .rfmax = 450000, .val = 0x90 }, + { .rfmax = 452000, .val = 0x91 }, + { .rfmax = 453000, .val = 0x93 }, + { .rfmax = 454000, .val = 0x94 }, + { .rfmax = 456000, .val = 0x96 }, + { .rfmax = 457000, .val = 0x98 }, + { .rfmax = 461000, .val = 0x11 }, + { .rfmax = 468000, .val = 0x12 }, + { .rfmax = 472000, .val = 0x13 }, + { .rfmax = 473000, .val = 0x14 }, + { .rfmax = 474000, .val = 0x15 }, + { .rfmax = 481000, .val = 0x16 }, + { .rfmax = 486000, .val = 0x17 }, + { .rfmax = 491000, .val = 0x18 }, + { .rfmax = 498000, .val = 0x19 }, + { .rfmax = 499000, .val = 0x1a }, + { .rfmax = 501000, .val = 0x1b }, + { .rfmax = 506000, .val = 0x1c }, + { .rfmax = 511000, .val = 0x1d }, + { .rfmax = 516000, .val = 0x1e }, + { .rfmax = 520000, .val = 0x1f }, + { .rfmax = 521000, .val = 0x20 }, + { .rfmax = 525000, .val = 0x21 }, + { .rfmax = 529000, .val = 0x22 }, + { .rfmax = 533000, .val = 0x23 }, + { .rfmax = 539000, .val = 0x24 }, + { .rfmax = 541000, .val = 0x25 }, + { .rfmax = 547000, .val = 0x26 }, + { .rfmax = 549000, .val = 0x27 }, + { .rfmax = 551000, .val = 0x28 }, + { .rfmax = 556000, .val = 0x29 }, + { .rfmax = 561000, .val = 0x2a }, + { .rfmax = 563000, .val = 0x2b }, + { .rfmax = 565000, .val = 0x2c }, + { .rfmax = 569000, .val = 0x2d }, + { .rfmax = 571000, .val = 0x2e }, + { .rfmax = 577000, .val = 0x2f }, + { .rfmax = 580000, .val = 0x30 }, + { .rfmax = 582000, .val = 0x31 }, + { .rfmax = 584000, .val = 0x32 }, + { .rfmax = 588000, .val = 0x33 }, + { .rfmax = 591000, .val = 0x34 }, + { .rfmax = 596000, .val = 0x35 }, + { .rfmax = 598000, .val = 0x36 }, + { .rfmax = 603000, .val = 0x37 }, + { .rfmax = 604000, .val = 0x38 }, + { .rfmax = 606000, .val = 0x39 }, + { .rfmax = 612000, .val = 0x3a }, + { .rfmax = 615000, .val = 0x3b }, + { .rfmax = 617000, .val = 0x3c }, + { .rfmax = 621000, .val = 0x3d }, + { .rfmax = 622000, .val = 0x3e }, + { .rfmax = 625000, .val = 0x3f }, + { .rfmax = 632000, .val = 0x40 }, + { .rfmax = 633000, .val = 0x41 }, + { .rfmax = 634000, .val = 0x42 }, + { .rfmax = 642000, .val = 0x43 }, + { .rfmax = 643000, .val = 0x44 }, + { .rfmax = 647000, .val = 0x45 }, + { .rfmax = 650000, .val = 0x46 }, + { .rfmax = 652000, .val = 0x47 }, + { .rfmax = 657000, .val = 0x48 }, + { .rfmax = 661000, .val = 0x49 }, + { .rfmax = 662000, .val = 0x4a }, + { .rfmax = 665000, .val = 0x4b }, + { .rfmax = 667000, .val = 0x4c }, + { .rfmax = 670000, .val = 0x4d }, + { .rfmax = 673000, .val = 0x4e }, + { .rfmax = 676000, .val = 0x4f }, + { .rfmax = 677000, .val = 0x50 }, + { .rfmax = 681000, .val = 0x51 }, + { .rfmax = 683000, .val = 0x52 }, + { .rfmax = 686000, .val = 0x53 }, + { .rfmax = 688000, .val = 0x54 }, + { .rfmax = 689000, .val = 0x55 }, + { .rfmax = 691000, .val = 0x56 }, + { .rfmax = 695000, .val = 0x57 }, + { .rfmax = 698000, .val = 0x58 }, + { .rfmax = 703000, .val = 0x59 }, + { .rfmax = 704000, .val = 0x5a }, + { .rfmax = 705000, .val = 0x5b }, + { .rfmax = 707000, .val = 0x5c }, + { .rfmax = 710000, .val = 0x5d }, + { .rfmax = 712000, .val = 0x5e }, + { .rfmax = 717000, .val = 0x5f }, + { .rfmax = 718000, .val = 0x60 }, + { .rfmax = 721000, .val = 0x61 }, + { .rfmax = 722000, .val = 0x62 }, + { .rfmax = 723000, .val = 0x63 }, + { .rfmax = 725000, .val = 0x64 }, + { .rfmax = 727000, .val = 0x65 }, + { .rfmax = 730000, .val = 0x66 }, + { .rfmax = 732000, .val = 0x67 }, + { .rfmax = 735000, .val = 0x68 }, + { .rfmax = 740000, .val = 0x69 }, + { .rfmax = 741000, .val = 0x6a }, + { .rfmax = 742000, .val = 0x6b }, + { .rfmax = 743000, .val = 0x6c }, + { .rfmax = 745000, .val = 0x6d }, + { .rfmax = 747000, .val = 0x6e }, + { .rfmax = 748000, .val = 0x6f }, + { .rfmax = 750000, .val = 0x70 }, + { .rfmax = 752000, .val = 0x71 }, + { .rfmax = 754000, .val = 0x72 }, + { .rfmax = 757000, .val = 0x73 }, + { .rfmax = 758000, .val = 0x74 }, + { .rfmax = 760000, .val = 0x75 }, + { .rfmax = 763000, .val = 0x76 }, + { .rfmax = 764000, .val = 0x77 }, + { .rfmax = 766000, .val = 0x78 }, + { .rfmax = 767000, .val = 0x79 }, + { .rfmax = 768000, .val = 0x7a }, + { .rfmax = 773000, .val = 0x7b }, + { .rfmax = 774000, .val = 0x7c }, + { .rfmax = 776000, .val = 0x7d }, + { .rfmax = 777000, .val = 0x7e }, + { .rfmax = 778000, .val = 0x7f }, + { .rfmax = 779000, .val = 0x80 }, + { .rfmax = 781000, .val = 0x81 }, + { .rfmax = 783000, .val = 0x82 }, + { .rfmax = 784000, .val = 0x83 }, + { .rfmax = 785000, .val = 0x84 }, + { .rfmax = 786000, .val = 0x85 }, + { .rfmax = 793000, .val = 0x86 }, + { .rfmax = 794000, .val = 0x87 }, + { .rfmax = 795000, .val = 0x88 }, + { .rfmax = 797000, .val = 0x89 }, + { .rfmax = 799000, .val = 0x8a }, + { .rfmax = 801000, .val = 0x8b }, + { .rfmax = 802000, .val = 0x8c }, + { .rfmax = 803000, .val = 0x8d }, + { .rfmax = 804000, .val = 0x8e }, + { .rfmax = 810000, .val = 0x90 }, + { .rfmax = 811000, .val = 0x91 }, + { .rfmax = 812000, .val = 0x92 }, + { .rfmax = 814000, .val = 0x93 }, + { .rfmax = 816000, .val = 0x94 }, + { .rfmax = 817000, .val = 0x96 }, + { .rfmax = 818000, .val = 0x97 }, + { .rfmax = 820000, .val = 0x98 }, + { .rfmax = 821000, .val = 0x99 }, + { .rfmax = 822000, .val = 0x9a }, + { .rfmax = 828000, .val = 0x9b }, + { .rfmax = 829000, .val = 0x9d }, + { .rfmax = 830000, .val = 0x9f }, + { .rfmax = 831000, .val = 0xa0 }, + { .rfmax = 833000, .val = 0xa1 }, + { .rfmax = 835000, .val = 0xa2 }, + { .rfmax = 836000, .val = 0xa3 }, + { .rfmax = 837000, .val = 0xa4 }, + { .rfmax = 838000, .val = 0xa6 }, + { .rfmax = 840000, .val = 0xa8 }, + { .rfmax = 842000, .val = 0xa9 }, + { .rfmax = 845000, .val = 0xaa }, + { .rfmax = 846000, .val = 0xab }, + { .rfmax = 847000, .val = 0xad }, + { .rfmax = 848000, .val = 0xae }, + { .rfmax = 852000, .val = 0xaf }, + { .rfmax = 853000, .val = 0xb0 }, + { .rfmax = 858000, .val = 0xb1 }, + { .rfmax = 860000, .val = 0xb2 }, + { .rfmax = 861000, .val = 0xb3 }, + { .rfmax = 862000, .val = 0xb4 }, + { .rfmax = 863000, .val = 0xb6 }, + { .rfmax = 864000, .val = 0xb8 }, + { .rfmax = 865000, .val = 0xb9 }, + { .rfmax = 0, .val = 0x00 }, /* end */ +}; + +static struct tda18271_map tda18271_ir_measure[] = { + { .rfmax = 30000, .val = 4 }, + { .rfmax = 200000, .val = 5 }, + { .rfmax = 600000, .val = 6 }, + { .rfmax = 865000, .val = 7 }, + { .rfmax = 0, .val = 0 }, /* end */ +}; + +static struct tda18271_map tda18271_rf_cal_dc_over_dt[] = { + { .rfmax = 47900, .val = 0x00 }, + { .rfmax = 55000, .val = 0x00 }, + { .rfmax = 61100, .val = 0x0a }, + { .rfmax = 64000, .val = 0x0a }, + { .rfmax = 82000, .val = 0x14 }, + { .rfmax = 84000, .val = 0x19 }, + { .rfmax = 119000, .val = 0x1c }, + { .rfmax = 124000, .val = 0x20 }, + { .rfmax = 129000, .val = 0x2a }, + { .rfmax = 134000, .val = 0x32 }, + { .rfmax = 139000, .val = 0x39 }, + { .rfmax = 144000, .val = 0x3e }, + { .rfmax = 149000, .val = 0x3f }, + { .rfmax = 152600, .val = 0x40 }, + { .rfmax = 154000, .val = 0x40 }, + { .rfmax = 164700, .val = 0x41 }, + { .rfmax = 203500, .val = 0x32 }, + { .rfmax = 353000, .val = 0x19 }, + { .rfmax = 356000, .val = 0x1a }, + { .rfmax = 359000, .val = 0x1b }, + { .rfmax = 363000, .val = 0x1c }, + { .rfmax = 366000, .val = 0x1d }, + { .rfmax = 369000, .val = 0x1e }, + { .rfmax = 373000, .val = 0x1f }, + { .rfmax = 376000, .val = 0x20 }, + { .rfmax = 379000, .val = 0x21 }, + { .rfmax = 383000, .val = 0x22 }, + { .rfmax = 386000, .val = 0x23 }, + { .rfmax = 389000, .val = 0x24 }, + { .rfmax = 393000, .val = 0x25 }, + { .rfmax = 396000, .val = 0x26 }, + { .rfmax = 399000, .val = 0x27 }, + { .rfmax = 402000, .val = 0x28 }, + { .rfmax = 404000, .val = 0x29 }, + { .rfmax = 407000, .val = 0x2a }, + { .rfmax = 409000, .val = 0x2b }, + { .rfmax = 412000, .val = 0x2c }, + { .rfmax = 414000, .val = 0x2d }, + { .rfmax = 417000, .val = 0x2e }, + { .rfmax = 419000, .val = 0x2f }, + { .rfmax = 422000, .val = 0x30 }, + { .rfmax = 424000, .val = 0x31 }, + { .rfmax = 427000, .val = 0x32 }, + { .rfmax = 429000, .val = 0x33 }, + { .rfmax = 432000, .val = 0x34 }, + { .rfmax = 434000, .val = 0x35 }, + { .rfmax = 437000, .val = 0x36 }, + { .rfmax = 439000, .val = 0x37 }, + { .rfmax = 442000, .val = 0x38 }, + { .rfmax = 444000, .val = 0x39 }, + { .rfmax = 447000, .val = 0x3a }, + { .rfmax = 449000, .val = 0x3b }, + { .rfmax = 457800, .val = 0x3c }, + { .rfmax = 465000, .val = 0x0f }, + { .rfmax = 477000, .val = 0x12 }, + { .rfmax = 483000, .val = 0x14 }, + { .rfmax = 502000, .val = 0x19 }, + { .rfmax = 508000, .val = 0x1b }, + { .rfmax = 519000, .val = 0x1c }, + { .rfmax = 522000, .val = 0x1d }, + { .rfmax = 524000, .val = 0x1e }, + { .rfmax = 534000, .val = 0x1f }, + { .rfmax = 549000, .val = 0x20 }, + { .rfmax = 554000, .val = 0x22 }, + { .rfmax = 584000, .val = 0x24 }, + { .rfmax = 589000, .val = 0x26 }, + { .rfmax = 658000, .val = 0x27 }, + { .rfmax = 664000, .val = 0x2c }, + { .rfmax = 669000, .val = 0x2d }, + { .rfmax = 699000, .val = 0x2e }, + { .rfmax = 704000, .val = 0x30 }, + { .rfmax = 709000, .val = 0x31 }, + { .rfmax = 714000, .val = 0x32 }, + { .rfmax = 724000, .val = 0x33 }, + { .rfmax = 729000, .val = 0x36 }, + { .rfmax = 739000, .val = 0x38 }, + { .rfmax = 744000, .val = 0x39 }, + { .rfmax = 749000, .val = 0x3b }, + { .rfmax = 754000, .val = 0x3c }, + { .rfmax = 759000, .val = 0x3d }, + { .rfmax = 764000, .val = 0x3e }, + { .rfmax = 769000, .val = 0x3f }, + { .rfmax = 774000, .val = 0x40 }, + { .rfmax = 779000, .val = 0x41 }, + { .rfmax = 784000, .val = 0x43 }, + { .rfmax = 789000, .val = 0x46 }, + { .rfmax = 794000, .val = 0x48 }, + { .rfmax = 799000, .val = 0x4b }, + { .rfmax = 804000, .val = 0x4f }, + { .rfmax = 809000, .val = 0x54 }, + { .rfmax = 814000, .val = 0x59 }, + { .rfmax = 819000, .val = 0x5d }, + { .rfmax = 824000, .val = 0x61 }, + { .rfmax = 829000, .val = 0x68 }, + { .rfmax = 834000, .val = 0x6e }, + { .rfmax = 839000, .val = 0x75 }, + { .rfmax = 844000, .val = 0x7e }, + { .rfmax = 849000, .val = 0x82 }, + { .rfmax = 854000, .val = 0x84 }, + { .rfmax = 859000, .val = 0x8f }, + { .rfmax = 865000, .val = 0x9a }, + { .rfmax = 0, .val = 0x00 }, /* end */ +}; + +/*---------------------------------------------------------------------*/ + +struct tda18271_thermo_map { + u8 d; + u8 r0; + u8 r1; +}; + +static struct tda18271_thermo_map tda18271_thermometer[] = { + { .d = 0x00, .r0 = 60, .r1 = 92 }, + { .d = 0x01, .r0 = 62, .r1 = 94 }, + { .d = 0x02, .r0 = 66, .r1 = 98 }, + { .d = 0x03, .r0 = 64, .r1 = 96 }, + { .d = 0x04, .r0 = 74, .r1 = 106 }, + { .d = 0x05, .r0 = 72, .r1 = 104 }, + { .d = 0x06, .r0 = 68, .r1 = 100 }, + { .d = 0x07, .r0 = 70, .r1 = 102 }, + { .d = 0x08, .r0 = 90, .r1 = 122 }, + { .d = 0x09, .r0 = 88, .r1 = 120 }, + { .d = 0x0a, .r0 = 84, .r1 = 116 }, + { .d = 0x0b, .r0 = 86, .r1 = 118 }, + { .d = 0x0c, .r0 = 76, .r1 = 108 }, + { .d = 0x0d, .r0 = 78, .r1 = 110 }, + { .d = 0x0e, .r0 = 82, .r1 = 114 }, + { .d = 0x0f, .r0 = 80, .r1 = 112 }, + { .d = 0x00, .r0 = 0, .r1 = 0 }, /* end */ +}; + +int tda18271_lookup_thermometer(struct dvb_frontend *fe) +{ + struct tda18271_priv *priv = fe->tuner_priv; + unsigned char *regs = priv->tda18271_regs; + int val, i = 0; + + while (tda18271_thermometer[i].d < (regs[R_TM] & 0x0f)) { + if (tda18271_thermometer[i + 1].d == 0) + break; + i++; + } + + if ((regs[R_TM] & 0x20) == 0x20) + val = tda18271_thermometer[i].r1; + else + val = tda18271_thermometer[i].r0; + + tda_map("(%d) tm = %d\n", i, val); + + return val; +} + +/*---------------------------------------------------------------------*/ + +struct tda18271_cid_target_map { + u32 rfmax; + u8 target; + u16 limit; +}; + +static struct tda18271_cid_target_map tda18271_cid_target[] = { + { .rfmax = 46000, .target = 0x04, .limit = 1800 }, + { .rfmax = 52200, .target = 0x0a, .limit = 1500 }, + { .rfmax = 79100, .target = 0x01, .limit = 4000 }, + { .rfmax = 136800, .target = 0x18, .limit = 4000 }, + { .rfmax = 156700, .target = 0x18, .limit = 4000 }, + { .rfmax = 156700, .target = 0x18, .limit = 4000 }, + { .rfmax = 186250, .target = 0x0a, .limit = 4000 }, + { .rfmax = 230000, .target = 0x0a, .limit = 4000 }, + { .rfmax = 345000, .target = 0x18, .limit = 4000 }, + { .rfmax = 426000, .target = 0x0e, .limit = 4000 }, + { .rfmax = 489500, .target = 0x1e, .limit = 4000 }, + { .rfmax = 697500, .target = 0x32, .limit = 4000 }, + { .rfmax = 842000, .target = 0x3a, .limit = 4000 }, + { .rfmax = 0, .target = 0x00, .limit = 0 }, /* end */ +}; + +int tda18271_lookup_cid_target(struct dvb_frontend *fe, + u32 *freq, u8 *cid_target, u16 *count_limit) +{ + int i = 0; + + while ((tda18271_cid_target[i].rfmax * 1000) < *freq) { + if (tda18271_cid_target[i + 1].rfmax == 0) + break; + i++; + } + *cid_target = tda18271_cid_target[i].target; + *count_limit = tda18271_cid_target[i].limit; + + tda_map("(%d) cid_target = %02x, count_limit = %d\n", i, + tda18271_cid_target[i].target, tda18271_cid_target[i].limit); + + return 0; +} + +/*---------------------------------------------------------------------*/ + +static struct tda18271_rf_tracking_filter_cal tda18271_rf_band_template[] = { + { .rfmax = 47900, .rfband = 0x00, + .rf1_def = 46000, .rf2_def = 0, .rf3_def = 0 }, + { .rfmax = 61100, .rfband = 0x01, + .rf1_def = 52200, .rf2_def = 0, .rf3_def = 0 }, + { .rfmax = 152600, .rfband = 0x02, + .rf1_def = 70100, .rf2_def = 136800, .rf3_def = 0 }, + { .rfmax = 164700, .rfband = 0x03, + .rf1_def = 156700, .rf2_def = 0, .rf3_def = 0 }, + { .rfmax = 203500, .rfband = 0x04, + .rf1_def = 186250, .rf2_def = 0, .rf3_def = 0 }, + { .rfmax = 457800, .rfband = 0x05, + .rf1_def = 230000, .rf2_def = 345000, .rf3_def = 426000 }, + { .rfmax = 865000, .rfband = 0x06, + .rf1_def = 489500, .rf2_def = 697500, .rf3_def = 842000 }, + { .rfmax = 0, .rfband = 0x00, + .rf1_def = 0, .rf2_def = 0, .rf3_def = 0 }, /* end */ +}; + +int tda18271_lookup_rf_band(struct dvb_frontend *fe, u32 *freq, u8 *rf_band) +{ + struct tda18271_priv *priv = fe->tuner_priv; + struct tda18271_rf_tracking_filter_cal *map = priv->rf_cal_state; + int i = 0; + + while ((map[i].rfmax * 1000) < *freq) { + if (tda18271_debug & DBG_ADV) + tda_map("(%d) rfmax = %d < freq = %d, " + "rf1_def = %d, rf2_def = %d, rf3_def = %d, " + "rf1 = %d, rf2 = %d, rf3 = %d, " + "rf_a1 = %d, rf_a2 = %d, " + "rf_b1 = %d, rf_b2 = %d\n", + i, map[i].rfmax * 1000, *freq, + map[i].rf1_def, map[i].rf2_def, map[i].rf3_def, + map[i].rf1, map[i].rf2, map[i].rf3, + map[i].rf_a1, map[i].rf_a2, + map[i].rf_b1, map[i].rf_b2); + if (map[i].rfmax == 0) + return -EINVAL; + i++; + } + if (rf_band) + *rf_band = map[i].rfband; + + tda_map("(%d) rf_band = %02x\n", i, map[i].rfband); + + return i; +} + +/*---------------------------------------------------------------------*/ + +struct tda18271_map_layout { + struct tda18271_pll_map *main_pll; + struct tda18271_pll_map *cal_pll; + + struct tda18271_map *rf_cal; + struct tda18271_map *rf_cal_kmco; + struct tda18271_map *rf_cal_dc_over_dt; + + struct tda18271_map *bp_filter; + struct tda18271_map *rf_band; + struct tda18271_map *gain_taper; + struct tda18271_map *ir_measure; +}; + +/*---------------------------------------------------------------------*/ + +int tda18271_lookup_pll_map(struct dvb_frontend *fe, + enum tda18271_map_type map_type, + u32 *freq, u8 *post_div, u8 *div) +{ + struct tda18271_priv *priv = fe->tuner_priv; + struct tda18271_pll_map *map = NULL; + unsigned int i = 0; + char *map_name; + int ret = 0; + + BUG_ON(!priv->maps); + + switch (map_type) { + case MAIN_PLL: + map = priv->maps->main_pll; + map_name = "main_pll"; + break; + case CAL_PLL: + map = priv->maps->cal_pll; + map_name = "cal_pll"; + break; + default: + /* we should never get here */ + map_name = "undefined"; + break; + } + + if (!map) { + tda_warn("%s map is not set!\n", map_name); + ret = -EINVAL; + goto fail; + } + + while ((map[i].lomax * 1000) < *freq) { + if (map[i + 1].lomax == 0) { + tda_map("%s: frequency (%d) out of range\n", + map_name, *freq); + ret = -ERANGE; + break; + } + i++; + } + *post_div = map[i].pd; + *div = map[i].d; + + tda_map("(%d) %s: post div = 0x%02x, div = 0x%02x\n", + i, map_name, *post_div, *div); +fail: + return ret; +} + +int tda18271_lookup_map(struct dvb_frontend *fe, + enum tda18271_map_type map_type, + u32 *freq, u8 *val) +{ + struct tda18271_priv *priv = fe->tuner_priv; + struct tda18271_map *map = NULL; + unsigned int i = 0; + char *map_name; + int ret = 0; + + BUG_ON(!priv->maps); + + switch (map_type) { + case BP_FILTER: + map = priv->maps->bp_filter; + map_name = "bp_filter"; + break; + case RF_CAL_KMCO: + map = priv->maps->rf_cal_kmco; + map_name = "km"; + break; + case RF_BAND: + map = priv->maps->rf_band; + map_name = "rf_band"; + break; + case GAIN_TAPER: + map = priv->maps->gain_taper; + map_name = "gain_taper"; + break; + case RF_CAL: + map = priv->maps->rf_cal; + map_name = "rf_cal"; + break; + case IR_MEASURE: + map = priv->maps->ir_measure; + map_name = "ir_measure"; + break; + case RF_CAL_DC_OVER_DT: + map = priv->maps->rf_cal_dc_over_dt; + map_name = "rf_cal_dc_over_dt"; + break; + default: + /* we should never get here */ + map_name = "undefined"; + break; + } + + if (!map) { + tda_warn("%s map is not set!\n", map_name); + ret = -EINVAL; + goto fail; + } + + while ((map[i].rfmax * 1000) < *freq) { + if (map[i + 1].rfmax == 0) { + tda_map("%s: frequency (%d) out of range\n", + map_name, *freq); + ret = -ERANGE; + break; + } + i++; + } + *val = map[i].val; + + tda_map("(%d) %s: 0x%02x\n", i, map_name, *val); +fail: + return ret; +} + +/*---------------------------------------------------------------------*/ + +static struct tda18271_std_map tda18271c1_std_map = { + .fm_radio = { .if_freq = 1250, .fm_rfn = 1, .agc_mode = 3, .std = 0, + .if_lvl = 0, .rfagc_top = 0x2c, }, /* EP3[4:0] 0x18 */ + .atv_b = { .if_freq = 6750, .fm_rfn = 0, .agc_mode = 1, .std = 6, + .if_lvl = 0, .rfagc_top = 0x2c, }, /* EP3[4:0] 0x0e */ + .atv_dk = { .if_freq = 7750, .fm_rfn = 0, .agc_mode = 1, .std = 7, + .if_lvl = 0, .rfagc_top = 0x2c, }, /* EP3[4:0] 0x0f */ + .atv_gh = { .if_freq = 7750, .fm_rfn = 0, .agc_mode = 1, .std = 7, + .if_lvl = 0, .rfagc_top = 0x2c, }, /* EP3[4:0] 0x0f */ + .atv_i = { .if_freq = 7750, .fm_rfn = 0, .agc_mode = 1, .std = 7, + .if_lvl = 0, .rfagc_top = 0x2c, }, /* EP3[4:0] 0x0f */ + .atv_l = { .if_freq = 7750, .fm_rfn = 0, .agc_mode = 1, .std = 7, + .if_lvl = 0, .rfagc_top = 0x2c, }, /* EP3[4:0] 0x0f */ + .atv_lc = { .if_freq = 1250, .fm_rfn = 0, .agc_mode = 1, .std = 7, + .if_lvl = 0, .rfagc_top = 0x2c, }, /* EP3[4:0] 0x0f */ + .atv_mn = { .if_freq = 5750, .fm_rfn = 0, .agc_mode = 1, .std = 5, + .if_lvl = 0, .rfagc_top = 0x2c, }, /* EP3[4:0] 0x0d */ + .atsc_6 = { .if_freq = 3250, .fm_rfn = 0, .agc_mode = 3, .std = 4, + .if_lvl = 1, .rfagc_top = 0x37, }, /* EP3[4:0] 0x1c */ + .dvbt_6 = { .if_freq = 3300, .fm_rfn = 0, .agc_mode = 3, .std = 4, + .if_lvl = 1, .rfagc_top = 0x37, }, /* EP3[4:0] 0x1c */ + .dvbt_7 = { .if_freq = 3800, .fm_rfn = 0, .agc_mode = 3, .std = 5, + .if_lvl = 1, .rfagc_top = 0x37, }, /* EP3[4:0] 0x1d */ + .dvbt_8 = { .if_freq = 4300, .fm_rfn = 0, .agc_mode = 3, .std = 6, + .if_lvl = 1, .rfagc_top = 0x37, }, /* EP3[4:0] 0x1e */ + .qam_6 = { .if_freq = 4000, .fm_rfn = 0, .agc_mode = 3, .std = 5, + .if_lvl = 1, .rfagc_top = 0x37, }, /* EP3[4:0] 0x1d */ + .qam_8 = { .if_freq = 5000, .fm_rfn = 0, .agc_mode = 3, .std = 7, + .if_lvl = 1, .rfagc_top = 0x37, }, /* EP3[4:0] 0x1f */ +}; + +static struct tda18271_std_map tda18271c2_std_map = { + .fm_radio = { .if_freq = 1250, .fm_rfn = 1, .agc_mode = 3, .std = 0, + .if_lvl = 0, .rfagc_top = 0x2c, }, /* EP3[4:0] 0x18 */ + .atv_b = { .if_freq = 6000, .fm_rfn = 0, .agc_mode = 1, .std = 5, + .if_lvl = 0, .rfagc_top = 0x2c, }, /* EP3[4:0] 0x0d */ + .atv_dk = { .if_freq = 6900, .fm_rfn = 0, .agc_mode = 1, .std = 6, + .if_lvl = 0, .rfagc_top = 0x2c, }, /* EP3[4:0] 0x0e */ + .atv_gh = { .if_freq = 7100, .fm_rfn = 0, .agc_mode = 1, .std = 6, + .if_lvl = 0, .rfagc_top = 0x2c, }, /* EP3[4:0] 0x0e */ + .atv_i = { .if_freq = 7250, .fm_rfn = 0, .agc_mode = 1, .std = 6, + .if_lvl = 0, .rfagc_top = 0x2c, }, /* EP3[4:0] 0x0e */ + .atv_l = { .if_freq = 6900, .fm_rfn = 0, .agc_mode = 1, .std = 6, + .if_lvl = 0, .rfagc_top = 0x2c, }, /* EP3[4:0] 0x0e */ + .atv_lc = { .if_freq = 1250, .fm_rfn = 0, .agc_mode = 1, .std = 6, + .if_lvl = 0, .rfagc_top = 0x2c, }, /* EP3[4:0] 0x0e */ + .atv_mn = { .if_freq = 5400, .fm_rfn = 0, .agc_mode = 1, .std = 4, + .if_lvl = 0, .rfagc_top = 0x2c, }, /* EP3[4:0] 0x0c */ + .atsc_6 = { .if_freq = 3250, .fm_rfn = 0, .agc_mode = 3, .std = 4, + .if_lvl = 1, .rfagc_top = 0x37, }, /* EP3[4:0] 0x1c */ + .dvbt_6 = { .if_freq = 3300, .fm_rfn = 0, .agc_mode = 3, .std = 4, + .if_lvl = 1, .rfagc_top = 0x37, }, /* EP3[4:0] 0x1c */ + .dvbt_7 = { .if_freq = 3500, .fm_rfn = 0, .agc_mode = 3, .std = 4, + .if_lvl = 1, .rfagc_top = 0x37, }, /* EP3[4:0] 0x1c */ + .dvbt_8 = { .if_freq = 4000, .fm_rfn = 0, .agc_mode = 3, .std = 5, + .if_lvl = 1, .rfagc_top = 0x37, }, /* EP3[4:0] 0x1d */ + .qam_6 = { .if_freq = 4000, .fm_rfn = 0, .agc_mode = 3, .std = 5, + .if_lvl = 1, .rfagc_top = 0x37, }, /* EP3[4:0] 0x1d */ + .qam_8 = { .if_freq = 5000, .fm_rfn = 0, .agc_mode = 3, .std = 7, + .if_lvl = 1, .rfagc_top = 0x37, }, /* EP3[4:0] 0x1f */ +}; + +/*---------------------------------------------------------------------*/ + +static struct tda18271_map_layout tda18271c1_map_layout = { + .main_pll = tda18271c1_main_pll, + .cal_pll = tda18271c1_cal_pll, + + .rf_cal = tda18271c1_rf_cal, + .rf_cal_kmco = tda18271c1_km, + + .bp_filter = tda18271_bp_filter, + .rf_band = tda18271_rf_band, + .gain_taper = tda18271_gain_taper, + .ir_measure = tda18271_ir_measure, +}; + +static struct tda18271_map_layout tda18271c2_map_layout = { + .main_pll = tda18271c2_main_pll, + .cal_pll = tda18271c2_cal_pll, + + .rf_cal = tda18271c2_rf_cal, + .rf_cal_kmco = tda18271c2_km, + + .rf_cal_dc_over_dt = tda18271_rf_cal_dc_over_dt, + + .bp_filter = tda18271_bp_filter, + .rf_band = tda18271_rf_band, + .gain_taper = tda18271_gain_taper, + .ir_measure = tda18271_ir_measure, +}; + +int tda18271_assign_map_layout(struct dvb_frontend *fe) +{ + struct tda18271_priv *priv = fe->tuner_priv; + int ret = 0; + + switch (priv->id) { + case TDA18271HDC1: + priv->maps = &tda18271c1_map_layout; + memcpy(&priv->std, &tda18271c1_std_map, + sizeof(struct tda18271_std_map)); + break; + case TDA18271HDC2: + priv->maps = &tda18271c2_map_layout; + memcpy(&priv->std, &tda18271c2_std_map, + sizeof(struct tda18271_std_map)); + break; + default: + ret = -EINVAL; + break; + } + memcpy(priv->rf_cal_state, &tda18271_rf_band_template, + sizeof(tda18271_rf_band_template)); + + return ret; +} + +/* + * Overrides for Emacs so that we follow Linus's tabbing style. + * --------------------------------------------------------------------------- + * Local variables: + * c-basic-offset: 8 + * End: + */ diff --git a/linux/drivers/media/common/tuners/tda18271-priv.h b/linux/drivers/media/common/tuners/tda18271-priv.h new file mode 100644 index 000000000..8ceeca081 --- /dev/null +++ b/linux/drivers/media/common/tuners/tda18271-priv.h @@ -0,0 +1,229 @@ +/* + tda18271-priv.h - private header for the NXP TDA18271 silicon tuner + + Copyright (C) 2007, 2008 Michael Krufky + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. +*/ + +#ifndef __TDA18271_PRIV_H__ +#define __TDA18271_PRIV_H__ + +#include +#include +#include "compat.h" +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,16) +#include +#else +#include +#endif +#include "tuner-i2c.h" +#include "tda18271.h" + +#define R_ID 0x00 /* ID byte */ +#define R_TM 0x01 /* Thermo byte */ +#define R_PL 0x02 /* Power level byte */ +#define R_EP1 0x03 /* Easy Prog byte 1 */ +#define R_EP2 0x04 /* Easy Prog byte 2 */ +#define R_EP3 0x05 /* Easy Prog byte 3 */ +#define R_EP4 0x06 /* Easy Prog byte 4 */ +#define R_EP5 0x07 /* Easy Prog byte 5 */ +#define R_CPD 0x08 /* Cal Post-Divider byte */ +#define R_CD1 0x09 /* Cal Divider byte 1 */ +#define R_CD2 0x0a /* Cal Divider byte 2 */ +#define R_CD3 0x0b /* Cal Divider byte 3 */ +#define R_MPD 0x0c /* Main Post-Divider byte */ +#define R_MD1 0x0d /* Main Divider byte 1 */ +#define R_MD2 0x0e /* Main Divider byte 2 */ +#define R_MD3 0x0f /* Main Divider byte 3 */ +#define R_EB1 0x10 /* Extended byte 1 */ +#define R_EB2 0x11 /* Extended byte 2 */ +#define R_EB3 0x12 /* Extended byte 3 */ +#define R_EB4 0x13 /* Extended byte 4 */ +#define R_EB5 0x14 /* Extended byte 5 */ +#define R_EB6 0x15 /* Extended byte 6 */ +#define R_EB7 0x16 /* Extended byte 7 */ +#define R_EB8 0x17 /* Extended byte 8 */ +#define R_EB9 0x18 /* Extended byte 9 */ +#define R_EB10 0x19 /* Extended byte 10 */ +#define R_EB11 0x1a /* Extended byte 11 */ +#define R_EB12 0x1b /* Extended byte 12 */ +#define R_EB13 0x1c /* Extended byte 13 */ +#define R_EB14 0x1d /* Extended byte 14 */ +#define R_EB15 0x1e /* Extended byte 15 */ +#define R_EB16 0x1f /* Extended byte 16 */ +#define R_EB17 0x20 /* Extended byte 17 */ +#define R_EB18 0x21 /* Extended byte 18 */ +#define R_EB19 0x22 /* Extended byte 19 */ +#define R_EB20 0x23 /* Extended byte 20 */ +#define R_EB21 0x24 /* Extended byte 21 */ +#define R_EB22 0x25 /* Extended byte 22 */ +#define R_EB23 0x26 /* Extended byte 23 */ + +#define TDA18271_NUM_REGS 39 + +/*---------------------------------------------------------------------*/ + +struct tda18271_rf_tracking_filter_cal { + u32 rfmax; + u8 rfband; + u32 rf1_def; + u32 rf2_def; + u32 rf3_def; + u32 rf1; + u32 rf2; + u32 rf3; + int rf_a1; + int rf_b1; + int rf_a2; + int rf_b2; +}; + +enum tda18271_pll { + TDA18271_MAIN_PLL, + TDA18271_CAL_PLL, +}; + +enum tda18271_mode { + TDA18271_ANALOG, + TDA18271_DIGITAL, +}; + +struct tda18271_map_layout; + +enum tda18271_ver { + TDA18271HDC1, + TDA18271HDC2, +}; + +struct tda18271_priv { + unsigned char tda18271_regs[TDA18271_NUM_REGS]; + + struct list_head hybrid_tuner_instance_list; + struct tuner_i2c_props i2c_props; + + enum tda18271_mode mode; + enum tda18271_role role; + enum tda18271_i2c_gate gate; + enum tda18271_ver id; + + unsigned int tm_rfcal; + unsigned int cal_initialized:1; + unsigned int small_i2c:1; + + struct tda18271_map_layout *maps; + struct tda18271_std_map std; + struct tda18271_rf_tracking_filter_cal rf_cal_state[8]; + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,16) + struct mutex lock; +#else + struct semaphore lock; +#endif + + u32 frequency; + u32 bandwidth; +}; + +/*---------------------------------------------------------------------*/ + +extern int tda18271_debug; + +#define DBG_INFO 1 +#define DBG_MAP 2 +#define DBG_REG 4 +#define DBG_ADV 8 +#define DBG_CAL 16 + +#define tda_printk(kern, fmt, arg...) \ + printk(kern "%s: " fmt, __func__, ##arg) + +#define dprintk(kern, lvl, fmt, arg...) do {\ + if (tda18271_debug & lvl) \ + tda_printk(kern, fmt, ##arg); } while (0) + +#define tda_info(fmt, arg...) printk(KERN_INFO fmt, ##arg) +#define tda_warn(fmt, arg...) tda_printk(KERN_WARNING, fmt, ##arg) +#define tda_err(fmt, arg...) tda_printk(KERN_ERR, fmt, ##arg) +#define tda_dbg(fmt, arg...) dprintk(KERN_DEBUG, DBG_INFO, fmt, ##arg) +#define tda_map(fmt, arg...) dprintk(KERN_DEBUG, DBG_MAP, fmt, ##arg) +#define tda_reg(fmt, arg...) dprintk(KERN_DEBUG, DBG_REG, fmt, ##arg) +#define tda_cal(fmt, arg...) dprintk(KERN_DEBUG, DBG_CAL, fmt, ##arg) + +/*---------------------------------------------------------------------*/ + +enum tda18271_map_type { + /* tda18271_pll_map */ + MAIN_PLL, + CAL_PLL, + /* tda18271_map */ + RF_CAL, + RF_CAL_KMCO, + RF_CAL_DC_OVER_DT, + BP_FILTER, + RF_BAND, + GAIN_TAPER, + IR_MEASURE, +}; + +extern int tda18271_lookup_pll_map(struct dvb_frontend *fe, + enum tda18271_map_type map_type, + u32 *freq, u8 *post_div, u8 *div); +extern int tda18271_lookup_map(struct dvb_frontend *fe, + enum tda18271_map_type map_type, + u32 *freq, u8 *val); + +extern int tda18271_lookup_thermometer(struct dvb_frontend *fe); + +extern int tda18271_lookup_rf_band(struct dvb_frontend *fe, + u32 *freq, u8 *rf_band); + +extern int tda18271_lookup_cid_target(struct dvb_frontend *fe, + u32 *freq, u8 *cid_target, + u16 *count_limit); + +extern int tda18271_assign_map_layout(struct dvb_frontend *fe); + +/*---------------------------------------------------------------------*/ + +extern int tda18271_read_regs(struct dvb_frontend *fe); +extern int tda18271_read_extended(struct dvb_frontend *fe); +extern int tda18271_write_regs(struct dvb_frontend *fe, int idx, int len); +extern int tda18271_init_regs(struct dvb_frontend *fe); + +extern int tda18271_charge_pump_source(struct dvb_frontend *fe, + enum tda18271_pll pll, int force); +extern int tda18271_set_standby_mode(struct dvb_frontend *fe, + int sm, int sm_lt, int sm_xt); + +extern int tda18271_calc_main_pll(struct dvb_frontend *fe, u32 freq); +extern int tda18271_calc_cal_pll(struct dvb_frontend *fe, u32 freq); + +extern int tda18271_calc_bp_filter(struct dvb_frontend *fe, u32 *freq); +extern int tda18271_calc_km(struct dvb_frontend *fe, u32 *freq); +extern int tda18271_calc_rf_band(struct dvb_frontend *fe, u32 *freq); +extern int tda18271_calc_gain_taper(struct dvb_frontend *fe, u32 *freq); +extern int tda18271_calc_ir_measure(struct dvb_frontend *fe, u32 *freq); +extern int tda18271_calc_rf_cal(struct dvb_frontend *fe, u32 *freq); + +#endif /* __TDA18271_PRIV_H__ */ + +/* + * Overrides for Emacs so that we follow Linus's tabbing style. + * --------------------------------------------------------------------------- + * Local variables: + * c-basic-offset: 8 + * End: + */ diff --git a/linux/drivers/media/common/tuners/tda18271.h b/linux/drivers/media/common/tuners/tda18271.h new file mode 100644 index 000000000..0e7af8d05 --- /dev/null +++ b/linux/drivers/media/common/tuners/tda18271.h @@ -0,0 +1,99 @@ +/* + tda18271.h - header for the Philips / NXP TDA18271 silicon tuner + + Copyright (C) 2007, 2008 Michael Krufky + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. +*/ + +#ifndef __TDA18271_H__ +#define __TDA18271_H__ + +#include +#include "dvb_frontend.h" + +struct tda18271_std_map_item { + u16 if_freq; + + /* EP3[4:3] */ + unsigned int agc_mode:2; + /* EP3[2:0] */ + unsigned int std:3; + /* EP4[7] */ + unsigned int fm_rfn:1; + /* EP4[4:2] */ + unsigned int if_lvl:3; + /* EB22[6:0] */ + unsigned int rfagc_top:7; +}; + +struct tda18271_std_map { + struct tda18271_std_map_item fm_radio; + struct tda18271_std_map_item atv_b; + struct tda18271_std_map_item atv_dk; + struct tda18271_std_map_item atv_gh; + struct tda18271_std_map_item atv_i; + struct tda18271_std_map_item atv_l; + struct tda18271_std_map_item atv_lc; + struct tda18271_std_map_item atv_mn; + struct tda18271_std_map_item atsc_6; + struct tda18271_std_map_item dvbt_6; + struct tda18271_std_map_item dvbt_7; + struct tda18271_std_map_item dvbt_8; + struct tda18271_std_map_item qam_6; + struct tda18271_std_map_item qam_8; +}; + +enum tda18271_role { + TDA18271_MASTER = 0, + TDA18271_SLAVE, +}; + +enum tda18271_i2c_gate { + TDA18271_GATE_AUTO = 0, + TDA18271_GATE_ANALOG, + TDA18271_GATE_DIGITAL, +}; + +struct tda18271_config { + /* override default if freq / std settings (optional) */ + struct tda18271_std_map *std_map; + + /* master / slave tuner: master uses main pll, slave uses cal pll */ + enum tda18271_role role; + + /* use i2c gate provided by analog or digital demod */ + enum tda18271_i2c_gate gate; + + /* some i2c providers cant write all 39 registers at once */ + unsigned int small_i2c:1; +}; + +#if defined(CONFIG_DVB_TDA18271) || (defined(CONFIG_DVB_TDA18271_MODULE) && defined(MODULE)) +extern struct dvb_frontend *tda18271_attach(struct dvb_frontend *fe, u8 addr, + struct i2c_adapter *i2c, + struct tda18271_config *cfg); +#else +static inline struct dvb_frontend *tda18271_attach(struct dvb_frontend *fe, + u8 addr, + struct i2c_adapter *i2c, + struct tda18271_config *cfg) +{ + printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__); + return NULL; +} +#endif + +#endif /* __TDA18271_H__ */ diff --git a/linux/drivers/media/common/tuners/tda827x.c b/linux/drivers/media/common/tuners/tda827x.c new file mode 100644 index 000000000..2d39f9be5 --- /dev/null +++ b/linux/drivers/media/common/tuners/tda827x.c @@ -0,0 +1,853 @@ +/* + * + * (c) 2005 Hartmut Hackmann + * (c) 2007 Michael Krufky + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include +#include +#include "compat.h" +#include +#include + +#include "tda827x.h" + +static int debug; +module_param(debug, int, 0644); +MODULE_PARM_DESC(debug, "Turn on/off frontend debugging (default:off)."); + +#define dprintk(args...) \ + do { \ + if (debug) printk(KERN_DEBUG "tda827x: " args); \ + } while (0) + +struct tda827x_priv { + int i2c_addr; + struct i2c_adapter *i2c_adap; + struct tda827x_config *cfg; + + unsigned int sgIF; + unsigned char lpsel; + + u32 frequency; + u32 bandwidth; +}; + +static void tda827x_set_std(struct dvb_frontend *fe, + struct analog_parameters *params) +{ + struct tda827x_priv *priv = fe->tuner_priv; + char *mode; + + priv->lpsel = 0; + if (params->std & V4L2_STD_MN) { + priv->sgIF = 92; + priv->lpsel = 1; + mode = "MN"; + } else if (params->std & V4L2_STD_B) { + priv->sgIF = 108; + mode = "B"; + } else if (params->std & V4L2_STD_GH) { + priv->sgIF = 124; + mode = "GH"; + } else if (params->std & V4L2_STD_PAL_I) { + priv->sgIF = 124; + mode = "I"; + } else if (params->std & V4L2_STD_DK) { + priv->sgIF = 124; + mode = "DK"; + } else if (params->std & V4L2_STD_SECAM_L) { + priv->sgIF = 124; + mode = "L"; + } else if (params->std & V4L2_STD_SECAM_LC) { + priv->sgIF = 20; + mode = "LC"; + } else { + priv->sgIF = 124; + mode = "xx"; + } + + if (params->mode == V4L2_TUNER_RADIO) + priv->sgIF = 88; /* if frequency is 5.5 MHz */ + + dprintk("setting tda827x to system %s\n", mode); +} + + +/* ------------------------------------------------------------------ */ + +struct tda827x_data { + u32 lomax; + u8 spd; + u8 bs; + u8 bp; + u8 cp; + u8 gc3; + u8 div1p5; +}; + +static const struct tda827x_data tda827x_table[] = { + { .lomax = 62000000, .spd = 3, .bs = 2, .bp = 0, .cp = 0, .gc3 = 3, .div1p5 = 1}, + { .lomax = 66000000, .spd = 3, .bs = 3, .bp = 0, .cp = 0, .gc3 = 3, .div1p5 = 1}, + { .lomax = 76000000, .spd = 3, .bs = 1, .bp = 0, .cp = 0, .gc3 = 3, .div1p5 = 0}, + { .lomax = 84000000, .spd = 3, .bs = 2, .bp = 0, .cp = 0, .gc3 = 3, .div1p5 = 0}, + { .lomax = 93000000, .spd = 3, .bs = 2, .bp = 0, .cp = 0, .gc3 = 1, .div1p5 = 0}, + { .lomax = 98000000, .spd = 3, .bs = 3, .bp = 0, .cp = 0, .gc3 = 1, .div1p5 = 0}, + { .lomax = 109000000, .spd = 3, .bs = 3, .bp = 1, .cp = 0, .gc3 = 1, .div1p5 = 0}, + { .lomax = 123000000, .spd = 2, .bs = 2, .bp = 1, .cp = 0, .gc3 = 1, .div1p5 = 1}, + { .lomax = 133000000, .spd = 2, .bs = 3, .bp = 1, .cp = 0, .gc3 = 1, .div1p5 = 1}, + { .lomax = 151000000, .spd = 2, .bs = 1, .bp = 1, .cp = 0, .gc3 = 1, .div1p5 = 0}, + { .lomax = 154000000, .spd = 2, .bs = 2, .bp = 1, .cp = 0, .gc3 = 1, .div1p5 = 0}, + { .lomax = 181000000, .spd = 2, .bs = 2, .bp = 1, .cp = 0, .gc3 = 0, .div1p5 = 0}, + { .lomax = 185000000, .spd = 2, .bs = 2, .bp = 2, .cp = 0, .gc3 = 1, .div1p5 = 0}, + { .lomax = 217000000, .spd = 2, .bs = 3, .bp = 2, .cp = 0, .gc3 = 1, .div1p5 = 0}, + { .lomax = 244000000, .spd = 1, .bs = 2, .bp = 2, .cp = 0, .gc3 = 1, .div1p5 = 1}, + { .lomax = 265000000, .spd = 1, .bs = 3, .bp = 2, .cp = 0, .gc3 = 1, .div1p5 = 1}, + { .lomax = 302000000, .spd = 1, .bs = 1, .bp = 2, .cp = 0, .gc3 = 1, .div1p5 = 0}, + { .lomax = 324000000, .spd = 1, .bs = 2, .bp = 2, .cp = 0, .gc3 = 1, .div1p5 = 0}, + { .lomax = 370000000, .spd = 1, .bs = 2, .bp = 3, .cp = 0, .gc3 = 1, .div1p5 = 0}, + { .lomax = 454000000, .spd = 1, .bs = 3, .bp = 3, .cp = 0, .gc3 = 1, .div1p5 = 0}, + { .lomax = 493000000, .spd = 0, .bs = 2, .bp = 3, .cp = 0, .gc3 = 1, .div1p5 = 1}, + { .lomax = 530000000, .spd = 0, .bs = 3, .bp = 3, .cp = 0, .gc3 = 1, .div1p5 = 1}, + { .lomax = 554000000, .spd = 0, .bs = 1, .bp = 3, .cp = 0, .gc3 = 1, .div1p5 = 0}, + { .lomax = 604000000, .spd = 0, .bs = 1, .bp = 4, .cp = 0, .gc3 = 0, .div1p5 = 0}, + { .lomax = 696000000, .spd = 0, .bs = 2, .bp = 4, .cp = 0, .gc3 = 0, .div1p5 = 0}, + { .lomax = 740000000, .spd = 0, .bs = 2, .bp = 4, .cp = 1, .gc3 = 0, .div1p5 = 0}, + { .lomax = 820000000, .spd = 0, .bs = 3, .bp = 4, .cp = 0, .gc3 = 0, .div1p5 = 0}, + { .lomax = 865000000, .spd = 0, .bs = 3, .bp = 4, .cp = 1, .gc3 = 0, .div1p5 = 0}, + { .lomax = 0, .spd = 0, .bs = 0, .bp = 0, .cp = 0, .gc3 = 0, .div1p5 = 0} +}; + +static int tda827xo_set_params(struct dvb_frontend *fe, + struct dvb_frontend_parameters *params) +{ + struct tda827x_priv *priv = fe->tuner_priv; + u8 buf[14]; + + struct i2c_msg msg = { .addr = priv->i2c_addr, .flags = 0, + .buf = buf, .len = sizeof(buf) }; + int i, tuner_freq, if_freq; + u32 N; + + dprintk("%s:\n", __func__); + switch (params->u.ofdm.bandwidth) { + case BANDWIDTH_6_MHZ: + if_freq = 4000000; + break; + case BANDWIDTH_7_MHZ: + if_freq = 4500000; + break; + default: /* 8 MHz or Auto */ + if_freq = 5000000; + break; + } + tuner_freq = params->frequency + if_freq; + + i = 0; + while (tda827x_table[i].lomax < tuner_freq) { + if (tda827x_table[i + 1].lomax == 0) + break; + i++; + } + + N = ((tuner_freq + 125000) / 250000) << (tda827x_table[i].spd + 2); + buf[0] = 0; + buf[1] = (N>>8) | 0x40; + buf[2] = N & 0xff; + buf[3] = 0; + buf[4] = 0x52; + buf[5] = (tda827x_table[i].spd << 6) + (tda827x_table[i].div1p5 << 5) + + (tda827x_table[i].bs << 3) + + tda827x_table[i].bp; + buf[6] = (tda827x_table[i].gc3 << 4) + 0x8f; + buf[7] = 0xbf; + buf[8] = 0x2a; + buf[9] = 0x05; + buf[10] = 0xff; + buf[11] = 0x00; + buf[12] = 0x00; + buf[13] = 0x40; + + msg.len = 14; + if (fe->ops.i2c_gate_ctrl) + fe->ops.i2c_gate_ctrl(fe, 1); + if (i2c_transfer(priv->i2c_adap, &msg, 1) != 1) { + printk("%s: could not write to tuner at addr: 0x%02x\n", + __func__, priv->i2c_addr << 1); + return -EIO; + } + msleep(500); + /* correct CP value */ + buf[0] = 0x30; + buf[1] = 0x50 + tda827x_table[i].cp; + msg.len = 2; + + if (fe->ops.i2c_gate_ctrl) + fe->ops.i2c_gate_ctrl(fe, 1); + i2c_transfer(priv->i2c_adap, &msg, 1); + + priv->frequency = tuner_freq - if_freq; // FIXME + priv->bandwidth = (fe->ops.info.type == FE_OFDM) ? params->u.ofdm.bandwidth : 0; + + return 0; +} + +static int tda827xo_sleep(struct dvb_frontend *fe) +{ + struct tda827x_priv *priv = fe->tuner_priv; + static u8 buf[] = { 0x30, 0xd0 }; + struct i2c_msg msg = { .addr = priv->i2c_addr, .flags = 0, + .buf = buf, .len = sizeof(buf) }; + + dprintk("%s:\n", __func__); + if (fe->ops.i2c_gate_ctrl) + fe->ops.i2c_gate_ctrl(fe, 1); + i2c_transfer(priv->i2c_adap, &msg, 1); + + if (priv->cfg && priv->cfg->sleep) + priv->cfg->sleep(fe); + + return 0; +} + +/* ------------------------------------------------------------------ */ + +static int tda827xo_set_analog_params(struct dvb_frontend *fe, + struct analog_parameters *params) +{ + unsigned char tuner_reg[8]; + unsigned char reg2[2]; + u32 N; + int i; + struct tda827x_priv *priv = fe->tuner_priv; + struct i2c_msg msg = { .addr = priv->i2c_addr, .flags = 0 }; + unsigned int freq = params->frequency; + + tda827x_set_std(fe, params); + + if (params->mode == V4L2_TUNER_RADIO) + freq = freq / 1000; + + N = freq + priv->sgIF; + + i = 0; + while (tda827x_table[i].lomax < N * 62500) { + if (tda827x_table[i + 1].lomax == 0) + break; + i++; + } + + N = N << tda827x_table[i].spd; + + tuner_reg[0] = 0; + tuner_reg[1] = (unsigned char)(N>>8); + tuner_reg[2] = (unsigned char) N; + tuner_reg[3] = 0x40; + tuner_reg[4] = 0x52 + (priv->lpsel << 5); + tuner_reg[5] = (tda827x_table[i].spd << 6) + + (tda827x_table[i].div1p5 << 5) + + (tda827x_table[i].bs << 3) + tda827x_table[i].bp; + tuner_reg[6] = 0x8f + (tda827x_table[i].gc3 << 4); + tuner_reg[7] = 0x8f; + + msg.buf = tuner_reg; + msg.len = 8; + i2c_transfer(priv->i2c_adap, &msg, 1); + + msg.buf = reg2; + msg.len = 2; + reg2[0] = 0x80; + reg2[1] = 0; + i2c_transfer(priv->i2c_adap, &msg, 1); + + reg2[0] = 0x60; + reg2[1] = 0xbf; + i2c_transfer(priv->i2c_adap, &msg, 1); + + reg2[0] = 0x30; + reg2[1] = tuner_reg[4] + 0x80; + i2c_transfer(priv->i2c_adap, &msg, 1); + + msleep(1); + reg2[0] = 0x30; + reg2[1] = tuner_reg[4] + 4; + i2c_transfer(priv->i2c_adap, &msg, 1); + + msleep(1); + reg2[0] = 0x30; + reg2[1] = tuner_reg[4]; + i2c_transfer(priv->i2c_adap, &msg, 1); + + msleep(550); + reg2[0] = 0x30; + reg2[1] = (tuner_reg[4] & 0xfc) + tda827x_table[i].cp; + i2c_transfer(priv->i2c_adap, &msg, 1); + + reg2[0] = 0x60; + reg2[1] = 0x3f; + i2c_transfer(priv->i2c_adap, &msg, 1); + + reg2[0] = 0x80; + reg2[1] = 0x08; /* Vsync en */ + i2c_transfer(priv->i2c_adap, &msg, 1); + + priv->frequency = freq * 62500; + + return 0; +} + +static void tda827xo_agcf(struct dvb_frontend *fe) +{ + struct tda827x_priv *priv = fe->tuner_priv; + unsigned char data[] = { 0x80, 0x0c }; + struct i2c_msg msg = { .addr = priv->i2c_addr, .flags = 0, + .buf = data, .len = 2}; + + i2c_transfer(priv->i2c_adap, &msg, 1); +} + +/* ------------------------------------------------------------------ */ + +struct tda827xa_data { + u32 lomax; + u8 svco; + u8 spd; + u8 scr; + u8 sbs; + u8 gc3; +}; + +static const struct tda827xa_data tda827xa_dvbt[] = { + { .lomax = 56875000, .svco = 3, .spd = 4, .scr = 0, .sbs = 0, .gc3 = 1}, + { .lomax = 67250000, .svco = 0, .spd = 3, .scr = 0, .sbs = 0, .gc3 = 1}, + { .lomax = 81250000, .svco = 1, .spd = 3, .scr = 0, .sbs = 0, .gc3 = 1}, + { .lomax = 97500000, .svco = 2, .spd = 3, .scr = 0, .sbs = 0, .gc3 = 1}, + { .lomax = 113750000, .svco = 3, .spd = 3, .scr = 0, .sbs = 1, .gc3 = 1}, + { .lomax = 134500000, .svco = 0, .spd = 2, .scr = 0, .sbs = 1, .gc3 = 1}, + { .lomax = 154000000, .svco = 1, .spd = 2, .scr = 0, .sbs = 1, .gc3 = 1}, + { .lomax = 162500000, .svco = 1, .spd = 2, .scr = 0, .sbs = 1, .gc3 = 1}, + { .lomax = 183000000, .svco = 2, .spd = 2, .scr = 0, .sbs = 1, .gc3 = 1}, + { .lomax = 195000000, .svco = 2, .spd = 2, .scr = 0, .sbs = 2, .gc3 = 1}, + { .lomax = 227500000, .svco = 3, .spd = 2, .scr = 0, .sbs = 2, .gc3 = 1}, + { .lomax = 269000000, .svco = 0, .spd = 1, .scr = 0, .sbs = 2, .gc3 = 1}, + { .lomax = 290000000, .svco = 1, .spd = 1, .scr = 0, .sbs = 2, .gc3 = 1}, + { .lomax = 325000000, .svco = 1, .spd = 1, .scr = 0, .sbs = 3, .gc3 = 1}, + { .lomax = 390000000, .svco = 2, .spd = 1, .scr = 0, .sbs = 3, .gc3 = 1}, + { .lomax = 455000000, .svco = 3, .spd = 1, .scr = 0, .sbs = 3, .gc3 = 1}, + { .lomax = 520000000, .svco = 0, .spd = 0, .scr = 0, .sbs = 3, .gc3 = 1}, + { .lomax = 538000000, .svco = 0, .spd = 0, .scr = 1, .sbs = 3, .gc3 = 1}, + { .lomax = 550000000, .svco = 1, .spd = 0, .scr = 0, .sbs = 3, .gc3 = 1}, + { .lomax = 620000000, .svco = 1, .spd = 0, .scr = 0, .sbs = 4, .gc3 = 0}, + { .lomax = 650000000, .svco = 1, .spd = 0, .scr = 1, .sbs = 4, .gc3 = 0}, + { .lomax = 700000000, .svco = 2, .spd = 0, .scr = 0, .sbs = 4, .gc3 = 0}, + { .lomax = 780000000, .svco = 2, .spd = 0, .scr = 1, .sbs = 4, .gc3 = 0}, + { .lomax = 820000000, .svco = 3, .spd = 0, .scr = 0, .sbs = 4, .gc3 = 0}, + { .lomax = 870000000, .svco = 3, .spd = 0, .scr = 1, .sbs = 4, .gc3 = 0}, + { .lomax = 911000000, .svco = 3, .spd = 0, .scr = 2, .sbs = 4, .gc3 = 0}, + { .lomax = 0, .svco = 0, .spd = 0, .scr = 0, .sbs = 0, .gc3 = 0} +}; + +static struct tda827xa_data tda827xa_analog[] = { + { .lomax = 56875000, .svco = 3, .spd = 4, .scr = 0, .sbs = 0, .gc3 = 3}, + { .lomax = 67250000, .svco = 0, .spd = 3, .scr = 0, .sbs = 0, .gc3 = 3}, + { .lomax = 81250000, .svco = 1, .spd = 3, .scr = 0, .sbs = 0, .gc3 = 3}, + { .lomax = 97500000, .svco = 2, .spd = 3, .scr = 0, .sbs = 0, .gc3 = 3}, + { .lomax = 113750000, .svco = 3, .spd = 3, .scr = 0, .sbs = 1, .gc3 = 1}, + { .lomax = 134500000, .svco = 0, .spd = 2, .scr = 0, .sbs = 1, .gc3 = 1}, + { .lomax = 154000000, .svco = 1, .spd = 2, .scr = 0, .sbs = 1, .gc3 = 1}, + { .lomax = 162500000, .svco = 1, .spd = 2, .scr = 0, .sbs = 1, .gc3 = 1}, + { .lomax = 183000000, .svco = 2, .spd = 2, .scr = 0, .sbs = 1, .gc3 = 1}, + { .lomax = 195000000, .svco = 2, .spd = 2, .scr = 0, .sbs = 2, .gc3 = 1}, + { .lomax = 227500000, .svco = 3, .spd = 2, .scr = 0, .sbs = 2, .gc3 = 3}, + { .lomax = 269000000, .svco = 0, .spd = 1, .scr = 0, .sbs = 2, .gc3 = 3}, + { .lomax = 325000000, .svco = 1, .spd = 1, .scr = 0, .sbs = 2, .gc3 = 1}, + { .lomax = 390000000, .svco = 2, .spd = 1, .scr = 0, .sbs = 3, .gc3 = 3}, + { .lomax = 455000000, .svco = 3, .spd = 1, .scr = 0, .sbs = 3, .gc3 = 3}, + { .lomax = 520000000, .svco = 0, .spd = 0, .scr = 0, .sbs = 3, .gc3 = 1}, + { .lomax = 538000000, .svco = 0, .spd = 0, .scr = 1, .sbs = 3, .gc3 = 1}, + { .lomax = 554000000, .svco = 1, .spd = 0, .scr = 0, .sbs = 3, .gc3 = 1}, + { .lomax = 620000000, .svco = 1, .spd = 0, .scr = 0, .sbs = 4, .gc3 = 0}, + { .lomax = 650000000, .svco = 1, .spd = 0, .scr = 1, .sbs = 4, .gc3 = 0}, + { .lomax = 700000000, .svco = 2, .spd = 0, .scr = 0, .sbs = 4, .gc3 = 0}, + { .lomax = 780000000, .svco = 2, .spd = 0, .scr = 1, .sbs = 4, .gc3 = 0}, + { .lomax = 820000000, .svco = 3, .spd = 0, .scr = 0, .sbs = 4, .gc3 = 0}, + { .lomax = 870000000, .svco = 3, .spd = 0, .scr = 1, .sbs = 4, .gc3 = 0}, + { .lomax = 911000000, .svco = 3, .spd = 0, .scr = 2, .sbs = 4, .gc3 = 0}, + { .lomax = 0, .svco = 0, .spd = 0, .scr = 0, .sbs = 0, .gc3 = 0} +}; + +static int tda827xa_sleep(struct dvb_frontend *fe) +{ + struct tda827x_priv *priv = fe->tuner_priv; + static u8 buf[] = { 0x30, 0x90 }; + struct i2c_msg msg = { .addr = priv->i2c_addr, .flags = 0, + .buf = buf, .len = sizeof(buf) }; + + dprintk("%s:\n", __func__); + if (fe->ops.i2c_gate_ctrl) + fe->ops.i2c_gate_ctrl(fe, 1); + + i2c_transfer(priv->i2c_adap, &msg, 1); + + if (fe->ops.i2c_gate_ctrl) + fe->ops.i2c_gate_ctrl(fe, 0); + + if (priv->cfg && priv->cfg->sleep) + priv->cfg->sleep(fe); + + return 0; +} + +static void tda827xa_lna_gain(struct dvb_frontend *fe, int high, + struct analog_parameters *params) +{ + struct tda827x_priv *priv = fe->tuner_priv; + unsigned char buf[] = {0x22, 0x01}; + int arg; + int gp_func; + struct i2c_msg msg = { .addr = priv->cfg->switch_addr, .flags = 0, + .buf = buf, .len = sizeof(buf) }; + + if (NULL == priv->cfg) { + dprintk("tda827x_config not defined, cannot set LNA gain!\n"); + return; + } + if (priv->cfg->config) { + if (high) + dprintk("setting LNA to high gain\n"); + else + dprintk("setting LNA to low gain\n"); + } + switch (priv->cfg->config) { + case 0: /* no LNA */ + break; + case 1: /* switch is GPIO 0 of tda8290 */ + case 2: + if (params == NULL) { + gp_func = 0; + arg = 0; + } else { + /* turn Vsync on */ + gp_func = 1; + if (params->std & V4L2_STD_MN) + arg = 1; + else + arg = 0; + } + if (priv->cfg->tuner_callback) + priv->cfg->tuner_callback(priv->i2c_adap->algo_data, + gp_func, arg); + buf[1] = high ? 0 : 1; + if (priv->cfg->config == 2) + buf[1] = high ? 1 : 0; + i2c_transfer(priv->i2c_adap, &msg, 1); + break; + case 3: /* switch with GPIO of saa713x */ + if (priv->cfg->tuner_callback) + priv->cfg->tuner_callback(priv->i2c_adap->algo_data, 0, high); + break; + } +} + +static int tda827xa_set_params(struct dvb_frontend *fe, + struct dvb_frontend_parameters *params) +{ + struct tda827x_priv *priv = fe->tuner_priv; + u8 buf[11]; + + struct i2c_msg msg = { .addr = priv->i2c_addr, .flags = 0, + .buf = buf, .len = sizeof(buf) }; + + int i, tuner_freq, if_freq; + u32 N; + + dprintk("%s:\n", __func__); + + tda827xa_lna_gain(fe, 1, NULL); + msleep(20); + + switch (params->u.ofdm.bandwidth) { + case BANDWIDTH_6_MHZ: + if_freq = 4000000; + break; + case BANDWIDTH_7_MHZ: + if_freq = 4500000; + break; + default: /* 8 MHz or Auto */ + if_freq = 5000000; + break; + } + tuner_freq = params->frequency + if_freq; + + i = 0; + while (tda827xa_dvbt[i].lomax < tuner_freq) { + if(tda827xa_dvbt[i + 1].lomax == 0) + break; + i++; + } + + N = ((tuner_freq + 31250) / 62500) << tda827xa_dvbt[i].spd; + buf[0] = 0; // subaddress + buf[1] = N >> 8; + buf[2] = N & 0xff; + buf[3] = 0; + buf[4] = 0x16; + buf[5] = (tda827xa_dvbt[i].spd << 5) + (tda827xa_dvbt[i].svco << 3) + + tda827xa_dvbt[i].sbs; + buf[6] = 0x4b + (tda827xa_dvbt[i].gc3 << 4); + buf[7] = 0x1c; + buf[8] = 0x06; + buf[9] = 0x24; + buf[10] = 0x00; + msg.len = 11; + if (fe->ops.i2c_gate_ctrl) + fe->ops.i2c_gate_ctrl(fe, 1); + if (i2c_transfer(priv->i2c_adap, &msg, 1) != 1) { + printk("%s: could not write to tuner at addr: 0x%02x\n", + __func__, priv->i2c_addr << 1); + return -EIO; + } + buf[0] = 0x90; + buf[1] = 0xff; + buf[2] = 0x60; + buf[3] = 0x00; + buf[4] = 0x59; // lpsel, for 6MHz + 2 + msg.len = 5; + if (fe->ops.i2c_gate_ctrl) + fe->ops.i2c_gate_ctrl(fe, 1); + i2c_transfer(priv->i2c_adap, &msg, 1); + + buf[0] = 0xa0; + buf[1] = 0x40; + msg.len = 2; + if (fe->ops.i2c_gate_ctrl) + fe->ops.i2c_gate_ctrl(fe, 1); + i2c_transfer(priv->i2c_adap, &msg, 1); + + msleep(11); + msg.flags = I2C_M_RD; + if (fe->ops.i2c_gate_ctrl) + fe->ops.i2c_gate_ctrl(fe, 1); + i2c_transfer(priv->i2c_adap, &msg, 1); + msg.flags = 0; + + buf[1] >>= 4; + dprintk("tda8275a AGC2 gain is: %d\n", buf[1]); + if ((buf[1]) < 2) { + tda827xa_lna_gain(fe, 0, NULL); + buf[0] = 0x60; + buf[1] = 0x0c; + if (fe->ops.i2c_gate_ctrl) + fe->ops.i2c_gate_ctrl(fe, 1); + i2c_transfer(priv->i2c_adap, &msg, 1); + } + + buf[0] = 0xc0; + buf[1] = 0x99; // lpsel, for 6MHz + 2 + if (fe->ops.i2c_gate_ctrl) + fe->ops.i2c_gate_ctrl(fe, 1); + i2c_transfer(priv->i2c_adap, &msg, 1); + + buf[0] = 0x60; + buf[1] = 0x3c; + if (fe->ops.i2c_gate_ctrl) + fe->ops.i2c_gate_ctrl(fe, 1); + i2c_transfer(priv->i2c_adap, &msg, 1); + + /* correct CP value */ + buf[0] = 0x30; + buf[1] = 0x10 + tda827xa_dvbt[i].scr; + if (fe->ops.i2c_gate_ctrl) + fe->ops.i2c_gate_ctrl(fe, 1); + i2c_transfer(priv->i2c_adap, &msg, 1); + + msleep(163); + buf[0] = 0xc0; + buf[1] = 0x39; // lpsel, for 6MHz + 2 + if (fe->ops.i2c_gate_ctrl) + fe->ops.i2c_gate_ctrl(fe, 1); + i2c_transfer(priv->i2c_adap, &msg, 1); + + msleep(3); + /* freeze AGC1 */ + buf[0] = 0x50; + buf[1] = 0x4f + (tda827xa_dvbt[i].gc3 << 4); + if (fe->ops.i2c_gate_ctrl) + fe->ops.i2c_gate_ctrl(fe, 1); + i2c_transfer(priv->i2c_adap, &msg, 1); + + priv->frequency = tuner_freq - if_freq; // FIXME + priv->bandwidth = (fe->ops.info.type == FE_OFDM) ? params->u.ofdm.bandwidth : 0; + + return 0; +} + + +static int tda827xa_set_analog_params(struct dvb_frontend *fe, + struct analog_parameters *params) +{ + unsigned char tuner_reg[11]; + u32 N; + int i; + struct tda827x_priv *priv = fe->tuner_priv; + struct i2c_msg msg = { .addr = priv->i2c_addr, .flags = 0, + .buf = tuner_reg, .len = sizeof(tuner_reg) }; + unsigned int freq = params->frequency; + + tda827x_set_std(fe, params); + + tda827xa_lna_gain(fe, 1, params); + msleep(10); + + if (params->mode == V4L2_TUNER_RADIO) + freq = freq / 1000; + + N = freq + priv->sgIF; + + i = 0; + while (tda827xa_analog[i].lomax < N * 62500) { + if (tda827xa_analog[i + 1].lomax == 0) + break; + i++; + } + + N = N << tda827xa_analog[i].spd; + + tuner_reg[0] = 0; + tuner_reg[1] = (unsigned char)(N>>8); + tuner_reg[2] = (unsigned char) N; + tuner_reg[3] = 0; + tuner_reg[4] = 0x16; + tuner_reg[5] = (tda827xa_analog[i].spd << 5) + + (tda827xa_analog[i].svco << 3) + + tda827xa_analog[i].sbs; + tuner_reg[6] = 0x8b + (tda827xa_analog[i].gc3 << 4); + tuner_reg[7] = 0x1c; + tuner_reg[8] = 4; + tuner_reg[9] = 0x20; + tuner_reg[10] = 0x00; + msg.len = 11; + i2c_transfer(priv->i2c_adap, &msg, 1); + + tuner_reg[0] = 0x90; + tuner_reg[1] = 0xff; + tuner_reg[2] = 0xe0; + tuner_reg[3] = 0; + tuner_reg[4] = 0x99 + (priv->lpsel << 1); + msg.len = 5; + i2c_transfer(priv->i2c_adap, &msg, 1); + + tuner_reg[0] = 0xa0; + tuner_reg[1] = 0xc0; + msg.len = 2; + i2c_transfer(priv->i2c_adap, &msg, 1); + + tuner_reg[0] = 0x30; + tuner_reg[1] = 0x10 + tda827xa_analog[i].scr; + i2c_transfer(priv->i2c_adap, &msg, 1); + + msg.flags = I2C_M_RD; + i2c_transfer(priv->i2c_adap, &msg, 1); + msg.flags = 0; + tuner_reg[1] >>= 4; + dprintk("AGC2 gain is: %d\n", tuner_reg[1]); + if (tuner_reg[1] < 1) + tda827xa_lna_gain(fe, 0, params); + + msleep(100); + tuner_reg[0] = 0x60; + tuner_reg[1] = 0x3c; + i2c_transfer(priv->i2c_adap, &msg, 1); + + msleep(163); + tuner_reg[0] = 0x50; + tuner_reg[1] = 0x8f + (tda827xa_analog[i].gc3 << 4); + i2c_transfer(priv->i2c_adap, &msg, 1); + + tuner_reg[0] = 0x80; + tuner_reg[1] = 0x28; + i2c_transfer(priv->i2c_adap, &msg, 1); + + tuner_reg[0] = 0xb0; + tuner_reg[1] = 0x01; + i2c_transfer(priv->i2c_adap, &msg, 1); + + tuner_reg[0] = 0xc0; + tuner_reg[1] = 0x19 + (priv->lpsel << 1); + i2c_transfer(priv->i2c_adap, &msg, 1); + + priv->frequency = freq * 62500; + + return 0; +} + +static void tda827xa_agcf(struct dvb_frontend *fe) +{ + struct tda827x_priv *priv = fe->tuner_priv; + unsigned char data[] = {0x80, 0x2c}; + struct i2c_msg msg = {.addr = priv->i2c_addr, .flags = 0, + .buf = data, .len = 2}; + i2c_transfer(priv->i2c_adap, &msg, 1); +} + +/* ------------------------------------------------------------------ */ + +static int tda827x_release(struct dvb_frontend *fe) +{ + kfree(fe->tuner_priv); + fe->tuner_priv = NULL; + return 0; +} + +static int tda827x_get_frequency(struct dvb_frontend *fe, u32 *frequency) +{ + struct tda827x_priv *priv = fe->tuner_priv; + *frequency = priv->frequency; + return 0; +} + +static int tda827x_get_bandwidth(struct dvb_frontend *fe, u32 *bandwidth) +{ + struct tda827x_priv *priv = fe->tuner_priv; + *bandwidth = priv->bandwidth; + return 0; +} + +static int tda827x_init(struct dvb_frontend *fe) +{ + struct tda827x_priv *priv = fe->tuner_priv; + dprintk("%s:\n", __func__); + if (priv->cfg && priv->cfg->init) + priv->cfg->init(fe); + + return 0; +} + +static int tda827x_probe_version(struct dvb_frontend *fe); + +static int tda827x_initial_init(struct dvb_frontend *fe) +{ + int ret; + ret = tda827x_probe_version(fe); + if (ret) + return ret; + return fe->ops.tuner_ops.init(fe); +} + +static int tda827x_initial_sleep(struct dvb_frontend *fe) +{ + int ret; + ret = tda827x_probe_version(fe); + if (ret) + return ret; + return fe->ops.tuner_ops.sleep(fe); +} + +static struct dvb_tuner_ops tda827xo_tuner_ops = { + .info = { + .name = "Philips TDA827X", + .frequency_min = 55000000, + .frequency_max = 860000000, + .frequency_step = 250000 + }, + .release = tda827x_release, + .init = tda827x_initial_init, + .sleep = tda827x_initial_sleep, + .set_params = tda827xo_set_params, + .set_analog_params = tda827xo_set_analog_params, + .get_frequency = tda827x_get_frequency, + .get_bandwidth = tda827x_get_bandwidth, +}; + +static struct dvb_tuner_ops tda827xa_tuner_ops = { + .info = { + .name = "Philips TDA827XA", + .frequency_min = 44000000, + .frequency_max = 906000000, + .frequency_step = 62500 + }, + .release = tda827x_release, + .init = tda827x_init, + .sleep = tda827xa_sleep, + .set_params = tda827xa_set_params, + .set_analog_params = tda827xa_set_analog_params, + .get_frequency = tda827x_get_frequency, + .get_bandwidth = tda827x_get_bandwidth, +}; + +static int tda827x_probe_version(struct dvb_frontend *fe) +{ u8 data; + struct tda827x_priv *priv = fe->tuner_priv; + struct i2c_msg msg = { .addr = priv->i2c_addr, .flags = I2C_M_RD, + .buf = &data, .len = 1 }; + if (fe->ops.i2c_gate_ctrl) + fe->ops.i2c_gate_ctrl(fe, 1); + if (i2c_transfer(priv->i2c_adap, &msg, 1) != 1) { + printk("%s: could not read from tuner at addr: 0x%02x\n", + __func__, msg.addr << 1); + return -EIO; + } + if ((data & 0x3c) == 0) { + dprintk("tda827x tuner found\n"); + fe->ops.tuner_ops.init = tda827x_init; + fe->ops.tuner_ops.sleep = tda827xo_sleep; + if (priv->cfg) + priv->cfg->agcf = tda827xo_agcf; + } else { + dprintk("tda827xa tuner found\n"); + memcpy(&fe->ops.tuner_ops, &tda827xa_tuner_ops, sizeof(struct dvb_tuner_ops)); + if (priv->cfg) + priv->cfg->agcf = tda827xa_agcf; + } + return 0; +} + +struct dvb_frontend *tda827x_attach(struct dvb_frontend *fe, int addr, + struct i2c_adapter *i2c, + struct tda827x_config *cfg) +{ + struct tda827x_priv *priv = NULL; + + dprintk("%s:\n", __func__); + priv = kzalloc(sizeof(struct tda827x_priv), GFP_KERNEL); + if (priv == NULL) + return NULL; + + priv->i2c_addr = addr; + priv->i2c_adap = i2c; + priv->cfg = cfg; + memcpy(&fe->ops.tuner_ops, &tda827xo_tuner_ops, sizeof(struct dvb_tuner_ops)); + fe->tuner_priv = priv; + + dprintk("type set to %s\n", fe->ops.tuner_ops.info.name); + + return fe; +} +EXPORT_SYMBOL_GPL(tda827x_attach); + +MODULE_DESCRIPTION("DVB TDA827x driver"); +MODULE_AUTHOR("Hartmut Hackmann "); +MODULE_AUTHOR("Michael Krufky "); +MODULE_LICENSE("GPL"); + +/* + * Overrides for Emacs so that we follow Linus's tabbing style. + * --------------------------------------------------------------------------- + * Local variables: + * c-basic-offset: 8 + * End: + */ diff --git a/linux/drivers/media/common/tuners/tda827x.h b/linux/drivers/media/common/tuners/tda827x.h new file mode 100644 index 000000000..b73c23570 --- /dev/null +++ b/linux/drivers/media/common/tuners/tda827x.h @@ -0,0 +1,69 @@ + /* + DVB Driver for Philips tda827x / tda827xa Silicon tuners + + (c) 2005 Hartmut Hackmann + (c) 2007 Michael Krufky + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + + */ + +#ifndef __DVB_TDA827X_H__ +#define __DVB_TDA827X_H__ + +#include +#include "dvb_frontend.h" + +struct tda827x_config +{ + /* saa7134 - provided callbacks */ + int (*init) (struct dvb_frontend *fe); + int (*sleep) (struct dvb_frontend *fe); + + /* interface to tda829x driver */ + unsigned int config; + int switch_addr; + int (*tuner_callback) (void *dev, int command, int arg); + + void (*agcf)(struct dvb_frontend *fe); +}; + + +/** + * Attach a tda827x tuner to the supplied frontend structure. + * + * @param fe Frontend to attach to. + * @param addr i2c address of the tuner. + * @param i2c i2c adapter to use. + * @param cfg optional callback function pointers. + * @return FE pointer on success, NULL on failure. + */ +#if defined(CONFIG_DVB_TDA827X) || (defined(CONFIG_DVB_TDA827X_MODULE) && defined(MODULE)) +extern struct dvb_frontend* tda827x_attach(struct dvb_frontend *fe, int addr, + struct i2c_adapter *i2c, + struct tda827x_config *cfg); +#else +static inline struct dvb_frontend* tda827x_attach(struct dvb_frontend *fe, + int addr, + struct i2c_adapter *i2c, + struct tda827x_config *cfg) +{ + printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__); + return NULL; +} +#endif // CONFIG_DVB_TDA827X + +#endif // __DVB_TDA827X_H__ diff --git a/linux/drivers/media/common/tuners/tda8290.c b/linux/drivers/media/common/tuners/tda8290.c new file mode 100644 index 000000000..d57602d22 --- /dev/null +++ b/linux/drivers/media/common/tuners/tda8290.c @@ -0,0 +1,833 @@ +/* + + i2c tv tuner chip device driver + controls the philips tda8290+75 tuner chip combo. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + + This "tda8290" module was split apart from the original "tuner" module. +*/ + +#include +#include +#include "compat.h" +#include +#include "tuner-i2c.h" +#include "tda8290.h" +#include "tda827x.h" +#include "tda18271.h" +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0) +#include "i2c-compat.h" +#endif + +static int debug; +module_param(debug, int, 0644); +MODULE_PARM_DESC(debug, "enable verbose debug messages"); + +/* ---------------------------------------------------------------------- */ + +struct tda8290_priv { + struct tuner_i2c_props i2c_props; + + unsigned char tda8290_easy_mode; + + unsigned char tda827x_addr; + + unsigned char ver; +#define TDA8290 1 +#define TDA8295 2 +#define TDA8275 4 +#define TDA8275A 8 +#define TDA18271 16 + + struct tda827x_config cfg; +}; + +/*---------------------------------------------------------------------*/ + +static int tda8290_i2c_bridge(struct dvb_frontend *fe, int close) +{ + struct tda8290_priv *priv = fe->analog_demod_priv; + + unsigned char enable[2] = { 0x21, 0xC0 }; + unsigned char disable[2] = { 0x21, 0x00 }; + unsigned char *msg; + + if (close) { + msg = enable; + tuner_i2c_xfer_send(&priv->i2c_props, msg, 2); + /* let the bridge stabilize */ + msleep(20); + } else { + msg = disable; + tuner_i2c_xfer_send(&priv->i2c_props, msg, 2); + } + + return 0; +} + +#if 1 +static int tda8295_i2c_bridge(struct dvb_frontend *fe, int close) +{ + struct tda8290_priv *priv = fe->analog_demod_priv; + + unsigned char enable[2] = { 0x45, 0xc1 }; + unsigned char disable[2] = { 0x46, 0x00 }; + unsigned char buf[3] = { 0x45, 0x01, 0x00 }; + unsigned char *msg; + + if (close) { + msg = enable; + tuner_i2c_xfer_send(&priv->i2c_props, msg, 2); + /* let the bridge stabilize */ + msleep(20); + } else { + msg = disable; + tuner_i2c_xfer_send(&priv->i2c_props, msg, 1); + tuner_i2c_xfer_recv(&priv->i2c_props, &msg[1], 1); + + buf[2] = msg[1]; + buf[2] &= ~0x04; + tuner_i2c_xfer_send(&priv->i2c_props, buf, 3); + msleep(5); + + msg[1] |= 0x04; + tuner_i2c_xfer_send(&priv->i2c_props, msg, 2); + } + + return 0; +} +#else +static int tda8295_i2c_bridge(struct dvb_frontend *fe, int close) +{ + struct tda8290_priv *priv = fe->analog_demod_priv; + + unsigned char buf[] = { 0x45, 0x00 }; + + tuner_i2c_xfer_send(&priv->i2c_props, &buf[0], 1); + tuner_i2c_xfer_recv(&priv->i2c_props, &buf[1], 1); + + buf[1] &= 0x3f; + if (close) + buf[1] |= 0xc0; + else + buf[1] |= 0x80; + + tuner_i2c_xfer_send(&priv->i2c_props, buf, 2); + + return 0; +} +#endif + +/*---------------------------------------------------------------------*/ + +static void set_audio(struct dvb_frontend *fe, + struct analog_parameters *params) +{ + struct tda8290_priv *priv = fe->analog_demod_priv; + char* mode; + + if (params->std & V4L2_STD_MN) { + priv->tda8290_easy_mode = 0x01; + mode = "MN"; + } else if (params->std & V4L2_STD_B) { + priv->tda8290_easy_mode = 0x02; + mode = "B"; + } else if (params->std & V4L2_STD_GH) { + priv->tda8290_easy_mode = 0x04; + mode = "GH"; + } else if (params->std & V4L2_STD_PAL_I) { + priv->tda8290_easy_mode = 0x08; + mode = "I"; + } else if (params->std & V4L2_STD_DK) { + priv->tda8290_easy_mode = 0x10; + mode = "DK"; + } else if (params->std & V4L2_STD_SECAM_L) { + priv->tda8290_easy_mode = 0x20; + mode = "L"; + } else if (params->std & V4L2_STD_SECAM_LC) { + priv->tda8290_easy_mode = 0x40; + mode = "LC"; + } else { + priv->tda8290_easy_mode = 0x10; + mode = "xx"; + } + + tuner_dbg("setting tda829x to system %s\n", mode); +} + +static void tda8290_set_params(struct dvb_frontend *fe, + struct analog_parameters *params) +{ + struct tda8290_priv *priv = fe->analog_demod_priv; + + unsigned char soft_reset[] = { 0x00, 0x00 }; + unsigned char easy_mode[] = { 0x01, priv->tda8290_easy_mode }; + unsigned char expert_mode[] = { 0x01, 0x80 }; + unsigned char agc_out_on[] = { 0x02, 0x00 }; + unsigned char gainset_off[] = { 0x28, 0x14 }; + unsigned char if_agc_spd[] = { 0x0f, 0x88 }; + unsigned char adc_head_6[] = { 0x05, 0x04 }; + unsigned char adc_head_9[] = { 0x05, 0x02 }; + unsigned char adc_head_12[] = { 0x05, 0x01 }; + unsigned char pll_bw_nom[] = { 0x0d, 0x47 }; + unsigned char pll_bw_low[] = { 0x0d, 0x27 }; + unsigned char gainset_2[] = { 0x28, 0x64 }; + unsigned char agc_rst_on[] = { 0x0e, 0x0b }; + unsigned char agc_rst_off[] = { 0x0e, 0x09 }; + unsigned char if_agc_set[] = { 0x0f, 0x81 }; + unsigned char addr_adc_sat = 0x1a; + unsigned char addr_agc_stat = 0x1d; + unsigned char addr_pll_stat = 0x1b; + unsigned char adc_sat, agc_stat, + pll_stat; + int i; + + set_audio(fe, params); + + if (priv->cfg.config) + tuner_dbg("tda827xa config is 0x%02x\n", priv->cfg.config); + tuner_i2c_xfer_send(&priv->i2c_props, easy_mode, 2); + tuner_i2c_xfer_send(&priv->i2c_props, agc_out_on, 2); + tuner_i2c_xfer_send(&priv->i2c_props, soft_reset, 2); + msleep(1); + + expert_mode[1] = priv->tda8290_easy_mode + 0x80; + tuner_i2c_xfer_send(&priv->i2c_props, expert_mode, 2); + tuner_i2c_xfer_send(&priv->i2c_props, gainset_off, 2); + tuner_i2c_xfer_send(&priv->i2c_props, if_agc_spd, 2); + if (priv->tda8290_easy_mode & 0x60) + tuner_i2c_xfer_send(&priv->i2c_props, adc_head_9, 2); + else + tuner_i2c_xfer_send(&priv->i2c_props, adc_head_6, 2); + tuner_i2c_xfer_send(&priv->i2c_props, pll_bw_nom, 2); + + tda8290_i2c_bridge(fe, 1); + + if (fe->ops.tuner_ops.set_analog_params) + fe->ops.tuner_ops.set_analog_params(fe, params); + + for (i = 0; i < 3; i++) { + tuner_i2c_xfer_send(&priv->i2c_props, &addr_pll_stat, 1); + tuner_i2c_xfer_recv(&priv->i2c_props, &pll_stat, 1); + if (pll_stat & 0x80) { + tuner_i2c_xfer_send(&priv->i2c_props, &addr_adc_sat, 1); + tuner_i2c_xfer_recv(&priv->i2c_props, &adc_sat, 1); + tuner_i2c_xfer_send(&priv->i2c_props, &addr_agc_stat, 1); + tuner_i2c_xfer_recv(&priv->i2c_props, &agc_stat, 1); + tuner_dbg("tda8290 is locked, AGC: %d\n", agc_stat); + break; + } else { + tuner_dbg("tda8290 not locked, no signal?\n"); + msleep(100); + } + } + /* adjust headroom resp. gain */ + if ((agc_stat > 115) || (!(pll_stat & 0x80) && (adc_sat < 20))) { + tuner_dbg("adjust gain, step 1. Agc: %d, ADC stat: %d, lock: %d\n", + agc_stat, adc_sat, pll_stat & 0x80); + tuner_i2c_xfer_send(&priv->i2c_props, gainset_2, 2); + msleep(100); + tuner_i2c_xfer_send(&priv->i2c_props, &addr_agc_stat, 1); + tuner_i2c_xfer_recv(&priv->i2c_props, &agc_stat, 1); + tuner_i2c_xfer_send(&priv->i2c_props, &addr_pll_stat, 1); + tuner_i2c_xfer_recv(&priv->i2c_props, &pll_stat, 1); + if ((agc_stat > 115) || !(pll_stat & 0x80)) { + tuner_dbg("adjust gain, step 2. Agc: %d, lock: %d\n", + agc_stat, pll_stat & 0x80); + if (priv->cfg.agcf) + priv->cfg.agcf(fe); + msleep(100); + tuner_i2c_xfer_send(&priv->i2c_props, &addr_agc_stat, 1); + tuner_i2c_xfer_recv(&priv->i2c_props, &agc_stat, 1); + tuner_i2c_xfer_send(&priv->i2c_props, &addr_pll_stat, 1); + tuner_i2c_xfer_recv(&priv->i2c_props, &pll_stat, 1); + if((agc_stat > 115) || !(pll_stat & 0x80)) { + tuner_dbg("adjust gain, step 3. Agc: %d\n", agc_stat); + tuner_i2c_xfer_send(&priv->i2c_props, adc_head_12, 2); + tuner_i2c_xfer_send(&priv->i2c_props, pll_bw_low, 2); + msleep(100); + } + } + } + + /* l/ l' deadlock? */ + if(priv->tda8290_easy_mode & 0x60) { + tuner_i2c_xfer_send(&priv->i2c_props, &addr_adc_sat, 1); + tuner_i2c_xfer_recv(&priv->i2c_props, &adc_sat, 1); + tuner_i2c_xfer_send(&priv->i2c_props, &addr_pll_stat, 1); + tuner_i2c_xfer_recv(&priv->i2c_props, &pll_stat, 1); + if ((adc_sat > 20) || !(pll_stat & 0x80)) { + tuner_dbg("trying to resolve SECAM L deadlock\n"); + tuner_i2c_xfer_send(&priv->i2c_props, agc_rst_on, 2); + msleep(40); + tuner_i2c_xfer_send(&priv->i2c_props, agc_rst_off, 2); + } + } + + tda8290_i2c_bridge(fe, 0); + tuner_i2c_xfer_send(&priv->i2c_props, if_agc_set, 2); +} + +/*---------------------------------------------------------------------*/ + +static void tda8295_power(struct dvb_frontend *fe, int enable) +{ + struct tda8290_priv *priv = fe->analog_demod_priv; + unsigned char buf[] = { 0x30, 0x00 }; /* clb_stdbt */ + + tuner_i2c_xfer_send(&priv->i2c_props, &buf[0], 1); + tuner_i2c_xfer_recv(&priv->i2c_props, &buf[1], 1); + + if (enable) + buf[1] = 0x01; + else + buf[1] = 0x03; + + tuner_i2c_xfer_send(&priv->i2c_props, buf, 2); +} + +static void tda8295_set_easy_mode(struct dvb_frontend *fe, int enable) +{ + struct tda8290_priv *priv = fe->analog_demod_priv; + unsigned char buf[] = { 0x01, 0x00 }; + + tuner_i2c_xfer_send(&priv->i2c_props, &buf[0], 1); + tuner_i2c_xfer_recv(&priv->i2c_props, &buf[1], 1); + + if (enable) + buf[1] = 0x01; /* rising edge sets regs 0x02 - 0x23 */ + else + buf[1] = 0x00; /* reset active bit */ + + tuner_i2c_xfer_send(&priv->i2c_props, buf, 2); +} + +static void tda8295_set_video_std(struct dvb_frontend *fe) +{ + struct tda8290_priv *priv = fe->analog_demod_priv; + unsigned char buf[] = { 0x00, priv->tda8290_easy_mode }; + + tuner_i2c_xfer_send(&priv->i2c_props, buf, 2); + + tda8295_set_easy_mode(fe, 1); + msleep(20); + tda8295_set_easy_mode(fe, 0); +} + +/*---------------------------------------------------------------------*/ + +static void tda8295_agc1_out(struct dvb_frontend *fe, int enable) +{ + struct tda8290_priv *priv = fe->analog_demod_priv; + unsigned char buf[] = { 0x02, 0x00 }; /* DIV_FUNC */ + + tuner_i2c_xfer_send(&priv->i2c_props, &buf[0], 1); + tuner_i2c_xfer_recv(&priv->i2c_props, &buf[1], 1); + + if (enable) + buf[1] &= ~0x40; + else + buf[1] |= 0x40; + + tuner_i2c_xfer_send(&priv->i2c_props, buf, 2); +} + +static void tda8295_agc2_out(struct dvb_frontend *fe, int enable) +{ + struct tda8290_priv *priv = fe->analog_demod_priv; + unsigned char set_gpio_cf[] = { 0x44, 0x00 }; + unsigned char set_gpio_val[] = { 0x46, 0x00 }; + + tuner_i2c_xfer_send(&priv->i2c_props, &set_gpio_cf[0], 1); + tuner_i2c_xfer_recv(&priv->i2c_props, &set_gpio_cf[1], 1); + tuner_i2c_xfer_send(&priv->i2c_props, &set_gpio_val[0], 1); + tuner_i2c_xfer_recv(&priv->i2c_props, &set_gpio_val[1], 1); + + set_gpio_cf[1] &= 0xf0; /* clear GPIO_0 bits 3-0 */ + + if (enable) { + set_gpio_cf[1] |= 0x01; /* config GPIO_0 as Open Drain Out */ + set_gpio_val[1] &= 0xfe; /* set GPIO_0 pin low */ + } + tuner_i2c_xfer_send(&priv->i2c_props, set_gpio_cf, 2); + tuner_i2c_xfer_send(&priv->i2c_props, set_gpio_val, 2); +} + +static int tda8295_has_signal(struct dvb_frontend *fe) +{ + struct tda8290_priv *priv = fe->analog_demod_priv; + + unsigned char hvpll_stat = 0x26; + unsigned char ret; + + tuner_i2c_xfer_send(&priv->i2c_props, &hvpll_stat, 1); + tuner_i2c_xfer_recv(&priv->i2c_props, &ret, 1); + return (ret & 0x01) ? 65535 : 0; +} + +/*---------------------------------------------------------------------*/ + +static void tda8295_set_params(struct dvb_frontend *fe, + struct analog_parameters *params) +{ + struct tda8290_priv *priv = fe->analog_demod_priv; + + unsigned char blanking_mode[] = { 0x1d, 0x00 }; + + set_audio(fe, params); + + tuner_dbg("%s: freq = %d\n", __func__, params->frequency); + + tda8295_power(fe, 1); + tda8295_agc1_out(fe, 1); + + tuner_i2c_xfer_send(&priv->i2c_props, &blanking_mode[0], 1); + tuner_i2c_xfer_recv(&priv->i2c_props, &blanking_mode[1], 1); + + tda8295_set_video_std(fe); + + blanking_mode[1] = 0x03; + tuner_i2c_xfer_send(&priv->i2c_props, blanking_mode, 2); + msleep(20); + + tda8295_i2c_bridge(fe, 1); + + if (fe->ops.tuner_ops.set_analog_params) + fe->ops.tuner_ops.set_analog_params(fe, params); + + if (priv->cfg.agcf) + priv->cfg.agcf(fe); + + if (tda8295_has_signal(fe)) + tuner_dbg("tda8295 is locked\n"); + else + tuner_dbg("tda8295 not locked, no signal?\n"); + + tda8295_i2c_bridge(fe, 0); +} + +/*---------------------------------------------------------------------*/ + +static int tda8290_has_signal(struct dvb_frontend *fe) +{ + struct tda8290_priv *priv = fe->analog_demod_priv; + + unsigned char i2c_get_afc[1] = { 0x1B }; + unsigned char afc = 0; + + tuner_i2c_xfer_send(&priv->i2c_props, i2c_get_afc, ARRAY_SIZE(i2c_get_afc)); + tuner_i2c_xfer_recv(&priv->i2c_props, &afc, 1); + return (afc & 0x80)? 65535:0; +} + +/*---------------------------------------------------------------------*/ + +static void tda8290_standby(struct dvb_frontend *fe) +{ + struct tda8290_priv *priv = fe->analog_demod_priv; + + unsigned char cb1[] = { 0x30, 0xD0 }; + unsigned char tda8290_standby[] = { 0x00, 0x02 }; + unsigned char tda8290_agc_tri[] = { 0x02, 0x20 }; + struct i2c_msg msg = {.addr = priv->tda827x_addr, .flags=0, .buf=cb1, .len = 2}; + + tda8290_i2c_bridge(fe, 1); + if (priv->ver & TDA8275A) + cb1[1] = 0x90; + i2c_transfer(priv->i2c_props.adap, &msg, 1); + tda8290_i2c_bridge(fe, 0); + tuner_i2c_xfer_send(&priv->i2c_props, tda8290_agc_tri, 2); + tuner_i2c_xfer_send(&priv->i2c_props, tda8290_standby, 2); +} + +static void tda8295_standby(struct dvb_frontend *fe) +{ + tda8295_agc1_out(fe, 0); /* Put AGC in tri-state */ + + tda8295_power(fe, 0); +} + +static void tda8290_init_if(struct dvb_frontend *fe) +{ + struct tda8290_priv *priv = fe->analog_demod_priv; + + unsigned char set_VS[] = { 0x30, 0x6F }; + unsigned char set_GP00_CF[] = { 0x20, 0x01 }; + unsigned char set_GP01_CF[] = { 0x20, 0x0B }; + + if ((priv->cfg.config == 1) || (priv->cfg.config == 2)) + tuner_i2c_xfer_send(&priv->i2c_props, set_GP00_CF, 2); + else + tuner_i2c_xfer_send(&priv->i2c_props, set_GP01_CF, 2); + tuner_i2c_xfer_send(&priv->i2c_props, set_VS, 2); +} + +static void tda8295_init_if(struct dvb_frontend *fe) +{ + struct tda8290_priv *priv = fe->analog_demod_priv; + + static unsigned char set_adc_ctl[] = { 0x33, 0x14 }; + static unsigned char set_adc_ctl2[] = { 0x34, 0x00 }; + static unsigned char set_pll_reg6[] = { 0x3e, 0x63 }; + static unsigned char set_pll_reg0[] = { 0x38, 0x23 }; + static unsigned char set_pll_reg7[] = { 0x3f, 0x01 }; + static unsigned char set_pll_reg10[] = { 0x42, 0x61 }; + static unsigned char set_gpio_reg0[] = { 0x44, 0x0b }; + + tda8295_power(fe, 1); + + tda8295_set_easy_mode(fe, 0); + tda8295_set_video_std(fe); + + tuner_i2c_xfer_send(&priv->i2c_props, set_adc_ctl, 2); + tuner_i2c_xfer_send(&priv->i2c_props, set_adc_ctl2, 2); + tuner_i2c_xfer_send(&priv->i2c_props, set_pll_reg6, 2); + tuner_i2c_xfer_send(&priv->i2c_props, set_pll_reg0, 2); + tuner_i2c_xfer_send(&priv->i2c_props, set_pll_reg7, 2); + tuner_i2c_xfer_send(&priv->i2c_props, set_pll_reg10, 2); + tuner_i2c_xfer_send(&priv->i2c_props, set_gpio_reg0, 2); + + tda8295_agc1_out(fe, 0); + tda8295_agc2_out(fe, 0); +} + +static void tda8290_init_tuner(struct dvb_frontend *fe) +{ + struct tda8290_priv *priv = fe->analog_demod_priv; + unsigned char tda8275_init[] = { 0x00, 0x00, 0x00, 0x40, 0xdC, 0x04, 0xAf, + 0x3F, 0x2A, 0x04, 0xFF, 0x00, 0x00, 0x40 }; + unsigned char tda8275a_init[] = { 0x00, 0x00, 0x00, 0x00, 0xdC, 0x05, 0x8b, + 0x0c, 0x04, 0x20, 0xFF, 0x00, 0x00, 0x4b }; + struct i2c_msg msg = {.addr = priv->tda827x_addr, .flags=0, + .buf=tda8275_init, .len = 14}; + if (priv->ver & TDA8275A) + msg.buf = tda8275a_init; + + tda8290_i2c_bridge(fe, 1); + i2c_transfer(priv->i2c_props.adap, &msg, 1); + tda8290_i2c_bridge(fe, 0); +} + +/*---------------------------------------------------------------------*/ + +static void tda829x_release(struct dvb_frontend *fe) +{ + struct tda8290_priv *priv = fe->analog_demod_priv; + + /* only try to release the tuner if we've + * attached it from within this module */ + if (priv->ver & (TDA18271 | TDA8275 | TDA8275A)) + if (fe->ops.tuner_ops.release) + fe->ops.tuner_ops.release(fe); + + kfree(fe->analog_demod_priv); + fe->analog_demod_priv = NULL; +} + +static struct tda18271_config tda829x_tda18271_config = { + .gate = TDA18271_GATE_ANALOG, +}; + +static int tda829x_find_tuner(struct dvb_frontend *fe) +{ + struct tda8290_priv *priv = fe->analog_demod_priv; + struct analog_demod_ops *analog_ops = &fe->ops.analog_ops; + int i, ret, tuners_found; + u32 tuner_addrs; + u8 data; + struct i2c_msg msg = { .flags = I2C_M_RD, .buf = &data, .len = 1 }; + + if (NULL == analog_ops->i2c_gate_ctrl) + return -EINVAL; + + analog_ops->i2c_gate_ctrl(fe, 1); + + /* probe for tuner chip */ + tuners_found = 0; + tuner_addrs = 0; + for (i = 0x60; i <= 0x63; i++) { + msg.addr = i; + ret = i2c_transfer(priv->i2c_props.adap, &msg, 1); + if (ret == 1) { + tuners_found++; + tuner_addrs = (tuner_addrs << 8) + i; + } + } + /* if there is more than one tuner, we expect the right one is + behind the bridge and we choose the highest address that doesn't + give a response now + */ + + analog_ops->i2c_gate_ctrl(fe, 0); + + if (tuners_found > 1) + for (i = 0; i < tuners_found; i++) { + msg.addr = tuner_addrs & 0xff; + ret = i2c_transfer(priv->i2c_props.adap, &msg, 1); + if (ret == 1) + tuner_addrs = tuner_addrs >> 8; + else + break; + } + + if (tuner_addrs == 0) { + tuner_addrs = 0x60; + tuner_info("could not clearly identify tuner address, " + "defaulting to %x\n", tuner_addrs); + } else { + tuner_addrs = tuner_addrs & 0xff; + tuner_info("setting tuner address to %x\n", tuner_addrs); + } + priv->tda827x_addr = tuner_addrs; + msg.addr = tuner_addrs; + + analog_ops->i2c_gate_ctrl(fe, 1); + ret = i2c_transfer(priv->i2c_props.adap, &msg, 1); + + if (ret != 1) { + tuner_warn("tuner access failed!\n"); + return -EREMOTEIO; + } + + if ((data == 0x83) || (data == 0x84)) { + priv->ver |= TDA18271; + tda18271_attach(fe, priv->tda827x_addr, + priv->i2c_props.adap, + &tda829x_tda18271_config); + } else { + if ((data & 0x3c) == 0) + priv->ver |= TDA8275; + else + priv->ver |= TDA8275A; + + tda827x_attach(fe, priv->tda827x_addr, priv->i2c_props.adap, &priv->cfg); + priv->cfg.switch_addr = priv->i2c_props.addr; + } + if (fe->ops.tuner_ops.init) + fe->ops.tuner_ops.init(fe); + + if (fe->ops.tuner_ops.sleep) + fe->ops.tuner_ops.sleep(fe); + + analog_ops->i2c_gate_ctrl(fe, 0); + + return 0; +} + +static int tda8290_probe(struct tuner_i2c_props *i2c_props) +{ +#define TDA8290_ID 0x89 + unsigned char tda8290_id[] = { 0x1f, 0x00 }; + + /* detect tda8290 */ + tuner_i2c_xfer_send(i2c_props, &tda8290_id[0], 1); + tuner_i2c_xfer_recv(i2c_props, &tda8290_id[1], 1); + + if (tda8290_id[1] == TDA8290_ID) { + if (debug) + printk(KERN_DEBUG "%s: tda8290 detected @ %d-%04x\n", + __func__, i2c_adapter_id(i2c_props->adap), + i2c_props->addr); + return 0; + } + + return -ENODEV; +} + +static int tda8295_probe(struct tuner_i2c_props *i2c_props) +{ +#define TDA8295_ID 0x8a + unsigned char tda8295_id[] = { 0x2f, 0x00 }; + + /* detect tda8295 */ + tuner_i2c_xfer_send(i2c_props, &tda8295_id[0], 1); + tuner_i2c_xfer_recv(i2c_props, &tda8295_id[1], 1); + + if (tda8295_id[1] == TDA8295_ID) { + if (debug) + printk(KERN_DEBUG "%s: tda8295 detected @ %d-%04x\n", + __func__, i2c_adapter_id(i2c_props->adap), + i2c_props->addr); + return 0; + } + + return -ENODEV; +} + +static struct analog_demod_ops tda8290_ops = { + .set_params = tda8290_set_params, + .has_signal = tda8290_has_signal, + .standby = tda8290_standby, + .release = tda829x_release, + .i2c_gate_ctrl = tda8290_i2c_bridge, +}; + +static struct analog_demod_ops tda8295_ops = { + .set_params = tda8295_set_params, + .has_signal = tda8295_has_signal, + .standby = tda8295_standby, + .release = tda829x_release, + .i2c_gate_ctrl = tda8295_i2c_bridge, +}; + +struct dvb_frontend *tda829x_attach(struct dvb_frontend *fe, + struct i2c_adapter *i2c_adap, u8 i2c_addr, + struct tda829x_config *cfg) +{ + struct tda8290_priv *priv = NULL; + char *name; + + priv = kzalloc(sizeof(struct tda8290_priv), GFP_KERNEL); + if (priv == NULL) + return NULL; + fe->analog_demod_priv = priv; + + priv->i2c_props.addr = i2c_addr; + priv->i2c_props.adap = i2c_adap; + priv->i2c_props.name = "tda829x"; + if (cfg) { + priv->cfg.config = cfg->lna_cfg; + priv->cfg.tuner_callback = cfg->tuner_callback; + } + + if (tda8290_probe(&priv->i2c_props) == 0) { + priv->ver = TDA8290; + memcpy(&fe->ops.analog_ops, &tda8290_ops, + sizeof(struct analog_demod_ops)); + } + + if (tda8295_probe(&priv->i2c_props) == 0) { + priv->ver = TDA8295; + memcpy(&fe->ops.analog_ops, &tda8295_ops, + sizeof(struct analog_demod_ops)); + } + + if ((!(cfg) || (TDA829X_PROBE_TUNER == cfg->probe_tuner)) && + (tda829x_find_tuner(fe) < 0)) + goto fail; + + switch (priv->ver) { + case TDA8290: + name = "tda8290"; + break; + case TDA8295: + name = "tda8295"; + break; + case TDA8290 | TDA8275: + name = "tda8290+75"; + break; + case TDA8295 | TDA8275: + name = "tda8295+75"; + break; + case TDA8290 | TDA8275A: + name = "tda8290+75a"; + break; + case TDA8295 | TDA8275A: + name = "tda8295+75a"; + break; + case TDA8290 | TDA18271: + name = "tda8290+18271"; + break; + case TDA8295 | TDA18271: + name = "tda8295+18271"; + break; + default: + goto fail; + } + tuner_info("type set to %s\n", name); + + fe->ops.analog_ops.info.name = name; + + if (priv->ver & TDA8290) { + tda8290_init_tuner(fe); + tda8290_init_if(fe); + } else if (priv->ver & TDA8295) + tda8295_init_if(fe); + +#if 0 + t->mode = V4L2_TUNER_ANALOG_TV; +#endif + return fe; + +fail: + tda829x_release(fe); + return NULL; +} +EXPORT_SYMBOL_GPL(tda829x_attach); + +int tda829x_probe(struct i2c_adapter *i2c_adap, u8 i2c_addr) +{ + struct tuner_i2c_props i2c_props = { + .adap = i2c_adap, + .addr = i2c_addr, + }; + + unsigned char soft_reset[] = { 0x00, 0x00 }; + unsigned char easy_mode_b[] = { 0x01, 0x02 }; + unsigned char easy_mode_g[] = { 0x01, 0x04 }; + unsigned char restore_9886[] = { 0x00, 0xd6, 0x30 }; + unsigned char addr_dto_lsb = 0x07; + unsigned char data; +#define PROBE_BUFFER_SIZE 8 + unsigned char buf[PROBE_BUFFER_SIZE]; + int i; + + /* rule out tda9887, which would return the same byte repeatedly */ + tuner_i2c_xfer_send(&i2c_props, soft_reset, 1); + tuner_i2c_xfer_recv(&i2c_props, buf, PROBE_BUFFER_SIZE); + for (i = 1; i < PROBE_BUFFER_SIZE; i++) { + if (buf[i] != buf[0]) + break; + } + + /* all bytes are equal, not a tda829x - probably a tda9887 */ + if (i == PROBE_BUFFER_SIZE) + return -ENODEV; + + if ((tda8290_probe(&i2c_props) == 0) || + (tda8295_probe(&i2c_props) == 0)) + return 0; + + /* fall back to old probing method */ + tuner_i2c_xfer_send(&i2c_props, easy_mode_b, 2); + tuner_i2c_xfer_send(&i2c_props, soft_reset, 2); + tuner_i2c_xfer_send(&i2c_props, &addr_dto_lsb, 1); + tuner_i2c_xfer_recv(&i2c_props, &data, 1); + if (data == 0) { + tuner_i2c_xfer_send(&i2c_props, easy_mode_g, 2); + tuner_i2c_xfer_send(&i2c_props, soft_reset, 2); + tuner_i2c_xfer_send(&i2c_props, &addr_dto_lsb, 1); + tuner_i2c_xfer_recv(&i2c_props, &data, 1); + if (data == 0x7b) { + return 0; + } + } + tuner_i2c_xfer_send(&i2c_props, restore_9886, 3); + return -ENODEV; +} +EXPORT_SYMBOL_GPL(tda829x_probe); + +MODULE_DESCRIPTION("Philips/NXP TDA8290/TDA8295 analog IF demodulator driver"); +MODULE_AUTHOR("Gerd Knorr, Hartmut Hackmann, Michael Krufky"); +MODULE_LICENSE("GPL"); + +/* + * Overrides for Emacs so that we follow Linus's tabbing style. + * --------------------------------------------------------------------------- + * Local variables: + * c-basic-offset: 8 + * End: + */ diff --git a/linux/drivers/media/common/tuners/tda8290.h b/linux/drivers/media/common/tuners/tda8290.h new file mode 100644 index 000000000..d3bbf276a --- /dev/null +++ b/linux/drivers/media/common/tuners/tda8290.h @@ -0,0 +1,57 @@ +/* + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. +*/ + +#ifndef __TDA8290_H__ +#define __TDA8290_H__ + +#include +#include "dvb_frontend.h" + +struct tda829x_config { + unsigned int lna_cfg; + int (*tuner_callback) (void *dev, int command, int arg); + + unsigned int probe_tuner:1; +#define TDA829X_PROBE_TUNER 0 +#define TDA829X_DONT_PROBE 1 +}; + +#if defined(CONFIG_TUNER_TDA8290) || (defined(CONFIG_TUNER_TDA8290_MODULE) && defined(MODULE)) +extern int tda829x_probe(struct i2c_adapter *i2c_adap, u8 i2c_addr); + +extern struct dvb_frontend *tda829x_attach(struct dvb_frontend *fe, + struct i2c_adapter *i2c_adap, + u8 i2c_addr, + struct tda829x_config *cfg); +#else +static inline int tda829x_probe(struct i2c_adapter *i2c_adap, u8 i2c_addr) +{ + printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__); + return -EINVAL; +} + +static inline struct dvb_frontend *tda829x_attach(struct dvb_frontend *fe, + struct i2c_adapter *i2c_adap, + u8 i2c_addr, + struct tda829x_config *cfg) +{ + printk(KERN_INFO "%s: not probed - driver disabled by Kconfig\n", + __func__); + return NULL; +} +#endif + +#endif /* __TDA8290_H__ */ diff --git a/linux/drivers/media/common/tuners/tda9887.c b/linux/drivers/media/common/tuners/tda9887.c new file mode 100644 index 000000000..e98de7d40 --- /dev/null +++ b/linux/drivers/media/common/tuners/tda9887.c @@ -0,0 +1,728 @@ +#include +#include +#include +#include +#include +#include +#include +#include +#include "compat.h" +#include +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0) +#include "i2c-compat.h" +#endif +#include +#include +#include "tuner-i2c.h" +#include "tda9887.h" + + +/* Chips: + TDA9885 (PAL, NTSC) + TDA9886 (PAL, SECAM, NTSC) + TDA9887 (PAL, SECAM, NTSC, FM Radio) + + Used as part of several tuners +*/ + +static int debug; +module_param(debug, int, 0644); +MODULE_PARM_DESC(debug, "enable verbose debug messages"); + +static DEFINE_MUTEX(tda9887_list_mutex); +static LIST_HEAD(hybrid_tuner_instance_list); + +struct tda9887_priv { + struct tuner_i2c_props i2c_props; + struct list_head hybrid_tuner_instance_list; + + unsigned char data[4]; + unsigned int config; + unsigned int mode; + unsigned int audmode; + v4l2_std_id std; +}; + +/* ---------------------------------------------------------------------- */ + +#define UNSET (-1U) + +struct tvnorm { + v4l2_std_id std; + char *name; + unsigned char b; + unsigned char c; + unsigned char e; +}; + +/* ---------------------------------------------------------------------- */ + +// +// TDA defines +// + +//// first reg (b) +#define cVideoTrapBypassOFF 0x00 // bit b0 +#define cVideoTrapBypassON 0x01 // bit b0 + +#define cAutoMuteFmInactive 0x00 // bit b1 +#define cAutoMuteFmActive 0x02 // bit b1 + +#define cIntercarrier 0x00 // bit b2 +#define cQSS 0x04 // bit b2 + +#define cPositiveAmTV 0x00 // bit b3:4 +#define cFmRadio 0x08 // bit b3:4 +#define cNegativeFmTV 0x10 // bit b3:4 + + +#define cForcedMuteAudioON 0x20 // bit b5 +#define cForcedMuteAudioOFF 0x00 // bit b5 + +#define cOutputPort1Active 0x00 // bit b6 +#define cOutputPort1Inactive 0x40 // bit b6 + +#define cOutputPort2Active 0x00 // bit b7 +#define cOutputPort2Inactive 0x80 // bit b7 + + +//// second reg (c) +#define cDeemphasisOFF 0x00 // bit c5 +#define cDeemphasisON 0x20 // bit c5 + +#define cDeemphasis75 0x00 // bit c6 +#define cDeemphasis50 0x40 // bit c6 + +#define cAudioGain0 0x00 // bit c7 +#define cAudioGain6 0x80 // bit c7 + +#define cTopMask 0x1f // bit c0:4 +#define cTopDefault 0x10 // bit c0:4 + +//// third reg (e) +#define cAudioIF_4_5 0x00 // bit e0:1 +#define cAudioIF_5_5 0x01 // bit e0:1 +#define cAudioIF_6_0 0x02 // bit e0:1 +#define cAudioIF_6_5 0x03 // bit e0:1 + + +#define cVideoIFMask 0x1c // bit e2:4 +/* Video IF selection in TV Mode (bit B3=0) */ +#define cVideoIF_58_75 0x00 // bit e2:4 +#define cVideoIF_45_75 0x04 // bit e2:4 +#define cVideoIF_38_90 0x08 // bit e2:4 +#define cVideoIF_38_00 0x0C // bit e2:4 +#define cVideoIF_33_90 0x10 // bit e2:4 +#define cVideoIF_33_40 0x14 // bit e2:4 +#define cRadioIF_45_75 0x18 // bit e2:4 +#define cRadioIF_38_90 0x1C // bit e2:4 + +/* IF1 selection in Radio Mode (bit B3=1) */ +#define cRadioIF_33_30 0x00 // bit e2,4 (also 0x10,0x14) +#define cRadioIF_41_30 0x04 // bit e2,4 + +/* Output of AFC pin in radio mode when bit E7=1 */ +#define cRadioAGC_SIF 0x00 // bit e3 +#define cRadioAGC_FM 0x08 // bit e3 + +#define cTunerGainNormal 0x00 // bit e5 +#define cTunerGainLow 0x20 // bit e5 + +#define cGating_18 0x00 // bit e6 +#define cGating_36 0x40 // bit e6 + +#define cAgcOutON 0x80 // bit e7 +#define cAgcOutOFF 0x00 // bit e7 + +/* ---------------------------------------------------------------------- */ + +static struct tvnorm tvnorms[] = { + { + .std = V4L2_STD_PAL_BG | V4L2_STD_PAL_H | V4L2_STD_PAL_N, + .name = "PAL-BGHN", + .b = ( cNegativeFmTV | + cQSS ), + .c = ( cDeemphasisON | + cDeemphasis50 | + cTopDefault), + .e = ( cGating_36 | + cAudioIF_5_5 | + cVideoIF_38_90 ), + },{ + .std = V4L2_STD_PAL_I, + .name = "PAL-I", + .b = ( cNegativeFmTV | + cQSS ), + .c = ( cDeemphasisON | + cDeemphasis50 | + cTopDefault), + .e = ( cGating_36 | + cAudioIF_6_0 | + cVideoIF_38_90 ), + },{ + .std = V4L2_STD_PAL_DK, + .name = "PAL-DK", + .b = ( cNegativeFmTV | + cQSS ), + .c = ( cDeemphasisON | + cDeemphasis50 | + cTopDefault), + .e = ( cGating_36 | + cAudioIF_6_5 | + cVideoIF_38_90 ), + },{ + .std = V4L2_STD_PAL_M | V4L2_STD_PAL_Nc, + .name = "PAL-M/Nc", + .b = ( cNegativeFmTV | + cQSS ), + .c = ( cDeemphasisON | + cDeemphasis75 | + cTopDefault), + .e = ( cGating_36 | + cAudioIF_4_5 | + cVideoIF_45_75 ), + },{ + .std = V4L2_STD_SECAM_B | V4L2_STD_SECAM_G | V4L2_STD_SECAM_H, + .name = "SECAM-BGH", + .b = ( cPositiveAmTV | + cQSS ), + .c = ( cTopDefault), + .e = ( cGating_36 | + cAudioIF_5_5 | + cVideoIF_38_90 ), + },{ + .std = V4L2_STD_SECAM_L, + .name = "SECAM-L", + .b = ( cPositiveAmTV | + cQSS ), + .c = ( cTopDefault), + .e = ( cGating_36 | + cAudioIF_6_5 | + cVideoIF_38_90 ), + },{ + .std = V4L2_STD_SECAM_LC, + .name = "SECAM-L'", + .b = ( cOutputPort2Inactive | + cPositiveAmTV | + cQSS ), + .c = ( cTopDefault), + .e = ( cGating_36 | + cAudioIF_6_5 | + cVideoIF_33_90 ), + },{ + .std = V4L2_STD_SECAM_DK, + .name = "SECAM-DK", + .b = ( cNegativeFmTV | + cQSS ), + .c = ( cDeemphasisON | + cDeemphasis50 | + cTopDefault), + .e = ( cGating_36 | + cAudioIF_6_5 | + cVideoIF_38_90 ), + },{ + .std = V4L2_STD_NTSC_M | V4L2_STD_NTSC_M_KR, + .name = "NTSC-M", + .b = ( cNegativeFmTV | + cQSS ), + .c = ( cDeemphasisON | + cDeemphasis75 | + cTopDefault), + .e = ( cGating_36 | + cAudioIF_4_5 | + cVideoIF_45_75 ), + },{ + .std = V4L2_STD_NTSC_M_JP, + .name = "NTSC-M-JP", + .b = ( cNegativeFmTV | + cQSS ), + .c = ( cDeemphasisON | + cDeemphasis50 | + cTopDefault), + .e = ( cGating_36 | + cAudioIF_4_5 | + cVideoIF_58_75 ), + } +}; + +static struct tvnorm radio_stereo = { + .name = "Radio Stereo", + .b = ( cFmRadio | + cQSS ), + .c = ( cDeemphasisOFF | + cAudioGain6 | + cTopDefault), + .e = ( cTunerGainLow | + cAudioIF_5_5 | + cRadioIF_38_90 ), +}; + +static struct tvnorm radio_mono = { + .name = "Radio Mono", + .b = ( cFmRadio | + cQSS ), + .c = ( cDeemphasisON | + cDeemphasis75 | + cTopDefault), + .e = ( cTunerGainLow | + cAudioIF_5_5 | + cRadioIF_38_90 ), +}; + +/* ---------------------------------------------------------------------- */ + +static void dump_read_message(struct dvb_frontend *fe, unsigned char *buf) +{ + struct tda9887_priv *priv = fe->analog_demod_priv; + + static char *afc[16] = { + "- 12.5 kHz", + "- 37.5 kHz", + "- 62.5 kHz", + "- 87.5 kHz", + "-112.5 kHz", + "-137.5 kHz", + "-162.5 kHz", + "-187.5 kHz [min]", + "+187.5 kHz [max]", + "+162.5 kHz", + "+137.5 kHz", + "+112.5 kHz", + "+ 87.5 kHz", + "+ 62.5 kHz", + "+ 37.5 kHz", + "+ 12.5 kHz", + }; + tuner_info("read: 0x%2x\n", buf[0]); + tuner_info(" after power on : %s\n", (buf[0] & 0x01) ? "yes" : "no"); + tuner_info(" afc : %s\n", afc[(buf[0] >> 1) & 0x0f]); + tuner_info(" fmif level : %s\n", (buf[0] & 0x20) ? "high" : "low"); + tuner_info(" afc window : %s\n", (buf[0] & 0x40) ? "in" : "out"); + tuner_info(" vfi level : %s\n", (buf[0] & 0x80) ? "high" : "low"); +} + +static void dump_write_message(struct dvb_frontend *fe, unsigned char *buf) +{ + struct tda9887_priv *priv = fe->analog_demod_priv; + + static char *sound[4] = { + "AM/TV", + "FM/radio", + "FM/TV", + "FM/radio" + }; + static char *adjust[32] = { + "-16", "-15", "-14", "-13", "-12", "-11", "-10", "-9", + "-8", "-7", "-6", "-5", "-4", "-3", "-2", "-1", + "0", "+1", "+2", "+3", "+4", "+5", "+6", "+7", + "+8", "+9", "+10", "+11", "+12", "+13", "+14", "+15" + }; + static char *deemph[4] = { + "no", "no", "75", "50" + }; + static char *carrier[4] = { + "4.5 MHz", + "5.5 MHz", + "6.0 MHz", + "6.5 MHz / AM" + }; + static char *vif[8] = { + "58.75 MHz", + "45.75 MHz", + "38.9 MHz", + "38.0 MHz", + "33.9 MHz", + "33.4 MHz", + "45.75 MHz + pin13", + "38.9 MHz + pin13", + }; + static char *rif[4] = { + "44 MHz", + "52 MHz", + "52 MHz", + "44 MHz", + }; + + tuner_info("write: byte B 0x%02x\n", buf[1]); + tuner_info(" B0 video mode : %s\n", + (buf[1] & 0x01) ? "video trap" : "sound trap"); + tuner_info(" B1 auto mute fm : %s\n", + (buf[1] & 0x02) ? "yes" : "no"); + tuner_info(" B2 carrier mode : %s\n", + (buf[1] & 0x04) ? "QSS" : "Intercarrier"); + tuner_info(" B3-4 tv sound/radio : %s\n", + sound[(buf[1] & 0x18) >> 3]); + tuner_info(" B5 force mute audio: %s\n", + (buf[1] & 0x20) ? "yes" : "no"); + tuner_info(" B6 output port 1 : %s\n", + (buf[1] & 0x40) ? "high (inactive)" : "low (active)"); + tuner_info(" B7 output port 2 : %s\n", + (buf[1] & 0x80) ? "high (inactive)" : "low (active)"); + + tuner_info("write: byte C 0x%02x\n", buf[2]); + tuner_info(" C0-4 top adjustment : %s dB\n", + adjust[buf[2] & 0x1f]); + tuner_info(" C5-6 de-emphasis : %s\n", + deemph[(buf[2] & 0x60) >> 5]); + tuner_info(" C7 audio gain : %s\n", + (buf[2] & 0x80) ? "-6" : "0"); + + tuner_info("write: byte E 0x%02x\n", buf[3]); + tuner_info(" E0-1 sound carrier : %s\n", + carrier[(buf[3] & 0x03)]); + tuner_info(" E6 l pll gating : %s\n", + (buf[3] & 0x40) ? "36" : "13"); + + if (buf[1] & 0x08) { + /* radio */ + tuner_info(" E2-4 video if : %s\n", + rif[(buf[3] & 0x0c) >> 2]); + tuner_info(" E7 vif agc output : %s\n", + (buf[3] & 0x80) + ? ((buf[3] & 0x10) ? "fm-agc radio" : + "sif-agc radio") + : "fm radio carrier afc"); + } else { + /* video */ + tuner_info(" E2-4 video if : %s\n", + vif[(buf[3] & 0x1c) >> 2]); + tuner_info(" E5 tuner gain : %s\n", + (buf[3] & 0x80) + ? ((buf[3] & 0x20) ? "external" : "normal") + : ((buf[3] & 0x20) ? "minimum" : "normal")); + tuner_info(" E7 vif agc output : %s\n", + (buf[3] & 0x80) ? ((buf[3] & 0x20) + ? "pin3 port, pin22 vif agc out" + : "pin22 port, pin3 vif acg ext in") + : "pin3+pin22 port"); + } + tuner_info("--\n"); +} + +/* ---------------------------------------------------------------------- */ + +static int tda9887_set_tvnorm(struct dvb_frontend *fe) +{ + struct tda9887_priv *priv = fe->analog_demod_priv; + struct tvnorm *norm = NULL; + char *buf = priv->data; + int i; + + if (priv->mode == V4L2_TUNER_RADIO) { + if (priv->audmode == V4L2_TUNER_MODE_MONO) + norm = &radio_mono; + else + norm = &radio_stereo; + } else { + for (i = 0; i < ARRAY_SIZE(tvnorms); i++) { + if (tvnorms[i].std & priv->std) { + norm = tvnorms+i; + break; + } + } + } + if (NULL == norm) { + tuner_dbg("Unsupported tvnorm entry - audio muted\n"); + return -1; + } + + tuner_dbg("configure for: %s\n", norm->name); + buf[1] = norm->b; + buf[2] = norm->c; + buf[3] = norm->e; + return 0; +} + +static unsigned int port1 = UNSET; +static unsigned int port2 = UNSET; +static unsigned int qss = UNSET; +static unsigned int adjust = UNSET; + +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0) +MODULE_PARM(port1, "i"); +MODULE_PARM(port2, "i"); +MODULE_PARM(qss, "i"); +MODULE_PARM(adjust, "i"); +#else +module_param(port1, int, 0644); +module_param(port2, int, 0644); +module_param(qss, int, 0644); +module_param(adjust, int, 0644); +#endif + +static int tda9887_set_insmod(struct dvb_frontend *fe) +{ + struct tda9887_priv *priv = fe->analog_demod_priv; + char *buf = priv->data; + + if (UNSET != port1) { + if (port1) + buf[1] |= cOutputPort1Inactive; + else + buf[1] &= ~cOutputPort1Inactive; + } + if (UNSET != port2) { + if (port2) + buf[1] |= cOutputPort2Inactive; + else + buf[1] &= ~cOutputPort2Inactive; + } + + if (UNSET != qss) { + if (qss) + buf[1] |= cQSS; + else + buf[1] &= ~cQSS; + } + + if (adjust >= 0x00 && adjust < 0x20) { + buf[2] &= ~cTopMask; + buf[2] |= adjust; + } + return 0; +} + +static int tda9887_do_config(struct dvb_frontend *fe) +{ + struct tda9887_priv *priv = fe->analog_demod_priv; + char *buf = priv->data; + + if (priv->config & TDA9887_PORT1_ACTIVE) + buf[1] &= ~cOutputPort1Inactive; + if (priv->config & TDA9887_PORT1_INACTIVE) + buf[1] |= cOutputPort1Inactive; + if (priv->config & TDA9887_PORT2_ACTIVE) + buf[1] &= ~cOutputPort2Inactive; + if (priv->config & TDA9887_PORT2_INACTIVE) + buf[1] |= cOutputPort2Inactive; + + if (priv->config & TDA9887_QSS) + buf[1] |= cQSS; + if (priv->config & TDA9887_INTERCARRIER) + buf[1] &= ~cQSS; + + if (priv->config & TDA9887_AUTOMUTE) + buf[1] |= cAutoMuteFmActive; + if (priv->config & TDA9887_DEEMPHASIS_MASK) { + buf[2] &= ~0x60; + switch (priv->config & TDA9887_DEEMPHASIS_MASK) { + case TDA9887_DEEMPHASIS_NONE: + buf[2] |= cDeemphasisOFF; + break; + case TDA9887_DEEMPHASIS_50: + buf[2] |= cDeemphasisON | cDeemphasis50; + break; + case TDA9887_DEEMPHASIS_75: + buf[2] |= cDeemphasisON | cDeemphasis75; + break; + } + } + if (priv->config & TDA9887_TOP_SET) { + buf[2] &= ~cTopMask; + buf[2] |= (priv->config >> 8) & cTopMask; + } + if ((priv->config & TDA9887_INTERCARRIER_NTSC) && + (priv->std & V4L2_STD_NTSC)) + buf[1] &= ~cQSS; + if (priv->config & TDA9887_GATING_18) + buf[3] &= ~cGating_36; + + if (priv->mode == V4L2_TUNER_RADIO) { + if (priv->config & TDA9887_RIF_41_3) { + buf[3] &= ~cVideoIFMask; + buf[3] |= cRadioIF_41_30; + } + if (priv->config & TDA9887_GAIN_NORMAL) + buf[3] &= ~cTunerGainLow; + } + + return 0; +} + +/* ---------------------------------------------------------------------- */ + +static int tda9887_status(struct dvb_frontend *fe) +{ + struct tda9887_priv *priv = fe->analog_demod_priv; + unsigned char buf[1]; + int rc; + + memset(buf,0,sizeof(buf)); + if (1 != (rc = tuner_i2c_xfer_recv(&priv->i2c_props,buf,1))) + tuner_info("i2c i/o error: rc == %d (should be 1)\n", rc); + dump_read_message(fe, buf); + return 0; +} + +static void tda9887_configure(struct dvb_frontend *fe) +{ + struct tda9887_priv *priv = fe->analog_demod_priv; + int rc; + + memset(priv->data,0,sizeof(priv->data)); + tda9887_set_tvnorm(fe); + + /* A note on the port settings: + These settings tend to depend on the specifics of the board. + By default they are set to inactive (bit value 1) by this driver, + overwriting any changes made by the tvnorm. This means that it + is the responsibility of the module using the tda9887 to set + these values in case of changes in the tvnorm. + In many cases port 2 should be made active (0) when selecting + SECAM-L, and port 2 should remain inactive (1) for SECAM-L'. + + For the other standards the tda9887 application note says that + the ports should be set to active (0), but, again, that may + differ depending on the precise hardware configuration. + */ + priv->data[1] |= cOutputPort1Inactive; + priv->data[1] |= cOutputPort2Inactive; + + tda9887_do_config(fe); + tda9887_set_insmod(fe); + + if (priv->mode == T_STANDBY) + priv->data[1] |= cForcedMuteAudioON; + + tuner_dbg("writing: b=0x%02x c=0x%02x e=0x%02x\n", + priv->data[1], priv->data[2], priv->data[3]); + if (debug > 1) + dump_write_message(fe, priv->data); + + if (4 != (rc = tuner_i2c_xfer_send(&priv->i2c_props,priv->data,4))) + tuner_info("i2c i/o error: rc == %d (should be 4)\n", rc); + + if (debug > 2) { + msleep_interruptible(1000); + tda9887_status(fe); + } +} + +/* ---------------------------------------------------------------------- */ + +static void tda9887_tuner_status(struct dvb_frontend *fe) +{ + struct tda9887_priv *priv = fe->analog_demod_priv; + tuner_info("Data bytes: b=0x%02x c=0x%02x e=0x%02x\n", + priv->data[1], priv->data[2], priv->data[3]); +} + +static int tda9887_get_afc(struct dvb_frontend *fe) +{ + struct tda9887_priv *priv = fe->analog_demod_priv; + static int AFC_BITS_2_kHz[] = { + -12500, -37500, -62500, -97500, + -112500, -137500, -162500, -187500, + 187500, 162500, 137500, 112500, + 97500 , 62500, 37500 , 12500 + }; + int afc=0; + __u8 reg = 0; + + if (1 == tuner_i2c_xfer_recv(&priv->i2c_props,®,1)) + afc = AFC_BITS_2_kHz[(reg>>1)&0x0f]; + + return afc; +} + +static void tda9887_standby(struct dvb_frontend *fe) +{ + struct tda9887_priv *priv = fe->analog_demod_priv; + + priv->mode = T_STANDBY; + + tda9887_configure(fe); +} + +static void tda9887_set_params(struct dvb_frontend *fe, + struct analog_parameters *params) +{ + struct tda9887_priv *priv = fe->analog_demod_priv; + + priv->mode = params->mode; + priv->audmode = params->audmode; + priv->std = params->std; + tda9887_configure(fe); +} + +static int tda9887_set_config(struct dvb_frontend *fe, void *priv_cfg) +{ + struct tda9887_priv *priv = fe->analog_demod_priv; + + priv->config = *(unsigned int *)priv_cfg; + tda9887_configure(fe); + + return 0; +} + +static void tda9887_release(struct dvb_frontend *fe) +{ + struct tda9887_priv *priv = fe->analog_demod_priv; + + mutex_lock(&tda9887_list_mutex); + + if (priv) + hybrid_tuner_release_state(priv); + + mutex_unlock(&tda9887_list_mutex); + + fe->analog_demod_priv = NULL; +} + +static struct analog_demod_ops tda9887_ops = { + .info = { + .name = "tda9887", + }, + .set_params = tda9887_set_params, + .standby = tda9887_standby, + .tuner_status = tda9887_tuner_status, + .get_afc = tda9887_get_afc, + .release = tda9887_release, + .set_config = tda9887_set_config, +}; + +struct dvb_frontend *tda9887_attach(struct dvb_frontend *fe, + struct i2c_adapter *i2c_adap, + u8 i2c_addr) +{ + struct tda9887_priv *priv = NULL; + int instance; + + mutex_lock(&tda9887_list_mutex); + + instance = hybrid_tuner_request_state(struct tda9887_priv, priv, + hybrid_tuner_instance_list, + i2c_adap, i2c_addr, "tda9887"); + switch (instance) { + case 0: + mutex_unlock(&tda9887_list_mutex); + return NULL; + break; + case 1: + fe->analog_demod_priv = priv; + priv->mode = T_STANDBY; + tuner_info("tda988[5/6/7] found\n"); + break; + default: + fe->analog_demod_priv = priv; + break; + } + + mutex_unlock(&tda9887_list_mutex); + + memcpy(&fe->ops.analog_ops, &tda9887_ops, + sizeof(struct analog_demod_ops)); + + return fe; +} +EXPORT_SYMBOL_GPL(tda9887_attach); + +MODULE_LICENSE("GPL"); + +/* + * Overrides for Emacs so that we follow Linus's tabbing style. + * --------------------------------------------------------------------------- + * Local variables: + * c-basic-offset: 8 + * End: + */ diff --git a/linux/drivers/media/common/tuners/tda9887.h b/linux/drivers/media/common/tuners/tda9887.h new file mode 100644 index 000000000..be49dcbfc --- /dev/null +++ b/linux/drivers/media/common/tuners/tda9887.h @@ -0,0 +1,38 @@ +/* + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. +*/ + +#ifndef __TDA9887_H__ +#define __TDA9887_H__ + +#include +#include "dvb_frontend.h" + +/* ------------------------------------------------------------------------ */ +#if defined(CONFIG_TUNER_TDA9887) || (defined(CONFIG_TUNER_TDA9887_MODULE) && defined(MODULE)) +extern struct dvb_frontend *tda9887_attach(struct dvb_frontend *fe, + struct i2c_adapter *i2c_adap, + u8 i2c_addr); +#else +static inline struct dvb_frontend *tda9887_attach(struct dvb_frontend *fe, + struct i2c_adapter *i2c_adap, + u8 i2c_addr) +{ + printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__); + return NULL; +} +#endif + +#endif /* __TDA9887_H__ */ diff --git a/linux/drivers/media/common/tuners/tea5761.c b/linux/drivers/media/common/tuners/tea5761.c new file mode 100644 index 000000000..11e2991ef --- /dev/null +++ b/linux/drivers/media/common/tuners/tea5761.c @@ -0,0 +1,330 @@ +/* + * For Philips TEA5761 FM Chip + * I2C address is allways 0x20 (0x10 at 7-bit mode). + * + * Copyright (c) 2005-2007 Mauro Carvalho Chehab (mchehab@infradead.org) + * This code is placed under the terms of the GNUv2 General Public License + * + */ + +#include +#include +#include "compat.h" +#include +#include +#include "tuner-i2c.h" +#include "tea5761.h" + +static int debug; +module_param(debug, int, 0644); +MODULE_PARM_DESC(debug, "enable verbose debug messages"); + +struct tea5761_priv { + struct tuner_i2c_props i2c_props; + + u32 frequency; +}; + +/*****************************************************************************/ + +/*************************** + * TEA5761HN I2C registers * + ***************************/ + +/* INTREG - Read: bytes 0 and 1 / Write: byte 0 */ + + /* first byte for reading */ +#define TEA5761_INTREG_IFFLAG 0x10 +#define TEA5761_INTREG_LEVFLAG 0x8 +#define TEA5761_INTREG_FRRFLAG 0x2 +#define TEA5761_INTREG_BLFLAG 0x1 + + /* second byte for reading / byte for writing */ +#define TEA5761_INTREG_IFMSK 0x10 +#define TEA5761_INTREG_LEVMSK 0x8 +#define TEA5761_INTREG_FRMSK 0x2 +#define TEA5761_INTREG_BLMSK 0x1 + +/* FRQSET - Read: bytes 2 and 3 / Write: byte 1 and 2 */ + + /* First byte */ +#define TEA5761_FRQSET_SEARCH_UP 0x80 /* 1=Station search from botton to up */ +#define TEA5761_FRQSET_SEARCH_MODE 0x40 /* 1=Search mode */ + + /* Bits 0-5 for divider MSB */ + + /* Second byte */ + /* Bits 0-7 for divider LSB */ + +/* TNCTRL - Read: bytes 4 and 5 / Write: Bytes 3 and 4 */ + + /* first byte */ + +#define TEA5761_TNCTRL_PUPD_0 0x40 /* Power UP/Power Down MSB */ +#define TEA5761_TNCTRL_BLIM 0X20 /* 1= Japan Frequencies, 0= European frequencies */ +#define TEA5761_TNCTRL_SWPM 0x10 /* 1= software port is FRRFLAG */ +#define TEA5761_TNCTRL_IFCTC 0x08 /* 1= IF count time 15.02 ms, 0= IF count time 2.02 ms */ +#define TEA5761_TNCTRL_AFM 0x04 +#define TEA5761_TNCTRL_SMUTE 0x02 /* 1= Soft mute */ +#define TEA5761_TNCTRL_SNC 0x01 + + /* second byte */ + +#define TEA5761_TNCTRL_MU 0x80 /* 1=Hard mute */ +#define TEA5761_TNCTRL_SSL_1 0x40 +#define TEA5761_TNCTRL_SSL_0 0x20 +#define TEA5761_TNCTRL_HLSI 0x10 +#define TEA5761_TNCTRL_MST 0x08 /* 1 = mono */ +#define TEA5761_TNCTRL_SWP 0x04 +#define TEA5761_TNCTRL_DTC 0x02 /* 1 = deemphasis 50 us, 0 = deemphasis 75 us */ +#define TEA5761_TNCTRL_AHLSI 0x01 + +/* FRQCHECK - Read: bytes 6 and 7 */ + /* First byte */ + + /* Bits 0-5 for divider MSB */ + + /* Second byte */ + /* Bits 0-7 for divider LSB */ + +/* TUNCHECK - Read: bytes 8 and 9 */ + + /* First byte */ +#define TEA5761_TUNCHECK_IF_MASK 0x7e /* IF count */ +#define TEA5761_TUNCHECK_TUNTO 0x01 + + /* Second byte */ +#define TEA5761_TUNCHECK_LEV_MASK 0xf0 /* Level Count */ +#define TEA5761_TUNCHECK_LD 0x08 +#define TEA5761_TUNCHECK_STEREO 0x04 + +/* TESTREG - Read: bytes 10 and 11 / Write: bytes 5 and 6 */ + + /* All zero = no test mode */ + +/* MANID - Read: bytes 12 and 13 */ + + /* First byte - should be 0x10 */ +#define TEA5767_MANID_VERSION_MASK 0xf0 /* Version = 1 */ +#define TEA5767_MANID_ID_MSB_MASK 0x0f /* Manufacurer ID - should be 0 */ + + /* Second byte - Should be 0x2b */ + +#define TEA5767_MANID_ID_LSB_MASK 0xfe /* Manufacturer ID - should be 0x15 */ +#define TEA5767_MANID_IDAV 0x01 /* 1 = Chip has ID, 0 = Chip has no ID */ + +/* Chip ID - Read: bytes 14 and 15 */ + + /* First byte - should be 0x57 */ + + /* Second byte - should be 0x61 */ + +/*****************************************************************************/ + +#define FREQ_OFFSET 0 /* for TEA5767, it is 700 to give the right freq */ +static void tea5761_status_dump(unsigned char *buffer) +{ + unsigned int div, frq; + + div = ((buffer[2] & 0x3f) << 8) | buffer[3]; + + frq = 1000 * (div * 32768 / 1000 + FREQ_OFFSET + 225) / 4; /* Freq in KHz */ + + printk(KERN_INFO "tea5761: Frequency %d.%03d KHz (divider = 0x%04x)\n", + frq / 1000, frq % 1000, div); +} + +/* Freq should be specifyed at 62.5 Hz */ +static int set_radio_freq(struct dvb_frontend *fe, + struct analog_parameters *params) +{ + struct tea5761_priv *priv = fe->tuner_priv; + unsigned int frq = params->frequency; + unsigned char buffer[7] = {0, 0, 0, 0, 0, 0, 0 }; + unsigned div; + int rc; + + tuner_dbg("radio freq counter %d\n", frq); + + if (params->mode == T_STANDBY) { + tuner_dbg("TEA5761 set to standby mode\n"); + buffer[5] |= TEA5761_TNCTRL_MU; + } else { + buffer[4] |= TEA5761_TNCTRL_PUPD_0; + } + + + if (params->audmode == V4L2_TUNER_MODE_MONO) { + tuner_dbg("TEA5761 set to mono\n"); + buffer[5] |= TEA5761_TNCTRL_MST; + } else { + tuner_dbg("TEA5761 set to stereo\n"); + } + + div = (1000 * (frq * 4 / 16 + 700 + 225) ) >> 15; + buffer[1] = (div >> 8) & 0x3f; + buffer[2] = div & 0xff; + + if (debug) + tea5761_status_dump(buffer); + + if (7 != (rc = tuner_i2c_xfer_send(&priv->i2c_props, buffer, 7))) + tuner_warn("i2c i/o error: rc == %d (should be 5)\n", rc); + + priv->frequency = frq * 125 / 2; + + return 0; +} + +static int tea5761_read_status(struct dvb_frontend *fe, char *buffer) +{ + struct tea5761_priv *priv = fe->tuner_priv; + int rc; + + memset(buffer, 0, 16); + if (16 != (rc = tuner_i2c_xfer_recv(&priv->i2c_props, buffer, 16))) { + tuner_warn("i2c i/o error: rc == %d (should be 16)\n", rc); + return -EREMOTEIO; + } + + return 0; +} + +static inline int tea5761_signal(struct dvb_frontend *fe, const char *buffer) +{ + struct tea5761_priv *priv = fe->tuner_priv; + + int signal = ((buffer[9] & TEA5761_TUNCHECK_LEV_MASK) << (13 - 4)); + + tuner_dbg("Signal strength: %d\n", signal); + + return signal; +} + +static inline int tea5761_stereo(struct dvb_frontend *fe, const char *buffer) +{ + struct tea5761_priv *priv = fe->tuner_priv; + + int stereo = buffer[9] & TEA5761_TUNCHECK_STEREO; + + tuner_dbg("Radio ST GET = %02x\n", stereo); + + return (stereo ? V4L2_TUNER_SUB_STEREO : 0); +} + +static int tea5761_get_status(struct dvb_frontend *fe, u32 *status) +{ + unsigned char buffer[16]; + + *status = 0; + + if (0 == tea5761_read_status(fe, buffer)) { + if (tea5761_signal(fe, buffer)) + *status = TUNER_STATUS_LOCKED; + if (tea5761_stereo(fe, buffer)) + *status |= TUNER_STATUS_STEREO; + } + + return 0; +} + +static int tea5761_get_rf_strength(struct dvb_frontend *fe, u16 *strength) +{ + unsigned char buffer[16]; + + *strength = 0; + + if (0 == tea5761_read_status(fe, buffer)) + *strength = tea5761_signal(fe, buffer); + + return 0; +} + +int tea5761_autodetection(struct i2c_adapter* i2c_adap, u8 i2c_addr) +{ + unsigned char buffer[16]; + int rc; + struct tuner_i2c_props i2c = { .adap = i2c_adap, .addr = i2c_addr }; + + if (16 != (rc = tuner_i2c_xfer_recv(&i2c, buffer, 16))) { + printk(KERN_WARNING "it is not a TEA5761. Received %i chars.\n", rc); + return -EINVAL; + } + + if ((buffer[13] != 0x2b) || (buffer[14] != 0x57) || (buffer[15] != 0x061)) { + printk(KERN_WARNING "Manufacturer ID= 0x%02x, Chip ID = %02x%02x." + " It is not a TEA5761\n", + buffer[13], buffer[14], buffer[15]); + return -EINVAL; + } + printk(KERN_WARNING "tea5761: TEA%02x%02x detected. " + "Manufacturer ID= 0x%02x\n", + buffer[14], buffer[15], buffer[13]); + + return 0; +} + +static int tea5761_release(struct dvb_frontend *fe) +{ + kfree(fe->tuner_priv); + fe->tuner_priv = NULL; + + return 0; +} + +static int tea5761_get_frequency(struct dvb_frontend *fe, u32 *frequency) +{ + struct tea5761_priv *priv = fe->tuner_priv; + *frequency = priv->frequency; + return 0; +} + +static struct dvb_tuner_ops tea5761_tuner_ops = { + .info = { + .name = "tea5761", // Philips TEA5761HN FM Radio +#if 0 + .frequency_min = , + .frequency_max = , + .frequency_step = , +#endif + }, + .set_analog_params = set_radio_freq, + .release = tea5761_release, + .get_frequency = tea5761_get_frequency, + .get_status = tea5761_get_status, + .get_rf_strength = tea5761_get_rf_strength, +}; + +struct dvb_frontend *tea5761_attach(struct dvb_frontend *fe, + struct i2c_adapter* i2c_adap, + u8 i2c_addr) +{ + struct tea5761_priv *priv = NULL; + + if (tea5761_autodetection(i2c_adap, i2c_addr) == EINVAL) + return NULL; + + priv = kzalloc(sizeof(struct tea5761_priv), GFP_KERNEL); + if (priv == NULL) + return NULL; + fe->tuner_priv = priv; + + priv->i2c_props.addr = i2c_addr; + priv->i2c_props.adap = i2c_adap; + priv->i2c_props.name = "tea5761"; + + memcpy(&fe->ops.tuner_ops, &tea5761_tuner_ops, + sizeof(struct dvb_tuner_ops)); + + tuner_info("type set to %s\n", "Philips TEA5761HN FM Radio"); + + return fe; +} + + +EXPORT_SYMBOL_GPL(tea5761_attach); +EXPORT_SYMBOL_GPL(tea5761_autodetection); + +MODULE_DESCRIPTION("Philips TEA5761 FM tuner driver"); +MODULE_AUTHOR("Mauro Carvalho Chehab "); +MODULE_LICENSE("GPL"); diff --git a/linux/drivers/media/common/tuners/tea5761.h b/linux/drivers/media/common/tuners/tea5761.h new file mode 100644 index 000000000..8eb62722b --- /dev/null +++ b/linux/drivers/media/common/tuners/tea5761.h @@ -0,0 +1,47 @@ +/* + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. +*/ + +#ifndef __TEA5761_H__ +#define __TEA5761_H__ + +#include +#include "dvb_frontend.h" + +#if defined(CONFIG_TUNER_TEA5761) || (defined(CONFIG_TUNER_TEA5761_MODULE) && defined(MODULE)) +extern int tea5761_autodetection(struct i2c_adapter* i2c_adap, u8 i2c_addr); + +extern struct dvb_frontend *tea5761_attach(struct dvb_frontend *fe, + struct i2c_adapter* i2c_adap, + u8 i2c_addr); +#else +static inline int tea5761_autodetection(struct i2c_adapter* i2c_adap, + u8 i2c_addr) +{ + printk(KERN_INFO "%s: not probed - driver disabled by Kconfig\n", + __func__); + return -EINVAL; +} + +static inline struct dvb_frontend *tea5761_attach(struct dvb_frontend *fe, + struct i2c_adapter* i2c_adap, + u8 i2c_addr) +{ + printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__); + return NULL; +} +#endif + +#endif /* __TEA5761_H__ */ diff --git a/linux/drivers/media/common/tuners/tea5767.c b/linux/drivers/media/common/tuners/tea5767.c new file mode 100644 index 000000000..e5bfc72a4 --- /dev/null +++ b/linux/drivers/media/common/tuners/tea5767.c @@ -0,0 +1,525 @@ +/* + * For Philips TEA5767 FM Chip used on some TV Cards like Prolink Pixelview + * I2C address is allways 0xC0. + * + * + * Copyright (c) 2005 Mauro Carvalho Chehab (mchehab@infradead.org) + * This code is placed under the terms of the GNU General Public License + * + * tea5767 autodetection thanks to Torsten Seeboth and Atsushi Nakagawa + * from their contributions on DScaler. + */ + +#include +#include +#include "compat.h" +#include +#include "tuner-i2c.h" +#include "tea5767.h" +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0) +#include "i2c-compat.h" +#endif + +static int debug; +module_param(debug, int, 0644); +MODULE_PARM_DESC(debug, "enable verbose debug messages"); + +/*****************************************************************************/ + +struct tea5767_priv { + struct tuner_i2c_props i2c_props; + u32 frequency; + struct tea5767_ctrl ctrl; +}; + +/*****************************************************************************/ + +/****************************** + * Write mode register values * + ******************************/ + +/* First register */ +#define TEA5767_MUTE 0x80 /* Mutes output */ +#define TEA5767_SEARCH 0x40 /* Activates station search */ +/* Bits 0-5 for divider MSB */ + +/* Second register */ +/* Bits 0-7 for divider LSB */ + +/* Third register */ + +/* Station search from botton to up */ +#define TEA5767_SEARCH_UP 0x80 + +/* Searches with ADC output = 10 */ +#define TEA5767_SRCH_HIGH_LVL 0x60 + +/* Searches with ADC output = 10 */ +#define TEA5767_SRCH_MID_LVL 0x40 + +/* Searches with ADC output = 5 */ +#define TEA5767_SRCH_LOW_LVL 0x20 + +/* if on, div=4*(Frf+Fif)/Fref otherwise, div=4*(Frf-Fif)/Freq) */ +#define TEA5767_HIGH_LO_INJECT 0x10 + +/* Disable stereo */ +#define TEA5767_MONO 0x08 + +/* Disable right channel and turns to mono */ +#define TEA5767_MUTE_RIGHT 0x04 + +/* Disable left channel and turns to mono */ +#define TEA5767_MUTE_LEFT 0x02 + +#define TEA5767_PORT1_HIGH 0x01 + +/* Fourth register */ +#define TEA5767_PORT2_HIGH 0x80 +/* Chips stops working. Only I2C bus remains on */ +#define TEA5767_STDBY 0x40 + +/* Japan freq (76-108 MHz. If disabled, 87.5-108 MHz */ +#define TEA5767_JAPAN_BAND 0x20 + +/* Unselected means 32.768 KHz freq as reference. Otherwise Xtal at 13 MHz */ +#define TEA5767_XTAL_32768 0x10 + +/* Cuts weak signals */ +#define TEA5767_SOFT_MUTE 0x08 + +/* Activates high cut control */ +#define TEA5767_HIGH_CUT_CTRL 0x04 + +/* Activates stereo noise control */ +#define TEA5767_ST_NOISE_CTL 0x02 + +/* If activate PORT 1 indicates SEARCH or else it is used as PORT1 */ +#define TEA5767_SRCH_IND 0x01 + +/* Fifth register */ + +/* By activating, it will use Xtal at 13 MHz as reference for divider */ +#define TEA5767_PLLREF_ENABLE 0x80 + +/* By activating, deemphasis=50, or else, deemphasis of 50us */ +#define TEA5767_DEEMPH_75 0X40 + +/***************************** + * Read mode register values * + *****************************/ + +/* First register */ +#define TEA5767_READY_FLAG_MASK 0x80 +#define TEA5767_BAND_LIMIT_MASK 0X40 +/* Bits 0-5 for divider MSB after search or preset */ + +/* Second register */ +/* Bits 0-7 for divider LSB after search or preset */ + +/* Third register */ +#define TEA5767_STEREO_MASK 0x80 +#define TEA5767_IF_CNTR_MASK 0x7f + +/* Fourth register */ +#define TEA5767_ADC_LEVEL_MASK 0xf0 + +/* should be 0 */ +#define TEA5767_CHIP_ID_MASK 0x0f + +/* Fifth register */ +/* Reserved for future extensions */ +#define TEA5767_RESERVED_MASK 0xff + +/*****************************************************************************/ + +static void tea5767_status_dump(struct tea5767_priv *priv, + unsigned char *buffer) +{ + unsigned int div, frq; + + if (TEA5767_READY_FLAG_MASK & buffer[0]) + tuner_info("Ready Flag ON\n"); + else + tuner_info("Ready Flag OFF\n"); + + if (TEA5767_BAND_LIMIT_MASK & buffer[0]) + tuner_info("Tuner at band limit\n"); + else + tuner_info("Tuner not at band limit\n"); + + div = ((buffer[0] & 0x3f) << 8) | buffer[1]; + + switch (priv->ctrl.xtal_freq) { + case TEA5767_HIGH_LO_13MHz: + frq = (div * 50000 - 700000 - 225000) / 4; /* Freq in KHz */ + break; + case TEA5767_LOW_LO_13MHz: + frq = (div * 50000 + 700000 + 225000) / 4; /* Freq in KHz */ + break; + case TEA5767_LOW_LO_32768: + frq = (div * 32768 + 700000 + 225000) / 4; /* Freq in KHz */ + break; + case TEA5767_HIGH_LO_32768: + default: + frq = (div * 32768 - 700000 - 225000) / 4; /* Freq in KHz */ + break; + } + buffer[0] = (div >> 8) & 0x3f; + buffer[1] = div & 0xff; + + tuner_info("Frequency %d.%03d KHz (divider = 0x%04x)\n", + frq / 1000, frq % 1000, div); + + if (TEA5767_STEREO_MASK & buffer[2]) + tuner_info("Stereo\n"); + else + tuner_info("Mono\n"); + + tuner_info("IF Counter = %d\n", buffer[2] & TEA5767_IF_CNTR_MASK); + + tuner_info("ADC Level = %d\n", + (buffer[3] & TEA5767_ADC_LEVEL_MASK) >> 4); + + tuner_info("Chip ID = %d\n", (buffer[3] & TEA5767_CHIP_ID_MASK)); + + tuner_info("Reserved = 0x%02x\n", + (buffer[4] & TEA5767_RESERVED_MASK)); +} + +/* Freq should be specifyed at 62.5 Hz */ +static int set_radio_freq(struct dvb_frontend *fe, + struct analog_parameters *params) +{ + struct tea5767_priv *priv = fe->tuner_priv; + unsigned int frq = params->frequency; + unsigned char buffer[5]; + unsigned div; + int rc; + + tuner_dbg("radio freq = %d.%03d MHz\n", frq/16000,(frq/16)%1000); + + buffer[2] = 0; + + if (priv->ctrl.port1) + buffer[2] |= TEA5767_PORT1_HIGH; + + if (params->audmode == V4L2_TUNER_MODE_MONO) { + tuner_dbg("TEA5767 set to mono\n"); + buffer[2] |= TEA5767_MONO; + } else { + tuner_dbg("TEA5767 set to stereo\n"); + } + + + buffer[3] = 0; + + if (priv->ctrl.port2) + buffer[3] |= TEA5767_PORT2_HIGH; + + if (priv->ctrl.high_cut) + buffer[3] |= TEA5767_HIGH_CUT_CTRL; + + if (priv->ctrl.st_noise) + buffer[3] |= TEA5767_ST_NOISE_CTL; + + if (priv->ctrl.soft_mute) + buffer[3] |= TEA5767_SOFT_MUTE; + + if (priv->ctrl.japan_band) + buffer[3] |= TEA5767_JAPAN_BAND; + + buffer[4] = 0; + + if (priv->ctrl.deemph_75) + buffer[4] |= TEA5767_DEEMPH_75; + + if (priv->ctrl.pllref) + buffer[4] |= TEA5767_PLLREF_ENABLE; + + + /* Rounds freq to next decimal value - for 62.5 KHz step */ + /* frq = 20*(frq/16)+radio_frq[frq%16]; */ + + switch (priv->ctrl.xtal_freq) { + case TEA5767_HIGH_LO_13MHz: + tuner_dbg("radio HIGH LO inject xtal @ 13 MHz\n"); + buffer[2] |= TEA5767_HIGH_LO_INJECT; + div = (frq * (4000 / 16) + 700000 + 225000 + 25000) / 50000; + break; + case TEA5767_LOW_LO_13MHz: + tuner_dbg("radio LOW LO inject xtal @ 13 MHz\n"); + + div = (frq * (4000 / 16) - 700000 - 225000 + 25000) / 50000; + break; + case TEA5767_LOW_LO_32768: + tuner_dbg("radio LOW LO inject xtal @ 32,768 MHz\n"); + buffer[3] |= TEA5767_XTAL_32768; + /* const 700=4000*175 Khz - to adjust freq to right value */ + div = ((frq * (4000 / 16) - 700000 - 225000) + 16384) >> 15; + break; + case TEA5767_HIGH_LO_32768: + default: + tuner_dbg("radio HIGH LO inject xtal @ 32,768 MHz\n"); + + buffer[2] |= TEA5767_HIGH_LO_INJECT; + buffer[3] |= TEA5767_XTAL_32768; + div = ((frq * (4000 / 16) + 700000 + 225000) + 16384) >> 15; + break; + } + buffer[0] = (div >> 8) & 0x3f; + buffer[1] = div & 0xff; + + if (5 != (rc = tuner_i2c_xfer_send(&priv->i2c_props, buffer, 5))) + tuner_warn("i2c i/o error: rc == %d (should be 5)\n", rc); + + if (debug) { + if (5 != (rc = tuner_i2c_xfer_recv(&priv->i2c_props, buffer, 5))) + tuner_warn("i2c i/o error: rc == %d (should be 5)\n", rc); + else + tea5767_status_dump(priv, buffer); + } + + priv->frequency = frq * 125 / 2; + + return 0; +} + +static int tea5767_read_status(struct dvb_frontend *fe, char *buffer) +{ + struct tea5767_priv *priv = fe->tuner_priv; + int rc; + + memset(buffer, 0, 5); + if (5 != (rc = tuner_i2c_xfer_recv(&priv->i2c_props, buffer, 5))) { + tuner_warn("i2c i/o error: rc == %d (should be 5)\n", rc); + return -EREMOTEIO; + } + + return 0; +} + +static inline int tea5767_signal(struct dvb_frontend *fe, const char *buffer) +{ + struct tea5767_priv *priv = fe->tuner_priv; + + int signal = ((buffer[3] & TEA5767_ADC_LEVEL_MASK) << 8); + + tuner_dbg("Signal strength: %d\n", signal); + + return signal; +} + +static inline int tea5767_stereo(struct dvb_frontend *fe, const char *buffer) +{ + struct tea5767_priv *priv = fe->tuner_priv; + + int stereo = buffer[2] & TEA5767_STEREO_MASK; + + tuner_dbg("Radio ST GET = %02x\n", stereo); + + return (stereo ? V4L2_TUNER_SUB_STEREO : 0); +} + +static int tea5767_get_status(struct dvb_frontend *fe, u32 *status) +{ + unsigned char buffer[5]; + + *status = 0; + + if (0 == tea5767_read_status(fe, buffer)) { + if (tea5767_signal(fe, buffer)) + *status = TUNER_STATUS_LOCKED; + if (tea5767_stereo(fe, buffer)) + *status |= TUNER_STATUS_STEREO; + } + + return 0; +} + +static int tea5767_get_rf_strength(struct dvb_frontend *fe, u16 *strength) +{ + unsigned char buffer[5]; + + *strength = 0; + + if (0 == tea5767_read_status(fe, buffer)) + *strength = tea5767_signal(fe, buffer); + + return 0; +} + +static int tea5767_standby(struct dvb_frontend *fe) +{ + unsigned char buffer[5]; + struct tea5767_priv *priv = fe->tuner_priv; + unsigned div, rc; + + div = (87500 * 4 + 700 + 225 + 25) / 50; /* Set frequency to 87.5 MHz */ + buffer[0] = (div >> 8) & 0x3f; + buffer[1] = div & 0xff; + buffer[2] = TEA5767_PORT1_HIGH; + buffer[3] = TEA5767_PORT2_HIGH | TEA5767_HIGH_CUT_CTRL | + TEA5767_ST_NOISE_CTL | TEA5767_JAPAN_BAND | TEA5767_STDBY; + buffer[4] = 0; + + if (5 != (rc = tuner_i2c_xfer_send(&priv->i2c_props, buffer, 5))) + tuner_warn("i2c i/o error: rc == %d (should be 5)\n", rc); + + return 0; +} + +int tea5767_autodetection(struct i2c_adapter* i2c_adap, u8 i2c_addr) +{ + struct tuner_i2c_props i2c = { .adap = i2c_adap, .addr = i2c_addr }; + unsigned char buffer[7] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }; + int rc; +#if 0 /* Needed if uncomment I2C send code below */ + int div; +#endif + + if ((rc = tuner_i2c_xfer_recv(&i2c, buffer, 7))< 5) { + printk(KERN_WARNING "It is not a TEA5767. Received %i bytes.\n", rc); + return EINVAL; + } + + /* If all bytes are the same then it's a TV tuner and not a tea5767 */ + if (buffer[0] == buffer[1] && buffer[0] == buffer[2] && + buffer[0] == buffer[3] && buffer[0] == buffer[4]) { + printk(KERN_WARNING "All bytes are equal. It is not a TEA5767\n"); + return EINVAL; + } + + /* Status bytes: + * Byte 4: bit 3:1 : CI (Chip Identification) == 0 + * bit 0 : internally set to 0 + * Byte 5: bit 7:0 : == 0 + */ + if (((buffer[3] & 0x0f) != 0x00) || (buffer[4] != 0x00)) { + printk(KERN_WARNING "Chip ID is not zero. It is not a TEA5767\n"); + return EINVAL; + } + +#if 0 /* Not working for TEA5767 in Beholder Columbus card */ + /* It seems that tea5767 returns 0xff after the 5th byte */ + if ((buffer[5] != 0xff) || (buffer[6] != 0xff)) { + printk(KERN_WARNING "Returned more than 5 bytes. It is not a TEA5767\n"); + return EINVAL; + } +#endif + +#if 0 /*Sometimes, this code doesn't work */ + /* Sets tuner at some freq (87.5 MHz) and see if it is ok */ + div = ((87500 * 4000 + 700000 + 225000) + 16768) >> 15; + buffer[0] = ((div >> 8) & 0x3f) | TEA5767_MUTE; + buffer[1] = div & 0xff; + buffer[2] = TEA5767_PORT1_HIGH; + buffer[3] = TEA5767_PORT2_HIGH | TEA5767_HIGH_CUT_CTRL | + TEA5767_ST_NOISE_CTL; + buffer[4] = 0; + + if (5 != (rc = tuner_i2c_xfer_send(&i2c, buffer, 5))) + printk(KERN_WARNING "i2c i/o error: rc == %d (should be 5)\n", rc); + + msleep(15); + + if (5 != (rc = tuner_i2c_xfer_recv(&i2c, buffer, 5))) { + printk(KERN_WARNING "It is not a TEA5767. Received %i bytes.\n", rc); + return EINVAL; + } + + /* Initial freq for 32.768KHz clock */ + if ((buffer[1] != (div & 0xff) ) || ((buffer[0] & 0x3f) != ((div >> 8) & 0x3f))) { + printk(KERN_WARNING "It is not a TEA5767. div=%d, Return: %02x %02x %02x %02x %02x\n", + div,buffer[0],buffer[1],buffer[2],buffer[3],buffer[4]); + tea5767_status_dump(buffer); + return EINVAL; + } +#endif + return 0; +} + +static int tea5767_release(struct dvb_frontend *fe) +{ + kfree(fe->tuner_priv); + fe->tuner_priv = NULL; + + return 0; +} + +static int tea5767_get_frequency(struct dvb_frontend *fe, u32 *frequency) +{ + struct tea5767_priv *priv = fe->tuner_priv; + *frequency = priv->frequency; + + return 0; +} + +static int tea5767_set_config (struct dvb_frontend *fe, void *priv_cfg) +{ + struct tea5767_priv *priv = fe->tuner_priv; + + memcpy(&priv->ctrl, priv_cfg, sizeof(priv->ctrl)); + + return 0; +} + +static struct dvb_tuner_ops tea5767_tuner_ops = { + .info = { + .name = "tea5767", // Philips TEA5767HN FM Radio +#if 0 + .frequency_min = , + .frequency_max = , + .frequency_step = , +#endif + }, + + .set_analog_params = set_radio_freq, + .set_config = tea5767_set_config, + .sleep = tea5767_standby, + .release = tea5767_release, + .get_frequency = tea5767_get_frequency, + .get_status = tea5767_get_status, + .get_rf_strength = tea5767_get_rf_strength, +}; + +struct dvb_frontend *tea5767_attach(struct dvb_frontend *fe, + struct i2c_adapter* i2c_adap, + u8 i2c_addr) +{ + struct tea5767_priv *priv = NULL; + +#if 0 /* By removing autodetection allows forcing TEA chip */ + if (tea5767_autodetection(i2c_adap, i2c_addr) == EINVAL) + return EINVAL; +#endif + priv = kzalloc(sizeof(struct tea5767_priv), GFP_KERNEL); + if (priv == NULL) + return NULL; + fe->tuner_priv = priv; + + priv->i2c_props.addr = i2c_addr; + priv->i2c_props.adap = i2c_adap; + priv->i2c_props.name = "tea5767"; + + priv->ctrl.xtal_freq = TEA5767_HIGH_LO_32768; + priv->ctrl.port1 = 1; + priv->ctrl.port2 = 1; + priv->ctrl.high_cut = 1; + priv->ctrl.st_noise = 1; + priv->ctrl.japan_band = 1; + + memcpy(&fe->ops.tuner_ops, &tea5767_tuner_ops, + sizeof(struct dvb_tuner_ops)); + + tuner_info("type set to %s\n", "Philips TEA5767HN FM Radio"); + + return fe; +} + +EXPORT_SYMBOL_GPL(tea5767_attach); +EXPORT_SYMBOL_GPL(tea5767_autodetection); + +MODULE_DESCRIPTION("Philips TEA5767 FM tuner driver"); +MODULE_AUTHOR("Mauro Carvalho Chehab "); +MODULE_LICENSE("GPL"); diff --git a/linux/drivers/media/common/tuners/tea5767.h b/linux/drivers/media/common/tuners/tea5767.h new file mode 100644 index 000000000..7b547c092 --- /dev/null +++ b/linux/drivers/media/common/tuners/tea5767.h @@ -0,0 +1,66 @@ +/* + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. +*/ + +#ifndef __TEA5767_H__ +#define __TEA5767_H__ + +#include +#include "dvb_frontend.h" + +enum tea5767_xtal { + TEA5767_LOW_LO_32768 = 0, + TEA5767_HIGH_LO_32768 = 1, + TEA5767_LOW_LO_13MHz = 2, + TEA5767_HIGH_LO_13MHz = 3, +}; + +struct tea5767_ctrl { + unsigned int port1:1; + unsigned int port2:1; + unsigned int high_cut:1; + unsigned int st_noise:1; + unsigned int soft_mute:1; + unsigned int japan_band:1; + unsigned int deemph_75:1; + unsigned int pllref:1; + enum tea5767_xtal xtal_freq; +}; + +#if defined(CONFIG_TUNER_TEA5767) || (defined(CONFIG_TUNER_TEA5767_MODULE) && defined(MODULE)) +extern int tea5767_autodetection(struct i2c_adapter* i2c_adap, u8 i2c_addr); + +extern struct dvb_frontend *tea5767_attach(struct dvb_frontend *fe, + struct i2c_adapter* i2c_adap, + u8 i2c_addr); +#else +static inline int tea5767_autodetection(struct i2c_adapter* i2c_adap, + u8 i2c_addr) +{ + printk(KERN_INFO "%s: not probed - driver disabled by Kconfig\n", + __func__); + return -EINVAL; +} + +static inline struct dvb_frontend *tea5767_attach(struct dvb_frontend *fe, + struct i2c_adapter* i2c_adap, + u8 i2c_addr) +{ + printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__); + return NULL; +} +#endif + +#endif /* __TEA5767_H__ */ diff --git a/linux/drivers/media/common/tuners/tuner-i2c.h b/linux/drivers/media/common/tuners/tuner-i2c.h new file mode 100644 index 000000000..3ad6c8e0b --- /dev/null +++ b/linux/drivers/media/common/tuners/tuner-i2c.h @@ -0,0 +1,173 @@ +/* + tuner-i2c.h - i2c interface for different tuners + + Copyright (C) 2007 Michael Krufky (mkrufky@linuxtv.org) + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. +*/ + +#ifndef __TUNER_I2C_H__ +#define __TUNER_I2C_H__ + +#include + +struct tuner_i2c_props { + u8 addr; + struct i2c_adapter *adap; + + /* used for tuner instance management */ + int count; + char *name; +}; + +static inline int tuner_i2c_xfer_send(struct tuner_i2c_props *props, char *buf, int len) +{ + struct i2c_msg msg = { .addr = props->addr, .flags = 0, + .buf = buf, .len = len }; + int ret = i2c_transfer(props->adap, &msg, 1); + + return (ret == 1) ? len : ret; +} + +static inline int tuner_i2c_xfer_recv(struct tuner_i2c_props *props, char *buf, int len) +{ + struct i2c_msg msg = { .addr = props->addr, .flags = I2C_M_RD, + .buf = buf, .len = len }; + int ret = i2c_transfer(props->adap, &msg, 1); + + return (ret == 1) ? len : ret; +} + +static inline int tuner_i2c_xfer_send_recv(struct tuner_i2c_props *props, + char *obuf, int olen, + char *ibuf, int ilen) +{ + struct i2c_msg msg[2] = { { .addr = props->addr, .flags = 0, + .buf = obuf, .len = olen }, + { .addr = props->addr, .flags = I2C_M_RD, + .buf = ibuf, .len = ilen } }; + int ret = i2c_transfer(props->adap, msg, 2); + + return (ret == 2) ? ilen : ret; +} + +/* Callers must declare as a global for the module: + * + * static LIST_HEAD(hybrid_tuner_instance_list); + * + * hybrid_tuner_instance_list should be the third argument + * passed into hybrid_tuner_request_state(). + * + * state structure must contain the following: + * + * struct list_head hybrid_tuner_instance_list; + * struct tuner_i2c_props i2c_props; + * + * hybrid_tuner_instance_list (both within state structure and globally) + * is only required if the driver is using hybrid_tuner_request_state + * and hybrid_tuner_release_state to manage state sharing between + * multiple instances of hybrid tuners. + */ + +#define tuner_printk(kernlvl, i2cprops, fmt, arg...) do { \ + printk(kernlvl "%s %d-%04x: " fmt, i2cprops.name, \ + i2cprops.adap ? \ + i2c_adapter_id(i2cprops.adap) : -1, \ + i2cprops.addr, ##arg); \ + } while (0) + +/* TO DO: convert all callers of these macros to pass in + * struct tuner_i2c_props, then remove the macro wrappers */ + +#define __tuner_warn(i2cprops, fmt, arg...) do { \ + tuner_printk(KERN_WARNING, i2cprops, fmt, ##arg); \ + } while (0) + +#define __tuner_info(i2cprops, fmt, arg...) do { \ + tuner_printk(KERN_INFO, i2cprops, fmt, ##arg); \ + } while (0) + +#define __tuner_err(i2cprops, fmt, arg...) do { \ + tuner_printk(KERN_ERR, i2cprops, fmt, ##arg); \ + } while (0) + +#define __tuner_dbg(i2cprops, fmt, arg...) do { \ + if ((debug)) \ + tuner_printk(KERN_DEBUG, i2cprops, fmt, ##arg); \ + } while (0) + +#define tuner_warn(fmt, arg...) __tuner_warn(priv->i2c_props, fmt, ##arg) +#define tuner_info(fmt, arg...) __tuner_info(priv->i2c_props, fmt, ##arg) +#define tuner_err(fmt, arg...) __tuner_err(priv->i2c_props, fmt, ##arg) +#define tuner_dbg(fmt, arg...) __tuner_dbg(priv->i2c_props, fmt, ##arg) + +/****************************************************************************/ + +/* The return value of hybrid_tuner_request_state indicates the number of + * instances using this tuner object. + * + * 0 - no instances, indicates an error - kzalloc must have failed + * + * 1 - one instance, indicates that the tuner object was created successfully + * + * 2 (or more) instances, indicates that an existing tuner object was found + */ + +#define hybrid_tuner_request_state(type, state, list, i2cadap, i2caddr, devname)\ +({ \ + int __ret = 0; \ + list_for_each_entry(state, &list, hybrid_tuner_instance_list) { \ + if (((i2cadap) && (state->i2c_props.adap)) && \ + ((i2c_adapter_id(state->i2c_props.adap) == \ + i2c_adapter_id(i2cadap)) && \ + (i2caddr == state->i2c_props.addr))) { \ + __tuner_info(state->i2c_props, \ + "attaching existing instance\n"); \ + state->i2c_props.count++; \ + __ret = state->i2c_props.count; \ + break; \ + } \ + } \ + if (0 == __ret) { \ + state = kzalloc(sizeof(type), GFP_KERNEL); \ + if (NULL == state) \ + goto __fail; \ + state->i2c_props.addr = i2caddr; \ + state->i2c_props.adap = i2cadap; \ + state->i2c_props.name = devname; \ + __tuner_info(state->i2c_props, \ + "creating new instance\n"); \ + list_add_tail(&state->hybrid_tuner_instance_list, &list);\ + state->i2c_props.count++; \ + __ret = state->i2c_props.count; \ + } \ +__fail: \ + __ret; \ +}) + +#define hybrid_tuner_release_state(state) \ +({ \ + int __ret; \ + state->i2c_props.count--; \ + __ret = state->i2c_props.count; \ + if (!state->i2c_props.count) { \ + __tuner_info(state->i2c_props, "destroying instance\n");\ + list_del(&state->hybrid_tuner_instance_list); \ + kfree(state); \ + } \ + __ret; \ +}) + +#endif /* __TUNER_I2C_H__ */ diff --git a/linux/drivers/media/common/tuners/tuner-simple.c b/linux/drivers/media/common/tuners/tuner-simple.c new file mode 100644 index 000000000..29c14a4c6 --- /dev/null +++ b/linux/drivers/media/common/tuners/tuner-simple.c @@ -0,0 +1,1136 @@ +/* + * i2c tv tuner chip device driver + * controls all those simple 4-control-bytes style tuners. + * + * This "tuner-simple" module was split apart from the original "tuner" module. + */ +#include +#include +#include "compat.h" +#include +#include +#include +#include +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0) +#include "i2c-compat.h" +#endif +#include "tuner-i2c.h" +#include "tuner-simple.h" + +static int debug; +module_param(debug, int, 0644); +MODULE_PARM_DESC(debug, "enable verbose debug messages"); + +#define TUNER_SIMPLE_MAX 64 +static unsigned int simple_devcount; + +static int offset; +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0) +MODULE_PARM(offset, "i"); +#else +module_param(offset, int, 0664); +#endif +MODULE_PARM_DESC(offset, "Allows to specify an offset for tuner"); + +static unsigned int atv_input[TUNER_SIMPLE_MAX] = \ + { [0 ... (TUNER_SIMPLE_MAX-1)] = 0 }; +static unsigned int dtv_input[TUNER_SIMPLE_MAX] = \ + { [0 ... (TUNER_SIMPLE_MAX-1)] = 0 }; +module_param_array(atv_input, int, NULL, 0644); +module_param_array(dtv_input, int, NULL, 0644); +MODULE_PARM_DESC(atv_input, "specify atv rf input, 0 for autoselect"); +MODULE_PARM_DESC(dtv_input, "specify dtv rf input, 0 for autoselect"); + +/* ---------------------------------------------------------------------- */ + +/* tv standard selection for Temic 4046 FM5 + this value takes the low bits of control byte 2 + from datasheet Rev.01, Feb.00 + standard BG I L L2 D + picture IF 38.9 38.9 38.9 33.95 38.9 + sound 1 33.4 32.9 32.4 40.45 32.4 + sound 2 33.16 + NICAM 33.05 32.348 33.05 33.05 + */ +#define TEMIC_SET_PAL_I 0x05 +#define TEMIC_SET_PAL_DK 0x09 +#define TEMIC_SET_PAL_L 0x0a /* SECAM ? */ +#define TEMIC_SET_PAL_L2 0x0b /* change IF ! */ +#define TEMIC_SET_PAL_BG 0x0c + +/* tv tuner system standard selection for Philips FQ1216ME + this value takes the low bits of control byte 2 + from datasheet "1999 Nov 16" (supersedes "1999 Mar 23") + standard BG DK I L L` + picture carrier 38.90 38.90 38.90 38.90 33.95 + colour 34.47 34.47 34.47 34.47 38.38 + sound 1 33.40 32.40 32.90 32.40 40.45 + sound 2 33.16 - - - - + NICAM 33.05 33.05 32.35 33.05 39.80 + */ +#define PHILIPS_SET_PAL_I 0x01 /* Bit 2 always zero !*/ +#define PHILIPS_SET_PAL_BGDK 0x09 +#define PHILIPS_SET_PAL_L2 0x0a +#define PHILIPS_SET_PAL_L 0x0b + +/* system switching for Philips FI1216MF MK2 + from datasheet "1996 Jul 09", + standard BG L L' + picture carrier 38.90 38.90 33.95 + colour 34.47 34.37 38.38 + sound 1 33.40 32.40 40.45 + sound 2 33.16 - - + NICAM 33.05 33.05 39.80 + */ +#define PHILIPS_MF_SET_STD_BG 0x01 /* Bit 2 must be zero, Bit 3 is system output */ +#define PHILIPS_MF_SET_STD_L 0x03 /* Used on Secam France */ +#define PHILIPS_MF_SET_STD_LC 0x02 /* Used on SECAM L' */ + +/* Control byte */ + +#define TUNER_RATIO_MASK 0x06 /* Bit cb1:cb2 */ +#define TUNER_RATIO_SELECT_50 0x00 +#define TUNER_RATIO_SELECT_32 0x02 +#define TUNER_RATIO_SELECT_166 0x04 +#define TUNER_RATIO_SELECT_62 0x06 + +#define TUNER_CHARGE_PUMP 0x40 /* Bit cb6 */ + +/* Status byte */ + +#define TUNER_POR 0x80 +#define TUNER_FL 0x40 +#define TUNER_MODE 0x38 +#define TUNER_AFC 0x07 +#define TUNER_SIGNAL 0x07 +#define TUNER_STEREO 0x10 + +#define TUNER_PLL_LOCKED 0x40 +#define TUNER_STEREO_MK3 0x04 + +static DEFINE_MUTEX(tuner_simple_list_mutex); +static LIST_HEAD(hybrid_tuner_instance_list); + +struct tuner_simple_priv { + unsigned int nr; + u16 last_div; + + struct tuner_i2c_props i2c_props; + struct list_head hybrid_tuner_instance_list; + + unsigned int type; + struct tunertype *tun; + + u32 frequency; + u32 bandwidth; +}; + +/* ---------------------------------------------------------------------- */ + +static int tuner_read_status(struct dvb_frontend *fe) +{ + struct tuner_simple_priv *priv = fe->tuner_priv; + unsigned char byte; + + if (1 != tuner_i2c_xfer_recv(&priv->i2c_props, &byte, 1)) + return 0; + + return byte; +} + +static inline int tuner_signal(const int status) +{ + return (status & TUNER_SIGNAL) << 13; +} + +static inline int tuner_stereo(const int type, const int status) +{ + switch (type) { + case TUNER_PHILIPS_FM1216ME_MK3: + case TUNER_PHILIPS_FM1236_MK3: + case TUNER_PHILIPS_FM1256_IH3: + case TUNER_LG_NTSC_TAPE: + return ((status & TUNER_SIGNAL) == TUNER_STEREO_MK3); + default: + return status & TUNER_STEREO; + } +} + +static inline int tuner_islocked(const int status) +{ + return (status & TUNER_FL); +} + +static inline int tuner_afcstatus(const int status) +{ + return (status & TUNER_AFC) - 2; +} + +#if 0 /* unused */ +static inline int tuner_mode(const int status) +{ + return (status & TUNER_MODE) >> 3; +} +#endif + +static int simple_get_status(struct dvb_frontend *fe, u32 *status) +{ + struct tuner_simple_priv *priv = fe->tuner_priv; + int tuner_status; + + if (priv->i2c_props.adap == NULL) + return -EINVAL; + + tuner_status = tuner_read_status(fe); + + *status = 0; + + if (tuner_islocked(tuner_status)) + *status = TUNER_STATUS_LOCKED; + if (tuner_stereo(priv->type, tuner_status)) + *status |= TUNER_STATUS_STEREO; + + tuner_dbg("AFC Status: %d\n", tuner_afcstatus(tuner_status)); + + return 0; +} + +static int simple_get_rf_strength(struct dvb_frontend *fe, u16 *strength) +{ + struct tuner_simple_priv *priv = fe->tuner_priv; + int signal; + + if (priv->i2c_props.adap == NULL) + return -EINVAL; + + signal = tuner_signal(tuner_read_status(fe)); + + *strength = signal; + + tuner_dbg("Signal strength: %d\n", signal); + + return 0; +} + +/* ---------------------------------------------------------------------- */ + +static inline char *tuner_param_name(enum param_type type) +{ + char *name; + + switch (type) { + case TUNER_PARAM_TYPE_RADIO: + name = "radio"; + break; + case TUNER_PARAM_TYPE_PAL: + name = "pal"; + break; + case TUNER_PARAM_TYPE_SECAM: + name = "secam"; + break; + case TUNER_PARAM_TYPE_NTSC: + name = "ntsc"; + break; + case TUNER_PARAM_TYPE_DIGITAL: + name = "digital"; + break; + default: + name = "unknown"; + break; + } + return name; +} + +static struct tuner_params *simple_tuner_params(struct dvb_frontend *fe, + enum param_type desired_type) +{ + struct tuner_simple_priv *priv = fe->tuner_priv; + struct tunertype *tun = priv->tun; + int i; + + for (i = 0; i < tun->count; i++) + if (desired_type == tun->params[i].type) + break; + + /* use default tuner params if desired_type not available */ + if (i == tun->count) { + tuner_dbg("desired params (%s) undefined for tuner %d\n", + tuner_param_name(desired_type), priv->type); + i = 0; + } + + tuner_dbg("using tuner params #%d (%s)\n", i, + tuner_param_name(tun->params[i].type)); + + return &tun->params[i]; +} + +static int simple_config_lookup(struct dvb_frontend *fe, + struct tuner_params *t_params, + int *frequency, u8 *config, u8 *cb) +{ + struct tuner_simple_priv *priv = fe->tuner_priv; + int i; + + for (i = 0; i < t_params->count; i++) { + if (*frequency > t_params->ranges[i].limit) + continue; + break; + } + if (i == t_params->count) { + tuner_dbg("frequency out of range (%d > %d)\n", + *frequency, t_params->ranges[i - 1].limit); + *frequency = t_params->ranges[--i].limit; + } + *config = t_params->ranges[i].config; + *cb = t_params->ranges[i].cb; + + tuner_dbg("freq = %d.%02d (%d), range = %d, " + "config = 0x%02x, cb = 0x%02x\n", + *frequency / 16, *frequency % 16 * 100 / 16, *frequency, + i, *config, *cb); + + return i; +} + +/* ---------------------------------------------------------------------- */ + +static void simple_set_rf_input(struct dvb_frontend *fe, + u8 *config, u8 *cb, unsigned int rf) +{ + struct tuner_simple_priv *priv = fe->tuner_priv; + + switch (priv->type) { + case TUNER_PHILIPS_TUV1236D: + switch (rf) { + case 1: + *cb |= 0x08; + break; + default: + *cb &= ~0x08; + break; + } + break; + case TUNER_PHILIPS_FCV1236D: + switch (rf) { + case 1: + *cb |= 0x01; + break; + default: + *cb &= ~0x01; + break; + } + break; + default: + break; + } +} + +static int simple_std_setup(struct dvb_frontend *fe, + struct analog_parameters *params, + u8 *config, u8 *cb) +{ + struct tuner_simple_priv *priv = fe->tuner_priv; + u8 tuneraddr; + int rc; + + /* tv norm specific stuff for multi-norm tuners */ + switch (priv->type) { + case TUNER_PHILIPS_SECAM: /* FI1216MF */ + /* 0x01 -> ??? no change ??? */ + /* 0x02 -> PAL BDGHI / SECAM L */ + /* 0x04 -> ??? PAL others / SECAM others ??? */ + *cb &= ~0x03; + if (params->std & V4L2_STD_SECAM_L) + /* also valid for V4L2_STD_SECAM */ + *cb |= PHILIPS_MF_SET_STD_L; + else if (params->std & V4L2_STD_SECAM_LC) + *cb |= PHILIPS_MF_SET_STD_LC; + else /* V4L2_STD_B|V4L2_STD_GH */ + *cb |= PHILIPS_MF_SET_STD_BG; + break; + + case TUNER_TEMIC_4046FM5: + *cb &= ~0x0f; + + if (params->std & V4L2_STD_PAL_BG) { + *cb |= TEMIC_SET_PAL_BG; + + } else if (params->std & V4L2_STD_PAL_I) { + *cb |= TEMIC_SET_PAL_I; + + } else if (params->std & V4L2_STD_PAL_DK) { + *cb |= TEMIC_SET_PAL_DK; + + } else if (params->std & V4L2_STD_SECAM_L) { + *cb |= TEMIC_SET_PAL_L; + + } + break; + + case TUNER_PHILIPS_FQ1216ME: + *cb &= ~0x0f; + + if (params->std & (V4L2_STD_PAL_BG|V4L2_STD_PAL_DK)) { + *cb |= PHILIPS_SET_PAL_BGDK; + + } else if (params->std & V4L2_STD_PAL_I) { + *cb |= PHILIPS_SET_PAL_I; + + } else if (params->std & V4L2_STD_SECAM_L) { + *cb |= PHILIPS_SET_PAL_L; + + } + break; + + case TUNER_PHILIPS_FCV1236D: + /* 0x00 -> ATSC antenna input 1 */ + /* 0x01 -> ATSC antenna input 2 */ + /* 0x02 -> NTSC antenna input 1 */ + /* 0x03 -> NTSC antenna input 2 */ + *cb &= ~0x03; + if (!(params->std & V4L2_STD_ATSC)) + *cb |= 2; + break; + + case TUNER_MICROTUNE_4042FI5: + /* Set the charge pump for fast tuning */ + *config |= TUNER_CHARGE_PUMP; + break; + + case TUNER_PHILIPS_TUV1236D: + { + /* 0x40 -> ATSC antenna input 1 */ + /* 0x48 -> ATSC antenna input 2 */ + /* 0x00 -> NTSC antenna input 1 */ + /* 0x08 -> NTSC antenna input 2 */ + u8 buffer[4] = { 0x14, 0x00, 0x17, 0x00}; + *cb &= ~0x40; + if (params->std & V4L2_STD_ATSC) { + *cb |= 0x40; + buffer[1] = 0x04; + } + /* set to the correct mode (analog or digital) */ + tuneraddr = priv->i2c_props.addr; + priv->i2c_props.addr = 0x0a; + rc = tuner_i2c_xfer_send(&priv->i2c_props, &buffer[0], 2); + if (2 != rc) + tuner_warn("i2c i/o error: rc == %d " + "(should be 2)\n", rc); + rc = tuner_i2c_xfer_send(&priv->i2c_props, &buffer[2], 2); + if (2 != rc) + tuner_warn("i2c i/o error: rc == %d " + "(should be 2)\n", rc); + priv->i2c_props.addr = tuneraddr; + break; + } + } + if (atv_input[priv->nr]) + simple_set_rf_input(fe, config, cb, atv_input[priv->nr]); + + return 0; +} + +static int simple_post_tune(struct dvb_frontend *fe, u8 *buffer, + u16 div, u8 config, u8 cb) +{ + struct tuner_simple_priv *priv = fe->tuner_priv; + int rc; + + switch (priv->type) { + case TUNER_LG_TDVS_H06XF: + /* Set the Auxiliary Byte. */ +#if 0 + buffer[2] &= ~0x20; + buffer[2] |= 0x18; + buffer[3] = 0x20; + tuner_dbg("tv 0x%02x 0x%02x 0x%02x 0x%02x\n", + buffer[0], buffer[1], buffer[2], buffer[3]); + + rc = tuner_i2c_xfer_send(&priv->i2c_props, buffer, 4); + if (4 != rc) + tuner_warn("i2c i/o error: rc == %d " + "(should be 4)\n", rc); +#else + buffer[0] = buffer[2]; + buffer[0] &= ~0x20; + buffer[0] |= 0x18; + buffer[1] = 0x20; + tuner_dbg("tv 0x%02x 0x%02x\n", buffer[0], buffer[1]); + + rc = tuner_i2c_xfer_send(&priv->i2c_props, buffer, 2); + if (2 != rc) + tuner_warn("i2c i/o error: rc == %d " + "(should be 2)\n", rc); +#endif + break; + case TUNER_MICROTUNE_4042FI5: + { + /* FIXME - this may also work for other tuners */ + unsigned long timeout = jiffies + msecs_to_jiffies(1); + u8 status_byte = 0; + + /* Wait until the PLL locks */ + for (;;) { + if (time_after(jiffies, timeout)) + return 0; + rc = tuner_i2c_xfer_recv(&priv->i2c_props, + &status_byte, 1); + if (1 != rc) { + tuner_warn("i2c i/o read error: rc == %d " + "(should be 1)\n", rc); + break; + } + if (status_byte & TUNER_PLL_LOCKED) + break; + udelay(10); + } + + /* Set the charge pump for optimized phase noise figure */ + config &= ~TUNER_CHARGE_PUMP; + buffer[0] = (div>>8) & 0x7f; + buffer[1] = div & 0xff; + buffer[2] = config; + buffer[3] = cb; + tuner_dbg("tv 0x%02x 0x%02x 0x%02x 0x%02x\n", + buffer[0], buffer[1], buffer[2], buffer[3]); + + rc = tuner_i2c_xfer_send(&priv->i2c_props, buffer, 4); + if (4 != rc) + tuner_warn("i2c i/o error: rc == %d " + "(should be 4)\n", rc); + break; + } + } + + return 0; +} + +static int simple_radio_bandswitch(struct dvb_frontend *fe, u8 *buffer) +{ + struct tuner_simple_priv *priv = fe->tuner_priv; + + switch (priv->type) { + case TUNER_TENA_9533_DI: + case TUNER_YMEC_TVF_5533MF: + tuner_dbg("This tuner doesn't have FM. " + "Most cards have a TEA5767 for FM\n"); + return 0; + case TUNER_PHILIPS_FM1216ME_MK3: + case TUNER_PHILIPS_FM1236_MK3: + case TUNER_PHILIPS_FMD1216ME_MK3: + case TUNER_LG_NTSC_TAPE: + case TUNER_PHILIPS_FM1256_IH3: + buffer[3] = 0x19; + break; + case TUNER_TNF_5335MF: + buffer[3] = 0x11; + break; + case TUNER_LG_PAL_FM: + buffer[3] = 0xa5; + break; + case TUNER_THOMSON_DTT761X: + buffer[3] = 0x39; + break; + case TUNER_MICROTUNE_4049FM5: + default: + buffer[3] = 0xa4; + break; + } + + return 0; +} + +/* ---------------------------------------------------------------------- */ + +static int simple_set_tv_freq(struct dvb_frontend *fe, + struct analog_parameters *params) +{ + struct tuner_simple_priv *priv = fe->tuner_priv; + u8 config, cb; + u16 div; + struct tunertype *tun; + u8 buffer[4]; + int rc, IFPCoff, i; + enum param_type desired_type; + struct tuner_params *t_params; + + tun = priv->tun; + + /* IFPCoff = Video Intermediate Frequency - Vif: + 940 =16*58.75 NTSC/J (Japan) + 732 =16*45.75 M/N STD + 704 =16*44 ATSC (at DVB code) + 632 =16*39.50 I U.K. + 622.4=16*38.90 B/G D/K I, L STD + 592 =16*37.00 D China + 590 =16.36.875 B Australia + 543.2=16*33.95 L' STD + 171.2=16*10.70 FM Radio (at set_radio_freq) + */ + + if (params->std == V4L2_STD_NTSC_M_JP) { + IFPCoff = 940; + desired_type = TUNER_PARAM_TYPE_NTSC; + } else if ((params->std & V4L2_STD_MN) && + !(params->std & ~V4L2_STD_MN)) { + IFPCoff = 732; + desired_type = TUNER_PARAM_TYPE_NTSC; + } else if (params->std == V4L2_STD_SECAM_LC) { + IFPCoff = 543; + desired_type = TUNER_PARAM_TYPE_SECAM; + } else { + IFPCoff = 623; + desired_type = TUNER_PARAM_TYPE_PAL; + } + + t_params = simple_tuner_params(fe, desired_type); + + i = simple_config_lookup(fe, t_params, ¶ms->frequency, + &config, &cb); + + div = params->frequency + IFPCoff + offset; + + tuner_dbg("Freq= %d.%02d MHz, V_IF=%d.%02d MHz, " + "Offset=%d.%02d MHz, div=%0d\n", + params->frequency / 16, params->frequency % 16 * 100 / 16, + IFPCoff / 16, IFPCoff % 16 * 100 / 16, + offset / 16, offset % 16 * 100 / 16, div); + + /* tv norm specific stuff for multi-norm tuners */ + simple_std_setup(fe, params, &config, &cb); + + if (t_params->cb_first_if_lower_freq && div < priv->last_div) { + buffer[0] = config; + buffer[1] = cb; + buffer[2] = (div>>8) & 0x7f; + buffer[3] = div & 0xff; + } else { + buffer[0] = (div>>8) & 0x7f; + buffer[1] = div & 0xff; + buffer[2] = config; + buffer[3] = cb; + } + priv->last_div = div; + if (t_params->has_tda9887) { + struct v4l2_priv_tun_config tda9887_cfg; + int config = 0; + int is_secam_l = (params->std & (V4L2_STD_SECAM_L | + V4L2_STD_SECAM_LC)) && + !(params->std & ~(V4L2_STD_SECAM_L | + V4L2_STD_SECAM_LC)); + + tda9887_cfg.tuner = TUNER_TDA9887; + tda9887_cfg.priv = &config; + + if (params->std == V4L2_STD_SECAM_LC) { + if (t_params->port1_active ^ t_params->port1_invert_for_secam_lc) + config |= TDA9887_PORT1_ACTIVE; + if (t_params->port2_active ^ t_params->port2_invert_for_secam_lc) + config |= TDA9887_PORT2_ACTIVE; + } else { + if (t_params->port1_active) + config |= TDA9887_PORT1_ACTIVE; + if (t_params->port2_active) + config |= TDA9887_PORT2_ACTIVE; + } + if (t_params->intercarrier_mode) + config |= TDA9887_INTERCARRIER; + if (is_secam_l) { + if (i == 0 && t_params->default_top_secam_low) + config |= TDA9887_TOP(t_params->default_top_secam_low); + else if (i == 1 && t_params->default_top_secam_mid) + config |= TDA9887_TOP(t_params->default_top_secam_mid); + else if (t_params->default_top_secam_high) + config |= TDA9887_TOP(t_params->default_top_secam_high); + } else { + if (i == 0 && t_params->default_top_low) + config |= TDA9887_TOP(t_params->default_top_low); + else if (i == 1 && t_params->default_top_mid) + config |= TDA9887_TOP(t_params->default_top_mid); + else if (t_params->default_top_high) + config |= TDA9887_TOP(t_params->default_top_high); + } + if (t_params->default_pll_gating_18) + config |= TDA9887_GATING_18; + i2c_clients_command(priv->i2c_props.adap, TUNER_SET_CONFIG, + &tda9887_cfg); + } + tuner_dbg("tv 0x%02x 0x%02x 0x%02x 0x%02x\n", + buffer[0], buffer[1], buffer[2], buffer[3]); + + rc = tuner_i2c_xfer_send(&priv->i2c_props, buffer, 4); + if (4 != rc) + tuner_warn("i2c i/o error: rc == %d (should be 4)\n", rc); + + simple_post_tune(fe, &buffer[0], div, config, cb); + + return 0; +} + +static int simple_set_radio_freq(struct dvb_frontend *fe, + struct analog_parameters *params) +{ + struct tunertype *tun; + struct tuner_simple_priv *priv = fe->tuner_priv; + u8 buffer[4]; + u16 div; + int rc, j; + struct tuner_params *t_params; + unsigned int freq = params->frequency; + + tun = priv->tun; + + for (j = tun->count-1; j > 0; j--) + if (tun->params[j].type == TUNER_PARAM_TYPE_RADIO) + break; + /* default t_params (j=0) will be used if desired type wasn't found */ + t_params = &tun->params[j]; + + /* Select Radio 1st IF used */ + switch (t_params->radio_if) { + case 0: /* 10.7 MHz */ + freq += (unsigned int)(10.7*16000); + break; + case 1: /* 33.3 MHz */ + freq += (unsigned int)(33.3*16000); + break; + case 2: /* 41.3 MHz */ + freq += (unsigned int)(41.3*16000); + break; + default: + tuner_warn("Unsupported radio_if value %d\n", + t_params->radio_if); + return 0; + } + + /* Bandswitch byte */ + simple_radio_bandswitch(fe, &buffer[0]); + + buffer[2] = (t_params->ranges[0].config & ~TUNER_RATIO_MASK) | + TUNER_RATIO_SELECT_50; /* 50 kHz step */ + + /* Convert from 1/16 kHz V4L steps to 1/20 MHz (=50 kHz) PLL steps + freq * (1 Mhz / 16000 V4L steps) * (20 PLL steps / 1 MHz) = + freq * (1/800) */ + div = (freq + 400) / 800; + + if (t_params->cb_first_if_lower_freq && div < priv->last_div) { + buffer[0] = buffer[2]; + buffer[1] = buffer[3]; + buffer[2] = (div>>8) & 0x7f; + buffer[3] = div & 0xff; + } else { + buffer[0] = (div>>8) & 0x7f; + buffer[1] = div & 0xff; + } + + tuner_dbg("radio 0x%02x 0x%02x 0x%02x 0x%02x\n", + buffer[0], buffer[1], buffer[2], buffer[3]); + priv->last_div = div; + + if (t_params->has_tda9887) { + int config = 0; + struct v4l2_priv_tun_config tda9887_cfg; + + tda9887_cfg.tuner = TUNER_TDA9887; + tda9887_cfg.priv = &config; + + if (t_params->port1_active && + !t_params->port1_fm_high_sensitivity) + config |= TDA9887_PORT1_ACTIVE; + if (t_params->port2_active && + !t_params->port2_fm_high_sensitivity) + config |= TDA9887_PORT2_ACTIVE; + if (t_params->intercarrier_mode) + config |= TDA9887_INTERCARRIER; +/* if (t_params->port1_set_for_fm_mono) + config &= ~TDA9887_PORT1_ACTIVE;*/ + if (t_params->fm_gain_normal) + config |= TDA9887_GAIN_NORMAL; + if (t_params->radio_if == 2) + config |= TDA9887_RIF_41_3; + i2c_clients_command(priv->i2c_props.adap, TUNER_SET_CONFIG, + &tda9887_cfg); + } + rc = tuner_i2c_xfer_send(&priv->i2c_props, buffer, 4); + if (4 != rc) + tuner_warn("i2c i/o error: rc == %d (should be 4)\n", rc); + + return 0; +} + +static int simple_set_params(struct dvb_frontend *fe, + struct analog_parameters *params) +{ + struct tuner_simple_priv *priv = fe->tuner_priv; + int ret = -EINVAL; + + if (priv->i2c_props.adap == NULL) + return -EINVAL; + + switch (params->mode) { + case V4L2_TUNER_RADIO: + ret = simple_set_radio_freq(fe, params); + priv->frequency = params->frequency * 125 / 2; + break; + case V4L2_TUNER_ANALOG_TV: + case V4L2_TUNER_DIGITAL_TV: + ret = simple_set_tv_freq(fe, params); + priv->frequency = params->frequency * 62500; + break; + } + priv->bandwidth = 0; + + return ret; +} + +static void simple_set_dvb(struct dvb_frontend *fe, u8 *buf, + const struct dvb_frontend_parameters *params) +{ + struct tuner_simple_priv *priv = fe->tuner_priv; + + switch (priv->type) { + case TUNER_PHILIPS_FMD1216ME_MK3: + if (params->u.ofdm.bandwidth == BANDWIDTH_8_MHZ && + params->frequency >= 158870000) + buf[3] |= 0x08; + break; + case TUNER_PHILIPS_TD1316: + /* determine band */ + buf[3] |= (params->frequency < 161000000) ? 1 : + (params->frequency < 444000000) ? 2 : 4; + + /* setup PLL filter */ + if (params->u.ofdm.bandwidth == BANDWIDTH_8_MHZ) + buf[3] |= 1 << 3; + break; + case TUNER_PHILIPS_TUV1236D: + case TUNER_PHILIPS_FCV1236D: + { + unsigned int new_rf; + + if (dtv_input[priv->nr]) + new_rf = dtv_input[priv->nr]; + else + switch (params->u.vsb.modulation) { + case QAM_64: + case QAM_256: + new_rf = 1; + break; + case VSB_8: + default: + new_rf = 0; + break; + } + simple_set_rf_input(fe, &buf[2], &buf[3], new_rf); + break; + } + default: + break; + } +} + +static u32 simple_dvb_configure(struct dvb_frontend *fe, u8 *buf, + const struct dvb_frontend_parameters *params) +{ + /* This function returns the tuned frequency on success, 0 on error */ + struct tuner_simple_priv *priv = fe->tuner_priv; + struct tunertype *tun = priv->tun; + static struct tuner_params *t_params; + u8 config, cb; + u32 div; + int ret, frequency = params->frequency / 62500; + + t_params = simple_tuner_params(fe, TUNER_PARAM_TYPE_DIGITAL); + ret = simple_config_lookup(fe, t_params, &frequency, &config, &cb); + if (ret < 0) + return 0; /* failure */ + + div = ((frequency + t_params->iffreq) * 62500 + offset + + tun->stepsize/2) / tun->stepsize; + + buf[0] = div >> 8; + buf[1] = div & 0xff; + buf[2] = config; + buf[3] = cb; + + simple_set_dvb(fe, buf, params); + + tuner_dbg("%s: div=%d | buf=0x%02x,0x%02x,0x%02x,0x%02x\n", + tun->name, div, buf[0], buf[1], buf[2], buf[3]); + + /* calculate the frequency we set it to */ + return (div * tun->stepsize) - t_params->iffreq; +} + +static int simple_dvb_calc_regs(struct dvb_frontend *fe, + struct dvb_frontend_parameters *params, + u8 *buf, int buf_len) +{ + struct tuner_simple_priv *priv = fe->tuner_priv; + u32 frequency; + + if (buf_len < 5) + return -EINVAL; + + frequency = simple_dvb_configure(fe, buf+1, params); + if (frequency == 0) + return -EINVAL; + + buf[0] = priv->i2c_props.addr; + + priv->frequency = frequency; + priv->bandwidth = (fe->ops.info.type == FE_OFDM) ? + params->u.ofdm.bandwidth : 0; + + return 5; +} + +static int simple_dvb_set_params(struct dvb_frontend *fe, + struct dvb_frontend_parameters *params) +{ + struct tuner_simple_priv *priv = fe->tuner_priv; + u32 prev_freq, prev_bw; + int ret; + u8 buf[5]; + + if (priv->i2c_props.adap == NULL) + return -EINVAL; + + prev_freq = priv->frequency; + prev_bw = priv->bandwidth; + + ret = simple_dvb_calc_regs(fe, params, buf, 5); + if (ret != 5) + goto fail; + + /* put analog demod in standby when tuning digital */ + if (fe->ops.analog_ops.standby) + fe->ops.analog_ops.standby(fe); + + if (fe->ops.i2c_gate_ctrl) + fe->ops.i2c_gate_ctrl(fe, 1); + + /* buf[0] contains the i2c address, but * + * we already have it in i2c_props.addr */ + ret = tuner_i2c_xfer_send(&priv->i2c_props, buf+1, 4); + if (ret != 4) + goto fail; + + return 0; +fail: + /* calc_regs sets frequency and bandwidth. if we failed, unset them */ + priv->frequency = prev_freq; + priv->bandwidth = prev_bw; + + return ret; +} + +static int simple_init(struct dvb_frontend *fe) +{ + struct tuner_simple_priv *priv = fe->tuner_priv; + + if (priv->i2c_props.adap == NULL) + return -EINVAL; + + if (priv->tun->initdata) { + int ret; + + if (fe->ops.i2c_gate_ctrl) + fe->ops.i2c_gate_ctrl(fe, 1); + + ret = tuner_i2c_xfer_send(&priv->i2c_props, + priv->tun->initdata + 1, + priv->tun->initdata[0]); + if (ret != priv->tun->initdata[0]) + return ret; + } + + return 0; +} + +static int simple_sleep(struct dvb_frontend *fe) +{ + struct tuner_simple_priv *priv = fe->tuner_priv; + + if (priv->i2c_props.adap == NULL) + return -EINVAL; + + if (priv->tun->sleepdata) { + int ret; + + if (fe->ops.i2c_gate_ctrl) + fe->ops.i2c_gate_ctrl(fe, 1); + + ret = tuner_i2c_xfer_send(&priv->i2c_props, + priv->tun->sleepdata + 1, + priv->tun->sleepdata[0]); + if (ret != priv->tun->sleepdata[0]) + return ret; + } + + return 0; +} + +static int simple_release(struct dvb_frontend *fe) +{ + struct tuner_simple_priv *priv = fe->tuner_priv; + + mutex_lock(&tuner_simple_list_mutex); + + if (priv) + hybrid_tuner_release_state(priv); + + mutex_unlock(&tuner_simple_list_mutex); + + fe->tuner_priv = NULL; + + return 0; +} + +static int simple_get_frequency(struct dvb_frontend *fe, u32 *frequency) +{ + struct tuner_simple_priv *priv = fe->tuner_priv; + *frequency = priv->frequency; + return 0; +} + +static int simple_get_bandwidth(struct dvb_frontend *fe, u32 *bandwidth) +{ + struct tuner_simple_priv *priv = fe->tuner_priv; + *bandwidth = priv->bandwidth; + return 0; +} + +static struct dvb_tuner_ops simple_tuner_ops = { +#if 0 + .info = { + .name = "tuner-simple", + .frequency_min = , + .frequency_max = , + .frequency_step = , + }, +#endif + .init = simple_init, + .sleep = simple_sleep, + .set_analog_params = simple_set_params, + .set_params = simple_dvb_set_params, + .calc_regs = simple_dvb_calc_regs, + .release = simple_release, + .get_frequency = simple_get_frequency, + .get_bandwidth = simple_get_bandwidth, + .get_status = simple_get_status, + .get_rf_strength = simple_get_rf_strength, +}; + +struct dvb_frontend *simple_tuner_attach(struct dvb_frontend *fe, + struct i2c_adapter *i2c_adap, + u8 i2c_addr, + unsigned int type) +{ + struct tuner_simple_priv *priv = NULL; + int instance; + + if (type >= tuner_count) { + printk(KERN_WARNING "%s: invalid tuner type: %d (max: %d)\n", + __func__, type, tuner_count-1); + return NULL; + } + + /* If i2c_adap is set, check that the tuner is at the correct address. + * Otherwise, if i2c_adap is NULL, the tuner will be programmed directly + * by the digital demod via calc_regs. + */ + if (i2c_adap != NULL) { + u8 b[1]; + struct i2c_msg msg = { + .addr = i2c_addr, .flags = I2C_M_RD, + .buf = b, .len = 1, + }; + + if (fe->ops.i2c_gate_ctrl) + fe->ops.i2c_gate_ctrl(fe, 1); + + if (1 != i2c_transfer(i2c_adap, &msg, 1)) + tuner_warn("unable to probe %s, proceeding anyway.", + tuners[type].name); + + if (fe->ops.i2c_gate_ctrl) + fe->ops.i2c_gate_ctrl(fe, 0); + } + + mutex_lock(&tuner_simple_list_mutex); + + instance = hybrid_tuner_request_state(struct tuner_simple_priv, priv, + hybrid_tuner_instance_list, + i2c_adap, i2c_addr, + "tuner-simple"); + switch (instance) { + case 0: + mutex_unlock(&tuner_simple_list_mutex); + return NULL; + break; + case 1: + fe->tuner_priv = priv; + + priv->type = type; + priv->tun = &tuners[type]; + priv->nr = simple_devcount++; + break; + default: + fe->tuner_priv = priv; +#if 0 + /* caller didn't pass in a configuration last time + * use current configuration, instead */ + if (!priv->tun) { + priv->type = type; + priv->tun = &tuners[type]; + } +#endif + break; + } + + mutex_unlock(&tuner_simple_list_mutex); + + memcpy(&fe->ops.tuner_ops, &simple_tuner_ops, + sizeof(struct dvb_tuner_ops)); + + tuner_info("type set to %d (%s)\n", type, priv->tun->name); + + if ((debug) || ((atv_input[priv->nr] > 0) || + (dtv_input[priv->nr] > 0))) { + if (0 == atv_input[priv->nr]) + tuner_info("tuner %d atv rf input will be " + "autoselected\n", priv->nr); + else + tuner_info("tuner %d atv rf input will be " + "set to input %d (insmod option)\n", + priv->nr, atv_input[priv->nr]); + if (0 == dtv_input[priv->nr]) + tuner_info("tuner %d dtv rf input will be " + "autoselected\n", priv->nr); + else + tuner_info("tuner %d dtv rf input will be " + "set to input %d (insmod option)\n", + priv->nr, dtv_input[priv->nr]); + } + + strlcpy(fe->ops.tuner_ops.info.name, priv->tun->name, + sizeof(fe->ops.tuner_ops.info.name)); + + return fe; +} +EXPORT_SYMBOL_GPL(simple_tuner_attach); + +MODULE_DESCRIPTION("Simple 4-control-bytes style tuner driver"); +MODULE_AUTHOR("Ralph Metzler, Gerd Knorr, Gunther Mayer"); +MODULE_LICENSE("GPL"); + +/* + * Overrides for Emacs so that we follow Linus's tabbing style. + * --------------------------------------------------------------------------- + * Local variables: + * c-basic-offset: 8 + * End: + */ diff --git a/linux/drivers/media/common/tuners/tuner-simple.h b/linux/drivers/media/common/tuners/tuner-simple.h new file mode 100644 index 000000000..e46cf0121 --- /dev/null +++ b/linux/drivers/media/common/tuners/tuner-simple.h @@ -0,0 +1,39 @@ +/* + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. +*/ + +#ifndef __TUNER_SIMPLE_H__ +#define __TUNER_SIMPLE_H__ + +#include +#include "dvb_frontend.h" + +#if defined(CONFIG_TUNER_SIMPLE) || (defined(CONFIG_TUNER_SIMPLE_MODULE) && defined(MODULE)) +extern struct dvb_frontend *simple_tuner_attach(struct dvb_frontend *fe, + struct i2c_adapter *i2c_adap, + u8 i2c_addr, + unsigned int type); +#else +static inline struct dvb_frontend *simple_tuner_attach(struct dvb_frontend *fe, + struct i2c_adapter *i2c_adap, + u8 i2c_addr, + unsigned int type) +{ + printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__); + return NULL; +} +#endif + +#endif /* __TUNER_SIMPLE_H__ */ diff --git a/linux/drivers/media/common/tuners/tuner-types.c b/linux/drivers/media/common/tuners/tuner-types.c new file mode 100644 index 000000000..b3f0f62e0 --- /dev/null +++ b/linux/drivers/media/common/tuners/tuner-types.c @@ -0,0 +1,1653 @@ +/* + * + * i2c tv tuner chip device type database. + * + */ + +#include +#include +#include +#include "compat.h" + +/* ---------------------------------------------------------------------- */ + +/* + * The floats in the tuner struct are computed at compile time + * by gcc and cast back to integers. Thus we don't violate the + * "no float in kernel" rule. + * + * A tuner_range may be referenced by multiple tuner_params structs. + * There are many duplicates in here. Reusing tuner_range structs, + * rather than defining new ones for each tuner, will cut down on + * memory usage, and is preferred when possible. + * + * Each tuner_params array may contain one or more elements, one + * for each video standard. + * + * FIXME: tuner_params struct contains an element, tda988x. We must + * set this for all tuners that contain a tda988x chip, and then we + * can remove this setting from the various card structs. + * + * FIXME: Right now, all tuners are using the first tuner_params[] + * array element for analog mode. In the future, we will be merging + * similar tuner definitions together, such that each tuner definition + * will have a tuner_params struct for each available video standard. + * At that point, the tuner_params[] array element will be chosen + * based on the video standard in use. + */ + +/* The following was taken from dvb-pll.c: */ + +/* Set AGC TOP value to 103 dBuV: + * 0x80 = Control Byte + * 0x40 = 250 uA charge pump (irrelevant) + * 0x18 = Aux Byte to follow + * 0x06 = 64.5 kHz divider (irrelevant) + * 0x01 = Disable Vt (aka sleep) + * + * 0x00 = AGC Time constant 2s Iagc = 300 nA (vs 0x80 = 9 nA) + * 0x50 = AGC Take over point = 103 dBuV + */ +static u8 tua603x_agc103[] = { 2, 0x80|0x40|0x18|0x06|0x01, 0x00|0x50 }; + +/* 0x04 = 166.67 kHz divider + * + * 0x80 = AGC Time constant 50ms Iagc = 9 uA + * 0x20 = AGC Take over point = 112 dBuV + */ +static u8 tua603x_agc112[] = { 2, 0x80|0x40|0x18|0x04|0x01, 0x80|0x20 }; + +/* 0-9 */ +/* ------------ TUNER_TEMIC_PAL - TEMIC PAL ------------ */ + +static struct tuner_range tuner_temic_pal_ranges[] = { + { 16 * 140.25 /*MHz*/, 0x8e, 0x02, }, + { 16 * 463.25 /*MHz*/, 0x8e, 0x04, }, + { 16 * 999.99 , 0x8e, 0x01, }, +}; + +static struct tuner_params tuner_temic_pal_params[] = { + { + .type = TUNER_PARAM_TYPE_PAL, + .ranges = tuner_temic_pal_ranges, + .count = ARRAY_SIZE(tuner_temic_pal_ranges), + }, +}; + +/* ------------ TUNER_PHILIPS_PAL_I - Philips PAL_I ------------ */ + +static struct tuner_range tuner_philips_pal_i_ranges[] = { + { 16 * 140.25 /*MHz*/, 0x8e, 0xa0, }, + { 16 * 463.25 /*MHz*/, 0x8e, 0x90, }, + { 16 * 999.99 , 0x8e, 0x30, }, +}; + +static struct tuner_params tuner_philips_pal_i_params[] = { + { + .type = TUNER_PARAM_TYPE_PAL, + .ranges = tuner_philips_pal_i_ranges, + .count = ARRAY_SIZE(tuner_philips_pal_i_ranges), + }, +}; + +/* ------------ TUNER_PHILIPS_NTSC - Philips NTSC ------------ */ + +static struct tuner_range tuner_philips_ntsc_ranges[] = { + { 16 * 157.25 /*MHz*/, 0x8e, 0xa0, }, + { 16 * 451.25 /*MHz*/, 0x8e, 0x90, }, + { 16 * 999.99 , 0x8e, 0x30, }, +}; + +static struct tuner_params tuner_philips_ntsc_params[] = { + { + .type = TUNER_PARAM_TYPE_NTSC, + .ranges = tuner_philips_ntsc_ranges, + .count = ARRAY_SIZE(tuner_philips_ntsc_ranges), + .cb_first_if_lower_freq = 1, + }, +}; + +/* ------------ TUNER_PHILIPS_SECAM - Philips SECAM ------------ */ + +static struct tuner_range tuner_philips_secam_ranges[] = { + { 16 * 168.25 /*MHz*/, 0x8e, 0xa7, }, + { 16 * 447.25 /*MHz*/, 0x8e, 0x97, }, + { 16 * 999.99 , 0x8e, 0x37, }, +}; + +static struct tuner_params tuner_philips_secam_params[] = { + { + .type = TUNER_PARAM_TYPE_SECAM, + .ranges = tuner_philips_secam_ranges, + .count = ARRAY_SIZE(tuner_philips_secam_ranges), + .cb_first_if_lower_freq = 1, + }, +}; + +/* ------------ TUNER_PHILIPS_PAL - Philips PAL ------------ */ + +static struct tuner_range tuner_philips_pal_ranges[] = { + { 16 * 168.25 /*MHz*/, 0x8e, 0xa0, }, + { 16 * 447.25 /*MHz*/, 0x8e, 0x90, }, + { 16 * 999.99 , 0x8e, 0x30, }, +}; + +static struct tuner_params tuner_philips_pal_params[] = { + { + .type = TUNER_PARAM_TYPE_PAL, + .ranges = tuner_philips_pal_ranges, + .count = ARRAY_SIZE(tuner_philips_pal_ranges), + .cb_first_if_lower_freq = 1, + }, +}; + +/* ------------ TUNER_TEMIC_NTSC - TEMIC NTSC ------------ */ + +static struct tuner_range tuner_temic_ntsc_ranges[] = { + { 16 * 157.25 /*MHz*/, 0x8e, 0x02, }, + { 16 * 463.25 /*MHz*/, 0x8e, 0x04, }, + { 16 * 999.99 , 0x8e, 0x01, }, +}; + +static struct tuner_params tuner_temic_ntsc_params[] = { + { + .type = TUNER_PARAM_TYPE_NTSC, + .ranges = tuner_temic_ntsc_ranges, + .count = ARRAY_SIZE(tuner_temic_ntsc_ranges), + }, +}; + +/* ------------ TUNER_TEMIC_PAL_I - TEMIC PAL_I ------------ */ + +static struct tuner_range tuner_temic_pal_i_ranges[] = { + { 16 * 170.00 /*MHz*/, 0x8e, 0x02, }, + { 16 * 450.00 /*MHz*/, 0x8e, 0x04, }, + { 16 * 999.99 , 0x8e, 0x01, }, +}; + +static struct tuner_params tuner_temic_pal_i_params[] = { + { + .type = TUNER_PARAM_TYPE_PAL, + .ranges = tuner_temic_pal_i_ranges, + .count = ARRAY_SIZE(tuner_temic_pal_i_ranges), + }, +}; + +/* ------------ TUNER_TEMIC_4036FY5_NTSC - TEMIC NTSC ------------ */ + +static struct tuner_range tuner_temic_4036fy5_ntsc_ranges[] = { + { 16 * 157.25 /*MHz*/, 0x8e, 0xa0, }, + { 16 * 463.25 /*MHz*/, 0x8e, 0x90, }, + { 16 * 999.99 , 0x8e, 0x30, }, +}; + +static struct tuner_params tuner_temic_4036fy5_ntsc_params[] = { + { + .type = TUNER_PARAM_TYPE_NTSC, + .ranges = tuner_temic_4036fy5_ntsc_ranges, + .count = ARRAY_SIZE(tuner_temic_4036fy5_ntsc_ranges), + }, +}; + +/* ------------ TUNER_ALPS_TSBH1_NTSC - TEMIC NTSC ------------ */ + +static struct tuner_range tuner_alps_tsb_1_ranges[] = { + { 16 * 137.25 /*MHz*/, 0x8e, 0x01, }, + { 16 * 385.25 /*MHz*/, 0x8e, 0x02, }, + { 16 * 999.99 , 0x8e, 0x08, }, +}; + +static struct tuner_params tuner_alps_tsbh1_ntsc_params[] = { + { + .type = TUNER_PARAM_TYPE_NTSC, + .ranges = tuner_alps_tsb_1_ranges, + .count = ARRAY_SIZE(tuner_alps_tsb_1_ranges), + }, +}; + +/* 10-19 */ +/* ------------ TUNER_ALPS_TSBE1_PAL - TEMIC PAL ------------ */ + +static struct tuner_params tuner_alps_tsb_1_params[] = { + { + .type = TUNER_PARAM_TYPE_PAL, + .ranges = tuner_alps_tsb_1_ranges, + .count = ARRAY_SIZE(tuner_alps_tsb_1_ranges), + }, +}; + +/* ------------ TUNER_ALPS_TSBB5_PAL_I - Alps PAL_I ------------ */ + +static struct tuner_range tuner_alps_tsb_5_pal_ranges[] = { + { 16 * 133.25 /*MHz*/, 0x8e, 0x01, }, + { 16 * 351.25 /*MHz*/, 0x8e, 0x02, }, + { 16 * 999.99 , 0x8e, 0x08, }, +}; + +static struct tuner_params tuner_alps_tsbb5_params[] = { + { + .type = TUNER_PARAM_TYPE_PAL, + .ranges = tuner_alps_tsb_5_pal_ranges, + .count = ARRAY_SIZE(tuner_alps_tsb_5_pal_ranges), + }, +}; + +/* ------------ TUNER_ALPS_TSBE5_PAL - Alps PAL ------------ */ + +static struct tuner_params tuner_alps_tsbe5_params[] = { + { + .type = TUNER_PARAM_TYPE_PAL, + .ranges = tuner_alps_tsb_5_pal_ranges, + .count = ARRAY_SIZE(tuner_alps_tsb_5_pal_ranges), + }, +}; + +/* ------------ TUNER_ALPS_TSBC5_PAL - Alps PAL ------------ */ + +static struct tuner_params tuner_alps_tsbc5_params[] = { + { + .type = TUNER_PARAM_TYPE_PAL, + .ranges = tuner_alps_tsb_5_pal_ranges, + .count = ARRAY_SIZE(tuner_alps_tsb_5_pal_ranges), + }, +}; + +/* ------------ TUNER_TEMIC_4006FH5_PAL - TEMIC PAL ------------ */ + +static struct tuner_range tuner_lg_pal_ranges[] = { + { 16 * 170.00 /*MHz*/, 0x8e, 0xa0, }, + { 16 * 450.00 /*MHz*/, 0x8e, 0x90, }, + { 16 * 999.99 , 0x8e, 0x30, }, +}; + +static struct tuner_params tuner_temic_4006fh5_params[] = { + { + .type = TUNER_PARAM_TYPE_PAL, + .ranges = tuner_lg_pal_ranges, + .count = ARRAY_SIZE(tuner_lg_pal_ranges), + }, +}; + +/* ------------ TUNER_ALPS_TSHC6_NTSC - Alps NTSC ------------ */ + +static struct tuner_range tuner_alps_tshc6_ntsc_ranges[] = { + { 16 * 137.25 /*MHz*/, 0x8e, 0x14, }, + { 16 * 385.25 /*MHz*/, 0x8e, 0x12, }, + { 16 * 999.99 , 0x8e, 0x11, }, +}; + +static struct tuner_params tuner_alps_tshc6_params[] = { + { + .type = TUNER_PARAM_TYPE_NTSC, + .ranges = tuner_alps_tshc6_ntsc_ranges, + .count = ARRAY_SIZE(tuner_alps_tshc6_ntsc_ranges), + }, +}; + +/* ------------ TUNER_TEMIC_PAL_DK - TEMIC PAL ------------ */ + +static struct tuner_range tuner_temic_pal_dk_ranges[] = { + { 16 * 168.25 /*MHz*/, 0x8e, 0xa0, }, + { 16 * 456.25 /*MHz*/, 0x8e, 0x90, }, + { 16 * 999.99 , 0x8e, 0x30, }, +}; + +static struct tuner_params tuner_temic_pal_dk_params[] = { + { + .type = TUNER_PARAM_TYPE_PAL, + .ranges = tuner_temic_pal_dk_ranges, + .count = ARRAY_SIZE(tuner_temic_pal_dk_ranges), + }, +}; + +/* ------------ TUNER_PHILIPS_NTSC_M - Philips NTSC ------------ */ + +static struct tuner_range tuner_philips_ntsc_m_ranges[] = { + { 16 * 160.00 /*MHz*/, 0x8e, 0xa0, }, + { 16 * 454.00 /*MHz*/, 0x8e, 0x90, }, + { 16 * 999.99 , 0x8e, 0x30, }, +}; + +static struct tuner_params tuner_philips_ntsc_m_params[] = { + { + .type = TUNER_PARAM_TYPE_NTSC, + .ranges = tuner_philips_ntsc_m_ranges, + .count = ARRAY_SIZE(tuner_philips_ntsc_m_ranges), + }, +}; + +/* ------------ TUNER_TEMIC_4066FY5_PAL_I - TEMIC PAL_I ------------ */ + +static struct tuner_range tuner_temic_40x6f_5_pal_ranges[] = { + { 16 * 169.00 /*MHz*/, 0x8e, 0xa0, }, + { 16 * 454.00 /*MHz*/, 0x8e, 0x90, }, + { 16 * 999.99 , 0x8e, 0x30, }, +}; + +static struct tuner_params tuner_temic_4066fy5_pal_i_params[] = { + { + .type = TUNER_PARAM_TYPE_PAL, + .ranges = tuner_temic_40x6f_5_pal_ranges, + .count = ARRAY_SIZE(tuner_temic_40x6f_5_pal_ranges), + }, +}; + +/* ------------ TUNER_TEMIC_4006FN5_MULTI_PAL - TEMIC PAL ------------ */ + +static struct tuner_params tuner_temic_4006fn5_multi_params[] = { + { + .type = TUNER_PARAM_TYPE_PAL, + .ranges = tuner_temic_40x6f_5_pal_ranges, + .count = ARRAY_SIZE(tuner_temic_40x6f_5_pal_ranges), + }, +}; + +/* 20-29 */ +/* ------------ TUNER_TEMIC_4009FR5_PAL - TEMIC PAL ------------ */ + +static struct tuner_range tuner_temic_4009f_5_pal_ranges[] = { + { 16 * 141.00 /*MHz*/, 0x8e, 0xa0, }, + { 16 * 464.00 /*MHz*/, 0x8e, 0x90, }, + { 16 * 999.99 , 0x8e, 0x30, }, +}; + +static struct tuner_params tuner_temic_4009f_5_params[] = { + { + .type = TUNER_PARAM_TYPE_PAL, + .ranges = tuner_temic_4009f_5_pal_ranges, + .count = ARRAY_SIZE(tuner_temic_4009f_5_pal_ranges), + }, +}; + +/* ------------ TUNER_TEMIC_4039FR5_NTSC - TEMIC NTSC ------------ */ + +static struct tuner_range tuner_temic_4x3x_f_5_ntsc_ranges[] = { + { 16 * 158.00 /*MHz*/, 0x8e, 0xa0, }, + { 16 * 453.00 /*MHz*/, 0x8e, 0x90, }, + { 16 * 999.99 , 0x8e, 0x30, }, +}; + +static struct tuner_params tuner_temic_4039fr5_params[] = { + { + .type = TUNER_PARAM_TYPE_NTSC, + .ranges = tuner_temic_4x3x_f_5_ntsc_ranges, + .count = ARRAY_SIZE(tuner_temic_4x3x_f_5_ntsc_ranges), + }, +}; + +/* ------------ TUNER_TEMIC_4046FM5 - TEMIC PAL ------------ */ + +static struct tuner_params tuner_temic_4046fm5_params[] = { + { + .type = TUNER_PARAM_TYPE_PAL, + .ranges = tuner_temic_40x6f_5_pal_ranges, + .count = ARRAY_SIZE(tuner_temic_40x6f_5_pal_ranges), + }, +}; + +/* ------------ TUNER_PHILIPS_PAL_DK - Philips PAL ------------ */ + +static struct tuner_params tuner_philips_pal_dk_params[] = { + { + .type = TUNER_PARAM_TYPE_PAL, + .ranges = tuner_lg_pal_ranges, + .count = ARRAY_SIZE(tuner_lg_pal_ranges), + }, +}; + +/* ------------ TUNER_PHILIPS_FQ1216ME - Philips PAL ------------ */ + +static struct tuner_params tuner_philips_fq1216me_params[] = { + { + .type = TUNER_PARAM_TYPE_PAL, + .ranges = tuner_lg_pal_ranges, + .count = ARRAY_SIZE(tuner_lg_pal_ranges), + .has_tda9887 = 1, + .port1_active = 1, + .port2_active = 1, + .port2_invert_for_secam_lc = 1, + }, +}; + +/* ------------ TUNER_LG_PAL_I_FM - LGINNOTEK PAL_I ------------ */ + +static struct tuner_params tuner_lg_pal_i_fm_params[] = { + { + .type = TUNER_PARAM_TYPE_PAL, + .ranges = tuner_lg_pal_ranges, + .count = ARRAY_SIZE(tuner_lg_pal_ranges), + }, +}; + +/* ------------ TUNER_LG_PAL_I - LGINNOTEK PAL_I ------------ */ + +static struct tuner_params tuner_lg_pal_i_params[] = { + { + .type = TUNER_PARAM_TYPE_PAL, + .ranges = tuner_lg_pal_ranges, + .count = ARRAY_SIZE(tuner_lg_pal_ranges), + }, +}; + +/* ------------ TUNER_LG_NTSC_FM - LGINNOTEK NTSC ------------ */ + +static struct tuner_range tuner_lg_ntsc_fm_ranges[] = { + { 16 * 210.00 /*MHz*/, 0x8e, 0xa0, }, + { 16 * 497.00 /*MHz*/, 0x8e, 0x90, }, + { 16 * 999.99 , 0x8e, 0x30, }, +}; + +static struct tuner_params tuner_lg_ntsc_fm_params[] = { + { + .type = TUNER_PARAM_TYPE_NTSC, + .ranges = tuner_lg_ntsc_fm_ranges, + .count = ARRAY_SIZE(tuner_lg_ntsc_fm_ranges), + }, +}; + +/* ------------ TUNER_LG_PAL_FM - LGINNOTEK PAL ------------ */ + +static struct tuner_params tuner_lg_pal_fm_params[] = { + { + .type = TUNER_PARAM_TYPE_PAL, + .ranges = tuner_lg_pal_ranges, + .count = ARRAY_SIZE(tuner_lg_pal_ranges), + }, +}; + +/* ------------ TUNER_LG_PAL - LGINNOTEK PAL ------------ */ + +static struct tuner_params tuner_lg_pal_params[] = { + { + .type = TUNER_PARAM_TYPE_PAL, + .ranges = tuner_lg_pal_ranges, + .count = ARRAY_SIZE(tuner_lg_pal_ranges), + }, +}; + +/* 30-39 */ +/* ------------ TUNER_TEMIC_4009FN5_MULTI_PAL_FM - TEMIC PAL ------------ */ + +static struct tuner_params tuner_temic_4009_fn5_multi_pal_fm_params[] = { + { + .type = TUNER_PARAM_TYPE_PAL, + .ranges = tuner_temic_4009f_5_pal_ranges, + .count = ARRAY_SIZE(tuner_temic_4009f_5_pal_ranges), + }, +}; + +/* ------------ TUNER_SHARP_2U5JF5540_NTSC - SHARP NTSC ------------ */ + +static struct tuner_range tuner_sharp_2u5jf5540_ntsc_ranges[] = { + { 16 * 137.25 /*MHz*/, 0x8e, 0x01, }, + { 16 * 317.25 /*MHz*/, 0x8e, 0x02, }, + { 16 * 999.99 , 0x8e, 0x08, }, +}; + +static struct tuner_params tuner_sharp_2u5jf5540_params[] = { + { + .type = TUNER_PARAM_TYPE_NTSC, + .ranges = tuner_sharp_2u5jf5540_ntsc_ranges, + .count = ARRAY_SIZE(tuner_sharp_2u5jf5540_ntsc_ranges), + }, +}; + +/* ------------ TUNER_Samsung_PAL_TCPM9091PD27 - Samsung PAL ------------ */ + +static struct tuner_range tuner_samsung_pal_tcpm9091pd27_ranges[] = { + { 16 * 169 /*MHz*/, 0x8e, 0xa0, }, + { 16 * 464 /*MHz*/, 0x8e, 0x90, }, + { 16 * 999.99 , 0x8e, 0x30, }, +}; + +static struct tuner_params tuner_samsung_pal_tcpm9091pd27_params[] = { + { + .type = TUNER_PARAM_TYPE_PAL, + .ranges = tuner_samsung_pal_tcpm9091pd27_ranges, + .count = ARRAY_SIZE(tuner_samsung_pal_tcpm9091pd27_ranges), + }, +}; + +/* ------------ TUNER_TEMIC_4106FH5 - TEMIC PAL ------------ */ + +static struct tuner_params tuner_temic_4106fh5_params[] = { + { + .type = TUNER_PARAM_TYPE_PAL, + .ranges = tuner_temic_4009f_5_pal_ranges, + .count = ARRAY_SIZE(tuner_temic_4009f_5_pal_ranges), + }, +}; + +/* ------------ TUNER_TEMIC_4012FY5 - TEMIC PAL ------------ */ + +static struct tuner_params tuner_temic_4012fy5_params[] = { + { + .type = TUNER_PARAM_TYPE_PAL, + .ranges = tuner_temic_pal_ranges, + .count = ARRAY_SIZE(tuner_temic_pal_ranges), + }, +}; + +/* ------------ TUNER_TEMIC_4136FY5 - TEMIC NTSC ------------ */ + +static struct tuner_params tuner_temic_4136_fy5_params[] = { + { + .type = TUNER_PARAM_TYPE_NTSC, + .ranges = tuner_temic_4x3x_f_5_ntsc_ranges, + .count = ARRAY_SIZE(tuner_temic_4x3x_f_5_ntsc_ranges), + }, +}; + +/* ------------ TUNER_LG_PAL_NEW_TAPC - LGINNOTEK PAL ------------ */ + +static struct tuner_range tuner_lg_new_tapc_ranges[] = { + { 16 * 170.00 /*MHz*/, 0x8e, 0x01, }, + { 16 * 450.00 /*MHz*/, 0x8e, 0x02, }, + { 16 * 999.99 , 0x8e, 0x08, }, +}; + +static struct tuner_params tuner_lg_pal_new_tapc_params[] = { + { + .type = TUNER_PARAM_TYPE_PAL, + .ranges = tuner_lg_new_tapc_ranges, + .count = ARRAY_SIZE(tuner_lg_new_tapc_ranges), + }, +}; + +/* ------------ TUNER_PHILIPS_FM1216ME_MK3 - Philips PAL ------------ */ + +static struct tuner_range tuner_fm1216me_mk3_pal_ranges[] = { + { 16 * 158.00 /*MHz*/, 0x8e, 0x01, }, + { 16 * 442.00 /*MHz*/, 0x8e, 0x02, }, + { 16 * 999.99 , 0x8e, 0x04, }, +}; + +static struct tuner_params tuner_fm1216me_mk3_params[] = { + { + .type = TUNER_PARAM_TYPE_PAL, + .ranges = tuner_fm1216me_mk3_pal_ranges, + .count = ARRAY_SIZE(tuner_fm1216me_mk3_pal_ranges), + .cb_first_if_lower_freq = 1, + .has_tda9887 = 1, + .port1_active = 1, + .port2_active = 1, + .port2_invert_for_secam_lc = 1, + .port1_fm_high_sensitivity = 1, + .default_top_mid = -2, + .default_top_secam_mid = -2, + .default_top_secam_high = -2, + }, +}; + +/* ------------ TUNER_LG_NTSC_NEW_TAPC - LGINNOTEK NTSC ------------ */ + +static struct tuner_params tuner_lg_ntsc_new_tapc_params[] = { + { + .type = TUNER_PARAM_TYPE_NTSC, + .ranges = tuner_lg_new_tapc_ranges, + .count = ARRAY_SIZE(tuner_lg_new_tapc_ranges), + }, +}; + +/* 40-49 */ +/* ------------ TUNER_HITACHI_NTSC - HITACHI NTSC ------------ */ + +static struct tuner_params tuner_hitachi_ntsc_params[] = { + { + .type = TUNER_PARAM_TYPE_NTSC, + .ranges = tuner_lg_new_tapc_ranges, + .count = ARRAY_SIZE(tuner_lg_new_tapc_ranges), + }, +}; + +/* ------------ TUNER_PHILIPS_PAL_MK - Philips PAL ------------ */ + +static struct tuner_range tuner_philips_pal_mk_pal_ranges[] = { + { 16 * 140.25 /*MHz*/, 0x8e, 0x01, }, + { 16 * 463.25 /*MHz*/, 0x8e, 0xc2, }, + { 16 * 999.99 , 0x8e, 0xcf, }, +}; + +static struct tuner_params tuner_philips_pal_mk_params[] = { + { + .type = TUNER_PARAM_TYPE_PAL, + .ranges = tuner_philips_pal_mk_pal_ranges, + .count = ARRAY_SIZE(tuner_philips_pal_mk_pal_ranges), + }, +}; + +/* ---- TUNER_PHILIPS_FCV1236D - Philips FCV1236D (ATSC/NTSC) ---- */ + +static struct tuner_range tuner_philips_fcv1236d_ntsc_ranges[] = { + { 16 * 157.25 /*MHz*/, 0x8e, 0xa2, }, + { 16 * 451.25 /*MHz*/, 0x8e, 0x92, }, + { 16 * 999.99 , 0x8e, 0x32, }, +}; + +static struct tuner_range tuner_philips_fcv1236d_atsc_ranges[] = { + { 16 * 159.00 /*MHz*/, 0x8e, 0xa0, }, + { 16 * 453.00 /*MHz*/, 0x8e, 0x90, }, + { 16 * 999.99 , 0x8e, 0x30, }, +}; + +static struct tuner_params tuner_philips_fcv1236d_params[] = { + { + .type = TUNER_PARAM_TYPE_NTSC, + .ranges = tuner_philips_fcv1236d_ntsc_ranges, + .count = ARRAY_SIZE(tuner_philips_fcv1236d_ntsc_ranges), + }, + { + .type = TUNER_PARAM_TYPE_DIGITAL, + .ranges = tuner_philips_fcv1236d_atsc_ranges, + .count = ARRAY_SIZE(tuner_philips_fcv1236d_atsc_ranges), + .iffreq = 16 * 44.00, + }, +}; + +/* ------------ TUNER_PHILIPS_FM1236_MK3 - Philips NTSC ------------ */ + +static struct tuner_range tuner_fm1236_mk3_ntsc_ranges[] = { + { 16 * 160.00 /*MHz*/, 0x8e, 0x01, }, + { 16 * 442.00 /*MHz*/, 0x8e, 0x02, }, + { 16 * 999.99 , 0x8e, 0x04, }, +}; + +static struct tuner_params tuner_fm1236_mk3_params[] = { + { + .type = TUNER_PARAM_TYPE_NTSC, + .ranges = tuner_fm1236_mk3_ntsc_ranges, + .count = ARRAY_SIZE(tuner_fm1236_mk3_ntsc_ranges), + .cb_first_if_lower_freq = 1, + .has_tda9887 = 1, + .port1_active = 1, + .port2_active = 1, + .port1_fm_high_sensitivity = 1, + }, +}; + +/* ------------ TUNER_PHILIPS_4IN1 - Philips NTSC ------------ */ + +static struct tuner_params tuner_philips_4in1_params[] = { + { + .type = TUNER_PARAM_TYPE_NTSC, + .ranges = tuner_fm1236_mk3_ntsc_ranges, + .count = ARRAY_SIZE(tuner_fm1236_mk3_ntsc_ranges), + }, +}; + +/* ------------ TUNER_MICROTUNE_4049FM5 - Microtune PAL ------------ */ + +static struct tuner_params tuner_microtune_4049_fm5_params[] = { + { + .type = TUNER_PARAM_TYPE_PAL, + .ranges = tuner_temic_4009f_5_pal_ranges, + .count = ARRAY_SIZE(tuner_temic_4009f_5_pal_ranges), + .has_tda9887 = 1, + .port1_invert_for_secam_lc = 1, + .default_pll_gating_18 = 1, + .fm_gain_normal=1, + .radio_if = 1, /* 33.3 MHz */ + }, +}; + +/* ------------ TUNER_PANASONIC_VP27 - Panasonic NTSC ------------ */ + +static struct tuner_range tuner_panasonic_vp27_ntsc_ranges[] = { + { 16 * 160.00 /*MHz*/, 0xce, 0x01, }, + { 16 * 454.00 /*MHz*/, 0xce, 0x02, }, + { 16 * 999.99 , 0xce, 0x08, }, +}; + +static struct tuner_params tuner_panasonic_vp27_params[] = { + { + .type = TUNER_PARAM_TYPE_NTSC, + .ranges = tuner_panasonic_vp27_ntsc_ranges, + .count = ARRAY_SIZE(tuner_panasonic_vp27_ntsc_ranges), + .has_tda9887 = 1, + .intercarrier_mode = 1, + .default_top_low = -3, + .default_top_mid = -3, + .default_top_high = -3, + }, +}; + +/* ------------ TUNER_TNF_8831BGFF - Philips PAL ------------ */ + +static struct tuner_range tuner_tnf_8831bgff_pal_ranges[] = { + { 16 * 161.25 /*MHz*/, 0x8e, 0xa0, }, + { 16 * 463.25 /*MHz*/, 0x8e, 0x90, }, + { 16 * 999.99 , 0x8e, 0x30, }, +}; + +static struct tuner_params tuner_tnf_8831bgff_params[] = { + { + .type = TUNER_PARAM_TYPE_PAL, + .ranges = tuner_tnf_8831bgff_pal_ranges, + .count = ARRAY_SIZE(tuner_tnf_8831bgff_pal_ranges), + }, +}; + +/* ------------ TUNER_MICROTUNE_4042FI5 - Microtune NTSC ------------ */ + +static struct tuner_range tuner_microtune_4042fi5_ntsc_ranges[] = { + { 16 * 162.00 /*MHz*/, 0x8e, 0xa2, }, + { 16 * 457.00 /*MHz*/, 0x8e, 0x94, }, + { 16 * 999.99 , 0x8e, 0x31, }, +}; + +static struct tuner_range tuner_microtune_4042fi5_atsc_ranges[] = { + { 16 * 162.00 /*MHz*/, 0x8e, 0xa1, }, + { 16 * 457.00 /*MHz*/, 0x8e, 0x91, }, + { 16 * 999.99 , 0x8e, 0x31, }, +}; + +static struct tuner_params tuner_microtune_4042fi5_params[] = { + { + .type = TUNER_PARAM_TYPE_NTSC, + .ranges = tuner_microtune_4042fi5_ntsc_ranges, + .count = ARRAY_SIZE(tuner_microtune_4042fi5_ntsc_ranges), + }, + { + .type = TUNER_PARAM_TYPE_DIGITAL, + .ranges = tuner_microtune_4042fi5_atsc_ranges, + .count = ARRAY_SIZE(tuner_microtune_4042fi5_atsc_ranges), + .iffreq = 16 * 44.00 /*MHz*/, + }, +}; + +/* 50-59 */ +/* ------------ TUNER_TCL_2002N - TCL NTSC ------------ */ + +static struct tuner_range tuner_tcl_2002n_ntsc_ranges[] = { + { 16 * 172.00 /*MHz*/, 0x8e, 0x01, }, + { 16 * 448.00 /*MHz*/, 0x8e, 0x02, }, + { 16 * 999.99 , 0x8e, 0x08, }, +}; + +static struct tuner_params tuner_tcl_2002n_params[] = { + { + .type = TUNER_PARAM_TYPE_NTSC, + .ranges = tuner_tcl_2002n_ntsc_ranges, + .count = ARRAY_SIZE(tuner_tcl_2002n_ntsc_ranges), + .cb_first_if_lower_freq = 1, + }, +}; + +/* ------------ TUNER_PHILIPS_FM1256_IH3 - Philips PAL ------------ */ + +static struct tuner_params tuner_philips_fm1256_ih3_params[] = { + { + .type = TUNER_PARAM_TYPE_PAL, + .ranges = tuner_fm1236_mk3_ntsc_ranges, + .count = ARRAY_SIZE(tuner_fm1236_mk3_ntsc_ranges), + .radio_if = 1, /* 33.3 MHz */ + }, +}; + +/* ------------ TUNER_THOMSON_DTT7610 - THOMSON ATSC ------------ */ + +/* single range used for both ntsc and atsc */ +static struct tuner_range tuner_thomson_dtt7610_ntsc_ranges[] = { + { 16 * 157.25 /*MHz*/, 0x8e, 0x39, }, + { 16 * 454.00 /*MHz*/, 0x8e, 0x3a, }, + { 16 * 999.99 , 0x8e, 0x3c, }, +}; + +static struct tuner_params tuner_thomson_dtt7610_params[] = { + { + .type = TUNER_PARAM_TYPE_NTSC, + .ranges = tuner_thomson_dtt7610_ntsc_ranges, + .count = ARRAY_SIZE(tuner_thomson_dtt7610_ntsc_ranges), + }, + { + .type = TUNER_PARAM_TYPE_DIGITAL, + .ranges = tuner_thomson_dtt7610_ntsc_ranges, + .count = ARRAY_SIZE(tuner_thomson_dtt7610_ntsc_ranges), + .iffreq = 16 * 44.00 /*MHz*/, + }, +}; + +/* ------------ TUNER_PHILIPS_FQ1286 - Philips NTSC ------------ */ + +static struct tuner_range tuner_philips_fq1286_ntsc_ranges[] = { + { 16 * 160.00 /*MHz*/, 0x8e, 0x41, }, + { 16 * 454.00 /*MHz*/, 0x8e, 0x42, }, + { 16 * 999.99 , 0x8e, 0x04, }, +}; + +static struct tuner_params tuner_philips_fq1286_params[] = { + { + .type = TUNER_PARAM_TYPE_NTSC, + .ranges = tuner_philips_fq1286_ntsc_ranges, + .count = ARRAY_SIZE(tuner_philips_fq1286_ntsc_ranges), + }, +}; + +/* ------------ TUNER_TCL_2002MB - TCL PAL ------------ */ + +static struct tuner_range tuner_tcl_2002mb_pal_ranges[] = { + { 16 * 170.00 /*MHz*/, 0xce, 0x01, }, + { 16 * 450.00 /*MHz*/, 0xce, 0x02, }, + { 16 * 999.99 , 0xce, 0x08, }, +}; + +static struct tuner_params tuner_tcl_2002mb_params[] = { + { + .type = TUNER_PARAM_TYPE_PAL, + .ranges = tuner_tcl_2002mb_pal_ranges, + .count = ARRAY_SIZE(tuner_tcl_2002mb_pal_ranges), + }, +}; + +/* ------------ TUNER_PHILIPS_FQ1216AME_MK4 - Philips PAL ------------ */ + +static struct tuner_range tuner_philips_fq12_6a___mk4_pal_ranges[] = { + { 16 * 160.00 /*MHz*/, 0xce, 0x01, }, + { 16 * 442.00 /*MHz*/, 0xce, 0x02, }, + { 16 * 999.99 , 0xce, 0x04, }, +}; + +static struct tuner_params tuner_philips_fq1216ame_mk4_params[] = { + { + .type = TUNER_PARAM_TYPE_PAL, + .ranges = tuner_philips_fq12_6a___mk4_pal_ranges, + .count = ARRAY_SIZE(tuner_philips_fq12_6a___mk4_pal_ranges), + .has_tda9887 = 1, + .port1_active = 1, + .port2_invert_for_secam_lc = 1, + .default_top_mid = -2, + .default_top_secam_low = -2, + .default_top_secam_mid = -2, + .default_top_secam_high = -2, + }, +}; + +/* ------------ TUNER_PHILIPS_FQ1236A_MK4 - Philips NTSC ------------ */ + +static struct tuner_params tuner_philips_fq1236a_mk4_params[] = { + { + .type = TUNER_PARAM_TYPE_NTSC, + .ranges = tuner_fm1236_mk3_ntsc_ranges, + .count = ARRAY_SIZE(tuner_fm1236_mk3_ntsc_ranges), + }, +}; + +/* ------------ TUNER_YMEC_TVF_8531MF - Philips NTSC ------------ */ + +static struct tuner_params tuner_ymec_tvf_8531mf_params[] = { + { + .type = TUNER_PARAM_TYPE_NTSC, + .ranges = tuner_philips_ntsc_m_ranges, + .count = ARRAY_SIZE(tuner_philips_ntsc_m_ranges), + }, +}; + +/* ------------ TUNER_YMEC_TVF_5533MF - Philips NTSC ------------ */ + +static struct tuner_range tuner_ymec_tvf_5533mf_ntsc_ranges[] = { + { 16 * 160.00 /*MHz*/, 0x8e, 0x01, }, + { 16 * 454.00 /*MHz*/, 0x8e, 0x02, }, + { 16 * 999.99 , 0x8e, 0x04, }, +}; + +static struct tuner_params tuner_ymec_tvf_5533mf_params[] = { + { + .type = TUNER_PARAM_TYPE_NTSC, + .ranges = tuner_ymec_tvf_5533mf_ntsc_ranges, + .count = ARRAY_SIZE(tuner_ymec_tvf_5533mf_ntsc_ranges), + }, +}; + +/* 60-69 */ +/* ------------ TUNER_THOMSON_DTT761X - THOMSON ATSC ------------ */ +/* DTT 7611 7611A 7612 7613 7613A 7614 7615 7615A */ + +static struct tuner_range tuner_thomson_dtt761x_ntsc_ranges[] = { + { 16 * 145.25 /*MHz*/, 0x8e, 0x39, }, + { 16 * 415.25 /*MHz*/, 0x8e, 0x3a, }, + { 16 * 999.99 , 0x8e, 0x3c, }, +}; + +static struct tuner_range tuner_thomson_dtt761x_atsc_ranges[] = { + { 16 * 147.00 /*MHz*/, 0x8e, 0x39, }, + { 16 * 417.00 /*MHz*/, 0x8e, 0x3a, }, + { 16 * 999.99 , 0x8e, 0x3c, }, +}; + +static struct tuner_params tuner_thomson_dtt761x_params[] = { + { + .type = TUNER_PARAM_TYPE_NTSC, + .ranges = tuner_thomson_dtt761x_ntsc_ranges, + .count = ARRAY_SIZE(tuner_thomson_dtt761x_ntsc_ranges), + .has_tda9887 = 1, + .fm_gain_normal = 1, + .radio_if = 2, /* 41.3 MHz */ + }, + { + .type = TUNER_PARAM_TYPE_DIGITAL, + .ranges = tuner_thomson_dtt761x_atsc_ranges, + .count = ARRAY_SIZE(tuner_thomson_dtt761x_atsc_ranges), + .iffreq = 16 * 44.00, /*MHz*/ + }, +}; + +/* ------------ TUNER_TENA_9533_DI - Philips PAL ------------ */ + +static struct tuner_range tuner_tena_9533_di_pal_ranges[] = { + { 16 * 160.25 /*MHz*/, 0x8e, 0x01, }, + { 16 * 464.25 /*MHz*/, 0x8e, 0x02, }, + { 16 * 999.99 , 0x8e, 0x04, }, +}; + +static struct tuner_params tuner_tena_9533_di_params[] = { + { + .type = TUNER_PARAM_TYPE_PAL, + .ranges = tuner_tena_9533_di_pal_ranges, + .count = ARRAY_SIZE(tuner_tena_9533_di_pal_ranges), + }, +}; + +/* ------------ TUNER_PHILIPS_FMD1216ME_MK3 - Philips PAL ------------ */ + +static struct tuner_range tuner_philips_fmd1216me_mk3_pal_ranges[] = { + { 16 * 160.00 /*MHz*/, 0x86, 0x51, }, + { 16 * 442.00 /*MHz*/, 0x86, 0x52, }, + { 16 * 999.99 , 0x86, 0x54, }, +}; + +static struct tuner_range tuner_philips_fmd1216me_mk3_dvb_ranges[] = { + { 16 * 143.87 /*MHz*/, 0xbc, 0x41 }, + { 16 * 158.87 /*MHz*/, 0xf4, 0x41 }, + { 16 * 329.87 /*MHz*/, 0xbc, 0x42 }, + { 16 * 441.87 /*MHz*/, 0xf4, 0x42 }, + { 16 * 625.87 /*MHz*/, 0xbc, 0x44 }, + { 16 * 803.87 /*MHz*/, 0xf4, 0x44 }, + { 16 * 999.99 , 0xfc, 0x44 }, +}; + +static struct tuner_params tuner_philips_fmd1216me_mk3_params[] = { + { + .type = TUNER_PARAM_TYPE_PAL, + .ranges = tuner_philips_fmd1216me_mk3_pal_ranges, + .count = ARRAY_SIZE(tuner_philips_fmd1216me_mk3_pal_ranges), + .has_tda9887 = 1, + .port1_active = 1, + .port2_active = 1, + .port2_fm_high_sensitivity = 1, + .port2_invert_for_secam_lc = 1, + .port1_set_for_fm_mono = 1, + }, + { + .type = TUNER_PARAM_TYPE_DIGITAL, + .ranges = tuner_philips_fmd1216me_mk3_dvb_ranges, + .count = ARRAY_SIZE(tuner_philips_fmd1216me_mk3_dvb_ranges), + .iffreq = 16 * 36.125, /*MHz*/ + }, +}; + + +/* ------ TUNER_LG_TDVS_H06XF - LG INNOTEK / INFINEON ATSC ----- */ + +static struct tuner_range tuner_tua6034_ntsc_ranges[] = { + { 16 * 165.00 /*MHz*/, 0x8e, 0x01 }, + { 16 * 450.00 /*MHz*/, 0x8e, 0x02 }, + { 16 * 999.99 , 0x8e, 0x04 }, +}; + +static struct tuner_range tuner_tua6034_atsc_ranges[] = { + { 16 * 165.00 /*MHz*/, 0xce, 0x01 }, + { 16 * 450.00 /*MHz*/, 0xce, 0x02 }, + { 16 * 999.99 , 0xce, 0x04 }, +}; + +static struct tuner_params tuner_lg_tdvs_h06xf_params[] = { + { + .type = TUNER_PARAM_TYPE_NTSC, + .ranges = tuner_tua6034_ntsc_ranges, + .count = ARRAY_SIZE(tuner_tua6034_ntsc_ranges), + }, + { + .type = TUNER_PARAM_TYPE_DIGITAL, + .ranges = tuner_tua6034_atsc_ranges, + .count = ARRAY_SIZE(tuner_tua6034_atsc_ranges), + .iffreq = 16 * 44.00, + }, +}; + +/* ------------ TUNER_YMEC_TVF66T5_B_DFF - Philips PAL ------------ */ + +static struct tuner_range tuner_ymec_tvf66t5_b_dff_pal_ranges[] = { + { 16 * 160.25 /*MHz*/, 0x8e, 0x01, }, + { 16 * 464.25 /*MHz*/, 0x8e, 0x02, }, + { 16 * 999.99 , 0x8e, 0x08, }, +}; + +static struct tuner_params tuner_ymec_tvf66t5_b_dff_params[] = { + { + .type = TUNER_PARAM_TYPE_PAL, + .ranges = tuner_ymec_tvf66t5_b_dff_pal_ranges, + .count = ARRAY_SIZE(tuner_ymec_tvf66t5_b_dff_pal_ranges), + }, +}; + +/* ------------ TUNER_LG_NTSC_TALN_MINI - LGINNOTEK NTSC ------------ */ + +static struct tuner_range tuner_lg_taln_ntsc_ranges[] = { + { 16 * 137.25 /*MHz*/, 0x8e, 0x01, }, + { 16 * 373.25 /*MHz*/, 0x8e, 0x02, }, + { 16 * 999.99 , 0x8e, 0x08, }, +}; + +static struct tuner_range tuner_lg_taln_pal_secam_ranges[] = { + { 16 * 150.00 /*MHz*/, 0x8e, 0x01, }, + { 16 * 425.00 /*MHz*/, 0x8e, 0x02, }, + { 16 * 999.99 , 0x8e, 0x08, }, +}; + +static struct tuner_params tuner_lg_taln_params[] = { + { + .type = TUNER_PARAM_TYPE_NTSC, + .ranges = tuner_lg_taln_ntsc_ranges, + .count = ARRAY_SIZE(tuner_lg_taln_ntsc_ranges), + },{ + .type = TUNER_PARAM_TYPE_PAL, + .ranges = tuner_lg_taln_pal_secam_ranges, + .count = ARRAY_SIZE(tuner_lg_taln_pal_secam_ranges), + }, +}; + +/* ------------ TUNER_PHILIPS_TD1316 - Philips PAL ------------ */ + +static struct tuner_range tuner_philips_td1316_pal_ranges[] = { + { 16 * 160.00 /*MHz*/, 0xc8, 0xa1, }, + { 16 * 442.00 /*MHz*/, 0xc8, 0xa2, }, + { 16 * 999.99 , 0xc8, 0xa4, }, +}; + +static struct tuner_range tuner_philips_td1316_dvb_ranges[] = { + { 16 * 93.834 /*MHz*/, 0xca, 0x60, }, + { 16 * 123.834 /*MHz*/, 0xca, 0xa0, }, + { 16 * 163.834 /*MHz*/, 0xca, 0xc0, }, + { 16 * 253.834 /*MHz*/, 0xca, 0x60, }, + { 16 * 383.834 /*MHz*/, 0xca, 0xa0, }, + { 16 * 443.834 /*MHz*/, 0xca, 0xc0, }, + { 16 * 583.834 /*MHz*/, 0xca, 0x60, }, + { 16 * 793.834 /*MHz*/, 0xca, 0xa0, }, + { 16 * 999.999 , 0xca, 0xe0, }, +}; + +static struct tuner_params tuner_philips_td1316_params[] = { + { + .type = TUNER_PARAM_TYPE_PAL, + .ranges = tuner_philips_td1316_pal_ranges, + .count = ARRAY_SIZE(tuner_philips_td1316_pal_ranges), + }, + { + .type = TUNER_PARAM_TYPE_DIGITAL, + .ranges = tuner_philips_td1316_dvb_ranges, + .count = ARRAY_SIZE(tuner_philips_td1316_dvb_ranges), + .iffreq = 16 * 36.166667 /*MHz*/, + }, +}; + +/* ------------ TUNER_PHILIPS_TUV1236D - Philips ATSC ------------ */ + +static struct tuner_range tuner_tuv1236d_ntsc_ranges[] = { + { 16 * 157.25 /*MHz*/, 0xce, 0x01, }, + { 16 * 454.00 /*MHz*/, 0xce, 0x02, }, + { 16 * 999.99 , 0xce, 0x04, }, +}; + +static struct tuner_range tuner_tuv1236d_atsc_ranges[] = { + { 16 * 157.25 /*MHz*/, 0xc6, 0x41, }, + { 16 * 454.00 /*MHz*/, 0xc6, 0x42, }, + { 16 * 999.99 , 0xc6, 0x44, }, +}; + +static struct tuner_params tuner_tuv1236d_params[] = { + { + .type = TUNER_PARAM_TYPE_NTSC, + .ranges = tuner_tuv1236d_ntsc_ranges, + .count = ARRAY_SIZE(tuner_tuv1236d_ntsc_ranges), + }, + { + .type = TUNER_PARAM_TYPE_DIGITAL, + .ranges = tuner_tuv1236d_atsc_ranges, + .count = ARRAY_SIZE(tuner_tuv1236d_atsc_ranges), + .iffreq = 16 * 44.00, + }, +}; + +/* ------------ TUNER_TNF_xxx5 - Texas Instruments--------- */ +/* This is known to work with Tenna TVF58t5-MFF and TVF5835 MFF + * but it is expected to work also with other Tenna/Ymec + * models based on TI SN 761677 chip on both PAL and NTSC + */ + +static struct tuner_range tuner_tnf_5335_d_if_pal_ranges[] = { + { 16 * 168.25 /*MHz*/, 0x8e, 0x01, }, + { 16 * 471.25 /*MHz*/, 0x8e, 0x02, }, + { 16 * 999.99 , 0x8e, 0x08, }, +}; + +static struct tuner_range tuner_tnf_5335mf_ntsc_ranges[] = { + { 16 * 169.25 /*MHz*/, 0x8e, 0x01, }, + { 16 * 469.25 /*MHz*/, 0x8e, 0x02, }, + { 16 * 999.99 , 0x8e, 0x08, }, +}; + +static struct tuner_params tuner_tnf_5335mf_params[] = { + { + .type = TUNER_PARAM_TYPE_NTSC, + .ranges = tuner_tnf_5335mf_ntsc_ranges, + .count = ARRAY_SIZE(tuner_tnf_5335mf_ntsc_ranges), + }, + { + .type = TUNER_PARAM_TYPE_PAL, + .ranges = tuner_tnf_5335_d_if_pal_ranges, + .count = ARRAY_SIZE(tuner_tnf_5335_d_if_pal_ranges), + }, +}; + +/* 70-79 */ +/* ------------ TUNER_SAMSUNG_TCPN_2121P30A - Samsung NTSC ------------ */ + +/* '+ 4' turns on the Low Noise Amplifier */ +static struct tuner_range tuner_samsung_tcpn_2121p30a_ntsc_ranges[] = { + { 16 * 130.00 /*MHz*/, 0xce, 0x01 + 4, }, + { 16 * 364.50 /*MHz*/, 0xce, 0x02 + 4, }, + { 16 * 999.99 , 0xce, 0x08 + 4, }, +}; + +static struct tuner_params tuner_samsung_tcpn_2121p30a_params[] = { + { + .type = TUNER_PARAM_TYPE_NTSC, + .ranges = tuner_samsung_tcpn_2121p30a_ntsc_ranges, + .count = ARRAY_SIZE(tuner_samsung_tcpn_2121p30a_ntsc_ranges), + }, +}; + +/* ------------ TUNER_THOMSON_FE6600 - DViCO Hybrid PAL ------------ */ + +static struct tuner_range tuner_thomson_fe6600_pal_ranges[] = { + { 16 * 160.00 /*MHz*/, 0xfe, 0x11, }, + { 16 * 442.00 /*MHz*/, 0xf6, 0x12, }, + { 16 * 999.99 , 0xf6, 0x18, }, +}; + +static struct tuner_range tuner_thomson_fe6600_dvb_ranges[] = { + { 16 * 250.00 /*MHz*/, 0xb4, 0x12, }, + { 16 * 455.00 /*MHz*/, 0xfe, 0x11, }, + { 16 * 775.50 /*MHz*/, 0xbc, 0x18, }, + { 16 * 999.99 , 0xf4, 0x18, }, +}; + +static struct tuner_params tuner_thomson_fe6600_params[] = { + { + .type = TUNER_PARAM_TYPE_PAL, + .ranges = tuner_thomson_fe6600_pal_ranges, + .count = ARRAY_SIZE(tuner_thomson_fe6600_pal_ranges), + }, + { + .type = TUNER_PARAM_TYPE_DIGITAL, + .ranges = tuner_thomson_fe6600_dvb_ranges, + .count = ARRAY_SIZE(tuner_thomson_fe6600_dvb_ranges), + .iffreq = 16 * 36.125 /*MHz*/, + }, +}; + +/* ------------ TUNER_SAMSUNG_TCPG_6121P30A - Samsung PAL ------------ */ + +/* '+ 4' turns on the Low Noise Amplifier */ +static struct tuner_range tuner_samsung_tcpg_6121p30a_pal_ranges[] = { + { 16 * 146.25 /*MHz*/, 0xce, 0x01 + 4, }, + { 16 * 428.50 /*MHz*/, 0xce, 0x02 + 4, }, + { 16 * 999.99 , 0xce, 0x08 + 4, }, +}; + +static struct tuner_params tuner_samsung_tcpg_6121p30a_params[] = { + { + .type = TUNER_PARAM_TYPE_PAL, + .ranges = tuner_samsung_tcpg_6121p30a_pal_ranges, + .count = ARRAY_SIZE(tuner_samsung_tcpg_6121p30a_pal_ranges), + .has_tda9887 = 1, + .port1_active = 1, + .port2_active = 1, + .port2_invert_for_secam_lc = 1, + }, +}; + +/* --------------------------------------------------------------------- */ + +struct tunertype tuners[] = { + /* 0-9 */ + [TUNER_TEMIC_PAL] = { /* TEMIC PAL */ + .name = "Temic PAL (4002 FH5)", + .params = tuner_temic_pal_params, + .count = ARRAY_SIZE(tuner_temic_pal_params), + }, + [TUNER_PHILIPS_PAL_I] = { /* Philips PAL_I */ + .name = "Philips PAL_I (FI1246 and compatibles)", + .params = tuner_philips_pal_i_params, + .count = ARRAY_SIZE(tuner_philips_pal_i_params), + }, + [TUNER_PHILIPS_NTSC] = { /* Philips NTSC */ + .name = "Philips NTSC (FI1236,FM1236 and compatibles)", + .params = tuner_philips_ntsc_params, + .count = ARRAY_SIZE(tuner_philips_ntsc_params), + }, + [TUNER_PHILIPS_SECAM] = { /* Philips SECAM */ + .name = "Philips (SECAM+PAL_BG) (FI1216MF, FM1216MF, FR1216MF)", + .params = tuner_philips_secam_params, + .count = ARRAY_SIZE(tuner_philips_secam_params), + }, + [TUNER_ABSENT] = { /* Tuner Absent */ + .name = "NoTuner", + }, + [TUNER_PHILIPS_PAL] = { /* Philips PAL */ + .name = "Philips PAL_BG (FI1216 and compatibles)", + .params = tuner_philips_pal_params, + .count = ARRAY_SIZE(tuner_philips_pal_params), + }, + [TUNER_TEMIC_NTSC] = { /* TEMIC NTSC */ + .name = "Temic NTSC (4032 FY5)", + .params = tuner_temic_ntsc_params, + .count = ARRAY_SIZE(tuner_temic_ntsc_params), + }, + [TUNER_TEMIC_PAL_I] = { /* TEMIC PAL_I */ + .name = "Temic PAL_I (4062 FY5)", + .params = tuner_temic_pal_i_params, + .count = ARRAY_SIZE(tuner_temic_pal_i_params), + }, + [TUNER_TEMIC_4036FY5_NTSC] = { /* TEMIC NTSC */ + .name = "Temic NTSC (4036 FY5)", + .params = tuner_temic_4036fy5_ntsc_params, + .count = ARRAY_SIZE(tuner_temic_4036fy5_ntsc_params), + }, + [TUNER_ALPS_TSBH1_NTSC] = { /* TEMIC NTSC */ + .name = "Alps HSBH1", + .params = tuner_alps_tsbh1_ntsc_params, + .count = ARRAY_SIZE(tuner_alps_tsbh1_ntsc_params), + }, + + /* 10-19 */ + [TUNER_ALPS_TSBE1_PAL] = { /* TEMIC PAL */ + .name = "Alps TSBE1", + .params = tuner_alps_tsb_1_params, + .count = ARRAY_SIZE(tuner_alps_tsb_1_params), + }, + [TUNER_ALPS_TSBB5_PAL_I] = { /* Alps PAL_I */ + .name = "Alps TSBB5", + .params = tuner_alps_tsbb5_params, + .count = ARRAY_SIZE(tuner_alps_tsbb5_params), + }, + [TUNER_ALPS_TSBE5_PAL] = { /* Alps PAL */ + .name = "Alps TSBE5", + .params = tuner_alps_tsbe5_params, + .count = ARRAY_SIZE(tuner_alps_tsbe5_params), + }, + [TUNER_ALPS_TSBC5_PAL] = { /* Alps PAL */ + .name = "Alps TSBC5", + .params = tuner_alps_tsbc5_params, + .count = ARRAY_SIZE(tuner_alps_tsbc5_params), + }, + [TUNER_TEMIC_4006FH5_PAL] = { /* TEMIC PAL */ + .name = "Temic PAL_BG (4006FH5)", + .params = tuner_temic_4006fh5_params, + .count = ARRAY_SIZE(tuner_temic_4006fh5_params), + }, + [TUNER_ALPS_TSHC6_NTSC] = { /* Alps NTSC */ + .name = "Alps TSCH6", + .params = tuner_alps_tshc6_params, + .count = ARRAY_SIZE(tuner_alps_tshc6_params), + }, + [TUNER_TEMIC_PAL_DK] = { /* TEMIC PAL */ + .name = "Temic PAL_DK (4016 FY5)", + .params = tuner_temic_pal_dk_params, + .count = ARRAY_SIZE(tuner_temic_pal_dk_params), + }, + [TUNER_PHILIPS_NTSC_M] = { /* Philips NTSC */ + .name = "Philips NTSC_M (MK2)", + .params = tuner_philips_ntsc_m_params, + .count = ARRAY_SIZE(tuner_philips_ntsc_m_params), + }, + [TUNER_TEMIC_4066FY5_PAL_I] = { /* TEMIC PAL_I */ + .name = "Temic PAL_I (4066 FY5)", + .params = tuner_temic_4066fy5_pal_i_params, + .count = ARRAY_SIZE(tuner_temic_4066fy5_pal_i_params), + }, + [TUNER_TEMIC_4006FN5_MULTI_PAL] = { /* TEMIC PAL */ + .name = "Temic PAL* auto (4006 FN5)", + .params = tuner_temic_4006fn5_multi_params, + .count = ARRAY_SIZE(tuner_temic_4006fn5_multi_params), + }, + + /* 20-29 */ + [TUNER_TEMIC_4009FR5_PAL] = { /* TEMIC PAL */ + .name = "Temic PAL_BG (4009 FR5) or PAL_I (4069 FR5)", + .params = tuner_temic_4009f_5_params, + .count = ARRAY_SIZE(tuner_temic_4009f_5_params), + }, + [TUNER_TEMIC_4039FR5_NTSC] = { /* TEMIC NTSC */ + .name = "Temic NTSC (4039 FR5)", + .params = tuner_temic_4039fr5_params, + .count = ARRAY_SIZE(tuner_temic_4039fr5_params), + }, + [TUNER_TEMIC_4046FM5] = { /* TEMIC PAL */ + .name = "Temic PAL/SECAM multi (4046 FM5)", + .params = tuner_temic_4046fm5_params, + .count = ARRAY_SIZE(tuner_temic_4046fm5_params), + }, + [TUNER_PHILIPS_PAL_DK] = { /* Philips PAL */ + .name = "Philips PAL_DK (FI1256 and compatibles)", + .params = tuner_philips_pal_dk_params, + .count = ARRAY_SIZE(tuner_philips_pal_dk_params), + }, + [TUNER_PHILIPS_FQ1216ME] = { /* Philips PAL */ + .name = "Philips PAL/SECAM multi (FQ1216ME)", + .params = tuner_philips_fq1216me_params, + .count = ARRAY_SIZE(tuner_philips_fq1216me_params), + }, + [TUNER_LG_PAL_I_FM] = { /* LGINNOTEK PAL_I */ + .name = "LG PAL_I+FM (TAPC-I001D)", + .params = tuner_lg_pal_i_fm_params, + .count = ARRAY_SIZE(tuner_lg_pal_i_fm_params), + }, + [TUNER_LG_PAL_I] = { /* LGINNOTEK PAL_I */ + .name = "LG PAL_I (TAPC-I701D)", + .params = tuner_lg_pal_i_params, + .count = ARRAY_SIZE(tuner_lg_pal_i_params), + }, + [TUNER_LG_NTSC_FM] = { /* LGINNOTEK NTSC */ + .name = "LG NTSC+FM (TPI8NSR01F)", + .params = tuner_lg_ntsc_fm_params, + .count = ARRAY_SIZE(tuner_lg_ntsc_fm_params), + }, + [TUNER_LG_PAL_FM] = { /* LGINNOTEK PAL */ + .name = "LG PAL_BG+FM (TPI8PSB01D)", + .params = tuner_lg_pal_fm_params, + .count = ARRAY_SIZE(tuner_lg_pal_fm_params), + }, + [TUNER_LG_PAL] = { /* LGINNOTEK PAL */ + .name = "LG PAL_BG (TPI8PSB11D)", + .params = tuner_lg_pal_params, + .count = ARRAY_SIZE(tuner_lg_pal_params), + }, + + /* 30-39 */ + [TUNER_TEMIC_4009FN5_MULTI_PAL_FM] = { /* TEMIC PAL */ + .name = "Temic PAL* auto + FM (4009 FN5)", + .params = tuner_temic_4009_fn5_multi_pal_fm_params, + .count = ARRAY_SIZE(tuner_temic_4009_fn5_multi_pal_fm_params), + }, + [TUNER_SHARP_2U5JF5540_NTSC] = { /* SHARP NTSC */ + .name = "SHARP NTSC_JP (2U5JF5540)", + .params = tuner_sharp_2u5jf5540_params, + .count = ARRAY_SIZE(tuner_sharp_2u5jf5540_params), + }, + [TUNER_Samsung_PAL_TCPM9091PD27] = { /* Samsung PAL */ + .name = "Samsung PAL TCPM9091PD27", + .params = tuner_samsung_pal_tcpm9091pd27_params, + .count = ARRAY_SIZE(tuner_samsung_pal_tcpm9091pd27_params), + }, + [TUNER_MT2032] = { /* Microtune PAL|NTSC */ + .name = "MT20xx universal", + /* see mt20xx.c for details */ }, + [TUNER_TEMIC_4106FH5] = { /* TEMIC PAL */ + .name = "Temic PAL_BG (4106 FH5)", + .params = tuner_temic_4106fh5_params, + .count = ARRAY_SIZE(tuner_temic_4106fh5_params), + }, + [TUNER_TEMIC_4012FY5] = { /* TEMIC PAL */ + .name = "Temic PAL_DK/SECAM_L (4012 FY5)", + .params = tuner_temic_4012fy5_params, + .count = ARRAY_SIZE(tuner_temic_4012fy5_params), + }, + [TUNER_TEMIC_4136FY5] = { /* TEMIC NTSC */ + .name = "Temic NTSC (4136 FY5)", + .params = tuner_temic_4136_fy5_params, + .count = ARRAY_SIZE(tuner_temic_4136_fy5_params), + }, + [TUNER_LG_PAL_NEW_TAPC] = { /* LGINNOTEK PAL */ + .name = "LG PAL (newer TAPC series)", + .params = tuner_lg_pal_new_tapc_params, + .count = ARRAY_SIZE(tuner_lg_pal_new_tapc_params), + }, + [TUNER_PHILIPS_FM1216ME_MK3] = { /* Philips PAL */ + .name = "Philips PAL/SECAM multi (FM1216ME MK3)", + .params = tuner_fm1216me_mk3_params, + .count = ARRAY_SIZE(tuner_fm1216me_mk3_params), + }, + [TUNER_LG_NTSC_NEW_TAPC] = { /* LGINNOTEK NTSC */ + .name = "LG NTSC (newer TAPC series)", + .params = tuner_lg_ntsc_new_tapc_params, + .count = ARRAY_SIZE(tuner_lg_ntsc_new_tapc_params), + }, + + /* 40-49 */ + [TUNER_HITACHI_NTSC] = { /* HITACHI NTSC */ + .name = "HITACHI V7-J180AT", + .params = tuner_hitachi_ntsc_params, + .count = ARRAY_SIZE(tuner_hitachi_ntsc_params), + }, + [TUNER_PHILIPS_PAL_MK] = { /* Philips PAL */ + .name = "Philips PAL_MK (FI1216 MK)", + .params = tuner_philips_pal_mk_params, + .count = ARRAY_SIZE(tuner_philips_pal_mk_params), + }, + [TUNER_PHILIPS_FCV1236D] = { /* Philips ATSC */ + .name = "Philips FCV1236D ATSC/NTSC dual in", + .params = tuner_philips_fcv1236d_params, + .count = ARRAY_SIZE(tuner_philips_fcv1236d_params), + .min = 16 * 53.00, + .max = 16 * 803.00, + .stepsize = 62500, + }, + [TUNER_PHILIPS_FM1236_MK3] = { /* Philips NTSC */ + .name = "Philips NTSC MK3 (FM1236MK3 or FM1236/F)", + .params = tuner_fm1236_mk3_params, + .count = ARRAY_SIZE(tuner_fm1236_mk3_params), + }, + [TUNER_PHILIPS_4IN1] = { /* Philips NTSC */ + .name = "Philips 4 in 1 (ATI TV Wonder Pro/Conexant)", + .params = tuner_philips_4in1_params, + .count = ARRAY_SIZE(tuner_philips_4in1_params), + }, + [TUNER_MICROTUNE_4049FM5] = { /* Microtune PAL */ + .name = "Microtune 4049 FM5", + .params = tuner_microtune_4049_fm5_params, + .count = ARRAY_SIZE(tuner_microtune_4049_fm5_params), + }, + [TUNER_PANASONIC_VP27] = { /* Panasonic NTSC */ + .name = "Panasonic VP27s/ENGE4324D", + .params = tuner_panasonic_vp27_params, + .count = ARRAY_SIZE(tuner_panasonic_vp27_params), + }, + [TUNER_LG_NTSC_TAPE] = { /* LGINNOTEK NTSC */ + .name = "LG NTSC (TAPE series)", + .params = tuner_fm1236_mk3_params, + .count = ARRAY_SIZE(tuner_fm1236_mk3_params), + }, + [TUNER_TNF_8831BGFF] = { /* Philips PAL */ + .name = "Tenna TNF 8831 BGFF)", + .params = tuner_tnf_8831bgff_params, + .count = ARRAY_SIZE(tuner_tnf_8831bgff_params), + }, + [TUNER_MICROTUNE_4042FI5] = { /* Microtune NTSC */ + .name = "Microtune 4042 FI5 ATSC/NTSC dual in", + .params = tuner_microtune_4042fi5_params, + .count = ARRAY_SIZE(tuner_microtune_4042fi5_params), + .min = 16 * 57.00, + .max = 16 * 858.00, + .stepsize = 62500, + }, + + /* 50-59 */ + [TUNER_TCL_2002N] = { /* TCL NTSC */ + .name = "TCL 2002N", + .params = tuner_tcl_2002n_params, + .count = ARRAY_SIZE(tuner_tcl_2002n_params), + }, + [TUNER_PHILIPS_FM1256_IH3] = { /* Philips PAL */ + .name = "Philips PAL/SECAM_D (FM 1256 I-H3)", + .params = tuner_philips_fm1256_ih3_params, + .count = ARRAY_SIZE(tuner_philips_fm1256_ih3_params), + }, + [TUNER_THOMSON_DTT7610] = { /* THOMSON ATSC */ + .name = "Thomson DTT 7610 (ATSC/NTSC)", + .params = tuner_thomson_dtt7610_params, + .count = ARRAY_SIZE(tuner_thomson_dtt7610_params), + .min = 16 * 44.00, + .max = 16 * 958.00, + .stepsize = 62500, + }, + [TUNER_PHILIPS_FQ1286] = { /* Philips NTSC */ + .name = "Philips FQ1286", + .params = tuner_philips_fq1286_params, + .count = ARRAY_SIZE(tuner_philips_fq1286_params), + }, + [TUNER_PHILIPS_TDA8290] = { /* Philips PAL|NTSC */ + .name = "Philips/NXP TDA 8290/8295 + 8275/8275A/18271", + /* see tda8290.c for details */ }, + [TUNER_TCL_2002MB] = { /* TCL PAL */ + .name = "TCL 2002MB", + .params = tuner_tcl_2002mb_params, + .count = ARRAY_SIZE(tuner_tcl_2002mb_params), + }, + [TUNER_PHILIPS_FQ1216AME_MK4] = { /* Philips PAL */ + .name = "Philips PAL/SECAM multi (FQ1216AME MK4)", + .params = tuner_philips_fq1216ame_mk4_params, + .count = ARRAY_SIZE(tuner_philips_fq1216ame_mk4_params), + }, + [TUNER_PHILIPS_FQ1236A_MK4] = { /* Philips NTSC */ + .name = "Philips FQ1236A MK4", + .params = tuner_philips_fq1236a_mk4_params, + .count = ARRAY_SIZE(tuner_philips_fq1236a_mk4_params), + }, + [TUNER_YMEC_TVF_8531MF] = { /* Philips NTSC */ + .name = "Ymec TVision TVF-8531MF/8831MF/8731MF", + .params = tuner_ymec_tvf_8531mf_params, + .count = ARRAY_SIZE(tuner_ymec_tvf_8531mf_params), + }, + [TUNER_YMEC_TVF_5533MF] = { /* Philips NTSC */ + .name = "Ymec TVision TVF-5533MF", + .params = tuner_ymec_tvf_5533mf_params, + .count = ARRAY_SIZE(tuner_ymec_tvf_5533mf_params), + }, + + /* 60-69 */ + [TUNER_THOMSON_DTT761X] = { /* THOMSON ATSC */ + /* DTT 7611 7611A 7612 7613 7613A 7614 7615 7615A */ + .name = "Thomson DTT 761X (ATSC/NTSC)", + .params = tuner_thomson_dtt761x_params, + .count = ARRAY_SIZE(tuner_thomson_dtt761x_params), + .min = 16 * 57.00, + .max = 16 * 863.00, + .stepsize = 62500, + .initdata = tua603x_agc103, + }, + [TUNER_TENA_9533_DI] = { /* Philips PAL */ + .name = "Tena TNF9533-D/IF/TNF9533-B/DF", + .params = tuner_tena_9533_di_params, + .count = ARRAY_SIZE(tuner_tena_9533_di_params), + }, + [TUNER_TEA5767] = { /* Philips RADIO */ + .name = "Philips TEA5767HN FM Radio", + /* see tea5767.c for details */ + }, + [TUNER_PHILIPS_FMD1216ME_MK3] = { /* Philips PAL */ + .name = "Philips FMD1216ME MK3 Hybrid Tuner", + .params = tuner_philips_fmd1216me_mk3_params, + .count = ARRAY_SIZE(tuner_philips_fmd1216me_mk3_params), + .min = 16 * 50.87, + .max = 16 * 858.00, + .stepsize = 166667, + .initdata = tua603x_agc112, + .sleepdata = (u8[]){ 4, 0x9c, 0x60, 0x85, 0x54 }, + }, + [TUNER_LG_TDVS_H06XF] = { /* LGINNOTEK ATSC */ + .name = "LG TDVS-H06xF", /* H061F, H062F & H064F */ + .params = tuner_lg_tdvs_h06xf_params, + .count = ARRAY_SIZE(tuner_lg_tdvs_h06xf_params), + .min = 16 * 54.00, + .max = 16 * 863.00, + .stepsize = 62500, + .initdata = tua603x_agc103, + }, + [TUNER_YMEC_TVF66T5_B_DFF] = { /* Philips PAL */ + .name = "Ymec TVF66T5-B/DFF", + .params = tuner_ymec_tvf66t5_b_dff_params, + .count = ARRAY_SIZE(tuner_ymec_tvf66t5_b_dff_params), + }, + [TUNER_LG_TALN] = { /* LGINNOTEK NTSC / PAL / SECAM */ + .name = "LG TALN series", + .params = tuner_lg_taln_params, + .count = ARRAY_SIZE(tuner_lg_taln_params), + }, + [TUNER_PHILIPS_TD1316] = { /* Philips PAL */ + .name = "Philips TD1316 Hybrid Tuner", + .params = tuner_philips_td1316_params, + .count = ARRAY_SIZE(tuner_philips_td1316_params), + .min = 16 * 87.00, + .max = 16 * 895.00, + .stepsize = 166667, + }, + [TUNER_PHILIPS_TUV1236D] = { /* Philips ATSC */ + .name = "Philips TUV1236D ATSC/NTSC dual in", + .params = tuner_tuv1236d_params, + .count = ARRAY_SIZE(tuner_tuv1236d_params), + .min = 16 * 54.00, + .max = 16 * 864.00, + .stepsize = 62500, + }, + [TUNER_TNF_5335MF] = { /* Tenna PAL/NTSC */ + .name = "Tena TNF 5335 and similar models", + .params = tuner_tnf_5335mf_params, + .count = ARRAY_SIZE(tuner_tnf_5335mf_params), + }, + + /* 70-79 */ + [TUNER_SAMSUNG_TCPN_2121P30A] = { /* Samsung NTSC */ + .name = "Samsung TCPN 2121P30A", + .params = tuner_samsung_tcpn_2121p30a_params, + .count = ARRAY_SIZE(tuner_samsung_tcpn_2121p30a_params), + }, + [TUNER_XC2028] = { /* Xceive 2028 */ + .name = "Xceive xc2028/xc3028 tuner", + /* see tuner-xc2028.c for details */ + }, + [TUNER_THOMSON_FE6600] = { /* Thomson PAL / DVB-T */ + .name = "Thomson FE6600", + .params = tuner_thomson_fe6600_params, + .count = ARRAY_SIZE(tuner_thomson_fe6600_params), + .min = 16 * 44.25, + .max = 16 * 858.00, + .stepsize = 166667, + }, + [TUNER_SAMSUNG_TCPG_6121P30A] = { /* Samsung PAL */ + .name = "Samsung TCPG 6121P30A", + .params = tuner_samsung_tcpg_6121p30a_params, + .count = ARRAY_SIZE(tuner_samsung_tcpg_6121p30a_params), + }, + [TUNER_TDA9887] = { /* Philips TDA 9887 IF PLL Demodulator. + This chip is part of some modern tuners */ + .name = "Philips TDA988[5,6,7] IF PLL Demodulator", + /* see tda9887.c for details */ + }, + [TUNER_TEA5761] = { /* Philips RADIO */ + .name = "Philips TEA5761 FM Radio", + /* see tea5767.c for details */ + }, + [TUNER_XC5000] = { /* Xceive 5000 */ + .name = "Xceive 5000 tuner", + /* see xc5000.c for details */ + }, +}; +EXPORT_SYMBOL(tuners); + +unsigned const int tuner_count = ARRAY_SIZE(tuners); +EXPORT_SYMBOL(tuner_count); + +MODULE_DESCRIPTION("Simple tuner device type database"); +MODULE_AUTHOR("Ralph Metzler, Gerd Knorr, Gunther Mayer"); +MODULE_LICENSE("GPL"); diff --git a/linux/drivers/media/common/tuners/tuner-xc2028-types.h b/linux/drivers/media/common/tuners/tuner-xc2028-types.h new file mode 100644 index 000000000..216665c2c --- /dev/null +++ b/linux/drivers/media/common/tuners/tuner-xc2028-types.h @@ -0,0 +1,153 @@ +/* tuner-xc2028_types + * + * This file includes internal tipes to be used inside tuner-xc2028. + * Shouldn't be included outside tuner-xc2028 + * + * Copyright (c) 2007-2008 Mauro Carvalho Chehab (mchehab@infradead.org) + * This code is placed under the terms of the GNU General Public License v2 + */ + +/* xc3028 firmware types */ + +/* BASE firmware should be loaded before any other firmware */ +#define BASE (1<<0) +#define BASE_TYPES (BASE|F8MHZ|MTS|FM|INPUT1|INPUT2|INIT1) + +/* F8MHZ marks BASE firmwares for 8 MHz Bandwidth */ +#define F8MHZ (1<<1) + +/* Multichannel Television Sound (MTS) + Those firmwares are capable of using xc2038 DSP to decode audio and + produce a baseband audio output on some pins of the chip. + There are MTS firmwares for the most used video standards. It should be + required to use MTS firmwares, depending on the way audio is routed into + the bridge chip + */ +#define MTS (1<<2) + +/* FIXME: I have no idea what's the difference between + D2620 and D2633 firmwares + */ +#define D2620 (1<<3) +#define D2633 (1<<4) + +/* DTV firmwares for 6, 7 and 8 MHz + DTV6 - 6MHz - ATSC/DVB-C/DVB-T/ISDB-T/DOCSIS + DTV8 - 8MHz - DVB-C/DVB-T + */ +#define DTV6 (1 << 5) +#define QAM (1 << 6) +#define DTV7 (1<<7) +#define DTV78 (1<<8) +#define DTV8 (1<<9) + +#define DTV_TYPES (D2620|D2633|DTV6|QAM|DTV7|DTV78|DTV8|ATSC) + +/* There's a FM | BASE firmware + FM specific firmware (std=0) */ +#define FM (1<<10) + +#define STD_SPECIFIC_TYPES (MTS|FM|LCD|NOGD) + +/* Applies only for FM firmware + Makes it use RF input 1 (pin #2) instead of input 2 (pin #4) + */ +#define INPUT1 (1<<11) + + +/* LCD firmwares exist only for MTS STD/MN (PAL or NTSC/M) + and for non-MTS STD/MN (PAL, NTSC/M or NTSC/Kr) + There are variants both with and without NOGD + Those firmwares produce better result with LCD displays + */ +#define LCD (1<<12) + +/* NOGD firmwares exist only for MTS STD/MN (PAL or NTSC/M) + and for non-MTS STD/MN (PAL, NTSC/M or NTSC/Kr) + The NOGD firmwares don't have group delay compensation filter + */ +#define NOGD (1<<13) + +/* Old firmwares were broken into init0 and init1 */ +#define INIT1 (1<<14) + +/* SCODE firmware selects particular behaviours */ +#define MONO (1 << 15) +#define ATSC (1 << 16) +#define IF (1 << 17) +#define LG60 (1 << 18) +#define ATI638 (1 << 19) +#define OREN538 (1 << 20) +#define OREN36 (1 << 21) +#define TOYOTA388 (1 << 22) +#define TOYOTA794 (1 << 23) +#define DIBCOM52 (1 << 24) +#define ZARLINK456 (1 << 25) +#define CHINA (1 << 26) +#define F6MHZ (1 << 27) +#define INPUT2 (1 << 28) +#define SCODE (1 << 29) + +/* This flag identifies that the scode table has a new format */ +#define HAS_IF (1 << 30) + +#if 0 +/* The current seek algorithm doesn'use those flags. Instead, this is + currently useful only for debug process, since this is a HINT table + associating an alias to an IF table that can be used by that digital + video standard (in the case of DTV6/7/78/8, QAM and ATSC), or to a + particular demod type + */ +#define SCODE_TYPES (DTV6|QAM|DTV7|DTV78|DTV8|LCD|NOGD|MONO|ATSC|IF| \ + LG60|ATI638|OREN538|OREN36|TOYOTA388|TOYOTA794| \ + DIBCOM52|ZARLINK456|CHINA|F6MHZ|SCODE) +#else +/* There are different scode tables for MTS and non-MTS. + The MTS firmwares support mono only + */ +#define SCODE_TYPES (SCODE | MTS) +#endif + + +/* Newer types not defined on videodev2.h. + The original idea were to move all those types to videodev2.h, but + it seemed overkill, since, with the exception of SECAM/K3, the other + types seem to be autodetected. + It is not clear where secam/k3 is used, nor we have a feedback of this + working or being autodetected by the standard secam firmware. + */ + +#define V4L2_STD_SECAM_K3 (0x04000000) + +/* Audio types */ + +#define V4L2_STD_A2_A (1LL<<32) +#define V4L2_STD_A2_B (1LL<<33) +#define V4L2_STD_NICAM_A (1LL<<34) +#define V4L2_STD_NICAM_B (1LL<<35) +#define V4L2_STD_AM (1LL<<36) +#define V4L2_STD_BTSC (1LL<<37) +#define V4L2_STD_EIAJ (1LL<<38) + +#define V4L2_STD_A2 (V4L2_STD_A2_A | V4L2_STD_A2_B) +#define V4L2_STD_NICAM (V4L2_STD_NICAM_A | V4L2_STD_NICAM_B) + +/* To preserve backward compatibilty, + (std & V4L2_STD_AUDIO) = 0 means that ALL audio stds are supported + */ + +#define V4L2_STD_AUDIO (V4L2_STD_A2 | \ + V4L2_STD_NICAM | \ + V4L2_STD_AM | \ + V4L2_STD_BTSC | \ + V4L2_STD_EIAJ) + +/* Used standards with audio restrictions */ + +#define V4L2_STD_PAL_BG_A2_A (V4L2_STD_PAL_BG | V4L2_STD_A2_A) +#define V4L2_STD_PAL_BG_A2_B (V4L2_STD_PAL_BG | V4L2_STD_A2_B) +#define V4L2_STD_PAL_BG_NICAM_A (V4L2_STD_PAL_BG | V4L2_STD_NICAM_A) +#define V4L2_STD_PAL_BG_NICAM_B (V4L2_STD_PAL_BG | V4L2_STD_NICAM_B) +#define V4L2_STD_PAL_DK_A2 (V4L2_STD_PAL_DK | V4L2_STD_A2) +#define V4L2_STD_PAL_DK_NICAM (V4L2_STD_PAL_DK | V4L2_STD_NICAM) +#define V4L2_STD_SECAM_L_NICAM (V4L2_STD_SECAM_L | V4L2_STD_NICAM) +#define V4L2_STD_SECAM_L_AM (V4L2_STD_SECAM_L | V4L2_STD_AM) diff --git a/linux/drivers/media/common/tuners/tuner-xc2028.c b/linux/drivers/media/common/tuners/tuner-xc2028.c new file mode 100644 index 000000000..3aa81ae99 --- /dev/null +++ b/linux/drivers/media/common/tuners/tuner-xc2028.c @@ -0,0 +1,1274 @@ +/* tuner-xc2028 + * + * Copyright (c) 2007-2008 Mauro Carvalho Chehab (mchehab@infradead.org) + * + * Copyright (c) 2007 Michel Ludwig (michel.ludwig@gmail.com) + * - frontend interface + * + * This code is placed under the terms of the GNU General Public License v2 + */ + +#include +#include +#include +#include +#include +#include +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 16) +#include +#else +#include +#endif +#include "compat.h" +#include "tuner-i2c.h" +#if LINUX_VERSION_CODE < KERNEL_VERSION(2, 5, 0) +#include "i2c-compat.h" +#endif +#include "tuner-xc2028.h" +#include "tuner-xc2028-types.h" + +#include +#include "dvb_frontend.h" + +#if LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 22) +#define strcasecmp(a, b) strnicmp(a, b, sizeof(a)) +#endif + +static int debug; +module_param(debug, int, 0644); +MODULE_PARM_DESC(debug, "enable verbose debug messages"); + +static char audio_std[8]; +module_param_string(audio_std, audio_std, sizeof(audio_std), 0); +MODULE_PARM_DESC(audio_std, + "Audio standard. XC3028 audio decoder explicitly " + "needs to know what audio\n" + "standard is needed for some video standards with audio A2 or NICAM.\n" + "The valid values are:\n" + "A2\n" + "A2/A\n" + "A2/B\n" + "NICAM\n" + "NICAM/A\n" + "NICAM/B\n"); + +static char firmware_name[FIRMWARE_NAME_MAX]; +module_param_string(firmware_name, firmware_name, sizeof(firmware_name), 0); +MODULE_PARM_DESC(firmware_name, "Firmware file name. Allows overriding the " + "default firmware name\n"); + +static LIST_HEAD(xc2028_list); +static DEFINE_MUTEX(xc2028_list_mutex); + +/* struct for storing firmware table */ +struct firmware_description { + unsigned int type; + v4l2_std_id id; + __u16 int_freq; + unsigned char *ptr; + unsigned int size; +}; + +struct firmware_properties { + unsigned int type; + v4l2_std_id id; + v4l2_std_id std_req; + __u16 int_freq; + unsigned int scode_table; + int scode_nr; +}; + +struct xc2028_data { + struct list_head xc2028_list; + struct tuner_i2c_props i2c_props; + int (*tuner_callback) (void *dev, + int command, int arg); + void *video_dev; + int count; + __u32 frequency; + + struct firmware_description *firm; + int firm_size; + __u16 firm_version; + + __u16 hwmodel; + __u16 hwvers; + + struct xc2028_ctrl ctrl; + + struct firmware_properties cur_fw; + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 16) + struct mutex lock; +#else + struct semaphore lock; +#endif +}; + +#define i2c_send(priv, buf, size) ({ \ + int _rc; \ + _rc = tuner_i2c_xfer_send(&priv->i2c_props, buf, size); \ + if (size != _rc) \ + tuner_info("i2c output error: rc = %d (should be %d)\n",\ + _rc, (int)size); \ + _rc; \ +}) + +#define i2c_rcv(priv, buf, size) ({ \ + int _rc; \ + _rc = tuner_i2c_xfer_recv(&priv->i2c_props, buf, size); \ + if (size != _rc) \ + tuner_err("i2c input error: rc = %d (should be %d)\n", \ + _rc, (int)size); \ + _rc; \ +}) + +#define i2c_send_recv(priv, obuf, osize, ibuf, isize) ({ \ + int _rc; \ + _rc = tuner_i2c_xfer_send_recv(&priv->i2c_props, obuf, osize, \ + ibuf, isize); \ + if (isize != _rc) \ + tuner_err("i2c input error: rc = %d (should be %d)\n", \ + _rc, (int)isize); \ + _rc; \ +}) + +#define send_seq(priv, data...) ({ \ + static u8 _val[] = data; \ + int _rc; \ + if (sizeof(_val) != \ + (_rc = tuner_i2c_xfer_send(&priv->i2c_props, \ + _val, sizeof(_val)))) { \ + tuner_err("Error on line %d: %d\n", __LINE__, _rc); \ + } else \ + msleep(10); \ + _rc; \ +}) + +static int xc2028_get_reg(struct xc2028_data *priv, u16 reg, u16 *val) +{ + unsigned char buf[2]; + unsigned char ibuf[2]; + + tuner_dbg("%s %04x called\n", __func__, reg); + + buf[0] = reg >> 8; + buf[1] = (unsigned char) reg; + + if (i2c_send_recv(priv, buf, 2, ibuf, 2) != 2) + return -EIO; + + *val = (ibuf[1]) | (ibuf[0] << 8); + return 0; +} + +#define dump_firm_type(t) dump_firm_type_and_int_freq(t, 0) +static void dump_firm_type_and_int_freq(unsigned int type, u16 int_freq) +{ + if (type & BASE) + printk("BASE "); + if (type & INIT1) + printk("INIT1 "); + if (type & F8MHZ) + printk("F8MHZ "); + if (type & MTS) + printk("MTS "); + if (type & D2620) + printk("D2620 "); + if (type & D2633) + printk("D2633 "); + if (type & DTV6) + printk("DTV6 "); + if (type & QAM) + printk("QAM "); + if (type & DTV7) + printk("DTV7 "); + if (type & DTV78) + printk("DTV78 "); + if (type & DTV8) + printk("DTV8 "); + if (type & FM) + printk("FM "); + if (type & INPUT1) + printk("INPUT1 "); + if (type & LCD) + printk("LCD "); + if (type & NOGD) + printk("NOGD "); + if (type & MONO) + printk("MONO "); + if (type & ATSC) + printk("ATSC "); + if (type & IF) + printk("IF "); + if (type & LG60) + printk("LG60 "); + if (type & ATI638) + printk("ATI638 "); + if (type & OREN538) + printk("OREN538 "); + if (type & OREN36) + printk("OREN36 "); + if (type & TOYOTA388) + printk("TOYOTA388 "); + if (type & TOYOTA794) + printk("TOYOTA794 "); + if (type & DIBCOM52) + printk("DIBCOM52 "); + if (type & ZARLINK456) + printk("ZARLINK456 "); + if (type & CHINA) + printk("CHINA "); + if (type & F6MHZ) + printk("F6MHZ "); + if (type & INPUT2) + printk("INPUT2 "); + if (type & SCODE) + printk("SCODE "); + if (type & HAS_IF) + printk("HAS_IF_%d ", int_freq); +} + +static v4l2_std_id parse_audio_std_option(void) +{ + if (strcasecmp(audio_std, "A2") == 0) + return V4L2_STD_A2; + if (strcasecmp(audio_std, "A2/A") == 0) + return V4L2_STD_A2_A; + if (strcasecmp(audio_std, "A2/B") == 0) + return V4L2_STD_A2_B; + if (strcasecmp(audio_std, "NICAM") == 0) + return V4L2_STD_NICAM; + if (strcasecmp(audio_std, "NICAM/A") == 0) + return V4L2_STD_NICAM_A; + if (strcasecmp(audio_std, "NICAM/B") == 0) + return V4L2_STD_NICAM_B; + + return 0; +} + +static void free_firmware(struct xc2028_data *priv) +{ + int i; + tuner_dbg("%s called\n", __func__); + + if (!priv->firm) + return; + + for (i = 0; i < priv->firm_size; i++) + kfree(priv->firm[i].ptr); + + kfree(priv->firm); + + priv->firm = NULL; + priv->firm_size = 0; + + memset(&priv->cur_fw, 0, sizeof(priv->cur_fw)); +} + +static int load_all_firmwares(struct dvb_frontend *fe) +{ + struct xc2028_data *priv = fe->tuner_priv; + const struct firmware *fw = NULL; + unsigned char *p, *endp; + int rc = 0; + int n, n_array; + char name[33]; + char *fname; + + tuner_dbg("%s called\n", __func__); + + if (!firmware_name[0]) + fname = priv->ctrl.fname; + else + fname = firmware_name; + + tuner_dbg("Reading firmware %s\n", fname); + rc = request_firmware(&fw, fname, &priv->i2c_props.adap->dev); + if (rc < 0) { + if (rc == -ENOENT) + tuner_err("Error: firmware %s not found.\n", + fname); + else + tuner_err("Error %d while requesting firmware %s \n", + rc, fname); + + return rc; + } + p = fw->data; + endp = p + fw->size; + + if (fw->size < sizeof(name) - 1 + 2 + 2) { + tuner_err("Error: firmware file %s has invalid size!\n", + fname); + goto corrupt; + } + + memcpy(name, p, sizeof(name) - 1); + name[sizeof(name) - 1] = 0; + p += sizeof(name) - 1; + + priv->firm_version = le16_to_cpu(*(__u16 *) p); + p += 2; + + n_array = le16_to_cpu(*(__u16 *) p); + p += 2; + + tuner_info("Loading %d firmware images from %s, type: %s, ver %d.%d\n", + n_array, fname, name, + priv->firm_version >> 8, priv->firm_version & 0xff); + + priv->firm = kzalloc(sizeof(*priv->firm) * n_array, GFP_KERNEL); + if (priv->firm == NULL) { + tuner_err("Not enough memory to load firmware file.\n"); + rc = -ENOMEM; + goto err; + } + priv->firm_size = n_array; + + n = -1; + while (p < endp) { + __u32 type, size; + v4l2_std_id id; + __u16 int_freq = 0; + + n++; + if (n >= n_array) { + tuner_err("More firmware images in file than " + "were expected!\n"); + goto corrupt; + } + + /* Checks if there's enough bytes to read */ + if (p + sizeof(type) + sizeof(id) + sizeof(size) > endp) { + tuner_err("Firmware header is incomplete!\n"); + goto corrupt; + } + + type = le32_to_cpu(*(__u32 *) p); + p += sizeof(type); + + id = le64_to_cpu(*(v4l2_std_id *) p); + p += sizeof(id); + + if (type & HAS_IF) { + int_freq = le16_to_cpu(*(__u16 *) p); + p += sizeof(int_freq); + } + + size = le32_to_cpu(*(__u32 *) p); + p += sizeof(size); + + if ((!size) || (size + p > endp)) { + tuner_err("Firmware type "); + dump_firm_type(type); + printk("(%x), id %llx is corrupted " + "(size=%d, expected %d)\n", + type, (unsigned long long)id, + (unsigned)(endp - p), size); + goto corrupt; + } + + priv->firm[n].ptr = kzalloc(size, GFP_KERNEL); + if (priv->firm[n].ptr == NULL) { + tuner_err("Not enough memory to load firmware file.\n"); + rc = -ENOMEM; + goto err; + } + tuner_dbg("Reading firmware type "); + if (debug) { + dump_firm_type_and_int_freq(type, int_freq); + printk("(%x), id %llx, size=%d.\n", + type, (unsigned long long)id, size); + } + + memcpy(priv->firm[n].ptr, p, size); + priv->firm[n].type = type; + priv->firm[n].id = id; + priv->firm[n].size = size; + priv->firm[n].int_freq = int_freq; + + p += size; + } + + if (n + 1 != priv->firm_size) { + tuner_err("Firmware file is incomplete!\n"); + goto corrupt; + } + + goto done; + +corrupt: + rc = -EINVAL; + tuner_err("Error: firmware file is corrupted!\n"); + +err: + tuner_info("Releasing partially loaded firmware file.\n"); + free_firmware(priv); + +done: + release_firmware(fw); + if (rc == 0) + tuner_dbg("Firmware files loaded.\n"); + + return rc; +} + +static int seek_firmware(struct dvb_frontend *fe, unsigned int type, + v4l2_std_id *id) +{ + struct xc2028_data *priv = fe->tuner_priv; + int i, best_i = -1, best_nr_matches = 0; + unsigned int type_mask = 0; + + tuner_dbg("%s called, want type=", __func__); + if (debug) { + dump_firm_type(type); + printk("(%x), id %016llx.\n", type, (unsigned long long)*id); + } + + if (!priv->firm) { + tuner_err("Error! firmware not loaded\n"); + return -EINVAL; + } + + if (((type & ~SCODE) == 0) && (*id == 0)) + *id = V4L2_STD_PAL; + + if (type & BASE) + type_mask = BASE_TYPES; + else if (type & SCODE) { + type &= SCODE_TYPES; + type_mask = SCODE_TYPES &~ HAS_IF; + } else if (type & DTV_TYPES) + type_mask = DTV_TYPES; + else if (type & STD_SPECIFIC_TYPES) + type_mask = STD_SPECIFIC_TYPES; + + type &= type_mask; + + if (!(type & SCODE)) + type_mask = ~0; + + /* Seek for exact match */ + for (i = 0; i < priv->firm_size; i++) { + if ((type == (priv->firm[i].type & type_mask)) && + (*id == priv->firm[i].id)) + goto found; + } + + /* Seek for generic video standard match */ + for (i = 0; i < priv->firm_size; i++) { + v4l2_std_id match_mask; + int nr_matches; + + if (type != (priv->firm[i].type & type_mask)) + continue; + + match_mask = *id & priv->firm[i].id; + if (!match_mask) + continue; + + if ((*id & match_mask) == *id) + goto found; /* Supports all the requested standards */ + + nr_matches = hweight64(match_mask); + if (nr_matches > best_nr_matches) { + best_nr_matches = nr_matches; + best_i = i; + } + } + + if (best_nr_matches > 0) { + tuner_dbg("Selecting best matching firmware (%d bits) for " + "type=", best_nr_matches); + dump_firm_type(type); + printk("(%x), id %016llx:\n", type, (unsigned long long)*id); + i = best_i; + goto found; + } + + /*FIXME: Would make sense to seek for type "hint" match ? */ + + i = -ENOENT; + goto ret; + +found: + *id = priv->firm[i].id; + +ret: + tuner_dbg("%s firmware for type=", (i < 0) ? "Can't find" : "Found"); + if (debug) { + dump_firm_type(type); + printk("(%x), id %016llx.\n", type, (unsigned long long)*id); + } + return i; +} + +static int load_firmware(struct dvb_frontend *fe, unsigned int type, + v4l2_std_id *id) +{ + struct xc2028_data *priv = fe->tuner_priv; + int pos, rc; + unsigned char *p, *endp, buf[priv->ctrl.max_len]; + + tuner_dbg("%s called\n", __func__); + + pos = seek_firmware(fe, type, id); + if (pos < 0) + return pos; + + tuner_info("Loading firmware for type="); + dump_firm_type(priv->firm[pos].type); + printk("(%x), id %016llx.\n", priv->firm[pos].type, + (unsigned long long)*id); + + p = priv->firm[pos].ptr; + endp = p + priv->firm[pos].size; + + while (p < endp) { + __u16 size; + + /* Checks if there's enough bytes to read */ + if (p + sizeof(size) > endp) { + tuner_err("Firmware chunk size is wrong\n"); + return -EINVAL; + } + + size = le16_to_cpu(*(__u16 *) p); + p += sizeof(size); + + if (size == 0xffff) + return 0; + + if (!size) { + /* Special callback command received */ + rc = priv->tuner_callback(priv->video_dev, + XC2028_TUNER_RESET, 0); + if (rc < 0) { + tuner_err("Error at RESET code %d\n", + (*p) & 0x7f); + return -EINVAL; + } + continue; + } + if (size >= 0xff00) { + switch (size) { + case 0xff00: + rc = priv->tuner_callback(priv->video_dev, + XC2028_RESET_CLK, 0); + if (rc < 0) { + tuner_err("Error at RESET code %d\n", + (*p) & 0x7f); + return -EINVAL; + } + break; + default: + tuner_info("Invalid RESET code %d\n", + size & 0x7f); + return -EINVAL; + + } + continue; + } + + /* Checks for a sleep command */ + if (size & 0x8000) { + msleep(size & 0x7fff); + continue; + } + + if ((size + p > endp)) { + tuner_err("missing bytes: need %d, have %d\n", + size, (int)(endp - p)); + return -EINVAL; + } + + buf[0] = *p; + p++; + size--; + + /* Sends message chunks */ + while (size > 0) { + int len = (size < priv->ctrl.max_len - 1) ? + size : priv->ctrl.max_len - 1; + + memcpy(buf + 1, p, len); + + rc = i2c_send(priv, buf, len + 1); + if (rc < 0) { + tuner_err("%d returned from send\n", rc); + return -EINVAL; + } + + p += len; + size -= len; + } + } + return 0; +} + +static int load_scode(struct dvb_frontend *fe, unsigned int type, + v4l2_std_id *id, __u16 int_freq, int scode) +{ + struct xc2028_data *priv = fe->tuner_priv; + int pos, rc; + unsigned char *p; + + tuner_dbg("%s called\n", __func__); + + if (!int_freq) { + pos = seek_firmware(fe, type, id); + if (pos < 0) + return pos; + } else { + for (pos = 0; pos < priv->firm_size; pos++) { + if ((priv->firm[pos].int_freq == int_freq) && + (priv->firm[pos].type & HAS_IF)) + break; + } + if (pos == priv->firm_size) + return -ENOENT; + } + + p = priv->firm[pos].ptr; + + if (priv->firm[pos].type & HAS_IF) { + if (priv->firm[pos].size != 12 * 16 || scode >= 16) + return -EINVAL; + p += 12 * scode; + } else { + /* 16 SCODE entries per file; each SCODE entry is 12 bytes and + * has a 2-byte size header in the firmware format. */ + if (priv->firm[pos].size != 14 * 16 || scode >= 16 || + le16_to_cpu(*(__u16 *)(p + 14 * scode)) != 12) + return -EINVAL; + p += 14 * scode + 2; + } + + tuner_info("Loading SCODE for type="); + dump_firm_type_and_int_freq(priv->firm[pos].type, + priv->firm[pos].int_freq); + printk("(%x), id %016llx.\n", priv->firm[pos].type, + (unsigned long long)*id); + + if (priv->firm_version < 0x0202) + rc = send_seq(priv, {0x20, 0x00, 0x00, 0x00}); + else + rc = send_seq(priv, {0xa0, 0x00, 0x00, 0x00}); + if (rc < 0) + return -EIO; + + rc = i2c_send(priv, p, 12); + if (rc < 0) + return -EIO; + + rc = send_seq(priv, {0x00, 0x8c}); + if (rc < 0) + return -EIO; + + return 0; +} + +static int check_firmware(struct dvb_frontend *fe, unsigned int type, + v4l2_std_id std, __u16 int_freq) +{ + struct xc2028_data *priv = fe->tuner_priv; + struct firmware_properties new_fw; + int rc = 0, is_retry = 0; + u16 version, hwmodel; + v4l2_std_id std0; + + tuner_dbg("%s called\n", __func__); + + if (!priv->firm) { + if (!priv->ctrl.fname) { + tuner_info("xc2028/3028 firmware name not set!\n"); + return -EINVAL; + } + + rc = load_all_firmwares(fe); + if (rc < 0) + return rc; + } + + if (priv->ctrl.mts && !(type & FM)) + type |= MTS; + +retry: + new_fw.type = type; + new_fw.id = std; + new_fw.std_req = std; + new_fw.scode_table = SCODE | priv->ctrl.scode_table; + new_fw.scode_nr = 0; + new_fw.int_freq = int_freq; + + tuner_dbg("checking firmware, user requested type="); + if (debug) { + dump_firm_type(new_fw.type); + printk("(%x), id %016llx, ", new_fw.type, + (unsigned long long)new_fw.std_req); + if (!int_freq) { + printk("scode_tbl "); + dump_firm_type(priv->ctrl.scode_table); + printk("(%x), ", priv->ctrl.scode_table); + } else + printk("int_freq %d, ", new_fw.int_freq); + printk("scode_nr %d\n", new_fw.scode_nr); + } + + /* No need to reload base firmware if it matches */ + if (((BASE | new_fw.type) & BASE_TYPES) == + (priv->cur_fw.type & BASE_TYPES)) { + tuner_dbg("BASE firmware not changed.\n"); + goto skip_base; + } + + /* Updating BASE - forget about all currently loaded firmware */ + memset(&priv->cur_fw, 0, sizeof(priv->cur_fw)); + + /* Reset is needed before loading firmware */ + rc = priv->tuner_callback(priv->video_dev, + XC2028_TUNER_RESET, 0); + if (rc < 0) + goto fail; + + /* BASE firmwares are all std0 */ + std0 = 0; + rc = load_firmware(fe, BASE | new_fw.type, &std0); + if (rc < 0) { + tuner_err("Error %d while loading base firmware\n", + rc); + goto fail; + } + + /* Load INIT1, if needed */ + tuner_dbg("Load init1 firmware, if exists\n"); + + rc = load_firmware(fe, BASE | INIT1 | new_fw.type, &std0); + if (rc == -ENOENT) + rc = load_firmware(fe, (BASE | INIT1 | new_fw.type) & ~F8MHZ, + &std0); + if (rc < 0 && rc != -ENOENT) { + tuner_err("Error %d while loading init1 firmware\n", + rc); + goto fail; + } + +skip_base: + /* + * No need to reload standard specific firmware if base firmware + * was not reloaded and requested video standards have not changed. + */ + if (priv->cur_fw.type == (BASE | new_fw.type) && + priv->cur_fw.std_req == std) { + tuner_dbg("Std-specific firmware already loaded.\n"); + goto skip_std_specific; + } + + /* Reloading std-specific firmware forces a SCODE update */ + priv->cur_fw.scode_table = 0; + + rc = load_firmware(fe, new_fw.type, &new_fw.id); + if (rc == -ENOENT) + rc = load_firmware(fe, new_fw.type & ~F8MHZ, &new_fw.id); + + if (rc < 0) + goto fail; + +skip_std_specific: + if (priv->cur_fw.scode_table == new_fw.scode_table && + priv->cur_fw.scode_nr == new_fw.scode_nr) { + tuner_dbg("SCODE firmware already loaded.\n"); + goto check_device; + } + + if (new_fw.type & FM) + goto check_device; + + /* Load SCODE firmware, if exists */ + tuner_dbg("Trying to load scode %d\n", new_fw.scode_nr); + + rc = load_scode(fe, new_fw.type | new_fw.scode_table, &new_fw.id, + new_fw.int_freq, new_fw.scode_nr); + +check_device: + if (xc2028_get_reg(priv, 0x0004, &version) < 0 || + xc2028_get_reg(priv, 0x0008, &hwmodel) < 0) { + tuner_err("Unable to read tuner registers.\n"); + goto fail; + } + + tuner_dbg("Device is Xceive %d version %d.%d, " + "firmware version %d.%d\n", + hwmodel, (version & 0xf000) >> 12, (version & 0xf00) >> 8, + (version & 0xf0) >> 4, version & 0xf); + + /* Check firmware version against what we downloaded. */ + if (priv->firm_version != ((version & 0xf0) << 4 | (version & 0x0f))) { + tuner_err("Incorrect readback of firmware version.\n"); + goto fail; + } + + /* Check that the tuner hardware model remains consistent over time. */ + if (priv->hwmodel == 0 && (hwmodel == 2028 || hwmodel == 3028)) { + priv->hwmodel = hwmodel; + priv->hwvers = version & 0xff00; + } else if (priv->hwmodel == 0 || priv->hwmodel != hwmodel || + priv->hwvers != (version & 0xff00)) { + tuner_err("Read invalid device hardware information - tuner " + "hung?\n"); + goto fail; + } + + memcpy(&priv->cur_fw, &new_fw, sizeof(priv->cur_fw)); + + /* + * By setting BASE in cur_fw.type only after successfully loading all + * firmwares, we can: + * 1. Identify that BASE firmware with type=0 has been loaded; + * 2. Tell whether BASE firmware was just changed the next time through. + */ + priv->cur_fw.type |= BASE; + + return 0; + +fail: + memset(&priv->cur_fw, 0, sizeof(priv->cur_fw)); + if (!is_retry) { + msleep(50); + is_retry = 1; + tuner_dbg("Retrying firmware load\n"); + goto retry; + } + + if (rc == -ENOENT) + rc = -EINVAL; + return rc; +} + +static int xc2028_signal(struct dvb_frontend *fe, u16 *strength) +{ + struct xc2028_data *priv = fe->tuner_priv; + u16 frq_lock, signal = 0; + int rc; + + tuner_dbg("%s called\n", __func__); + + mutex_lock(&priv->lock); + + /* Sync Lock Indicator */ + rc = xc2028_get_reg(priv, 0x0002, &frq_lock); + if (rc < 0) + goto ret; + + /* Frequency is locked */ + if (frq_lock == 1) + signal = 32768; + + /* Get SNR of the video signal */ + rc = xc2028_get_reg(priv, 0x0040, &signal); + if (rc < 0) + goto ret; + + /* Use both frq_lock and signal to generate the result */ + signal = signal || ((signal & 0x07) << 12); + +ret: + mutex_unlock(&priv->lock); + + *strength = signal; + + tuner_dbg("signal strength is %d\n", signal); + + return rc; +} + +#define DIV 15625 + +static int generic_set_freq(struct dvb_frontend *fe, u32 freq /* in HZ */, + enum tuner_mode new_mode, + unsigned int type, + v4l2_std_id std, + u16 int_freq) +{ + struct xc2028_data *priv = fe->tuner_priv; + int rc = -EINVAL; + unsigned char buf[4]; + u32 div, offset = 0; + + tuner_dbg("%s called\n", __func__); + + mutex_lock(&priv->lock); + + tuner_dbg("should set frequency %d kHz\n", freq / 1000); + + if (check_firmware(fe, type, std, int_freq) < 0) + goto ret; + + /* On some cases xc2028 can disable video output, if + * very weak signals are received. By sending a soft + * reset, this is re-enabled. So, it is better to always + * send a soft reset before changing channels, to be sure + * that xc2028 will be in a safe state. + * Maybe this might also be needed for DTV. + */ + if (new_mode == T_ANALOG_TV) { + rc = send_seq(priv, {0x00, 0x00}); + } else if (priv->cur_fw.type & ATSC) { + offset = 1750000; + } else { + offset = 2750000; + /* + * We must adjust the offset by 500kHz in two cases in order + * to correctly center the IF output: + * 1) When the ZARLINK456 or DIBCOM52 tables were explicitly + * selected and a 7MHz channel is tuned; + * 2) When tuning a VHF channel with DTV78 firmware. + */ + if (((priv->cur_fw.type & DTV7) && + (priv->cur_fw.scode_table & (ZARLINK456 | DIBCOM52))) || + ((priv->cur_fw.type & DTV78) && freq < 470000000)) + offset -= 500000; + } + + div = (freq - offset + DIV / 2) / DIV; + + /* CMD= Set frequency */ + if (priv->firm_version < 0x0202) + rc = send_seq(priv, {0x00, 0x02, 0x00, 0x00}); + else + rc = send_seq(priv, {0x80, 0x02, 0x00, 0x00}); + if (rc < 0) + goto ret; + + /* Return code shouldn't be checked. + The reset CLK is needed only with tm6000. + Driver should work fine even if this fails. + */ + priv->tuner_callback(priv->video_dev, XC2028_RESET_CLK, 1); + + msleep(10); + + buf[0] = 0xff & (div >> 24); + buf[1] = 0xff & (div >> 16); + buf[2] = 0xff & (div >> 8); + buf[3] = 0xff & (div); + + rc = i2c_send(priv, buf, sizeof(buf)); + if (rc < 0) + goto ret; + msleep(100); + + priv->frequency = freq; + + tuner_dbg("divisor= %02x %02x %02x %02x (freq=%d.%03d)\n", + buf[0], buf[1], buf[2], buf[3], + freq / 1000000, (freq % 1000000) / 1000); + + rc = 0; + +ret: + mutex_unlock(&priv->lock); + + return rc; +} + +static int xc2028_set_analog_freq(struct dvb_frontend *fe, + struct analog_parameters *p) +{ + struct xc2028_data *priv = fe->tuner_priv; + unsigned int type=0; + + tuner_dbg("%s called\n", __func__); + + if (p->mode == V4L2_TUNER_RADIO) { + type |= FM; + if (priv->ctrl.input1) + type |= INPUT1; + return generic_set_freq(fe, (625l * p->frequency) / 10, + T_ANALOG_TV, type, 0, 0); + } + + /* if std is not defined, choose one */ + if (!p->std) + p->std = V4L2_STD_MN; + + /* PAL/M, PAL/N, PAL/Nc and NTSC variants should use 6MHz firmware */ + if (!(p->std & V4L2_STD_MN)) + type |= F8MHZ; + + /* Add audio hack to std mask */ + p->std |= parse_audio_std_option(); + + return generic_set_freq(fe, 62500l * p->frequency, + T_ANALOG_TV, type, p->std, 0); +} + +static int xc2028_set_params(struct dvb_frontend *fe, + struct dvb_frontend_parameters *p) +{ + struct xc2028_data *priv = fe->tuner_priv; + unsigned int type=0; + fe_bandwidth_t bw = BANDWIDTH_8_MHZ; + u16 demod = 0; + + tuner_dbg("%s called\n", __func__); + + if (priv->ctrl.d2633) + type |= D2633; + else + type |= D2620; + + switch(fe->ops.info.type) { + case FE_OFDM: + bw = p->u.ofdm.bandwidth; + break; + case FE_QAM: + tuner_info("WARN: There are some reports that " + "QAM 6 MHz doesn't work.\n" + "If this works for you, please report by " + "e-mail to: v4l-dvb-maintainer@linuxtv.org\n"); + bw = BANDWIDTH_6_MHZ; + type |= QAM; + break; + case FE_ATSC: + bw = BANDWIDTH_6_MHZ; + /* The only ATSC firmware (at least on v2.7) is D2633, + so overrides ctrl->d2633 */ + type |= ATSC| D2633; + type &= ~D2620; + break; + /* DVB-S is not supported */ + default: + return -EINVAL; + } + + switch (bw) { + case BANDWIDTH_8_MHZ: + if (p->frequency < 470000000) + priv->ctrl.vhfbw7 = 0; + else + priv->ctrl.uhfbw8 = 1; + type |= (priv->ctrl.vhfbw7 && priv->ctrl.uhfbw8) ? DTV78 : DTV8; + type |= F8MHZ; + break; + case BANDWIDTH_7_MHZ: + if (p->frequency < 470000000) + priv->ctrl.vhfbw7 = 1; + else + priv->ctrl.uhfbw8 = 0; + type |= (priv->ctrl.vhfbw7 && priv->ctrl.uhfbw8) ? DTV78 : DTV7; + type |= F8MHZ; + break; + case BANDWIDTH_6_MHZ: + type |= DTV6; + priv->ctrl.vhfbw7 = 0; + priv->ctrl.uhfbw8 = 0; + break; + default: + tuner_err("error: bandwidth not supported.\n"); + }; + + /* All S-code tables need a 200kHz shift */ + if (priv->ctrl.demod) + demod = priv->ctrl.demod + 200; + + return generic_set_freq(fe, p->frequency, + T_DIGITAL_TV, type, 0, demod); +} + +#if 0 +/* This is needed at sleep (S1/S3), but not at fe_standby. Otherwise, + firmware will be loaded on every open() + */ +static int xc2028_sleep(struct dvb_frontend *fe) +{ + struct xc2028_data *priv = fe->tuner_priv; + int rc = 0; + + tuner_dbg("%s called\n", __func__); + + mutex_lock(&priv->lock); + + if (priv->firm_version < 0x0202) + rc = send_seq(priv, {0x00, 0x08, 0x00, 0x00}); + else + rc = send_seq(priv, {0x80, 0x08, 0x00, 0x00}); + + priv->cur_fw.type = 0; /* need firmware reload */ + + mutex_unlock(&priv->lock); + + return rc; +} +#endif + +static int xc2028_dvb_release(struct dvb_frontend *fe) +{ + struct xc2028_data *priv = fe->tuner_priv; + + tuner_dbg("%s called\n", __func__); + + mutex_lock(&xc2028_list_mutex); + + priv->count--; + + if (!priv->count) { + list_del(&priv->xc2028_list); + + kfree(priv->ctrl.fname); + + free_firmware(priv); + kfree(priv); + fe->tuner_priv = NULL; + } + + mutex_unlock(&xc2028_list_mutex); + + return 0; +} + +static int xc2028_get_frequency(struct dvb_frontend *fe, u32 *frequency) +{ + struct xc2028_data *priv = fe->tuner_priv; + + tuner_dbg("%s called\n", __func__); + + *frequency = priv->frequency; + + return 0; +} + +static int xc2028_set_config(struct dvb_frontend *fe, void *priv_cfg) +{ + struct xc2028_data *priv = fe->tuner_priv; + struct xc2028_ctrl *p = priv_cfg; + int rc = 0; + + tuner_dbg("%s called\n", __func__); + + mutex_lock(&priv->lock); + + memcpy(&priv->ctrl, p, sizeof(priv->ctrl)); + if (priv->ctrl.max_len < 9) + priv->ctrl.max_len = 13; + + if (p->fname) { + if (priv->ctrl.fname && strcmp(p->fname, priv->ctrl.fname)) { + kfree(priv->ctrl.fname); + free_firmware(priv); + } + + priv->ctrl.fname = kstrdup(p->fname, GFP_KERNEL); + if (priv->ctrl.fname == NULL) + rc = -ENOMEM; + } + + mutex_unlock(&priv->lock); + + return rc; +} + +static const struct dvb_tuner_ops xc2028_dvb_tuner_ops = { + .info = { + .name = "Xceive XC3028", + .frequency_min = 42000000, + .frequency_max = 864000000, + .frequency_step = 50000, + }, + + .set_config = xc2028_set_config, + .set_analog_params = xc2028_set_analog_freq, + .release = xc2028_dvb_release, + .get_frequency = xc2028_get_frequency, + .get_rf_strength = xc2028_signal, + .set_params = xc2028_set_params, +#if 0 + .sleep = xc2028_sleep, +#endif +#if 0 + int (*get_bandwidth)(struct dvb_frontend *fe, u32 *bandwidth); + int (*get_status)(struct dvb_frontend *fe, u32 *status); +#endif +}; + +struct dvb_frontend *xc2028_attach(struct dvb_frontend *fe, + struct xc2028_config *cfg) +{ + struct xc2028_data *priv; + void *video_dev; + + if (debug) + printk(KERN_DEBUG "xc2028: Xcv2028/3028 init called!\n"); + + if (NULL == cfg) + return NULL; + + if (!fe) { + printk(KERN_ERR "xc2028: No frontend!\n"); + return NULL; + } + + video_dev = cfg->i2c_adap->algo_data; + + if (debug) + printk(KERN_DEBUG "xc2028: video_dev =%p\n", video_dev); + + mutex_lock(&xc2028_list_mutex); + + list_for_each_entry(priv, &xc2028_list, xc2028_list) { + if (&priv->i2c_props.adap->dev == &cfg->i2c_adap->dev) { + video_dev = NULL; + if (debug) + printk(KERN_DEBUG "xc2028: reusing device\n"); + + break; + } + } + + if (video_dev) { + priv = kzalloc(sizeof(*priv), GFP_KERNEL); + if (priv == NULL) { + mutex_unlock(&xc2028_list_mutex); + return NULL; + } + + priv->i2c_props.addr = cfg->i2c_addr; + priv->i2c_props.adap = cfg->i2c_adap; + priv->i2c_props.name = "xc2028"; + + priv->video_dev = video_dev; + priv->tuner_callback = cfg->callback; + priv->ctrl.max_len = 13; + + mutex_init(&priv->lock); + + list_add_tail(&priv->xc2028_list, &xc2028_list); + } + + fe->tuner_priv = priv; + priv->count++; + + if (debug) + printk(KERN_DEBUG "xc2028: usage count is %i\n", priv->count); + + memcpy(&fe->ops.tuner_ops, &xc2028_dvb_tuner_ops, + sizeof(xc2028_dvb_tuner_ops)); + + tuner_info("type set to %s\n", "XCeive xc2028/xc3028 tuner"); + + if (cfg->ctrl) + xc2028_set_config(fe, cfg->ctrl); + + mutex_unlock(&xc2028_list_mutex); + + return fe; +} + +EXPORT_SYMBOL(xc2028_attach); + +MODULE_DESCRIPTION("Xceive xc2028/xc3028 tuner driver"); +MODULE_AUTHOR("Michel Ludwig "); +MODULE_AUTHOR("Mauro Carvalho Chehab "); +MODULE_LICENSE("GPL"); diff --git a/linux/drivers/media/common/tuners/tuner-xc2028.h b/linux/drivers/media/common/tuners/tuner-xc2028.h new file mode 100644 index 000000000..fc2f132a5 --- /dev/null +++ b/linux/drivers/media/common/tuners/tuner-xc2028.h @@ -0,0 +1,63 @@ +/* tuner-xc2028 + * + * Copyright (c) 2007-2008 Mauro Carvalho Chehab (mchehab@infradead.org) + * This code is placed under the terms of the GNU General Public License v2 + */ + +#ifndef __TUNER_XC2028_H__ +#define __TUNER_XC2028_H__ + +#include "dvb_frontend.h" + +#define XC2028_DEFAULT_FIRMWARE "xc3028-v27.fw" + +/* Dmoduler IF (kHz) */ +#define XC3028_FE_DEFAULT 0 /* Don't load SCODE */ +#define XC3028_FE_LG60 6000 +#define XC3028_FE_ATI638 6380 +#define XC3028_FE_OREN538 5380 +#define XC3028_FE_OREN36 3600 +#define XC3028_FE_TOYOTA388 3880 +#define XC3028_FE_TOYOTA794 7940 +#define XC3028_FE_DIBCOM52 5200 +#define XC3028_FE_ZARLINK456 4560 +#define XC3028_FE_CHINA 5200 + +struct xc2028_ctrl { + char *fname; + int max_len; + unsigned int scode_table; + unsigned int mts :1; + unsigned int d2633 :1; + unsigned int input1:1; + unsigned int vhfbw7:1; + unsigned int uhfbw8:1; + unsigned int demod; +}; + +struct xc2028_config { + struct i2c_adapter *i2c_adap; + u8 i2c_addr; + void *video_dev; + struct xc2028_ctrl *ctrl; + int (*callback) (void *dev, int command, int arg); +}; + +/* xc2028 commands for callback */ +#define XC2028_TUNER_RESET 0 +#define XC2028_RESET_CLK 1 + +#if defined(CONFIG_TUNER_XC2028) || (defined(CONFIG_TUNER_XC2028_MODULE) && defined(MODULE)) +extern struct dvb_frontend *xc2028_attach(struct dvb_frontend *fe, + struct xc2028_config *cfg); +#else +static inline struct dvb_frontend *xc2028_attach(struct dvb_frontend *fe, + struct xc2028_config *cfg) +{ + printk(KERN_INFO "%s: not probed - driver disabled by Kconfig\n", + __func__); + return NULL; +} +#endif + +#endif /* __TUNER_XC2028_H__ */ diff --git a/linux/drivers/media/common/tuners/xc5000.c b/linux/drivers/media/common/tuners/xc5000.c new file mode 100644 index 000000000..c832f39ab --- /dev/null +++ b/linux/drivers/media/common/tuners/xc5000.c @@ -0,0 +1,983 @@ +/* + * Driver for Xceive XC5000 "QAM/8VSB single chip tuner" + * + * Copyright (c) 2007 Xceive Corporation + * Copyright (c) 2007 Steven Toth + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include +#include +#include +#include +#include +#include + +#include "dvb_frontend.h" + +#include "xc5000.h" +#include "xc5000_priv.h" + +static int debug; +module_param(debug, int, 0644); +MODULE_PARM_DESC(debug, "Turn on/off debugging (default:off)."); + +#define dprintk(level,fmt, arg...) if (debug >= level) \ + printk(KERN_INFO "%s: " fmt, "xc5000", ## arg) + +#define XC5000_DEFAULT_FIRMWARE "dvb-fe-xc5000-1.1.fw" +#define XC5000_DEFAULT_FIRMWARE_SIZE 12332 + +/* Misc Defines */ +#define MAX_TV_STANDARD 23 +#define XC_MAX_I2C_WRITE_LENGTH 64 + +/* Signal Types */ +#define XC_RF_MODE_AIR 0 +#define XC_RF_MODE_CABLE 1 + +/* Result codes */ +#define XC_RESULT_SUCCESS 0 +#define XC_RESULT_RESET_FAILURE 1 +#define XC_RESULT_I2C_WRITE_FAILURE 2 +#define XC_RESULT_I2C_READ_FAILURE 3 +#define XC_RESULT_OUT_OF_RANGE 5 + +/* Product id */ +#define XC_PRODUCT_ID_FW_NOT_LOADED 0x2000 +#define XC_PRODUCT_ID_FW_LOADED 0x1388 + +/* Registers */ +#define XREG_INIT 0x00 +#define XREG_VIDEO_MODE 0x01 +#define XREG_AUDIO_MODE 0x02 +#define XREG_RF_FREQ 0x03 +#define XREG_D_CODE 0x04 +#define XREG_IF_OUT 0x05 +#define XREG_SEEK_MODE 0x07 +#define XREG_POWER_DOWN 0x0A +#define XREG_SIGNALSOURCE 0x0D /* 0=Air, 1=Cable */ +#define XREG_SMOOTHEDCVBS 0x0E +#define XREG_XTALFREQ 0x0F +#define XREG_FINERFFREQ 0x10 +#define XREG_DDIMODE 0x11 + +#define XREG_ADC_ENV 0x00 +#define XREG_QUALITY 0x01 +#define XREG_FRAME_LINES 0x02 +#define XREG_HSYNC_FREQ 0x03 +#define XREG_LOCK 0x04 +#define XREG_FREQ_ERROR 0x05 +#define XREG_SNR 0x06 +#define XREG_VERSION 0x07 +#define XREG_PRODUCT_ID 0x08 +#define XREG_BUSY 0x09 + +/* + Basic firmware description. This will remain with + the driver for documentation purposes. + + This represents an I2C firmware file encoded as a + string of unsigned char. Format is as follows: + + char[0 ]=len0_MSB -> len = len_MSB * 256 + len_LSB + char[1 ]=len0_LSB -> length of first write transaction + char[2 ]=data0 -> first byte to be sent + char[3 ]=data1 + char[4 ]=data2 + char[ ]=... + char[M ]=dataN -> last byte to be sent + char[M+1]=len1_MSB -> len = len_MSB * 256 + len_LSB + char[M+2]=len1_LSB -> length of second write transaction + char[M+3]=data0 + char[M+4]=data1 + ... + etc. + + The [len] value should be interpreted as follows: + + len= len_MSB _ len_LSB + len=1111_1111_1111_1111 : End of I2C_SEQUENCE + len=0000_0000_0000_0000 : Reset command: Do hardware reset + len=0NNN_NNNN_NNNN_NNNN : Normal transaction: number of bytes = {1:32767) + len=1WWW_WWWW_WWWW_WWWW : Wait command: wait for {1:32767} ms + + For the RESET and WAIT commands, the two following bytes will contain + immediately the length of the following transaction. + +*/ +typedef struct { + char *Name; + u16 AudioMode; + u16 VideoMode; +} XC_TV_STANDARD; + +/* Tuner standards */ +#define MN_NTSC_PAL_BTSC 0 +#define MN_NTSC_PAL_A2 1 +#define MN_NTSC_PAL_EIAJ 2 +#define MN_NTSC_PAL_Mono 3 +#define BG_PAL_A2 4 +#define BG_PAL_NICAM 5 +#define BG_PAL_MONO 6 +#define I_PAL_NICAM 7 +#define I_PAL_NICAM_MONO 8 +#define DK_PAL_A2 9 +#define DK_PAL_NICAM 10 +#define DK_PAL_MONO 11 +#define DK_SECAM_A2DK1 12 +#define DK_SECAM_A2LDK3 13 +#define DK_SECAM_A2MONO 14 +#define L_SECAM_NICAM 15 +#define LC_SECAM_NICAM 16 +#define DTV6 17 +#define DTV8 18 +#define DTV7_8 19 +#define DTV7 20 +#define FM_Radio_INPUT2 21 +#define FM_Radio_INPUT1 22 + +static XC_TV_STANDARD XC5000_Standard[MAX_TV_STANDARD] = { + {"M/N-NTSC/PAL-BTSC", 0x0400, 0x8020}, + {"M/N-NTSC/PAL-A2", 0x0600, 0x8020}, + {"M/N-NTSC/PAL-EIAJ", 0x0440, 0x8020}, + {"M/N-NTSC/PAL-Mono", 0x0478, 0x8020}, + {"B/G-PAL-A2", 0x0A00, 0x8049}, + {"B/G-PAL-NICAM", 0x0C04, 0x8049}, + {"B/G-PAL-MONO", 0x0878, 0x8059}, + {"I-PAL-NICAM", 0x1080, 0x8009}, + {"I-PAL-NICAM-MONO", 0x0E78, 0x8009}, + {"D/K-PAL-A2", 0x1600, 0x8009}, + {"D/K-PAL-NICAM", 0x0E80, 0x8009}, + {"D/K-PAL-MONO", 0x1478, 0x8009}, + {"D/K-SECAM-A2 DK1", 0x1200, 0x8009}, + {"D/K-SECAM-A2 L/DK3",0x0E00, 0x8009}, + {"D/K-SECAM-A2 MONO", 0x1478, 0x8009}, + {"L-SECAM-NICAM", 0x8E82, 0x0009}, + {"L'-SECAM-NICAM", 0x8E82, 0x4009}, + {"DTV6", 0x00C0, 0x8002}, + {"DTV8", 0x00C0, 0x800B}, + {"DTV7/8", 0x00C0, 0x801B}, + {"DTV7", 0x00C0, 0x8007}, + {"FM Radio-INPUT2", 0x9802, 0x9002}, + {"FM Radio-INPUT1", 0x0208, 0x9002} +}; + +static int xc5000_writeregs(struct xc5000_priv *priv, u8 *buf, u8 len); +static int xc5000_readregs(struct xc5000_priv *priv, u8 *buf, u8 len); +static void xc5000_TunerReset(struct dvb_frontend *fe); + +static int xc_send_i2c_data(struct xc5000_priv *priv, u8 *buf, int len) +{ + return xc5000_writeregs(priv, buf, len) + ? XC_RESULT_I2C_WRITE_FAILURE : XC_RESULT_SUCCESS; +} + +static int xc_read_i2c_data(struct xc5000_priv *priv, u8 *buf, int len) +{ + return xc5000_readregs(priv, buf, len) + ? XC_RESULT_I2C_READ_FAILURE : XC_RESULT_SUCCESS; +} + +static int xc_reset(struct dvb_frontend *fe) +{ + xc5000_TunerReset(fe); + return XC_RESULT_SUCCESS; +} + +static void xc_wait(int wait_ms) +{ + msleep(wait_ms); +} + +static void xc5000_TunerReset(struct dvb_frontend *fe) +{ + struct xc5000_priv *priv = fe->tuner_priv; + int ret; + + dprintk(1, "%s()\n", __func__); + + if (priv->cfg->tuner_callback) { + ret = priv->cfg->tuner_callback(priv->cfg->priv, + XC5000_TUNER_RESET, 0); + if (ret) + printk(KERN_ERR "xc5000: reset failed\n"); + } else + printk(KERN_ERR "xc5000: no tuner reset callback function, fatal\n"); +} + +static int xc_write_reg(struct xc5000_priv *priv, u16 regAddr, u16 i2cData) +{ + u8 buf[4]; + int WatchDogTimer = 5; + int result; + + buf[0] = (regAddr >> 8) & 0xFF; + buf[1] = regAddr & 0xFF; + buf[2] = (i2cData >> 8) & 0xFF; + buf[3] = i2cData & 0xFF; + result = xc_send_i2c_data(priv, buf, 4); + if (result == XC_RESULT_SUCCESS) { + /* wait for busy flag to clear */ + while ((WatchDogTimer > 0) && (result == XC_RESULT_SUCCESS)) { + buf[0] = 0; + buf[1] = XREG_BUSY; + + result = xc_send_i2c_data(priv, buf, 2); + if (result == XC_RESULT_SUCCESS) { + result = xc_read_i2c_data(priv, buf, 2); + if (result == XC_RESULT_SUCCESS) { + if ((buf[0] == 0) && (buf[1] == 0)) { + /* busy flag cleared */ + break; + } else { + xc_wait(100); /* wait 5 ms */ + WatchDogTimer--; + } + } + } + } + } + if (WatchDogTimer < 0) + result = XC_RESULT_I2C_WRITE_FAILURE; + + return result; +} + +static int xc_read_reg(struct xc5000_priv *priv, u16 regAddr, u16 *i2cData) +{ + u8 buf[2]; + int result; + + buf[0] = (regAddr >> 8) & 0xFF; + buf[1] = regAddr & 0xFF; + result = xc_send_i2c_data(priv, buf, 2); + if (result != XC_RESULT_SUCCESS) + return result; + + result = xc_read_i2c_data(priv, buf, 2); + if (result != XC_RESULT_SUCCESS) + return result; + + *i2cData = buf[0] * 256 + buf[1]; + return result; +} + +static int xc_load_i2c_sequence(struct dvb_frontend *fe, u8 i2c_sequence[]) +{ + struct xc5000_priv *priv = fe->tuner_priv; + + int i, nbytes_to_send, result; + unsigned int len, pos, index; + u8 buf[XC_MAX_I2C_WRITE_LENGTH]; + + index=0; + while ((i2c_sequence[index]!=0xFF) || (i2c_sequence[index+1]!=0xFF)) { + len = i2c_sequence[index]* 256 + i2c_sequence[index+1]; + if (len == 0x0000) { + /* RESET command */ + result = xc_reset(fe); + index += 2; + if (result != XC_RESULT_SUCCESS) + return result; + } else if (len & 0x8000) { + /* WAIT command */ + xc_wait(len & 0x7FFF); + index += 2; + } else { + /* Send i2c data whilst ensuring individual transactions + * do not exceed XC_MAX_I2C_WRITE_LENGTH bytes. + */ + index += 2; + buf[0] = i2c_sequence[index]; + buf[1] = i2c_sequence[index + 1]; + pos = 2; + while (pos < len) { + if ((len - pos) > XC_MAX_I2C_WRITE_LENGTH - 2) { + nbytes_to_send = XC_MAX_I2C_WRITE_LENGTH; + } else { + nbytes_to_send = (len - pos + 2); + } + for (i=2; ivideo_standard].Name); + + ret = xc_write_reg(priv, XREG_VIDEO_MODE, VideoMode); + if (ret == XC_RESULT_SUCCESS) + ret = xc_write_reg(priv, XREG_AUDIO_MODE, AudioMode); + + return ret; +} + +static int xc_shutdown(struct xc5000_priv *priv) +{ + return 0; + /* Fixme: cannot bring tuner back alive once shutdown + * without reloading the driver modules. + * return xc_write_reg(priv, XREG_POWER_DOWN, 0); + */ +} + +static int xc_SetSignalSource(struct xc5000_priv *priv, u16 rf_mode) +{ + dprintk(1, "%s(%d) Source = %s\n", __func__, rf_mode, + rf_mode == XC_RF_MODE_AIR ? "ANTENNA" : "CABLE"); + + if ((rf_mode != XC_RF_MODE_AIR) && (rf_mode != XC_RF_MODE_CABLE)) + { + rf_mode = XC_RF_MODE_CABLE; + printk(KERN_ERR + "%s(), Invalid mode, defaulting to CABLE", + __func__); + } + return xc_write_reg(priv, XREG_SIGNALSOURCE, rf_mode); +} + +static const struct dvb_tuner_ops xc5000_tuner_ops; + +static int xc_set_RF_frequency(struct xc5000_priv *priv, u32 freq_hz) +{ + u16 freq_code; + + dprintk(1, "%s(%u)\n", __func__, freq_hz); + + if ((freq_hz > xc5000_tuner_ops.info.frequency_max) || + (freq_hz < xc5000_tuner_ops.info.frequency_min)) + return XC_RESULT_OUT_OF_RANGE; + + freq_code = (u16)(freq_hz / 15625); + + return xc_write_reg(priv, XREG_RF_FREQ, freq_code); +} + +#if 0 +/* We'll probably need these for analog support */ +static int xc_FineTune_RF_frequency(struct xc5000_priv *priv, u32 freq_hz) +{ + u16 freq_code = (u16)(freq_hz / 15625); + + if ((freq_hz > xc5000_tuner_ops.info.frequency_max) || + (freq_hz < xc5000_tuner_ops.info.frequency_min)) + return XC_RESULT_OUT_OF_RANGE; + + return xc_write_reg(priv, XREG_FINERFFREQ, freq_code); +} + +static int xc_set_Xtal_frequency(struct xc5000_priv *priv, u32 xtalFreqInKHz) +{ + u16 xtalRatio = (32000 * 0x8000)/xtalFreqInKHz; + return xc_write_reg(priv, XREG_XTALFREQ, xtalRatio); +} +#endif + +static int xc_set_IF_frequency(struct xc5000_priv *priv, u32 freq_khz) +{ + u32 freq_code = (freq_khz * 1024)/1000; + dprintk(1, "%s(freq_khz = %d) freq_code = 0x%x\n", + __func__, freq_khz, freq_code); + + return xc_write_reg(priv, XREG_IF_OUT, freq_code); +} + + +static int xc_get_ADC_Envelope(struct xc5000_priv *priv, u16 *adc_envelope) +{ + return xc_read_reg(priv, XREG_ADC_ENV, adc_envelope); +} + +static int xc_get_frequency_error(struct xc5000_priv *priv, u32 *freq_error_hz) +{ + int result; + u16 regData; + u32 tmp; + + result = xc_read_reg(priv, XREG_FREQ_ERROR, ®Data); + if (result) + return result; + + tmp = (u32)regData; + (*freq_error_hz) = (tmp * 15625) / 1000; + return result; +} + +static int xc_get_lock_status(struct xc5000_priv *priv, u16 *lock_status) +{ + return xc_read_reg(priv, XREG_LOCK, lock_status); +} + +static int xc_get_version(struct xc5000_priv *priv, + u8 *hw_majorversion, u8 *hw_minorversion, + u8 *fw_majorversion, u8 *fw_minorversion) +{ + u16 data; + int result; + + result = xc_read_reg(priv, XREG_VERSION, &data); + if (result) + return result; + + (*hw_majorversion) = (data >> 12) & 0x0F; + (*hw_minorversion) = (data >> 8) & 0x0F; + (*fw_majorversion) = (data >> 4) & 0x0F; + (*fw_minorversion) = data & 0x0F; + + return 0; +} + +static int xc_get_hsync_freq(struct xc5000_priv *priv, u32 *hsync_freq_hz) +{ + u16 regData; + int result; + + result = xc_read_reg(priv, XREG_HSYNC_FREQ, ®Data); + if (result) + return result; + + (*hsync_freq_hz) = ((regData & 0x0fff) * 763)/100; + return result; +} + +static int xc_get_frame_lines(struct xc5000_priv *priv, u16 *frame_lines) +{ + return xc_read_reg(priv, XREG_FRAME_LINES, frame_lines); +} + +static int xc_get_quality(struct xc5000_priv *priv, u16 *quality) +{ + return xc_read_reg(priv, XREG_QUALITY, quality); +} + +static u16 WaitForLock(struct xc5000_priv *priv) +{ + u16 lockState = 0; + int watchDogCount = 40; + + while ((lockState == 0) && (watchDogCount > 0)) { + xc_get_lock_status(priv, &lockState); + if (lockState != 1) { + xc_wait(5); + watchDogCount--; + } + } + return lockState; +} + +static int xc_tune_channel(struct xc5000_priv *priv, u32 freq_hz) +{ + int found = 0; + + dprintk(1, "%s(%u)\n", __func__, freq_hz); + + if (xc_set_RF_frequency(priv, freq_hz) != XC_RESULT_SUCCESS) + return 0; + + if (WaitForLock(priv) == 1) + found = 1; + + return found; +} + +static int xc5000_readreg(struct xc5000_priv *priv, u16 reg, u16 *val) +{ + u8 buf[2] = { reg >> 8, reg & 0xff }; + u8 bval[2] = { 0, 0 }; + struct i2c_msg msg[2] = { + { .addr = priv->cfg->i2c_address, + .flags = 0, .buf = &buf[0], .len = 2 }, + { .addr = priv->cfg->i2c_address, + .flags = I2C_M_RD, .buf = &bval[0], .len = 2 }, + }; + + if (i2c_transfer(priv->i2c, msg, 2) != 2) { + printk(KERN_WARNING "xc5000: I2C read failed\n"); + return -EREMOTEIO; + } + + *val = (bval[0] << 8) | bval[1]; + return 0; +} + +static int xc5000_writeregs(struct xc5000_priv *priv, u8 *buf, u8 len) +{ + struct i2c_msg msg = { .addr = priv->cfg->i2c_address, + .flags = 0, .buf = buf, .len = len }; + + if (i2c_transfer(priv->i2c, &msg, 1) != 1) { + printk(KERN_ERR "xc5000: I2C write failed (len=%i)\n", + (int)len); + return -EREMOTEIO; + } + return 0; +} + +static int xc5000_readregs(struct xc5000_priv *priv, u8 *buf, u8 len) +{ + struct i2c_msg msg = { .addr = priv->cfg->i2c_address, + .flags = I2C_M_RD, .buf = buf, .len = len }; + + if (i2c_transfer(priv->i2c, &msg, 1) != 1) { + printk(KERN_ERR "xc5000 I2C read failed (len=%i)\n",(int)len); + return -EREMOTEIO; + } + return 0; +} + +static int xc5000_fwupload(struct dvb_frontend* fe) +{ + struct xc5000_priv *priv = fe->tuner_priv; + const struct firmware *fw; + int ret; + + /* request the firmware, this will block and timeout */ + printk(KERN_INFO "xc5000: waiting for firmware upload (%s)...\n", + XC5000_DEFAULT_FIRMWARE); + + ret = request_firmware(&fw, XC5000_DEFAULT_FIRMWARE, &priv->i2c->dev); + if (ret) { + printk(KERN_ERR "xc5000: Upload failed. (file not found?)\n"); + ret = XC_RESULT_RESET_FAILURE; + goto out; + } else { + printk(KERN_INFO "xc5000: firmware read %Zu bytes.\n", + fw->size); + ret = XC_RESULT_SUCCESS; + } + + if (fw->size != XC5000_DEFAULT_FIRMWARE_SIZE) { + printk(KERN_ERR "xc5000: firmware incorrect size\n"); + ret = XC_RESULT_RESET_FAILURE; + } else { + printk(KERN_INFO "xc5000: firmware upload\n"); + ret = xc_load_i2c_sequence(fe, fw->data ); + } + +out: + release_firmware(fw); + return ret; +} + +static void xc_debug_dump(struct xc5000_priv *priv) +{ + u16 adc_envelope; + u32 freq_error_hz = 0; + u16 lock_status; + u32 hsync_freq_hz = 0; + u16 frame_lines; + u16 quality; + u8 hw_majorversion = 0, hw_minorversion = 0; + u8 fw_majorversion = 0, fw_minorversion = 0; + + /* Wait for stats to stabilize. + * Frame Lines needs two frame times after initial lock + * before it is valid. + */ + xc_wait(100); + + xc_get_ADC_Envelope(priv, &adc_envelope); + dprintk(1, "*** ADC envelope (0-1023) = %d\n", adc_envelope); + + xc_get_frequency_error(priv, &freq_error_hz); + dprintk(1, "*** Frequency error = %d Hz\n", freq_error_hz); + + xc_get_lock_status(priv, &lock_status); + dprintk(1, "*** Lock status (0-Wait, 1-Locked, 2-No-signal) = %d\n", + lock_status); + + xc_get_version(priv, &hw_majorversion, &hw_minorversion, + &fw_majorversion, &fw_minorversion); + dprintk(1, "*** HW: V%02x.%02x, FW: V%02x.%02x\n", + hw_majorversion, hw_minorversion, + fw_majorversion, fw_minorversion); + + xc_get_hsync_freq(priv, &hsync_freq_hz); + dprintk(1, "*** Horizontal sync frequency = %d Hz\n", hsync_freq_hz); + + xc_get_frame_lines(priv, &frame_lines); + dprintk(1, "*** Frame lines = %d\n", frame_lines); + + xc_get_quality(priv, &quality); + dprintk(1, "*** Quality (0:<8dB, 7:>56dB) = %d\n", quality); +} + +static int xc5000_set_params(struct dvb_frontend *fe, + struct dvb_frontend_parameters *params) +{ + struct xc5000_priv *priv = fe->tuner_priv; + int ret; + + dprintk(1, "%s() frequency=%d (Hz)\n", __func__, params->frequency); + + switch(params->u.vsb.modulation) { + case VSB_8: + case VSB_16: + dprintk(1, "%s() VSB modulation\n", __func__); + priv->rf_mode = XC_RF_MODE_AIR; + priv->freq_hz = params->frequency - 1750000; + priv->bandwidth = BANDWIDTH_6_MHZ; + priv->video_standard = DTV6; + break; + case QAM_64: + case QAM_256: + case QAM_AUTO: + dprintk(1, "%s() QAM modulation\n", __func__); + priv->rf_mode = XC_RF_MODE_CABLE; + priv->freq_hz = params->frequency - 1750000; + priv->bandwidth = BANDWIDTH_6_MHZ; + priv->video_standard = DTV6; + break; + default: + return -EINVAL; + } + + dprintk(1, "%s() frequency=%d (compensated)\n", + __func__, priv->freq_hz); + + ret = xc_SetSignalSource(priv, priv->rf_mode); + if (ret != XC_RESULT_SUCCESS) { + printk(KERN_ERR + "xc5000: xc_SetSignalSource(%d) failed\n", + priv->rf_mode); + return -EREMOTEIO; + } + + ret = xc_SetTVStandard(priv, + XC5000_Standard[priv->video_standard].VideoMode, + XC5000_Standard[priv->video_standard].AudioMode); + if (ret != XC_RESULT_SUCCESS) { + printk(KERN_ERR "xc5000: xc_SetTVStandard failed\n"); + return -EREMOTEIO; + } + + ret = xc_set_IF_frequency(priv, priv->cfg->if_khz); + if (ret != XC_RESULT_SUCCESS) { + printk(KERN_ERR "xc5000: xc_Set_IF_frequency(%d) failed\n", + priv->cfg->if_khz); + return -EIO; + } + + xc_tune_channel(priv, priv->freq_hz); + + if (debug) + xc_debug_dump(priv); + + return 0; +} + +static int xc_load_fw_and_init_tuner(struct dvb_frontend *fe); + +static int xc5000_set_analog_params(struct dvb_frontend *fe, + struct analog_parameters *params) +{ + struct xc5000_priv *priv = fe->tuner_priv; + int ret; + + if(priv->fwloaded == 0) + xc_load_fw_and_init_tuner(fe); + + dprintk(1, "%s() frequency=%d (in units of 62.5khz)\n", + __func__, params->frequency); + + priv->rf_mode = XC_RF_MODE_CABLE; /* Fix me: it could be air. */ + + /* params->frequency is in units of 62.5khz */ + priv->freq_hz = params->frequency * 62500; + + /* FIX ME: Some video standards may have several possible audio + standards. We simply default to one of them here. + */ + if(params->std & V4L2_STD_MN) { + /* default to BTSC audio standard */ + priv->video_standard = MN_NTSC_PAL_BTSC; + goto tune_channel; + } + + if(params->std & V4L2_STD_PAL_BG) { + /* default to NICAM audio standard */ + priv->video_standard = BG_PAL_NICAM; + goto tune_channel; + } + + if(params->std & V4L2_STD_PAL_I) { + /* default to NICAM audio standard */ + priv->video_standard = I_PAL_NICAM; + goto tune_channel; + } + + if(params->std & V4L2_STD_PAL_DK) { + /* default to NICAM audio standard */ + priv->video_standard = DK_PAL_NICAM; + goto tune_channel; + } + + if(params->std & V4L2_STD_SECAM_DK) { + /* default to A2 DK1 audio standard */ + priv->video_standard = DK_SECAM_A2DK1; + goto tune_channel; + } + + if(params->std & V4L2_STD_SECAM_L) { + priv->video_standard = L_SECAM_NICAM; + goto tune_channel; + } + + if(params->std & V4L2_STD_SECAM_LC) { + priv->video_standard = LC_SECAM_NICAM; + goto tune_channel; + } + +tune_channel: + ret = xc_SetSignalSource(priv, priv->rf_mode); + if (ret != XC_RESULT_SUCCESS) { + printk(KERN_ERR + "xc5000: xc_SetSignalSource(%d) failed\n", + priv->rf_mode); + return -EREMOTEIO; + } + + ret = xc_SetTVStandard(priv, + XC5000_Standard[priv->video_standard].VideoMode, + XC5000_Standard[priv->video_standard].AudioMode); + if (ret != XC_RESULT_SUCCESS) { + printk(KERN_ERR "xc5000: xc_SetTVStandard failed\n"); + return -EREMOTEIO; + } + + xc_tune_channel(priv, priv->freq_hz); + + if (debug) + xc_debug_dump(priv); + + return 0; +} + +static int xc5000_get_frequency(struct dvb_frontend *fe, u32 *freq) +{ + struct xc5000_priv *priv = fe->tuner_priv; + dprintk(1, "%s()\n", __func__); + *freq = priv->freq_hz; + return 0; +} + +static int xc5000_get_bandwidth(struct dvb_frontend *fe, u32 *bw) +{ + struct xc5000_priv *priv = fe->tuner_priv; + dprintk(1, "%s()\n", __func__); + + *bw = priv->bandwidth; + return 0; +} + +static int xc5000_get_status(struct dvb_frontend *fe, u32 *status) +{ + struct xc5000_priv *priv = fe->tuner_priv; + u16 lock_status = 0; + + xc_get_lock_status(priv, &lock_status); + + dprintk(1, "%s() lock_status = 0x%08x\n", __func__, lock_status); + + *status = lock_status; + + return 0; +} + +static int xc_load_fw_and_init_tuner(struct dvb_frontend *fe) +{ + struct xc5000_priv *priv = fe->tuner_priv; + int ret = 0; + + if (priv->fwloaded == 0) { + ret = xc5000_fwupload(fe); + if (ret != XC_RESULT_SUCCESS) + return ret; + priv->fwloaded = 1; + } + + /* Start the tuner self-calibration process */ + ret |= xc_initialize(priv); + + /* Wait for calibration to complete. + * We could continue but XC5000 will clock stretch subsequent + * I2C transactions until calibration is complete. This way we + * don't have to rely on clock stretching working. + */ + xc_wait( 100 ); + + /* Default to "CABLE" mode */ + ret |= xc_write_reg(priv, XREG_SIGNALSOURCE, XC_RF_MODE_CABLE); + + return ret; +} + +static int xc5000_sleep(struct dvb_frontend *fe) +{ + struct xc5000_priv *priv = fe->tuner_priv; + int ret; + + dprintk(1, "%s()\n", __func__); + + /* On Pinnacle PCTV HD 800i, the tuner cannot be reinitialized + * once shutdown without reloading the driver. Maybe I am not + * doing something right. + * + */ + + ret = xc_shutdown(priv); + if(ret != XC_RESULT_SUCCESS) { + printk(KERN_ERR + "xc5000: %s() unable to shutdown tuner\n", + __func__); + return -EREMOTEIO; + } + else { + /* priv->fwloaded = 0; */ + return XC_RESULT_SUCCESS; + } +} + +static int xc5000_init(struct dvb_frontend *fe) +{ + struct xc5000_priv *priv = fe->tuner_priv; + dprintk(1, "%s()\n", __func__); + + if (xc_load_fw_and_init_tuner(fe) != XC_RESULT_SUCCESS) { + printk(KERN_ERR "xc5000: Unable to initialise tuner\n"); + return -EREMOTEIO; + } + + if (debug) + xc_debug_dump(priv); + + return 0; +} + +static int xc5000_release(struct dvb_frontend *fe) +{ + dprintk(1, "%s()\n", __func__); + kfree(fe->tuner_priv); + fe->tuner_priv = NULL; + return 0; +} + +static const struct dvb_tuner_ops xc5000_tuner_ops = { + .info = { + .name = "Xceive XC5000", + .frequency_min = 1000000, + .frequency_max = 1023000000, + .frequency_step = 50000, + }, + + .release = xc5000_release, + .init = xc5000_init, + .sleep = xc5000_sleep, + + .set_params = xc5000_set_params, + .set_analog_params = xc5000_set_analog_params, + .get_frequency = xc5000_get_frequency, + .get_bandwidth = xc5000_get_bandwidth, + .get_status = xc5000_get_status +}; + +struct dvb_frontend * xc5000_attach(struct dvb_frontend *fe, + struct i2c_adapter *i2c, + struct xc5000_config *cfg) +{ + struct xc5000_priv *priv = NULL; + u16 id = 0; + + dprintk(1, "%s()\n", __func__); + + priv = kzalloc(sizeof(struct xc5000_priv), GFP_KERNEL); + if (priv == NULL) + return NULL; + + priv->cfg = cfg; + priv->bandwidth = BANDWIDTH_6_MHZ; + priv->i2c = i2c; + + /* Check if firmware has been loaded. It is possible that another + instance of the driver has loaded the firmware. + */ + if (xc5000_readreg(priv, XREG_PRODUCT_ID, &id) != 0) { + kfree(priv); + return NULL; + } + + switch(id) { + case XC_PRODUCT_ID_FW_LOADED: + printk(KERN_INFO + "xc5000: Successfully identified at address 0x%02x\n", + cfg->i2c_address); + printk(KERN_INFO + "xc5000: Firmware has been loaded previously\n"); + priv->fwloaded = 1; + break; + case XC_PRODUCT_ID_FW_NOT_LOADED: + printk(KERN_INFO + "xc5000: Successfully identified at address 0x%02x\n", + cfg->i2c_address); + printk(KERN_INFO + "xc5000: Firmware has not been loaded previously\n"); + priv->fwloaded = 0; + break; + default: + printk(KERN_ERR + "xc5000: Device not found at addr 0x%02x (0x%x)\n", + cfg->i2c_address, id); + kfree(priv); + return NULL; + } + + memcpy(&fe->ops.tuner_ops, &xc5000_tuner_ops, + sizeof(struct dvb_tuner_ops)); + + fe->tuner_priv = priv; + + return fe; +} +EXPORT_SYMBOL(xc5000_attach); + +MODULE_AUTHOR("Steven Toth"); +MODULE_DESCRIPTION("Xceive xc5000 silicon tuner driver"); +MODULE_LICENSE("GPL"); diff --git a/linux/drivers/media/common/tuners/xc5000.h b/linux/drivers/media/common/tuners/xc5000.h new file mode 100644 index 000000000..b890883a0 --- /dev/null +++ b/linux/drivers/media/common/tuners/xc5000.h @@ -0,0 +1,63 @@ +/* + * Driver for Xceive XC5000 "QAM/8VSB single chip tuner" + * + * Copyright (c) 2007 Steven Toth + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#ifndef __XC5000_H__ +#define __XC5000_H__ + +#include + +struct dvb_frontend; +struct i2c_adapter; + +struct xc5000_config { + u8 i2c_address; + u32 if_khz; + + /* For each bridge framework, when it attaches either analog or digital, + * it has to store a reference back to its _core equivalent structure, + * so that it can service the hardware by steering gpio's etc. + * Each bridge implementation is different so cast priv accordingly. + * The xc5000 driver cares not for this value, other than ensuring + * it's passed back to a bridge during tuner_callback(). + */ + void *priv; + int (*tuner_callback) (void *priv, int command, int arg); +}; + +/* xc5000 callback command */ +#define XC5000_TUNER_RESET 0 + +#if defined(CONFIG_DVB_TUNER_XC5000) || \ + (defined(CONFIG_DVB_TUNER_XC5000_MODULE) && defined(MODULE)) +extern struct dvb_frontend* xc5000_attach(struct dvb_frontend *fe, + struct i2c_adapter *i2c, + struct xc5000_config *cfg); +#else +static inline struct dvb_frontend* xc5000_attach(struct dvb_frontend *fe, + struct i2c_adapter *i2c, + struct xc5000_config *cfg) +{ + printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__); + return NULL; +} +#endif // CONFIG_DVB_TUNER_XC5000 + +#endif // __XC5000_H__ diff --git a/linux/drivers/media/common/tuners/xc5000_priv.h b/linux/drivers/media/common/tuners/xc5000_priv.h new file mode 100644 index 000000000..13b2d1934 --- /dev/null +++ b/linux/drivers/media/common/tuners/xc5000_priv.h @@ -0,0 +1,36 @@ +/* + * Driver for Xceive XC5000 "QAM/8VSB single chip tuner" + * + * Copyright (c) 2007 Steven Toth + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#ifndef XC5000_PRIV_H +#define XC5000_PRIV_H + +struct xc5000_priv { + struct xc5000_config *cfg; + struct i2c_adapter *i2c; + + u32 freq_hz; + u32 bandwidth; + u8 video_standard; + u8 rf_mode; + u8 fwloaded; +}; + +#endif -- cgit v1.2.3 From a3ce5f09fee0d7eb07f6097a5f373bdd7908b4e7 Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Sat, 26 Apr 2008 13:22:39 -0300 Subject: Move other terrestrial tuners to common/tuners From: Mauro Carvalho Chehab Those tuners are currently used only under media/dvb. However, they can support also analog TV. Better to move them to the same place as the other hybrid tuners. This would make easier to use those tuners also by analog drivers. Signed-off-by: Mauro Carvalho Chehab --- linux/drivers/media/common/tuners/mt2060.c | 376 ++++++++++++++++++ linux/drivers/media/common/tuners/mt2060.h | 43 +++ linux/drivers/media/common/tuners/mt2060_priv.h | 105 +++++ linux/drivers/media/common/tuners/mt2131.c | 315 +++++++++++++++ linux/drivers/media/common/tuners/mt2131.h | 54 +++ linux/drivers/media/common/tuners/mt2131_priv.h | 49 +++ linux/drivers/media/common/tuners/mt2266.c | 352 +++++++++++++++++ linux/drivers/media/common/tuners/mt2266.h | 37 ++ linux/drivers/media/common/tuners/qt1010.c | 489 ++++++++++++++++++++++++ linux/drivers/media/common/tuners/qt1010.h | 53 +++ linux/drivers/media/common/tuners/qt1010_priv.h | 105 +++++ 11 files changed, 1978 insertions(+) create mode 100644 linux/drivers/media/common/tuners/mt2060.c create mode 100644 linux/drivers/media/common/tuners/mt2060.h create mode 100644 linux/drivers/media/common/tuners/mt2060_priv.h create mode 100644 linux/drivers/media/common/tuners/mt2131.c create mode 100644 linux/drivers/media/common/tuners/mt2131.h create mode 100644 linux/drivers/media/common/tuners/mt2131_priv.h create mode 100644 linux/drivers/media/common/tuners/mt2266.c create mode 100644 linux/drivers/media/common/tuners/mt2266.h create mode 100644 linux/drivers/media/common/tuners/qt1010.c create mode 100644 linux/drivers/media/common/tuners/qt1010.h create mode 100644 linux/drivers/media/common/tuners/qt1010_priv.h (limited to 'linux/drivers/media/common/tuners') diff --git a/linux/drivers/media/common/tuners/mt2060.c b/linux/drivers/media/common/tuners/mt2060.c new file mode 100644 index 000000000..355817754 --- /dev/null +++ b/linux/drivers/media/common/tuners/mt2060.c @@ -0,0 +1,376 @@ +/* + * Driver for Microtune MT2060 "Single chip dual conversion broadband tuner" + * + * Copyright (c) 2006 Olivier DANET + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.= + */ + +/* In that file, frequencies are expressed in kiloHertz to avoid 32 bits overflows */ + +#include +#include +#include +#include +#include "compat.h" + +#include "dvb_frontend.h" + +#include "mt2060.h" +#include "mt2060_priv.h" + +static int debug; +module_param(debug, int, 0644); +MODULE_PARM_DESC(debug, "Turn on/off debugging (default:off)."); + +#define dprintk(args...) do { if (debug) {printk(KERN_DEBUG "MT2060: " args); printk("\n"); }} while (0) + +// Reads a single register +static int mt2060_readreg(struct mt2060_priv *priv, u8 reg, u8 *val) +{ + struct i2c_msg msg[2] = { + { .addr = priv->cfg->i2c_address, .flags = 0, .buf = ®, .len = 1 }, + { .addr = priv->cfg->i2c_address, .flags = I2C_M_RD, .buf = val, .len = 1 }, + }; + + if (i2c_transfer(priv->i2c, msg, 2) != 2) { + printk(KERN_WARNING "mt2060 I2C read failed\n"); + return -EREMOTEIO; + } + return 0; +} + +// Writes a single register +static int mt2060_writereg(struct mt2060_priv *priv, u8 reg, u8 val) +{ + u8 buf[2] = { reg, val }; + struct i2c_msg msg = { + .addr = priv->cfg->i2c_address, .flags = 0, .buf = buf, .len = 2 + }; + + if (i2c_transfer(priv->i2c, &msg, 1) != 1) { + printk(KERN_WARNING "mt2060 I2C write failed\n"); + return -EREMOTEIO; + } + return 0; +} + +// Writes a set of consecutive registers +static int mt2060_writeregs(struct mt2060_priv *priv,u8 *buf, u8 len) +{ + struct i2c_msg msg = { + .addr = priv->cfg->i2c_address, .flags = 0, .buf = buf, .len = len + }; + if (i2c_transfer(priv->i2c, &msg, 1) != 1) { + printk(KERN_WARNING "mt2060 I2C write failed (len=%i)\n",(int)len); + return -EREMOTEIO; + } + return 0; +} + +// Initialisation sequences +// LNABAND=3, NUM1=0x3C, DIV1=0x74, NUM2=0x1080, DIV2=0x49 +static u8 mt2060_config1[] = { + REG_LO1C1, + 0x3F, 0x74, 0x00, 0x08, 0x93 +}; + +// FMCG=2, GP2=0, GP1=0 +static u8 mt2060_config2[] = { + REG_MISC_CTRL, + 0x20, 0x1E, 0x30, 0xff, 0x80, 0xff, 0x00, 0x2c, 0x42 +}; + +// VGAG=3, V1CSE=1 +#if 0 +static u8 mt2060_config3[] = { + REG_VGAG, + 0x33 +}; +#endif + +#ifdef MT2060_SPURCHECK +/* The function below calculates the frequency offset between the output frequency if2 + and the closer cross modulation subcarrier between lo1 and lo2 up to the tenth harmonic */ +static int mt2060_spurcalc(u32 lo1,u32 lo2,u32 if2) +{ + int I,J; + int dia,diamin,diff; + diamin=1000000; + for (I = 1; I < 10; I++) { + J = ((2*I*lo1)/lo2+1)/2; + diff = I*(int)lo1-J*(int)lo2; + if (diff < 0) diff=-diff; + dia = (diff-(int)if2); + if (dia < 0) dia=-dia; + if (diamin > dia) diamin=dia; + } + return diamin; +} + +#define BANDWIDTH 4000 // kHz + +/* Calculates the frequency offset to add to avoid spurs. Returns 0 if no offset is needed */ +static int mt2060_spurcheck(u32 lo1,u32 lo2,u32 if2) +{ + u32 Spur,Sp1,Sp2; + int I,J; + I=0; + J=1000; + + Spur=mt2060_spurcalc(lo1,lo2,if2); + if (Spur < BANDWIDTH) { + /* Potential spurs detected */ + dprintk("Spurs before : f_lo1: %d f_lo2: %d (kHz)", + (int)lo1,(int)lo2); + I=1000; + Sp1 = mt2060_spurcalc(lo1+I,lo2+I,if2); + Sp2 = mt2060_spurcalc(lo1-I,lo2-I,if2); + + if (Sp1 < Sp2) { + J=-J; I=-I; Spur=Sp2; + } else + Spur=Sp1; + + while (Spur < BANDWIDTH) { + I += J; + Spur = mt2060_spurcalc(lo1+I,lo2+I,if2); + } + dprintk("Spurs after : f_lo1: %d f_lo2: %d (kHz)", + (int)(lo1+I),(int)(lo2+I)); + } + return I; +} +#endif + +#define IF2 36150 // IF2 frequency = 36.150 MHz +#define FREF 16000 // Quartz oscillator 16 MHz + +static int mt2060_set_params(struct dvb_frontend *fe, struct dvb_frontend_parameters *params) +{ + struct mt2060_priv *priv; + int ret=0; + int i=0; + u32 freq; + u8 lnaband; + u32 f_lo1,f_lo2; + u32 div1,num1,div2,num2; + u8 b[8]; + u32 if1; + + priv = fe->tuner_priv; + + if1 = priv->if1_freq; + b[0] = REG_LO1B1; + b[1] = 0xFF; + + mt2060_writeregs(priv,b,2); + + freq = params->frequency / 1000; // Hz -> kHz + priv->bandwidth = (fe->ops.info.type == FE_OFDM) ? params->u.ofdm.bandwidth : 0; + + f_lo1 = freq + if1 * 1000; + f_lo1 = (f_lo1 / 250) * 250; + f_lo2 = f_lo1 - freq - IF2; + // From the Comtech datasheet, the step used is 50kHz. The tuner chip could be more precise + f_lo2 = ((f_lo2 + 25) / 50) * 50; + priv->frequency = (f_lo1 - f_lo2 - IF2) * 1000, + +#ifdef MT2060_SPURCHECK + // LO-related spurs detection and correction + num1 = mt2060_spurcheck(f_lo1,f_lo2,IF2); + f_lo1 += num1; + f_lo2 += num1; +#endif + //Frequency LO1 = 16MHz * (DIV1 + NUM1/64 ) + num1 = f_lo1 / (FREF / 64); + div1 = num1 / 64; + num1 &= 0x3f; + + // Frequency LO2 = 16MHz * (DIV2 + NUM2/8192 ) + num2 = f_lo2 * 64 / (FREF / 128); + div2 = num2 / 8192; + num2 &= 0x1fff; + + if (freq <= 95000) lnaband = 0xB0; else + if (freq <= 180000) lnaband = 0xA0; else + if (freq <= 260000) lnaband = 0x90; else + if (freq <= 335000) lnaband = 0x80; else + if (freq <= 425000) lnaband = 0x70; else + if (freq <= 480000) lnaband = 0x60; else + if (freq <= 570000) lnaband = 0x50; else + if (freq <= 645000) lnaband = 0x40; else + if (freq <= 730000) lnaband = 0x30; else + if (freq <= 810000) lnaband = 0x20; else lnaband = 0x10; + + b[0] = REG_LO1C1; + b[1] = lnaband | ((num1 >>2) & 0x0F); + b[2] = div1; + b[3] = (num2 & 0x0F) | ((num1 & 3) << 4); + b[4] = num2 >> 4; + b[5] = ((num2 >>12) & 1) | (div2 << 1); + + dprintk("IF1: %dMHz",(int)if1); + dprintk("PLL freq=%dkHz f_lo1=%dkHz f_lo2=%dkHz",(int)freq,(int)f_lo1,(int)f_lo2); + dprintk("PLL div1=%d num1=%d div2=%d num2=%d",(int)div1,(int)num1,(int)div2,(int)num2); + dprintk("PLL [1..5]: %2x %2x %2x %2x %2x",(int)b[1],(int)b[2],(int)b[3],(int)b[4],(int)b[5]); + + mt2060_writeregs(priv,b,6); + + //Waits for pll lock or timeout + i = 0; + do { + mt2060_readreg(priv,REG_LO_STATUS,b); + if ((b[0] & 0x88)==0x88) + break; + msleep(4); + i++; + } while (i<10); + + return ret; +} + +static void mt2060_calibrate(struct mt2060_priv *priv) +{ + u8 b = 0; + int i = 0; + + if (mt2060_writeregs(priv,mt2060_config1,sizeof(mt2060_config1))) + return; + if (mt2060_writeregs(priv,mt2060_config2,sizeof(mt2060_config2))) + return; + + /* initialize the clock output */ + mt2060_writereg(priv, REG_VGAG, (priv->cfg->clock_out << 6) | 0x30); + + do { + b |= (1 << 6); // FM1SS; + mt2060_writereg(priv, REG_LO2C1,b); + msleep(20); + + if (i == 0) { + b |= (1 << 7); // FM1CA; + mt2060_writereg(priv, REG_LO2C1,b); + b &= ~(1 << 7); // FM1CA; + msleep(20); + } + + b &= ~(1 << 6); // FM1SS + mt2060_writereg(priv, REG_LO2C1,b); + + msleep(20); + i++; + } while (i < 9); + + i = 0; + while (i++ < 10 && mt2060_readreg(priv, REG_MISC_STAT, &b) == 0 && (b & (1 << 6)) == 0) + msleep(20); + + if (i < 10) { + mt2060_readreg(priv, REG_FM_FREQ, &priv->fmfreq); // now find out, what is fmreq used for :) + dprintk("calibration was successful: %d", (int)priv->fmfreq); + } else + dprintk("FMCAL timed out"); +} + +static int mt2060_get_frequency(struct dvb_frontend *fe, u32 *frequency) +{ + struct mt2060_priv *priv = fe->tuner_priv; + *frequency = priv->frequency; + return 0; +} + +static int mt2060_get_bandwidth(struct dvb_frontend *fe, u32 *bandwidth) +{ + struct mt2060_priv *priv = fe->tuner_priv; + *bandwidth = priv->bandwidth; + return 0; +} + +static int mt2060_init(struct dvb_frontend *fe) +{ + struct mt2060_priv *priv = fe->tuner_priv; + return mt2060_writereg(priv, REG_VGAG, (priv->cfg->clock_out << 6) | 0x33); +} + +static int mt2060_sleep(struct dvb_frontend *fe) +{ + struct mt2060_priv *priv = fe->tuner_priv; + return mt2060_writereg(priv, REG_VGAG, (priv->cfg->clock_out << 6) | 0x30); +} + +static int mt2060_release(struct dvb_frontend *fe) +{ + kfree(fe->tuner_priv); + fe->tuner_priv = NULL; + return 0; +} + +static const struct dvb_tuner_ops mt2060_tuner_ops = { + .info = { + .name = "Microtune MT2060", + .frequency_min = 48000000, + .frequency_max = 860000000, + .frequency_step = 50000, + }, + + .release = mt2060_release, + + .init = mt2060_init, + .sleep = mt2060_sleep, + + .set_params = mt2060_set_params, + .get_frequency = mt2060_get_frequency, + .get_bandwidth = mt2060_get_bandwidth +}; + +/* This functions tries to identify a MT2060 tuner by reading the PART/REV register. This is hasty. */ +struct dvb_frontend * mt2060_attach(struct dvb_frontend *fe, struct i2c_adapter *i2c, struct mt2060_config *cfg, u16 if1) +{ + struct mt2060_priv *priv = NULL; + u8 id = 0; + + priv = kzalloc(sizeof(struct mt2060_priv), GFP_KERNEL); + if (priv == NULL) + return NULL; + + priv->cfg = cfg; + priv->i2c = i2c; + priv->if1_freq = if1; + + if (mt2060_readreg(priv,REG_PART_REV,&id) != 0) { + kfree(priv); + return NULL; + } + + if (id != PART_REV) { + kfree(priv); + return NULL; + } + printk(KERN_INFO "MT2060: successfully identified (IF1 = %d)\n", if1); + memcpy(&fe->ops.tuner_ops, &mt2060_tuner_ops, sizeof(struct dvb_tuner_ops)); + + fe->tuner_priv = priv; + + mt2060_calibrate(priv); + + return fe; +} +EXPORT_SYMBOL(mt2060_attach); + +MODULE_AUTHOR("Olivier DANET"); +MODULE_DESCRIPTION("Microtune MT2060 silicon tuner driver"); +MODULE_LICENSE("GPL"); diff --git a/linux/drivers/media/common/tuners/mt2060.h b/linux/drivers/media/common/tuners/mt2060.h new file mode 100644 index 000000000..acba0058f --- /dev/null +++ b/linux/drivers/media/common/tuners/mt2060.h @@ -0,0 +1,43 @@ +/* + * Driver for Microtune MT2060 "Single chip dual conversion broadband tuner" + * + * Copyright (c) 2006 Olivier DANET + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.= + */ + +#ifndef MT2060_H +#define MT2060_H + +struct dvb_frontend; +struct i2c_adapter; + +struct mt2060_config { + u8 i2c_address; + u8 clock_out; /* 0 = off, 1 = CLK/4, 2 = CLK/2, 3 = CLK/1 */ +}; + +#if defined(CONFIG_DVB_TUNER_MT2060) || (defined(CONFIG_DVB_TUNER_MT2060_MODULE) && defined(MODULE)) +extern struct dvb_frontend * mt2060_attach(struct dvb_frontend *fe, struct i2c_adapter *i2c, struct mt2060_config *cfg, u16 if1); +#else +static inline struct dvb_frontend * mt2060_attach(struct dvb_frontend *fe, struct i2c_adapter *i2c, struct mt2060_config *cfg, u16 if1) +{ + printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__); + return NULL; +} +#endif // CONFIG_DVB_TUNER_MT2060 + +#endif diff --git a/linux/drivers/media/common/tuners/mt2060_priv.h b/linux/drivers/media/common/tuners/mt2060_priv.h new file mode 100644 index 000000000..5eaccdefd --- /dev/null +++ b/linux/drivers/media/common/tuners/mt2060_priv.h @@ -0,0 +1,105 @@ +/* + * Driver for Microtune MT2060 "Single chip dual conversion broadband tuner" + * + * Copyright (c) 2006 Olivier DANET + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.= + */ + +#ifndef MT2060_PRIV_H +#define MT2060_PRIV_H + +// Uncomment the #define below to enable spurs checking. The results where quite unconvincing. +// #define MT2060_SPURCHECK + +/* This driver is based on the information available in the datasheet of the + "Comtech SDVBT-3K6M" tuner ( K1000737843.pdf ) which features the MT2060 register map : + + I2C Address : 0x60 + + Reg.No | B7 | B6 | B5 | B4 | B3 | B2 | B1 | B0 | ( defaults ) + -------------------------------------------------------------------------------- + 00 | [ PART ] | [ REV ] | R = 0x63 + 01 | [ LNABAND ] | [ NUM1(5:2) ] | RW = 0x3F + 02 | [ DIV1 ] | RW = 0x74 + 03 | FM1CA | FM1SS | [ NUM1(1:0) ] | [ NUM2(3:0) ] | RW = 0x00 + 04 | NUM2(11:4) ] | RW = 0x08 + 05 | [ DIV2 ] |NUM2(12)| RW = 0x93 + 06 | L1LK | [ TAD1 ] | L2LK | [ TAD2 ] | R + 07 | [ FMF ] | R + 08 | ? | FMCAL | ? | ? | ? | ? | ? | TEMP | R + 09 | 0 | 0 | [ FMGC ] | 0 | GP02 | GP01 | 0 | RW = 0x20 + 0A | ?? + 0B | 0 | 0 | 1 | 1 | 0 | 0 | [ VGAG ] | RW = 0x30 + 0C | V1CSE | 1 | 1 | 1 | 1 | 1 | 1 | 1 | RW = 0xFF + 0D | 1 | 0 | [ V1CS ] | RW = 0xB0 + 0E | ?? + 0F | ?? + 10 | ?? + 11 | [ LOTO ] | 0 | 0 | 1 | 0 | RW = 0x42 + + PART : Part code : 6 for MT2060 + REV : Revision code : 3 for current revision + LNABAND : Input frequency range : ( See code for details ) + NUM1 / DIV1 / NUM2 / DIV2 : Frequencies programming ( See code for details ) + FM1CA : Calibration Start Bit + FM1SS : Calibration Single Step bit + L1LK : LO1 Lock Detect + TAD1 : Tune Line ADC ( ? ) + L2LK : LO2 Lock Detect + TAD2 : Tune Line ADC ( ? ) + FMF : Estimated first IF Center frequency Offset ( ? ) + FM1CAL : Calibration done bit + TEMP : On chip temperature sensor + FMCG : Mixer 1 Cap Gain ( ? ) + GP01 / GP02 : Programmable digital outputs. Unconnected pins ? + V1CSE : LO1 VCO Automatic Capacitor Select Enable ( ? ) + V1CS : LO1 Capacitor Selection Value ( ? ) + LOTO : LO Timeout ( ? ) + VGAG : Tuner Output gain +*/ + +#define I2C_ADDRESS 0x60 + +#define REG_PART_REV 0 +#define REG_LO1C1 1 +#define REG_LO1C2 2 +#define REG_LO2C1 3 +#define REG_LO2C2 4 +#define REG_LO2C3 5 +#define REG_LO_STATUS 6 +#define REG_FM_FREQ 7 +#define REG_MISC_STAT 8 +#define REG_MISC_CTRL 9 +#define REG_RESERVED_A 0x0A +#define REG_VGAG 0x0B +#define REG_LO1B1 0x0C +#define REG_LO1B2 0x0D +#define REG_LOTO 0x11 + +#define PART_REV 0x63 // The current driver works only with PART=6 and REV=3 chips + +struct mt2060_priv { + struct mt2060_config *cfg; + struct i2c_adapter *i2c; + + u32 frequency; + u32 bandwidth; + u16 if1_freq; + u8 fmfreq; +}; + +#endif diff --git a/linux/drivers/media/common/tuners/mt2131.c b/linux/drivers/media/common/tuners/mt2131.c new file mode 100644 index 000000000..becc409d9 --- /dev/null +++ b/linux/drivers/media/common/tuners/mt2131.c @@ -0,0 +1,315 @@ +/* + * Driver for Microtune MT2131 "QAM/8VSB single chip tuner" + * + * Copyright (c) 2006 Steven Toth + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include +#include +#include +#include +#include "compat.h" + +#include "dvb_frontend.h" + +#include "mt2131.h" +#include "mt2131_priv.h" + +static int debug; +module_param(debug, int, 0644); +MODULE_PARM_DESC(debug, "Turn on/off debugging (default:off)."); + +#define dprintk(level,fmt, arg...) if (debug >= level) \ + printk(KERN_INFO "%s: " fmt, "mt2131", ## arg) + +static u8 mt2131_config1[] = { + 0x01, + 0x50, 0x00, 0x50, 0x80, 0x00, 0x49, 0xfa, 0x88, + 0x08, 0x77, 0x41, 0x04, 0x00, 0x00, 0x00, 0x32, + 0x7f, 0xda, 0x4c, 0x00, 0x10, 0xaa, 0x78, 0x80, + 0xff, 0x68, 0xa0, 0xff, 0xdd, 0x00, 0x00 +}; + +static u8 mt2131_config2[] = { + 0x10, + 0x7f, 0xc8, 0x0a, 0x5f, 0x00, 0x04 +}; + +static int mt2131_readreg(struct mt2131_priv *priv, u8 reg, u8 *val) +{ + struct i2c_msg msg[2] = { + { .addr = priv->cfg->i2c_address, .flags = 0, + .buf = ®, .len = 1 }, + { .addr = priv->cfg->i2c_address, .flags = I2C_M_RD, + .buf = val, .len = 1 }, + }; + + if (i2c_transfer(priv->i2c, msg, 2) != 2) { + printk(KERN_WARNING "mt2131 I2C read failed\n"); + return -EREMOTEIO; + } + return 0; +} + +static int mt2131_writereg(struct mt2131_priv *priv, u8 reg, u8 val) +{ + u8 buf[2] = { reg, val }; + struct i2c_msg msg = { .addr = priv->cfg->i2c_address, .flags = 0, + .buf = buf, .len = 2 }; + + if (i2c_transfer(priv->i2c, &msg, 1) != 1) { + printk(KERN_WARNING "mt2131 I2C write failed\n"); + return -EREMOTEIO; + } + return 0; +} + +static int mt2131_writeregs(struct mt2131_priv *priv,u8 *buf, u8 len) +{ + struct i2c_msg msg = { .addr = priv->cfg->i2c_address, + .flags = 0, .buf = buf, .len = len }; + + if (i2c_transfer(priv->i2c, &msg, 1) != 1) { + printk(KERN_WARNING "mt2131 I2C write failed (len=%i)\n", + (int)len); + return -EREMOTEIO; + } + return 0; +} + +static int mt2131_set_params(struct dvb_frontend *fe, + struct dvb_frontend_parameters *params) +{ + struct mt2131_priv *priv; + int ret=0, i; + u32 freq; + u8 if_band_center; + u32 f_lo1, f_lo2; + u32 div1, num1, div2, num2; + u8 b[8]; + u8 lockval = 0; + + priv = fe->tuner_priv; + if (fe->ops.info.type == FE_OFDM) + priv->bandwidth = params->u.ofdm.bandwidth; + else + priv->bandwidth = 0; + + freq = params->frequency / 1000; // Hz -> kHz + dprintk(1, "%s() freq=%d\n", __func__, freq); + + f_lo1 = freq + MT2131_IF1 * 1000; + f_lo1 = (f_lo1 / 250) * 250; + f_lo2 = f_lo1 - freq - MT2131_IF2; + + priv->frequency = (f_lo1 - f_lo2 - MT2131_IF2) * 1000; + + /* Frequency LO1 = 16MHz * (DIV1 + NUM1/8192 ) */ + num1 = f_lo1 * 64 / (MT2131_FREF / 128); + div1 = num1 / 8192; + num1 &= 0x1fff; + + /* Frequency LO2 = 16MHz * (DIV2 + NUM2/8192 ) */ + num2 = f_lo2 * 64 / (MT2131_FREF / 128); + div2 = num2 / 8192; + num2 &= 0x1fff; + + if (freq <= 82500) if_band_center = 0x00; else + if (freq <= 137500) if_band_center = 0x01; else + if (freq <= 192500) if_band_center = 0x02; else + if (freq <= 247500) if_band_center = 0x03; else + if (freq <= 302500) if_band_center = 0x04; else + if (freq <= 357500) if_band_center = 0x05; else + if (freq <= 412500) if_band_center = 0x06; else + if (freq <= 467500) if_band_center = 0x07; else + if (freq <= 522500) if_band_center = 0x08; else + if (freq <= 577500) if_band_center = 0x09; else + if (freq <= 632500) if_band_center = 0x0A; else + if (freq <= 687500) if_band_center = 0x0B; else + if (freq <= 742500) if_band_center = 0x0C; else + if (freq <= 797500) if_band_center = 0x0D; else + if (freq <= 852500) if_band_center = 0x0E; else + if (freq <= 907500) if_band_center = 0x0F; else + if (freq <= 962500) if_band_center = 0x10; else + if (freq <= 1017500) if_band_center = 0x11; else + if (freq <= 1072500) if_band_center = 0x12; else if_band_center = 0x13; + + b[0] = 1; + b[1] = (num1 >> 5) & 0xFF; + b[2] = (num1 & 0x1F); + b[3] = div1; + b[4] = (num2 >> 5) & 0xFF; + b[5] = num2 & 0x1F; + b[6] = div2; + + dprintk(1, "IF1: %dMHz IF2: %dMHz\n", MT2131_IF1, MT2131_IF2); + dprintk(1, "PLL freq=%dkHz band=%d\n", (int)freq, (int)if_band_center); + dprintk(1, "PLL f_lo1=%dkHz f_lo2=%dkHz\n", (int)f_lo1, (int)f_lo2); + dprintk(1, "PLL div1=%d num1=%d div2=%d num2=%d\n", + (int)div1, (int)num1, (int)div2, (int)num2); + dprintk(1, "PLL [1..6]: %2x %2x %2x %2x %2x %2x\n", + (int)b[1], (int)b[2], (int)b[3], (int)b[4], (int)b[5], + (int)b[6]); + + ret = mt2131_writeregs(priv,b,7); + if (ret < 0) + return ret; + + mt2131_writereg(priv, 0x0b, if_band_center); + + /* Wait for lock */ + i = 0; + do { + mt2131_readreg(priv, 0x08, &lockval); + if ((lockval & 0x88) == 0x88) + break; + msleep(4); + i++; + } while (i < 10); + + return ret; +} + +static int mt2131_get_frequency(struct dvb_frontend *fe, u32 *frequency) +{ + struct mt2131_priv *priv = fe->tuner_priv; + dprintk(1, "%s()\n", __func__); + *frequency = priv->frequency; + return 0; +} + +static int mt2131_get_bandwidth(struct dvb_frontend *fe, u32 *bandwidth) +{ + struct mt2131_priv *priv = fe->tuner_priv; + dprintk(1, "%s()\n", __func__); + *bandwidth = priv->bandwidth; + return 0; +} + +static int mt2131_get_status(struct dvb_frontend *fe, u32 *status) +{ + struct mt2131_priv *priv = fe->tuner_priv; + u8 lock_status = 0; + u8 afc_status = 0; + + *status = 0; + + mt2131_readreg(priv, 0x08, &lock_status); + if ((lock_status & 0x88) == 0x88) + *status = TUNER_STATUS_LOCKED; + + mt2131_readreg(priv, 0x09, &afc_status); + dprintk(1, "%s() - LO Status = 0x%x, AFC Status = 0x%x\n", + __func__, lock_status, afc_status); + + return 0; +} + +static int mt2131_init(struct dvb_frontend *fe) +{ + struct mt2131_priv *priv = fe->tuner_priv; + int ret; + dprintk(1, "%s()\n", __func__); + + if ((ret = mt2131_writeregs(priv, mt2131_config1, + sizeof(mt2131_config1))) < 0) + return ret; + + mt2131_writereg(priv, 0x0b, 0x09); + mt2131_writereg(priv, 0x15, 0x47); + mt2131_writereg(priv, 0x07, 0xf2); + mt2131_writereg(priv, 0x0b, 0x01); + + if ((ret = mt2131_writeregs(priv, mt2131_config2, + sizeof(mt2131_config2))) < 0) + return ret; + + return ret; +} + +static int mt2131_release(struct dvb_frontend *fe) +{ + dprintk(1, "%s()\n", __func__); + kfree(fe->tuner_priv); + fe->tuner_priv = NULL; + return 0; +} + +static const struct dvb_tuner_ops mt2131_tuner_ops = { + .info = { + .name = "Microtune MT2131", + .frequency_min = 48000000, + .frequency_max = 860000000, + .frequency_step = 50000, + }, + + .release = mt2131_release, + .init = mt2131_init, + + .set_params = mt2131_set_params, + .get_frequency = mt2131_get_frequency, + .get_bandwidth = mt2131_get_bandwidth, + .get_status = mt2131_get_status +}; + +struct dvb_frontend * mt2131_attach(struct dvb_frontend *fe, + struct i2c_adapter *i2c, + struct mt2131_config *cfg, u16 if1) +{ + struct mt2131_priv *priv = NULL; + u8 id = 0; + + dprintk(1, "%s()\n", __func__); + + priv = kzalloc(sizeof(struct mt2131_priv), GFP_KERNEL); + if (priv == NULL) + return NULL; + + priv->cfg = cfg; + priv->bandwidth = 6000000; /* 6MHz */ + priv->i2c = i2c; + + if (mt2131_readreg(priv, 0, &id) != 0) { + kfree(priv); + return NULL; + } + if ( (id != 0x3E) && (id != 0x3F) ) { + printk(KERN_ERR "MT2131: Device not found at addr 0x%02x\n", + cfg->i2c_address); + kfree(priv); + return NULL; + } + + printk(KERN_INFO "MT2131: successfully identified at address 0x%02x\n", + cfg->i2c_address); + memcpy(&fe->ops.tuner_ops, &mt2131_tuner_ops, + sizeof(struct dvb_tuner_ops)); + + fe->tuner_priv = priv; + return fe; +} +EXPORT_SYMBOL(mt2131_attach); + +MODULE_AUTHOR("Steven Toth"); +MODULE_DESCRIPTION("Microtune MT2131 silicon tuner driver"); +MODULE_LICENSE("GPL"); + +/* + * Local variables: + * c-basic-offset: 8 + */ diff --git a/linux/drivers/media/common/tuners/mt2131.h b/linux/drivers/media/common/tuners/mt2131.h new file mode 100644 index 000000000..606d8576b --- /dev/null +++ b/linux/drivers/media/common/tuners/mt2131.h @@ -0,0 +1,54 @@ +/* + * Driver for Microtune MT2131 "QAM/8VSB single chip tuner" + * + * Copyright (c) 2006 Steven Toth + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#ifndef __MT2131_H__ +#define __MT2131_H__ + +struct dvb_frontend; +struct i2c_adapter; + +struct mt2131_config { + u8 i2c_address; + u8 clock_out; /* 0 = off, 1 = CLK/4, 2 = CLK/2, 3 = CLK/1 */ +}; + +#if defined(CONFIG_DVB_TUNER_MT2131) || (defined(CONFIG_DVB_TUNER_MT2131_MODULE) && defined(MODULE)) +extern struct dvb_frontend* mt2131_attach(struct dvb_frontend *fe, + struct i2c_adapter *i2c, + struct mt2131_config *cfg, + u16 if1); +#else +static inline struct dvb_frontend* mt2131_attach(struct dvb_frontend *fe, + struct i2c_adapter *i2c, + struct mt2131_config *cfg, + u16 if1) +{ + printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__); + return NULL; +} +#endif /* CONFIG_DVB_TUNER_MT2131 */ + +#endif /* __MT2131_H__ */ + +/* + * Local variables: + * c-basic-offset: 8 + */ diff --git a/linux/drivers/media/common/tuners/mt2131_priv.h b/linux/drivers/media/common/tuners/mt2131_priv.h new file mode 100644 index 000000000..e930759c2 --- /dev/null +++ b/linux/drivers/media/common/tuners/mt2131_priv.h @@ -0,0 +1,49 @@ +/* + * Driver for Microtune MT2131 "QAM/8VSB single chip tuner" + * + * Copyright (c) 2006 Steven Toth + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#ifndef __MT2131_PRIV_H__ +#define __MT2131_PRIV_H__ + +/* Regs */ +#define MT2131_PWR 0x07 +#define MT2131_UPC_1 0x0b +#define MT2131_AGC_RL 0x10 +#define MT2131_MISC_2 0x15 + +/* frequency values in KHz */ +#define MT2131_IF1 1220 +#define MT2131_IF2 44000 +#define MT2131_FREF 16000 + +struct mt2131_priv { + struct mt2131_config *cfg; + struct i2c_adapter *i2c; + + u32 frequency; + u32 bandwidth; +}; + +#endif /* __MT2131_PRIV_H__ */ + +/* + * Local variables: + * c-basic-offset: 8 + */ diff --git a/linux/drivers/media/common/tuners/mt2266.c b/linux/drivers/media/common/tuners/mt2266.c new file mode 100644 index 000000000..9927a1a55 --- /dev/null +++ b/linux/drivers/media/common/tuners/mt2266.c @@ -0,0 +1,352 @@ +/* + * Driver for Microtune MT2266 "Direct conversion low power broadband tuner" + * + * Copyright (c) 2007 Olivier DANET + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include "compat.h" + +#include "dvb_frontend.h" +#include "mt2266.h" + +#define I2C_ADDRESS 0x60 + +#define REG_PART_REV 0 +#define REG_TUNE 1 +#define REG_BAND 6 +#define REG_BANDWIDTH 8 +#define REG_LOCK 0x12 + +#define PART_REV 0x85 + +struct mt2266_priv { + struct mt2266_config *cfg; + struct i2c_adapter *i2c; + + u32 frequency; + u32 bandwidth; + u8 band; +}; + +#define MT2266_VHF 1 +#define MT2266_UHF 0 + +/* Here, frequencies are expressed in kiloHertz to avoid 32 bits overflows */ + +static int debug; +module_param(debug, int, 0644); +MODULE_PARM_DESC(debug, "Turn on/off debugging (default:off)."); + +#define dprintk(args...) do { if (debug) {printk(KERN_DEBUG "MT2266: " args); printk("\n"); }} while (0) + +// Reads a single register +static int mt2266_readreg(struct mt2266_priv *priv, u8 reg, u8 *val) +{ + struct i2c_msg msg[2] = { + { .addr = priv->cfg->i2c_address, .flags = 0, .buf = ®, .len = 1 }, + { .addr = priv->cfg->i2c_address, .flags = I2C_M_RD, .buf = val, .len = 1 }, + }; + if (i2c_transfer(priv->i2c, msg, 2) != 2) { + printk(KERN_WARNING "MT2266 I2C read failed\n"); + return -EREMOTEIO; + } + return 0; +} + +// Writes a single register +static int mt2266_writereg(struct mt2266_priv *priv, u8 reg, u8 val) +{ + u8 buf[2] = { reg, val }; + struct i2c_msg msg = { + .addr = priv->cfg->i2c_address, .flags = 0, .buf = buf, .len = 2 + }; + if (i2c_transfer(priv->i2c, &msg, 1) != 1) { + printk(KERN_WARNING "MT2266 I2C write failed\n"); + return -EREMOTEIO; + } + return 0; +} + +// Writes a set of consecutive registers +static int mt2266_writeregs(struct mt2266_priv *priv,u8 *buf, u8 len) +{ + struct i2c_msg msg = { + .addr = priv->cfg->i2c_address, .flags = 0, .buf = buf, .len = len + }; + if (i2c_transfer(priv->i2c, &msg, 1) != 1) { + printk(KERN_WARNING "MT2266 I2C write failed (len=%i)\n",(int)len); + return -EREMOTEIO; + } + return 0; +} + +// Initialisation sequences +static u8 mt2266_init1[] = { REG_TUNE, 0x00, 0x00, 0x28, + 0x00, 0x52, 0x99, 0x3f }; + +static u8 mt2266_init2[] = { + 0x17, 0x6d, 0x71, 0x61, 0xc0, 0xbf, 0xff, 0xdc, 0x00, 0x0a, 0xd4, + 0x03, 0x64, 0x64, 0x64, 0x64, 0x22, 0xaa, 0xf2, 0x1e, 0x80, 0x14, + 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x7f, 0x5e, 0x3f, 0xff, 0xff, + 0xff, 0x00, 0x77, 0x0f, 0x2d +}; + +static u8 mt2266_init_8mhz[] = { REG_BANDWIDTH, 0x22, 0x22, 0x22, 0x22, + 0x22, 0x22, 0x22, 0x22 }; + +static u8 mt2266_init_7mhz[] = { REG_BANDWIDTH, 0x32, 0x32, 0x32, 0x32, + 0x32, 0x32, 0x32, 0x32 }; + +static u8 mt2266_init_6mhz[] = { REG_BANDWIDTH, 0xa7, 0xa7, 0xa7, 0xa7, + 0xa7, 0xa7, 0xa7, 0xa7 }; + +static u8 mt2266_uhf[] = { 0x1d, 0xdc, 0x00, 0x0a, 0xd4, 0x03, 0x64, 0x64, + 0x64, 0x64, 0x22, 0xaa, 0xf2, 0x1e, 0x80, 0x14 }; + +static u8 mt2266_vhf[] = { 0x1d, 0xfe, 0x00, 0x00, 0xb4, 0x03, 0xa5, 0xa5, + 0xa5, 0xa5, 0x82, 0xaa, 0xf1, 0x17, 0x80, 0x1f }; + +#define FREF 30000 // Quartz oscillator 30 MHz + +static int mt2266_set_params(struct dvb_frontend *fe, struct dvb_frontend_parameters *params) +{ + struct mt2266_priv *priv; + int ret=0; + u32 freq; + u32 tune; + u8 lnaband; + u8 b[10]; + int i; + u8 band; + + priv = fe->tuner_priv; + + freq = params->frequency / 1000; // Hz -> kHz + if (freq < 470000 && freq > 230000) + return -EINVAL; /* Gap between VHF and UHF bands */ + priv->bandwidth = (fe->ops.info.type == FE_OFDM) ? params->u.ofdm.bandwidth : 0; + priv->frequency = freq * 1000; + + tune = 2 * freq * (8192/16) / (FREF/16); + band = (freq < 300000) ? MT2266_VHF : MT2266_UHF; + if (band == MT2266_VHF) + tune *= 2; + + switch (params->u.ofdm.bandwidth) { + case BANDWIDTH_6_MHZ: + mt2266_writeregs(priv, mt2266_init_6mhz, + sizeof(mt2266_init_6mhz)); + break; + case BANDWIDTH_7_MHZ: + mt2266_writeregs(priv, mt2266_init_7mhz, + sizeof(mt2266_init_7mhz)); + break; + case BANDWIDTH_8_MHZ: + default: + mt2266_writeregs(priv, mt2266_init_8mhz, + sizeof(mt2266_init_8mhz)); + break; + } + + if (band == MT2266_VHF && priv->band == MT2266_UHF) { + dprintk("Switch from UHF to VHF"); + mt2266_writereg(priv, 0x05, 0x04); + mt2266_writereg(priv, 0x19, 0x61); + mt2266_writeregs(priv, mt2266_vhf, sizeof(mt2266_vhf)); + } else if (band == MT2266_UHF && priv->band == MT2266_VHF) { + dprintk("Switch from VHF to UHF"); + mt2266_writereg(priv, 0x05, 0x52); + mt2266_writereg(priv, 0x19, 0x61); + mt2266_writeregs(priv, mt2266_uhf, sizeof(mt2266_uhf)); + } + msleep(10); + + if (freq <= 495000) + lnaband = 0xEE; + else if (freq <= 525000) + lnaband = 0xDD; + else if (freq <= 550000) + lnaband = 0xCC; + else if (freq <= 580000) + lnaband = 0xBB; + else if (freq <= 605000) + lnaband = 0xAA; + else if (freq <= 630000) + lnaband = 0x99; + else if (freq <= 655000) + lnaband = 0x88; + else if (freq <= 685000) + lnaband = 0x77; + else if (freq <= 710000) + lnaband = 0x66; + else if (freq <= 735000) + lnaband = 0x55; + else if (freq <= 765000) + lnaband = 0x44; + else if (freq <= 802000) + lnaband = 0x33; + else if (freq <= 840000) + lnaband = 0x22; + else + lnaband = 0x11; + + b[0] = REG_TUNE; + b[1] = (tune >> 8) & 0x1F; + b[2] = tune & 0xFF; + b[3] = tune >> 13; + mt2266_writeregs(priv,b,4); + + dprintk("set_parms: tune=%d band=%d %s", + (int) tune, (int) lnaband, + (band == MT2266_UHF) ? "UHF" : "VHF"); + dprintk("set_parms: [1..3]: %2x %2x %2x", + (int) b[1], (int) b[2], (int)b[3]); + + if (band == MT2266_UHF) { + b[0] = 0x05; + b[1] = (priv->band == MT2266_VHF) ? 0x52 : 0x62; + b[2] = lnaband; + mt2266_writeregs(priv, b, 3); + } + + /* Wait for pll lock or timeout */ + i = 0; + do { + mt2266_readreg(priv,REG_LOCK,b); + if (b[0] & 0x40) + break; + msleep(10); + i++; + } while (i<10); + dprintk("Lock when i=%i",(int)i); + + if (band == MT2266_UHF && priv->band == MT2266_VHF) + mt2266_writereg(priv, 0x05, 0x62); + + priv->band = band; + + return ret; +} + +static void mt2266_calibrate(struct mt2266_priv *priv) +{ + mt2266_writereg(priv, 0x11, 0x03); + mt2266_writereg(priv, 0x11, 0x01); + mt2266_writeregs(priv, mt2266_init1, sizeof(mt2266_init1)); + mt2266_writeregs(priv, mt2266_init2, sizeof(mt2266_init2)); + mt2266_writereg(priv, 0x33, 0x5e); + mt2266_writereg(priv, 0x10, 0x10); + mt2266_writereg(priv, 0x10, 0x00); + mt2266_writeregs(priv, mt2266_init_8mhz, sizeof(mt2266_init_8mhz)); + msleep(25); + mt2266_writereg(priv, 0x17, 0x6d); + mt2266_writereg(priv, 0x1c, 0x00); + msleep(75); + mt2266_writereg(priv, 0x17, 0x6d); + mt2266_writereg(priv, 0x1c, 0xff); +} + +static int mt2266_get_frequency(struct dvb_frontend *fe, u32 *frequency) +{ + struct mt2266_priv *priv = fe->tuner_priv; + *frequency = priv->frequency; + return 0; +} + +static int mt2266_get_bandwidth(struct dvb_frontend *fe, u32 *bandwidth) +{ + struct mt2266_priv *priv = fe->tuner_priv; + *bandwidth = priv->bandwidth; + return 0; +} + +static int mt2266_init(struct dvb_frontend *fe) +{ + int ret; + struct mt2266_priv *priv = fe->tuner_priv; + ret = mt2266_writereg(priv, 0x17, 0x6d); + if (ret < 0) + return ret; + ret = mt2266_writereg(priv, 0x1c, 0xff); + if (ret < 0) + return ret; + return 0; +} + +static int mt2266_sleep(struct dvb_frontend *fe) +{ + struct mt2266_priv *priv = fe->tuner_priv; + mt2266_writereg(priv, 0x17, 0x6d); + mt2266_writereg(priv, 0x1c, 0x00); + return 0; +} + +static int mt2266_release(struct dvb_frontend *fe) +{ + kfree(fe->tuner_priv); + fe->tuner_priv = NULL; + return 0; +} + +static const struct dvb_tuner_ops mt2266_tuner_ops = { + .info = { + .name = "Microtune MT2266", + .frequency_min = 174000000, + .frequency_max = 862000000, + .frequency_step = 50000, + }, + .release = mt2266_release, + .init = mt2266_init, + .sleep = mt2266_sleep, + .set_params = mt2266_set_params, + .get_frequency = mt2266_get_frequency, + .get_bandwidth = mt2266_get_bandwidth +}; + +struct dvb_frontend * mt2266_attach(struct dvb_frontend *fe, struct i2c_adapter *i2c, struct mt2266_config *cfg) +{ + struct mt2266_priv *priv = NULL; + u8 id = 0; + + priv = kzalloc(sizeof(struct mt2266_priv), GFP_KERNEL); + if (priv == NULL) + return NULL; + + priv->cfg = cfg; + priv->i2c = i2c; + priv->band = MT2266_UHF; + + if (mt2266_readreg(priv, 0, &id)) { + kfree(priv); + return NULL; + } + if (id != PART_REV) { + kfree(priv); + return NULL; + } + printk(KERN_INFO "MT2266: successfully identified\n"); + memcpy(&fe->ops.tuner_ops, &mt2266_tuner_ops, sizeof(struct dvb_tuner_ops)); + + fe->tuner_priv = priv; + mt2266_calibrate(priv); + return fe; +} +EXPORT_SYMBOL(mt2266_attach); + +MODULE_AUTHOR("Olivier DANET"); +MODULE_DESCRIPTION("Microtune MT2266 silicon tuner driver"); +MODULE_LICENSE("GPL"); diff --git a/linux/drivers/media/common/tuners/mt2266.h b/linux/drivers/media/common/tuners/mt2266.h new file mode 100644 index 000000000..c5113efe3 --- /dev/null +++ b/linux/drivers/media/common/tuners/mt2266.h @@ -0,0 +1,37 @@ +/* + * Driver for Microtune MT2266 "Direct conversion low power broadband tuner" + * + * Copyright (c) 2007 Olivier DANET + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef MT2266_H +#define MT2266_H + +struct dvb_frontend; +struct i2c_adapter; + +struct mt2266_config { + u8 i2c_address; +}; + +#if defined(CONFIG_DVB_TUNER_MT2266) || (defined(CONFIG_DVB_TUNER_MT2266_MODULE) && defined(MODULE)) +extern struct dvb_frontend * mt2266_attach(struct dvb_frontend *fe, struct i2c_adapter *i2c, struct mt2266_config *cfg); +#else +static inline struct dvb_frontend * mt2266_attach(struct dvb_frontend *fe, struct i2c_adapter *i2c, struct mt2266_config *cfg) +{ + printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__); + return NULL; +} +#endif // CONFIG_DVB_TUNER_MT2266 + +#endif diff --git a/linux/drivers/media/common/tuners/qt1010.c b/linux/drivers/media/common/tuners/qt1010.c new file mode 100644 index 000000000..4afed44ab --- /dev/null +++ b/linux/drivers/media/common/tuners/qt1010.c @@ -0,0 +1,489 @@ +/* + * Driver for Quantek QT1010 silicon tuner + * + * Copyright (C) 2006 Antti Palosaari + * Aapo Tahkola + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ +#include "qt1010.h" +#include "compat.h" +#include "qt1010_priv.h" + +static int debug; +module_param(debug, int, 0644); +MODULE_PARM_DESC(debug, "Turn on/off debugging (default:off)."); + +#define dprintk(args...) \ + do { \ + if (debug) printk(KERN_DEBUG "QT1010: " args); \ + } while (0) + +/* read single register */ +static int qt1010_readreg(struct qt1010_priv *priv, u8 reg, u8 *val) +{ + struct i2c_msg msg[2] = { + { .addr = priv->cfg->i2c_address, + .flags = 0, .buf = ®, .len = 1 }, + { .addr = priv->cfg->i2c_address, + .flags = I2C_M_RD, .buf = val, .len = 1 }, + }; + + if (i2c_transfer(priv->i2c, msg, 2) != 2) { + printk(KERN_WARNING "qt1010 I2C read failed\n"); + return -EREMOTEIO; + } + return 0; +} + +/* write single register */ +static int qt1010_writereg(struct qt1010_priv *priv, u8 reg, u8 val) +{ + u8 buf[2] = { reg, val }; + struct i2c_msg msg = { .addr = priv->cfg->i2c_address, + .flags = 0, .buf = buf, .len = 2 }; + + if (i2c_transfer(priv->i2c, &msg, 1) != 1) { + printk(KERN_WARNING "qt1010 I2C write failed\n"); + return -EREMOTEIO; + } + return 0; +} + +/* dump all registers */ +static void qt1010_dump_regs(struct qt1010_priv *priv) +{ + char buf[52], buf2[4]; + u8 reg, val; + + for (reg = 0; ; reg++) { + if (reg % 16 == 0) { + if (reg) + printk("%s\n", buf); + sprintf(buf, "%02x: ", reg); + } + if (qt1010_readreg(priv, reg, &val) == 0) + sprintf(buf2, "%02x ", val); + else + strcpy(buf2, "-- "); + strcat(buf, buf2); + if (reg == 0x2f) + break; + } + printk("%s\n", buf); +} + +static int qt1010_set_params(struct dvb_frontend *fe, + struct dvb_frontend_parameters *params) +{ + struct qt1010_priv *priv; + int err; + u32 freq, div, mod1, mod2; + u8 i, tmpval, reg05; + qt1010_i2c_oper_t rd[48] = { + { QT1010_WR, 0x01, 0x80 }, + { QT1010_WR, 0x02, 0x3f }, + { QT1010_WR, 0x05, 0xff }, /* 02 c write */ + { QT1010_WR, 0x06, 0x44 }, + { QT1010_WR, 0x07, 0xff }, /* 04 c write */ + { QT1010_WR, 0x08, 0x08 }, + { QT1010_WR, 0x09, 0xff }, /* 06 c write */ + { QT1010_WR, 0x0a, 0xff }, /* 07 c write */ + { QT1010_WR, 0x0b, 0xff }, /* 08 c write */ + { QT1010_WR, 0x0c, 0xe1 }, + { QT1010_WR, 0x1a, 0xff }, /* 10 c write */ + { QT1010_WR, 0x1b, 0x00 }, + { QT1010_WR, 0x1c, 0x89 }, + { QT1010_WR, 0x11, 0xff }, /* 13 c write */ + { QT1010_WR, 0x12, 0xff }, /* 14 c write */ + { QT1010_WR, 0x22, 0xff }, /* 15 c write */ + { QT1010_WR, 0x1e, 0x00 }, + { QT1010_WR, 0x1e, 0xd0 }, + { QT1010_RD, 0x22, 0xff }, /* 16 c read */ + { QT1010_WR, 0x1e, 0x00 }, + { QT1010_RD, 0x05, 0xff }, /* 20 c read */ + { QT1010_RD, 0x22, 0xff }, /* 21 c read */ + { QT1010_WR, 0x23, 0xd0 }, + { QT1010_WR, 0x1e, 0x00 }, + { QT1010_WR, 0x1e, 0xe0 }, + { QT1010_RD, 0x23, 0xff }, /* 25 c read */ + { QT1010_RD, 0x23, 0xff }, /* 26 c read */ + { QT1010_WR, 0x1e, 0x00 }, + { QT1010_WR, 0x24, 0xd0 }, + { QT1010_WR, 0x1e, 0x00 }, + { QT1010_WR, 0x1e, 0xf0 }, + { QT1010_RD, 0x24, 0xff }, /* 31 c read */ + { QT1010_WR, 0x1e, 0x00 }, + { QT1010_WR, 0x14, 0x7f }, + { QT1010_WR, 0x15, 0x7f }, + { QT1010_WR, 0x05, 0xff }, /* 35 c write */ + { QT1010_WR, 0x06, 0x00 }, + { QT1010_WR, 0x15, 0x1f }, + { QT1010_WR, 0x16, 0xff }, + { QT1010_WR, 0x18, 0xff }, + { QT1010_WR, 0x1f, 0xff }, /* 40 c write */ + { QT1010_WR, 0x20, 0xff }, /* 41 c write */ + { QT1010_WR, 0x21, 0x53 }, + { QT1010_WR, 0x25, 0xff }, /* 43 c write */ + { QT1010_WR, 0x26, 0x15 }, + { QT1010_WR, 0x00, 0xff }, /* 45 c write */ + { QT1010_WR, 0x02, 0x00 }, + { QT1010_WR, 0x01, 0x00 } + }; + +#define FREQ1 32000000 /* 32 MHz */ +#define FREQ2 4000000 /* 4 MHz Quartz oscillator in the stick? */ + + priv = fe->tuner_priv; + freq = params->frequency; + div = (freq + QT1010_OFFSET) / QT1010_STEP; + freq = (div * QT1010_STEP) - QT1010_OFFSET; + mod1 = (freq + QT1010_OFFSET) % FREQ1; + mod2 = (freq + QT1010_OFFSET) % FREQ2; + priv->bandwidth = + (fe->ops.info.type == FE_OFDM) ? params->u.ofdm.bandwidth : 0; + priv->frequency = freq; + + if (fe->ops.i2c_gate_ctrl) + fe->ops.i2c_gate_ctrl(fe, 1); /* open i2c_gate */ + + /* reg 05 base value */ + if (freq < 290000000) reg05 = 0x14; /* 290 MHz */ + else if (freq < 610000000) reg05 = 0x34; /* 610 MHz */ + else if (freq < 802000000) reg05 = 0x54; /* 802 MHz */ + else reg05 = 0x74; + + /* 0x5 */ + rd[2].val = reg05; + + /* 07 - set frequency: 32 MHz scale */ + rd[4].val = (freq + QT1010_OFFSET) / FREQ1; + + /* 09 - changes every 8/24 MHz */ + if (mod1 < 8000000) rd[6].val = 0x1d; + else rd[6].val = 0x1c; + + /* 0a - set frequency: 4 MHz scale (max 28 MHz) */ + if (mod1 < 1*FREQ2) rd[7].val = 0x09; /* +0 MHz */ + else if (mod1 < 2*FREQ2) rd[7].val = 0x08; /* +4 MHz */ + else if (mod1 < 3*FREQ2) rd[7].val = 0x0f; /* +8 MHz */ + else if (mod1 < 4*FREQ2) rd[7].val = 0x0e; /* +12 MHz */ + else if (mod1 < 5*FREQ2) rd[7].val = 0x0d; /* +16 MHz */ + else if (mod1 < 6*FREQ2) rd[7].val = 0x0c; /* +20 MHz */ + else if (mod1 < 7*FREQ2) rd[7].val = 0x0b; /* +24 MHz */ + else rd[7].val = 0x0a; /* +28 MHz */ + + /* 0b - changes every 2/2 MHz */ + if (mod2 < 2000000) rd[8].val = 0x45; + else rd[8].val = 0x44; + + /* 1a - set frequency: 125 kHz scale (max 3875 kHz)*/ + tmpval = 0x78; /* byte, overflows intentionally */ + rd[10].val = tmpval-((mod2/QT1010_STEP)*0x08); + + /* 11 */ + rd[13].val = 0xfd; /* TODO: correct value calculation */ + + /* 12 */ + rd[14].val = 0x91; /* TODO: correct value calculation */ + + /* 22 */ + if (freq < 450000000) rd[15].val = 0xd0; /* 450 MHz */ + else if (freq < 482000000) rd[15].val = 0xd1; /* 482 MHz */ + else if (freq < 514000000) rd[15].val = 0xd4; /* 514 MHz */ + else if (freq < 546000000) rd[15].val = 0xd7; /* 546 MHz */ + else if (freq < 610000000) rd[15].val = 0xda; /* 610 MHz */ + else rd[15].val = 0xd0; + + /* 05 */ + rd[35].val = (reg05 & 0xf0); + + /* 1f */ + if (mod1 < 8000000) tmpval = 0x00; + else if (mod1 < 12000000) tmpval = 0x01; + else if (mod1 < 16000000) tmpval = 0x02; + else if (mod1 < 24000000) tmpval = 0x03; + else if (mod1 < 28000000) tmpval = 0x04; + else tmpval = 0x05; + rd[40].val = (priv->reg1f_init_val + 0x0e + tmpval); + + /* 20 */ + if (mod1 < 8000000) tmpval = 0x00; + else if (mod1 < 12000000) tmpval = 0x01; + else if (mod1 < 20000000) tmpval = 0x02; + else if (mod1 < 24000000) tmpval = 0x03; + else if (mod1 < 28000000) tmpval = 0x04; + else tmpval = 0x05; + rd[41].val = (priv->reg20_init_val + 0x0d + tmpval); + + /* 25 */ + rd[43].val = priv->reg25_init_val; + + /* 00 */ + rd[45].val = 0x92; /* TODO: correct value calculation */ + + dprintk("freq:%u 05:%02x 07:%02x 09:%02x 0a:%02x 0b:%02x " \ + "1a:%02x 11:%02x 12:%02x 22:%02x 05:%02x 1f:%02x " \ + "20:%02x 25:%02x 00:%02x", \ + freq, rd[2].val, rd[4].val, rd[6].val, rd[7].val, rd[8].val, \ + rd[10].val, rd[13].val, rd[14].val, rd[15].val, rd[35].val, \ + rd[40].val, rd[41].val, rd[43].val, rd[45].val); + + for (i = 0; i < ARRAY_SIZE(rd); i++) { + if (rd[i].oper == QT1010_WR) { + err = qt1010_writereg(priv, rd[i].reg, rd[i].val); + } else { /* read is required to proper locking */ + err = qt1010_readreg(priv, rd[i].reg, &tmpval); + } + if (err) return err; + } + + if (debug) + qt1010_dump_regs(priv); + + if (fe->ops.i2c_gate_ctrl) + fe->ops.i2c_gate_ctrl(fe, 0); /* close i2c_gate */ + + return 0; +} + +static int qt1010_init_meas1(struct qt1010_priv *priv, + u8 oper, u8 reg, u8 reg_init_val, u8 *retval) +{ + u8 i, val1, val2; + int err; + + qt1010_i2c_oper_t i2c_data[] = { + { QT1010_WR, reg, reg_init_val }, + { QT1010_WR, 0x1e, 0x00 }, + { QT1010_WR, 0x1e, oper }, + { QT1010_RD, reg, 0xff } + }; + + for (i = 0; i < ARRAY_SIZE(i2c_data); i++) { + if (i2c_data[i].oper == QT1010_WR) { + err = qt1010_writereg(priv, i2c_data[i].reg, + i2c_data[i].val); + } else { + err = qt1010_readreg(priv, i2c_data[i].reg, &val2); + } + if (err) return err; + } + + do { + val1 = val2; + err = qt1010_readreg(priv, reg, &val2); + if (err) return err; + dprintk("compare reg:%02x %02x %02x", reg, val1, val2); + } while (val1 != val2); + *retval = val1; + + return qt1010_writereg(priv, 0x1e, 0x00); +} + +static u8 qt1010_init_meas2(struct qt1010_priv *priv, + u8 reg_init_val, u8 *retval) +{ + u8 i, val; + int err; + qt1010_i2c_oper_t i2c_data[] = { + { QT1010_WR, 0x07, reg_init_val }, + { QT1010_WR, 0x22, 0xd0 }, + { QT1010_WR, 0x1e, 0x00 }, + { QT1010_WR, 0x1e, 0xd0 }, + { QT1010_RD, 0x22, 0xff }, + { QT1010_WR, 0x1e, 0x00 }, + { QT1010_WR, 0x22, 0xff } + }; + for (i = 0; i < ARRAY_SIZE(i2c_data); i++) { + if (i2c_data[i].oper == QT1010_WR) { + err = qt1010_writereg(priv, i2c_data[i].reg, + i2c_data[i].val); + } else { + err = qt1010_readreg(priv, i2c_data[i].reg, &val); + } + if (err) return err; + } + *retval = val; + return 0; +} + +static int qt1010_init(struct dvb_frontend *fe) +{ + struct qt1010_priv *priv = fe->tuner_priv; + struct dvb_frontend_parameters params; + int err = 0; + u8 i, tmpval, *valptr = NULL; + + qt1010_i2c_oper_t i2c_data[] = { + { QT1010_WR, 0x01, 0x80 }, + { QT1010_WR, 0x0d, 0x84 }, + { QT1010_WR, 0x0e, 0xb7 }, + { QT1010_WR, 0x2a, 0x23 }, + { QT1010_WR, 0x2c, 0xdc }, + { QT1010_M1, 0x25, 0x40 }, /* get reg 25 init value */ + { QT1010_M1, 0x81, 0xff }, /* get reg 25 init value */ + { QT1010_WR, 0x2b, 0x70 }, + { QT1010_WR, 0x2a, 0x23 }, + { QT1010_M1, 0x26, 0x08 }, + { QT1010_M1, 0x82, 0xff }, + { QT1010_WR, 0x05, 0x14 }, + { QT1010_WR, 0x06, 0x44 }, + { QT1010_WR, 0x07, 0x28 }, + { QT1010_WR, 0x08, 0x0b }, + { QT1010_WR, 0x11, 0xfd }, + { QT1010_M1, 0x22, 0x0d }, + { QT1010_M1, 0xd0, 0xff }, + { QT1010_WR, 0x06, 0x40 }, + { QT1010_WR, 0x16, 0xf0 }, + { QT1010_WR, 0x02, 0x38 }, + { QT1010_WR, 0x03, 0x18 }, + { QT1010_WR, 0x20, 0xe0 }, + { QT1010_M1, 0x1f, 0x20 }, /* get reg 1f init value */ + { QT1010_M1, 0x84, 0xff }, /* get reg 1f init value */ + { QT1010_RD, 0x20, 0x20 }, /* get reg 20 init value */ + { QT1010_WR, 0x03, 0x19 }, + { QT1010_WR, 0x02, 0x3f }, + { QT1010_WR, 0x21, 0x53 }, + { QT1010_RD, 0x21, 0xff }, + { QT1010_WR, 0x11, 0xfd }, + { QT1010_WR, 0x05, 0x34 }, + { QT1010_WR, 0x06, 0x44 }, + { QT1010_WR, 0x08, 0x08 } + }; + + if (fe->ops.i2c_gate_ctrl) + fe->ops.i2c_gate_ctrl(fe, 1); /* open i2c_gate */ + + for (i = 0; i < ARRAY_SIZE(i2c_data); i++) { + switch (i2c_data[i].oper) { + case QT1010_WR: + err = qt1010_writereg(priv, i2c_data[i].reg, + i2c_data[i].val); + break; + case QT1010_RD: + if (i2c_data[i].val == 0x20) + valptr = &priv->reg20_init_val; + else + valptr = &tmpval; + err = qt1010_readreg(priv, i2c_data[i].reg, valptr); + break; + case QT1010_M1: + if (i2c_data[i].val == 0x25) + valptr = &priv->reg25_init_val; + else if (i2c_data[i].val == 0x1f) + valptr = &priv->reg1f_init_val; + else + valptr = &tmpval; + err = qt1010_init_meas1(priv, i2c_data[i+1].reg, + i2c_data[i].reg, + i2c_data[i].val, valptr); + i++; + break; + } + if (err) return err; + } + + for (i = 0x31; i < 0x3a; i++) /* 0x31 - 0x39 */ + if ((err = qt1010_init_meas2(priv, i, &tmpval))) + return err; + + params.frequency = 545000000; /* Sigmatek DVB-110 545000000 */ + /* MSI Megasky 580 GL861 533000000 */ + return qt1010_set_params(fe, ¶ms); +} + +static int qt1010_release(struct dvb_frontend *fe) +{ + kfree(fe->tuner_priv); + fe->tuner_priv = NULL; + return 0; +} + +static int qt1010_get_frequency(struct dvb_frontend *fe, u32 *frequency) +{ + struct qt1010_priv *priv = fe->tuner_priv; + *frequency = priv->frequency; + return 0; +} + +static int qt1010_get_bandwidth(struct dvb_frontend *fe, u32 *bandwidth) +{ + struct qt1010_priv *priv = fe->tuner_priv; + *bandwidth = priv->bandwidth; + return 0; +} + +static const struct dvb_tuner_ops qt1010_tuner_ops = { + .info = { + .name = "Quantek QT1010", + .frequency_min = QT1010_MIN_FREQ, + .frequency_max = QT1010_MAX_FREQ, + .frequency_step = QT1010_STEP, + }, + + .release = qt1010_release, + .init = qt1010_init, + /* TODO: implement sleep */ + + .set_params = qt1010_set_params, + .get_frequency = qt1010_get_frequency, + .get_bandwidth = qt1010_get_bandwidth +}; + +struct dvb_frontend * qt1010_attach(struct dvb_frontend *fe, + struct i2c_adapter *i2c, + struct qt1010_config *cfg) +{ + struct qt1010_priv *priv = NULL; + u8 id; + + priv = kzalloc(sizeof(struct qt1010_priv), GFP_KERNEL); + if (priv == NULL) + return NULL; + + priv->cfg = cfg; + priv->i2c = i2c; + + if (fe->ops.i2c_gate_ctrl) + fe->ops.i2c_gate_ctrl(fe, 1); /* open i2c_gate */ + +#if 0 + qt1010_dump_regs(priv); +#endif + + /* Try to detect tuner chip. Probably this is not correct register. */ + if (qt1010_readreg(priv, 0x29, &id) != 0 || (id != 0x39)) { + kfree(priv); + return NULL; + } + + if (fe->ops.i2c_gate_ctrl) + fe->ops.i2c_gate_ctrl(fe, 0); /* close i2c_gate */ + + printk(KERN_INFO "Quantek QT1010 successfully identified.\n"); + memcpy(&fe->ops.tuner_ops, &qt1010_tuner_ops, + sizeof(struct dvb_tuner_ops)); + + fe->tuner_priv = priv; + return fe; +} +EXPORT_SYMBOL(qt1010_attach); + +MODULE_DESCRIPTION("Quantek QT1010 silicon tuner driver"); +MODULE_AUTHOR("Antti Palosaari "); +MODULE_AUTHOR("Aapo Tahkola "); +MODULE_VERSION("0.1"); +MODULE_LICENSE("GPL"); diff --git a/linux/drivers/media/common/tuners/qt1010.h b/linux/drivers/media/common/tuners/qt1010.h new file mode 100644 index 000000000..cff6a7ca5 --- /dev/null +++ b/linux/drivers/media/common/tuners/qt1010.h @@ -0,0 +1,53 @@ +/* + * Driver for Quantek QT1010 silicon tuner + * + * Copyright (C) 2006 Antti Palosaari + * Aapo Tahkola + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#ifndef QT1010_H +#define QT1010_H + +#include "dvb_frontend.h" + +struct qt1010_config { + u8 i2c_address; +}; + +/** + * Attach a qt1010 tuner to the supplied frontend structure. + * + * @param fe frontend to attach to + * @param i2c i2c adapter to use + * @param cfg tuner hw based configuration + * @return fe pointer on success, NULL on failure + */ +#if defined(CONFIG_DVB_TUNER_QT1010) || (defined(CONFIG_DVB_TUNER_QT1010_MODULE) && defined(MODULE)) +extern struct dvb_frontend *qt1010_attach(struct dvb_frontend *fe, + struct i2c_adapter *i2c, + struct qt1010_config *cfg); +#else +static inline struct dvb_frontend *qt1010_attach(struct dvb_frontend *fe, + struct i2c_adapter *i2c, + struct qt1010_config *cfg) +{ + printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__); + return NULL; +} +#endif // CONFIG_DVB_TUNER_QT1010 + +#endif diff --git a/linux/drivers/media/common/tuners/qt1010_priv.h b/linux/drivers/media/common/tuners/qt1010_priv.h new file mode 100644 index 000000000..090cf475f --- /dev/null +++ b/linux/drivers/media/common/tuners/qt1010_priv.h @@ -0,0 +1,105 @@ +/* + * Driver for Quantek QT1010 silicon tuner + * + * Copyright (C) 2006 Antti Palosaari + * Aapo Tahkola + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#ifndef QT1010_PRIV_H +#define QT1010_PRIV_H + +/* +reg def meaning +=== === ======= +00 00 ? +01 a0 ? operation start/stop; start=80, stop=00 +02 00 ? +03 19 ? +04 00 ? +05 00 ? maybe band selection +06 00 ? +07 2b set frequency: 32 MHz scale, n*32 MHz +08 0b ? +09 10 ? changes every 8/24 MHz; values 1d/1c +0a 08 set frequency: 4 MHz scale, n*4 MHz +0b 41 ? changes every 2/2 MHz; values 45/45 +0c e1 ? +0d 94 ? +0e b6 ? +0f 2c ? +10 10 ? +11 f1 ? maybe device specified adjustment +12 11 ? maybe device specified adjustment +13 3f ? +14 1f ? +15 3f ? +16 ff ? +17 ff ? +18 f7 ? +19 80 ? +1a d0 set frequency: 125 kHz scale, n*125 kHz +1b 00 ? +1c 89 ? +1d 00 ? +1e 00 ? looks like operation register; write cmd here, read result from 1f-26 +1f 20 ? chip initialization +20 e0 ? chip initialization +21 20 ? +22 d0 ? +23 d0 ? +24 d0 ? +25 40 ? chip initialization +26 08 ? +27 29 ? +28 55 ? +29 39 ? +2a 13 ? +2b 01 ? +2c ea ? +2d 00 ? +2e 00 ? not used? +2f 00 ? not used? +*/ + +#define QT1010_STEP 125000 /* 125 kHz used by Windows drivers, + hw could be more precise but we don't + know how to use */ +#define QT1010_MIN_FREQ 48000000 /* 48 MHz */ +#define QT1010_MAX_FREQ 860000000 /* 860 MHz */ +#define QT1010_OFFSET 1246000000 /* 1246 MHz */ + +#define QT1010_WR 0 +#define QT1010_RD 1 +#define QT1010_M1 3 + +typedef struct { + u8 oper, reg, val; +} qt1010_i2c_oper_t; + +struct qt1010_priv { + struct qt1010_config *cfg; + struct i2c_adapter *i2c; + + u8 reg1f_init_val; + u8 reg20_init_val; + u8 reg25_init_val; + + u32 frequency; + u32 bandwidth; +}; + +#endif -- cgit v1.2.3 From d914f7c6f9da26e897afbdf438d9f1271bf42240 Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Sat, 26 Apr 2008 13:58:37 -0300 Subject: Forgot to add those patches. From: Mauro Carvalho Chehab kernel-sync: Signed-off-by: Mauro Carvalho Chehab --- linux/drivers/media/common/tuners/Kconfig | 146 +++++++++++++++++++++++++++++ linux/drivers/media/common/tuners/Makefile | 25 +++++ 2 files changed, 171 insertions(+) create mode 100644 linux/drivers/media/common/tuners/Kconfig create mode 100644 linux/drivers/media/common/tuners/Makefile (limited to 'linux/drivers/media/common/tuners') diff --git a/linux/drivers/media/common/tuners/Kconfig b/linux/drivers/media/common/tuners/Kconfig new file mode 100644 index 000000000..e6926e9fa --- /dev/null +++ b/linux/drivers/media/common/tuners/Kconfig @@ -0,0 +1,146 @@ +config DVB_CORE_ATTACH + bool "Load and attach frontend driver modules as needed" + depends on DVB_CORE + depends on MODULES + help + Remove the static dependency of DVB card drivers on all + frontend modules for all possible card variants. Instead, + allow the card drivers to only load the frontend modules + they require. This saves several KBytes of memory. + + Note: You will need module-init-tools v3.2 or later for this feature. + + If unsure say Y. + +config VIDEO_TUNER + tristate + default DVB_CORE || VIDEO_DEV + depends on DVB_CORE || VIDEO_DEV + select TUNER_XC2028 if !VIDEO_TUNER_CUSTOMIZE + select DVB_TUNER_XC5000 if !VIDEO_TUNER_CUSTOMIZE + select TUNER_MT20XX if !VIDEO_TUNER_CUSTOMIZE + select TUNER_TDA8290 if !VIDEO_TUNER_CUSTOMIZE + select TUNER_TEA5761 if !VIDEO_TUNER_CUSTOMIZE + select TUNER_TEA5767 if !VIDEO_TUNER_CUSTOMIZE + select TUNER_SIMPLE if !VIDEO_TUNER_CUSTOMIZE + select TUNER_TDA9887 if !VIDEO_TUNER_CUSTOMIZE + +menuconfig VIDEO_TUNER_CUSTOMIZE + bool "Customize analog and hybrid tuner modules to build" + depends on VIDEO_TUNER + help + This allows the user to deselect tuner drivers unnecessary + for their hardware from the build. Use this option with care + as deselecting tuner drivers which are in fact necessary will + result in V4L/DVB devices which cannot be tuned due to lack of + driver support + + If unsure say N. + +if VIDEO_TUNER_CUSTOMIZE + +config TUNER_SIMPLE + tristate "Simple tuner support" + depends on I2C + select TUNER_TDA9887 + default m if VIDEO_TUNER_CUSTOMIZE + help + Say Y here to include support for various simple tuners. + +config TUNER_TDA8290 + tristate "TDA 8290/8295 + 8275(a)/18271 tuner combo" + depends on I2C + select DVB_TDA827X + select DVB_TDA18271 + default m if VIDEO_TUNER_CUSTOMIZE + help + Say Y here to include support for Philips TDA8290+8275(a) tuner. + +config DVB_TDA827X + tristate "Philips TDA827X silicon tuner" + depends on DVB_CORE && I2C + default m if DVB_FE_CUSTOMISE + help + A DVB-T silicon tuner module. Say Y when you want to support this tuner. + +config DVB_TDA18271 + tristate "NXP TDA18271 silicon tuner" + depends on I2C + default m if DVB_FE_CUSTOMISE + help + A silicon tuner module. Say Y when you want to support this tuner. + +config TUNER_TDA9887 + tristate "TDA 9885/6/7 analog IF demodulator" + depends on I2C + default m if VIDEO_TUNER_CUSTOMIZE + help + Say Y here to include support for Philips TDA9885/6/7 + analog IF demodulator. + +config TUNER_TEA5761 + tristate "TEA 5761 radio tuner (EXPERIMENTAL)" + depends on I2C && EXPERIMENTAL + default m if VIDEO_TUNER_CUSTOMIZE + help + Say Y here to include support for the Philips TEA5761 radio tuner. + +config TUNER_TEA5767 + tristate "TEA 5767 radio tuner" + depends on I2C + default m if VIDEO_TUNER_CUSTOMIZE + help + Say Y here to include support for the Philips TEA5767 radio tuner. + +config TUNER_MT20XX + tristate "Microtune 2032 / 2050 tuners" + depends on I2C + default m if VIDEO_TUNER_CUSTOMIZE + help + Say Y here to include support for the MT2032 / MT2050 tuner. + +config DVB_TUNER_MT2060 + tristate "Microtune MT2060 silicon IF tuner" + depends on I2C + default m if DVB_FE_CUSTOMISE + help + A driver for the silicon IF tuner MT2060 from Microtune. + +config DVB_TUNER_MT2266 + tristate "Microtune MT2266 silicon tuner" + depends on I2C + default m if DVB_FE_CUSTOMISE + help + A driver for the silicon baseband tuner MT2266 from Microtune. + +config DVB_TUNER_MT2131 + tristate "Microtune MT2131 silicon tuner" + depends on I2C + default m if DVB_FE_CUSTOMISE + help + A driver for the silicon baseband tuner MT2131 from Microtune. + +config DVB_TUNER_QT1010 + tristate "Quantek QT1010 silicon tuner" + depends on DVB_CORE && I2C + default m if DVB_FE_CUSTOMISE + help + A driver for the silicon tuner QT1010 from Quantek. + +config TUNER_XC2028 + tristate "XCeive xc2028/xc3028 tuners" + depends on I2C && FW_LOADER + default m if VIDEO_TUNER_CUSTOMIZE + help + Say Y here to include support for the xc2028/xc3028 tuners. + +config DVB_TUNER_XC5000 + tristate "Xceive XC5000 silicon tuner" + depends on I2C + default m if DVB_FE_CUSTOMISE + help + A driver for the silicon tuner XC5000 from Xceive. + This device is only used inside a SiP called togther with a + demodulator for now. + +endif # VIDEO_TUNER_CUSTOMIZE diff --git a/linux/drivers/media/common/tuners/Makefile b/linux/drivers/media/common/tuners/Makefile new file mode 100644 index 000000000..812864312 --- /dev/null +++ b/linux/drivers/media/common/tuners/Makefile @@ -0,0 +1,25 @@ +# +# Makefile for common V4L/DVB tuners +# + +tda18271-objs := tda18271-maps.o tda18271-common.o tda18271-fe.o + +obj-$(CONFIG_TUNER_XC2028) += tuner-xc2028.o +obj-$(CONFIG_TUNER_SIMPLE) += tuner-simple.o +# tuner-types will be merged into tuner-simple, in the future +obj-$(CONFIG_TUNER_SIMPLE) += tuner-types.o +obj-$(CONFIG_TUNER_MT20XX) += mt20xx.o +obj-$(CONFIG_TUNER_TDA8290) += tda8290.o +obj-$(CONFIG_TUNER_TEA5767) += tea5767.o +obj-$(CONFIG_TUNER_TEA5761) += tea5761.o +obj-$(CONFIG_TUNER_TDA9887) += tda9887.o +obj-$(CONFIG_DVB_TDA827X) += tda827x.o +obj-$(CONFIG_DVB_TDA18271) += tda18271.o +obj-$(CONFIG_DVB_TUNER_XC5000) += xc5000.o +obj-$(CONFIG_DVB_TUNER_MT2060) += mt2060.o +obj-$(CONFIG_DVB_TUNER_MT2266) += mt2266.o +obj-$(CONFIG_DVB_TUNER_QT1010) += qt1010.o +obj-$(CONFIG_DVB_TUNER_MT2131) += mt2131.o + +EXTRA_CFLAGS += -Idrivers/media/dvb/dvb-core +EXTRA_CFLAGS += -Idrivers/media/dvb/frontends -- cgit v1.2.3 From 38289d94bcb5008e33c10db7a29d4e6c4d34cb8c Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Sat, 26 Apr 2008 14:23:19 -0300 Subject: A few CodingStyle fixes From: Mauro Carvalho Chehab kernel-sync: Signed-off-by: Mauro Carvalho Chehab --- linux/drivers/media/common/tuners/tuner-xc2028.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'linux/drivers/media/common/tuners') diff --git a/linux/drivers/media/common/tuners/tuner-xc2028.c b/linux/drivers/media/common/tuners/tuner-xc2028.c index 3aa81ae99..4c6a0b7ea 100644 --- a/linux/drivers/media/common/tuners/tuner-xc2028.c +++ b/linux/drivers/media/common/tuners/tuner-xc2028.c @@ -439,7 +439,7 @@ static int seek_firmware(struct dvb_frontend *fe, unsigned int type, type_mask = BASE_TYPES; else if (type & SCODE) { type &= SCODE_TYPES; - type_mask = SCODE_TYPES &~ HAS_IF; + type_mask = SCODE_TYPES & ~HAS_IF; } else if (type & DTV_TYPES) type_mask = DTV_TYPES; else if (type & STD_SPECIFIC_TYPES) -- cgit v1.2.3 From ab22038f9ae859daf0fcfd1a09a53f720fa54fed Mon Sep 17 00:00:00 2001 From: Michael Krufky Date: Mon, 28 Apr 2008 23:54:19 -0400 Subject: tuner: remove static dependencies on analog tuner sub-modules From: Michael Krufky Signed-off-by: Michael Krufky --- linux/drivers/media/common/tuners/tda8290.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'linux/drivers/media/common/tuners') diff --git a/linux/drivers/media/common/tuners/tda8290.c b/linux/drivers/media/common/tuners/tda8290.c index d57602d22..9bda53be5 100644 --- a/linux/drivers/media/common/tuners/tda8290.c +++ b/linux/drivers/media/common/tuners/tda8290.c @@ -604,16 +604,16 @@ static int tda829x_find_tuner(struct dvb_frontend *fe) if ((data == 0x83) || (data == 0x84)) { priv->ver |= TDA18271; - tda18271_attach(fe, priv->tda827x_addr, - priv->i2c_props.adap, - &tda829x_tda18271_config); + dvb_attach(tda18271_attach, fe, priv->tda827x_addr, + priv->i2c_props.adap, &tda829x_tda18271_config); } else { if ((data & 0x3c) == 0) priv->ver |= TDA8275; else priv->ver |= TDA8275A; - tda827x_attach(fe, priv->tda827x_addr, priv->i2c_props.adap, &priv->cfg); + dvb_attach(tda827x_attach, fe, priv->tda827x_addr, + priv->i2c_props.adap, &priv->cfg); priv->cfg.switch_addr = priv->i2c_props.addr; } if (fe->ops.tuner_ops.init) -- cgit v1.2.3 From c8566d4e92c2279fd31da9154b12034dd1d1984d Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Wed, 30 Apr 2008 00:09:25 -0300 Subject: Use the same name convention for all tuners under common/tuners From: Mauro Carvalho Chehab kernel-sync: Auto generated by this script: for i in `find drivers/media/ -name Kconfig`; do cat $i |\ sed s,DVB_CORE_ATTACH,MEDIA_ATTACH,g |\ sed s,VIDEO_TUNER,MEDIA_TUNER,g |\ sed s,TUNER_SIMPLE,MEDIA_TUNER_SIMPLE,g |\ sed s,TUNER_TDA8290,MEDIA_TUNER_TDA8290,g |\ sed s,DVB_TDA827X,MEDIA_TUNER_TDA827X,g |\ sed s,DVB_TDA18271,MEDIA_TUNER_TDA18271,g |\ sed s,TUNER_TDA9887,MEDIA_TUNER_TDA9887,g |\ sed s,TUNER_TEA5761,MEDIA_TUNER_TEA5761,g |\ sed s,TUNER_TEA5767,MEDIA_TUNER_TEA5767,g |\ sed s,TUNER_MT20XX,MEDIA_TUNER_MT20XX,g |\ sed s,DVB_TUNER_MT2060,MEDIA_TUNER_MT2060,g |\ sed s,DVB_TUNER_MT2266,MEDIA_TUNER_MT2266,g |\ sed s,DVB_TUNER_MT2131,MEDIA_TUNER_MT2131,g |\ sed s,DVB_TUNER_QT1010,MEDIA_TUNER_QT1010,g |\ sed s,TUNER_XC2028,MEDIA_TUNER_XC2028,g |\ sed s,DVB_TUNER_XC5000,MEDIA_TUNER_XC5000,g >/tmp/temp_mv$$ mv /tmp/temp_mv$$ $i done for i in `find drivers/media/ -type f`; do cat $i |\ sed s,CONFIG_DVB_CORE_ATTACH,CONFIG_MEDIA_ATTACH,g |\ sed s,CONFIG_VIDEO_TUNER,CONFIG_MEDIA_TUNER,g |\ sed s,CONFIG_TUNER_SIMPLE,CONFIG_MEDIA_TUNER_SIMPLE,g |\ sed s,CONFIG_TUNER_TDA8290,CONFIG_MEDIA_TUNER_TDA8290,g |\ sed s,CONFIG_DVB_TDA827X,CONFIG_MEDIA_TUNER_TDA827X,g |\ sed s,CONFIG_DVB_TDA18271,CONFIG_MEDIA_TUNER_TDA18271,g |\ sed s,CONFIG_TUNER_TDA9887,CONFIG_MEDIA_TUNER_TDA9887,g |\ sed s,CONFIG_TUNER_TEA5761,CONFIG_MEDIA_TUNER_TEA5761,g |\ sed s,CONFIG_TUNER_TEA5767,CONFIG_MEDIA_TUNER_TEA5767,g |\ sed s,CONFIG_TUNER_MT20XX,CONFIG_MEDIA_TUNER_MT20XX,g |\ sed s,CONFIG_DVB_TUNER_MT2060,CONFIG_MEDIA_TUNER_MT2060,g |\ sed s,CONFIG_DVB_TUNER_MT2266,CONFIG_MEDIA_TUNER_MT2266,g |\ sed s,CONFIG_DVB_TUNER_MT2131,CONFIG_MEDIA_TUNER_MT2131,g |\ sed s,CONFIG_DVB_TUNER_QT1010,CONFIG_MEDIA_TUNER_QT1010,g |\ sed s,CONFIG_TUNER_XC2028,CONFIG_MEDIA_TUNER_XC2028,g |\ sed s,CONFIG_DVB_TUNER_XC5000,CONFIG_MEDIA_TUNER_XC5000,g >/tmp/temp_mv$$ mv /tmp/temp_mv$$ $i done Signed-off-by: Mauro Carvalho Chehab --- linux/drivers/media/common/tuners/Kconfig | 78 ++++++++++++------------ linux/drivers/media/common/tuners/Makefile | 30 ++++----- linux/drivers/media/common/tuners/mt2060.h | 4 +- linux/drivers/media/common/tuners/mt20xx.h | 2 +- linux/drivers/media/common/tuners/mt2131.h | 4 +- linux/drivers/media/common/tuners/mt2266.h | 4 +- linux/drivers/media/common/tuners/qt1010.h | 4 +- linux/drivers/media/common/tuners/tda18271.h | 2 +- linux/drivers/media/common/tuners/tda827x.h | 4 +- linux/drivers/media/common/tuners/tda8290.h | 2 +- linux/drivers/media/common/tuners/tda9887.h | 2 +- linux/drivers/media/common/tuners/tea5761.h | 2 +- linux/drivers/media/common/tuners/tea5767.h | 2 +- linux/drivers/media/common/tuners/tuner-simple.h | 2 +- linux/drivers/media/common/tuners/tuner-xc2028.h | 2 +- linux/drivers/media/common/tuners/xc5000.h | 6 +- 16 files changed, 75 insertions(+), 75 deletions(-) (limited to 'linux/drivers/media/common/tuners') diff --git a/linux/drivers/media/common/tuners/Kconfig b/linux/drivers/media/common/tuners/Kconfig index e6926e9fa..7b379e1ce 100644 --- a/linux/drivers/media/common/tuners/Kconfig +++ b/linux/drivers/media/common/tuners/Kconfig @@ -1,4 +1,4 @@ -config DVB_CORE_ATTACH +config MEDIA_ATTACH bool "Load and attach frontend driver modules as needed" depends on DVB_CORE depends on MODULES @@ -12,22 +12,22 @@ config DVB_CORE_ATTACH If unsure say Y. -config VIDEO_TUNER +config MEDIA_TUNER tristate default DVB_CORE || VIDEO_DEV depends on DVB_CORE || VIDEO_DEV - select TUNER_XC2028 if !VIDEO_TUNER_CUSTOMIZE - select DVB_TUNER_XC5000 if !VIDEO_TUNER_CUSTOMIZE - select TUNER_MT20XX if !VIDEO_TUNER_CUSTOMIZE - select TUNER_TDA8290 if !VIDEO_TUNER_CUSTOMIZE - select TUNER_TEA5761 if !VIDEO_TUNER_CUSTOMIZE - select TUNER_TEA5767 if !VIDEO_TUNER_CUSTOMIZE - select TUNER_SIMPLE if !VIDEO_TUNER_CUSTOMIZE - select TUNER_TDA9887 if !VIDEO_TUNER_CUSTOMIZE - -menuconfig VIDEO_TUNER_CUSTOMIZE + select MEDIA_TUNER_XC2028 if !MEDIA_TUNER_CUSTOMIZE + select MEDIA_TUNER_XC5000 if !MEDIA_TUNER_CUSTOMIZE + select MEDIA_TUNER_MT20XX if !MEDIA_TUNER_CUSTOMIZE + select MEDIA_TUNER_TDA8290 if !MEDIA_TUNER_CUSTOMIZE + select MEDIA_TUNER_TEA5761 if !MEDIA_TUNER_CUSTOMIZE + select MEDIA_TUNER_TEA5767 if !MEDIA_TUNER_CUSTOMIZE + select MEDIA_TUNER_SIMPLE if !MEDIA_TUNER_CUSTOMIZE + select MEDIA_TUNER_TDA9887 if !MEDIA_TUNER_CUSTOMIZE + +menuconfig MEDIA_TUNER_CUSTOMIZE bool "Customize analog and hybrid tuner modules to build" - depends on VIDEO_TUNER + depends on MEDIA_TUNER help This allows the user to deselect tuner drivers unnecessary for their hardware from the build. Use this option with care @@ -37,104 +37,104 @@ menuconfig VIDEO_TUNER_CUSTOMIZE If unsure say N. -if VIDEO_TUNER_CUSTOMIZE +if MEDIA_TUNER_CUSTOMIZE -config TUNER_SIMPLE +config MEDIA_TUNER_SIMPLE tristate "Simple tuner support" depends on I2C - select TUNER_TDA9887 - default m if VIDEO_TUNER_CUSTOMIZE + select MEDIA_TUNER_TDA9887 + default m if MEDIA_TUNER_CUSTOMIZE help Say Y here to include support for various simple tuners. -config TUNER_TDA8290 +config MEDIA_TUNER_TDA8290 tristate "TDA 8290/8295 + 8275(a)/18271 tuner combo" depends on I2C - select DVB_TDA827X - select DVB_TDA18271 - default m if VIDEO_TUNER_CUSTOMIZE + select MEDIA_TUNER_TDA827X + select MEDIA_TUNER_TDA18271 + default m if MEDIA_TUNER_CUSTOMIZE help Say Y here to include support for Philips TDA8290+8275(a) tuner. -config DVB_TDA827X +config MEDIA_TUNER_TDA827X tristate "Philips TDA827X silicon tuner" depends on DVB_CORE && I2C default m if DVB_FE_CUSTOMISE help A DVB-T silicon tuner module. Say Y when you want to support this tuner. -config DVB_TDA18271 +config MEDIA_TUNER_TDA18271 tristate "NXP TDA18271 silicon tuner" depends on I2C default m if DVB_FE_CUSTOMISE help A silicon tuner module. Say Y when you want to support this tuner. -config TUNER_TDA9887 +config MEDIA_TUNER_TDA9887 tristate "TDA 9885/6/7 analog IF demodulator" depends on I2C - default m if VIDEO_TUNER_CUSTOMIZE + default m if MEDIA_TUNER_CUSTOMIZE help Say Y here to include support for Philips TDA9885/6/7 analog IF demodulator. -config TUNER_TEA5761 +config MEDIA_TUNER_TEA5761 tristate "TEA 5761 radio tuner (EXPERIMENTAL)" depends on I2C && EXPERIMENTAL - default m if VIDEO_TUNER_CUSTOMIZE + default m if MEDIA_TUNER_CUSTOMIZE help Say Y here to include support for the Philips TEA5761 radio tuner. -config TUNER_TEA5767 +config MEDIA_TUNER_TEA5767 tristate "TEA 5767 radio tuner" depends on I2C - default m if VIDEO_TUNER_CUSTOMIZE + default m if MEDIA_TUNER_CUSTOMIZE help Say Y here to include support for the Philips TEA5767 radio tuner. -config TUNER_MT20XX +config MEDIA_TUNER_MT20XX tristate "Microtune 2032 / 2050 tuners" depends on I2C - default m if VIDEO_TUNER_CUSTOMIZE + default m if MEDIA_TUNER_CUSTOMIZE help Say Y here to include support for the MT2032 / MT2050 tuner. -config DVB_TUNER_MT2060 +config MEDIA_TUNER_MT2060 tristate "Microtune MT2060 silicon IF tuner" depends on I2C default m if DVB_FE_CUSTOMISE help A driver for the silicon IF tuner MT2060 from Microtune. -config DVB_TUNER_MT2266 +config MEDIA_TUNER_MT2266 tristate "Microtune MT2266 silicon tuner" depends on I2C default m if DVB_FE_CUSTOMISE help A driver for the silicon baseband tuner MT2266 from Microtune. -config DVB_TUNER_MT2131 +config MEDIA_TUNER_MT2131 tristate "Microtune MT2131 silicon tuner" depends on I2C default m if DVB_FE_CUSTOMISE help A driver for the silicon baseband tuner MT2131 from Microtune. -config DVB_TUNER_QT1010 +config MEDIA_TUNER_QT1010 tristate "Quantek QT1010 silicon tuner" depends on DVB_CORE && I2C default m if DVB_FE_CUSTOMISE help A driver for the silicon tuner QT1010 from Quantek. -config TUNER_XC2028 +config MEDIA_TUNER_XC2028 tristate "XCeive xc2028/xc3028 tuners" depends on I2C && FW_LOADER - default m if VIDEO_TUNER_CUSTOMIZE + default m if MEDIA_TUNER_CUSTOMIZE help Say Y here to include support for the xc2028/xc3028 tuners. -config DVB_TUNER_XC5000 +config MEDIA_TUNER_XC5000 tristate "Xceive XC5000 silicon tuner" depends on I2C default m if DVB_FE_CUSTOMISE @@ -143,4 +143,4 @@ config DVB_TUNER_XC5000 This device is only used inside a SiP called togther with a demodulator for now. -endif # VIDEO_TUNER_CUSTOMIZE +endif # MEDIA_TUNER_CUSTOMIZE diff --git a/linux/drivers/media/common/tuners/Makefile b/linux/drivers/media/common/tuners/Makefile index 812864312..236d9932f 100644 --- a/linux/drivers/media/common/tuners/Makefile +++ b/linux/drivers/media/common/tuners/Makefile @@ -4,22 +4,22 @@ tda18271-objs := tda18271-maps.o tda18271-common.o tda18271-fe.o -obj-$(CONFIG_TUNER_XC2028) += tuner-xc2028.o -obj-$(CONFIG_TUNER_SIMPLE) += tuner-simple.o +obj-$(CONFIG_MEDIA_TUNER_XC2028) += tuner-xc2028.o +obj-$(CONFIG_MEDIA_TUNER_SIMPLE) += tuner-simple.o # tuner-types will be merged into tuner-simple, in the future -obj-$(CONFIG_TUNER_SIMPLE) += tuner-types.o -obj-$(CONFIG_TUNER_MT20XX) += mt20xx.o -obj-$(CONFIG_TUNER_TDA8290) += tda8290.o -obj-$(CONFIG_TUNER_TEA5767) += tea5767.o -obj-$(CONFIG_TUNER_TEA5761) += tea5761.o -obj-$(CONFIG_TUNER_TDA9887) += tda9887.o -obj-$(CONFIG_DVB_TDA827X) += tda827x.o -obj-$(CONFIG_DVB_TDA18271) += tda18271.o -obj-$(CONFIG_DVB_TUNER_XC5000) += xc5000.o -obj-$(CONFIG_DVB_TUNER_MT2060) += mt2060.o -obj-$(CONFIG_DVB_TUNER_MT2266) += mt2266.o -obj-$(CONFIG_DVB_TUNER_QT1010) += qt1010.o -obj-$(CONFIG_DVB_TUNER_MT2131) += mt2131.o +obj-$(CONFIG_MEDIA_TUNER_SIMPLE) += tuner-types.o +obj-$(CONFIG_MEDIA_TUNER_MT20XX) += mt20xx.o +obj-$(CONFIG_MEDIA_TUNER_TDA8290) += tda8290.o +obj-$(CONFIG_MEDIA_TUNER_TEA5767) += tea5767.o +obj-$(CONFIG_MEDIA_TUNER_TEA5761) += tea5761.o +obj-$(CONFIG_MEDIA_TUNER_TDA9887) += tda9887.o +obj-$(CONFIG_MEDIA_TUNER_TDA827X) += tda827x.o +obj-$(CONFIG_MEDIA_TUNER_TDA18271) += tda18271.o +obj-$(CONFIG_MEDIA_TUNER_XC5000) += xc5000.o +obj-$(CONFIG_MEDIA_TUNER_MT2060) += mt2060.o +obj-$(CONFIG_MEDIA_TUNER_MT2266) += mt2266.o +obj-$(CONFIG_MEDIA_TUNER_QT1010) += qt1010.o +obj-$(CONFIG_MEDIA_TUNER_MT2131) += mt2131.o EXTRA_CFLAGS += -Idrivers/media/dvb/dvb-core EXTRA_CFLAGS += -Idrivers/media/dvb/frontends diff --git a/linux/drivers/media/common/tuners/mt2060.h b/linux/drivers/media/common/tuners/mt2060.h index acba0058f..cb60caffb 100644 --- a/linux/drivers/media/common/tuners/mt2060.h +++ b/linux/drivers/media/common/tuners/mt2060.h @@ -30,7 +30,7 @@ struct mt2060_config { u8 clock_out; /* 0 = off, 1 = CLK/4, 2 = CLK/2, 3 = CLK/1 */ }; -#if defined(CONFIG_DVB_TUNER_MT2060) || (defined(CONFIG_DVB_TUNER_MT2060_MODULE) && defined(MODULE)) +#if defined(CONFIG_MEDIA_TUNER_MT2060) || (defined(CONFIG_MEDIA_TUNER_MT2060_MODULE) && defined(MODULE)) extern struct dvb_frontend * mt2060_attach(struct dvb_frontend *fe, struct i2c_adapter *i2c, struct mt2060_config *cfg, u16 if1); #else static inline struct dvb_frontend * mt2060_attach(struct dvb_frontend *fe, struct i2c_adapter *i2c, struct mt2060_config *cfg, u16 if1) @@ -38,6 +38,6 @@ static inline struct dvb_frontend * mt2060_attach(struct dvb_frontend *fe, struc printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__); return NULL; } -#endif // CONFIG_DVB_TUNER_MT2060 +#endif // CONFIG_MEDIA_TUNER_MT2060 #endif diff --git a/linux/drivers/media/common/tuners/mt20xx.h b/linux/drivers/media/common/tuners/mt20xx.h index aa848e14c..259553a24 100644 --- a/linux/drivers/media/common/tuners/mt20xx.h +++ b/linux/drivers/media/common/tuners/mt20xx.h @@ -20,7 +20,7 @@ #include #include "dvb_frontend.h" -#if defined(CONFIG_TUNER_MT20XX) || (defined(CONFIG_TUNER_MT20XX_MODULE) && defined(MODULE)) +#if defined(CONFIG_MEDIA_TUNER_MT20XX) || (defined(CONFIG_MEDIA_TUNER_MT20XX_MODULE) && defined(MODULE)) extern struct dvb_frontend *microtune_attach(struct dvb_frontend *fe, struct i2c_adapter* i2c_adap, u8 i2c_addr); diff --git a/linux/drivers/media/common/tuners/mt2131.h b/linux/drivers/media/common/tuners/mt2131.h index 606d8576b..cd8376f6f 100644 --- a/linux/drivers/media/common/tuners/mt2131.h +++ b/linux/drivers/media/common/tuners/mt2131.h @@ -30,7 +30,7 @@ struct mt2131_config { u8 clock_out; /* 0 = off, 1 = CLK/4, 2 = CLK/2, 3 = CLK/1 */ }; -#if defined(CONFIG_DVB_TUNER_MT2131) || (defined(CONFIG_DVB_TUNER_MT2131_MODULE) && defined(MODULE)) +#if defined(CONFIG_MEDIA_TUNER_MT2131) || (defined(CONFIG_MEDIA_TUNER_MT2131_MODULE) && defined(MODULE)) extern struct dvb_frontend* mt2131_attach(struct dvb_frontend *fe, struct i2c_adapter *i2c, struct mt2131_config *cfg, @@ -44,7 +44,7 @@ static inline struct dvb_frontend* mt2131_attach(struct dvb_frontend *fe, printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__); return NULL; } -#endif /* CONFIG_DVB_TUNER_MT2131 */ +#endif /* CONFIG_MEDIA_TUNER_MT2131 */ #endif /* __MT2131_H__ */ diff --git a/linux/drivers/media/common/tuners/mt2266.h b/linux/drivers/media/common/tuners/mt2266.h index c5113efe3..4d083882d 100644 --- a/linux/drivers/media/common/tuners/mt2266.h +++ b/linux/drivers/media/common/tuners/mt2266.h @@ -24,7 +24,7 @@ struct mt2266_config { u8 i2c_address; }; -#if defined(CONFIG_DVB_TUNER_MT2266) || (defined(CONFIG_DVB_TUNER_MT2266_MODULE) && defined(MODULE)) +#if defined(CONFIG_MEDIA_TUNER_MT2266) || (defined(CONFIG_MEDIA_TUNER_MT2266_MODULE) && defined(MODULE)) extern struct dvb_frontend * mt2266_attach(struct dvb_frontend *fe, struct i2c_adapter *i2c, struct mt2266_config *cfg); #else static inline struct dvb_frontend * mt2266_attach(struct dvb_frontend *fe, struct i2c_adapter *i2c, struct mt2266_config *cfg) @@ -32,6 +32,6 @@ static inline struct dvb_frontend * mt2266_attach(struct dvb_frontend *fe, struc printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__); return NULL; } -#endif // CONFIG_DVB_TUNER_MT2266 +#endif // CONFIG_MEDIA_TUNER_MT2266 #endif diff --git a/linux/drivers/media/common/tuners/qt1010.h b/linux/drivers/media/common/tuners/qt1010.h index cff6a7ca5..807fb7b61 100644 --- a/linux/drivers/media/common/tuners/qt1010.h +++ b/linux/drivers/media/common/tuners/qt1010.h @@ -36,7 +36,7 @@ struct qt1010_config { * @param cfg tuner hw based configuration * @return fe pointer on success, NULL on failure */ -#if defined(CONFIG_DVB_TUNER_QT1010) || (defined(CONFIG_DVB_TUNER_QT1010_MODULE) && defined(MODULE)) +#if defined(CONFIG_MEDIA_TUNER_QT1010) || (defined(CONFIG_MEDIA_TUNER_QT1010_MODULE) && defined(MODULE)) extern struct dvb_frontend *qt1010_attach(struct dvb_frontend *fe, struct i2c_adapter *i2c, struct qt1010_config *cfg); @@ -48,6 +48,6 @@ static inline struct dvb_frontend *qt1010_attach(struct dvb_frontend *fe, printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__); return NULL; } -#endif // CONFIG_DVB_TUNER_QT1010 +#endif // CONFIG_MEDIA_TUNER_QT1010 #endif diff --git a/linux/drivers/media/common/tuners/tda18271.h b/linux/drivers/media/common/tuners/tda18271.h index 0e7af8d05..7db9831c0 100644 --- a/linux/drivers/media/common/tuners/tda18271.h +++ b/linux/drivers/media/common/tuners/tda18271.h @@ -81,7 +81,7 @@ struct tda18271_config { unsigned int small_i2c:1; }; -#if defined(CONFIG_DVB_TDA18271) || (defined(CONFIG_DVB_TDA18271_MODULE) && defined(MODULE)) +#if defined(CONFIG_MEDIA_TUNER_TDA18271) || (defined(CONFIG_MEDIA_TUNER_TDA18271_MODULE) && defined(MODULE)) extern struct dvb_frontend *tda18271_attach(struct dvb_frontend *fe, u8 addr, struct i2c_adapter *i2c, struct tda18271_config *cfg); diff --git a/linux/drivers/media/common/tuners/tda827x.h b/linux/drivers/media/common/tuners/tda827x.h index b73c23570..7850a9a1d 100644 --- a/linux/drivers/media/common/tuners/tda827x.h +++ b/linux/drivers/media/common/tuners/tda827x.h @@ -51,7 +51,7 @@ struct tda827x_config * @param cfg optional callback function pointers. * @return FE pointer on success, NULL on failure. */ -#if defined(CONFIG_DVB_TDA827X) || (defined(CONFIG_DVB_TDA827X_MODULE) && defined(MODULE)) +#if defined(CONFIG_MEDIA_TUNER_TDA827X) || (defined(CONFIG_MEDIA_TUNER_TDA827X_MODULE) && defined(MODULE)) extern struct dvb_frontend* tda827x_attach(struct dvb_frontend *fe, int addr, struct i2c_adapter *i2c, struct tda827x_config *cfg); @@ -64,6 +64,6 @@ static inline struct dvb_frontend* tda827x_attach(struct dvb_frontend *fe, printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__); return NULL; } -#endif // CONFIG_DVB_TDA827X +#endif // CONFIG_MEDIA_TUNER_TDA827X #endif // __DVB_TDA827X_H__ diff --git a/linux/drivers/media/common/tuners/tda8290.h b/linux/drivers/media/common/tuners/tda8290.h index d3bbf276a..aa074f3f0 100644 --- a/linux/drivers/media/common/tuners/tda8290.h +++ b/linux/drivers/media/common/tuners/tda8290.h @@ -29,7 +29,7 @@ struct tda829x_config { #define TDA829X_DONT_PROBE 1 }; -#if defined(CONFIG_TUNER_TDA8290) || (defined(CONFIG_TUNER_TDA8290_MODULE) && defined(MODULE)) +#if defined(CONFIG_MEDIA_TUNER_TDA8290) || (defined(CONFIG_MEDIA_TUNER_TDA8290_MODULE) && defined(MODULE)) extern int tda829x_probe(struct i2c_adapter *i2c_adap, u8 i2c_addr); extern struct dvb_frontend *tda829x_attach(struct dvb_frontend *fe, diff --git a/linux/drivers/media/common/tuners/tda9887.h b/linux/drivers/media/common/tuners/tda9887.h index be49dcbfc..acc419e8c 100644 --- a/linux/drivers/media/common/tuners/tda9887.h +++ b/linux/drivers/media/common/tuners/tda9887.h @@ -21,7 +21,7 @@ #include "dvb_frontend.h" /* ------------------------------------------------------------------------ */ -#if defined(CONFIG_TUNER_TDA9887) || (defined(CONFIG_TUNER_TDA9887_MODULE) && defined(MODULE)) +#if defined(CONFIG_MEDIA_TUNER_TDA9887) || (defined(CONFIG_MEDIA_TUNER_TDA9887_MODULE) && defined(MODULE)) extern struct dvb_frontend *tda9887_attach(struct dvb_frontend *fe, struct i2c_adapter *i2c_adap, u8 i2c_addr); diff --git a/linux/drivers/media/common/tuners/tea5761.h b/linux/drivers/media/common/tuners/tea5761.h index 8eb62722b..2e2ff82c9 100644 --- a/linux/drivers/media/common/tuners/tea5761.h +++ b/linux/drivers/media/common/tuners/tea5761.h @@ -20,7 +20,7 @@ #include #include "dvb_frontend.h" -#if defined(CONFIG_TUNER_TEA5761) || (defined(CONFIG_TUNER_TEA5761_MODULE) && defined(MODULE)) +#if defined(CONFIG_MEDIA_TUNER_TEA5761) || (defined(CONFIG_MEDIA_TUNER_TEA5761_MODULE) && defined(MODULE)) extern int tea5761_autodetection(struct i2c_adapter* i2c_adap, u8 i2c_addr); extern struct dvb_frontend *tea5761_attach(struct dvb_frontend *fe, diff --git a/linux/drivers/media/common/tuners/tea5767.h b/linux/drivers/media/common/tuners/tea5767.h index 7b547c092..d30ab1b48 100644 --- a/linux/drivers/media/common/tuners/tea5767.h +++ b/linux/drivers/media/common/tuners/tea5767.h @@ -39,7 +39,7 @@ struct tea5767_ctrl { enum tea5767_xtal xtal_freq; }; -#if defined(CONFIG_TUNER_TEA5767) || (defined(CONFIG_TUNER_TEA5767_MODULE) && defined(MODULE)) +#if defined(CONFIG_MEDIA_TUNER_TEA5767) || (defined(CONFIG_MEDIA_TUNER_TEA5767_MODULE) && defined(MODULE)) extern int tea5767_autodetection(struct i2c_adapter* i2c_adap, u8 i2c_addr); extern struct dvb_frontend *tea5767_attach(struct dvb_frontend *fe, diff --git a/linux/drivers/media/common/tuners/tuner-simple.h b/linux/drivers/media/common/tuners/tuner-simple.h index e46cf0121..381fa5d35 100644 --- a/linux/drivers/media/common/tuners/tuner-simple.h +++ b/linux/drivers/media/common/tuners/tuner-simple.h @@ -20,7 +20,7 @@ #include #include "dvb_frontend.h" -#if defined(CONFIG_TUNER_SIMPLE) || (defined(CONFIG_TUNER_SIMPLE_MODULE) && defined(MODULE)) +#if defined(CONFIG_MEDIA_TUNER_SIMPLE) || (defined(CONFIG_MEDIA_TUNER_SIMPLE_MODULE) && defined(MODULE)) extern struct dvb_frontend *simple_tuner_attach(struct dvb_frontend *fe, struct i2c_adapter *i2c_adap, u8 i2c_addr, diff --git a/linux/drivers/media/common/tuners/tuner-xc2028.h b/linux/drivers/media/common/tuners/tuner-xc2028.h index fc2f132a5..216025cf5 100644 --- a/linux/drivers/media/common/tuners/tuner-xc2028.h +++ b/linux/drivers/media/common/tuners/tuner-xc2028.h @@ -47,7 +47,7 @@ struct xc2028_config { #define XC2028_TUNER_RESET 0 #define XC2028_RESET_CLK 1 -#if defined(CONFIG_TUNER_XC2028) || (defined(CONFIG_TUNER_XC2028_MODULE) && defined(MODULE)) +#if defined(CONFIG_MEDIA_TUNER_XC2028) || (defined(CONFIG_MEDIA_TUNER_XC2028_MODULE) && defined(MODULE)) extern struct dvb_frontend *xc2028_attach(struct dvb_frontend *fe, struct xc2028_config *cfg); #else diff --git a/linux/drivers/media/common/tuners/xc5000.h b/linux/drivers/media/common/tuners/xc5000.h index b890883a0..0ee80f9d1 100644 --- a/linux/drivers/media/common/tuners/xc5000.h +++ b/linux/drivers/media/common/tuners/xc5000.h @@ -45,8 +45,8 @@ struct xc5000_config { /* xc5000 callback command */ #define XC5000_TUNER_RESET 0 -#if defined(CONFIG_DVB_TUNER_XC5000) || \ - (defined(CONFIG_DVB_TUNER_XC5000_MODULE) && defined(MODULE)) +#if defined(CONFIG_MEDIA_TUNER_XC5000) || \ + (defined(CONFIG_MEDIA_TUNER_XC5000_MODULE) && defined(MODULE)) extern struct dvb_frontend* xc5000_attach(struct dvb_frontend *fe, struct i2c_adapter *i2c, struct xc5000_config *cfg); @@ -58,6 +58,6 @@ static inline struct dvb_frontend* xc5000_attach(struct dvb_frontend *fe, printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__); return NULL; } -#endif // CONFIG_DVB_TUNER_XC5000 +#endif // CONFIG_MEDIA_TUNER_XC5000 #endif // __XC5000_H__ -- cgit v1.2.3 From 2e955b594aaf98271653530ce57dafc0c15dd94c Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Wed, 30 Apr 2008 00:19:33 -0300 Subject: tuners/Kconfig: Change config name and help to reflect dynamic load for tuners From: Mauro Carvalho Chehab Signed-off-by: Mauro Carvalho Chehab --- linux/drivers/media/common/tuners/Kconfig | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) (limited to 'linux/drivers/media/common/tuners') diff --git a/linux/drivers/media/common/tuners/Kconfig b/linux/drivers/media/common/tuners/Kconfig index 7b379e1ce..5be85ff53 100644 --- a/linux/drivers/media/common/tuners/Kconfig +++ b/linux/drivers/media/common/tuners/Kconfig @@ -1,12 +1,17 @@ config MEDIA_ATTACH - bool "Load and attach frontend driver modules as needed" + bool "Load and attach frontend and tuner driver modules as needed" depends on DVB_CORE depends on MODULES help Remove the static dependency of DVB card drivers on all frontend modules for all possible card variants. Instead, allow the card drivers to only load the frontend modules - they require. This saves several KBytes of memory. + they require. + + Also, tuner module will automatically load a tuner driver + when needed, for analog mode. + + This saves several KBytes of memory. Note: You will need module-init-tools v3.2 or later for this feature. -- cgit v1.2.3 From ac958e9cce48978cd215e7146fefacee8b3ae490 Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Wed, 30 Apr 2008 12:45:00 -0300 Subject: tea5767: Fix error logic From: Mauro Carvalho Chehab As pointed by Andrew Morton, the error testing were wrong. After reviewing tea5767, it were returning a positive value for errors. So, the double errors were cancelling each other. This patch fix it properly. It also considers any positive value as ok, on tuner-core. CC: Andrew Morton Signed-off-by: Mauro Carvalho Chehab --- linux/drivers/media/common/tuners/tea5767.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) (limited to 'linux/drivers/media/common/tuners') diff --git a/linux/drivers/media/common/tuners/tea5767.c b/linux/drivers/media/common/tuners/tea5767.c index e5bfc72a4..5990a63ef 100644 --- a/linux/drivers/media/common/tuners/tea5767.c +++ b/linux/drivers/media/common/tuners/tea5767.c @@ -380,14 +380,14 @@ int tea5767_autodetection(struct i2c_adapter* i2c_adap, u8 i2c_addr) if ((rc = tuner_i2c_xfer_recv(&i2c, buffer, 7))< 5) { printk(KERN_WARNING "It is not a TEA5767. Received %i bytes.\n", rc); - return EINVAL; + return -EINVAL; } /* If all bytes are the same then it's a TV tuner and not a tea5767 */ if (buffer[0] == buffer[1] && buffer[0] == buffer[2] && buffer[0] == buffer[3] && buffer[0] == buffer[4]) { printk(KERN_WARNING "All bytes are equal. It is not a TEA5767\n"); - return EINVAL; + return -EINVAL; } /* Status bytes: @@ -397,14 +397,14 @@ int tea5767_autodetection(struct i2c_adapter* i2c_adap, u8 i2c_addr) */ if (((buffer[3] & 0x0f) != 0x00) || (buffer[4] != 0x00)) { printk(KERN_WARNING "Chip ID is not zero. It is not a TEA5767\n"); - return EINVAL; + return -EINVAL; } #if 0 /* Not working for TEA5767 in Beholder Columbus card */ /* It seems that tea5767 returns 0xff after the 5th byte */ if ((buffer[5] != 0xff) || (buffer[6] != 0xff)) { printk(KERN_WARNING "Returned more than 5 bytes. It is not a TEA5767\n"); - return EINVAL; + return -EINVAL; } #endif @@ -425,7 +425,7 @@ int tea5767_autodetection(struct i2c_adapter* i2c_adap, u8 i2c_addr) if (5 != (rc = tuner_i2c_xfer_recv(&i2c, buffer, 5))) { printk(KERN_WARNING "It is not a TEA5767. Received %i bytes.\n", rc); - return EINVAL; + return -EINVAL; } /* Initial freq for 32.768KHz clock */ @@ -433,7 +433,7 @@ int tea5767_autodetection(struct i2c_adapter* i2c_adap, u8 i2c_addr) printk(KERN_WARNING "It is not a TEA5767. div=%d, Return: %02x %02x %02x %02x %02x\n", div,buffer[0],buffer[1],buffer[2],buffer[3],buffer[4]); tea5767_status_dump(buffer); - return EINVAL; + return -EINVAL; } #endif return 0; @@ -490,8 +490,8 @@ struct dvb_frontend *tea5767_attach(struct dvb_frontend *fe, struct tea5767_priv *priv = NULL; #if 0 /* By removing autodetection allows forcing TEA chip */ - if (tea5767_autodetection(i2c_adap, i2c_addr) == EINVAL) - return EINVAL; + if (tea5767_autodetection(i2c_adap, i2c_addr) == -EINVAL) + return -EINVAL; #endif priv = kzalloc(sizeof(struct tea5767_priv), GFP_KERNEL); if (priv == NULL) -- cgit v1.2.3 From b203244d2a4a0bc0ec26fde6c54a91c8525aae42 Mon Sep 17 00:00:00 2001 From: Michael Krufky Date: Sat, 3 May 2008 14:20:21 -0400 Subject: tda18271: fix error handling in init and sleep paths From: Michael Krufky Signed-off-by: Michael Krufky --- .../drivers/media/common/tuners/tda18271-common.c | 7 ++-- linux/drivers/media/common/tuners/tda18271-fe.c | 38 ++++++++++++++-------- 2 files changed, 27 insertions(+), 18 deletions(-) (limited to 'linux/drivers/media/common/tuners') diff --git a/linux/drivers/media/common/tuners/tda18271-common.c b/linux/drivers/media/common/tuners/tda18271-common.c index 43c0bec83..e07f69b29 100644 --- a/linux/drivers/media/common/tuners/tda18271-common.c +++ b/linux/drivers/media/common/tuners/tda18271-common.c @@ -227,9 +227,8 @@ int tda18271_charge_pump_source(struct dvb_frontend *fe, regs[r_cp] &= ~0x20; regs[r_cp] |= ((force & 1) << 5); - tda18271_write_regs(fe, r_cp, 1); - return 0; + return tda18271_write_regs(fe, r_cp, 1); } int tda18271_init_regs(struct dvb_frontend *fe) @@ -562,9 +561,7 @@ int tda18271_set_standby_mode(struct dvb_frontend *fe, sm_lt ? (1 << 6) : 0 | sm_xt ? (1 << 5) : 0; - tda18271_write_regs(fe, R_EP3, 1); - - return 0; + return tda18271_write_regs(fe, R_EP3, 1); } /*---------------------------------------------------------------------*/ diff --git a/linux/drivers/media/common/tuners/tda18271-fe.c b/linux/drivers/media/common/tuners/tda18271-fe.c index 355c37a42..7b1fe6614 100644 --- a/linux/drivers/media/common/tuners/tda18271-fe.c +++ b/linux/drivers/media/common/tuners/tda18271-fe.c @@ -720,45 +720,56 @@ static int tda18271_ir_cal_init(struct dvb_frontend *fe) { struct tda18271_priv *priv = fe->tuner_priv; unsigned char *regs = priv->tda18271_regs; + int ret; - tda18271_read_regs(fe); + ret = tda18271_read_regs(fe); + if (ret < 0) + goto fail; /* test IR_CAL_OK to see if we need init */ if ((regs[R_EP1] & 0x08) == 0) - tda18271_init_regs(fe); - - return 0; + ret = tda18271_init_regs(fe); +fail: + return ret; } static int tda18271_init(struct dvb_frontend *fe) { struct tda18271_priv *priv = fe->tuner_priv; + int ret; mutex_lock(&priv->lock); /* power up */ - tda18271_set_standby_mode(fe, 0, 0, 0); + ret = tda18271_set_standby_mode(fe, 0, 0, 0); + if (ret < 0) + goto fail; /* initialization */ - tda18271_ir_cal_init(fe); + ret = tda18271_ir_cal_init(fe); + if (ret < 0) + goto fail; if (priv->id == TDA18271HDC2) tda18271c2_rf_cal_init(fe); - +fail: mutex_unlock(&priv->lock); - return 0; + return ret; } static int tda18271_tune(struct dvb_frontend *fe, struct tda18271_std_map_item *map, u32 freq, u32 bw) { struct tda18271_priv *priv = fe->tuner_priv; + int ret; tda_dbg("freq = %d, ifc = %d, bw = %d, agc_mode = %d, std = %d\n", freq, map->if_freq, bw, map->agc_mode, map->std); - tda18271_init(fe); + ret = tda18271_init(fe); + if (ret < 0) + goto fail; mutex_lock(&priv->lock); @@ -773,8 +784,8 @@ static int tda18271_tune(struct dvb_frontend *fe, tda18271_channel_configuration(fe, map, freq, bw); mutex_unlock(&priv->lock); - - return 0; +fail: + return ret; } /* ------------------------------------------------------------------ */ @@ -906,16 +917,17 @@ fail: static int tda18271_sleep(struct dvb_frontend *fe) { struct tda18271_priv *priv = fe->tuner_priv; + int ret; mutex_lock(&priv->lock); /* standby mode w/ slave tuner output * & loop thru & xtal oscillator on */ - tda18271_set_standby_mode(fe, 1, 0, 0); + ret = tda18271_set_standby_mode(fe, 1, 0, 0); mutex_unlock(&priv->lock); - return 0; + return ret; } static int tda18271_release(struct dvb_frontend *fe) -- cgit v1.2.3 From a609e1bc62ca00624fc93702dc635e3c29c9ba02 Mon Sep 17 00:00:00 2001 From: Michael Krufky Date: Sat, 3 May 2008 15:28:00 -0400 Subject: tda18271: fix error handling in tda18271c2_rf_cal_init path From: Michael Krufky fix error handling in tda18271c2_rf_cal_init immediate path Signed-off-by: Michael Krufky --- linux/drivers/media/common/tuners/tda18271-fe.c | 68 +++++++++++++++++-------- 1 file changed, 47 insertions(+), 21 deletions(-) (limited to 'linux/drivers/media/common/tuners') diff --git a/linux/drivers/media/common/tuners/tda18271-fe.c b/linux/drivers/media/common/tuners/tda18271-fe.c index 7b1fe6614..b876465c9 100644 --- a/linux/drivers/media/common/tuners/tda18271-fe.c +++ b/linux/drivers/media/common/tuners/tda18271-fe.c @@ -260,26 +260,33 @@ static int tda18271_por(struct dvb_frontend *fe) { struct tda18271_priv *priv = fe->tuner_priv; unsigned char *regs = priv->tda18271_regs; + int ret; /* power up detector 1 */ regs[R_EB12] &= ~0x20; - tda18271_write_regs(fe, R_EB12, 1); + ret = tda18271_write_regs(fe, R_EB12, 1); + if (ret < 0) + goto fail; regs[R_EB18] &= ~0x80; /* turn agc1 loop on */ regs[R_EB18] &= ~0x03; /* set agc1_gain to 6 dB */ - tda18271_write_regs(fe, R_EB18, 1); + ret = tda18271_write_regs(fe, R_EB18, 1); + if (ret < 0) + goto fail; regs[R_EB21] |= 0x03; /* set agc2_gain to -6 dB */ /* POR mode */ - tda18271_set_standby_mode(fe, 1, 0, 0); + ret = tda18271_set_standby_mode(fe, 1, 0, 0); + if (ret < 0) + goto fail; /* disable 1.5 MHz low pass filter */ regs[R_EB23] &= ~0x04; /* forcelp_fc2_en = 0 */ regs[R_EB23] &= ~0x02; /* XXX: lp_fc[2] = 0 */ - tda18271_write_regs(fe, R_EB21, 3); - - return 0; + ret = tda18271_write_regs(fe, R_EB21, 3); +fail: + return ret; } static int tda18271_calibrate_rf(struct dvb_frontend *fe, u32 freq) @@ -390,7 +397,7 @@ static int tda18271_powerscan(struct dvb_frontend *fe, { struct tda18271_priv *priv = fe->tuner_priv; unsigned char *regs = priv->tda18271_regs; - int sgn, bcal, count, wait; + int sgn, bcal, count, wait, ret; u8 cid_target; u16 count_limit; u32 freq; @@ -422,7 +429,9 @@ static int tda18271_powerscan(struct dvb_frontend *fe, tda18271_write_regs(fe, R_EP2, 1); /* read power detection info, stored in EB10 */ - tda18271_read_extended(fe); + ret = tda18271_read_extended(fe); + if (ret < 0) + return ret; /* algorithm initialization */ sgn = 1; @@ -448,7 +457,9 @@ static int tda18271_powerscan(struct dvb_frontend *fe, tda18271_write_regs(fe, R_EP2, 1); /* read power detection info, stored in EB10 */ - tda18271_read_extended(fe); + ret = tda18271_read_extended(fe); + if (ret < 0) + return ret; count += 200; @@ -479,6 +490,7 @@ static int tda18271_powerscan_init(struct dvb_frontend *fe) { struct tda18271_priv *priv = fe->tuner_priv; unsigned char *regs = priv->tda18271_regs; + int ret; /* set standard to digital */ regs[R_EP3] &= ~0x1f; /* clear std bits */ @@ -490,10 +502,14 @@ static int tda18271_powerscan_init(struct dvb_frontend *fe) /* update IF output level & IF notch frequency */ regs[R_EP4] &= ~0x1c; /* clear if level bits */ - tda18271_write_regs(fe, R_EP3, 2); + ret = tda18271_write_regs(fe, R_EP3, 2); + if (ret < 0) + goto fail; regs[R_EB18] &= ~0x03; /* set agc1_gain to 6 dB */ - tda18271_write_regs(fe, R_EB18, 1); + ret = tda18271_write_regs(fe, R_EB18, 1); + if (ret < 0) + goto fail; regs[R_EB21] &= ~0x03; /* set agc2_gain to -15 dB */ @@ -501,9 +517,9 @@ static int tda18271_powerscan_init(struct dvb_frontend *fe) regs[R_EB23] |= 0x04; /* forcelp_fc2_en = 1 */ regs[R_EB23] |= 0x02; /* lp_fc[2] = 1 */ - tda18271_write_regs(fe, R_EB21, 3); - - return 0; + ret = tda18271_write_regs(fe, R_EB21, 3); +fail: + return ret; } static int tda18271_rf_tracking_filters_init(struct dvb_frontend *fe, u32 freq) @@ -536,6 +552,8 @@ static int tda18271_rf_tracking_filters_init(struct dvb_frontend *fe, u32 freq) /* look for optimized calibration frequency */ bcal = tda18271_powerscan(fe, &rf_default[rf], &rf_freq[rf]); + if (bcal < 0) + return bcal; tda18271_calc_rf_cal(fe, &rf_freq[rf]); prog_tab[rf] = regs[R_EB14]; @@ -576,13 +594,16 @@ static int tda18271_calc_rf_filter_curve(struct dvb_frontend *fe) { struct tda18271_priv *priv = fe->tuner_priv; unsigned int i; + int ret; tda_info("tda18271: performing RF tracking filter calibration\n"); /* wait for die temperature stabilization */ msleep(200); - tda18271_powerscan_init(fe); + ret = tda18271_powerscan_init(fe); + if (ret < 0) + goto fail; /* rf band calibration */ for (i = 0; priv->rf_cal_state[i].rfmax != 0; i++) @@ -590,8 +611,8 @@ static int tda18271_calc_rf_filter_curve(struct dvb_frontend *fe) priv->rf_cal_state[i].rfmax); priv->tm_rfcal = tda18271_read_thermometer(fe); - - return 0; +fail: + return ret; } /* ------------------------------------------------------------------ */ @@ -600,6 +621,7 @@ static int tda18271c2_rf_cal_init(struct dvb_frontend *fe) { struct tda18271_priv *priv = fe->tuner_priv; unsigned char *regs = priv->tda18271_regs; + int ret; /* test RF_CAL_OK to see if we need init */ if ((regs[R_EP1] & 0x10) == 0) @@ -608,15 +630,19 @@ static int tda18271c2_rf_cal_init(struct dvb_frontend *fe) if (priv->cal_initialized) return 0; - tda18271_calc_rf_filter_curve(fe); + ret = tda18271_calc_rf_filter_curve(fe); + if (ret < 0) + goto fail; - tda18271_por(fe); + ret = tda18271_por(fe); + if (ret < 0) + goto fail; tda_info("tda18271: RF tracking filter calibration complete\n"); priv->cal_initialized = true; - - return 0; +fail: + return ret; } static int tda18271c1_rf_tracking_filter_calibration(struct dvb_frontend *fe, -- cgit v1.2.3 From e5d7fed984ca2b3454accbea7be4b5cb91a71512 Mon Sep 17 00:00:00 2001 From: Michael Krufky Date: Mon, 5 May 2008 17:08:28 -0400 Subject: xc5000: MEDIA_TUNER_XC5000 must select FW_LOADER From: Michael Krufky Fix the following build error: drivers/built-in.o: In function `xc_load_fw_and_init_tuner': xc5000.c:(.text+0x2dacd): undefined reference to `request_firmware' xc5000.c:(.text+0x2daf0): undefined reference to `release_firmware' xc5000.c:(.text+0x2db85): undefined reference to `release_firmware' make[1]: *** [.tmp_vmlinux1] Error 1 Signed-off-by: Michael Krufky --- linux/drivers/media/common/tuners/Kconfig | 1 + 1 file changed, 1 insertion(+) (limited to 'linux/drivers/media/common/tuners') diff --git a/linux/drivers/media/common/tuners/Kconfig b/linux/drivers/media/common/tuners/Kconfig index 5be85ff53..c0b472eae 100644 --- a/linux/drivers/media/common/tuners/Kconfig +++ b/linux/drivers/media/common/tuners/Kconfig @@ -142,6 +142,7 @@ config MEDIA_TUNER_XC2028 config MEDIA_TUNER_XC5000 tristate "Xceive XC5000 silicon tuner" depends on I2C + select FW_LOADER default m if DVB_FE_CUSTOMISE help A driver for the silicon tuner XC5000 from Xceive. -- cgit v1.2.3 From 795210ef84f3116328c8e10766f9aa019a9842b3 Mon Sep 17 00:00:00 2001 From: Michael Krufky Date: Sun, 4 May 2008 13:54:23 -0400 Subject: tda18271: abort rf band calibration loop on errors From: Michael Krufky Abort rf band calibration loop for the TDA18271HD/C2 if an error is detected. Signed-off-by: Michael Krufky --- linux/drivers/media/common/tuners/tda18271-fe.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) (limited to 'linux/drivers/media/common/tuners') diff --git a/linux/drivers/media/common/tuners/tda18271-fe.c b/linux/drivers/media/common/tuners/tda18271-fe.c index b876465c9..41a7798e0 100644 --- a/linux/drivers/media/common/tuners/tda18271-fe.c +++ b/linux/drivers/media/common/tuners/tda18271-fe.c @@ -606,9 +606,13 @@ static int tda18271_calc_rf_filter_curve(struct dvb_frontend *fe) goto fail; /* rf band calibration */ - for (i = 0; priv->rf_cal_state[i].rfmax != 0; i++) + for (i = 0; priv->rf_cal_state[i].rfmax != 0; i++) { + ret = tda18271_rf_tracking_filters_init(fe, 1000 * priv->rf_cal_state[i].rfmax); + if (ret < 0) + goto fail; + } priv->tm_rfcal = tda18271_read_thermometer(fe); fail: @@ -641,7 +645,10 @@ static int tda18271c2_rf_cal_init(struct dvb_frontend *fe) tda_info("tda18271: RF tracking filter calibration complete\n"); priv->cal_initialized = true; + goto end; fail: + tda_info("tda18271: RF tracking filter calibration failed!\n"); +end: return ret; } -- cgit v1.2.3 From d54a5aeffd20a5eb9c73e2aebe19c86499e0c6c7 Mon Sep 17 00:00:00 2001 From: Michael Krufky Date: Sun, 4 May 2008 14:18:48 -0400 Subject: tda18271: make tda18271_set_standby_mode less verbose for basic debug From: Michael Krufky Only show debug from tda18271_set_standby_mode if DBG_ADV is set. Signed-off-by: Michael Krufky --- linux/drivers/media/common/tuners/tda18271-common.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'linux/drivers/media/common/tuners') diff --git a/linux/drivers/media/common/tuners/tda18271-common.c b/linux/drivers/media/common/tuners/tda18271-common.c index e07f69b29..28575e4c5 100644 --- a/linux/drivers/media/common/tuners/tda18271-common.c +++ b/linux/drivers/media/common/tuners/tda18271-common.c @@ -554,7 +554,8 @@ int tda18271_set_standby_mode(struct dvb_frontend *fe, struct tda18271_priv *priv = fe->tuner_priv; unsigned char *regs = priv->tda18271_regs; - tda_dbg("sm = %d, sm_lt = %d, sm_xt = %d\n", sm, sm_lt, sm_xt); + if (tda18271_debug & DBG_ADV) + tda_dbg("sm = %d, sm_lt = %d, sm_xt = %d\n", sm, sm_lt, sm_xt); regs[R_EP3] &= ~0xe0; /* clear sm, sm_lt, sm_xt */ regs[R_EP3] |= sm ? (1 << 7) : 0 | -- cgit v1.2.3 From 57729e354e389335c094defa1dc9978780438d74 Mon Sep 17 00:00:00 2001 From: Michael Krufky Date: Sun, 4 May 2008 15:37:27 -0400 Subject: tda18271: fix error handling in tda18271_channel_configuration From: Michael Krufky Signed-off-by: Michael Krufky --- linux/drivers/media/common/tuners/tda18271-fe.c | 21 ++++++++++++++------- 1 file changed, 14 insertions(+), 7 deletions(-) (limited to 'linux/drivers/media/common/tuners') diff --git a/linux/drivers/media/common/tuners/tda18271-fe.c b/linux/drivers/media/common/tuners/tda18271-fe.c index 41a7798e0..15e2deb3f 100644 --- a/linux/drivers/media/common/tuners/tda18271-fe.c +++ b/linux/drivers/media/common/tuners/tda18271-fe.c @@ -52,6 +52,7 @@ static int tda18271_channel_configuration(struct dvb_frontend *fe, { struct tda18271_priv *priv = fe->tuner_priv; unsigned char *regs = priv->tda18271_regs; + int ret; u32 N; /* update TV broadcast parameters */ @@ -86,7 +87,9 @@ static int tda18271_channel_configuration(struct dvb_frontend *fe, /* update rf top / if top */ regs[R_EB22] = 0x00; regs[R_EB22] |= map->rfagc_top; - tda18271_write_regs(fe, R_EB22, 1); + ret = tda18271_write_regs(fe, R_EB22, 1); + if (ret < 0) + goto fail; /* --------------------------------------------------------------- */ @@ -122,7 +125,9 @@ static int tda18271_channel_configuration(struct dvb_frontend *fe, /* agc1 has priority on agc2 */ regs[R_EB1] &= ~0x01; - tda18271_write_regs(fe, R_EB1, 1); + ret = tda18271_write_regs(fe, R_EB1, 1); + if (ret < 0) + goto fail; /* --------------------------------------------------------------- */ @@ -142,7 +147,9 @@ static int tda18271_channel_configuration(struct dvb_frontend *fe, break; } - tda18271_write_regs(fe, R_TM, 7); + ret = tda18271_write_regs(fe, R_TM, 7); + if (ret < 0) + goto fail; /* force charge pump source */ charge_pump_source(fe, 1); @@ -159,9 +166,9 @@ static int tda18271_channel_configuration(struct dvb_frontend *fe, regs[R_EP3] &= ~0x04; else regs[R_EP3] |= 0x04; - tda18271_write_regs(fe, R_EP3, 1); - - return 0; + ret = tda18271_write_regs(fe, R_EP3, 1); +fail: + return ret; } static int tda18271_read_thermometer(struct dvb_frontend *fe) @@ -814,7 +821,7 @@ static int tda18271_tune(struct dvb_frontend *fe, tda18271c2_rf_tracking_filters_correction(fe, freq); break; } - tda18271_channel_configuration(fe, map, freq, bw); + ret = tda18271_channel_configuration(fe, map, freq, bw); mutex_unlock(&priv->lock); fail: -- cgit v1.2.3 From 2ba71a7d6966f5c647046c556d9bb6cb3145b5fd Mon Sep 17 00:00:00 2001 From: Michael Krufky Date: Sun, 4 May 2008 15:57:06 -0400 Subject: tda18271: fix error handling in tda18271c2_rf_tracking_filters_correction From: Michael Krufky Signed-off-by: Michael Krufky --- linux/drivers/media/common/tuners/tda18271-fe.c | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) (limited to 'linux/drivers/media/common/tuners') diff --git a/linux/drivers/media/common/tuners/tda18271-fe.c b/linux/drivers/media/common/tuners/tda18271-fe.c index 15e2deb3f..e4fbbaa72 100644 --- a/linux/drivers/media/common/tuners/tda18271-fe.c +++ b/linux/drivers/media/common/tuners/tda18271-fe.c @@ -221,11 +221,13 @@ static int tda18271c2_rf_tracking_filters_correction(struct dvb_frontend *fe, struct tda18271_priv *priv = fe->tuner_priv; struct tda18271_rf_tracking_filter_cal *map = priv->rf_cal_state; unsigned char *regs = priv->tda18271_regs; - int tm_current, rfcal_comp, approx, i; + int tm_current, rfcal_comp, approx, i, ret; u8 dc_over_dt, rf_tab; /* power up */ - tda18271_set_standby_mode(fe, 0, 0, 0); + ret = tda18271_set_standby_mode(fe, 0, 0, 0); + if (ret < 0) + goto fail; /* read die current temperature */ tm_current = tda18271_read_thermometer(fe); @@ -258,9 +260,9 @@ static int tda18271c2_rf_tracking_filters_correction(struct dvb_frontend *fe, rfcal_comp = dc_over_dt * (tm_current - priv->tm_rfcal); regs[R_EB14] = approx + rfcal_comp; - tda18271_write_regs(fe, R_EB14, 1); - - return 0; + ret = tda18271_write_regs(fe, R_EB14, 1); +fail: + return ret; } static int tda18271_por(struct dvb_frontend *fe) -- cgit v1.2.3 From 71b667bfafcc16721f19d2546ff8b03b7fe20c5b Mon Sep 17 00:00:00 2001 From: Michael Krufky Date: Sun, 4 May 2008 16:26:47 -0400 Subject: tda18271: fix error handling in tda18271c1_rf_tracking_filter_calibration From: Michael Krufky Signed-off-by: Michael Krufky --- linux/drivers/media/common/tuners/tda18271-fe.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) (limited to 'linux/drivers/media/common/tuners') diff --git a/linux/drivers/media/common/tuners/tda18271-fe.c b/linux/drivers/media/common/tuners/tda18271-fe.c index e4fbbaa72..d963ce4b6 100644 --- a/linux/drivers/media/common/tuners/tda18271-fe.c +++ b/linux/drivers/media/common/tuners/tda18271-fe.c @@ -666,6 +666,7 @@ static int tda18271c1_rf_tracking_filter_calibration(struct dvb_frontend *fe, { struct tda18271_priv *priv = fe->tuner_priv; unsigned char *regs = priv->tda18271_regs; + int ret; u32 N = 0; /* calculate bp filter */ @@ -714,7 +715,10 @@ static int tda18271c1_rf_tracking_filter_calibration(struct dvb_frontend *fe, tda18271_calc_main_pll(fe, N); - tda18271_write_regs(fe, R_EP3, 11); + ret = tda18271_write_regs(fe, R_EP3, 11); + if (ret < 0) + return ret; + msleep(5); /* RF tracking filter calibration initialization */ /* search for K,M,CO for RF calibration */ -- cgit v1.2.3 From 974a77dd9750f19d791952fc153425a2241836b7 Mon Sep 17 00:00:00 2001 From: Michael Krufky Date: Sun, 4 May 2008 17:32:21 -0400 Subject: tda18271: add tda_fail macro to log error cases From: Michael Krufky Signed-off-by: Michael Krufky --- .../drivers/media/common/tuners/tda18271-common.c | 14 +++--- linux/drivers/media/common/tuners/tda18271-fe.c | 56 +++++++++++----------- linux/drivers/media/common/tuners/tda18271-priv.h | 9 ++++ 3 files changed, 44 insertions(+), 35 deletions(-) (limited to 'linux/drivers/media/common/tuners') diff --git a/linux/drivers/media/common/tuners/tda18271-common.c b/linux/drivers/media/common/tuners/tda18271-common.c index 28575e4c5..5bdab8181 100644 --- a/linux/drivers/media/common/tuners/tda18271-common.c +++ b/linux/drivers/media/common/tuners/tda18271-common.c @@ -576,7 +576,7 @@ int tda18271_calc_main_pll(struct dvb_frontend *fe, u32 freq) u32 div; int ret = tda18271_lookup_pll_map(fe, MAIN_PLL, &freq, &pd, &d); - if (ret < 0) + if (tda_fail(ret)) goto fail; regs[R_MPD] = (0x77 & pd); @@ -608,7 +608,7 @@ int tda18271_calc_cal_pll(struct dvb_frontend *fe, u32 freq) u32 div; int ret = tda18271_lookup_pll_map(fe, CAL_PLL, &freq, &pd, &d); - if (ret < 0) + if (tda_fail(ret)) goto fail; regs[R_CPD] = pd; @@ -632,7 +632,7 @@ int tda18271_calc_bp_filter(struct dvb_frontend *fe, u32 *freq) u8 val; int ret = tda18271_lookup_map(fe, BP_FILTER, freq, &val); - if (ret < 0) + if (tda_fail(ret)) goto fail; regs[R_EP1] &= ~0x07; /* clear bp filter bits */ @@ -649,7 +649,7 @@ int tda18271_calc_km(struct dvb_frontend *fe, u32 *freq) u8 val; int ret = tda18271_lookup_map(fe, RF_CAL_KMCO, freq, &val); - if (ret < 0) + if (tda_fail(ret)) goto fail; regs[R_EB13] &= ~0x7c; /* clear k & m bits */ @@ -666,7 +666,7 @@ int tda18271_calc_rf_band(struct dvb_frontend *fe, u32 *freq) u8 val; int ret = tda18271_lookup_map(fe, RF_BAND, freq, &val); - if (ret < 0) + if (tda_fail(ret)) goto fail; regs[R_EP2] &= ~0xe0; /* clear rf band bits */ @@ -683,7 +683,7 @@ int tda18271_calc_gain_taper(struct dvb_frontend *fe, u32 *freq) u8 val; int ret = tda18271_lookup_map(fe, GAIN_TAPER, freq, &val); - if (ret < 0) + if (tda_fail(ret)) goto fail; regs[R_EP2] &= ~0x1f; /* clear gain taper bits */ @@ -700,7 +700,7 @@ int tda18271_calc_ir_measure(struct dvb_frontend *fe, u32 *freq) u8 val; int ret = tda18271_lookup_map(fe, IR_MEASURE, freq, &val); - if (ret < 0) + if (tda_fail(ret)) goto fail; regs[R_EP5] &= ~0x07; diff --git a/linux/drivers/media/common/tuners/tda18271-fe.c b/linux/drivers/media/common/tuners/tda18271-fe.c index d963ce4b6..f9e2957bb 100644 --- a/linux/drivers/media/common/tuners/tda18271-fe.c +++ b/linux/drivers/media/common/tuners/tda18271-fe.c @@ -88,7 +88,7 @@ static int tda18271_channel_configuration(struct dvb_frontend *fe, regs[R_EB22] = 0x00; regs[R_EB22] |= map->rfagc_top; ret = tda18271_write_regs(fe, R_EB22, 1); - if (ret < 0) + if (tda_fail(ret)) goto fail; /* --------------------------------------------------------------- */ @@ -126,7 +126,7 @@ static int tda18271_channel_configuration(struct dvb_frontend *fe, regs[R_EB1] &= ~0x01; ret = tda18271_write_regs(fe, R_EB1, 1); - if (ret < 0) + if (tda_fail(ret)) goto fail; /* --------------------------------------------------------------- */ @@ -148,7 +148,7 @@ static int tda18271_channel_configuration(struct dvb_frontend *fe, } ret = tda18271_write_regs(fe, R_TM, 7); - if (ret < 0) + if (tda_fail(ret)) goto fail; /* force charge pump source */ @@ -226,7 +226,7 @@ static int tda18271c2_rf_tracking_filters_correction(struct dvb_frontend *fe, /* power up */ ret = tda18271_set_standby_mode(fe, 0, 0, 0); - if (ret < 0) + if (tda_fail(ret)) goto fail; /* read die current temperature */ @@ -238,8 +238,8 @@ static int tda18271c2_rf_tracking_filters_correction(struct dvb_frontend *fe, rf_tab = regs[R_EB14]; i = tda18271_lookup_rf_band(fe, &freq, NULL); - if (i < 0) - return -EINVAL; + if (tda_fail(i)) + return i; if ((0 == map[i].rf3) || (freq / 1000 < map[i].rf2)) { approx = map[i].rf_a1 * @@ -274,20 +274,20 @@ static int tda18271_por(struct dvb_frontend *fe) /* power up detector 1 */ regs[R_EB12] &= ~0x20; ret = tda18271_write_regs(fe, R_EB12, 1); - if (ret < 0) + if (tda_fail(ret)) goto fail; regs[R_EB18] &= ~0x80; /* turn agc1 loop on */ regs[R_EB18] &= ~0x03; /* set agc1_gain to 6 dB */ ret = tda18271_write_regs(fe, R_EB18, 1); - if (ret < 0) + if (tda_fail(ret)) goto fail; regs[R_EB21] |= 0x03; /* set agc2_gain to -6 dB */ /* POR mode */ ret = tda18271_set_standby_mode(fe, 1, 0, 0); - if (ret < 0) + if (tda_fail(ret)) goto fail; /* disable 1.5 MHz low pass filter */ @@ -439,7 +439,7 @@ static int tda18271_powerscan(struct dvb_frontend *fe, /* read power detection info, stored in EB10 */ ret = tda18271_read_extended(fe); - if (ret < 0) + if (tda_fail(ret)) return ret; /* algorithm initialization */ @@ -467,7 +467,7 @@ static int tda18271_powerscan(struct dvb_frontend *fe, /* read power detection info, stored in EB10 */ ret = tda18271_read_extended(fe); - if (ret < 0) + if (tda_fail(ret)) return ret; count += 200; @@ -512,12 +512,12 @@ static int tda18271_powerscan_init(struct dvb_frontend *fe) regs[R_EP4] &= ~0x1c; /* clear if level bits */ ret = tda18271_write_regs(fe, R_EP3, 2); - if (ret < 0) + if (tda_fail(ret)) goto fail; regs[R_EB18] &= ~0x03; /* set agc1_gain to 6 dB */ ret = tda18271_write_regs(fe, R_EB18, 1); - if (ret < 0) + if (tda_fail(ret)) goto fail; regs[R_EB21] &= ~0x03; /* set agc2_gain to -15 dB */ @@ -547,7 +547,7 @@ static int tda18271_rf_tracking_filters_init(struct dvb_frontend *fe, u32 freq) i = tda18271_lookup_rf_band(fe, &freq, NULL); - if (i < 0) + if (tda_fail(i)) return i; rf_default[RF1] = 1000 * map[i].rf1_def; @@ -561,7 +561,7 @@ static int tda18271_rf_tracking_filters_init(struct dvb_frontend *fe, u32 freq) /* look for optimized calibration frequency */ bcal = tda18271_powerscan(fe, &rf_default[rf], &rf_freq[rf]); - if (bcal < 0) + if (tda_fail(bcal)) return bcal; tda18271_calc_rf_cal(fe, &rf_freq[rf]); @@ -611,7 +611,7 @@ static int tda18271_calc_rf_filter_curve(struct dvb_frontend *fe) msleep(200); ret = tda18271_powerscan_init(fe); - if (ret < 0) + if (tda_fail(ret)) goto fail; /* rf band calibration */ @@ -619,7 +619,7 @@ static int tda18271_calc_rf_filter_curve(struct dvb_frontend *fe) ret = tda18271_rf_tracking_filters_init(fe, 1000 * priv->rf_cal_state[i].rfmax); - if (ret < 0) + if (tda_fail(ret)) goto fail; } @@ -644,11 +644,11 @@ static int tda18271c2_rf_cal_init(struct dvb_frontend *fe) return 0; ret = tda18271_calc_rf_filter_curve(fe); - if (ret < 0) + if (tda_fail(ret)) goto fail; ret = tda18271_por(fe); - if (ret < 0) + if (tda_fail(ret)) goto fail; tda_info("tda18271: RF tracking filter calibration complete\n"); @@ -716,7 +716,7 @@ static int tda18271c1_rf_tracking_filter_calibration(struct dvb_frontend *fe, tda18271_calc_main_pll(fe, N); ret = tda18271_write_regs(fe, R_EP3, 11); - if (ret < 0) + if (tda_fail(ret)) return ret; msleep(5); /* RF tracking filter calibration initialization */ @@ -769,7 +769,7 @@ static int tda18271_ir_cal_init(struct dvb_frontend *fe) int ret; ret = tda18271_read_regs(fe); - if (ret < 0) + if (tda_fail(ret)) goto fail; /* test IR_CAL_OK to see if we need init */ @@ -788,12 +788,12 @@ static int tda18271_init(struct dvb_frontend *fe) /* power up */ ret = tda18271_set_standby_mode(fe, 0, 0, 0); - if (ret < 0) + if (tda_fail(ret)) goto fail; /* initialization */ ret = tda18271_ir_cal_init(fe); - if (ret < 0) + if (tda_fail(ret)) goto fail; if (priv->id == TDA18271HDC2) @@ -814,7 +814,7 @@ static int tda18271_tune(struct dvb_frontend *fe, freq, map->if_freq, bw, map->agc_mode, map->std); ret = tda18271_init(fe); - if (ret < 0) + if (tda_fail(ret)) goto fail; mutex_lock(&priv->lock); @@ -895,7 +895,7 @@ static int tda18271_set_params(struct dvb_frontend *fe, ret = tda18271_tune(fe, map, freq, bw); - if (ret < 0) + if (tda_fail(ret)) goto fail; priv->frequency = freq; @@ -951,7 +951,7 @@ static int tda18271_set_analog_params(struct dvb_frontend *fe, ret = tda18271_tune(fe, map, freq, 0); - if (ret < 0) + if (tda_fail(ret)) goto fail; priv->frequency = freq; @@ -1154,10 +1154,10 @@ struct dvb_frontend *tda18271_attach(struct dvb_frontend *fe, u8 addr, if (cfg) priv->small_i2c = cfg->small_i2c; - if (tda18271_get_id(fe) < 0) + if (tda_fail(tda18271_get_id(fe))) goto fail; - if (tda18271_assign_map_layout(fe) < 0) + if (tda_fail(tda18271_assign_map_layout(fe))) goto fail; mutex_lock(&priv->lock); diff --git a/linux/drivers/media/common/tuners/tda18271-priv.h b/linux/drivers/media/common/tuners/tda18271-priv.h index 8ceeca081..2ed61a31f 100644 --- a/linux/drivers/media/common/tuners/tda18271-priv.h +++ b/linux/drivers/media/common/tuners/tda18271-priv.h @@ -162,6 +162,15 @@ extern int tda18271_debug; #define tda_reg(fmt, arg...) dprintk(KERN_DEBUG, DBG_REG, fmt, ##arg) #define tda_cal(fmt, arg...) dprintk(KERN_DEBUG, DBG_CAL, fmt, ##arg) +#define tda_fail(ret) \ +({ \ + int __ret; \ + __ret = (ret < 0); \ + if (__ret) \ + tda_printk(KERN_ERR, "error %d on line %d\n", ret, __LINE__);\ + __ret; \ +}) + /*---------------------------------------------------------------------*/ enum tda18271_map_type { -- cgit v1.2.3 From 383d0edbcc8521f7e77d3952121975ff3840b172 Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Tue, 6 May 2008 09:38:24 -0300 Subject: Simplifies Kconfig rules. From: Mauro Carvalho Chehab Since all tuners are dependent of I2C, move I2C dependency to MEDIA_TUNER. Also, simplifies the dependencies for the other Kconfig items. Signed-off-by: Mauro Carvalho Chehab --- linux/drivers/media/common/tuners/Kconfig | 20 ++++---------------- 1 file changed, 4 insertions(+), 16 deletions(-) (limited to 'linux/drivers/media/common/tuners') diff --git a/linux/drivers/media/common/tuners/Kconfig b/linux/drivers/media/common/tuners/Kconfig index c0b472eae..ecbccc3cd 100644 --- a/linux/drivers/media/common/tuners/Kconfig +++ b/linux/drivers/media/common/tuners/Kconfig @@ -19,8 +19,8 @@ config MEDIA_ATTACH config MEDIA_TUNER tristate - default DVB_CORE || VIDEO_DEV - depends on DVB_CORE || VIDEO_DEV + default VIDEO_MEDIA && I2C + depends on VIDEO_MEDIA && I2C select MEDIA_TUNER_XC2028 if !MEDIA_TUNER_CUSTOMIZE select MEDIA_TUNER_XC5000 if !MEDIA_TUNER_CUSTOMIZE select MEDIA_TUNER_MT20XX if !MEDIA_TUNER_CUSTOMIZE @@ -46,7 +46,6 @@ if MEDIA_TUNER_CUSTOMIZE config MEDIA_TUNER_SIMPLE tristate "Simple tuner support" - depends on I2C select MEDIA_TUNER_TDA9887 default m if MEDIA_TUNER_CUSTOMIZE help @@ -54,7 +53,6 @@ config MEDIA_TUNER_SIMPLE config MEDIA_TUNER_TDA8290 tristate "TDA 8290/8295 + 8275(a)/18271 tuner combo" - depends on I2C select MEDIA_TUNER_TDA827X select MEDIA_TUNER_TDA18271 default m if MEDIA_TUNER_CUSTOMIZE @@ -63,21 +61,18 @@ config MEDIA_TUNER_TDA8290 config MEDIA_TUNER_TDA827X tristate "Philips TDA827X silicon tuner" - depends on DVB_CORE && I2C default m if DVB_FE_CUSTOMISE help A DVB-T silicon tuner module. Say Y when you want to support this tuner. config MEDIA_TUNER_TDA18271 tristate "NXP TDA18271 silicon tuner" - depends on I2C default m if DVB_FE_CUSTOMISE help A silicon tuner module. Say Y when you want to support this tuner. config MEDIA_TUNER_TDA9887 tristate "TDA 9885/6/7 analog IF demodulator" - depends on I2C default m if MEDIA_TUNER_CUSTOMIZE help Say Y here to include support for Philips TDA9885/6/7 @@ -85,63 +80,56 @@ config MEDIA_TUNER_TDA9887 config MEDIA_TUNER_TEA5761 tristate "TEA 5761 radio tuner (EXPERIMENTAL)" - depends on I2C && EXPERIMENTAL + depends on EXPERIMENTAL default m if MEDIA_TUNER_CUSTOMIZE help Say Y here to include support for the Philips TEA5761 radio tuner. config MEDIA_TUNER_TEA5767 tristate "TEA 5767 radio tuner" - depends on I2C default m if MEDIA_TUNER_CUSTOMIZE help Say Y here to include support for the Philips TEA5767 radio tuner. config MEDIA_TUNER_MT20XX tristate "Microtune 2032 / 2050 tuners" - depends on I2C default m if MEDIA_TUNER_CUSTOMIZE help Say Y here to include support for the MT2032 / MT2050 tuner. config MEDIA_TUNER_MT2060 tristate "Microtune MT2060 silicon IF tuner" - depends on I2C default m if DVB_FE_CUSTOMISE help A driver for the silicon IF tuner MT2060 from Microtune. config MEDIA_TUNER_MT2266 tristate "Microtune MT2266 silicon tuner" - depends on I2C default m if DVB_FE_CUSTOMISE help A driver for the silicon baseband tuner MT2266 from Microtune. config MEDIA_TUNER_MT2131 tristate "Microtune MT2131 silicon tuner" - depends on I2C default m if DVB_FE_CUSTOMISE help A driver for the silicon baseband tuner MT2131 from Microtune. config MEDIA_TUNER_QT1010 tristate "Quantek QT1010 silicon tuner" - depends on DVB_CORE && I2C default m if DVB_FE_CUSTOMISE help A driver for the silicon tuner QT1010 from Quantek. config MEDIA_TUNER_XC2028 tristate "XCeive xc2028/xc3028 tuners" - depends on I2C && FW_LOADER + depends on FW_LOADER default m if MEDIA_TUNER_CUSTOMIZE help Say Y here to include support for the xc2028/xc3028 tuners. config MEDIA_TUNER_XC5000 tristate "Xceive XC5000 silicon tuner" - depends on I2C select FW_LOADER default m if DVB_FE_CUSTOMISE help -- cgit v1.2.3 From f9de0013eede12a00d0ab63a345afa89a1d2bca4 Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Tue, 6 May 2008 10:44:03 -0300 Subject: Fix dependencies for tuner-xc2028 and em28xx-dvb From: Mauro Carvalho Chehab em28xx-dvb doesn't need FW_LOADER. Instead, tuner-xc2028 needs to select FW_LOADER. Also, this can happen only if HOTPLUG is selected, since FW_LOADER is dependent on HOTPLUG. Signed-off-by: Mauro Carvalho Chehab --- linux/drivers/media/common/tuners/Kconfig | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'linux/drivers/media/common/tuners') diff --git a/linux/drivers/media/common/tuners/Kconfig b/linux/drivers/media/common/tuners/Kconfig index ecbccc3cd..4fb77bc71 100644 --- a/linux/drivers/media/common/tuners/Kconfig +++ b/linux/drivers/media/common/tuners/Kconfig @@ -21,7 +21,7 @@ config MEDIA_TUNER tristate default VIDEO_MEDIA && I2C depends on VIDEO_MEDIA && I2C - select MEDIA_TUNER_XC2028 if !MEDIA_TUNER_CUSTOMIZE + select MEDIA_TUNER_XC2028 if !MEDIA_TUNER_CUSTOMIZE && HOTPLUG select MEDIA_TUNER_XC5000 if !MEDIA_TUNER_CUSTOMIZE select MEDIA_TUNER_MT20XX if !MEDIA_TUNER_CUSTOMIZE select MEDIA_TUNER_TDA8290 if !MEDIA_TUNER_CUSTOMIZE @@ -123,7 +123,8 @@ config MEDIA_TUNER_QT1010 config MEDIA_TUNER_XC2028 tristate "XCeive xc2028/xc3028 tuners" - depends on FW_LOADER + depends on HOTPLUG + select FW_LOADER default m if MEDIA_TUNER_CUSTOMIZE help Say Y here to include support for the xc2028/xc3028 tuners. -- cgit v1.2.3 From d2e4d325373507cb36a3c4993cd675331edad4cd Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Tue, 6 May 2008 11:09:01 -0300 Subject: Fix FW_LOADER depencency at v4l/dvb From: Mauro Carvalho Chehab Since: 1) FW_LOADER is defined as: config FW_LOADER tristate "Userspace firmware loading support" depends on HOTPLUG 2) several V4L/DVB driver just selects it; 3) select is not smart enough to auto-select HOTPLUG, if select FW_LOADER. So, All drivers that select FW_LOADER should also depend on HOTPLUG. An easier solution (for the end-user perspective) would be to "select HOTPLUG". However, live is not simple. This would cause recursive dependency issues like this one: drivers/usb/Kconfig:62:error: found recursive dependency: USB -> USB_OHCI_HCD -> I2C -> MEDIA_TUNER -> MEDIA_TUNER_XC2028 -> HOTPLUG -> PCCARD -> PCMCIA -> USB_ARCH_HAS_HCD -> MOUSE_APPLETOUCH -> USB Signed-off-by: Mauro Carvalho Chehab --- linux/drivers/media/common/tuners/Kconfig | 1 + 1 file changed, 1 insertion(+) (limited to 'linux/drivers/media/common/tuners') diff --git a/linux/drivers/media/common/tuners/Kconfig b/linux/drivers/media/common/tuners/Kconfig index 4fb77bc71..10f12bad1 100644 --- a/linux/drivers/media/common/tuners/Kconfig +++ b/linux/drivers/media/common/tuners/Kconfig @@ -131,6 +131,7 @@ config MEDIA_TUNER_XC2028 config MEDIA_TUNER_XC5000 tristate "Xceive XC5000 silicon tuner" + depends on HOTPLUG select FW_LOADER default m if DVB_FE_CUSTOMISE help -- cgit v1.2.3 From 02e4a810677e35f1776558db988bc728f2fa3af5 Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Thu, 1 May 2008 00:57:01 -0400 Subject: Add mxl5505s driver for MaxiLinear 5505 chipsets From: Steven Toth Initial check-in of the original driver to establish history. Signed-off-by: Chia-Ling Lu Developer Signed-off-by: Steven Toth Signed-off-by: Mauro Carvalho Chehab --- linux/drivers/media/common/tuners/mxl5005s.c | 4989 ++++++++++++++++++++++++++ linux/drivers/media/common/tuners/mxl5005s.h | 718 ++++ 2 files changed, 5707 insertions(+) create mode 100644 linux/drivers/media/common/tuners/mxl5005s.c create mode 100644 linux/drivers/media/common/tuners/mxl5005s.h (limited to 'linux/drivers/media/common/tuners') diff --git a/linux/drivers/media/common/tuners/mxl5005s.c b/linux/drivers/media/common/tuners/mxl5005s.c new file mode 100644 index 000000000..a32475fa1 --- /dev/null +++ b/linux/drivers/media/common/tuners/mxl5005s.c @@ -0,0 +1,4989 @@ +/* + * For the Realtek RTL chip RTL2831U + * Realtek Release Date: 2008-03-14, ver 080314 + * Realtek version RTL2831 Linux driver version 080314 + * ver 080314 + * + * for linux kernel version 2.6.21.4 - 2.6.22-14 + * support MXL5005s and MT2060 tuners (support tuner auto-detecting) + * support two IR types -- RC5 and NEC + * + * Known boards with Realtek RTL chip RTL2821U + * Freecom USB stick 14aa:0160 (version 4) + * Conceptronic CTVDIGRCU + * + * Copyright (c) 2008 Realtek + * Copyright (c) 2008 Jan Hoogenraad, Barnaby Shearer, Andy Hasper + * This code is placed under the terms of the GNU General Public License + * + * Released by Realtek under GPLv2. + * Thanks to Realtek for a lot of support we received ! + * + * Revision: 080314 - original version + */ + + +/** + +@file + +@brief MxL5005S tuner module definition + +One can manipulate MxL5005S tuner through MxL5005S module. +MxL5005S module is derived from tuner module. + +*/ + + +#include "tuner_mxl5005s.h" +#include "tuner_demod_io.h" + + + + + + +/** + +@defgroup MXL5005S_TUNER_MODULE MxL5005S tuner module + +MxL5005S tuner module is drived from tuner base module. + +@see TUNER_BASE_MODULE + +*/ + + + + + +/** + +@defgroup MXL5005S_MODULE_BUILDER MxL5005S module builder +@ingroup MXL5005S_TUNER_MODULE + +One should call MxL5005S module builder before using MxL5005S module. + +*/ +/// @{ + + + + + +/** + +@brief MxL5005S tuner module builder + +Use BuildMxl5005sModule() to build MxL5005S module, set all module function pointers with the corresponding functions, +and initialize module private variables. + + +@param [in] ppTuner Pointer to MxL5005S tuner module pointer +@param [in] pTunerModuleMemory Pointer to an allocated tuner module memory +@param [in] pMxl5005sExtraModuleMemory Pointer to an allocated MxL5005S extra module memory +@param [in] pI2cBridgeModuleMemory Pointer to an allocated I2C bridge module memory +@param [in] DeviceAddr MxL5005S I2C device address +@param [in] CrystalFreqHz MxL5005S crystal frequency in Hz + + +@note \n + -# One should call BuildMxl5005sModule() to build MxL5005S module before using it. + +*/ +void +BuildMxl5005sModule( + TUNER_MODULE **ppTuner, + TUNER_MODULE *pTunerModuleMemory, + MXL5005S_EXTRA_MODULE *pMxl5005sExtraModuleMemory, + BASE_INTERFACE_MODULE *pBaseInterfaceModuleMemory, + I2C_BRIDGE_MODULE *pI2cBridgeModuleMemory, + unsigned char DeviceAddr, + int StandardMode + ) +{ + MXL5005S_EXTRA_MODULE *pExtra; + + int MxlModMode; + int MxlIfMode; + unsigned long MxlBandwitdh; + unsigned long MxlIfFreqHz; + unsigned long MxlCrystalFreqHz; + int MxlAgcMode; + unsigned short MxlTop; + unsigned short MxlIfOutputLoad; + int MxlClockOut; + int MxlDivOut; + int MxlCapSel; + int MxlRssiOnOff; + unsigned char MxlStandard; + unsigned char MxlTfType; + + + + // Set tuner module pointer, tuner extra module pointer, and I2C bridge module pointer. + *ppTuner = pTunerModuleMemory; + (*ppTuner)->pExtra = pMxl5005sExtraModuleMemory; + (*ppTuner)->pBaseInterface = pBaseInterfaceModuleMemory; + (*ppTuner)->pI2cBridge = pI2cBridgeModuleMemory; + + // Get tuner extra module pointer. + pExtra = (MXL5005S_EXTRA_MODULE *)(*ppTuner)->pExtra; + + + // Set I2C bridge tuner arguments. + mxl5005s_SetI2cBridgeModuleTunerArg(*ppTuner); + + + // Set tuner module manipulating function pointers. + (*ppTuner)->SetDeviceAddr = mxl5005s_SetDeviceAddr; + + (*ppTuner)->GetTunerType = mxl5005s_GetTunerType; + (*ppTuner)->GetDeviceAddr = mxl5005s_GetDeviceAddr; + + (*ppTuner)->Initialize = mxl5005s_Initialize; + (*ppTuner)->SetRfFreqHz = mxl5005s_SetRfFreqHz; + (*ppTuner)->GetRfFreqHz = mxl5005s_GetRfFreqHz; + + + // Set tuner extra module manipulating function pointers. + pExtra->SetRegsWithTable = mxl5005s_SetRegsWithTable; + pExtra->SetRegMaskBits = mxl5005s_SetRegMaskBits; + pExtra->SetSpectrumMode = mxl5005s_SetSpectrumMode; + pExtra->SetBandwidthHz = mxl5005s_SetBandwidthHz; + + + // Initialize tuner parameter setting status. + (*ppTuner)->IsDeviceAddrSet = NO; + (*ppTuner)->IsRfFreqHzSet = NO; + + + // Set MxL5005S parameters. + MxlModMode = MXL_DIGITAL_MODE; + MxlIfMode = MXL_ZERO_IF; + MxlBandwitdh = MXL5005S_BANDWIDTH_8MHZ; + MxlIfFreqHz = IF_FREQ_4570000HZ; + MxlCrystalFreqHz = CRYSTAL_FREQ_16000000HZ; + MxlAgcMode = MXL_SINGLE_AGC; + MxlTop = MXL5005S_TOP_25P2; + MxlIfOutputLoad = MXL5005S_IF_OUTPUT_LOAD_200_OHM; + MxlClockOut = MXL_CLOCK_OUT_DISABLE; + MxlDivOut = MXL_DIV_OUT_4; + MxlCapSel = MXL_CAP_SEL_ENABLE; + MxlRssiOnOff = MXL_RSSI_ENABLE; + MxlTfType = MXL_TF_C_H; + + + // Set MxL5005S parameters according to standard mode + switch(StandardMode) + { + default: + case MXL5005S_STANDARD_DVBT: MxlStandard = MXL_DVBT; break; + case MXL5005S_STANDARD_ATSC: MxlStandard = MXL_ATSC; break; + } + + + // Set MxL5005S extra module. + pExtra->AgcMasterByte = (MxlAgcMode == MXL_DUAL_AGC) ? 0x4 : 0x0; + + MXL5005_TunerConfig(&pExtra->MxlDefinedTunerStructure, (unsigned char)MxlModMode, (unsigned char)MxlIfMode, + MxlBandwitdh, MxlIfFreqHz, MxlCrystalFreqHz, (unsigned char)MxlAgcMode, MxlTop, MxlIfOutputLoad, + (unsigned char)MxlClockOut, (unsigned char)MxlDivOut, (unsigned char)MxlCapSel, (unsigned char)MxlRssiOnOff, + MxlStandard, MxlTfType); + + + + // Note: Need to set all module arguments before using module functions. + + + // Set tuner type. + (*ppTuner)->TunerType = TUNER_TYPE_MXL5005S; + + // Set tuner I2C device address. + (*ppTuner)->SetDeviceAddr(*ppTuner, DeviceAddr); + + + return; +} + + + + + +/// @} + + + + + +/** + +@defgroup MXL5005S_MANIPULATING_FUNCTIONS MxL5005S manipulating functions derived from tuner base module +@ingroup MXL5005S_TUNER_MODULE + +One can use the MxL5005S tuner module manipulating interface implemented by MxL5005S manipulating functions to +manipulate MxL5005S tuner. + +*/ +/// @{ + + + + + +/** + +@brief Set MxL5005S tuner I2C device address. + +@note \n + -# MxL5005S tuner builder will set TUNER_FP_SET_DEVICE_ADDR() function pointer with mxl5005s_SetDeviceAddr(). + +@see TUNER_FP_SET_DEVICE_ADDR + +*/ +void +mxl5005s_SetDeviceAddr( + TUNER_MODULE *pTuner, + unsigned char DeviceAddr + ) +{ + // Set tuner I2C device address. + pTuner->DeviceAddr = DeviceAddr; + pTuner->IsDeviceAddrSet = YES; + + + return; +} + + + + + +/** + +@brief Get MxL5005S tuner type. + +@note \n + -# MxL5005S tuner builder will set TUNER_FP_GET_TUNER_TYPE() function pointer with mxl5005s_GetTunerType(). + +@see TUNER_FP_GET_TUNER_TYPE + +*/ +void +mxl5005s_GetTunerType( + TUNER_MODULE *pTuner, + int *pTunerType + ) +{ + // Get tuner type from tuner module. + *pTunerType = pTuner->TunerType; + + + return; +} + + + + + +/** + +@brief Get MxL5005S tuner I2C device address. + +@note \n + -# MxL5005S tuner builder will set TUNER_FP_GET_DEVICE_ADDR() function pointer with mxl5005s_GetDeviceAddr(). + +@see TUNER_FP_GET_DEVICE_ADDR + +*/ +int +mxl5005s_GetDeviceAddr( + TUNER_MODULE *pTuner, + unsigned char *pDeviceAddr + ) +{ + // Get tuner I2C device address from tuner module. + if(pTuner->IsDeviceAddrSet != YES) + goto error_status_get_tuner_i2c_device_addr; + + *pDeviceAddr = pTuner->DeviceAddr; + + + return FUNCTION_SUCCESS; + + +error_status_get_tuner_i2c_device_addr: + return FUNCTION_ERROR; +} + + + + + +/** + +@brief Initialize MxL5005S tuner. + +@note \n + -# MxL5005S tuner builder will set TUNER_FP_INITIALIZE() function pointer with mxl5005s_Initialize(). + +@see TUNER_FP_INITIALIZE + +*/ +int +mxl5005s_Initialize( + struct dvb_usb_device* dib, + TUNER_MODULE *pTuner + ) +{ + MXL5005S_EXTRA_MODULE *pExtra; + + unsigned char AgcMasterByte; + unsigned char AddrTable[MXL5005S_REG_WRITING_TABLE_LEN_MAX]; + unsigned char ByteTable[MXL5005S_REG_WRITING_TABLE_LEN_MAX]; + int TableLen; + + + + // Get tuner extra module. + pExtra = (MXL5005S_EXTRA_MODULE *)pTuner->pExtra; + + + // Get AGC master byte + AgcMasterByte = pExtra->AgcMasterByte; + + + // Initialize MxL5005S tuner according to MxL5005S tuner example code. + + // Tuner initialization stage 0 + MXL_GetMasterControl(ByteTable, MC_SYNTH_RESET); + AddrTable[0] = MASTER_CONTROL_ADDR; + ByteTable[0] |= AgcMasterByte; + + if(pExtra->SetRegsWithTable( dib,pTuner, AddrTable, ByteTable, LEN_1_BYTE) != FUNCTION_SUCCESS) + goto error_status_set_tuner_registers; + + + // Tuner initialization stage 1 + MXL_GetInitRegister(&pExtra->MxlDefinedTunerStructure, AddrTable, ByteTable, &TableLen); + + if(pExtra->SetRegsWithTable( dib,pTuner, AddrTable, ByteTable, TableLen) != FUNCTION_SUCCESS) + goto error_status_set_tuner_registers; + + + return FUNCTION_SUCCESS; + + +error_status_set_tuner_registers: + return FUNCTION_ERROR; +} + + + + + +/** + +@brief Set MxL5005S tuner RF frequency in Hz. + +@note \n + -# MxL5005S tuner builder will set TUNER_FP_SET_RF_FREQ_HZ() function pointer with mxl5005s_SetRfFreqHz(). + +@see TUNER_FP_SET_RF_FREQ_HZ + +*/ +int +mxl5005s_SetRfFreqHz( + struct dvb_usb_device* dib, + TUNER_MODULE *pTuner, + unsigned long RfFreqHz + ) +{ + MXL5005S_EXTRA_MODULE *pExtra; + BASE_INTERFACE_MODULE *pBaseInterface; + + unsigned char AgcMasterByte; + unsigned char AddrTable[MXL5005S_REG_WRITING_TABLE_LEN_MAX]; + unsigned char ByteTable[MXL5005S_REG_WRITING_TABLE_LEN_MAX]; + int TableLen; + + unsigned long IfDivval; + unsigned char MasterControlByte; + + + + // Get tuner extra module and base interface module. + pExtra = (MXL5005S_EXTRA_MODULE *)pTuner->pExtra; + pBaseInterface = pTuner->pBaseInterface; + + + // Get AGC master byte + AgcMasterByte = pExtra->AgcMasterByte; + + + // Set MxL5005S tuner RF frequency according to MxL5005S tuner example code. + + // Tuner RF frequency setting stage 0 + MXL_GetMasterControl(ByteTable, MC_SYNTH_RESET) ; + AddrTable[0] = MASTER_CONTROL_ADDR; + ByteTable[0] |= AgcMasterByte; + + if(pExtra->SetRegsWithTable( dib,pTuner, AddrTable, ByteTable, LEN_1_BYTE) != FUNCTION_SUCCESS) + goto error_status_set_tuner_registers; + + + // Tuner RF frequency setting stage 1 + MXL_TuneRF(&pExtra->MxlDefinedTunerStructure, RfFreqHz); + + MXL_ControlRead(&pExtra->MxlDefinedTunerStructure, IF_DIVVAL, &IfDivval); + + MXL_ControlWrite(&pExtra->MxlDefinedTunerStructure, SEQ_FSM_PULSE, 0); + MXL_ControlWrite(&pExtra->MxlDefinedTunerStructure, SEQ_EXTPOWERUP, 1); + MXL_ControlWrite(&pExtra->MxlDefinedTunerStructure, IF_DIVVAL, 8); + + MXL_GetCHRegister(&pExtra->MxlDefinedTunerStructure, AddrTable, ByteTable, &TableLen) ; + + MXL_GetMasterControl(&MasterControlByte, MC_LOAD_START) ; + AddrTable[TableLen] = MASTER_CONTROL_ADDR ; + ByteTable[TableLen] = MasterControlByte | AgcMasterByte; + TableLen += 1; + + if(pExtra->SetRegsWithTable( dib,pTuner, AddrTable, ByteTable, TableLen) != FUNCTION_SUCCESS) + goto error_status_set_tuner_registers; + + + // Wait 30 ms. + pBaseInterface->WaitMs(pBaseInterface, 30); + + + // Tuner RF frequency setting stage 2 + MXL_ControlWrite(&pExtra->MxlDefinedTunerStructure, SEQ_FSM_PULSE, 1) ; + MXL_ControlWrite(&pExtra->MxlDefinedTunerStructure, IF_DIVVAL, IfDivval) ; + MXL_GetCHRegister_ZeroIF(&pExtra->MxlDefinedTunerStructure, AddrTable, ByteTable, &TableLen) ; + + MXL_GetMasterControl(&MasterControlByte, MC_LOAD_START) ; + AddrTable[TableLen] = MASTER_CONTROL_ADDR ; + ByteTable[TableLen] = MasterControlByte | AgcMasterByte ; + TableLen += 1; + + if(pExtra->SetRegsWithTable( dib,pTuner, AddrTable, ByteTable, TableLen) != FUNCTION_SUCCESS) + goto error_status_set_tuner_registers; + + + // Set tuner RF frequency parameter. + pTuner->RfFreqHz = RfFreqHz; + pTuner->IsRfFreqHzSet = YES; + + + return FUNCTION_SUCCESS; + + +error_status_set_tuner_registers: + return FUNCTION_ERROR; +} + + + + + +/** + +@brief Get MxL5005S tuner RF frequency in Hz. + +@note \n + -# MxL5005S tuner builder will set TUNER_FP_GET_RF_FREQ_HZ() function pointer with mxl5005s_GetRfFreqHz(). + +@see TUNER_FP_GET_RF_FREQ_HZ + +*/ +int +mxl5005s_GetRfFreqHz( + struct dvb_usb_device* dib, + TUNER_MODULE *pTuner, + unsigned long *pRfFreqHz + ) +{ + // Get tuner RF frequency in Hz from tuner module. + if(pTuner->IsRfFreqHzSet != YES) + goto error_status_get_tuner_rf_frequency; + + *pRfFreqHz = pTuner->RfFreqHz; + + + return FUNCTION_SUCCESS; + + +error_status_get_tuner_rf_frequency: + return FUNCTION_ERROR; +} + + + + + +/** + +@brief Set MxL5005S tuner registers with table. + +*/ +/* +int +mxl5005s_SetRegsWithTable( + struct dvb_usb_device* dib, + TUNER_MODULE *pTuner, + unsigned char *pAddrTable, + unsigned char *pByteTable, + int TableLen + ) +{ + BASE_INTERFACE_MODULE *pBaseInterface; + I2C_BRIDGE_MODULE *pI2cBridge; + unsigned char WritingByteNumMax; + + int i; + unsigned char WritingBuffer[I2C_BUFFER_LEN]; + unsigned char WritingIndex; + + + + // Get base interface, I2C bridge, and maximum writing byte number. + pBaseInterface = pTuner->pBaseInterface; + pI2cBridge = pTuner->pI2cBridge; + WritingByteNumMax = pBaseInterface->I2cWritingByteNumMax; + + + // Set registers with table. + // Note: 1. The I2C format of MxL5005S is described as follows: + // start_bit + (device_addr | writing_bit) + (register_addr + writing_byte) * n + stop_bit + // ... + // start_bit + (device_addr | writing_bit) + (register_addr + writing_byte) * m + latch_byte + stop_bit + // 2. The latch_byte is 0xfe. + // 3. The following writing byte separating scheme takes latch_byte as two byte data. + for(i = 0, WritingIndex = 0; i < TableLen; i++) + { + // Put register address and register byte value into writing buffer. + WritingBuffer[WritingIndex] = pAddrTable[i]; + WritingBuffer[WritingIndex + 1] = pByteTable[i]; + WritingIndex += 2; + + // If writing buffer is full, send the I2C writing command with writing buffer. + if(WritingIndex > (WritingByteNumMax - 2)) + { + if(pI2cBridge->ForwardI2cWritingCmd(pI2cBridge, WritingBuffer, WritingIndex) != FUNCTION_SUCCESS) + goto error_status_set_tuner_registers; + + WritingIndex = 0; + } + } + + + // Send the last I2C writing command with writing buffer and latch byte. + WritingBuffer[WritingIndex] = MXL5005S_LATCH_BYTE; + WritingIndex += 1; + + if(pI2cBridge->ForwardI2cWritingCmd(pI2cBridge, WritingBuffer, WritingIndex) != FUNCTION_SUCCESS) + goto error_status_set_tuner_registers; + + + return FUNCTION_SUCCESS; + + +error_status_set_tuner_registers: + return FUNCTION_ERROR; +} +*/ + + +int +mxl5005s_SetRegsWithTable( + struct dvb_usb_device* dib, + TUNER_MODULE *pTuner, + unsigned char *pAddrTable, + unsigned char *pByteTable, + int TableLen + ) +{ + int i; + u8 end_two_bytes_buf[]={ 0 , 0 }; + u8 tuner_addr=0x00; + + pTuner->GetDeviceAddr(pTuner , &tuner_addr); + + for( i = 0 ; i < TableLen - 1 ; i++) + { + if ( TUNER_WI2C(dib , tuner_addr , pAddrTable[i] , &pByteTable[i] , 1 ) ) + return FUNCTION_ERROR; + } + + end_two_bytes_buf[0] = pByteTable[i]; + end_two_bytes_buf[1] = MXL5005S_LATCH_BYTE; + + if ( TUNER_WI2C(dib , tuner_addr , pAddrTable[i] , end_two_bytes_buf , 2 ) ) + return FUNCTION_ERROR; + + return FUNCTION_SUCCESS; +} + + + + + +/** + +@brief Set MxL5005S tuner register bits. + +*/ +int +mxl5005s_SetRegMaskBits( + struct dvb_usb_device* dib, + TUNER_MODULE *pTuner, + unsigned char RegAddr, + unsigned char Msb, + unsigned char Lsb, + const unsigned char WritingValue + ) +{ + MXL5005S_EXTRA_MODULE *pExtra; + + int i; + + unsigned char Mask; + unsigned char Shift; + + unsigned char RegByte; + + + + // Get tuner extra module. + pExtra = (MXL5005S_EXTRA_MODULE *)pTuner->pExtra; + + + // Generate mask and shift according to MSB and LSB. + Mask = 0; + for(i = Lsb; i < (unsigned char)(Msb + 1); i++) + Mask |= 0x1 << i; + + Shift = Lsb; + + + // Get tuner register byte according to register adddress. + MXL_RegRead(&pExtra->MxlDefinedTunerStructure, RegAddr, &RegByte); + + + // Reserve register byte unmask bit with mask and inlay writing value into it. + RegByte &= ~Mask; + RegByte |= (WritingValue << Shift) & Mask; + + + // Update tuner register byte table. + MXL_RegWrite(&pExtra->MxlDefinedTunerStructure, RegAddr, RegByte); + + + // Write tuner register byte with writing byte. + if(pExtra->SetRegsWithTable( dib, pTuner, &RegAddr, &RegByte, LEN_1_BYTE) != FUNCTION_SUCCESS) + goto error_status_set_tuner_registers; + + + return FUNCTION_SUCCESS; + + +error_status_set_tuner_registers: + return FUNCTION_ERROR; +} + + + + + +/** + +@brief Set MxL5005S tuner spectrum mode. + +*/ +int +mxl5005s_SetSpectrumMode( + struct dvb_usb_device* dib, + TUNER_MODULE *pTuner, + int SpectrumMode + ) +{ + static const unsigned char BbIqswapTable[SPECTRUM_MODE_NUM] = + { + // BB_IQSWAP + 0, // Normal spectrum + 1, // Inverse spectrum + }; + + + MXL5005S_EXTRA_MODULE *pExtra; + + + + // Get tuner extra module. + pExtra = (MXL5005S_EXTRA_MODULE *)pTuner->pExtra; + + + // Set BB_IQSWAP according to BB_IQSWAP table and spectrum mode. + if(pExtra->SetRegMaskBits(dib,pTuner, MXL5005S_BB_IQSWAP_ADDR, MXL5005S_BB_IQSWAP_MSB, + MXL5005S_BB_IQSWAP_LSB, BbIqswapTable[SpectrumMode]) != FUNCTION_SUCCESS) + goto error_status_set_tuner_registers; + + + return FUNCTION_SUCCESS; + + +error_status_set_tuner_registers: + return FUNCTION_ERROR; +} + + + + + +/** + +@brief Set MxL5005S tuner bandwidth in Hz. + +*/ +int +mxl5005s_SetBandwidthHz( + struct dvb_usb_device* dib, + TUNER_MODULE *pTuner, + unsigned long BandwidthHz + ) +{ + MXL5005S_EXTRA_MODULE *pExtra; + + unsigned char BbDlpfBandsel; + + + + // Get tuner extra module. + pExtra = (MXL5005S_EXTRA_MODULE *)pTuner->pExtra; + + + // Set BB_DLPF_BANDSEL according to bandwidth. + switch(BandwidthHz) + { + default: + case MXL5005S_BANDWIDTH_6MHZ: BbDlpfBandsel = 3; break; + case MXL5005S_BANDWIDTH_7MHZ: BbDlpfBandsel = 2; break; + case MXL5005S_BANDWIDTH_8MHZ: BbDlpfBandsel = 0; break; + } + + if(pExtra->SetRegMaskBits(dib,pTuner, MXL5005S_BB_DLPF_BANDSEL_ADDR, MXL5005S_BB_DLPF_BANDSEL_MSB, + MXL5005S_BB_DLPF_BANDSEL_LSB, BbDlpfBandsel) != FUNCTION_SUCCESS) + goto error_status_set_tuner_registers; + + + return FUNCTION_SUCCESS; + + +error_status_set_tuner_registers: + return FUNCTION_ERROR; +} + + + + + +/// @} + + + + + +/** + +@defgroup MXL5005S_DEPENDENCE MxL5005S dependence +@ingroup MXL5005S_TUNER_MODULE + +MxL5005S dependence is the related functions for MxL5005S tuner module interface. +One should not use MxL5005S dependence directly. + +*/ +/// @{ + + + + + +/** + +@brief Set I2C bridge module tuner arguments. + +MxL5005S builder will use mxl5005s_SetI2cBridgeModuleTunerArg() to set I2C bridge module tuner arguments. + + +@param [in] pTuner The tuner module pointer + + +@see BuildMxl5005sModule() + +*/ +void +mxl5005s_SetI2cBridgeModuleTunerArg( + TUNER_MODULE *pTuner + ) +{ + I2C_BRIDGE_MODULE *pI2cBridge; + + + + // Get I2C bridge module. + pI2cBridge = pTuner->pI2cBridge; + + // Set I2C bridge module tuner arguments. + pI2cBridge->pTunerDeviceAddr = &pTuner->DeviceAddr; + + + return; +} + + + + + +/// @} + + + + + + + + + + + + + + + + + + + + + + + +// The following context is source code provided by MaxLinear. + + + + + +// MaxLinear source code - MXL5005_Initialize.cpp + + + +//#ifdef _MXL_HEADER +//#include "stdafx.h" +//#endif +//#include "MXL5005_c.h" + +_u16 MXL5005_RegisterInit (Tuner_struct * Tuner) +{ + Tuner->TunerRegs_Num = TUNER_REGS_NUM ; +// Tuner->TunerRegs = (TunerReg_struct *) calloc( TUNER_REGS_NUM, sizeof(TunerReg_struct) ) ; + + Tuner->TunerRegs[0].Reg_Num = 9 ; + Tuner->TunerRegs[0].Reg_Val = 0x40 ; + + Tuner->TunerRegs[1].Reg_Num = 11 ; + Tuner->TunerRegs[1].Reg_Val = 0x19 ; + + Tuner->TunerRegs[2].Reg_Num = 12 ; + Tuner->TunerRegs[2].Reg_Val = 0x60 ; + + Tuner->TunerRegs[3].Reg_Num = 13 ; + Tuner->TunerRegs[3].Reg_Val = 0x00 ; + + Tuner->TunerRegs[4].Reg_Num = 14 ; + Tuner->TunerRegs[4].Reg_Val = 0x00 ; + + Tuner->TunerRegs[5].Reg_Num = 15 ; + Tuner->TunerRegs[5].Reg_Val = 0xC0 ; + + Tuner->TunerRegs[6].Reg_Num = 16 ; + Tuner->TunerRegs[6].Reg_Val = 0x00 ; + + Tuner->TunerRegs[7].Reg_Num = 17 ; + Tuner->TunerRegs[7].Reg_Val = 0x00 ; + + Tuner->TunerRegs[8].Reg_Num = 18 ; + Tuner->TunerRegs[8].Reg_Val = 0x00 ; + + Tuner->TunerRegs[9].Reg_Num = 19 ; + Tuner->TunerRegs[9].Reg_Val = 0x34 ; + + Tuner->TunerRegs[10].Reg_Num = 21 ; + Tuner->TunerRegs[10].Reg_Val = 0x00 ; + + Tuner->TunerRegs[11].Reg_Num = 22 ; + Tuner->TunerRegs[11].Reg_Val = 0x6B ; + + Tuner->TunerRegs[12].Reg_Num = 23 ; + Tuner->TunerRegs[12].Reg_Val = 0x35 ; + + Tuner->TunerRegs[13].Reg_Num = 24 ; + Tuner->TunerRegs[13].Reg_Val = 0x70 ; + + Tuner->TunerRegs[14].Reg_Num = 25 ; + Tuner->TunerRegs[14].Reg_Val = 0x3E ; + + Tuner->TunerRegs[15].Reg_Num = 26 ; + Tuner->TunerRegs[15].Reg_Val = 0x82 ; + + Tuner->TunerRegs[16].Reg_Num = 31 ; + Tuner->TunerRegs[16].Reg_Val = 0x00 ; + + Tuner->TunerRegs[17].Reg_Num = 32 ; + Tuner->TunerRegs[17].Reg_Val = 0x40 ; + + Tuner->TunerRegs[18].Reg_Num = 33 ; + Tuner->TunerRegs[18].Reg_Val = 0x53 ; + + Tuner->TunerRegs[19].Reg_Num = 34 ; + Tuner->TunerRegs[19].Reg_Val = 0x81 ; + + Tuner->TunerRegs[20].Reg_Num = 35 ; + Tuner->TunerRegs[20].Reg_Val = 0xC9 ; + + Tuner->TunerRegs[21].Reg_Num = 36 ; + Tuner->TunerRegs[21].Reg_Val = 0x01 ; + + Tuner->TunerRegs[22].Reg_Num = 37 ; + Tuner->TunerRegs[22].Reg_Val = 0x00 ; + + Tuner->TunerRegs[23].Reg_Num = 41 ; + Tuner->TunerRegs[23].Reg_Val = 0x00 ; + + Tuner->TunerRegs[24].Reg_Num = 42 ; + Tuner->TunerRegs[24].Reg_Val = 0xF8 ; + + Tuner->TunerRegs[25].Reg_Num = 43 ; + Tuner->TunerRegs[25].Reg_Val = 0x43 ; + + Tuner->TunerRegs[26].Reg_Num = 44 ; + Tuner->TunerRegs[26].Reg_Val = 0x20 ; + + Tuner->TunerRegs[27].Reg_Num = 45 ; + Tuner->TunerRegs[27].Reg_Val = 0x80 ; + + Tuner->TunerRegs[28].Reg_Num = 46 ; + Tuner->TunerRegs[28].Reg_Val = 0x88 ; + + Tuner->TunerRegs[29].Reg_Num = 47 ; + Tuner->TunerRegs[29].Reg_Val = 0x86 ; + + Tuner->TunerRegs[30].Reg_Num = 48 ; + Tuner->TunerRegs[30].Reg_Val = 0x00 ; + + Tuner->TunerRegs[31].Reg_Num = 49 ; + Tuner->TunerRegs[31].Reg_Val = 0x00 ; + + Tuner->TunerRegs[32].Reg_Num = 53 ; + Tuner->TunerRegs[32].Reg_Val = 0x94 ; + + Tuner->TunerRegs[33].Reg_Num = 54 ; + Tuner->TunerRegs[33].Reg_Val = 0xFA ; + + Tuner->TunerRegs[34].Reg_Num = 55 ; + Tuner->TunerRegs[34].Reg_Val = 0x92 ; + + Tuner->TunerRegs[35].Reg_Num = 56 ; + Tuner->TunerRegs[35].Reg_Val = 0x80 ; + + Tuner->TunerRegs[36].Reg_Num = 57 ; + Tuner->TunerRegs[36].Reg_Val = 0x41 ; + + Tuner->TunerRegs[37].Reg_Num = 58 ; + Tuner->TunerRegs[37].Reg_Val = 0xDB ; + + Tuner->TunerRegs[38].Reg_Num = 59 ; + Tuner->TunerRegs[38].Reg_Val = 0x00 ; + + Tuner->TunerRegs[39].Reg_Num = 60 ; + Tuner->TunerRegs[39].Reg_Val = 0x00 ; + + Tuner->TunerRegs[40].Reg_Num = 61 ; + Tuner->TunerRegs[40].Reg_Val = 0x00 ; + + Tuner->TunerRegs[41].Reg_Num = 62 ; + Tuner->TunerRegs[41].Reg_Val = 0x00 ; + + Tuner->TunerRegs[42].Reg_Num = 65 ; + Tuner->TunerRegs[42].Reg_Val = 0xF8 ; + + Tuner->TunerRegs[43].Reg_Num = 66 ; + Tuner->TunerRegs[43].Reg_Val = 0xE4 ; + + Tuner->TunerRegs[44].Reg_Num = 67 ; + Tuner->TunerRegs[44].Reg_Val = 0x90 ; + + Tuner->TunerRegs[45].Reg_Num = 68 ; + Tuner->TunerRegs[45].Reg_Val = 0xC0 ; + + Tuner->TunerRegs[46].Reg_Num = 69 ; + Tuner->TunerRegs[46].Reg_Val = 0x01 ; + + Tuner->TunerRegs[47].Reg_Num = 70 ; + Tuner->TunerRegs[47].Reg_Val = 0x50 ; + + Tuner->TunerRegs[48].Reg_Num = 71 ; + Tuner->TunerRegs[48].Reg_Val = 0x06 ; + + Tuner->TunerRegs[49].Reg_Num = 72 ; + Tuner->TunerRegs[49].Reg_Val = 0x00 ; + + Tuner->TunerRegs[50].Reg_Num = 73 ; + Tuner->TunerRegs[50].Reg_Val = 0x20 ; + + Tuner->TunerRegs[51].Reg_Num = 76 ; + Tuner->TunerRegs[51].Reg_Val = 0xBB ; + + Tuner->TunerRegs[52].Reg_Num = 77 ; + Tuner->TunerRegs[52].Reg_Val = 0x13 ; + + Tuner->TunerRegs[53].Reg_Num = 81 ; + Tuner->TunerRegs[53].Reg_Val = 0x04 ; + + Tuner->TunerRegs[54].Reg_Num = 82 ; + Tuner->TunerRegs[54].Reg_Val = 0x75 ; + + Tuner->TunerRegs[55].Reg_Num = 83 ; + Tuner->TunerRegs[55].Reg_Val = 0x00 ; + + Tuner->TunerRegs[56].Reg_Num = 84 ; + Tuner->TunerRegs[56].Reg_Val = 0x00 ; + + Tuner->TunerRegs[57].Reg_Num = 85 ; + Tuner->TunerRegs[57].Reg_Val = 0x00 ; + + Tuner->TunerRegs[58].Reg_Num = 91 ; + Tuner->TunerRegs[58].Reg_Val = 0x70 ; + + Tuner->TunerRegs[59].Reg_Num = 92 ; + Tuner->TunerRegs[59].Reg_Val = 0x00 ; + + Tuner->TunerRegs[60].Reg_Num = 93 ; + Tuner->TunerRegs[60].Reg_Val = 0x00 ; + + Tuner->TunerRegs[61].Reg_Num = 94 ; + Tuner->TunerRegs[61].Reg_Val = 0x00 ; + + Tuner->TunerRegs[62].Reg_Num = 95 ; + Tuner->TunerRegs[62].Reg_Val = 0x0C ; + + Tuner->TunerRegs[63].Reg_Num = 96 ; + Tuner->TunerRegs[63].Reg_Val = 0x00 ; + + Tuner->TunerRegs[64].Reg_Num = 97 ; + Tuner->TunerRegs[64].Reg_Val = 0x00 ; + + Tuner->TunerRegs[65].Reg_Num = 98 ; + Tuner->TunerRegs[65].Reg_Val = 0xE2 ; + + Tuner->TunerRegs[66].Reg_Num = 99 ; + Tuner->TunerRegs[66].Reg_Val = 0x00 ; + + Tuner->TunerRegs[67].Reg_Num = 100 ; + Tuner->TunerRegs[67].Reg_Val = 0x00 ; + + Tuner->TunerRegs[68].Reg_Num = 101 ; + Tuner->TunerRegs[68].Reg_Val = 0x12 ; + + Tuner->TunerRegs[69].Reg_Num = 102 ; + Tuner->TunerRegs[69].Reg_Val = 0x80 ; + + Tuner->TunerRegs[70].Reg_Num = 103 ; + Tuner->TunerRegs[70].Reg_Val = 0x32 ; + + Tuner->TunerRegs[71].Reg_Num = 104 ; + Tuner->TunerRegs[71].Reg_Val = 0xB4 ; + + Tuner->TunerRegs[72].Reg_Num = 105 ; + Tuner->TunerRegs[72].Reg_Val = 0x60 ; + + Tuner->TunerRegs[73].Reg_Num = 106 ; + Tuner->TunerRegs[73].Reg_Val = 0x83 ; + + Tuner->TunerRegs[74].Reg_Num = 107 ; + Tuner->TunerRegs[74].Reg_Val = 0x84 ; + + Tuner->TunerRegs[75].Reg_Num = 108 ; + Tuner->TunerRegs[75].Reg_Val = 0x9C ; + + Tuner->TunerRegs[76].Reg_Num = 109 ; + Tuner->TunerRegs[76].Reg_Val = 0x02 ; + + Tuner->TunerRegs[77].Reg_Num = 110 ; + Tuner->TunerRegs[77].Reg_Val = 0x81 ; + + Tuner->TunerRegs[78].Reg_Num = 111 ; + Tuner->TunerRegs[78].Reg_Val = 0xC0 ; + + Tuner->TunerRegs[79].Reg_Num = 112 ; + Tuner->TunerRegs[79].Reg_Val = 0x10 ; + + Tuner->TunerRegs[80].Reg_Num = 131 ; + Tuner->TunerRegs[80].Reg_Val = 0x8A ; + + Tuner->TunerRegs[81].Reg_Num = 132 ; + Tuner->TunerRegs[81].Reg_Val = 0x10 ; + + Tuner->TunerRegs[82].Reg_Num = 133 ; + Tuner->TunerRegs[82].Reg_Val = 0x24 ; + + Tuner->TunerRegs[83].Reg_Num = 134 ; + Tuner->TunerRegs[83].Reg_Val = 0x00 ; + + Tuner->TunerRegs[84].Reg_Num = 135 ; + Tuner->TunerRegs[84].Reg_Val = 0x00 ; + + Tuner->TunerRegs[85].Reg_Num = 136 ; + Tuner->TunerRegs[85].Reg_Val = 0x7E ; + + Tuner->TunerRegs[86].Reg_Num = 137 ; + Tuner->TunerRegs[86].Reg_Val = 0x40 ; + + Tuner->TunerRegs[87].Reg_Num = 138 ; + Tuner->TunerRegs[87].Reg_Val = 0x38 ; + + Tuner->TunerRegs[88].Reg_Num = 146 ; + Tuner->TunerRegs[88].Reg_Val = 0xF6 ; + + Tuner->TunerRegs[89].Reg_Num = 147 ; + Tuner->TunerRegs[89].Reg_Val = 0x1A ; + + Tuner->TunerRegs[90].Reg_Num = 148 ; + Tuner->TunerRegs[90].Reg_Val = 0x62 ; + + Tuner->TunerRegs[91].Reg_Num = 149 ; + Tuner->TunerRegs[91].Reg_Val = 0x33 ; + + Tuner->TunerRegs[92].Reg_Num = 150 ; + Tuner->TunerRegs[92].Reg_Val = 0x80 ; + + Tuner->TunerRegs[93].Reg_Num = 156 ; + Tuner->TunerRegs[93].Reg_Val = 0x56 ; + + Tuner->TunerRegs[94].Reg_Num = 157 ; + Tuner->TunerRegs[94].Reg_Val = 0x17 ; + + Tuner->TunerRegs[95].Reg_Num = 158 ; + Tuner->TunerRegs[95].Reg_Val = 0xA9 ; + + Tuner->TunerRegs[96].Reg_Num = 159 ; + Tuner->TunerRegs[96].Reg_Val = 0x00 ; + + Tuner->TunerRegs[97].Reg_Num = 160 ; + Tuner->TunerRegs[97].Reg_Val = 0x00 ; + + Tuner->TunerRegs[98].Reg_Num = 161 ; + Tuner->TunerRegs[98].Reg_Val = 0x00 ; + + Tuner->TunerRegs[99].Reg_Num = 162 ; + Tuner->TunerRegs[99].Reg_Val = 0x40 ; + + Tuner->TunerRegs[100].Reg_Num = 166 ; + Tuner->TunerRegs[100].Reg_Val = 0xAE ; + + Tuner->TunerRegs[101].Reg_Num = 167 ; + Tuner->TunerRegs[101].Reg_Val = 0x1B ; + + Tuner->TunerRegs[102].Reg_Num = 168 ; + Tuner->TunerRegs[102].Reg_Val = 0xF2 ; + + Tuner->TunerRegs[103].Reg_Num = 195 ; + Tuner->TunerRegs[103].Reg_Val = 0x00 ; + + return 0 ; +} + +_u16 MXL5005_ControlInit (Tuner_struct *Tuner) +{ + Tuner->Init_Ctrl_Num = INITCTRL_NUM ; + + Tuner->Init_Ctrl[0].Ctrl_Num = DN_IQTN_AMP_CUT ; + Tuner->Init_Ctrl[0].size = 1 ; + Tuner->Init_Ctrl[0].addr[0] = 73; + Tuner->Init_Ctrl[0].bit[0] = 7; + Tuner->Init_Ctrl[0].val[0] = 0; + + Tuner->Init_Ctrl[1].Ctrl_Num = BB_MODE ; + Tuner->Init_Ctrl[1].size = 1 ; + Tuner->Init_Ctrl[1].addr[0] = 53; + Tuner->Init_Ctrl[1].bit[0] = 2; + Tuner->Init_Ctrl[1].val[0] = 1; + + Tuner->Init_Ctrl[2].Ctrl_Num = BB_BUF ; + Tuner->Init_Ctrl[2].size = 2 ; + Tuner->Init_Ctrl[2].addr[0] = 53; + Tuner->Init_Ctrl[2].bit[0] = 1; + Tuner->Init_Ctrl[2].val[0] = 0; + Tuner->Init_Ctrl[2].addr[1] = 57; + Tuner->Init_Ctrl[2].bit[1] = 0; + Tuner->Init_Ctrl[2].val[1] = 1; + + Tuner->Init_Ctrl[3].Ctrl_Num = BB_BUF_OA ; + Tuner->Init_Ctrl[3].size = 1 ; + Tuner->Init_Ctrl[3].addr[0] = 53; + Tuner->Init_Ctrl[3].bit[0] = 0; + Tuner->Init_Ctrl[3].val[0] = 0; + + Tuner->Init_Ctrl[4].Ctrl_Num = BB_ALPF_BANDSELECT ; + Tuner->Init_Ctrl[4].size = 3 ; + Tuner->Init_Ctrl[4].addr[0] = 53; + Tuner->Init_Ctrl[4].bit[0] = 5; + Tuner->Init_Ctrl[4].val[0] = 0; + Tuner->Init_Ctrl[4].addr[1] = 53; + Tuner->Init_Ctrl[4].bit[1] = 6; + Tuner->Init_Ctrl[4].val[1] = 0; + Tuner->Init_Ctrl[4].addr[2] = 53; + Tuner->Init_Ctrl[4].bit[2] = 7; + Tuner->Init_Ctrl[4].val[2] = 1; + + Tuner->Init_Ctrl[5].Ctrl_Num = BB_IQSWAP ; + Tuner->Init_Ctrl[5].size = 1 ; + Tuner->Init_Ctrl[5].addr[0] = 59; + Tuner->Init_Ctrl[5].bit[0] = 0; + Tuner->Init_Ctrl[5].val[0] = 0; + + Tuner->Init_Ctrl[6].Ctrl_Num = BB_DLPF_BANDSEL ; + Tuner->Init_Ctrl[6].size = 2 ; + Tuner->Init_Ctrl[6].addr[0] = 53; + Tuner->Init_Ctrl[6].bit[0] = 3; + Tuner->Init_Ctrl[6].val[0] = 0; + Tuner->Init_Ctrl[6].addr[1] = 53; + Tuner->Init_Ctrl[6].bit[1] = 4; + Tuner->Init_Ctrl[6].val[1] = 1; + + Tuner->Init_Ctrl[7].Ctrl_Num = RFSYN_CHP_GAIN ; + Tuner->Init_Ctrl[7].size = 4 ; + Tuner->Init_Ctrl[7].addr[0] = 22; + Tuner->Init_Ctrl[7].bit[0] = 4; + Tuner->Init_Ctrl[7].val[0] = 0; + Tuner->Init_Ctrl[7].addr[1] = 22; + Tuner->Init_Ctrl[7].bit[1] = 5; + Tuner->Init_Ctrl[7].val[1] = 1; + Tuner->Init_Ctrl[7].addr[2] = 22; + Tuner->Init_Ctrl[7].bit[2] = 6; + Tuner->Init_Ctrl[7].val[2] = 1; + Tuner->Init_Ctrl[7].addr[3] = 22; + Tuner->Init_Ctrl[7].bit[3] = 7; + Tuner->Init_Ctrl[7].val[3] = 0; + + Tuner->Init_Ctrl[8].Ctrl_Num = RFSYN_EN_CHP_HIGAIN ; + Tuner->Init_Ctrl[8].size = 1 ; + Tuner->Init_Ctrl[8].addr[0] = 22; + Tuner->Init_Ctrl[8].bit[0] = 2; + Tuner->Init_Ctrl[8].val[0] = 0; + + Tuner->Init_Ctrl[9].Ctrl_Num = AGC_IF ; + Tuner->Init_Ctrl[9].size = 4 ; + Tuner->Init_Ctrl[9].addr[0] = 76; + Tuner->Init_Ctrl[9].bit[0] = 0; + Tuner->Init_Ctrl[9].val[0] = 1; + Tuner->Init_Ctrl[9].addr[1] = 76; + Tuner->Init_Ctrl[9].bit[1] = 1; + Tuner->Init_Ctrl[9].val[1] = 1; + Tuner->Init_Ctrl[9].addr[2] = 76; + Tuner->Init_Ctrl[9].bit[2] = 2; + Tuner->Init_Ctrl[9].val[2] = 0; + Tuner->Init_Ctrl[9].addr[3] = 76; + Tuner->Init_Ctrl[9].bit[3] = 3; + Tuner->Init_Ctrl[9].val[3] = 1; + + Tuner->Init_Ctrl[10].Ctrl_Num = AGC_RF ; + Tuner->Init_Ctrl[10].size = 4 ; + Tuner->Init_Ctrl[10].addr[0] = 76; + Tuner->Init_Ctrl[10].bit[0] = 4; + Tuner->Init_Ctrl[10].val[0] = 1; + Tuner->Init_Ctrl[10].addr[1] = 76; + Tuner->Init_Ctrl[10].bit[1] = 5; + Tuner->Init_Ctrl[10].val[1] = 1; + Tuner->Init_Ctrl[10].addr[2] = 76; + Tuner->Init_Ctrl[10].bit[2] = 6; + Tuner->Init_Ctrl[10].val[2] = 0; + Tuner->Init_Ctrl[10].addr[3] = 76; + Tuner->Init_Ctrl[10].bit[3] = 7; + Tuner->Init_Ctrl[10].val[3] = 1; + + Tuner->Init_Ctrl[11].Ctrl_Num = IF_DIVVAL ; + Tuner->Init_Ctrl[11].size = 5 ; + Tuner->Init_Ctrl[11].addr[0] = 43; + Tuner->Init_Ctrl[11].bit[0] = 3; + Tuner->Init_Ctrl[11].val[0] = 0; + Tuner->Init_Ctrl[11].addr[1] = 43; + Tuner->Init_Ctrl[11].bit[1] = 4; + Tuner->Init_Ctrl[11].val[1] = 0; + Tuner->Init_Ctrl[11].addr[2] = 43; + Tuner->Init_Ctrl[11].bit[2] = 5; + Tuner->Init_Ctrl[11].val[2] = 0; + Tuner->Init_Ctrl[11].addr[3] = 43; + Tuner->Init_Ctrl[11].bit[3] = 6; + Tuner->Init_Ctrl[11].val[3] = 1; + Tuner->Init_Ctrl[11].addr[4] = 43; + Tuner->Init_Ctrl[11].bit[4] = 7; + Tuner->Init_Ctrl[11].val[4] = 0; + + Tuner->Init_Ctrl[12].Ctrl_Num = IF_VCO_BIAS ; + Tuner->Init_Ctrl[12].size = 6 ; + Tuner->Init_Ctrl[12].addr[0] = 44; + Tuner->Init_Ctrl[12].bit[0] = 2; + Tuner->Init_Ctrl[12].val[0] = 0; + Tuner->Init_Ctrl[12].addr[1] = 44; + Tuner->Init_Ctrl[12].bit[1] = 3; + Tuner->Init_Ctrl[12].val[1] = 0; + Tuner->Init_Ctrl[12].addr[2] = 44; + Tuner->Init_Ctrl[12].bit[2] = 4; + Tuner->Init_Ctrl[12].val[2] = 0; + Tuner->Init_Ctrl[12].addr[3] = 44; + Tuner->Init_Ctrl[12].bit[3] = 5; + Tuner->Init_Ctrl[12].val[3] = 1; + Tuner->Init_Ctrl[12].addr[4] = 44; + Tuner->Init_Ctrl[12].bit[4] = 6; + Tuner->Init_Ctrl[12].val[4] = 0; + Tuner->Init_Ctrl[12].addr[5] = 44; + Tuner->Init_Ctrl[12].bit[5] = 7; + Tuner->Init_Ctrl[12].val[5] = 0; + + Tuner->Init_Ctrl[13].Ctrl_Num = CHCAL_INT_MOD_IF ; + Tuner->Init_Ctrl[13].size = 7 ; + Tuner->Init_Ctrl[13].addr[0] = 11; + Tuner->Init_Ctrl[13].bit[0] = 0; + Tuner->Init_Ctrl[13].val[0] = 1; + Tuner->Init_Ctrl[13].addr[1] = 11; + Tuner->Init_Ctrl[13].bit[1] = 1; + Tuner->Init_Ctrl[13].val[1] = 0; + Tuner->Init_Ctrl[13].addr[2] = 11; + Tuner->Init_Ctrl[13].bit[2] = 2; + Tuner->Init_Ctrl[13].val[2] = 0; + Tuner->Init_Ctrl[13].addr[3] = 11; + Tuner->Init_Ctrl[13].bit[3] = 3; + Tuner->Init_Ctrl[13].val[3] = 1; + Tuner->Init_Ctrl[13].addr[4] = 11; + Tuner->Init_Ctrl[13].bit[4] = 4; + Tuner->Init_Ctrl[13].val[4] = 1; + Tuner->Init_Ctrl[13].addr[5] = 11; + Tuner->Init_Ctrl[13].bit[5] = 5; + Tuner->Init_Ctrl[13].val[5] = 0; + Tuner->Init_Ctrl[13].addr[6] = 11; + Tuner->Init_Ctrl[13].bit[6] = 6; + Tuner->Init_Ctrl[13].val[6] = 0; + + Tuner->Init_Ctrl[14].Ctrl_Num = CHCAL_FRAC_MOD_IF ; + Tuner->Init_Ctrl[14].size = 16 ; + Tuner->Init_Ctrl[14].addr[0] = 13; + Tuner->Init_Ctrl[14].bit[0] = 0; + Tuner->Init_Ctrl[14].val[0] = 0; + Tuner->Init_Ctrl[14].addr[1] = 13; + Tuner->Init_Ctrl[14].bit[1] = 1; + Tuner->Init_Ctrl[14].val[1] = 0; + Tuner->Init_Ctrl[14].addr[2] = 13; + Tuner->Init_Ctrl[14].bit[2] = 2; + Tuner->Init_Ctrl[14].val[2] = 0; + Tuner->Init_Ctrl[14].addr[3] = 13; + Tuner->Init_Ctrl[14].bit[3] = 3; + Tuner->Init_Ctrl[14].val[3] = 0; + Tuner->Init_Ctrl[14].addr[4] = 13; + Tuner->Init_Ctrl[14].bit[4] = 4; + Tuner->Init_Ctrl[14].val[4] = 0; + Tuner->Init_Ctrl[14].addr[5] = 13; + Tuner->Init_Ctrl[14].bit[5] = 5; + Tuner->Init_Ctrl[14].val[5] = 0; + Tuner->Init_Ctrl[14].addr[6] = 13; + Tuner->Init_Ctrl[14].bit[6] = 6; + Tuner->Init_Ctrl[14].val[6] = 0; + Tuner->Init_Ctrl[14].addr[7] = 13; + Tuner->Init_Ctrl[14].bit[7] = 7; + Tuner->Init_Ctrl[14].val[7] = 0; + Tuner->Init_Ctrl[14].addr[8] = 12; + Tuner->Init_Ctrl[14].bit[8] = 0; + Tuner->Init_Ctrl[14].val[8] = 0; + Tuner->Init_Ctrl[14].addr[9] = 12; + Tuner->Init_Ctrl[14].bit[9] = 1; + Tuner->Init_Ctrl[14].val[9] = 0; + Tuner->Init_Ctrl[14].addr[10] = 12; + Tuner->Init_Ctrl[14].bit[10] = 2; + Tuner->Init_Ctrl[14].val[10] = 0; + Tuner->Init_Ctrl[14].addr[11] = 12; + Tuner->Init_Ctrl[14].bit[11] = 3; + Tuner->Init_Ctrl[14].val[11] = 0; + Tuner->Init_Ctrl[14].addr[12] = 12; + Tuner->Init_Ctrl[14].bit[12] = 4; + Tuner->Init_Ctrl[14].val[12] = 0; + Tuner->Init_Ctrl[14].addr[13] = 12; + Tuner->Init_Ctrl[14].bit[13] = 5; + Tuner->Init_Ctrl[14].val[13] = 1; + Tuner->Init_Ctrl[14].addr[14] = 12; + Tuner->Init_Ctrl[14].bit[14] = 6; + Tuner->Init_Ctrl[14].val[14] = 1; + Tuner->Init_Ctrl[14].addr[15] = 12; + Tuner->Init_Ctrl[14].bit[15] = 7; + Tuner->Init_Ctrl[14].val[15] = 0; + + Tuner->Init_Ctrl[15].Ctrl_Num = DRV_RES_SEL ; + Tuner->Init_Ctrl[15].size = 3 ; + Tuner->Init_Ctrl[15].addr[0] = 147; + Tuner->Init_Ctrl[15].bit[0] = 2; + Tuner->Init_Ctrl[15].val[0] = 0; + Tuner->Init_Ctrl[15].addr[1] = 147; + Tuner->Init_Ctrl[15].bit[1] = 3; + Tuner->Init_Ctrl[15].val[1] = 1; + Tuner->Init_Ctrl[15].addr[2] = 147; + Tuner->Init_Ctrl[15].bit[2] = 4; + Tuner->Init_Ctrl[15].val[2] = 1; + + Tuner->Init_Ctrl[16].Ctrl_Num = I_DRIVER ; + Tuner->Init_Ctrl[16].size = 2 ; + Tuner->Init_Ctrl[16].addr[0] = 147; + Tuner->Init_Ctrl[16].bit[0] = 0; + Tuner->Init_Ctrl[16].val[0] = 0; + Tuner->Init_Ctrl[16].addr[1] = 147; + Tuner->Init_Ctrl[16].bit[1] = 1; + Tuner->Init_Ctrl[16].val[1] = 1; + + Tuner->Init_Ctrl[17].Ctrl_Num = EN_AAF ; + Tuner->Init_Ctrl[17].size = 1 ; + Tuner->Init_Ctrl[17].addr[0] = 147; + Tuner->Init_Ctrl[17].bit[0] = 7; + Tuner->Init_Ctrl[17].val[0] = 0; + + Tuner->Init_Ctrl[18].Ctrl_Num = EN_3P ; + Tuner->Init_Ctrl[18].size = 1 ; + Tuner->Init_Ctrl[18].addr[0] = 147; + Tuner->Init_Ctrl[18].bit[0] = 6; + Tuner->Init_Ctrl[18].val[0] = 0; + + Tuner->Init_Ctrl[19].Ctrl_Num = EN_AUX_3P ; + Tuner->Init_Ctrl[19].size = 1 ; + Tuner->Init_Ctrl[19].addr[0] = 156; + Tuner->Init_Ctrl[19].bit[0] = 0; + Tuner->Init_Ctrl[19].val[0] = 0; + + Tuner->Init_Ctrl[20].Ctrl_Num = SEL_AAF_BAND ; + Tuner->Init_Ctrl[20].size = 1 ; + Tuner->Init_Ctrl[20].addr[0] = 147; + Tuner->Init_Ctrl[20].bit[0] = 5; + Tuner->Init_Ctrl[20].val[0] = 0; + + Tuner->Init_Ctrl[21].Ctrl_Num = SEQ_ENCLK16_CLK_OUT ; + Tuner->Init_Ctrl[21].size = 1 ; + Tuner->Init_Ctrl[21].addr[0] = 137; + Tuner->Init_Ctrl[21].bit[0] = 4; + Tuner->Init_Ctrl[21].val[0] = 0; + + Tuner->Init_Ctrl[22].Ctrl_Num = SEQ_SEL4_16B ; + Tuner->Init_Ctrl[22].size = 1 ; + Tuner->Init_Ctrl[22].addr[0] = 137; + Tuner->Init_Ctrl[22].bit[0] = 7; + Tuner->Init_Ctrl[22].val[0] = 0; + + Tuner->Init_Ctrl[23].Ctrl_Num = XTAL_CAPSELECT ; + Tuner->Init_Ctrl[23].size = 1 ; + Tuner->Init_Ctrl[23].addr[0] = 91; + Tuner->Init_Ctrl[23].bit[0] = 5; + Tuner->Init_Ctrl[23].val[0] = 1; + + Tuner->Init_Ctrl[24].Ctrl_Num = IF_SEL_DBL ; + Tuner->Init_Ctrl[24].size = 1 ; + Tuner->Init_Ctrl[24].addr[0] = 43; + Tuner->Init_Ctrl[24].bit[0] = 0; + Tuner->Init_Ctrl[24].val[0] = 1; + + Tuner->Init_Ctrl[25].Ctrl_Num = RFSYN_R_DIV ; + Tuner->Init_Ctrl[25].size = 2 ; + Tuner->Init_Ctrl[25].addr[0] = 22; + Tuner->Init_Ctrl[25].bit[0] = 0; + Tuner->Init_Ctrl[25].val[0] = 1; + Tuner->Init_Ctrl[25].addr[1] = 22; + Tuner->Init_Ctrl[25].bit[1] = 1; + Tuner->Init_Ctrl[25].val[1] = 1; + + Tuner->Init_Ctrl[26].Ctrl_Num = SEQ_EXTSYNTHCALIF ; + Tuner->Init_Ctrl[26].size = 1 ; + Tuner->Init_Ctrl[26].addr[0] = 134; + Tuner->Init_Ctrl[26].bit[0] = 2; + Tuner->Init_Ctrl[26].val[0] = 0; + + Tuner->Init_Ctrl[27].Ctrl_Num = SEQ_EXTDCCAL ; + Tuner->Init_Ctrl[27].size = 1 ; + Tuner->Init_Ctrl[27].addr[0] = 137; + Tuner->Init_Ctrl[27].bit[0] = 3; + Tuner->Init_Ctrl[27].val[0] = 0; + + Tuner->Init_Ctrl[28].Ctrl_Num = AGC_EN_RSSI ; + Tuner->Init_Ctrl[28].size = 1 ; + Tuner->Init_Ctrl[28].addr[0] = 77; + Tuner->Init_Ctrl[28].bit[0] = 7; + Tuner->Init_Ctrl[28].val[0] = 0; + + Tuner->Init_Ctrl[29].Ctrl_Num = RFA_ENCLKRFAGC ; + Tuner->Init_Ctrl[29].size = 1 ; + Tuner->Init_Ctrl[29].addr[0] = 166; + Tuner->Init_Ctrl[29].bit[0] = 7; + Tuner->Init_Ctrl[29].val[0] = 1; + + Tuner->Init_Ctrl[30].Ctrl_Num = RFA_RSSI_REFH ; + Tuner->Init_Ctrl[30].size = 3 ; + Tuner->Init_Ctrl[30].addr[0] = 166; + Tuner->Init_Ctrl[30].bit[0] = 0; + Tuner->Init_Ctrl[30].val[0] = 0; + Tuner->Init_Ctrl[30].addr[1] = 166; + Tuner->Init_Ctrl[30].bit[1] = 1; + Tuner->Init_Ctrl[30].val[1] = 1; + Tuner->Init_Ctrl[30].addr[2] = 166; + Tuner->Init_Ctrl[30].bit[2] = 2; + Tuner->Init_Ctrl[30].val[2] = 1; + + Tuner->Init_Ctrl[31].Ctrl_Num = RFA_RSSI_REF ; + Tuner->Init_Ctrl[31].size = 3 ; + Tuner->Init_Ctrl[31].addr[0] = 166; + Tuner->Init_Ctrl[31].bit[0] = 3; + Tuner->Init_Ctrl[31].val[0] = 1; + Tuner->Init_Ctrl[31].addr[1] = 166; + Tuner->Init_Ctrl[31].bit[1] = 4; + Tuner->Init_Ctrl[31].val[1] = 0; + Tuner->Init_Ctrl[31].addr[2] = 166; + Tuner->Init_Ctrl[31].bit[2] = 5; + Tuner->Init_Ctrl[31].val[2] = 1; + + Tuner->Init_Ctrl[32].Ctrl_Num = RFA_RSSI_REFL ; + Tuner->Init_Ctrl[32].size = 3 ; + Tuner->Init_Ctrl[32].addr[0] = 167; + Tuner->Init_Ctrl[32].bit[0] = 0; + Tuner->Init_Ctrl[32].val[0] = 1; + Tuner->Init_Ctrl[32].addr[1] = 167; + Tuner->Init_Ctrl[32].bit[1] = 1; + Tuner->Init_Ctrl[32].val[1] = 1; + Tuner->Init_Ctrl[32].addr[2] = 167; + Tuner->Init_Ctrl[32].bit[2] = 2; + Tuner->Init_Ctrl[32].val[2] = 0; + + Tuner->Init_Ctrl[33].Ctrl_Num = RFA_FLR ; + Tuner->Init_Ctrl[33].size = 4 ; + Tuner->Init_Ctrl[33].addr[0] = 168; + Tuner->Init_Ctrl[33].bit[0] = 0; + Tuner->Init_Ctrl[33].val[0] = 0; + Tuner->Init_Ctrl[33].addr[1] = 168; + Tuner->Init_Ctrl[33].bit[1] = 1; + Tuner->Init_Ctrl[33].val[1] = 1; + Tuner->Init_Ctrl[33].addr[2] = 168; + Tuner->Init_Ctrl[33].bit[2] = 2; + Tuner->Init_Ctrl[33].val[2] = 0; + Tuner->Init_Ctrl[33].addr[3] = 168; + Tuner->Init_Ctrl[33].bit[3] = 3; + Tuner->Init_Ctrl[33].val[3] = 0; + + Tuner->Init_Ctrl[34].Ctrl_Num = RFA_CEIL ; + Tuner->Init_Ctrl[34].size = 4 ; + Tuner->Init_Ctrl[34].addr[0] = 168; + Tuner->Init_Ctrl[34].bit[0] = 4; + Tuner->Init_Ctrl[34].val[0] = 1; + Tuner->Init_Ctrl[34].addr[1] = 168; + Tuner->Init_Ctrl[34].bit[1] = 5; + Tuner->Init_Ctrl[34].val[1] = 1; + Tuner->Init_Ctrl[34].addr[2] = 168; + Tuner->Init_Ctrl[34].bit[2] = 6; + Tuner->Init_Ctrl[34].val[2] = 1; + Tuner->Init_Ctrl[34].addr[3] = 168; + Tuner->Init_Ctrl[34].bit[3] = 7; + Tuner->Init_Ctrl[34].val[3] = 1; + + Tuner->Init_Ctrl[35].Ctrl_Num = SEQ_EXTIQFSMPULSE ; + Tuner->Init_Ctrl[35].size = 1 ; + Tuner->Init_Ctrl[35].addr[0] = 135; + Tuner->Init_Ctrl[35].bit[0] = 0; + Tuner->Init_Ctrl[35].val[0] = 0; + + Tuner->Init_Ctrl[36].Ctrl_Num = OVERRIDE_1 ; + Tuner->Init_Ctrl[36].size = 1 ; + Tuner->Init_Ctrl[36].addr[0] = 56; + Tuner->Init_Ctrl[36].bit[0] = 3; + Tuner->Init_Ctrl[36].val[0] = 0; + + Tuner->Init_Ctrl[37].Ctrl_Num = BB_INITSTATE_DLPF_TUNE ; + Tuner->Init_Ctrl[37].size = 7 ; + Tuner->Init_Ctrl[37].addr[0] = 59; + Tuner->Init_Ctrl[37].bit[0] = 1; + Tuner->Init_Ctrl[37].val[0] = 0; + Tuner->Init_Ctrl[37].addr[1] = 59; + Tuner->Init_Ctrl[37].bit[1] = 2; + Tuner->Init_Ctrl[37].val[1] = 0; + Tuner->Init_Ctrl[37].addr[2] = 59; + Tuner->Init_Ctrl[37].bit[2] = 3; + Tuner->Init_Ctrl[37].val[2] = 0; + Tuner->Init_Ctrl[37].addr[3] = 59; + Tuner->Init_Ctrl[37].bit[3] = 4; + Tuner->Init_Ctrl[37].val[3] = 0; + Tuner->Init_Ctrl[37].addr[4] = 59; + Tuner->Init_Ctrl[37].bit[4] = 5; + Tuner->Init_Ctrl[37].val[4] = 0; + Tuner->Init_Ctrl[37].addr[5] = 59; + Tuner->Init_Ctrl[37].bit[5] = 6; + Tuner->Init_Ctrl[37].val[5] = 0; + Tuner->Init_Ctrl[37].addr[6] = 59; + Tuner->Init_Ctrl[37].bit[6] = 7; + Tuner->Init_Ctrl[37].val[6] = 0; + + Tuner->Init_Ctrl[38].Ctrl_Num = TG_R_DIV ; + Tuner->Init_Ctrl[38].size = 6 ; + Tuner->Init_Ctrl[38].addr[0] = 32; + Tuner->Init_Ctrl[38].bit[0] = 2; + Tuner->Init_Ctrl[38].val[0] = 0; + Tuner->Init_Ctrl[38].addr[1] = 32; + Tuner->Init_Ctrl[38].bit[1] = 3; + Tuner->Init_Ctrl[38].val[1] = 0; + Tuner->Init_Ctrl[38].addr[2] = 32; + Tuner->Init_Ctrl[38].bit[2] = 4; + Tuner->Init_Ctrl[38].val[2] = 0; + Tuner->Init_Ctrl[38].addr[3] = 32; + Tuner->Init_Ctrl[38].bit[3] = 5; + Tuner->Init_Ctrl[38].val[3] = 0; + Tuner->Init_Ctrl[38].addr[4] = 32; + Tuner->Init_Ctrl[38].bit[4] = 6; + Tuner->Init_Ctrl[38].val[4] = 1; + Tuner->Init_Ctrl[38].addr[5] = 32; + Tuner->Init_Ctrl[38].bit[5] = 7; + Tuner->Init_Ctrl[38].val[5] = 0; + + Tuner->Init_Ctrl[39].Ctrl_Num = EN_CHP_LIN_B ; + Tuner->Init_Ctrl[39].size = 1 ; + Tuner->Init_Ctrl[39].addr[0] = 25; + Tuner->Init_Ctrl[39].bit[0] = 3; + Tuner->Init_Ctrl[39].val[0] = 1; + + + Tuner->CH_Ctrl_Num = CHCTRL_NUM ; + + Tuner->CH_Ctrl[0].Ctrl_Num = DN_POLY ; + Tuner->CH_Ctrl[0].size = 2 ; + Tuner->CH_Ctrl[0].addr[0] = 68; + Tuner->CH_Ctrl[0].bit[0] = 6; + Tuner->CH_Ctrl[0].val[0] = 1; + Tuner->CH_Ctrl[0].addr[1] = 68; + Tuner->CH_Ctrl[0].bit[1] = 7; + Tuner->CH_Ctrl[0].val[1] = 1; + + Tuner->CH_Ctrl[1].Ctrl_Num = DN_RFGAIN ; + Tuner->CH_Ctrl[1].size = 2 ; + Tuner->CH_Ctrl[1].addr[0] = 70; + Tuner->CH_Ctrl[1].bit[0] = 6; + Tuner->CH_Ctrl[1].val[0] = 1; + Tuner->CH_Ctrl[1].addr[1] = 70; + Tuner->CH_Ctrl[1].bit[1] = 7; + Tuner->CH_Ctrl[1].val[1] = 0; + + Tuner->CH_Ctrl[2].Ctrl_Num = DN_CAP_RFLPF ; + Tuner->CH_Ctrl[2].size = 9 ; + Tuner->CH_Ctrl[2].addr[0] = 69; + Tuner->CH_Ctrl[2].bit[0] = 5; + Tuner->CH_Ctrl[2].val[0] = 0; + Tuner->CH_Ctrl[2].addr[1] = 69; + Tuner->CH_Ctrl[2].bit[1] = 6; + Tuner->CH_Ctrl[2].val[1] = 0; + Tuner->CH_Ctrl[2].addr[2] = 69; + Tuner->CH_Ctrl[2].bit[2] = 7; + Tuner->CH_Ctrl[2].val[2] = 0; + Tuner->CH_Ctrl[2].addr[3] = 68; + Tuner->CH_Ctrl[2].bit[3] = 0; + Tuner->CH_Ctrl[2].val[3] = 0; + Tuner->CH_Ctrl[2].addr[4] = 68; + Tuner->CH_Ctrl[2].bit[4] = 1; + Tuner->CH_Ctrl[2].val[4] = 0; + Tuner->CH_Ctrl[2].addr[5] = 68; + Tuner->CH_Ctrl[2].bit[5] = 2; + Tuner->CH_Ctrl[2].val[5] = 0; + Tuner->CH_Ctrl[2].addr[6] = 68; + Tuner->CH_Ctrl[2].bit[6] = 3; + Tuner->CH_Ctrl[2].val[6] = 0; + Tuner->CH_Ctrl[2].addr[7] = 68; + Tuner->CH_Ctrl[2].bit[7] = 4; + Tuner->CH_Ctrl[2].val[7] = 0; + Tuner->CH_Ctrl[2].addr[8] = 68; + Tuner->CH_Ctrl[2].bit[8] = 5; + Tuner->CH_Ctrl[2].val[8] = 0; + + Tuner->CH_Ctrl[3].Ctrl_Num = DN_EN_VHFUHFBAR ; + Tuner->CH_Ctrl[3].size = 1 ; + Tuner->CH_Ctrl[3].addr[0] = 70; + Tuner->CH_Ctrl[3].bit[0] = 5; + Tuner->CH_Ctrl[3].val[0] = 0; + + Tuner->CH_Ctrl[4].Ctrl_Num = DN_GAIN_ADJUST ; + Tuner->CH_Ctrl[4].size = 3 ; + Tuner->CH_Ctrl[4].addr[0] = 73; + Tuner->CH_Ctrl[4].bit[0] = 4; + Tuner->CH_Ctrl[4].val[0] = 0; + Tuner->CH_Ctrl[4].addr[1] = 73; + Tuner->CH_Ctrl[4].bit[1] = 5; + Tuner->CH_Ctrl[4].val[1] = 1; + Tuner->CH_Ctrl[4].addr[2] = 73; + Tuner->CH_Ctrl[4].bit[2] = 6; + Tuner->CH_Ctrl[4].val[2] = 0; + + Tuner->CH_Ctrl[5].Ctrl_Num = DN_IQTNBUF_AMP ; + Tuner->CH_Ctrl[5].size = 4 ; + Tuner->CH_Ctrl[5].addr[0] = 70; + Tuner->CH_Ctrl[5].bit[0] = 0; + Tuner->CH_Ctrl[5].val[0] = 0; + Tuner->CH_Ctrl[5].addr[1] = 70; + Tuner->CH_Ctrl[5].bit[1] = 1; + Tuner->CH_Ctrl[5].val[1] = 0; + Tuner->CH_Ctrl[5].addr[2] = 70; + Tuner->CH_Ctrl[5].bit[2] = 2; + Tuner->CH_Ctrl[5].val[2] = 0; + Tuner->CH_Ctrl[5].addr[3] = 70; + Tuner->CH_Ctrl[5].bit[3] = 3; + Tuner->CH_Ctrl[5].val[3] = 0; + + Tuner->CH_Ctrl[6].Ctrl_Num = DN_IQTNGNBFBIAS_BST ; + Tuner->CH_Ctrl[6].size = 1 ; + Tuner->CH_Ctrl[6].addr[0] = 70; + Tuner->CH_Ctrl[6].bit[0] = 4; + Tuner->CH_Ctrl[6].val[0] = 1; + + Tuner->CH_Ctrl[7].Ctrl_Num = RFSYN_EN_OUTMUX ; + Tuner->CH_Ctrl[7].size = 1 ; + Tuner->CH_Ctrl[7].addr[0] = 111; + Tuner->CH_Ctrl[7].bit[0] = 4; + Tuner->CH_Ctrl[7].val[0] = 0; + + Tuner->CH_Ctrl[8].Ctrl_Num = RFSYN_SEL_VCO_OUT ; + Tuner->CH_Ctrl[8].size = 1 ; + Tuner->CH_Ctrl[8].addr[0] = 111; + Tuner->CH_Ctrl[8].bit[0] = 7; + Tuner->CH_Ctrl[8].val[0] = 1; + + Tuner->CH_Ctrl[9].Ctrl_Num = RFSYN_SEL_VCO_HI ; + Tuner->CH_Ctrl[9].size = 1 ; + Tuner->CH_Ctrl[9].addr[0] = 111; + Tuner->CH_Ctrl[9].bit[0] = 6; + Tuner->CH_Ctrl[9].val[0] = 1; + + Tuner->CH_Ctrl[10].Ctrl_Num = RFSYN_SEL_DIVM ; + Tuner->CH_Ctrl[10].size = 1 ; + Tuner->CH_Ctrl[10].addr[0] = 111; + Tuner->CH_Ctrl[10].bit[0] = 5; + Tuner->CH_Ctrl[10].val[0] = 0; + + Tuner->CH_Ctrl[11].Ctrl_Num = RFSYN_RF_DIV_BIAS ; + Tuner->CH_Ctrl[11].size = 2 ; + Tuner->CH_Ctrl[11].addr[0] = 110; + Tuner->CH_Ctrl[11].bit[0] = 0; + Tuner->CH_Ctrl[11].val[0] = 1; + Tuner->CH_Ctrl[11].addr[1] = 110; + Tuner->CH_Ctrl[11].bit[1] = 1; + Tuner->CH_Ctrl[11].val[1] = 0; + + Tuner->CH_Ctrl[12].Ctrl_Num = DN_SEL_FREQ ; + Tuner->CH_Ctrl[12].size = 3 ; + Tuner->CH_Ctrl[12].addr[0] = 69; + Tuner->CH_Ctrl[12].bit[0] = 2; + Tuner->CH_Ctrl[12].val[0] = 0; + Tuner->CH_Ctrl[12].addr[1] = 69; + Tuner->CH_Ctrl[12].bit[1] = 3; + Tuner->CH_Ctrl[12].val[1] = 0; + Tuner->CH_Ctrl[12].addr[2] = 69; + Tuner->CH_Ctrl[12].bit[2] = 4; + Tuner->CH_Ctrl[12].val[2] = 0; + + Tuner->CH_Ctrl[13].Ctrl_Num = RFSYN_VCO_BIAS ; + Tuner->CH_Ctrl[13].size = 6 ; + Tuner->CH_Ctrl[13].addr[0] = 110; + Tuner->CH_Ctrl[13].bit[0] = 2; + Tuner->CH_Ctrl[13].val[0] = 0; + Tuner->CH_Ctrl[13].addr[1] = 110; + Tuner->CH_Ctrl[13].bit[1] = 3; + Tuner->CH_Ctrl[13].val[1] = 0; + Tuner->CH_Ctrl[13].addr[2] = 110; + Tuner->CH_Ctrl[13].bit[2] = 4; + Tuner->CH_Ctrl[13].val[2] = 0; + Tuner->CH_Ctrl[13].addr[3] = 110; + Tuner->CH_Ctrl[13].bit[3] = 5; + Tuner->CH_Ctrl[13].val[3] = 0; + Tuner->CH_Ctrl[13].addr[4] = 110; + Tuner->CH_Ctrl[13].bit[4] = 6; + Tuner->CH_Ctrl[13].val[4] = 0; + Tuner->CH_Ctrl[13].addr[5] = 110; + Tuner->CH_Ctrl[13].bit[5] = 7; + Tuner->CH_Ctrl[13].val[5] = 1; + + Tuner->CH_Ctrl[14].Ctrl_Num = CHCAL_INT_MOD_RF ; + Tuner->CH_Ctrl[14].size = 7 ; + Tuner->CH_Ctrl[14].addr[0] = 14; + Tuner->CH_Ctrl[14].bit[0] = 0; + Tuner->CH_Ctrl[14].val[0] = 0; + Tuner->CH_Ctrl[14].addr[1] = 14; + Tuner->CH_Ctrl[14].bit[1] = 1; + Tuner->CH_Ctrl[14].val[1] = 0; + Tuner->CH_Ctrl[14].addr[2] = 14; + Tuner->CH_Ctrl[14].bit[2] = 2; + Tuner->CH_Ctrl[14].val[2] = 0; + Tuner->CH_Ctrl[14].addr[3] = 14; + Tuner->CH_Ctrl[14].bit[3] = 3; + Tuner->CH_Ctrl[14].val[3] = 0; + Tuner->CH_Ctrl[14].addr[4] = 14; + Tuner->CH_Ctrl[14].bit[4] = 4; + Tuner->CH_Ctrl[14].val[4] = 0; + Tuner->CH_Ctrl[14].addr[5] = 14; + Tuner->CH_Ctrl[14].bit[5] = 5; + Tuner->CH_Ctrl[14].val[5] = 0; + Tuner->CH_Ctrl[14].addr[6] = 14; + Tuner->CH_Ctrl[14].bit[6] = 6; + Tuner->CH_Ctrl[14].val[6] = 0; + + Tuner->CH_Ctrl[15].Ctrl_Num = CHCAL_FRAC_MOD_RF ; + Tuner->CH_Ctrl[15].size = 18 ; + Tuner->CH_Ctrl[15].addr[0] = 17; + Tuner->CH_Ctrl[15].bit[0] = 6; + Tuner->CH_Ctrl[15].val[0] = 0; + Tuner->CH_Ctrl[15].addr[1] = 17; + Tuner->CH_Ctrl[15].bit[1] = 7; + Tuner->CH_Ctrl[15].val[1] = 0; + Tuner->CH_Ctrl[15].addr[2] = 16; + Tuner->CH_Ctrl[15].bit[2] = 0; + Tuner->CH_Ctrl[15].val[2] = 0; + Tuner->CH_Ctrl[15].addr[3] = 16; + Tuner->CH_Ctrl[15].bit[3] = 1; + Tuner->CH_Ctrl[15].val[3] = 0; + Tuner->CH_Ctrl[15].addr[4] = 16; + Tuner->CH_Ctrl[15].bit[4] = 2; + Tuner->CH_Ctrl[15].val[4] = 0; + Tuner->CH_Ctrl[15].addr[5] = 16; + Tuner->CH_Ctrl[15].bit[5] = 3; + Tuner->CH_Ctrl[15].val[5] = 0; + Tuner->CH_Ctrl[15].addr[6] = 16; + Tuner->CH_Ctrl[15].bit[6] = 4; + Tuner->CH_Ctrl[15].val[6] = 0; + Tuner->CH_Ctrl[15].addr[7] = 16; + Tuner->CH_Ctrl[15].bit[7] = 5; + Tuner->CH_Ctrl[15].val[7] = 0; + Tuner->CH_Ctrl[15].addr[8] = 16; + Tuner->CH_Ctrl[15].bit[8] = 6; + Tuner->CH_Ctrl[15].val[8] = 0; + Tuner->CH_Ctrl[15].addr[9] = 16; + Tuner->CH_Ctrl[15].bit[9] = 7; + Tuner->CH_Ctrl[15].val[9] = 0; + Tuner->CH_Ctrl[15].addr[10] = 15; + Tuner->CH_Ctrl[15].bit[10] = 0; + Tuner->CH_Ctrl[15].val[10] = 0; + Tuner->CH_Ctrl[15].addr[11] = 15; + Tuner->CH_Ctrl[15].bit[11] = 1; + Tuner->CH_Ctrl[15].val[11] = 0; + Tuner->CH_Ctrl[15].addr[12] = 15; + Tuner->CH_Ctrl[15].bit[12] = 2; + Tuner->CH_Ctrl[15].val[12] = 0; + Tuner->CH_Ctrl[15].addr[13] = 15; + Tuner->CH_Ctrl[15].bit[13] = 3; + Tuner->CH_Ctrl[15].val[13] = 0; + Tuner->CH_Ctrl[15].addr[14] = 15; + Tuner->CH_Ctrl[15].bit[14] = 4; + Tuner->CH_Ctrl[15].val[14] = 0; + Tuner->CH_Ctrl[15].addr[15] = 15; + Tuner->CH_Ctrl[15].bit[15] = 5; + Tuner->CH_Ctrl[15].val[15] = 0; + Tuner->CH_Ctrl[15].addr[16] = 15; + Tuner->CH_Ctrl[15].bit[16] = 6; + Tuner->CH_Ctrl[15].val[16] = 1; + Tuner->CH_Ctrl[15].addr[17] = 15; + Tuner->CH_Ctrl[15].bit[17] = 7; + Tuner->CH_Ctrl[15].val[17] = 1; + + Tuner->CH_Ctrl[16].Ctrl_Num = RFSYN_LPF_R ; + Tuner->CH_Ctrl[16].size = 5 ; + Tuner->CH_Ctrl[16].addr[0] = 112; + Tuner->CH_Ctrl[16].bit[0] = 0; + Tuner->CH_Ctrl[16].val[0] = 0; + Tuner->CH_Ctrl[16].addr[1] = 112; + Tuner->CH_Ctrl[16].bit[1] = 1; + Tuner->CH_Ctrl[16].val[1] = 0; + Tuner->CH_Ctrl[16].addr[2] = 112; + Tuner->CH_Ctrl[16].bit[2] = 2; + Tuner->CH_Ctrl[16].val[2] = 0; + Tuner->CH_Ctrl[16].addr[3] = 112; + Tuner->CH_Ctrl[16].bit[3] = 3; + Tuner->CH_Ctrl[16].val[3] = 0; + Tuner->CH_Ctrl[16].addr[4] = 112; + Tuner->CH_Ctrl[16].bit[4] = 4; + Tuner->CH_Ctrl[16].val[4] = 1; + + Tuner->CH_Ctrl[17].Ctrl_Num = CHCAL_EN_INT_RF ; + Tuner->CH_Ctrl[17].size = 1 ; + Tuner->CH_Ctrl[17].addr[0] = 14; + Tuner->CH_Ctrl[17].bit[0] = 7; + Tuner->CH_Ctrl[17].val[0] = 0; + + Tuner->CH_Ctrl[18].Ctrl_Num = TG_LO_DIVVAL ; + Tuner->CH_Ctrl[18].size = 4 ; + Tuner->CH_Ctrl[18].addr[0] = 107; + Tuner->CH_Ctrl[18].bit[0] = 3; + Tuner->CH_Ctrl[18].val[0] = 0; + Tuner->CH_Ctrl[18].addr[1] = 107; + Tuner->CH_Ctrl[18].bit[1] = 4; + Tuner->CH_Ctrl[18].val[1] = 0; + Tuner->CH_Ctrl[18].addr[2] = 107; + Tuner->CH_Ctrl[18].bit[2] = 5; + Tuner->CH_Ctrl[18].val[2] = 0; + Tuner->CH_Ctrl[18].addr[3] = 107; + Tuner->CH_Ctrl[18].bit[3] = 6; + Tuner->CH_Ctrl[18].val[3] = 0; + + Tuner->CH_Ctrl[19].Ctrl_Num = TG_LO_SELVAL ; + Tuner->CH_Ctrl[19].size = 3 ; + Tuner->CH_Ctrl[19].addr[0] = 107; + Tuner->CH_Ctrl[19].bit[0] = 7; + Tuner->CH_Ctrl[19].val[0] = 1; + Tuner->CH_Ctrl[19].addr[1] = 106; + Tuner->CH_Ctrl[19].bit[1] = 0; + Tuner->CH_Ctrl[19].val[1] = 1; + Tuner->CH_Ctrl[19].addr[2] = 106; + Tuner->CH_Ctrl[19].bit[2] = 1; + Tuner->CH_Ctrl[19].val[2] = 1; + + Tuner->CH_Ctrl[20].Ctrl_Num = TG_DIV_VAL ; + Tuner->CH_Ctrl[20].size = 11 ; + Tuner->CH_Ctrl[20].addr[0] = 109; + Tuner->CH_Ctrl[20].bit[0] = 2; + Tuner->CH_Ctrl[20].val[0] = 0; + Tuner->CH_Ctrl[20].addr[1] = 109; + Tuner->CH_Ctrl[20].bit[1] = 3; + Tuner->CH_Ctrl[20].val[1] = 0; + Tuner->CH_Ctrl[20].addr[2] = 109; + Tuner->CH_Ctrl[20].bit[2] = 4; + Tuner->CH_Ctrl[20].val[2] = 0; + Tuner->CH_Ctrl[20].addr[3] = 109; + Tuner->CH_Ctrl[20].bit[3] = 5; + Tuner->CH_Ctrl[20].val[3] = 0; + Tuner->CH_Ctrl[20].addr[4] = 109; + Tuner->CH_Ctrl[20].bit[4] = 6; + Tuner->CH_Ctrl[20].val[4] = 0; + Tuner->CH_Ctrl[20].addr[5] = 109; + Tuner->CH_Ctrl[20].bit[5] = 7; + Tuner->CH_Ctrl[20].val[5] = 0; + Tuner->CH_Ctrl[20].addr[6] = 108; + Tuner->CH_Ctrl[20].bit[6] = 0; + Tuner->CH_Ctrl[20].val[6] = 0; + Tuner->CH_Ctrl[20].addr[7] = 108; + Tuner->CH_Ctrl[20].bit[7] = 1; + Tuner->CH_Ctrl[20].val[7] = 0; + Tuner->CH_Ctrl[20].addr[8] = 108; + Tuner->CH_Ctrl[20].bit[8] = 2; + Tuner->CH_Ctrl[20].val[8] = 1; + Tuner->CH_Ctrl[20].addr[9] = 108; + Tuner->CH_Ctrl[20].bit[9] = 3; + Tuner->CH_Ctrl[20].val[9] = 1; + Tuner->CH_Ctrl[20].addr[10] = 108; + Tuner->CH_Ctrl[20].bit[10] = 4; + Tuner->CH_Ctrl[20].val[10] = 1; + + Tuner->CH_Ctrl[21].Ctrl_Num = TG_VCO_BIAS ; + Tuner->CH_Ctrl[21].size = 6 ; + Tuner->CH_Ctrl[21].addr[0] = 106; + Tuner->CH_Ctrl[21].bit[0] = 2; + Tuner->CH_Ctrl[21].val[0] = 0; + Tuner->CH_Ctrl[21].addr[1] = 106; + Tuner->CH_Ctrl[21].bit[1] = 3; + Tuner->CH_Ctrl[21].val[1] = 0; + Tuner->CH_Ctrl[21].addr[2] = 106; + Tuner->CH_Ctrl[21].bit[2] = 4; + Tuner->CH_Ctrl[21].val[2] = 0; + Tuner->CH_Ctrl[21].addr[3] = 106; + Tuner->CH_Ctrl[21].bit[3] = 5; + Tuner->CH_Ctrl[21].val[3] = 0; + Tuner->CH_Ctrl[21].addr[4] = 106; + Tuner->CH_Ctrl[21].bit[4] = 6; + Tuner->CH_Ctrl[21].val[4] = 0; + Tuner->CH_Ctrl[21].addr[5] = 106; + Tuner->CH_Ctrl[21].bit[5] = 7; + Tuner->CH_Ctrl[21].val[5] = 1; + + Tuner->CH_Ctrl[22].Ctrl_Num = SEQ_EXTPOWERUP ; + Tuner->CH_Ctrl[22].size = 1 ; + Tuner->CH_Ctrl[22].addr[0] = 138; + Tuner->CH_Ctrl[22].bit[0] = 4; + Tuner->CH_Ctrl[22].val[0] = 1; + + Tuner->CH_Ctrl[23].Ctrl_Num = OVERRIDE_2 ; + Tuner->CH_Ctrl[23].size = 1 ; + Tuner->CH_Ctrl[23].addr[0] = 17; + Tuner->CH_Ctrl[23].bit[0] = 5; + Tuner->CH_Ctrl[23].val[0] = 0; + + Tuner->CH_Ctrl[24].Ctrl_Num = OVERRIDE_3 ; + Tuner->CH_Ctrl[24].size = 1 ; + Tuner->CH_Ctrl[24].addr[0] = 111; + Tuner->CH_Ctrl[24].bit[0] = 3; + Tuner->CH_Ctrl[24].val[0] = 0; + + Tuner->CH_Ctrl[25].Ctrl_Num = OVERRIDE_4 ; + Tuner->CH_Ctrl[25].size = 1 ; + Tuner->CH_Ctrl[25].addr[0] = 112; + Tuner->CH_Ctrl[25].bit[0] = 7; + Tuner->CH_Ctrl[25].val[0] = 0; + + Tuner->CH_Ctrl[26].Ctrl_Num = SEQ_FSM_PULSE ; + Tuner->CH_Ctrl[26].size = 1 ; + Tuner->CH_Ctrl[26].addr[0] = 136; + Tuner->CH_Ctrl[26].bit[0] = 7; + Tuner->CH_Ctrl[26].val[0] = 0; + + Tuner->CH_Ctrl[27].Ctrl_Num = GPIO_4B ; + Tuner->CH_Ctrl[27].size = 1 ; + Tuner->CH_Ctrl[27].addr[0] = 149; + Tuner->CH_Ctrl[27].bit[0] = 7; + Tuner->CH_Ctrl[27].val[0] = 0; + + Tuner->CH_Ctrl[28].Ctrl_Num = GPIO_3B ; + Tuner->CH_Ctrl[28].size = 1 ; + Tuner->CH_Ctrl[28].addr[0] = 149; + Tuner->CH_Ctrl[28].bit[0] = 6; + Tuner->CH_Ctrl[28].val[0] = 0; + + Tuner->CH_Ctrl[29].Ctrl_Num = GPIO_4 ; + Tuner->CH_Ctrl[29].size = 1 ; + Tuner->CH_Ctrl[29].addr[0] = 149; + Tuner->CH_Ctrl[29].bit[0] = 5; + Tuner->CH_Ctrl[29].val[0] = 1; + + Tuner->CH_Ctrl[30].Ctrl_Num = GPIO_3 ; + Tuner->CH_Ctrl[30].size = 1 ; + Tuner->CH_Ctrl[30].addr[0] = 149; + Tuner->CH_Ctrl[30].bit[0] = 4; + Tuner->CH_Ctrl[30].val[0] = 1; + + Tuner->CH_Ctrl[31].Ctrl_Num = GPIO_1B ; + Tuner->CH_Ctrl[31].size = 1 ; + Tuner->CH_Ctrl[31].addr[0] = 149; + Tuner->CH_Ctrl[31].bit[0] = 3; + Tuner->CH_Ctrl[31].val[0] = 0; + + Tuner->CH_Ctrl[32].Ctrl_Num = DAC_A_ENABLE ; + Tuner->CH_Ctrl[32].size = 1 ; + Tuner->CH_Ctrl[32].addr[0] = 93; + Tuner->CH_Ctrl[32].bit[0] = 1; + Tuner->CH_Ctrl[32].val[0] = 0; + + Tuner->CH_Ctrl[33].Ctrl_Num = DAC_B_ENABLE ; + Tuner->CH_Ctrl[33].size = 1 ; + Tuner->CH_Ctrl[33].addr[0] = 93; + Tuner->CH_Ctrl[33].bit[0] = 0; + Tuner->CH_Ctrl[33].val[0] = 0; + + Tuner->CH_Ctrl[34].Ctrl_Num = DAC_DIN_A ; + Tuner->CH_Ctrl[34].size = 6 ; + Tuner->CH_Ctrl[34].addr[0] = 92; + Tuner->CH_Ctrl[34].bit[0] = 2; + Tuner->CH_Ctrl[34].val[0] = 0; + Tuner->CH_Ctrl[34].addr[1] = 92; + Tuner->CH_Ctrl[34].bit[1] = 3; + Tuner->CH_Ctrl[34].val[1] = 0; + Tuner->CH_Ctrl[34].addr[2] = 92; + Tuner->CH_Ctrl[34].bit[2] = 4; + Tuner->CH_Ctrl[34].val[2] = 0; + Tuner->CH_Ctrl[34].addr[3] = 92; + Tuner->CH_Ctrl[34].bit[3] = 5; + Tuner->CH_Ctrl[34].val[3] = 0; + Tuner->CH_Ctrl[34].addr[4] = 92; + Tuner->CH_Ctrl[34].bit[4] = 6; + Tuner->CH_Ctrl[34].val[4] = 0; + Tuner->CH_Ctrl[34].addr[5] = 92; + Tuner->CH_Ctrl[34].bit[5] = 7; + Tuner->CH_Ctrl[34].val[5] = 0; + + Tuner->CH_Ctrl[35].Ctrl_Num = DAC_DIN_B ; + Tuner->CH_Ctrl[35].size = 6 ; + Tuner->CH_Ctrl[35].addr[0] = 93; + Tuner->CH_Ctrl[35].bit[0] = 2; + Tuner->CH_Ctrl[35].val[0] = 0; + Tuner->CH_Ctrl[35].addr[1] = 93; + Tuner->CH_Ctrl[35].bit[1] = 3; + Tuner->CH_Ctrl[35].val[1] = 0; + Tuner->CH_Ctrl[35].addr[2] = 93; + Tuner->CH_Ctrl[35].bit[2] = 4; + Tuner->CH_Ctrl[35].val[2] = 0; + Tuner->CH_Ctrl[35].addr[3] = 93; + Tuner->CH_Ctrl[35].bit[3] = 5; + Tuner->CH_Ctrl[35].val[3] = 0; + Tuner->CH_Ctrl[35].addr[4] = 93; + Tuner->CH_Ctrl[35].bit[4] = 6; + Tuner->CH_Ctrl[35].val[4] = 0; + Tuner->CH_Ctrl[35].addr[5] = 93; + Tuner->CH_Ctrl[35].bit[5] = 7; + Tuner->CH_Ctrl[35].val[5] = 0; + +#ifdef _MXL_PRODUCTION + Tuner->CH_Ctrl[36].Ctrl_Num = RFSYN_EN_DIV ; + Tuner->CH_Ctrl[36].size = 1 ; + Tuner->CH_Ctrl[36].addr[0] = 109; + Tuner->CH_Ctrl[36].bit[0] = 1; + Tuner->CH_Ctrl[36].val[0] = 1; + + Tuner->CH_Ctrl[37].Ctrl_Num = RFSYN_DIVM ; + Tuner->CH_Ctrl[37].size = 2 ; + Tuner->CH_Ctrl[37].addr[0] = 112; + Tuner->CH_Ctrl[37].bit[0] = 5; + Tuner->CH_Ctrl[37].val[0] = 0; + Tuner->CH_Ctrl[37].addr[1] = 112; + Tuner->CH_Ctrl[37].bit[1] = 6; + Tuner->CH_Ctrl[37].val[1] = 0; + + Tuner->CH_Ctrl[38].Ctrl_Num = DN_BYPASS_AGC_I2C ; + Tuner->CH_Ctrl[38].size = 1 ; + Tuner->CH_Ctrl[38].addr[0] = 65; + Tuner->CH_Ctrl[38].bit[0] = 1; + Tuner->CH_Ctrl[38].val[0] = 0; +#endif + + return 0 ; +} + + + + + + + + + + + + + + + +// MaxLinear source code - MXL5005_c.cpp + + + +// MXL5005.cpp : Defines the initialization routines for the DLL. +// 2.6.12 + + +//#ifdef _MXL_HEADER +//#include "stdafx.h" +//#endif +//#include "MXL5005_c.h" + + +void InitTunerControls(Tuner_struct *Tuner) +{ + MXL5005_RegisterInit(Tuner) ; + MXL5005_ControlInit(Tuner) ; +#ifdef _MXL_INTERNAL + MXL5005_MXLControlInit(Tuner) ; +#endif +} + + + +/////////////////////////////////////////////////////////////////////////////// +// // +// Function: MXL_ConfigTuner // +// // +// Description: Configure MXL5005Tuner structure for desired // +// Channel Bandwidth/Channel Frequency // +// // +// // +// Functions used: // +// MXL_SynthIFLO_Calc // +// // +// Inputs: // +// Tuner_struct: structure defined at higher level // +// Mode: Tuner Mode (Analog/Digital) // +// IF_Mode: IF Mode ( Zero/Low ) // +// Bandwidth: Filter Channel Bandwidth (in Hz) // +// IF_out: Desired IF out Frequency (in Hz) // +// Fxtal: Crystal Frerquency (in Hz) // +// TOP: 0: Dual AGC; Value: take over point // +// IF_OUT_LOAD: IF out load resistor (200/300 Ohms) // +// CLOCK_OUT: 0: Turn off clock out; 1: turn on clock out // +// DIV_OUT: 0: Div-1; 1: Div-4 // +// CAPSELECT: 0: Disable On-chip pulling cap; 1: Enable // +// EN_RSSI: 0: Disable RSSI; 1: Enable RSSI // +// // +// Outputs: // +// Tuner // +// // +// Return: // +// 0 : Successful // +// > 0 : Failed // +// // +/////////////////////////////////////////////////////////////////////////////// +_u16 MXL5005_TunerConfig(Tuner_struct *Tuner, + _u8 Mode, // 0: Analog Mode ; 1: Digital Mode + _u8 IF_mode, // for Analog Mode, 0: zero IF; 1: low IF + _u32 Bandwidth, // filter channel bandwidth (6, 7, 8) + _u32 IF_out, // Desired IF Out Frequency + _u32 Fxtal, // XTAL Frequency + _u8 AGC_Mode, // AGC Mode - Dual AGC: 0, Single AGC: 1 + _u16 TOP, // 0: Dual AGC; Value: take over point + _u16 IF_OUT_LOAD, // IF Out Load Resistor (200 / 300 Ohms) + _u8 CLOCK_OUT, // 0: turn off clock out; 1: turn on clock out + _u8 DIV_OUT, // 0: Div-1; 1: Div-4 + _u8 CAPSELECT, // 0: disable On-Chip pulling cap; 1: enable + _u8 EN_RSSI, // 0: disable RSSI; 1: enable RSSI + _u8 Mod_Type, // Modulation Type; + // 0 - Default; 1 - DVB-T; 2 - ATSC; 3 - QAM; 4 - Analog Cable + _u8 TF_Type // Tracking Filter + // 0 - Default; 1 - Off; 2 - Type C; 3 - Type C-H + ) +{ + _u16 status = 0 ; + + Tuner->Mode = Mode ; + Tuner->IF_Mode = IF_mode ; + Tuner->Chan_Bandwidth = Bandwidth ; + Tuner->IF_OUT = IF_out ; + Tuner->Fxtal = Fxtal ; + Tuner->AGC_Mode = AGC_Mode ; + Tuner->TOP = TOP ; + Tuner->IF_OUT_LOAD = IF_OUT_LOAD ; + Tuner->CLOCK_OUT = CLOCK_OUT ; + Tuner->DIV_OUT = DIV_OUT ; + Tuner->CAPSELECT = CAPSELECT ; + Tuner->EN_RSSI = EN_RSSI ; + Tuner->Mod_Type = Mod_Type ; + Tuner->TF_Type = TF_Type ; + + + + // + // Initialize all the controls and registers + // + InitTunerControls (Tuner) ; + // + // Synthesizer LO frequency calculation + // + MXL_SynthIFLO_Calc( Tuner ) ; + + return status ; +} + +/////////////////////////////////////////////////////////////////////////////// +// // +// Function: MXL_SynthIFLO_Calc // +// // +// Description: Calculate Internal IF-LO Frequency // +// // +// Globals: // +// NONE // +// // +// Functions used: // +// NONE // +// // +// Inputs: // +// Tuner_struct: structure defined at higher level // +// // +// Outputs: // +// Tuner // +// // +// Return: // +// 0 : Successful // +// > 0 : Failed // +// // +/////////////////////////////////////////////////////////////////////////////// +void MXL_SynthIFLO_Calc(Tuner_struct *Tuner) +{ + if (Tuner->Mode == 1) // Digital Mode + { + Tuner->IF_LO = Tuner->IF_OUT ; + } + else // Analog Mode + { + if(Tuner->IF_Mode == 0) // Analog Zero IF mode + { + Tuner->IF_LO = Tuner->IF_OUT + 400000 ; + } + else // Analog Low IF mode + { + Tuner->IF_LO = Tuner->IF_OUT + Tuner->Chan_Bandwidth/2 ; + } + } +} + +/////////////////////////////////////////////////////////////////////////////// +// // +// Function: MXL_SynthRFTGLO_Calc // +// // +// Description: Calculate Internal RF-LO frequency and // +// internal Tone-Gen(TG)-LO frequency // +// // +// Globals: // +// NONE // +// // +// Functions used: // +// NONE // +// // +// Inputs: // +// Tuner_struct: structure defined at higher level // +// // +// Outputs: // +// Tuner // +// // +// Return: // +// 0 : Successful // +// > 0 : Failed // +// // +/////////////////////////////////////////////////////////////////////////////// +void MXL_SynthRFTGLO_Calc(Tuner_struct *Tuner) +{ + if (Tuner->Mode == 1) // Digital Mode + { + //remove 20.48MHz setting for 2.6.10 + Tuner->RF_LO = Tuner->RF_IN ; + Tuner->TG_LO = Tuner->RF_IN - 750000 ; //change for 2.6.6 + } + else // Analog Mode + { + if(Tuner->IF_Mode == 0) // Analog Zero IF mode + { + Tuner->RF_LO = Tuner->RF_IN - 400000 ; + Tuner->TG_LO = Tuner->RF_IN - 1750000 ; + } + else // Analog Low IF mode + { + Tuner->RF_LO = Tuner->RF_IN - Tuner->Chan_Bandwidth/2 ; + Tuner->TG_LO = Tuner->RF_IN - Tuner->Chan_Bandwidth + 500000 ; + } + } +} + +/////////////////////////////////////////////////////////////////////////////// +// // +// Function: MXL_OverwriteICDefault // +// // +// Description: Overwrite the Default Register Setting // +// // +// // +// Functions used: // +// // +// Inputs: // +// Tuner_struct: structure defined at higher level // +// Outputs: // +// Tuner // +// // +// Return: // +// 0 : Successful // +// > 0 : Failed // +// // +/////////////////////////////////////////////////////////////////////////////// +_u16 MXL_OverwriteICDefault( Tuner_struct *Tuner) +{ + _u16 status = 0 ; + + status += MXL_ControlWrite(Tuner, OVERRIDE_1, 1) ; + status += MXL_ControlWrite(Tuner, OVERRIDE_2, 1) ; + status += MXL_ControlWrite(Tuner, OVERRIDE_3, 1) ; + status += MXL_ControlWrite(Tuner, OVERRIDE_4, 1) ; + + return status ; +} + +/////////////////////////////////////////////////////////////////////////////// +// // +// Function: MXL_BlockInit // +// // +// Description: Tuner Initialization as a function of 'User Settings' // +// * User settings in Tuner strcuture must be assigned // +// first // +// // +// Globals: // +// NONE // +// // +// Functions used: // +// Tuner_struct: structure defined at higher level // +// // +// Inputs: // +// Tuner : Tuner structure defined at higher level // +// // +// Outputs: // +// Tuner // +// // +// Return: // +// 0 : Successful // +// > 0 : Failed // +// // +/////////////////////////////////////////////////////////////////////////////// +_u16 MXL_BlockInit( Tuner_struct *Tuner ) +{ + _u16 status = 0 ; + + status += MXL_OverwriteICDefault(Tuner) ; + + // + // Downconverter Control + // Dig Ana + status += MXL_ControlWrite(Tuner, DN_IQTN_AMP_CUT, Tuner->Mode ? 1 : 0) ; + + // + // Filter Control + // Dig Ana + status += MXL_ControlWrite(Tuner, BB_MODE, Tuner->Mode ? 0 : 1) ; + status += MXL_ControlWrite(Tuner, BB_BUF, Tuner->Mode ? 3 : 2) ; + status += MXL_ControlWrite(Tuner, BB_BUF_OA, Tuner->Mode ? 1 : 0) ; + + status += MXL_ControlWrite(Tuner, BB_IQSWAP, Tuner->Mode ? 0 : 1) ; + status += MXL_ControlWrite(Tuner, BB_INITSTATE_DLPF_TUNE, 0) ; + + // Initialize Low-Pass Filter + if (Tuner->Mode) { // Digital Mode + switch (Tuner->Chan_Bandwidth) { + case 8000000: + status += MXL_ControlWrite(Tuner, BB_DLPF_BANDSEL, 0) ; + break ; + case 7000000: + status += MXL_ControlWrite(Tuner, BB_DLPF_BANDSEL, 2) ; + break ; + case 6000000: + status += MXL_ControlWrite(Tuner, BB_DLPF_BANDSEL, 3) ; + break ; + } + } else { // Analog Mode + switch (Tuner->Chan_Bandwidth) { + case 8000000: // Low Zero + status += MXL_ControlWrite(Tuner, BB_ALPF_BANDSELECT, (Tuner->IF_Mode ? 0 : 3)) ; + break ; + case 7000000: + status += MXL_ControlWrite(Tuner, BB_ALPF_BANDSELECT, (Tuner->IF_Mode ? 1 : 4)) ; + break ; + case 6000000: + status += MXL_ControlWrite(Tuner, BB_ALPF_BANDSELECT, (Tuner->IF_Mode ? 2 : 5)) ; + break ; + } + } + + // + // Charge Pump Control + // Dig Ana + status += MXL_ControlWrite(Tuner, RFSYN_CHP_GAIN, Tuner->Mode ? 5 : 8) ; + status += MXL_ControlWrite(Tuner, RFSYN_EN_CHP_HIGAIN, Tuner->Mode ? 1 : 1) ; + status += MXL_ControlWrite(Tuner, EN_CHP_LIN_B, Tuner->Mode ? 0 : 0) ; + + // + // AGC TOP Control + // + if (Tuner->AGC_Mode == 0) // Dual AGC + { + status += MXL_ControlWrite(Tuner, AGC_IF, 15) ; + status += MXL_ControlWrite(Tuner, AGC_RF, 15) ; + } + else // Single AGC Mode Dig Ana + status += MXL_ControlWrite(Tuner, AGC_RF, Tuner->Mode? 15 : 12) ; + + + if (Tuner->TOP == 55) // TOP == 5.5 + status += MXL_ControlWrite(Tuner, AGC_IF, 0x0) ; + + if (Tuner->TOP == 72) // TOP == 7.2 + status += MXL_ControlWrite(Tuner, AGC_IF, 0x1) ; + + if (Tuner->TOP == 92) // TOP == 9.2 + status += MXL_ControlWrite(Tuner, AGC_IF, 0x2) ; + + if (Tuner->TOP == 110) // TOP == 11.0 + status += MXL_ControlWrite(Tuner, AGC_IF, 0x3) ; + + if (Tuner->TOP == 129) // TOP == 12.9 + status += MXL_ControlWrite(Tuner, AGC_IF, 0x4) ; + + if (Tuner->TOP == 147) // TOP == 14.7 + status += MXL_ControlWrite(Tuner, AGC_IF, 0x5) ; + + if (Tuner->TOP == 168) // TOP == 16.8 + status += MXL_ControlWrite(Tuner, AGC_IF, 0x6) ; + + if (Tuner->TOP == 194) // TOP == 19.4 + status += MXL_ControlWrite(Tuner, AGC_IF, 0x7) ; + + if (Tuner->TOP == 212) // TOP == 21.2 + status += MXL_ControlWrite(Tuner, AGC_IF, 0x9) ; + + if (Tuner->TOP == 232) // TOP == 23.2 + status += MXL_ControlWrite(Tuner, AGC_IF, 0xA) ; + + if (Tuner->TOP == 252) // TOP == 25.2 + status += MXL_ControlWrite(Tuner, AGC_IF, 0xB) ; + + if (Tuner->TOP == 271) // TOP == 27.1 + status += MXL_ControlWrite(Tuner, AGC_IF, 0xC) ; + + if (Tuner->TOP == 292) // TOP == 29.2 + status += MXL_ControlWrite(Tuner, AGC_IF, 0xD) ; + + if (Tuner->TOP == 317) // TOP == 31.7 + status += MXL_ControlWrite(Tuner, AGC_IF, 0xE) ; + + if (Tuner->TOP == 349) // TOP == 34.9 + status += MXL_ControlWrite(Tuner, AGC_IF, 0xF) ; + + // + // IF Synthesizer Control + // + status += MXL_IFSynthInit( Tuner ) ; + + // + // IF UpConverter Control + if (Tuner->IF_OUT_LOAD == 200) + { + status += MXL_ControlWrite(Tuner, DRV_RES_SEL, 6) ; + status += MXL_ControlWrite(Tuner, I_DRIVER, 2) ; + } + if (Tuner->IF_OUT_LOAD == 300) + { + status += MXL_ControlWrite(Tuner, DRV_RES_SEL, 4) ; + status += MXL_ControlWrite(Tuner, I_DRIVER, 1) ; + } + + // + // Anti-Alias Filtering Control + // + // initialise Anti-Aliasing Filter + if (Tuner->Mode) {// Digital Mode + if (Tuner->IF_OUT >= 4000000UL && Tuner->IF_OUT <= 6280000UL) { + status += MXL_ControlWrite(Tuner, EN_AAF, 1) ; + status += MXL_ControlWrite(Tuner, EN_3P, 1) ; + status += MXL_ControlWrite(Tuner, EN_AUX_3P, 1) ; + status += MXL_ControlWrite(Tuner, SEL_AAF_BAND, 0) ; + } + if ((Tuner->IF_OUT == 36125000UL) || (Tuner->IF_OUT == 36150000UL)) { + status += MXL_ControlWrite(Tuner, EN_AAF, 1) ; + status += MXL_ControlWrite(Tuner, EN_3P, 1) ; + status += MXL_ControlWrite(Tuner, EN_AUX_3P, 1) ; + status += MXL_ControlWrite(Tuner, SEL_AAF_BAND, 1) ; + } + if (Tuner->IF_OUT > 36150000UL) { + status += MXL_ControlWrite(Tuner, EN_AAF, 0) ; + status += MXL_ControlWrite(Tuner, EN_3P, 1) ; + status += MXL_ControlWrite(Tuner, EN_AUX_3P, 1) ; + status += MXL_ControlWrite(Tuner, SEL_AAF_BAND, 1) ; + } + } else { // Analog Mode + if (Tuner->IF_OUT >= 4000000UL && Tuner->IF_OUT <= 5000000UL) + { + status += MXL_ControlWrite(Tuner, EN_AAF, 1) ; + status += MXL_ControlWrite(Tuner, EN_3P, 1) ; + status += MXL_ControlWrite(Tuner, EN_AUX_3P, 1) ; + status += MXL_ControlWrite(Tuner, SEL_AAF_BAND, 0) ; + } + if (Tuner->IF_OUT > 5000000UL) + { + status += MXL_ControlWrite(Tuner, EN_AAF, 0) ; + status += MXL_ControlWrite(Tuner, EN_3P, 0) ; + status += MXL_ControlWrite(Tuner, EN_AUX_3P, 0) ; + status += MXL_ControlWrite(Tuner, SEL_AAF_BAND, 0) ; + } + } + + // + // Demod Clock Out + // + if (Tuner->CLOCK_OUT) + status += MXL_ControlWrite(Tuner, SEQ_ENCLK16_CLK_OUT, 1) ; + else + status += MXL_ControlWrite(Tuner, SEQ_ENCLK16_CLK_OUT, 0) ; + + if (Tuner->DIV_OUT == 1) + status += MXL_ControlWrite(Tuner, SEQ_SEL4_16B, 1) ; + if (Tuner->DIV_OUT == 0) + status += MXL_ControlWrite(Tuner, SEQ_SEL4_16B, 0) ; + + // + // Crystal Control + // + if (Tuner->CAPSELECT) + status += MXL_ControlWrite(Tuner, XTAL_CAPSELECT, 1) ; + else + status += MXL_ControlWrite(Tuner, XTAL_CAPSELECT, 0) ; + + if (Tuner->Fxtal >= 12000000UL && Tuner->Fxtal <= 16000000UL) + status += MXL_ControlWrite(Tuner, IF_SEL_DBL, 1) ; + if (Tuner->Fxtal > 16000000UL && Tuner->Fxtal <= 32000000UL) + status += MXL_ControlWrite(Tuner, IF_SEL_DBL, 0) ; + + if (Tuner->Fxtal >= 12000000UL && Tuner->Fxtal <= 22000000UL) + status += MXL_ControlWrite(Tuner, RFSYN_R_DIV, 3) ; + if (Tuner->Fxtal > 22000000UL && Tuner->Fxtal <= 32000000UL) + status += MXL_ControlWrite(Tuner, RFSYN_R_DIV, 0) ; + + // + // Misc Controls + // + if (Tuner->Mode == 0 && Tuner->IF_Mode == 1) // Analog LowIF mode + status += MXL_ControlWrite(Tuner, SEQ_EXTIQFSMPULSE, 0); + else + status += MXL_ControlWrite(Tuner, SEQ_EXTIQFSMPULSE, 1); + +// status += MXL_ControlRead(Tuner, IF_DIVVAL, &IF_DIVVAL_Val) ; + + // Set TG_R_DIV + status += MXL_ControlWrite(Tuner, TG_R_DIV, MXL_Ceiling(Tuner->Fxtal, 1000000)) ; + + // + // Apply Default value to BB_INITSTATE_DLPF_TUNE + // + + + + // + // RSSI Control + // + if(Tuner->EN_RSSI) + { + status += MXL_ControlWrite(Tuner, SEQ_EXTSYNTHCALIF, 1) ; + status += MXL_ControlWrite(Tuner, SEQ_EXTDCCAL, 1) ; + status += MXL_ControlWrite(Tuner, AGC_EN_RSSI, 1) ; + status += MXL_ControlWrite(Tuner, RFA_ENCLKRFAGC, 1) ; + // RSSI reference point + status += MXL_ControlWrite(Tuner, RFA_RSSI_REF, 2) ; + status += MXL_ControlWrite(Tuner, RFA_RSSI_REFH, 3) ; + status += MXL_ControlWrite(Tuner, RFA_RSSI_REFL, 1) ; + // TOP point + status += MXL_ControlWrite(Tuner, RFA_FLR, 0) ; + status += MXL_ControlWrite(Tuner, RFA_CEIL, 12) ; + } + + // + // Modulation type bit settings + // Override the control values preset + // + if (Tuner->Mod_Type == MXL_DVBT) // DVB-T Mode + { + Tuner->AGC_Mode = 1 ; // Single AGC Mode + + // Enable RSSI + status += MXL_ControlWrite(Tuner, SEQ_EXTSYNTHCALIF, 1) ; + status += MXL_ControlWrite(Tuner, SEQ_EXTDCCAL, 1) ; + status += MXL_ControlWrite(Tuner, AGC_EN_RSSI, 1) ; + status += MXL_ControlWrite(Tuner, RFA_ENCLKRFAGC, 1) ; + // RSSI reference point + status += MXL_ControlWrite(Tuner, RFA_RSSI_REF, 3) ; + status += MXL_ControlWrite(Tuner, RFA_RSSI_REFH, 5) ; + status += MXL_ControlWrite(Tuner, RFA_RSSI_REFL, 1) ; + // TOP point + status += MXL_ControlWrite(Tuner, RFA_FLR, 2) ; + status += MXL_ControlWrite(Tuner, RFA_CEIL, 13) ; + if (Tuner->IF_OUT <= 6280000UL) // Low IF + status += MXL_ControlWrite(Tuner, BB_IQSWAP, 0) ; + else // High IF + status += MXL_ControlWrite(Tuner, BB_IQSWAP, 1) ; + + } + if (Tuner->Mod_Type == MXL_ATSC) // ATSC Mode + { + Tuner->AGC_Mode = 1 ; // Single AGC Mode + + // Enable RSSI + status += MXL_ControlWrite(Tuner, SEQ_EXTSYNTHCALIF, 1) ; + status += MXL_ControlWrite(Tuner, SEQ_EXTDCCAL, 1) ; + status += MXL_ControlWrite(Tuner, AGC_EN_RSSI, 1) ; + status += MXL_ControlWrite(Tuner, RFA_ENCLKRFAGC, 1) ; + // RSSI reference point + status += MXL_ControlWrite(Tuner, RFA_RSSI_REF, 2) ; + status += MXL_ControlWrite(Tuner, RFA_RSSI_REFH, 4) ; + status += MXL_ControlWrite(Tuner, RFA_RSSI_REFL, 1) ; + // TOP point + status += MXL_ControlWrite(Tuner, RFA_FLR, 2) ; + status += MXL_ControlWrite(Tuner, RFA_CEIL, 13) ; + + status += MXL_ControlWrite(Tuner, BB_INITSTATE_DLPF_TUNE, 1) ; + status += MXL_ControlWrite(Tuner, RFSYN_CHP_GAIN, 5) ; // Low Zero + if (Tuner->IF_OUT <= 6280000UL) // Low IF + status += MXL_ControlWrite(Tuner, BB_IQSWAP, 0) ; + else // High IF + status += MXL_ControlWrite(Tuner, BB_IQSWAP, 1) ; + } + if (Tuner->Mod_Type == MXL_QAM) // QAM Mode + { + Tuner->Mode = MXL_DIGITAL_MODE; + + //Tuner->AGC_Mode = 1 ; // Single AGC Mode + + // Disable RSSI //change here for v2.6.5 + status += MXL_ControlWrite(Tuner, SEQ_EXTSYNTHCALIF, 1) ; + status += MXL_ControlWrite(Tuner, SEQ_EXTDCCAL, 1) ; + status += MXL_ControlWrite(Tuner, AGC_EN_RSSI, 0) ; + status += MXL_ControlWrite(Tuner, RFA_ENCLKRFAGC, 1) ; + + // RSSI reference point + status += MXL_ControlWrite(Tuner, RFA_RSSI_REFH, 5) ; + status += MXL_ControlWrite(Tuner, RFA_RSSI_REF, 3) ; + status += MXL_ControlWrite(Tuner, RFA_RSSI_REFL, 2) ; + + status += MXL_ControlWrite(Tuner, RFSYN_CHP_GAIN, 3) ; //change here for v2.6.5 + + if (Tuner->IF_OUT <= 6280000UL) // Low IF + status += MXL_ControlWrite(Tuner, BB_IQSWAP, 0) ; + else // High IF + status += MXL_ControlWrite(Tuner, BB_IQSWAP, 1) ; + } + if (Tuner->Mod_Type == MXL_ANALOG_CABLE) // Analog Cable Mode + { + //Tuner->Mode = MXL_DIGITAL_MODE ; + Tuner->AGC_Mode = 1 ; // Single AGC Mode + + // Disable RSSI + status += MXL_ControlWrite(Tuner, SEQ_EXTSYNTHCALIF, 1) ; + status += MXL_ControlWrite(Tuner, SEQ_EXTDCCAL, 1) ; + status += MXL_ControlWrite(Tuner, AGC_EN_RSSI, 0) ; + status += MXL_ControlWrite(Tuner, RFA_ENCLKRFAGC, 1) ; + + status += MXL_ControlWrite(Tuner, AGC_IF, 1) ; //change for 2.6.3 + status += MXL_ControlWrite(Tuner, AGC_RF, 15) ; + + status += MXL_ControlWrite(Tuner, BB_IQSWAP, 1) ; + } + + if (Tuner->Mod_Type == MXL_ANALOG_OTA) //Analog OTA Terrestrial mode add for 2.6.7 + { + //Tuner->Mode = MXL_ANALOG_MODE; + + // Enable RSSI + status += MXL_ControlWrite(Tuner, SEQ_EXTSYNTHCALIF, 1) ; + status += MXL_ControlWrite(Tuner, SEQ_EXTDCCAL, 1) ; + status += MXL_ControlWrite(Tuner, AGC_EN_RSSI, 1) ; + status += MXL_ControlWrite(Tuner, RFA_ENCLKRFAGC, 1) ; + + // RSSI reference point + status += MXL_ControlWrite(Tuner, RFA_RSSI_REFH, 5) ; + status += MXL_ControlWrite(Tuner, RFA_RSSI_REF, 3) ; + status += MXL_ControlWrite(Tuner, RFA_RSSI_REFL, 2) ; + + status += MXL_ControlWrite(Tuner, RFSYN_CHP_GAIN, 3) ; + + status += MXL_ControlWrite(Tuner, BB_IQSWAP, 1) ; + } + + // RSSI disable + if(Tuner->EN_RSSI==0) + { + status += MXL_ControlWrite(Tuner, SEQ_EXTSYNTHCALIF, 1) ; + status += MXL_ControlWrite(Tuner, SEQ_EXTDCCAL, 1) ; + status += MXL_ControlWrite(Tuner, AGC_EN_RSSI, 0) ; + status += MXL_ControlWrite(Tuner, RFA_ENCLKRFAGC, 1) ; + } + + return status ; +} + +/////////////////////////////////////////////////////////////////////////////// +// // +// Function: MXL_IFSynthInit // +// // +// Description: Tuner IF Synthesizer related register initialization // +// // +// Globals: // +// NONE // +// // +// Functions used: // +// Tuner_struct: structure defined at higher level // +// // +// Inputs: // +// Tuner : Tuner structure defined at higher level // +// // +// Outputs: // +// Tuner // +// // +// Return: // +// 0 : Successful // +// > 0 : Failed // +// // +/////////////////////////////////////////////////////////////////////////////// +_u16 MXL_IFSynthInit( Tuner_struct * Tuner ) +{ + _u16 status = 0 ; + // Declare Local Variables + _u32 Fref = 0 ; + _u32 Kdbl, intModVal ; + _u32 fracModVal ; + Kdbl = 2 ; + + if (Tuner->Fxtal >= 12000000UL && Tuner->Fxtal <= 16000000UL) + Kdbl = 2 ; + if (Tuner->Fxtal > 16000000UL && Tuner->Fxtal <= 32000000UL) + Kdbl = 1 ; + + // + // IF Synthesizer Control + // + if (Tuner->Mode == 0 && Tuner->IF_Mode == 1) // Analog Low IF mode + { + if (Tuner->IF_LO == 41000000UL) { + status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x08) ; + status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x0C) ; + Fref = 328000000UL ; + } + if (Tuner->IF_LO == 47000000UL) { + status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x08) ; + status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x08) ; + Fref = 376000000UL ; + } + if (Tuner->IF_LO == 54000000UL) { + status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x10) ; + status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x0C) ; + Fref = 324000000UL ; + } + if (Tuner->IF_LO == 60000000UL) { + status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x10) ; + status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x08) ; + Fref = 360000000UL ; + } + if (Tuner->IF_LO == 39250000UL) { + status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x08) ; + status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x0C) ; + Fref = 314000000UL ; + } + if (Tuner->IF_LO == 39650000UL) { + status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x08) ; + status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x0C) ; + Fref = 317200000UL ; + } + if (Tuner->IF_LO == 40150000UL) { + status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x08) ; + status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x0C) ; + Fref = 321200000UL ; + } + if (Tuner->IF_LO == 40650000UL) { + status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x08) ; + status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x0C) ; + Fref = 325200000UL ; + } + } + + if (Tuner->Mode || (Tuner->Mode == 0 && Tuner->IF_Mode == 0)) + { + if (Tuner->IF_LO == 57000000UL) { + status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x10) ; + status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x08) ; + Fref = 342000000UL ; + } + if (Tuner->IF_LO == 44000000UL) { + status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x08) ; + status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x08) ; + Fref = 352000000UL ; + } + if (Tuner->IF_LO == 43750000UL) { + status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x08) ; + status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x08) ; + Fref = 350000000UL ; + } + if (Tuner->IF_LO == 36650000UL) { + status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x04) ; + status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x08) ; + Fref = 366500000UL ; + } + if (Tuner->IF_LO == 36150000UL) { + status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x04) ; + status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x08) ; + Fref = 361500000UL ; + } + if (Tuner->IF_LO == 36000000UL) { + status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x04) ; + status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x08) ; + Fref = 360000000UL ; + } + if (Tuner->IF_LO == 35250000UL) { + status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x04) ; + status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x08) ; + Fref = 352500000UL ; + } + if (Tuner->IF_LO == 34750000UL) { + status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x04) ; + status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x08) ; + Fref = 347500000UL ; + } + if (Tuner->IF_LO == 6280000UL) { + status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x07) ; + status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x08) ; + Fref = 376800000UL ; + } + if (Tuner->IF_LO == 5000000UL) { + status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x09) ; + status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x08) ; + Fref = 360000000UL ; + } + if (Tuner->IF_LO == 4500000UL) { + status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x06) ; + status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x08) ; + Fref = 360000000UL ; + } + if (Tuner->IF_LO == 4570000UL) { + status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x06) ; + status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x08) ; + Fref = 365600000UL ; + } + if (Tuner->IF_LO == 4000000UL) { + status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x05) ; + status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x08) ; + Fref = 360000000UL ; + } + if (Tuner->IF_LO == 57400000UL) + { + status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x10) ; + status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x08) ; + Fref = 344400000UL ; + } + if (Tuner->IF_LO == 44400000UL) + { + status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x08) ; + status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x08) ; + Fref = 355200000UL ; + } + if (Tuner->IF_LO == 44150000UL) + { + status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x08) ; + status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x08) ; + Fref = 353200000UL ; + } + if (Tuner->IF_LO == 37050000UL) + { + status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x04) ; + status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x08) ; + Fref = 370500000UL ; + } + if (Tuner->IF_LO == 36550000UL) + { + status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x04) ; + status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x08) ; + Fref = 365500000UL ; + } + if (Tuner->IF_LO == 36125000UL) { + status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x04) ; + status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x08) ; + Fref = 361250000UL ; + } + if (Tuner->IF_LO == 6000000UL) { + status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x07) ; + status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x08) ; + Fref = 360000000UL ; + } + if (Tuner->IF_LO == 5400000UL) + { + status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x07) ; + status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x0C) ; + Fref = 324000000UL ; + } + if (Tuner->IF_LO == 5380000UL) { + status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x07) ; + status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x0C) ; + Fref = 322800000UL ; + } + if (Tuner->IF_LO == 5200000UL) { + status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x09) ; + status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x08) ; + Fref = 374400000UL ; + } + if (Tuner->IF_LO == 4900000UL) + { + status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x09) ; + status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x08) ; + Fref = 352800000UL ; + } + if (Tuner->IF_LO == 4400000UL) + { + status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x06) ; + status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x08) ; + Fref = 352000000UL ; + } + if (Tuner->IF_LO == 4063000UL) //add for 2.6.8 + { + status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x05) ; + status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x08) ; + Fref = 365670000UL ; + } + } + // CHCAL_INT_MOD_IF + // CHCAL_FRAC_MOD_IF + intModVal = Fref / (Tuner->Fxtal * Kdbl/2) ; + status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_IF, intModVal ) ; + + fracModVal = (2<<15)*(Fref/1000 - (Tuner->Fxtal/1000 * Kdbl/2) * intModVal); + fracModVal = fracModVal / ((Tuner->Fxtal * Kdbl/2)/1000) ; + status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_IF, fracModVal) ; + + + + return status ; +} + +/////////////////////////////////////////////////////////////////////////////// +// // +// Function: MXL_GetXtalInt // +// // +// Description: return the Crystal Integration Value for // +// TG_VCO_BIAS calculation // +// // +// Globals: // +// NONE // +// // +// Functions used: // +// NONE // +// // +// Inputs: // +// Crystal Frequency Value in Hz // +// // +// Outputs: // +// Calculated Crystal Frequency Integration Value // +// // +// Return: // +// 0 : Successful // +// > 0 : Failed // +// // +/////////////////////////////////////////////////////////////////////////////// +_u32 MXL_GetXtalInt(_u32 Xtal_Freq) +{ + if ((Xtal_Freq % 1000000) == 0) + return (Xtal_Freq / 10000) ; + else + return (((Xtal_Freq / 1000000) + 1)*100) ; +} + +/////////////////////////////////////////////////////////////////////////////// +// // +// Function: MXL5005_TuneRF // +// // +// Description: Set control names to tune to requested RF_IN frequency // +// // +// Globals: // +// None // +// // +// Functions used: // +// MXL_SynthRFTGLO_Calc // +// MXL5005_ControlWrite // +// MXL_GetXtalInt // +// // +// Inputs: // +// Tuner : Tuner structure defined at higher level // +// // +// Outputs: // +// Tuner // +// // +// Return: // +// 0 : Successful // +// 1 : Unsuccessful // +/////////////////////////////////////////////////////////////////////////////// +_u16 MXL_TuneRF(Tuner_struct *Tuner, _u32 RF_Freq) +{ + // Declare Local Variables + _u16 status = 0 ; + _u32 divider_val, E3, E4, E5, E5A ; + _u32 Fmax, Fmin, FmaxBin, FminBin ; + _u32 Kdbl_RF = 2; + _u32 tg_divval ; + _u32 tg_lo ; + _u32 Xtal_Int ; + + _u32 Fref_TG; + _u32 Fvco; +// _u32 temp; + + + Xtal_Int = MXL_GetXtalInt(Tuner->Fxtal ) ; + + Tuner->RF_IN = RF_Freq ; + + MXL_SynthRFTGLO_Calc( Tuner ) ; + + if (Tuner->Fxtal >= 12000000UL && Tuner->Fxtal <= 22000000UL) + Kdbl_RF = 2 ; + if (Tuner->Fxtal > 22000000 && Tuner->Fxtal <= 32000000) + Kdbl_RF = 1 ; + + // + // Downconverter Controls + // + // Look-Up Table Implementation for: + // DN_POLY + // DN_RFGAIN + // DN_CAP_RFLPF + // DN_EN_VHFUHFBAR + // DN_GAIN_ADJUST + // Change the boundary reference from RF_IN to RF_LO + if (Tuner->RF_LO < 40000000UL) { + return -1; + } + if (Tuner->RF_LO >= 40000000UL && Tuner->RF_LO <= 75000000UL) { + // Look-Up Table implementation + status += MXL_ControlWrite(Tuner, DN_POLY, 2) ; + status += MXL_ControlWrite(Tuner, DN_RFGAIN, 3) ; + status += MXL_ControlWrite(Tuner, DN_CAP_RFLPF, 423) ; + status += MXL_ControlWrite(Tuner, DN_EN_VHFUHFBAR, 1) ; + status += MXL_ControlWrite(Tuner, DN_GAIN_ADJUST, 1) ; + } + if (Tuner->RF_LO > 75000000UL && Tuner->RF_LO <= 100000000UL) { + // Look-Up Table implementation + status += MXL_ControlWrite(Tuner, DN_POLY, 3) ; + status += MXL_ControlWrite(Tuner, DN_RFGAIN, 3) ; + status += MXL_ControlWrite(Tuner, DN_CAP_RFLPF, 222) ; + status += MXL_ControlWrite(Tuner, DN_EN_VHFUHFBAR, 1) ; + status += MXL_ControlWrite(Tuner, DN_GAIN_ADJUST, 1) ; + } + if (Tuner->RF_LO > 100000000UL && Tuner->RF_LO <= 150000000UL) { + // Look-Up Table implementation + status += MXL_ControlWrite(Tuner, DN_POLY, 3) ; + status += MXL_ControlWrite(Tuner, DN_RFGAIN, 3) ; + status += MXL_ControlWrite(Tuner, DN_CAP_RFLPF, 147) ; + status += MXL_ControlWrite(Tuner, DN_EN_VHFUHFBAR, 1) ; + status += MXL_ControlWrite(Tuner, DN_GAIN_ADJUST, 2) ; + } + if (Tuner->RF_LO > 150000000UL && Tuner->RF_LO <= 200000000UL) { + // Look-Up Table implementation + status += MXL_ControlWrite(Tuner, DN_POLY, 3) ; + status += MXL_ControlWrite(Tuner, DN_RFGAIN, 3) ; + status += MXL_ControlWrite(Tuner, DN_CAP_RFLPF, 9) ; + status += MXL_ControlWrite(Tuner, DN_EN_VHFUHFBAR, 1) ; + status += MXL_ControlWrite(Tuner, DN_GAIN_ADJUST, 2) ; + } + if (Tuner->RF_LO > 200000000UL && Tuner->RF_LO <= 300000000UL) { + // Look-Up Table implementation + status += MXL_ControlWrite(Tuner, DN_POLY, 3) ; + status += MXL_ControlWrite(Tuner, DN_RFGAIN, 3) ; + status += MXL_ControlWrite(Tuner, DN_CAP_RFLPF, 0) ; + status += MXL_ControlWrite(Tuner, DN_EN_VHFUHFBAR, 1) ; + status += MXL_ControlWrite(Tuner, DN_GAIN_ADJUST, 3) ; + } + if (Tuner->RF_LO > 300000000UL && Tuner->RF_LO <= 650000000UL) { + // Look-Up Table implementation + status += MXL_ControlWrite(Tuner, DN_POLY, 3) ; + status += MXL_ControlWrite(Tuner, DN_RFGAIN, 1) ; + status += MXL_ControlWrite(Tuner, DN_CAP_RFLPF, 0) ; + status += MXL_ControlWrite(Tuner, DN_EN_VHFUHFBAR, 0) ; + status += MXL_ControlWrite(Tuner, DN_GAIN_ADJUST, 3) ; + } + if (Tuner->RF_LO > 650000000UL && Tuner->RF_LO <= 900000000UL) { + // Look-Up Table implementation + status += MXL_ControlWrite(Tuner, DN_POLY, 3) ; + status += MXL_ControlWrite(Tuner, DN_RFGAIN, 2) ; + status += MXL_ControlWrite(Tuner, DN_CAP_RFLPF, 0) ; + status += MXL_ControlWrite(Tuner, DN_EN_VHFUHFBAR, 0) ; + status += MXL_ControlWrite(Tuner, DN_GAIN_ADJUST, 3) ; + } + if (Tuner->RF_LO > 900000000UL) { + return -1; + } + // DN_IQTNBUF_AMP + // DN_IQTNGNBFBIAS_BST + if (Tuner->RF_LO >= 40000000UL && Tuner->RF_LO <= 75000000UL) { + status += MXL_ControlWrite(Tuner, DN_IQTNBUF_AMP, 1) ; + status += MXL_ControlWrite(Tuner, DN_IQTNGNBFBIAS_BST, 0) ; + } + if (Tuner->RF_LO > 75000000UL && Tuner->RF_LO <= 100000000UL) { + status += MXL_ControlWrite(Tuner, DN_IQTNBUF_AMP, 1) ; + status += MXL_ControlWrite(Tuner, DN_IQTNGNBFBIAS_BST, 0) ; + } + if (Tuner->RF_LO > 100000000UL && Tuner->RF_LO <= 150000000UL) { + status += MXL_ControlWrite(Tuner, DN_IQTNBUF_AMP, 1) ; + status += MXL_ControlWrite(Tuner, DN_IQTNGNBFBIAS_BST, 0) ; + } + if (Tuner->RF_LO > 150000000UL && Tuner->RF_LO <= 200000000UL) { + status += MXL_ControlWrite(Tuner, DN_IQTNBUF_AMP, 1) ; + status += MXL_ControlWrite(Tuner, DN_IQTNGNBFBIAS_BST, 0) ; + } + if (Tuner->RF_LO > 200000000UL && Tuner->RF_LO <= 300000000UL) { + status += MXL_ControlWrite(Tuner, DN_IQTNBUF_AMP, 1) ; + status += MXL_ControlWrite(Tuner, DN_IQTNGNBFBIAS_BST, 0) ; + } + if (Tuner->RF_LO > 300000000UL && Tuner->RF_LO <= 400000000UL) { + status += MXL_ControlWrite(Tuner, DN_IQTNBUF_AMP, 1) ; + status += MXL_ControlWrite(Tuner, DN_IQTNGNBFBIAS_BST, 0) ; + } + if (Tuner->RF_LO > 400000000UL && Tuner->RF_LO <= 450000000UL) { + status += MXL_ControlWrite(Tuner, DN_IQTNBUF_AMP, 1) ; + status += MXL_ControlWrite(Tuner, DN_IQTNGNBFBIAS_BST, 0) ; + } + if (Tuner->RF_LO > 450000000UL && Tuner->RF_LO <= 500000000UL) { + status += MXL_ControlWrite(Tuner, DN_IQTNBUF_AMP, 1) ; + status += MXL_ControlWrite(Tuner, DN_IQTNGNBFBIAS_BST, 0) ; + } + if (Tuner->RF_LO > 500000000UL && Tuner->RF_LO <= 550000000UL) { + status += MXL_ControlWrite(Tuner, DN_IQTNBUF_AMP, 1) ; + status += MXL_ControlWrite(Tuner, DN_IQTNGNBFBIAS_BST, 0) ; + } + if (Tuner->RF_LO > 550000000UL && Tuner->RF_LO <= 600000000UL) { + status += MXL_ControlWrite(Tuner, DN_IQTNBUF_AMP, 1) ; + status += MXL_ControlWrite(Tuner, DN_IQTNGNBFBIAS_BST, 0) ; + } + if (Tuner->RF_LO > 600000000UL && Tuner->RF_LO <= 650000000UL) { + status += MXL_ControlWrite(Tuner, DN_IQTNBUF_AMP, 1) ; + status += MXL_ControlWrite(Tuner, DN_IQTNGNBFBIAS_BST, 0) ; + } + if (Tuner->RF_LO > 650000000UL && Tuner->RF_LO <= 700000000UL) { + status += MXL_ControlWrite(Tuner, DN_IQTNBUF_AMP, 1) ; + status += MXL_ControlWrite(Tuner, DN_IQTNGNBFBIAS_BST, 0) ; + } + if (Tuner->RF_LO > 700000000UL && Tuner->RF_LO <= 750000000UL) { + status += MXL_ControlWrite(Tuner, DN_IQTNBUF_AMP, 1) ; + status += MXL_ControlWrite(Tuner, DN_IQTNGNBFBIAS_BST, 0) ; + } + if (Tuner->RF_LO > 750000000UL && Tuner->RF_LO <= 800000000UL) { + status += MXL_ControlWrite(Tuner, DN_IQTNBUF_AMP, 1) ; + status += MXL_ControlWrite(Tuner, DN_IQTNGNBFBIAS_BST, 0) ; + } + if (Tuner->RF_LO > 800000000UL && Tuner->RF_LO <= 850000000UL) { + status += MXL_ControlWrite(Tuner, DN_IQTNBUF_AMP, 10) ; + status += MXL_ControlWrite(Tuner, DN_IQTNGNBFBIAS_BST, 1) ; + } + if (Tuner->RF_LO > 850000000UL && Tuner->RF_LO <= 900000000UL) { + status += MXL_ControlWrite(Tuner, DN_IQTNBUF_AMP, 10) ; + status += MXL_ControlWrite(Tuner, DN_IQTNGNBFBIAS_BST, 1) ; + } + + // + // Set RF Synth and LO Path Control + // + // Look-Up table implementation for: + // RFSYN_EN_OUTMUX + // RFSYN_SEL_VCO_OUT + // RFSYN_SEL_VCO_HI + // RFSYN_SEL_DIVM + // RFSYN_RF_DIV_BIAS + // DN_SEL_FREQ + // + // Set divider_val, Fmax, Fmix to use in Equations + FminBin = 28000000UL ; + FmaxBin = 42500000UL ; + if (Tuner->RF_LO >= 40000000UL && Tuner->RF_LO <= FmaxBin) { + status += MXL_ControlWrite(Tuner, RFSYN_EN_OUTMUX, 1) ; + status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_OUT, 0) ; + status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 0) ; + status += MXL_ControlWrite(Tuner, RFSYN_SEL_DIVM, 0) ; + status += MXL_ControlWrite(Tuner, RFSYN_RF_DIV_BIAS, 1) ; + status += MXL_ControlWrite(Tuner, DN_SEL_FREQ, 1) ; + divider_val = 64 ; + Fmax = FmaxBin ; + Fmin = FminBin ; + } + FminBin = 42500000UL ; + FmaxBin = 56000000UL ; + if (Tuner->RF_LO > FminBin && Tuner->RF_LO <= FmaxBin) { + status += MXL_ControlWrite(Tuner, RFSYN_EN_OUTMUX, 1) ; + status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_OUT, 0) ; + status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 1) ; + status += MXL_ControlWrite(Tuner, RFSYN_SEL_DIVM, 0) ; + status += MXL_ControlWrite(Tuner, RFSYN_RF_DIV_BIAS, 1) ; + status += MXL_ControlWrite(Tuner, DN_SEL_FREQ, 1) ; + divider_val = 64 ; + Fmax = FmaxBin ; + Fmin = FminBin ; + } + FminBin = 56000000UL ; + FmaxBin = 85000000UL ; + if (Tuner->RF_LO > FminBin && Tuner->RF_LO <= FmaxBin) { + status += MXL_ControlWrite(Tuner, RFSYN_EN_OUTMUX, 0) ; + status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_OUT, 1) ; + status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 0) ; + status += MXL_ControlWrite(Tuner, RFSYN_SEL_DIVM, 0) ; + status += MXL_ControlWrite(Tuner, RFSYN_RF_DIV_BIAS, 1) ; + status += MXL_ControlWrite(Tuner, DN_SEL_FREQ, 1) ; + divider_val = 32 ; + Fmax = FmaxBin ; + Fmin = FminBin ; + } + FminBin = 85000000UL ; + FmaxBin = 112000000UL ; + if (Tuner->RF_LO > FminBin && Tuner->RF_LO <= FmaxBin) { + status += MXL_ControlWrite(Tuner, RFSYN_EN_OUTMUX, 0) ; + status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_OUT, 1) ; + status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 1) ; + status += MXL_ControlWrite(Tuner, RFSYN_SEL_DIVM, 0) ; + status += MXL_ControlWrite(Tuner, RFSYN_RF_DIV_BIAS, 1) ; + status += MXL_ControlWrite(Tuner, DN_SEL_FREQ, 1) ; + divider_val = 32 ; + Fmax = FmaxBin ; + Fmin = FminBin ; + } + FminBin = 112000000UL ; + FmaxBin = 170000000UL ; + if (Tuner->RF_LO > FminBin && Tuner->RF_LO <= FmaxBin) { + status += MXL_ControlWrite(Tuner, RFSYN_EN_OUTMUX, 0) ; + status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_OUT, 1) ; + status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 0) ; + status += MXL_ControlWrite(Tuner, RFSYN_SEL_DIVM, 0) ; + status += MXL_ControlWrite(Tuner, RFSYN_RF_DIV_BIAS, 1) ; + status += MXL_ControlWrite(Tuner, DN_SEL_FREQ, 2) ; + divider_val = 16 ; + Fmax = FmaxBin ; + Fmin = FminBin ; + } + FminBin = 170000000UL ; + FmaxBin = 225000000UL ; + if (Tuner->RF_LO > FminBin && Tuner->RF_LO <= FmaxBin) { + status += MXL_ControlWrite(Tuner, RFSYN_EN_OUTMUX, 0) ; + status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_OUT, 1) ; + status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 1) ; + status += MXL_ControlWrite(Tuner, RFSYN_SEL_DIVM, 0) ; + status += MXL_ControlWrite(Tuner, RFSYN_RF_DIV_BIAS, 1) ; + status += MXL_ControlWrite(Tuner, DN_SEL_FREQ, 2) ; + divider_val = 16 ; + Fmax = FmaxBin ; + Fmin = FminBin ; + } + FminBin = 225000000UL ; + FmaxBin = 300000000UL ; + if (Tuner->RF_LO > FminBin && Tuner->RF_LO <= FmaxBin) { + status += MXL_ControlWrite(Tuner, RFSYN_EN_OUTMUX, 0) ; + status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_OUT, 1) ; + status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 0) ; + status += MXL_ControlWrite(Tuner, RFSYN_SEL_DIVM, 0) ; + status += MXL_ControlWrite(Tuner, RFSYN_RF_DIV_BIAS, 1) ; + status += MXL_ControlWrite(Tuner, DN_SEL_FREQ, 4) ; + divider_val = 8 ; + Fmax = 340000000UL ; + Fmin = FminBin ; + } + FminBin = 300000000UL ; + FmaxBin = 340000000UL ; + if (Tuner->RF_LO > FminBin && Tuner->RF_LO <= FmaxBin) { + status += MXL_ControlWrite(Tuner, RFSYN_EN_OUTMUX, 1) ; + status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_OUT, 0) ; + status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 0) ; + status += MXL_ControlWrite(Tuner, RFSYN_SEL_DIVM, 0) ; + status += MXL_ControlWrite(Tuner, RFSYN_RF_DIV_BIAS, 1) ; + status += MXL_ControlWrite(Tuner, DN_SEL_FREQ, 0) ; + divider_val = 8 ; + Fmax = FmaxBin ; + Fmin = 225000000UL ; + } + FminBin = 340000000UL ; + FmaxBin = 450000000UL ; + if (Tuner->RF_LO > FminBin && Tuner->RF_LO <= FmaxBin) { + status += MXL_ControlWrite(Tuner, RFSYN_EN_OUTMUX, 1) ; + status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_OUT, 0) ; + status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 1) ; + status += MXL_ControlWrite(Tuner, RFSYN_SEL_DIVM, 0) ; + status += MXL_ControlWrite(Tuner, RFSYN_RF_DIV_BIAS, 2) ; + status += MXL_ControlWrite(Tuner, DN_SEL_FREQ, 0) ; + divider_val = 8 ; + Fmax = FmaxBin ; + Fmin = FminBin ; + } + FminBin = 450000000UL ; + FmaxBin = 680000000UL ; + if (Tuner->RF_LO > FminBin && Tuner->RF_LO <= FmaxBin) { + status += MXL_ControlWrite(Tuner, RFSYN_EN_OUTMUX, 0) ; + status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_OUT, 1) ; + status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 0) ; + status += MXL_ControlWrite(Tuner, RFSYN_SEL_DIVM, 1) ; + status += MXL_ControlWrite(Tuner, RFSYN_RF_DIV_BIAS, 1) ; + status += MXL_ControlWrite(Tuner, DN_SEL_FREQ, 0) ; + divider_val = 4 ; + Fmax = FmaxBin ; + Fmin = FminBin ; + } + FminBin = 680000000UL ; + FmaxBin = 900000000UL ; + if (Tuner->RF_LO > FminBin && Tuner->RF_LO <= FmaxBin) { + status += MXL_ControlWrite(Tuner, RFSYN_EN_OUTMUX, 0) ; + status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_OUT, 1) ; + status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 1) ; + status += MXL_ControlWrite(Tuner, RFSYN_SEL_DIVM, 1) ; + status += MXL_ControlWrite(Tuner, RFSYN_RF_DIV_BIAS, 1) ; + status += MXL_ControlWrite(Tuner, DN_SEL_FREQ, 0) ; + divider_val = 4 ; + Fmax = FmaxBin ; + Fmin = FminBin ; + } + + // CHCAL_INT_MOD_RF + // CHCAL_FRAC_MOD_RF + // RFSYN_LPF_R + // CHCAL_EN_INT_RF + + // Equation E3 + // RFSYN_VCO_BIAS + E3 = (((Fmax-Tuner->RF_LO)/1000)*32)/((Fmax-Fmin)/1000) + 8 ; + status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, E3) ; + + // Equation E4 + // CHCAL_INT_MOD_RF + E4 = (Tuner->RF_LO*divider_val/1000)/(2*Tuner->Fxtal*Kdbl_RF/1000) ; + MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, E4) ; + + // Equation E5 + // CHCAL_FRAC_MOD_RF + // CHCAL_EN_INT_RF + E5 = ((2<<17)*(Tuner->RF_LO/10000*divider_val - (E4*(2*Tuner->Fxtal*Kdbl_RF)/10000)))/(2*Tuner->Fxtal*Kdbl_RF/10000) ; + status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_RF, E5) ; + + // Equation E5A + // RFSYN_LPF_R + E5A = (((Fmax - Tuner->RF_LO)/1000)*4/((Fmax-Fmin)/1000)) + 1 ; + status += MXL_ControlWrite(Tuner, RFSYN_LPF_R, E5A) ; + + // Euqation E5B + // CHCAL_EN_INIT_RF + status += MXL_ControlWrite(Tuner, CHCAL_EN_INT_RF, ((E5 == 0) ? 1 : 0)); + //if (E5 == 0) + // status += MXL_ControlWrite(Tuner, CHCAL_EN_INT_RF, 1); + //else + // status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_RF, E5) ; + + // + // Set TG Synth + // + // Look-Up table implementation for: + // TG_LO_DIVVAL + // TG_LO_SELVAL + // + // Set divider_val, Fmax, Fmix to use in Equations + if (Tuner->TG_LO < 33000000UL) { + return -1; + } + FminBin = 33000000UL ; + FmaxBin = 50000000UL ; + if (Tuner->TG_LO >= FminBin && Tuner->TG_LO <= FmaxBin) { + status += MXL_ControlWrite(Tuner, TG_LO_DIVVAL, 0x6) ; + status += MXL_ControlWrite(Tuner, TG_LO_SELVAL, 0x0) ; + divider_val = 36 ; + Fmax = FmaxBin ; + Fmin = FminBin ; + } + FminBin = 50000000UL ; + FmaxBin = 67000000UL ; + if (Tuner->TG_LO > FminBin && Tuner->TG_LO <= FmaxBin) { + status += MXL_ControlWrite(Tuner, TG_LO_DIVVAL, 0x1) ; + status += MXL_ControlWrite(Tuner, TG_LO_SELVAL, 0x0) ; + divider_val = 24 ; + Fmax = FmaxBin ; + Fmin = FminBin ; + } + FminBin = 67000000UL ; + FmaxBin = 100000000UL ; + if (Tuner->TG_LO > FminBin && Tuner->TG_LO <= FmaxBin) { + status += MXL_ControlWrite(Tuner, TG_LO_DIVVAL, 0xC) ; + status += MXL_ControlWrite(Tuner, TG_LO_SELVAL, 0x2) ; + divider_val = 18 ; + Fmax = FmaxBin ; + Fmin = FminBin ; + } + FminBin = 100000000UL ; + FmaxBin = 150000000UL ; + if (Tuner->TG_LO > FminBin && Tuner->TG_LO <= FmaxBin) { + status += MXL_ControlWrite(Tuner, TG_LO_DIVVAL, 0x8) ; + status += MXL_ControlWrite(Tuner, TG_LO_SELVAL, 0x2) ; + divider_val = 12 ; + Fmax = FmaxBin ; + Fmin = FminBin ; + } + FminBin = 150000000UL ; + FmaxBin = 200000000UL ; + if (Tuner->TG_LO > FminBin && Tuner->TG_LO <= FmaxBin) { + status += MXL_ControlWrite(Tuner, TG_LO_DIVVAL, 0x0) ; + status += MXL_ControlWrite(Tuner, TG_LO_SELVAL, 0x2) ; + divider_val = 8 ; + Fmax = FmaxBin ; + Fmin = FminBin ; + } + FminBin = 200000000UL ; + FmaxBin = 300000000UL ; + if (Tuner->TG_LO > FminBin && Tuner->TG_LO <= FmaxBin) { + status += MXL_ControlWrite(Tuner, TG_LO_DIVVAL, 0x8) ; + status += MXL_ControlWrite(Tuner, TG_LO_SELVAL, 0x3) ; + divider_val = 6 ; + Fmax = FmaxBin ; + Fmin = FminBin ; + } + FminBin = 300000000UL ; + FmaxBin = 400000000UL ; + if (Tuner->TG_LO > FminBin && Tuner->TG_LO <= FmaxBin) { + status += MXL_ControlWrite(Tuner, TG_LO_DIVVAL, 0x0) ; + status += MXL_ControlWrite(Tuner, TG_LO_SELVAL, 0x3) ; + divider_val = 4 ; + Fmax = FmaxBin ; + Fmin = FminBin ; + } + FminBin = 400000000UL ; + FmaxBin = 600000000UL ; + if (Tuner->TG_LO > FminBin && Tuner->TG_LO <= FmaxBin) { + status += MXL_ControlWrite(Tuner, TG_LO_DIVVAL, 0x8) ; + status += MXL_ControlWrite(Tuner, TG_LO_SELVAL, 0x7) ; + divider_val = 3 ; + Fmax = FmaxBin ; + Fmin = FminBin ; + } + FminBin = 600000000UL ; + FmaxBin = 900000000UL ; + if (Tuner->TG_LO > FminBin && Tuner->TG_LO <= FmaxBin) { + status += MXL_ControlWrite(Tuner, TG_LO_DIVVAL, 0x0) ; + status += MXL_ControlWrite(Tuner, TG_LO_SELVAL, 0x7) ; + divider_val = 2 ; + Fmax = FmaxBin ; + Fmin = FminBin ; + } + + // TG_DIV_VAL + tg_divval = (Tuner->TG_LO*divider_val/100000) + *(MXL_Ceiling(Tuner->Fxtal,1000000) * 100) / (Tuner->Fxtal/1000) ; + status += MXL_ControlWrite(Tuner, TG_DIV_VAL, tg_divval) ; + + if (Tuner->TG_LO > 600000000UL) + status += MXL_ControlWrite(Tuner, TG_DIV_VAL, tg_divval + 1 ) ; + + Fmax = 1800000000UL ; + Fmin = 1200000000UL ; + + + + // to prevent overflow of 32 bit unsigned integer, use following equation. Edit for v2.6.4 + Fref_TG = (Tuner->Fxtal/1000)/ MXL_Ceiling(Tuner->Fxtal, 1000000) ; // Fref_TF = Fref_TG*1000 + + Fvco = (Tuner->TG_LO/10000) * divider_val * Fref_TG; //Fvco = Fvco/10 + + tg_lo = (((Fmax/10 - Fvco)/100)*32) / ((Fmax-Fmin)/1000)+8; + + //below equation is same as above but much harder to debug. + //tg_lo = ( ((Fmax/10000 * Xtal_Int)/100) - ((Tuner->TG_LO/10000)*divider_val*(Tuner->Fxtal/10000)/100) )*32/((Fmax-Fmin)/10000 * Xtal_Int/100) + 8 ; + + + status += MXL_ControlWrite(Tuner, TG_VCO_BIAS , tg_lo) ; + + + + //add for 2.6.5 + //Special setting for QAM + if(Tuner ->Mod_Type == MXL_QAM) + { + if(Tuner->RF_IN < 680000000) + status += MXL_ControlWrite(Tuner, RFSYN_CHP_GAIN, 3) ; + else + status += MXL_ControlWrite(Tuner, RFSYN_CHP_GAIN, 2) ; + } + + + //remove 20.48MHz setting for 2.6.10 + + // + // Off Chip Tracking Filter Control + // + if (Tuner->TF_Type == MXL_TF_OFF) // Tracking Filter Off State; turn off all the banks + { + status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 0) ; + status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; + + status += MXL_SetGPIO(Tuner, 3, 1) ; // turn off Bank 1 + status += MXL_SetGPIO(Tuner, 1, 1) ; // turn off Bank 2 + status += MXL_SetGPIO(Tuner, 4, 1) ; // turn off Bank 3 + } + + if (Tuner->TF_Type == MXL_TF_C) // Tracking Filter type C + { + status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 1) ; + status += MXL_ControlWrite(Tuner, DAC_DIN_A, 0) ; + + if (Tuner->RF_IN >= 43000000 && Tuner->RF_IN < 150000000) + { + + status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 0) ; // Bank4 Off + status += MXL_ControlWrite(Tuner, DAC_DIN_B, 0) ; + status += MXL_SetGPIO(Tuner, 3, 0) ; // Bank1 On + status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off + status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank3 Off + } + if (Tuner->RF_IN >= 150000000 && Tuner->RF_IN < 280000000) + { + status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 0) ; // Bank4 Off + status += MXL_ControlWrite(Tuner, DAC_DIN_B, 0) ; + status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank1 Off + status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank2 On + status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank3 Off + } + if (Tuner->RF_IN >= 280000000 && Tuner->RF_IN < 360000000) + { + status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 0) ; // Bank4 Off + status += MXL_ControlWrite(Tuner, DAC_DIN_B, 0) ; + status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank1 Off + status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank2 On + status += MXL_SetGPIO(Tuner, 4, 0) ; // Bank3 On + } + if (Tuner->RF_IN >= 360000000 && Tuner->RF_IN < 560000000) + { + status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 0) ; // Bank4 Off + status += MXL_ControlWrite(Tuner, DAC_DIN_B, 0) ; + status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank1 Off + status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off + status += MXL_SetGPIO(Tuner, 4, 0) ; // Bank3 On + } + if (Tuner->RF_IN >= 560000000 && Tuner->RF_IN < 580000000) + { + status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 1) ; // Bank4 On + status += MXL_ControlWrite(Tuner, DAC_DIN_B, 29) ; + status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank1 Off + status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off + status += MXL_SetGPIO(Tuner, 4, 0) ; // Bank3 On + } + if (Tuner->RF_IN >= 580000000 && Tuner->RF_IN < 630000000) + { + status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 1) ; // Bank4 On + status += MXL_ControlWrite(Tuner, DAC_DIN_B, 0) ; + status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank1 Off + status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off + status += MXL_SetGPIO(Tuner, 4, 0) ; // Bank3 On + } + if (Tuner->RF_IN >= 630000000 && Tuner->RF_IN < 700000000) + { + status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 1) ; // Bank4 On + status += MXL_ControlWrite(Tuner, DAC_DIN_B, 16) ; + status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank1 Off + status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off + status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank3 Off + } + if (Tuner->RF_IN >= 700000000 && Tuner->RF_IN < 760000000) + { + status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 1) ; // Bank4 On + status += MXL_ControlWrite(Tuner, DAC_DIN_B, 7) ; + status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank1 Off + status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off + status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank3 Off + } + if (Tuner->RF_IN >= 760000000 && Tuner->RF_IN <= 900000000) + { + status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 1) ; // Bank4 On + status += MXL_ControlWrite(Tuner, DAC_DIN_B, 0) ; + status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank1 Off + status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off + status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank3 Off + } + } + + if (Tuner->TF_Type == MXL_TF_C_H) // Tracking Filter type C-H for Hauppauge only + { + status += MXL_ControlWrite(Tuner, DAC_DIN_A, 0) ; + + if (Tuner->RF_IN >= 43000000 && Tuner->RF_IN < 150000000) + { + + status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 0) ; // Bank4 Off + status += MXL_SetGPIO(Tuner, 4, 0) ; // Bank1 On + status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank2 Off + status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank3 Off + } + if (Tuner->RF_IN >= 150000000 && Tuner->RF_IN < 280000000) + { + status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 0) ; // Bank4 Off + status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(Tuner, 3, 0) ; // Bank2 On + status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank3 Off + } + if (Tuner->RF_IN >= 280000000 && Tuner->RF_IN < 360000000) + { + status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 0) ; // Bank4 Off + status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(Tuner, 3, 0) ; // Bank2 On + status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank3 On + } + if (Tuner->RF_IN >= 360000000 && Tuner->RF_IN < 560000000) + { + status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 0) ; // Bank4 Off + status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank2 Off + status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank3 On + } + if (Tuner->RF_IN >= 560000000 && Tuner->RF_IN < 580000000) + { + status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 1) ; // Bank4 On + status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank2 Off + status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank3 On + } + if (Tuner->RF_IN >= 580000000 && Tuner->RF_IN < 630000000) + { + status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 1) ; // Bank4 On + status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank2 Off + status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank3 On + } + if (Tuner->RF_IN >= 630000000 && Tuner->RF_IN < 700000000) + { + status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 1) ; // Bank4 On + status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank2 Off + status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank3 Off + } + if (Tuner->RF_IN >= 700000000 && Tuner->RF_IN < 760000000) + { + status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 1) ; // Bank4 On + status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank2 Off + status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank3 Off + } + if (Tuner->RF_IN >= 760000000 && Tuner->RF_IN <= 900000000) + { + status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 1) ; // Bank4 On + status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank2 Off + status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank3 Off + } + } + + if (Tuner->TF_Type == MXL_TF_D) // Tracking Filter type D + { + status += MXL_ControlWrite(Tuner, DAC_DIN_B, 0) ; + + if (Tuner->RF_IN >= 43000000 && Tuner->RF_IN < 174000000) + { + + status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off + status += MXL_SetGPIO(Tuner, 4, 0) ; // Bank1 On + status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off + status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off + } + if (Tuner->RF_IN >= 174000000 && Tuner->RF_IN < 250000000) + { + status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off + status += MXL_SetGPIO(Tuner, 4, 0) ; // Bank1 On + status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank2 On + status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off + } + if (Tuner->RF_IN >= 250000000 && Tuner->RF_IN < 310000000) + { + status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off + status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank2 On + status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off + } + if (Tuner->RF_IN >= 310000000 && Tuner->RF_IN < 360000000) + { + status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off + status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank2 On + status += MXL_SetGPIO(Tuner, 3, 0) ; // Bank3 On + } + if (Tuner->RF_IN >= 360000000 && Tuner->RF_IN < 470000000) + { + status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off + status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off + status += MXL_SetGPIO(Tuner, 3, 0) ; // Bank3 On + } + if (Tuner->RF_IN >= 470000000 && Tuner->RF_IN < 640000000) + { + status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 1) ; // Bank4 On + status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off + status += MXL_SetGPIO(Tuner, 3, 0) ; // Bank3 On + } + if (Tuner->RF_IN >= 640000000 && Tuner->RF_IN <= 900000000) + { + status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 1) ; // Bank4 On + status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off + status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off + } + } + + + if (Tuner->TF_Type == MXL_TF_D_L) // Tracking Filter type D-L for Lumanate ONLY change for 2.6.3 + { + status += MXL_ControlWrite(Tuner, DAC_DIN_A, 0) ; + + if (Tuner->RF_IN >= 471000000 && (Tuner->RF_IN - 471000000)%6000000 != 0) // if UHF and terrestrial => Turn off Tracking Filter + { + // Turn off all the banks + status += MXL_SetGPIO(Tuner, 3, 1) ; + status += MXL_SetGPIO(Tuner, 1, 1) ; + status += MXL_SetGPIO(Tuner, 4, 1) ; + status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 0) ; + + status += MXL_ControlWrite(Tuner, AGC_IF, 10) ; + } + + else // if VHF or cable => Turn on Tracking Filter + { + if (Tuner->RF_IN >= 43000000 && Tuner->RF_IN < 140000000) + { + + status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 0) ; // Bank4 Off + status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 On + status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off + status += MXL_SetGPIO(Tuner, 3, 0) ; // Bank3 Off + } + if (Tuner->RF_IN >= 140000000 && Tuner->RF_IN < 240000000) + { + status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 0) ; // Bank4 Off + status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 On + status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank2 On + status += MXL_SetGPIO(Tuner, 3, 0) ; // Bank3 Off + } + if (Tuner->RF_IN >= 240000000 && Tuner->RF_IN < 340000000) + { + status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 0) ; // Bank4 Off + status += MXL_SetGPIO(Tuner, 4, 0) ; // Bank1 Off + status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 On + status += MXL_SetGPIO(Tuner, 3, 0) ; // Bank3 Off + } + if (Tuner->RF_IN >= 340000000 && Tuner->RF_IN < 430000000) + { + status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 0) ; // Bank4 Off + status += MXL_SetGPIO(Tuner, 4, 0) ; // Bank1 Off + status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank2 On + status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 On + } + if (Tuner->RF_IN >= 430000000 && Tuner->RF_IN < 470000000) + { + status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 1) ; // Bank4 Off + status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank2 Off + status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 On + } + if (Tuner->RF_IN >= 470000000 && Tuner->RF_IN < 570000000) + { + status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 1) ; // Bank4 On + status += MXL_SetGPIO(Tuner, 4, 0) ; // Bank1 Off + status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank2 Off + status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 On + } + if (Tuner->RF_IN >= 570000000 && Tuner->RF_IN < 620000000) + { + status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 0) ; // Bank4 On + status += MXL_SetGPIO(Tuner, 4, 0) ; // Bank1 Off + status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off + status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Offq + } + if (Tuner->RF_IN >= 620000000 && Tuner->RF_IN < 760000000) + { + status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 1) ; // Bank4 On + status += MXL_SetGPIO(Tuner, 4, 0) ; // Bank1 Off + status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off + status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off + } + if (Tuner->RF_IN >= 760000000 && Tuner->RF_IN <= 900000000) + { + status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 1) ; // Bank4 On + status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off + status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off + } + } + } + + if (Tuner->TF_Type == MXL_TF_E) // Tracking Filter type E + { + status += MXL_ControlWrite(Tuner, DAC_DIN_B, 0) ; + + if (Tuner->RF_IN >= 43000000 && Tuner->RF_IN < 174000000) + { + + status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off + status += MXL_SetGPIO(Tuner, 4, 0) ; // Bank1 On + status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off + status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off + } + if (Tuner->RF_IN >= 174000000 && Tuner->RF_IN < 250000000) + { + status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off + status += MXL_SetGPIO(Tuner, 4, 0) ; // Bank1 On + status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank2 On + status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off + } + if (Tuner->RF_IN >= 250000000 && Tuner->RF_IN < 310000000) + { + status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off + status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank2 On + status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off + } + if (Tuner->RF_IN >= 310000000 && Tuner->RF_IN < 360000000) + { + status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off + status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank2 On + status += MXL_SetGPIO(Tuner, 3, 0) ; // Bank3 On + } + if (Tuner->RF_IN >= 360000000 && Tuner->RF_IN < 470000000) + { + status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off + status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off + status += MXL_SetGPIO(Tuner, 3, 0) ; // Bank3 On + } + if (Tuner->RF_IN >= 470000000 && Tuner->RF_IN < 640000000) + { + status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 1) ; // Bank4 On + status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off + status += MXL_SetGPIO(Tuner, 3, 0) ; // Bank3 On + } + if (Tuner->RF_IN >= 640000000 && Tuner->RF_IN <= 900000000) + { + status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 1) ; // Bank4 On + status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off + status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off + } + } + + if (Tuner->TF_Type == MXL_TF_F) // Tracking Filter type F + { + status += MXL_ControlWrite(Tuner, DAC_DIN_B, 0) ; + + if (Tuner->RF_IN >= 43000000 && Tuner->RF_IN < 160000000) + { + + status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off + status += MXL_SetGPIO(Tuner, 4, 0) ; // Bank1 On + status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off + status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off + } + if (Tuner->RF_IN >= 160000000 && Tuner->RF_IN < 210000000) + { + status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off + status += MXL_SetGPIO(Tuner, 4, 0) ; // Bank1 On + status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank2 On + status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off + } + if (Tuner->RF_IN >= 210000000 && Tuner->RF_IN < 300000000) + { + status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off + status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank2 On + status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off + } + if (Tuner->RF_IN >= 300000000 && Tuner->RF_IN < 390000000) + { + status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off + status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank2 On + status += MXL_SetGPIO(Tuner, 3, 0) ; // Bank3 On + } + if (Tuner->RF_IN >= 390000000 && Tuner->RF_IN < 515000000) + { + status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off + status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off + status += MXL_SetGPIO(Tuner, 3, 0) ; // Bank3 On + } + if (Tuner->RF_IN >= 515000000 && Tuner->RF_IN < 650000000) + { + status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 1) ; // Bank4 On + status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off + status += MXL_SetGPIO(Tuner, 3, 0) ; // Bank3 On + } + if (Tuner->RF_IN >= 650000000 && Tuner->RF_IN <= 900000000) + { + status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 1) ; // Bank4 On + status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off + status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off + } + } + + if (Tuner->TF_Type == MXL_TF_E_2) // Tracking Filter type E_2 + { + status += MXL_ControlWrite(Tuner, DAC_DIN_B, 0) ; + + if (Tuner->RF_IN >= 43000000 && Tuner->RF_IN < 174000000) + { + + status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off + status += MXL_SetGPIO(Tuner, 4, 0) ; // Bank1 On + status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off + status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off + } + if (Tuner->RF_IN >= 174000000 && Tuner->RF_IN < 250000000) + { + status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off + status += MXL_SetGPIO(Tuner, 4, 0) ; // Bank1 On + status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank2 On + status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off + } + if (Tuner->RF_IN >= 250000000 && Tuner->RF_IN < 350000000) + { + status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off + status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank2 On + status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off + } + if (Tuner->RF_IN >= 350000000 && Tuner->RF_IN < 400000000) + { + status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off + status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank2 On + status += MXL_SetGPIO(Tuner, 3, 0) ; // Bank3 On + } + if (Tuner->RF_IN >= 400000000 && Tuner->RF_IN < 570000000) + { + status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off + status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off + status += MXL_SetGPIO(Tuner, 3, 0) ; // Bank3 On + } + if (Tuner->RF_IN >= 570000000 && Tuner->RF_IN < 770000000) + { + status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 1) ; // Bank4 On + status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off + status += MXL_SetGPIO(Tuner, 3, 0) ; // Bank3 On + } + if (Tuner->RF_IN >= 770000000 && Tuner->RF_IN <= 900000000) + { + status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 1) ; // Bank4 On + status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off + status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off + } + } + + if (Tuner->TF_Type == MXL_TF_G) // Tracking Filter type G add for v2.6.8 + { + status += MXL_ControlWrite(Tuner, DAC_DIN_B, 0) ; + + if (Tuner->RF_IN >= 50000000 && Tuner->RF_IN < 190000000) + { + + status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off + status += MXL_SetGPIO(Tuner, 4, 0) ; // Bank1 On + status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off + status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off + } + if (Tuner->RF_IN >= 190000000 && Tuner->RF_IN < 280000000) + { + status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off + status += MXL_SetGPIO(Tuner, 4, 0) ; // Bank1 On + status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank2 On + status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off + } + if (Tuner->RF_IN >= 280000000 && Tuner->RF_IN < 350000000) + { + status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off + status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank2 On + status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off + } + if (Tuner->RF_IN >= 350000000 && Tuner->RF_IN < 400000000) + { + status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off + status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank2 On + status += MXL_SetGPIO(Tuner, 3, 0) ; // Bank3 On + } + if (Tuner->RF_IN >= 400000000 && Tuner->RF_IN < 470000000) //modified for 2.6.11 + { + status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 1) ; // Bank4 On + status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 On + status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank2 Off + status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off + } + if (Tuner->RF_IN >= 470000000 && Tuner->RF_IN < 640000000) + { + status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off + status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off + status += MXL_SetGPIO(Tuner, 3, 0) ; // Bank3 On + } + if (Tuner->RF_IN >= 640000000 && Tuner->RF_IN < 820000000) + { + status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 1) ; // Bank4 On + status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off + status += MXL_SetGPIO(Tuner, 3, 0) ; // Bank3 On + } + if (Tuner->RF_IN >= 820000000 && Tuner->RF_IN <= 900000000) + { + status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 1) ; // Bank4 On + status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off + status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off + } + } + + if (Tuner->TF_Type == MXL_TF_E_NA) // Tracking Filter type E-NA for Empia ONLY change for 2.6.8 + { + status += MXL_ControlWrite(Tuner, DAC_DIN_B, 0) ; + + if (Tuner->RF_IN >= 471000000 && (Tuner->RF_IN - 471000000)%6000000 != 0) //if UHF and terrestrial=> Turn off Tracking Filter + { + // Turn off all the banks + status += MXL_SetGPIO(Tuner, 3, 1) ; + status += MXL_SetGPIO(Tuner, 1, 1) ; + status += MXL_SetGPIO(Tuner, 4, 1) ; + status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; + + //2.6.12 + //Turn on RSSI + status += MXL_ControlWrite(Tuner, SEQ_EXTSYNTHCALIF, 1) ; + status += MXL_ControlWrite(Tuner, SEQ_EXTDCCAL, 1) ; + status += MXL_ControlWrite(Tuner, AGC_EN_RSSI, 1) ; + status += MXL_ControlWrite(Tuner, RFA_ENCLKRFAGC, 1) ; + + // RSSI reference point + status += MXL_ControlWrite(Tuner, RFA_RSSI_REFH, 5) ; + status += MXL_ControlWrite(Tuner, RFA_RSSI_REF, 3) ; + status += MXL_ControlWrite(Tuner, RFA_RSSI_REFL, 2) ; + + + //status += MXL_ControlWrite(Tuner, AGC_IF, 10) ; //doesn't matter since RSSI is turn on + + //following parameter is from analog OTA mode, can be change to seek better performance + status += MXL_ControlWrite(Tuner, RFSYN_CHP_GAIN, 3) ; + } + + else //if VHF or Cable => Turn on Tracking Filter + { + //2.6.12 + //Turn off RSSI + status += MXL_ControlWrite(Tuner, AGC_EN_RSSI, 0) ; + + //change back from above condition + status += MXL_ControlWrite(Tuner, RFSYN_CHP_GAIN, 5) ; + + + if (Tuner->RF_IN >= 43000000 && Tuner->RF_IN < 174000000) + { + + status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off + status += MXL_SetGPIO(Tuner, 4, 0) ; // Bank1 On + status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off + status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off + } + if (Tuner->RF_IN >= 174000000 && Tuner->RF_IN < 250000000) + { + status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off + status += MXL_SetGPIO(Tuner, 4, 0) ; // Bank1 On + status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank2 On + status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off + } + if (Tuner->RF_IN >= 250000000 && Tuner->RF_IN < 350000000) + { + status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off + status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank2 On + status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off + } + if (Tuner->RF_IN >= 350000000 && Tuner->RF_IN < 400000000) + { + status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off + status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank2 On + status += MXL_SetGPIO(Tuner, 3, 0) ; // Bank3 On + } + if (Tuner->RF_IN >= 400000000 && Tuner->RF_IN < 570000000) + { + status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off + status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off + status += MXL_SetGPIO(Tuner, 3, 0) ; // Bank3 On + } + if (Tuner->RF_IN >= 570000000 && Tuner->RF_IN < 770000000) + { + status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 1) ; // Bank4 On + status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off + status += MXL_SetGPIO(Tuner, 3, 0) ; // Bank3 On + } + if (Tuner->RF_IN >= 770000000 && Tuner->RF_IN <= 900000000) + { + status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 1) ; // Bank4 On + status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off + status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off + } + } + } + return status ; +} + +_u16 MXL_SetGPIO(Tuner_struct *Tuner, _u8 GPIO_Num, _u8 GPIO_Val) +{ + _u16 status = 0 ; + + if (GPIO_Num == 1) + status += MXL_ControlWrite(Tuner, GPIO_1B, GPIO_Val ? 0 : 1) ; + // GPIO2 is not available + if (GPIO_Num == 3) + { + if (GPIO_Val == 1) { + status += MXL_ControlWrite(Tuner, GPIO_3, 0) ; + status += MXL_ControlWrite(Tuner, GPIO_3B, 0) ; + } + if (GPIO_Val == 0) { + status += MXL_ControlWrite(Tuner, GPIO_3, 1) ; + status += MXL_ControlWrite(Tuner, GPIO_3B, 1) ; + } + if (GPIO_Val == 3) { // tri-state + status += MXL_ControlWrite(Tuner, GPIO_3, 0) ; + status += MXL_ControlWrite(Tuner, GPIO_3B, 1) ; + } + } + if (GPIO_Num == 4) + { + if (GPIO_Val == 1) { + status += MXL_ControlWrite(Tuner, GPIO_4, 0) ; + status += MXL_ControlWrite(Tuner, GPIO_4B, 0) ; + } + if (GPIO_Val == 0) { + status += MXL_ControlWrite(Tuner, GPIO_4, 1) ; + status += MXL_ControlWrite(Tuner, GPIO_4B, 1) ; + } + if (GPIO_Val == 3) { // tri-state + status += MXL_ControlWrite(Tuner, GPIO_4, 0) ; + status += MXL_ControlWrite(Tuner, GPIO_4B, 1) ; + } + } + + return status ; +} + +/////////////////////////////////////////////////////////////////////////////// +// // +// Function: MXL_ControlWrite // +// // +// Description: Update control name value // +// // +// Globals: // +// NONE // +// // +// Functions used: // +// MXL_ControlWrite( Tuner, controlName, value, Group ) // +// // +// Inputs: // +// Tuner : Tuner structure // +// ControlName : Control name to be updated // +// value : Value to be written // +// // +// Outputs: // +// Tuner : Tuner structure defined at higher level // +// // +// Return: // +// 0 : Successful write // +// >0 : Value exceed maximum allowed for control number // +// // +/////////////////////////////////////////////////////////////////////////////// +_u16 MXL_ControlWrite(Tuner_struct *Tuner, _u16 ControlNum, _u32 value) +{ + _u16 status = 0 ; + // Will write ALL Matching Control Name + status += MXL_ControlWrite_Group( Tuner, ControlNum, value, 1 ) ; // Write Matching INIT Control + status += MXL_ControlWrite_Group( Tuner, ControlNum, value, 2 ) ; // Write Matching CH Control +#ifdef _MXL_INTERNAL + status += MXL_ControlWrite_Group( Tuner, ControlNum, value, 3 ) ; // Write Matching MXL Control +#endif + + return status ; +} + +/////////////////////////////////////////////////////////////////////////////// +// // +// Function: MXL_ControlWrite // +// // +// Description: Update control name value // +// // +// Globals: // +// NONE // +// // +// Functions used: // +// strcmp // +// // +// Inputs: // +// Tuner_struct: structure defined at higher level // +// ControlName : Control Name // +// value : Value Assigned to Control Name // +// controlGroup : Control Register Group // +// // +// Outputs: // +// NONE // +// // +// Return: // +// 0 : Successful write // +// 1 : Value exceed maximum allowed for control name // +// 2 : Control name not found // +// // +/////////////////////////////////////////////////////////////////////////////// +_u16 MXL_ControlWrite_Group(Tuner_struct *Tuner, _u16 controlNum, _u32 value, _u16 controlGroup) +{ + _u16 i, j, k ; + _u32 highLimit ; + _u32 ctrlVal ; + + if( controlGroup == 1) // Initial Control + { + for (i=0; iInit_Ctrl_Num ; i++) + { + if ( controlNum == Tuner->Init_Ctrl[i].Ctrl_Num ) + { // find the control Name + highLimit = 1 << Tuner->Init_Ctrl[i].size ; + if ( value < highLimit) + { + for( j=0; jInit_Ctrl[i].size; j++) + { + Tuner->Init_Ctrl[i].val[j] = (_u8)((value >> j) & 0x01) ; + // change the register map accordingly + MXL_RegWriteBit( Tuner, (_u8)(Tuner->Init_Ctrl[i].addr[j]), + (_u8)(Tuner->Init_Ctrl[i].bit[j]), + (_u8)((value>>j) & 0x01) ) ; + } + ctrlVal = 0 ; + for(k=0; kInit_Ctrl[i].size; k++) + { + ctrlVal += Tuner->Init_Ctrl[i].val[k] * (1 << k) ; + } + } + else + { + return -1 ; + } + } + } + } + if ( controlGroup == 2) // Chan change Control + { + for (i=0; iCH_Ctrl_Num; i++) + { + if ( controlNum == Tuner->CH_Ctrl[i].Ctrl_Num ) + { // find the control Name + highLimit = 1 << Tuner->CH_Ctrl[i].size ; + if ( value < highLimit) + { + for( j=0; jCH_Ctrl[i].size; j++) + { + Tuner->CH_Ctrl[i].val[j] = (_u8)((value >> j) & 0x01) ; + // change the register map accordingly + MXL_RegWriteBit( Tuner, (_u8)(Tuner->CH_Ctrl[i].addr[j]), + (_u8)(Tuner->CH_Ctrl[i].bit[j]), + (_u8)((value>>j) & 0x01) ) ; + } + ctrlVal = 0 ; + for(k=0; kCH_Ctrl[i].size; k++) + { + ctrlVal += Tuner->CH_Ctrl[i].val[k] * (1 << k) ; + } + } + else + { + return -1 ; + } + } + } + } +#ifdef _MXL_INTERNAL + if ( controlGroup == 3) // Maxlinear Control + { + for (i=0; iMXL_Ctrl_Num; i++) + { + if ( controlNum == Tuner->MXL_Ctrl[i].Ctrl_Num ) + { // find the control Name + highLimit = (1 << Tuner->MXL_Ctrl[i].size) ; + if ( value < highLimit) + { + for( j=0; jMXL_Ctrl[i].size; j++) + { + Tuner->MXL_Ctrl[i].val[j] = (_u8)((value >> j) & 0x01) ; + // change the register map accordingly + MXL_RegWriteBit( Tuner, (_u8)(Tuner->MXL_Ctrl[i].addr[j]), + (_u8)(Tuner->MXL_Ctrl[i].bit[j]), + (_u8)((value>>j) & 0x01) ) ; + } + ctrlVal = 0 ; + for(k=0; kMXL_Ctrl[i].size; k++) + { + ctrlVal += Tuner->MXL_Ctrl[i].val[k] * (1 << k) ; + } + } + else + { + return -1 ; + } + } + } + } +#endif + return 0 ; // successful return +} + +/////////////////////////////////////////////////////////////////////////////// +// // +// Function: MXL_RegWrite // +// // +// Description: Update tuner register value // +// // +// Globals: // +// NONE // +// // +// Functions used: // +// NONE // +// // +// Inputs: // +// Tuner_struct: structure defined at higher level // +// RegNum : Register address to be assigned a value // +// RegVal : Register value to write // +// // +// Outputs: // +// NONE // +// // +// Return: // +// 0 : Successful write // +// -1 : Invalid Register Address // +// // +/////////////////////////////////////////////////////////////////////////////// +_u16 MXL_RegWrite(Tuner_struct *Tuner, _u8 RegNum, _u8 RegVal) +{ + int i ; + + for (i=0; i<104; i++) + { + if (RegNum == Tuner->TunerRegs[i].Reg_Num ) + { + Tuner->TunerRegs[i].Reg_Val = RegVal ; + return 0 ; + } + } + + return 1 ; +} + +/////////////////////////////////////////////////////////////////////////////// +// // +// Function: MXL_RegRead // +// // +// Description: Retrieve tuner register value // +// // +// Globals: // +// NONE // +// // +// Functions used: // +// NONE // +// // +// Inputs: // +// Tuner_struct: structure defined at higher level // +// RegNum : Register address to be assigned a value // +// // +// Outputs: // +// RegVal : Retrieved register value // +// // +// Return: // +// 0 : Successful read // +// -1 : Invalid Register Address // +// // +/////////////////////////////////////////////////////////////////////////////// +_u16 MXL_RegRead(Tuner_struct *Tuner, _u8 RegNum, _u8 *RegVal) +{ + int i ; + + for (i=0; i<104; i++) + { + if (RegNum == Tuner->TunerRegs[i].Reg_Num ) + { + *RegVal = (_u8)(Tuner->TunerRegs[i].Reg_Val) ; + return 0 ; + } + } + + return 1 ; +} + +/////////////////////////////////////////////////////////////////////////////// +// // +// Function: MXL_ControlRead // +// // +// Description: Retrieve the control value based on the control name // +// // +// Globals: // +// NONE // +// // +// Inputs: // +// Tuner_struct : structure defined at higher level // +// ControlName : Control Name // +// // +// Outputs: // +// value : returned control value // +// // +// Return: // +// 0 : Successful read // +// -1 : Invalid control name // +// // +/////////////////////////////////////////////////////////////////////////////// +_u16 MXL_ControlRead(Tuner_struct *Tuner, _u16 controlNum, _u32 * value) +{ + _u32 ctrlVal ; + _u16 i, k ; + + for (i=0; iInit_Ctrl_Num ; i++) + { + if ( controlNum == Tuner->Init_Ctrl[i].Ctrl_Num ) + { + ctrlVal = 0 ; + for(k=0; kInit_Ctrl[i].size; k++) + ctrlVal += Tuner->Init_Ctrl[i].val[k] * (1 << k) ; + *value = ctrlVal ; + return 0 ; + } + } + for (i=0; iCH_Ctrl_Num ; i++) + { + if ( controlNum == Tuner->CH_Ctrl[i].Ctrl_Num ) + { + ctrlVal = 0 ; + for(k=0; kCH_Ctrl[i].size; k++) + ctrlVal += Tuner->CH_Ctrl[i].val[k] * (1 << k) ; + *value = ctrlVal ; + return 0 ; + } + } + +#ifdef _MXL_INTERNAL + for (i=0; iMXL_Ctrl_Num ; i++) + { + if ( controlNum == Tuner->MXL_Ctrl[i].Ctrl_Num ) + { + ctrlVal = 0 ; + for(k=0; kMXL_Ctrl[i].size; k++) + ctrlVal += Tuner->MXL_Ctrl[i].val[k] * (1<Init_Ctrl_Num ; i++) + { + if ( controlNum == Tuner->Init_Ctrl[i].Ctrl_Num ) + { + Count = 1 ; + RegNum[0] = (_u8)(Tuner->Init_Ctrl[i].addr[0]) ; + + for(k=1; kInit_Ctrl[i].size; k++) + { + for (j= 0; jInit_Ctrl[i].addr[k] != RegNum[j]) + { + Count ++ ; + RegNum[Count-1] = (_u8)(Tuner->Init_Ctrl[i].addr[k]) ; + } + } + + } + *count = Count ; + return 0 ; + } + } + for (i=0; iCH_Ctrl_Num ; i++) + { + if ( controlNum == Tuner->CH_Ctrl[i].Ctrl_Num ) + { + Count = 1 ; + RegNum[0] = (_u8)(Tuner->CH_Ctrl[i].addr[0]) ; + + for(k=1; kCH_Ctrl[i].size; k++) + { + for (j= 0; jCH_Ctrl[i].addr[k] != RegNum[j]) + { + Count ++ ; + RegNum[Count-1] = (_u8)(Tuner->CH_Ctrl[i].addr[k]) ; + } + } + } + *count = Count ; + return 0 ; + } + } +#ifdef _MXL_INTERNAL + for (i=0; iMXL_Ctrl_Num ; i++) + { + if ( controlNum == Tuner->MXL_Ctrl[i].Ctrl_Num ) + { + Count = 1 ; + RegNum[0] = (_u8)(Tuner->MXL_Ctrl[i].addr[0]) ; + + for(k=1; kMXL_Ctrl[i].size; k++) + { + for (j= 0; jMXL_Ctrl[i].addr[k] != RegNum[j]) + { + Count ++ ; + RegNum[Count-1] = (_u8)Tuner->MXL_Ctrl[i].addr[k] ; + } + } + } + *count = Count ; + return 0 ; + } + } +#endif + *count = 0 ; + return 1 ; +} + +/////////////////////////////////////////////////////////////////////////////// +// // +// Function: MXL_RegWriteBit // +// // +// Description: Write a register for specified register address, // +// register bit and register bit value // +// // +// Globals: // +// NONE // +// // +// Inputs: // +// Tuner_struct : structure defined at higher level // +// address : register address // +// bit : register bit number // +// bitVal : register bit value // +// // +// Outputs: // +// NONE // +// // +// Return: // +// NONE // +// // +/////////////////////////////////////////////////////////////////////////////// + +void MXL_RegWriteBit(Tuner_struct *Tuner, _u8 address, _u8 bit, _u8 bitVal) +{ + int i ; + + // Declare Local Constants + const _u8 AND_MAP[8] = { + 0xFE, 0xFD, 0xFB, 0xF7, + 0xEF, 0xDF, 0xBF, 0x7F } ; + + const _u8 OR_MAP[8] = { + 0x01, 0x02, 0x04, 0x08, + 0x10, 0x20, 0x40, 0x80 } ; + + for(i=0; iTunerRegs_Num; i++) { + if ( Tuner->TunerRegs[i].Reg_Num == address ) { + if (bitVal) + Tuner->TunerRegs[i].Reg_Val |= OR_MAP[bit] ; + else + Tuner->TunerRegs[i].Reg_Val &= AND_MAP[bit] ; + break ; + } + } +} ; + + +/////////////////////////////////////////////////////////////////////////////// +// // +// Function: MXL_Ceiling // +// // +// Description: Complete to closest increment of resolution // +// // +// Globals: // +// NONE // +// // +// Functions used: // +// NONE // +// // +// Inputs: // +// value : Input number to compute // +// resolution : Increment step // +// // +// Outputs: // +// NONE // +// // +// Return: // +// Computed value // +// // +/////////////////////////////////////////////////////////////////////////////// +_u32 MXL_Ceiling( _u32 value, _u32 resolution ) +{ + return (value/resolution + (value%resolution > 0 ? 1 : 0)) ; +}; + +// +// Retrieve the Initialzation Registers +// +_u16 MXL_GetInitRegister(Tuner_struct *Tuner, _u8 * RegNum, _u8 *RegVal, int *count) +{ + _u16 status = 0; + int i ; + + _u8 RegAddr[] = {11, 12, 13, 22, 32, 43, 44, 53, 56, 59, 73, + 76, 77, 91, 134, 135, 137, 147, + 156, 166, 167, 168, 25 } ; + *count = sizeof(RegAddr) / sizeof(_u8) ; + + status += MXL_BlockInit(Tuner) ; + + for (i=0 ; i< *count; i++) + { + RegNum[i] = RegAddr[i] ; + status += MXL_RegRead(Tuner, RegNum[i], &RegVal[i]) ; + } + + return status ; +} + +_u16 MXL_GetCHRegister(Tuner_struct *Tuner, _u8 * RegNum, _u8 *RegVal, int *count) +{ + _u16 status = 0; + int i ; + +//add 77, 166, 167, 168 register for 2.6.12 +#ifdef _MXL_PRODUCTION + _u8 RegAddr[] = {14, 15, 16, 17, 22, 43, 65, 68, 69, 70, 73, 92, 93, 106, + 107, 108, 109, 110, 111, 112, 136, 138, 149, 77, 166, 167, 168 } ; +#else + _u8 RegAddr[] = {14, 15, 16, 17, 22, 43, 68, 69, 70, 73, 92, 93, 106, + 107, 108, 109, 110, 111, 112, 136, 138, 149, 77, 166, 167, 168 } ; + //_u8 RegAddr[171]; + //for (i=0; i<=170; i++) + // RegAddr[i] = i; +#endif + + *count = sizeof(RegAddr) / sizeof(_u8) ; + + for (i=0 ; i< *count; i++) + { + RegNum[i] = RegAddr[i] ; + status += MXL_RegRead(Tuner, RegNum[i], &RegVal[i]) ; + } + + return status ; + +} + +_u16 MXL_GetCHRegister_ZeroIF(Tuner_struct *Tuner, _u8 * RegNum, _u8 *RegVal, int *count) +{ + _u16 status = 0 ; + int i ; + + _u8 RegAddr[] = {43, 136} ; + + *count = sizeof(RegAddr) / sizeof(_u8) ; + + for (i=0; i<*count; i++) + { + RegNum[i] = RegAddr[i] ; + status += MXL_RegRead(Tuner, RegNum[i], &RegVal[i]) ; + } + return status ; + +} + +_u16 MXL_GetCHRegister_LowIF(Tuner_struct *Tuner, _u8 * RegNum, _u8 *RegVal, int *count) +{ + _u16 status = 0 ; + int i ; + + _u8 RegAddr[] = {138} ; + + *count = sizeof(RegAddr) / sizeof(_u8) ; + + for (i=0; i<*count; i++) + { + RegNum[i] = RegAddr[i] ; + status += MXL_RegRead(Tuner, RegNum[i], &RegVal[i]) ; + } + return status ; + +} + +_u16 MXL_GetMasterControl(_u8 *MasterReg, int state) +{ + if (state == 1) // Load_Start + *MasterReg = 0xF3 ; + if (state == 2) // Power_Down + *MasterReg = 0x41 ; + if (state == 3) // Synth_Reset + *MasterReg = 0xB1 ; + if (state == 4) // Seq_Off + *MasterReg = 0xF1 ; + + return 0 ; +} + +#ifdef _MXL_PRODUCTION +_u16 MXL_VCORange_Test(Tuner_struct *Tuner, int VCO_Range) +{ + _u16 status = 0 ; + + if (VCO_Range == 1) { + status += MXL_ControlWrite(Tuner, RFSYN_EN_DIV, 1) ; + status += MXL_ControlWrite(Tuner, RFSYN_EN_OUTMUX, 0 ) ; + status += MXL_ControlWrite(Tuner, RFSYN_SEL_DIVM, 0 ) ; + status += MXL_ControlWrite(Tuner, RFSYN_DIVM, 1 ) ; + status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_OUT, 1 ) ; + status += MXL_ControlWrite(Tuner, RFSYN_RF_DIV_BIAS, 1 ) ; + status += MXL_ControlWrite(Tuner, DN_SEL_FREQ, 0 ) ; + if (Tuner->Mode == 0 && Tuner->IF_Mode == 1) // Analog Low IF Mode + { + status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 1 ) ; + status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 8 ) ; + status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 56 ) ; + status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_RF, 180224 ) ; + } + if (Tuner->Mode == 0 && Tuner->IF_Mode == 0) // Analog Zero IF Mode + { + status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 1 ) ; + status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 8 ) ; + status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 56 ) ; + status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_RF, 222822 ) ; + } + if (Tuner->Mode == 1) // Digital Mode + { + status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 1 ) ; + status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 8 ) ; + status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 56 ) ; + status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_RF, 229376 ) ; + } + } + + if (VCO_Range == 2) { + status += MXL_ControlWrite(Tuner, RFSYN_EN_DIV, 1) ; + status += MXL_ControlWrite(Tuner, RFSYN_EN_OUTMUX, 0 ) ; + status += MXL_ControlWrite(Tuner, RFSYN_SEL_DIVM, 0 ) ; + status += MXL_ControlWrite(Tuner, RFSYN_DIVM, 1 ) ; + status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_OUT, 1 ) ; + status += MXL_ControlWrite(Tuner, RFSYN_RF_DIV_BIAS, 1 ) ; + status += MXL_ControlWrite(Tuner, DN_SEL_FREQ, 0 ) ; + status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 1 ) ; + status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 40 ) ; + status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 41 ) ; + if (Tuner->Mode == 0 && Tuner->IF_Mode == 1) // Analog Low IF Mode + { + status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 1 ) ; + status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 40 ) ; + status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 42 ) ; + status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_RF, 206438 ) ; + } + if (Tuner->Mode == 0 && Tuner->IF_Mode == 0) // Analog Zero IF Mode + { + status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 1 ) ; + status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 40 ) ; + status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 42 ) ; + status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_RF, 206438 ) ; + } + if (Tuner->Mode == 1) // Digital Mode + { + status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 1 ) ; + status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 40 ) ; + status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 41 ) ; + status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_RF, 16384 ) ; + } + } + + if (VCO_Range == 3) { + status += MXL_ControlWrite(Tuner, RFSYN_EN_DIV, 1) ; + status += MXL_ControlWrite(Tuner, RFSYN_EN_OUTMUX, 0 ) ; + status += MXL_ControlWrite(Tuner, RFSYN_SEL_DIVM, 0 ) ; + status += MXL_ControlWrite(Tuner, RFSYN_DIVM, 1 ) ; + status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_OUT, 1 ) ; + status += MXL_ControlWrite(Tuner, RFSYN_RF_DIV_BIAS, 1 ) ; + status += MXL_ControlWrite(Tuner, DN_SEL_FREQ, 0 ) ; + status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 0 ) ; + status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 8 ) ; + status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 42 ) ; + if (Tuner->Mode == 0 && Tuner->IF_Mode == 1) // Analog Low IF Mode + { + status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 0 ) ; + status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 8 ) ; + status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 44 ) ; + status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_RF, 173670 ) ; + } + if (Tuner->Mode == 0 && Tuner->IF_Mode == 0) // Analog Zero IF Mode + { + status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 0 ) ; + status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 8 ) ; + status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 44 ) ; + status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_RF, 173670 ) ; + } + if (Tuner->Mode == 1) // Digital Mode + { + status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 0 ) ; + status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 8 ) ; + status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 42 ) ; + status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_RF, 245760 ) ; + } + } + + if (VCO_Range == 4) { + status += MXL_ControlWrite(Tuner, RFSYN_EN_DIV, 1) ; + status += MXL_ControlWrite(Tuner, RFSYN_EN_OUTMUX, 0 ) ; + status += MXL_ControlWrite(Tuner, RFSYN_SEL_DIVM, 0 ) ; + status += MXL_ControlWrite(Tuner, RFSYN_DIVM, 1 ) ; + status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_OUT, 1 ) ; + status += MXL_ControlWrite(Tuner, RFSYN_RF_DIV_BIAS, 1 ) ; + status += MXL_ControlWrite(Tuner, DN_SEL_FREQ, 0 ) ; + status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 0 ) ; + status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 40 ) ; + status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 27 ) ; + if (Tuner->Mode == 0 && Tuner->IF_Mode == 1) // Analog Low IF Mode + { + status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 0 ) ; + status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 40 ) ; + status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 27 ) ; + status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_RF, 206438 ) ; + } + if (Tuner->Mode == 0 && Tuner->IF_Mode == 0) // Analog Zero IF Mode + { + status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 0 ) ; + status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 40 ) ; + status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 27 ) ; + status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_RF, 206438 ) ; + } + if (Tuner->Mode == 1) // Digital Mode + { + status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 0 ) ; + status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 40 ) ; + status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 27 ) ; + status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_RF, 212992 ) ; + } + } + + return status ; +} + +_u16 MXL_Hystersis_Test(Tuner_struct *Tuner, int Hystersis) +{ + _u16 status = 0 ; + + if (Hystersis == 1) + status += MXL_ControlWrite(Tuner, DN_BYPASS_AGC_I2C, 1) ; + + return status ; +} +#endif + + + + + + + + + + + + + + + diff --git a/linux/drivers/media/common/tuners/mxl5005s.h b/linux/drivers/media/common/tuners/mxl5005s.h new file mode 100644 index 000000000..8542fc10a --- /dev/null +++ b/linux/drivers/media/common/tuners/mxl5005s.h @@ -0,0 +1,718 @@ +/* + * For the Realtek RTL chip RTL2831U + * Realtek Release Date: 2008-03-14, ver 080314 + * Realtek version RTL2831 Linux driver version 080314 + * ver 080314 + * + * for linux kernel version 2.6.21.4 - 2.6.22-14 + * support MXL5005s and MT2060 tuners (support tuner auto-detecting) + * support two IR types -- RC5 and NEC + * + * Known boards with Realtek RTL chip RTL2821U + * Freecom USB stick 14aa:0160 (version 4) + * Conceptronic CTVDIGRCU + * + * Copyright (c) 2008 Realtek + * Copyright (c) 2008 Jan Hoogenraad, Barnaby Shearer, Andy Hasper + * This code is placed under the terms of the GNU General Public License + * + * Released by Realtek under GPLv2. + * Thanks to Realtek for a lot of support we received ! + * + * Revision: 080314 - original version + */ + + +#ifndef __TUNER_MXL5005S_H +#define __TUNER_MXL5005S_H + + + +// The following context is source code provided by MaxLinear. + + +// MaxLinear source code - Common.h + + + +//#pragma once + +typedef unsigned char _u8; // At least 1 Byte +typedef unsigned short _u16; // At least 2 Bytes +typedef signed short _s16; +typedef unsigned long _u32; // At least 4 Bytes +typedef void * HANDLE; // Pointer to memory location + +#define TUNER_REGS_NUM 104 +#define INITCTRL_NUM 40 +#ifdef _MXL_PRODUCTION +#define CHCTRL_NUM 39 +#else +#define CHCTRL_NUM 36 +#endif + +#define MXLCTRL_NUM 189 + +#define MASTER_CONTROL_ADDR 9 + + + + +// Enumeration of AGC Mode +typedef enum +{ + MXL_DUAL_AGC = 0 , + MXL_SINGLE_AGC +} AGC_Mode ; + +// +// Enumeration of Master Control Register State +// +typedef enum +{ + MC_LOAD_START = 1 , + MC_POWER_DOWN , + MC_SYNTH_RESET , + MC_SEQ_OFF +} Master_Control_State ; + +// +// Enumeration of MXL5005 Tuner Mode +// +typedef enum +{ + MXL_ANALOG_MODE = 0 , + MXL_DIGITAL_MODE + +} Tuner_Mode ; + +// +// Enumeration of MXL5005 Tuner IF Mode +// +typedef enum +{ + MXL_ZERO_IF = 0 , + MXL_LOW_IF + +} Tuner_IF_Mode ; + +// +// Enumeration of MXL5005 Tuner Clock Out Mode +// +typedef enum +{ + MXL_CLOCK_OUT_DISABLE = 0 , + MXL_CLOCK_OUT_ENABLE +} Tuner_Clock_Out ; + +// +// Enumeration of MXL5005 Tuner Div Out Mode +// +typedef enum +{ + MXL_DIV_OUT_1 = 0 , + MXL_DIV_OUT_4 + +} Tuner_Div_Out ; + +// +// Enumeration of MXL5005 Tuner Pull-up Cap Select Mode +// +typedef enum +{ + MXL_CAP_SEL_DISABLE = 0 , + MXL_CAP_SEL_ENABLE + +} Tuner_Cap_Select ; + +// +// Enumeration of MXL5005 Tuner RSSI Mode +// +typedef enum +{ + MXL_RSSI_DISABLE = 0 , + MXL_RSSI_ENABLE + +} Tuner_RSSI ; + +// +// Enumeration of MXL5005 Tuner Modulation Type +// +typedef enum +{ + MXL_DEFAULT_MODULATION = 0 , + MXL_DVBT, + MXL_ATSC, + MXL_QAM, + MXL_ANALOG_CABLE, + MXL_ANALOG_OTA + +} Tuner_Modu_Type ; + +// +// Enumeration of MXL5005 Tuner Tracking Filter Type +// +typedef enum +{ + MXL_TF_DEFAULT = 0 , + MXL_TF_OFF, + MXL_TF_C, + MXL_TF_C_H, + MXL_TF_D, + MXL_TF_D_L, + MXL_TF_E, + MXL_TF_F, + MXL_TF_E_2, + MXL_TF_E_NA, + MXL_TF_G + + +} Tuner_TF_Type ; + + +// +// MXL5005 Tuner Register Struct +// +typedef struct _TunerReg_struct +{ + _u16 Reg_Num ; // Tuner Register Address + _u16 Reg_Val ; // Current sofware programmed value waiting to be writen +} TunerReg_struct ; + +// +// MXL5005 Tuner Control Struct +// +typedef struct _TunerControl_struct { + _u16 Ctrl_Num ; // Control Number + _u16 size ; // Number of bits to represent Value + _u16 addr[25] ; // Array of Tuner Register Address for each bit position + _u16 bit[25] ; // Array of bit position in Register Address for each bit position + _u16 val[25] ; // Binary representation of Value +} TunerControl_struct ; + +// +// MXL5005 Tuner Struct +// +typedef struct _Tuner_struct +{ + _u8 Mode ; // 0: Analog Mode ; 1: Digital Mode + _u8 IF_Mode ; // for Analog Mode, 0: zero IF; 1: low IF + _u32 Chan_Bandwidth ; // filter channel bandwidth (6, 7, 8) + _u32 IF_OUT ; // Desired IF Out Frequency + _u16 IF_OUT_LOAD ; // IF Out Load Resistor (200/300 Ohms) + _u32 RF_IN ; // RF Input Frequency + _u32 Fxtal ; // XTAL Frequency + _u8 AGC_Mode ; // AGC Mode 0: Dual AGC; 1: Single AGC + _u16 TOP ; // Value: take over point + _u8 CLOCK_OUT ; // 0: turn off clock out; 1: turn on clock out + _u8 DIV_OUT ; // 4MHz or 16MHz + _u8 CAPSELECT ; // 0: disable On-Chip pulling cap; 1: enable + _u8 EN_RSSI ; // 0: disable RSSI; 1: enable RSSI + _u8 Mod_Type ; // Modulation Type; + // 0 - Default; 1 - DVB-T; 2 - ATSC; 3 - QAM; 4 - Analog Cable + _u8 TF_Type ; // Tracking Filter Type + // 0 - Default; 1 - Off; 2 - Type C; 3 - Type C-H + + // Calculated Settings + _u32 RF_LO ; // Synth RF LO Frequency + _u32 IF_LO ; // Synth IF LO Frequency + _u32 TG_LO ; // Synth TG_LO Frequency + + // Pointers to ControlName Arrays + _u16 Init_Ctrl_Num ; // Number of INIT Control Names + TunerControl_struct Init_Ctrl[INITCTRL_NUM] ; // INIT Control Names Array Pointer + _u16 CH_Ctrl_Num ; // Number of CH Control Names + TunerControl_struct CH_Ctrl[CHCTRL_NUM] ; // CH Control Name Array Pointer + _u16 MXL_Ctrl_Num ; // Number of MXL Control Names + TunerControl_struct MXL_Ctrl[MXLCTRL_NUM] ; // MXL Control Name Array Pointer + + // Pointer to Tuner Register Array + _u16 TunerRegs_Num ; // Number of Tuner Registers + TunerReg_struct TunerRegs[TUNER_REGS_NUM] ; // Tuner Register Array Pointer +} Tuner_struct ; + + + +typedef enum +{ + // + // Initialization Control Names + // + DN_IQTN_AMP_CUT = 1 , // 1 + BB_MODE , // 2 + BB_BUF , // 3 + BB_BUF_OA , // 4 + BB_ALPF_BANDSELECT , // 5 + BB_IQSWAP , // 6 + BB_DLPF_BANDSEL , // 7 + RFSYN_CHP_GAIN , // 8 + RFSYN_EN_CHP_HIGAIN , // 9 + AGC_IF , // 10 + AGC_RF , // 11 + IF_DIVVAL , // 12 + IF_VCO_BIAS , // 13 + CHCAL_INT_MOD_IF , // 14 + CHCAL_FRAC_MOD_IF , // 15 + DRV_RES_SEL , // 16 + I_DRIVER , // 17 + EN_AAF , // 18 + EN_3P , // 19 + EN_AUX_3P , // 20 + SEL_AAF_BAND , // 21 + SEQ_ENCLK16_CLK_OUT , // 22 + SEQ_SEL4_16B , // 23 + XTAL_CAPSELECT , // 24 + IF_SEL_DBL , // 25 + RFSYN_R_DIV , // 26 + SEQ_EXTSYNTHCALIF , // 27 + SEQ_EXTDCCAL , // 28 + AGC_EN_RSSI , // 29 + RFA_ENCLKRFAGC , // 30 + RFA_RSSI_REFH , // 31 + RFA_RSSI_REF , // 32 + RFA_RSSI_REFL , // 33 + RFA_FLR , // 34 + RFA_CEIL , // 35 + SEQ_EXTIQFSMPULSE , // 36 + OVERRIDE_1 , // 37 + BB_INITSTATE_DLPF_TUNE, // 38 + TG_R_DIV, // 39 + EN_CHP_LIN_B , // 40 + + // + // Channel Change Control Names + // + DN_POLY = 51 , // 51 + DN_RFGAIN , // 52 + DN_CAP_RFLPF , // 53 + DN_EN_VHFUHFBAR , // 54 + DN_GAIN_ADJUST , // 55 + DN_IQTNBUF_AMP , // 56 + DN_IQTNGNBFBIAS_BST , // 57 + RFSYN_EN_OUTMUX , // 58 + RFSYN_SEL_VCO_OUT , // 59 + RFSYN_SEL_VCO_HI , // 60 + RFSYN_SEL_DIVM , // 61 + RFSYN_RF_DIV_BIAS , // 62 + DN_SEL_FREQ , // 63 + RFSYN_VCO_BIAS , // 64 + CHCAL_INT_MOD_RF , // 65 + CHCAL_FRAC_MOD_RF , // 66 + RFSYN_LPF_R , // 67 + CHCAL_EN_INT_RF , // 68 + TG_LO_DIVVAL , // 69 + TG_LO_SELVAL , // 70 + TG_DIV_VAL , // 71 + TG_VCO_BIAS , // 72 + SEQ_EXTPOWERUP , // 73 + OVERRIDE_2 , // 74 + OVERRIDE_3 , // 75 + OVERRIDE_4 , // 76 + SEQ_FSM_PULSE , // 77 + GPIO_4B, // 78 + GPIO_3B, // 79 + GPIO_4, // 80 + GPIO_3, // 81 + GPIO_1B, // 82 + DAC_A_ENABLE , // 83 + DAC_B_ENABLE , // 84 + DAC_DIN_A , // 85 + DAC_DIN_B , // 86 +#ifdef _MXL_PRODUCTION + RFSYN_EN_DIV, // 87 + RFSYN_DIVM, // 88 + DN_BYPASS_AGC_I2C // 89 +#endif + +} MXL5005_ControlName ; + + + + + + + + + + + + + + + +// MaxLinear source code - MXL5005_c.h + + + +// MXL5005.h : main header file for the MXL5005 DLL +// +//#pragma once + +//#include "Common.h" +#ifdef _MXL_INTERNAL +#include "Common_MXL.h" +#endif + +void InitTunerControls( Tuner_struct *Tuner) ; + +_u16 MXL_BlockInit( Tuner_struct *Tuner ) ; + +_u16 MXL5005_RegisterInit (Tuner_struct * Tuner) ; +_u16 MXL5005_ControlInit (Tuner_struct *Tuner) ; + +#ifdef _MXL_INTERNAL + _u16 MXL5005_MXLControlInit(Tuner_struct *Tuner) ; +#endif + +_u16 MXL5005_TunerConfig(Tuner_struct *Tuner, + _u8 Mode, // 0: Analog Mode ; 1: Digital Mode + _u8 IF_mode, // for Analog Mode, 0: zero IF; 1: low IF + _u32 Bandwidth, // filter channel bandwidth (6, 7, 8) + _u32 IF_out, // Desired IF Out Frequency + _u32 Fxtal, // XTAL Frequency + _u8 AGC_Mode, // AGC Mode - Dual AGC: 0, Single AGC: 1 + _u16 TOP, // 0: Dual AGC; Value: take over point + _u16 IF_OUT_LOAD,// IF Out Load Resistor (200 / 300 Ohms) + _u8 CLOCK_OUT, // 0: turn off clock out; 1: turn on clock out + _u8 DIV_OUT, // 4MHz or 16MHz + _u8 CAPSELECT, // 0: disable On-Chip pulling cap; 1: enable + _u8 EN_RSSI, // 0: disable RSSI; 1: enable RSSI + _u8 Mod_Type, // Modulation Type; + // 0 - Default; 1 - DVB-T; 2 - ATSC; 3 - QAM; 4 - Analog Cable + _u8 TF_Type // Tracking Filter Type + // 0 - Default; 1 - Off; 2 - Type C; 3 - Type C-H + ) ; + +void MXL_SynthIFLO_Calc(Tuner_struct *Tuner) ; +void MXL_SynthRFTGLO_Calc(Tuner_struct *Tuner) ; +_u16 MXL_RegWrite(Tuner_struct *Tuner, _u8 RegNum, _u8 RegVal) ; +_u16 MXL_RegRead(Tuner_struct *Tuner, _u8 RegNum, _u8 *RegVal) ; +_u16 MXL_ControlWrite(Tuner_struct *Tuner, _u16 ControlNum, _u32 value) ; +_u16 MXL_ControlWrite_Group(Tuner_struct *Tuner, _u16 ControlNum, _u32 value, _u16 controlGroup) ; +_u16 MXL_ControlRead(Tuner_struct *Tuner, _u16 ControlNum, _u32 * value) ; +_u16 MXL_ControlRegRead(Tuner_struct *Tuner, _u16 ControlNum, _u8 *RegNum, int * count) ; +void MXL_RegWriteBit(Tuner_struct *Tuner, _u8 address, _u8 bit, _u8 bitVal); +_u16 MXL_IFSynthInit( Tuner_struct * Tuner ) ; +_u16 MXL_TuneRF(Tuner_struct *Tuner, _u32 RF_Freq) ; +_u16 MXL_OverwriteICDefault( Tuner_struct *Tuner) ; +_u16 MXL_SetGPIO(Tuner_struct *Tuner, _u8 GPIO_Num, _u8 GPIO_Val) ; +_u32 MXL_Ceiling( _u32 value, _u32 resolution ) ; +_u32 MXL_GetXtalInt(_u32 Xtal_Freq) ; + +_u16 MXL_GetInitRegister(Tuner_struct *Tuner, _u8 * RegNum, _u8 *RegVal, int *count) ; +_u16 MXL_GetCHRegister(Tuner_struct *Tuner, _u8 * RegNum, _u8 *RegVal, int *count) ; +_u16 MXL_GetCHRegister_ZeroIF(Tuner_struct *Tuner, _u8 * RegNum, _u8 *RegVal, int *count) ; +_u16 MXL_GetCHRegister_LowIF(Tuner_struct *Tuner, _u8 * RegNum, _u8 *RegVal, int *count) ; +_u16 MXL_GetMasterControl(_u8 *MasterReg, int state) ; + +#ifdef _MXL_PRODUCTION +_u16 MXL_VCORange_Test(Tuner_struct *Tuner, int VCO_Range) ; +_u16 MXL_Hystersis_Test(Tuner_struct *Tuner, int Hystersis) ; +#endif + + + + + + + + + + + + + + + + + + + + + + + +// The following context is MxL5005S tuner API source code + + + + + +/** + +@file + +@brief MxL5005S tuner module declaration + +One can manipulate MxL5005S tuner through MxL5005S module. +MxL5005S module is derived from tuner module. + +*/ + + + +#include "tuner_base.h" + + + + + +// Definitions + +// Constants +#define MXL5005S_REG_WRITING_TABLE_LEN_MAX 104 +#define MXL5005S_LATCH_BYTE 0xfe + +// Register address, MSB, and LSB +#define MXL5005S_BB_IQSWAP_ADDR 59 +#define MXL5005S_BB_IQSWAP_MSB 0 +#define MXL5005S_BB_IQSWAP_LSB 0 + +#define MXL5005S_BB_DLPF_BANDSEL_ADDR 53 +#define MXL5005S_BB_DLPF_BANDSEL_MSB 4 +#define MXL5005S_BB_DLPF_BANDSEL_LSB 3 + + + +// Standard modes +enum +{ + MXL5005S_STANDARD_DVBT, + MXL5005S_STANDARD_ATSC, +}; +#define MXL5005S_STANDARD_MODE_NUM 2 + + +// Bandwidth modes +enum +{ + MXL5005S_BANDWIDTH_6MHZ = 6000000, + MXL5005S_BANDWIDTH_7MHZ = 7000000, + MXL5005S_BANDWIDTH_8MHZ = 8000000, +}; +#define MXL5005S_BANDWIDTH_MODE_NUM 3 + + +// Top modes +enum +{ + MXL5005S_TOP_5P5 = 55, + MXL5005S_TOP_7P2 = 72, + MXL5005S_TOP_9P2 = 92, + MXL5005S_TOP_11P0 = 110, + MXL5005S_TOP_12P9 = 129, + MXL5005S_TOP_14P7 = 147, + MXL5005S_TOP_16P8 = 168, + MXL5005S_TOP_19P4 = 194, + MXL5005S_TOP_21P2 = 212, + MXL5005S_TOP_23P2 = 232, + MXL5005S_TOP_25P2 = 252, + MXL5005S_TOP_27P1 = 271, + MXL5005S_TOP_29P2 = 292, + MXL5005S_TOP_31P7 = 317, + MXL5005S_TOP_34P9 = 349, +}; + + +// IF output load +enum +{ + MXL5005S_IF_OUTPUT_LOAD_200_OHM = 200, + MXL5005S_IF_OUTPUT_LOAD_300_OHM = 300, +}; + + + + + +/// MxL5005S extra module alias +typedef struct MXL5005S_EXTRA_MODULE_TAG MXL5005S_EXTRA_MODULE; + + + + + +// MxL5005S register setting function pointer +typedef int +(*MXL5005S_FP_SET_REGS_WITH_TABLE)( + struct dvb_usb_device* dib, + TUNER_MODULE *pTuner, + unsigned char *pAddrTable, + unsigned char *pByteTable, + int TableLen + ); + + +// MxL5005S register mask bits setting function pointer +typedef int +(*MXL5005S_FP_SET_REG_MASK_BITS)( + struct dvb_usb_device* dib, + TUNER_MODULE *pTuner, + unsigned char RegAddr, + unsigned char Msb, + unsigned char Lsb, + const unsigned char WritingValue + ); + + +// MxL5005S spectrum mode setting function pointer +typedef int +(*MXL5005S_FP_SET_SPECTRUM_MODE)( + struct dvb_usb_device* dib, + TUNER_MODULE *pTuner, + int SpectrumMode + ); + + +// MxL5005S bandwidth setting function pointer +typedef int +(*MXL5005S_FP_SET_BANDWIDTH_HZ)( + struct dvb_usb_device* dib, + TUNER_MODULE *pTuner, + unsigned long BandwidthHz + ); + + + + + +// MxL5005S extra module +struct MXL5005S_EXTRA_MODULE_TAG +{ + // MxL5005S function pointers + MXL5005S_FP_SET_REGS_WITH_TABLE SetRegsWithTable; + MXL5005S_FP_SET_REG_MASK_BITS SetRegMaskBits; + MXL5005S_FP_SET_SPECTRUM_MODE SetSpectrumMode; + MXL5005S_FP_SET_BANDWIDTH_HZ SetBandwidthHz; + + + // MxL5005S extra data + unsigned char AgcMasterByte; // Variable name in MaxLinear source code: AGC_MASTER_BYTE + + // MaxLinear defined struct + Tuner_struct MxlDefinedTunerStructure; +}; + + + + + +// Builder +void +BuildMxl5005sModule( + TUNER_MODULE **ppTuner, + TUNER_MODULE *pTunerModuleMemory, + MXL5005S_EXTRA_MODULE *pMxl5005sExtraModuleMemory, + BASE_INTERFACE_MODULE *pBaseInterfaceModuleMemory, + I2C_BRIDGE_MODULE *pI2cBridgeModuleMemory, + unsigned char DeviceAddr, + int StandardMode + ); + + + + + +// Manipulaing functions +void +mxl5005s_SetDeviceAddr( + TUNER_MODULE *pTuner, + unsigned char DeviceAddr + ); + +void +mxl5005s_GetTunerType( + TUNER_MODULE *pTuner, + int *pTunerType + ); + +int +mxl5005s_GetDeviceAddr( + TUNER_MODULE *pTuner, + unsigned char *pDeviceAddr + ); + +int +mxl5005s_Initialize( + struct dvb_usb_device* dib, + TUNER_MODULE *pTuner + ); + +int +mxl5005s_SetRfFreqHz( + struct dvb_usb_device* dib, + TUNER_MODULE *pTuner, + unsigned long RfFreqHz + ); + +int +mxl5005s_GetRfFreqHz( + struct dvb_usb_device* dib, + TUNER_MODULE *pTuner, + unsigned long *pRfFreqHz + ); + + + + + +// Extra manipulaing functions +int +mxl5005s_SetRegsWithTable( + struct dvb_usb_device* dib, + TUNER_MODULE *pTuner, + unsigned char *pAddrTable, + unsigned char *pByteTable, + int TableLen + ); + +int +mxl5005s_SetRegMaskBits( + struct dvb_usb_device* dib, + TUNER_MODULE *pTuner, + unsigned char RegAddr, + unsigned char Msb, + unsigned char Lsb, + const unsigned char WritingValue + ); + +int +mxl5005s_SetSpectrumMode( + struct dvb_usb_device* dib, + TUNER_MODULE *pTuner, + int SpectrumMode + ); + +int +mxl5005s_SetBandwidthHz( + struct dvb_usb_device* dib, + TUNER_MODULE *pTuner, + unsigned long BandwidthHz + ); + + + + + +// I2C birdge module demod argument setting +void +mxl5005s_SetI2cBridgeModuleTunerArg( + TUNER_MODULE *pTuner + ); + + + + + + + + + + + + + + + +#endif + -- cgit v1.2.3 From 1732457f78f0e5ae4f6cc008c8c53fdc5b251a40 Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Thu, 1 May 2008 01:01:31 -0400 Subject: mxl5005s: Cleanup #1 From: Steven Toth Cleanup #1 Signed-off-by: Steven Toth Signed-off-by: Mauro Carvalho Chehab --- linux/drivers/media/common/tuners/mxl5005s.c | 8 +- linux/drivers/media/common/tuners/mxl5005s.h | 773 +++++++++------------------ 2 files changed, 260 insertions(+), 521 deletions(-) (limited to 'linux/drivers/media/common/tuners') diff --git a/linux/drivers/media/common/tuners/mxl5005s.c b/linux/drivers/media/common/tuners/mxl5005s.c index a32475fa1..3c4330614 100644 --- a/linux/drivers/media/common/tuners/mxl5005s.c +++ b/linux/drivers/media/common/tuners/mxl5005s.c @@ -35,13 +35,7 @@ MxL5005S module is derived from tuner module. */ -#include "tuner_mxl5005s.h" -#include "tuner_demod_io.h" - - - - - +#include "mxl5005s.h" /** diff --git a/linux/drivers/media/common/tuners/mxl5005s.h b/linux/drivers/media/common/tuners/mxl5005s.h index 8542fc10a..1944d9e94 100644 --- a/linux/drivers/media/common/tuners/mxl5005s.h +++ b/linux/drivers/media/common/tuners/mxl5005s.h @@ -23,138 +23,104 @@ */ -#ifndef __TUNER_MXL5005S_H -#define __TUNER_MXL5005S_H +#ifndef __MXL5005S_H +#define __MXL5005S_H +/* + * The following context is source code provided by MaxLinear. + * MaxLinear source code - Common.h + */ - -// The following context is source code provided by MaxLinear. - - -// MaxLinear source code - Common.h - - - -//#pragma once - -typedef unsigned char _u8; // At least 1 Byte -typedef unsigned short _u16; // At least 2 Bytes -typedef signed short _s16; -typedef unsigned long _u32; // At least 4 Bytes -typedef void * HANDLE; // Pointer to memory location +typedef void *HANDLE; /* Pointer to memory location */ #define TUNER_REGS_NUM 104 #define INITCTRL_NUM 40 + #ifdef _MXL_PRODUCTION -#define CHCTRL_NUM 39 +#define CHCTRL_NUM 39 #else -#define CHCTRL_NUM 36 +#define CHCTRL_NUM 36 #endif -#define MXLCTRL_NUM 189 - -#define MASTER_CONTROL_ADDR 9 - +#define MXLCTRL_NUM 189 +#define MASTER_CONTROL_ADDR 9 - - -// Enumeration of AGC Mode +/* Enumeration of AGC Mode */ typedef enum { - MXL_DUAL_AGC = 0 , + MXL_DUAL_AGC = 0, MXL_SINGLE_AGC -} AGC_Mode ; +} AGC_Mode; -// -// Enumeration of Master Control Register State -// +/* Enumeration of Master Control Register State */ typedef enum { - MC_LOAD_START = 1 , - MC_POWER_DOWN , - MC_SYNTH_RESET , + MC_LOAD_START = 1, + MC_POWER_DOWN, + MC_SYNTH_RESET, MC_SEQ_OFF -} Master_Control_State ; +} Master_Control_State; -// -// Enumeration of MXL5005 Tuner Mode -// +/* Enumeration of MXL5005 Tuner Mode */ typedef enum { - MXL_ANALOG_MODE = 0 , + MXL_ANALOG_MODE = 0, MXL_DIGITAL_MODE +} Tuner_Mode; -} Tuner_Mode ; - -// -// Enumeration of MXL5005 Tuner IF Mode -// +/* Enumeration of MXL5005 Tuner IF Mode */ typedef enum { - MXL_ZERO_IF = 0 , + MXL_ZERO_IF = 0, MXL_LOW_IF +} Tuner_IF_Mode; -} Tuner_IF_Mode ; - -// -// Enumeration of MXL5005 Tuner Clock Out Mode -// +/* Enumeration of MXL5005 Tuner Clock Out Mode */ typedef enum { - MXL_CLOCK_OUT_DISABLE = 0 , + MXL_CLOCK_OUT_DISABLE = 0, MXL_CLOCK_OUT_ENABLE -} Tuner_Clock_Out ; +} Tuner_Clock_Out; -// -// Enumeration of MXL5005 Tuner Div Out Mode -// +/* Enumeration of MXL5005 Tuner Div Out Mode */ typedef enum { - MXL_DIV_OUT_1 = 0 , + MXL_DIV_OUT_1 = 0, MXL_DIV_OUT_4 -} Tuner_Div_Out ; +} Tuner_Div_Out; -// -// Enumeration of MXL5005 Tuner Pull-up Cap Select Mode -// +/* Enumeration of MXL5005 Tuner Pull-up Cap Select Mode */ typedef enum { - MXL_CAP_SEL_DISABLE = 0 , + MXL_CAP_SEL_DISABLE = 0, MXL_CAP_SEL_ENABLE -} Tuner_Cap_Select ; +} Tuner_Cap_Select; -// -// Enumeration of MXL5005 Tuner RSSI Mode -// +/* Enumeration of MXL5005 Tuner RSSI Mode */ typedef enum { - MXL_RSSI_DISABLE = 0 , + MXL_RSSI_DISABLE = 0, MXL_RSSI_ENABLE -} Tuner_RSSI ; +} Tuner_RSSI; -// -// Enumeration of MXL5005 Tuner Modulation Type -// +/* Enumeration of MXL5005 Tuner Modulation Type */ typedef enum { - MXL_DEFAULT_MODULATION = 0 , + MXL_DEFAULT_MODULATION = 0, MXL_DVBT, MXL_ATSC, MXL_QAM, MXL_ANALOG_CABLE, MXL_ANALOG_OTA +} Tuner_Modu_Type; -} Tuner_Modu_Type ; - -// -// Enumeration of MXL5005 Tuner Tracking Filter Type -// +/* Enumeration of MXL5005 Tuner Tracking Filter Type */ typedef enum { - MXL_TF_DEFAULT = 0 , + MXL_TF_DEFAULT = 0, MXL_TF_OFF, MXL_TF_C, MXL_TF_C_H, @@ -165,316 +131,233 @@ typedef enum MXL_TF_E_2, MXL_TF_E_NA, MXL_TF_G +} Tuner_TF_Type; - -} Tuner_TF_Type ; - - -// -// MXL5005 Tuner Register Struct -// +/* MXL5005 Tuner Register Struct */ typedef struct _TunerReg_struct { - _u16 Reg_Num ; // Tuner Register Address - _u16 Reg_Val ; // Current sofware programmed value waiting to be writen -} TunerReg_struct ; + u16 Reg_Num; /* Tuner Register Address */ + u16 Reg_Val; /* Current sofware programmed value waiting to be writen */ +} TunerReg_struct; -// -// MXL5005 Tuner Control Struct -// +/* MXL5005 Tuner Control Struct */ typedef struct _TunerControl_struct { - _u16 Ctrl_Num ; // Control Number - _u16 size ; // Number of bits to represent Value - _u16 addr[25] ; // Array of Tuner Register Address for each bit position - _u16 bit[25] ; // Array of bit position in Register Address for each bit position - _u16 val[25] ; // Binary representation of Value -} TunerControl_struct ; - -// -// MXL5005 Tuner Struct -// + u16 Ctrl_Num; /* Control Number */ + u16 size; /* Number of bits to represent Value */ + u16 addr[25]; /* Array of Tuner Register Address for each bit position */ + u16 bit[25]; /* Array of bit position in Register Address for each bit position */ + u16 val[25]; /* Binary representation of Value */ +} TunerControl_struct; + +/* MXL5005 Tuner Struct */ typedef struct _Tuner_struct { - _u8 Mode ; // 0: Analog Mode ; 1: Digital Mode - _u8 IF_Mode ; // for Analog Mode, 0: zero IF; 1: low IF - _u32 Chan_Bandwidth ; // filter channel bandwidth (6, 7, 8) - _u32 IF_OUT ; // Desired IF Out Frequency - _u16 IF_OUT_LOAD ; // IF Out Load Resistor (200/300 Ohms) - _u32 RF_IN ; // RF Input Frequency - _u32 Fxtal ; // XTAL Frequency - _u8 AGC_Mode ; // AGC Mode 0: Dual AGC; 1: Single AGC - _u16 TOP ; // Value: take over point - _u8 CLOCK_OUT ; // 0: turn off clock out; 1: turn on clock out - _u8 DIV_OUT ; // 4MHz or 16MHz - _u8 CAPSELECT ; // 0: disable On-Chip pulling cap; 1: enable - _u8 EN_RSSI ; // 0: disable RSSI; 1: enable RSSI - _u8 Mod_Type ; // Modulation Type; - // 0 - Default; 1 - DVB-T; 2 - ATSC; 3 - QAM; 4 - Analog Cable - _u8 TF_Type ; // Tracking Filter Type - // 0 - Default; 1 - Off; 2 - Type C; 3 - Type C-H - - // Calculated Settings - _u32 RF_LO ; // Synth RF LO Frequency - _u32 IF_LO ; // Synth IF LO Frequency - _u32 TG_LO ; // Synth TG_LO Frequency - - // Pointers to ControlName Arrays - _u16 Init_Ctrl_Num ; // Number of INIT Control Names - TunerControl_struct Init_Ctrl[INITCTRL_NUM] ; // INIT Control Names Array Pointer - _u16 CH_Ctrl_Num ; // Number of CH Control Names - TunerControl_struct CH_Ctrl[CHCTRL_NUM] ; // CH Control Name Array Pointer - _u16 MXL_Ctrl_Num ; // Number of MXL Control Names - TunerControl_struct MXL_Ctrl[MXLCTRL_NUM] ; // MXL Control Name Array Pointer - - // Pointer to Tuner Register Array - _u16 TunerRegs_Num ; // Number of Tuner Registers - TunerReg_struct TunerRegs[TUNER_REGS_NUM] ; // Tuner Register Array Pointer -} Tuner_struct ; - - + u8 Mode; /* 0: Analog Mode ; 1: Digital Mode */ + u8 IF_Mode; /* for Analog Mode, 0: zero IF; 1: low IF */ + u32 Chan_Bandwidth; /* filter channel bandwidth (6, 7, 8) */ + u32 IF_OUT; /* Desired IF Out Frequency */ + u16 IF_OUT_LOAD; /* IF Out Load Resistor (200/300 Ohms) */ + u32 RF_IN; /* RF Input Frequency */ + u32 Fxtal; /* XTAL Frequency */ + u8 AGC_Mode; /* AGC Mode 0: Dual AGC; 1: Single AGC */ + u16 TOP; /* Value: take over point */ + u8 CLOCK_OUT; /* 0: turn off clock out; 1: turn on clock out */ + u8 DIV_OUT; /* 4MHz or 16MHz */ + u8 CAPSELECT; /* 0: disable On-Chip pulling cap; 1: enable */ + u8 EN_RSSI; /* 0: disable RSSI; 1: enable RSSI */ + u8 Mod_Type; /* Modulation Type; */ + /* 0 - Default; 1 - DVB-T; 2 - ATSC; 3 - QAM; 4 - Analog Cable */ + u8 TF_Type; /* Tracking Filter Type */ + /* 0 - Default; 1 - Off; 2 - Type C; 3 - Type C-H */ + + /* Calculated Settings */ + u32 RF_LO; /* Synth RF LO Frequency */ + u32 IF_LO; /* Synth IF LO Frequency */ + u32 TG_LO; /* Synth TG_LO Frequency */ + + /* Pointers to ControlName Arrays */ + u16 Init_Ctrl_Num; /* Number of INIT Control Names */ + TunerControl_struct + Init_Ctrl[INITCTRL_NUM]; /* INIT Control Names Array Pointer */ + + u16 CH_Ctrl_Num; /* Number of CH Control Names */ + TunerControl_struct + CH_Ctrl[CHCTRL_NUM]; /* CH Control Name Array Pointer */ + + u16 MXL_Ctrl_Num; /* Number of MXL Control Names */ + TunerControl_struct + MXL_Ctrl[MXLCTRL_NUM]; /* MXL Control Name Array Pointer */ + + /* Pointer to Tuner Register Array */ + u16 TunerRegs_Num; /* Number of Tuner Registers */ + TunerReg_struct + TunerRegs[TUNER_REGS_NUM]; /* Tuner Register Array Pointer */ + +} Tuner_struct; typedef enum { - // - // Initialization Control Names - // - DN_IQTN_AMP_CUT = 1 , // 1 - BB_MODE , // 2 - BB_BUF , // 3 - BB_BUF_OA , // 4 - BB_ALPF_BANDSELECT , // 5 - BB_IQSWAP , // 6 - BB_DLPF_BANDSEL , // 7 - RFSYN_CHP_GAIN , // 8 - RFSYN_EN_CHP_HIGAIN , // 9 - AGC_IF , // 10 - AGC_RF , // 11 - IF_DIVVAL , // 12 - IF_VCO_BIAS , // 13 - CHCAL_INT_MOD_IF , // 14 - CHCAL_FRAC_MOD_IF , // 15 - DRV_RES_SEL , // 16 - I_DRIVER , // 17 - EN_AAF , // 18 - EN_3P , // 19 - EN_AUX_3P , // 20 - SEL_AAF_BAND , // 21 - SEQ_ENCLK16_CLK_OUT , // 22 - SEQ_SEL4_16B , // 23 - XTAL_CAPSELECT , // 24 - IF_SEL_DBL , // 25 - RFSYN_R_DIV , // 26 - SEQ_EXTSYNTHCALIF , // 27 - SEQ_EXTDCCAL , // 28 - AGC_EN_RSSI , // 29 - RFA_ENCLKRFAGC , // 30 - RFA_RSSI_REFH , // 31 - RFA_RSSI_REF , // 32 - RFA_RSSI_REFL , // 33 - RFA_FLR , // 34 - RFA_CEIL , // 35 - SEQ_EXTIQFSMPULSE , // 36 - OVERRIDE_1 , // 37 - BB_INITSTATE_DLPF_TUNE, // 38 - TG_R_DIV, // 39 - EN_CHP_LIN_B , // 40 - - // - // Channel Change Control Names - // - DN_POLY = 51 , // 51 - DN_RFGAIN , // 52 - DN_CAP_RFLPF , // 53 - DN_EN_VHFUHFBAR , // 54 - DN_GAIN_ADJUST , // 55 - DN_IQTNBUF_AMP , // 56 - DN_IQTNGNBFBIAS_BST , // 57 - RFSYN_EN_OUTMUX , // 58 - RFSYN_SEL_VCO_OUT , // 59 - RFSYN_SEL_VCO_HI , // 60 - RFSYN_SEL_DIVM , // 61 - RFSYN_RF_DIV_BIAS , // 62 - DN_SEL_FREQ , // 63 - RFSYN_VCO_BIAS , // 64 - CHCAL_INT_MOD_RF , // 65 - CHCAL_FRAC_MOD_RF , // 66 - RFSYN_LPF_R , // 67 - CHCAL_EN_INT_RF , // 68 - TG_LO_DIVVAL , // 69 - TG_LO_SELVAL , // 70 - TG_DIV_VAL , // 71 - TG_VCO_BIAS , // 72 - SEQ_EXTPOWERUP , // 73 - OVERRIDE_2 , // 74 - OVERRIDE_3 , // 75 - OVERRIDE_4 , // 76 - SEQ_FSM_PULSE , // 77 - GPIO_4B, // 78 - GPIO_3B, // 79 - GPIO_4, // 80 - GPIO_3, // 81 - GPIO_1B, // 82 - DAC_A_ENABLE , // 83 - DAC_B_ENABLE , // 84 - DAC_DIN_A , // 85 - DAC_DIN_B , // 86 + /* Initialization Control Names */ + DN_IQTN_AMP_CUT = 1, /* 1 */ + BB_MODE, /* 2 */ + BB_BUF, /* 3 */ + BB_BUF_OA, /* 4 */ + BB_ALPF_BANDSELECT, /* 5 */ + BB_IQSWAP, /* 6 */ + BB_DLPF_BANDSEL, /* 7 */ + RFSYN_CHP_GAIN, /* 8 */ + RFSYN_EN_CHP_HIGAIN, /* 9 */ + AGC_IF, /* 10 */ + AGC_RF, /* 11 */ + IF_DIVVAL, /* 12 */ + IF_VCO_BIAS, /* 13 */ + CHCAL_INT_MOD_IF, /* 14 */ + CHCAL_FRAC_MOD_IF, /* 15 */ + DRV_RES_SEL, /* 16 */ + I_DRIVER, /* 17 */ + EN_AAF, /* 18 */ + EN_3P, /* 19 */ + EN_AUX_3P, /* 20 */ + SEL_AAF_BAND, /* 21 */ + SEQ_ENCLK16_CLK_OUT, /* 22 */ + SEQ_SEL4_16B, /* 23 */ + XTAL_CAPSELECT, /* 24 */ + IF_SEL_DBL, /* 25 */ + RFSYN_R_DIV, /* 26 */ + SEQ_EXTSYNTHCALIF, /* 27 */ + SEQ_EXTDCCAL, /* 28 */ + AGC_EN_RSSI, /* 29 */ + RFA_ENCLKRFAGC, /* 30 */ + RFA_RSSI_REFH, /* 31 */ + RFA_RSSI_REF, /* 32 */ + RFA_RSSI_REFL, /* 33 */ + RFA_FLR, /* 34 */ + RFA_CEIL, /* 35 */ + SEQ_EXTIQFSMPULSE, /* 36 */ + OVERRIDE_1, /* 37 */ + BB_INITSTATE_DLPF_TUNE, /* 38 */ + TG_R_DIV, /* 39 */ + EN_CHP_LIN_B, /* 40 */ + + /* Channel Change Control Names */ + DN_POLY = 51, /* 51 */ + DN_RFGAIN, /* 52 */ + DN_CAP_RFLPF, /* 53 */ + DN_EN_VHFUHFBAR, /* 54 */ + DN_GAIN_ADJUST, /* 55 */ + DN_IQTNBUF_AMP, /* 56 */ + DN_IQTNGNBFBIAS_BST, /* 57 */ + RFSYN_EN_OUTMUX, /* 58 */ + RFSYN_SEL_VCO_OUT, /* 59 */ + RFSYN_SEL_VCO_HI, /* 60 */ + RFSYN_SEL_DIVM, /* 61 */ + RFSYN_RF_DIV_BIAS, /* 62 */ + DN_SEL_FREQ, /* 63 */ + RFSYN_VCO_BIAS, /* 64 */ + CHCAL_INT_MOD_RF, /* 65 */ + CHCAL_FRAC_MOD_RF, /* 66 */ + RFSYN_LPF_R, /* 67 */ + CHCAL_EN_INT_RF, /* 68 */ + TG_LO_DIVVAL, /* 69 */ + TG_LO_SELVAL, /* 70 */ + TG_DIV_VAL, /* 71 */ + TG_VCO_BIAS, /* 72 */ + SEQ_EXTPOWERUP, /* 73 */ + OVERRIDE_2, /* 74 */ + OVERRIDE_3, /* 75 */ + OVERRIDE_4, /* 76 */ + SEQ_FSM_PULSE, /* 77 */ + GPIO_4B, /* 78 */ + GPIO_3B, /* 79 */ + GPIO_4, /* 80 */ + GPIO_3, /* 81 */ + GPIO_1B, /* 82 */ + DAC_A_ENABLE, /* 83 */ + DAC_B_ENABLE, /* 84 */ + DAC_DIN_A, /* 85 */ + DAC_DIN_B, /* 86 */ #ifdef _MXL_PRODUCTION - RFSYN_EN_DIV, // 87 - RFSYN_DIVM, // 88 - DN_BYPASS_AGC_I2C // 89 + RFSYN_EN_DIV, /* 87 */ + RFSYN_DIVM, /* 88 */ + DN_BYPASS_AGC_I2C /* 89 */ #endif +} MXL5005_ControlName; -} MXL5005_ControlName ; - - +/* End of common.h */ +/* + * The following context is source code provided by MaxLinear. + * MaxLinear source code - Common_MXL.h (?) + */ - - - - - - - - - - - -// MaxLinear source code - MXL5005_c.h - - - -// MXL5005.h : main header file for the MXL5005 DLL -// -//#pragma once - -//#include "Common.h" +void InitTunerControls(Tuner_struct *Tuner); +u16 MXL_BlockInit(Tuner_struct *Tuner); +u16 MXL5005_RegisterInit(Tuner_struct *Tuner); +u16 MXL5005_ControlInit(Tuner_struct *Tuner); #ifdef _MXL_INTERNAL -#include "Common_MXL.h" +u16 MXL5005_MXLControlInit(Tuner_struct *Tuner); #endif -void InitTunerControls( Tuner_struct *Tuner) ; - -_u16 MXL_BlockInit( Tuner_struct *Tuner ) ; - -_u16 MXL5005_RegisterInit (Tuner_struct * Tuner) ; -_u16 MXL5005_ControlInit (Tuner_struct *Tuner) ; - -#ifdef _MXL_INTERNAL - _u16 MXL5005_MXLControlInit(Tuner_struct *Tuner) ; -#endif +u16 MXL5005_TunerConfig(Tuner_struct *Tuner, + u8 Mode, /* 0: Analog Mode ; 1: Digital Mode */ + u8 IF_mode, /* for Analog Mode, 0: zero IF; 1: low IF */ + u32 Bandwidth, /* filter channel bandwidth (6, 7, 8) */ + u32 IF_out, /* Desired IF Out Frequency */ + u32 Fxtal, /* XTAL Frequency */ + u8 AGC_Mode, /* AGC Mode - Dual AGC: 0, Single AGC: 1 */ + u16 TOP, /* 0: Dual AGC; Value: take over point */ + u16 IF_OUT_LOAD, /* IF Out Load Resistor (200 / 300 Ohms) */ + u8 CLOCK_OUT, /* 0: turn off clock out; 1: turn on clock out */ + u8 DIV_OUT, /* 4MHz or 16MHz */ + u8 CAPSELECT, /* 0: disable On-Chip pulling cap; 1: enable */ + u8 EN_RSSI, /* 0: disable RSSI; 1: enable RSSI */ + u8 Mod_Type, /* Modulation Type; */ + /* 0 - Default; 1 - DVB-T; 2 - ATSC; 3 - QAM; 4 - Analog Cable */ + u8 TF_Type /* Tracking Filter Type */ + /* 0 - Default; 1 - Off; 2 - Type C; 3 - Type C-H */ + ); -_u16 MXL5005_TunerConfig(Tuner_struct *Tuner, - _u8 Mode, // 0: Analog Mode ; 1: Digital Mode - _u8 IF_mode, // for Analog Mode, 0: zero IF; 1: low IF - _u32 Bandwidth, // filter channel bandwidth (6, 7, 8) - _u32 IF_out, // Desired IF Out Frequency - _u32 Fxtal, // XTAL Frequency - _u8 AGC_Mode, // AGC Mode - Dual AGC: 0, Single AGC: 1 - _u16 TOP, // 0: Dual AGC; Value: take over point - _u16 IF_OUT_LOAD,// IF Out Load Resistor (200 / 300 Ohms) - _u8 CLOCK_OUT, // 0: turn off clock out; 1: turn on clock out - _u8 DIV_OUT, // 4MHz or 16MHz - _u8 CAPSELECT, // 0: disable On-Chip pulling cap; 1: enable - _u8 EN_RSSI, // 0: disable RSSI; 1: enable RSSI - _u8 Mod_Type, // Modulation Type; - // 0 - Default; 1 - DVB-T; 2 - ATSC; 3 - QAM; 4 - Analog Cable - _u8 TF_Type // Tracking Filter Type - // 0 - Default; 1 - Off; 2 - Type C; 3 - Type C-H - ) ; - -void MXL_SynthIFLO_Calc(Tuner_struct *Tuner) ; -void MXL_SynthRFTGLO_Calc(Tuner_struct *Tuner) ; -_u16 MXL_RegWrite(Tuner_struct *Tuner, _u8 RegNum, _u8 RegVal) ; -_u16 MXL_RegRead(Tuner_struct *Tuner, _u8 RegNum, _u8 *RegVal) ; -_u16 MXL_ControlWrite(Tuner_struct *Tuner, _u16 ControlNum, _u32 value) ; -_u16 MXL_ControlWrite_Group(Tuner_struct *Tuner, _u16 ControlNum, _u32 value, _u16 controlGroup) ; -_u16 MXL_ControlRead(Tuner_struct *Tuner, _u16 ControlNum, _u32 * value) ; -_u16 MXL_ControlRegRead(Tuner_struct *Tuner, _u16 ControlNum, _u8 *RegNum, int * count) ; -void MXL_RegWriteBit(Tuner_struct *Tuner, _u8 address, _u8 bit, _u8 bitVal); -_u16 MXL_IFSynthInit( Tuner_struct * Tuner ) ; -_u16 MXL_TuneRF(Tuner_struct *Tuner, _u32 RF_Freq) ; -_u16 MXL_OverwriteICDefault( Tuner_struct *Tuner) ; -_u16 MXL_SetGPIO(Tuner_struct *Tuner, _u8 GPIO_Num, _u8 GPIO_Val) ; -_u32 MXL_Ceiling( _u32 value, _u32 resolution ) ; -_u32 MXL_GetXtalInt(_u32 Xtal_Freq) ; - -_u16 MXL_GetInitRegister(Tuner_struct *Tuner, _u8 * RegNum, _u8 *RegVal, int *count) ; -_u16 MXL_GetCHRegister(Tuner_struct *Tuner, _u8 * RegNum, _u8 *RegVal, int *count) ; -_u16 MXL_GetCHRegister_ZeroIF(Tuner_struct *Tuner, _u8 * RegNum, _u8 *RegVal, int *count) ; -_u16 MXL_GetCHRegister_LowIF(Tuner_struct *Tuner, _u8 * RegNum, _u8 *RegVal, int *count) ; -_u16 MXL_GetMasterControl(_u8 *MasterReg, int state) ; +void MXL_SynthIFLO_Calc(Tuner_struct *Tuner); +void MXL_SynthRFTGLO_Calc(Tuner_struct *Tuner); +u16 MXL_RegWrite(Tuner_struct *Tuner, u8 RegNum, u8 RegVal); +u16 MXL_RegRead(Tuner_struct *Tuner, u8 RegNum, u8 *RegVal); +u16 MXL_ControlWrite(Tuner_struct *Tuner, u16 ControlNum, u32 value); +u16 MXL_ControlWrite_Group(Tuner_struct *Tuner, u16 ControlNum, u32 value, u16 controlGroup); +u16 MXL_ControlRead(Tuner_struct *Tuner, u16 ControlNum, u32 * value); +u16 MXL_ControlRegRead(Tuner_struct *Tuner, u16 ControlNum, u8 *RegNum, int *count); +void MXL_RegWriteBit(Tuner_struct *Tuner, u8 address, u8 bit, u8 bitVal); +u16 MXL_IFSynthInit(Tuner_struct * Tuner ); +u16 MXL_TuneRF(Tuner_struct *Tuner, u32 RF_Freq); +u16 MXL_OverwriteICDefault(Tuner_struct *Tuner); +u16 MXL_SetGPIO(Tuner_struct *Tuner, u8 GPIO_Num, u8 GPIO_Val); +u32 MXL_Ceiling(u32 value, u32 resolution); +u32 MXL_GetXtalInt(u32 Xtal_Freq); + +u16 MXL_GetInitRegister(Tuner_struct *Tuner, u8 * RegNum, u8 *RegVal, int *count); +u16 MXL_GetCHRegister(Tuner_struct *Tuner, u8 * RegNum, u8 *RegVal, int *count); +u16 MXL_GetCHRegister_ZeroIF(Tuner_struct *Tuner, u8 * RegNum, u8 *RegVal, int *count); +u16 MXL_GetCHRegister_LowIF(Tuner_struct *Tuner, u8 * RegNum, u8 *RegVal, int *count); +u16 MXL_GetMasterControl(u8 *MasterReg, int state); #ifdef _MXL_PRODUCTION -_u16 MXL_VCORange_Test(Tuner_struct *Tuner, int VCO_Range) ; -_u16 MXL_Hystersis_Test(Tuner_struct *Tuner, int Hystersis) ; +u16 MXL_VCORange_Test(Tuner_struct *Tuner, int VCO_Range); +u16 MXL_Hystersis_Test(Tuner_struct *Tuner, int Hystersis); #endif +/* Constants */ +#define MXL5005S_REG_WRITING_TABLE_LEN_MAX 104 +#define MXL5005S_LATCH_BYTE 0xfe - - - - - - - - - - - - - - - - - - - - - -// The following context is MxL5005S tuner API source code - - - - - -/** - -@file - -@brief MxL5005S tuner module declaration - -One can manipulate MxL5005S tuner through MxL5005S module. -MxL5005S module is derived from tuner module. - -*/ - - - -#include "tuner_base.h" - - - - - -// Definitions - -// Constants -#define MXL5005S_REG_WRITING_TABLE_LEN_MAX 104 -#define MXL5005S_LATCH_BYTE 0xfe - -// Register address, MSB, and LSB -#define MXL5005S_BB_IQSWAP_ADDR 59 -#define MXL5005S_BB_IQSWAP_MSB 0 -#define MXL5005S_BB_IQSWAP_LSB 0 +/* Register address, MSB, and LSB */ +#define MXL5005S_BB_IQSWAP_ADDR 59 +#define MXL5005S_BB_IQSWAP_MSB 0 +#define MXL5005S_BB_IQSWAP_LSB 0 #define MXL5005S_BB_DLPF_BANDSEL_ADDR 53 #define MXL5005S_BB_DLPF_BANDSEL_MSB 4 #define MXL5005S_BB_DLPF_BANDSEL_LSB 3 - - -// Standard modes +/* Standard modes */ enum { MXL5005S_STANDARD_DVBT, @@ -482,8 +365,7 @@ enum }; #define MXL5005S_STANDARD_MODE_NUM 2 - -// Bandwidth modes +/* Bandwidth modes */ enum { MXL5005S_BANDWIDTH_6MHZ = 6000000, @@ -492,8 +374,7 @@ enum }; #define MXL5005S_BANDWIDTH_MODE_NUM 3 - -// Top modes +/* Top modes */ enum { MXL5005S_TOP_5P5 = 55, @@ -513,29 +394,20 @@ enum MXL5005S_TOP_34P9 = 349, }; - -// IF output load +/* IF output load */ enum { MXL5005S_IF_OUTPUT_LOAD_200_OHM = 200, MXL5005S_IF_OUTPUT_LOAD_300_OHM = 300, }; - - - - -/// MxL5005S extra module alias +/* MxL5005S extra module alias */ typedef struct MXL5005S_EXTRA_MODULE_TAG MXL5005S_EXTRA_MODULE; - - - - -// MxL5005S register setting function pointer +/* MxL5005S register setting function pointer */ typedef int (*MXL5005S_FP_SET_REGS_WITH_TABLE)( - struct dvb_usb_device* dib, + struct dvb_usb_device* dib, TUNER_MODULE *pTuner, unsigned char *pAddrTable, unsigned char *pByteTable, @@ -543,10 +415,10 @@ typedef int ); -// MxL5005S register mask bits setting function pointer +/* MxL5005S register mask bits setting function pointer */ typedef int (*MXL5005S_FP_SET_REG_MASK_BITS)( - struct dvb_usb_device* dib, + struct dvb_usb_device* dib, TUNER_MODULE *pTuner, unsigned char RegAddr, unsigned char Msb, @@ -554,17 +426,15 @@ typedef int const unsigned char WritingValue ); - -// MxL5005S spectrum mode setting function pointer +/* MxL5005S spectrum mode setting function pointer */ typedef int (*MXL5005S_FP_SET_SPECTRUM_MODE)( - struct dvb_usb_device* dib, + struct dvb_usb_device* dib, TUNER_MODULE *pTuner, int SpectrumMode ); - -// MxL5005S bandwidth setting function pointer +/* MxL5005S bandwidth setting function pointer */ typedef int (*MXL5005S_FP_SET_BANDWIDTH_HZ)( struct dvb_usb_device* dib, @@ -572,147 +442,22 @@ typedef int unsigned long BandwidthHz ); - - - - -// MxL5005S extra module +/* MxL5005S extra module */ struct MXL5005S_EXTRA_MODULE_TAG { - // MxL5005S function pointers + /* MxL5005S function pointers */ MXL5005S_FP_SET_REGS_WITH_TABLE SetRegsWithTable; MXL5005S_FP_SET_REG_MASK_BITS SetRegMaskBits; MXL5005S_FP_SET_SPECTRUM_MODE SetSpectrumMode; MXL5005S_FP_SET_BANDWIDTH_HZ SetBandwidthHz; + /* MxL5005S extra data */ + unsigned char AgcMasterByte; /* Variable name in MaxLinear source code: AGC_MASTER_BYTE */ - // MxL5005S extra data - unsigned char AgcMasterByte; // Variable name in MaxLinear source code: AGC_MASTER_BYTE - - // MaxLinear defined struct + /* MaxLinear defined struct */ Tuner_struct MxlDefinedTunerStructure; }; +/* End of common_mxl.h (?) */ - - - - -// Builder -void -BuildMxl5005sModule( - TUNER_MODULE **ppTuner, - TUNER_MODULE *pTunerModuleMemory, - MXL5005S_EXTRA_MODULE *pMxl5005sExtraModuleMemory, - BASE_INTERFACE_MODULE *pBaseInterfaceModuleMemory, - I2C_BRIDGE_MODULE *pI2cBridgeModuleMemory, - unsigned char DeviceAddr, - int StandardMode - ); - - - - - -// Manipulaing functions -void -mxl5005s_SetDeviceAddr( - TUNER_MODULE *pTuner, - unsigned char DeviceAddr - ); - -void -mxl5005s_GetTunerType( - TUNER_MODULE *pTuner, - int *pTunerType - ); - -int -mxl5005s_GetDeviceAddr( - TUNER_MODULE *pTuner, - unsigned char *pDeviceAddr - ); - -int -mxl5005s_Initialize( - struct dvb_usb_device* dib, - TUNER_MODULE *pTuner - ); - -int -mxl5005s_SetRfFreqHz( - struct dvb_usb_device* dib, - TUNER_MODULE *pTuner, - unsigned long RfFreqHz - ); - -int -mxl5005s_GetRfFreqHz( - struct dvb_usb_device* dib, - TUNER_MODULE *pTuner, - unsigned long *pRfFreqHz - ); - - - - - -// Extra manipulaing functions -int -mxl5005s_SetRegsWithTable( - struct dvb_usb_device* dib, - TUNER_MODULE *pTuner, - unsigned char *pAddrTable, - unsigned char *pByteTable, - int TableLen - ); - -int -mxl5005s_SetRegMaskBits( - struct dvb_usb_device* dib, - TUNER_MODULE *pTuner, - unsigned char RegAddr, - unsigned char Msb, - unsigned char Lsb, - const unsigned char WritingValue - ); - -int -mxl5005s_SetSpectrumMode( - struct dvb_usb_device* dib, - TUNER_MODULE *pTuner, - int SpectrumMode - ); - -int -mxl5005s_SetBandwidthHz( - struct dvb_usb_device* dib, - TUNER_MODULE *pTuner, - unsigned long BandwidthHz - ); - - - - - -// I2C birdge module demod argument setting -void -mxl5005s_SetI2cBridgeModuleTunerArg( - TUNER_MODULE *pTuner - ); - - - - - - - - - - - - - - - -#endif +#endif /* __MXL5005S_H */ -- cgit v1.2.3 From 692b5b4ff2d0c3034279573138de1db7087c0b20 Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Thu, 1 May 2008 01:02:58 -0400 Subject: mxl5005s: Cleanup #2 From: Steven Toth Cleanup #2 Signed-off-by: Steven Toth Signed-off-by: Mauro Carvalho Chehab --- linux/drivers/media/common/tuners/mxl5005s.c | 907 ++++++++------------------- 1 file changed, 271 insertions(+), 636 deletions(-) (limited to 'linux/drivers/media/common/tuners') diff --git a/linux/drivers/media/common/tuners/mxl5005s.c b/linux/drivers/media/common/tuners/mxl5005s.c index 3c4330614..2af14de73 100644 --- a/linux/drivers/media/common/tuners/mxl5005s.c +++ b/linux/drivers/media/common/tuners/mxl5005s.c @@ -22,71 +22,10 @@ * Revision: 080314 - original version */ - -/** - -@file - -@brief MxL5005S tuner module definition - -One can manipulate MxL5005S tuner through MxL5005S module. -MxL5005S module is derived from tuner module. - -*/ - - #include "mxl5005s.h" -/** - -@defgroup MXL5005S_TUNER_MODULE MxL5005S tuner module - -MxL5005S tuner module is drived from tuner base module. - -@see TUNER_BASE_MODULE - -*/ - - - - - -/** -@defgroup MXL5005S_MODULE_BUILDER MxL5005S module builder -@ingroup MXL5005S_TUNER_MODULE - -One should call MxL5005S module builder before using MxL5005S module. - -*/ -/// @{ - - - - - -/** - -@brief MxL5005S tuner module builder - -Use BuildMxl5005sModule() to build MxL5005S module, set all module function pointers with the corresponding functions, -and initialize module private variables. - - -@param [in] ppTuner Pointer to MxL5005S tuner module pointer -@param [in] pTunerModuleMemory Pointer to an allocated tuner module memory -@param [in] pMxl5005sExtraModuleMemory Pointer to an allocated MxL5005S extra module memory -@param [in] pI2cBridgeModuleMemory Pointer to an allocated I2C bridge module memory -@param [in] DeviceAddr MxL5005S I2C device address -@param [in] CrystalFreqHz MxL5005S crystal frequency in Hz - - -@note \n - -# One should call BuildMxl5005sModule() to build MxL5005S module before using it. - -*/ -void -BuildMxl5005sModule( +void BuildMxl5005sModule( TUNER_MODULE **ppTuner, TUNER_MODULE *pTunerModuleMemory, MXL5005S_EXTRA_MODULE *pMxl5005sExtraModuleMemory, @@ -200,43 +139,7 @@ BuildMxl5005sModule( return; } - - - - -/// @} - - - - - -/** - -@defgroup MXL5005S_MANIPULATING_FUNCTIONS MxL5005S manipulating functions derived from tuner base module -@ingroup MXL5005S_TUNER_MODULE - -One can use the MxL5005S tuner module manipulating interface implemented by MxL5005S manipulating functions to -manipulate MxL5005S tuner. - -*/ -/// @{ - - - - - -/** - -@brief Set MxL5005S tuner I2C device address. - -@note \n - -# MxL5005S tuner builder will set TUNER_FP_SET_DEVICE_ADDR() function pointer with mxl5005s_SetDeviceAddr(). - -@see TUNER_FP_SET_DEVICE_ADDR - -*/ -void -mxl5005s_SetDeviceAddr( +void mxl5005s_SetDeviceAddr( TUNER_MODULE *pTuner, unsigned char DeviceAddr ) @@ -249,22 +152,7 @@ mxl5005s_SetDeviceAddr( return; } - - - - -/** - -@brief Get MxL5005S tuner type. - -@note \n - -# MxL5005S tuner builder will set TUNER_FP_GET_TUNER_TYPE() function pointer with mxl5005s_GetTunerType(). - -@see TUNER_FP_GET_TUNER_TYPE - -*/ -void -mxl5005s_GetTunerType( +void mxl5005s_GetTunerType( TUNER_MODULE *pTuner, int *pTunerType ) @@ -276,22 +164,7 @@ mxl5005s_GetTunerType( return; } - - - - -/** - -@brief Get MxL5005S tuner I2C device address. - -@note \n - -# MxL5005S tuner builder will set TUNER_FP_GET_DEVICE_ADDR() function pointer with mxl5005s_GetDeviceAddr(). - -@see TUNER_FP_GET_DEVICE_ADDR - -*/ -int -mxl5005s_GetDeviceAddr( +int mxl5005s_GetDeviceAddr( TUNER_MODULE *pTuner, unsigned char *pDeviceAddr ) @@ -310,22 +183,7 @@ error_status_get_tuner_i2c_device_addr: return FUNCTION_ERROR; } - - - - -/** - -@brief Initialize MxL5005S tuner. - -@note \n - -# MxL5005S tuner builder will set TUNER_FP_INITIALIZE() function pointer with mxl5005s_Initialize(). - -@see TUNER_FP_INITIALIZE - -*/ -int -mxl5005s_Initialize( +int mxl5005s_Initialize( struct dvb_usb_device* dib, TUNER_MODULE *pTuner ) @@ -337,16 +195,12 @@ mxl5005s_Initialize( unsigned char ByteTable[MXL5005S_REG_WRITING_TABLE_LEN_MAX]; int TableLen; - - // Get tuner extra module. pExtra = (MXL5005S_EXTRA_MODULE *)pTuner->pExtra; - // Get AGC master byte AgcMasterByte = pExtra->AgcMasterByte; - // Initialize MxL5005S tuner according to MxL5005S tuner example code. // Tuner initialization stage 0 @@ -357,37 +211,19 @@ mxl5005s_Initialize( if(pExtra->SetRegsWithTable( dib,pTuner, AddrTable, ByteTable, LEN_1_BYTE) != FUNCTION_SUCCESS) goto error_status_set_tuner_registers; - // Tuner initialization stage 1 MXL_GetInitRegister(&pExtra->MxlDefinedTunerStructure, AddrTable, ByteTable, &TableLen); if(pExtra->SetRegsWithTable( dib,pTuner, AddrTable, ByteTable, TableLen) != FUNCTION_SUCCESS) goto error_status_set_tuner_registers; - return FUNCTION_SUCCESS; - error_status_set_tuner_registers: return FUNCTION_ERROR; } - - - - -/** - -@brief Set MxL5005S tuner RF frequency in Hz. - -@note \n - -# MxL5005S tuner builder will set TUNER_FP_SET_RF_FREQ_HZ() function pointer with mxl5005s_SetRfFreqHz(). - -@see TUNER_FP_SET_RF_FREQ_HZ - -*/ -int -mxl5005s_SetRfFreqHz( +int mxl5005s_SetRfFreqHz( struct dvb_usb_device* dib, TUNER_MODULE *pTuner, unsigned long RfFreqHz @@ -404,8 +240,6 @@ mxl5005s_SetRfFreqHz( unsigned long IfDivval; unsigned char MasterControlByte; - - // Get tuner extra module and base interface module. pExtra = (MXL5005S_EXTRA_MODULE *)pTuner->pExtra; pBaseInterface = pTuner->pBaseInterface; @@ -476,22 +310,7 @@ error_status_set_tuner_registers: return FUNCTION_ERROR; } - - - - -/** - -@brief Get MxL5005S tuner RF frequency in Hz. - -@note \n - -# MxL5005S tuner builder will set TUNER_FP_GET_RF_FREQ_HZ() function pointer with mxl5005s_GetRfFreqHz(). - -@see TUNER_FP_GET_RF_FREQ_HZ - -*/ -int -mxl5005s_GetRfFreqHz( +int mxl5005s_GetRfFreqHz( struct dvb_usb_device* dib, TUNER_MODULE *pTuner, unsigned long *pRfFreqHz @@ -511,18 +330,7 @@ error_status_get_tuner_rf_frequency: return FUNCTION_ERROR; } - - - - -/** - -@brief Set MxL5005S tuner registers with table. - -*/ -/* -int -mxl5005s_SetRegsWithTable( +int mxl5005s_SetRegsWithTable( struct dvb_usb_device* dib, TUNER_MODULE *pTuner, unsigned char *pAddrTable, @@ -585,11 +393,8 @@ mxl5005s_SetRegsWithTable( error_status_set_tuner_registers: return FUNCTION_ERROR; } -*/ - -int -mxl5005s_SetRegsWithTable( +int mxl5005s_SetRegsWithTable( struct dvb_usb_device* dib, TUNER_MODULE *pTuner, unsigned char *pAddrTable, @@ -618,17 +423,7 @@ mxl5005s_SetRegsWithTable( return FUNCTION_SUCCESS; } - - - - -/** - -@brief Set MxL5005S tuner register bits. - -*/ -int -mxl5005s_SetRegMaskBits( +int mxl5005s_SetRegMaskBits( struct dvb_usb_device* dib, TUNER_MODULE *pTuner, unsigned char RegAddr, @@ -685,17 +480,7 @@ error_status_set_tuner_registers: return FUNCTION_ERROR; } - - - - -/** - -@brief Set MxL5005S tuner spectrum mode. - -*/ -int -mxl5005s_SetSpectrumMode( +int mxl5005s_SetSpectrumMode( struct dvb_usb_device* dib, TUNER_MODULE *pTuner, int SpectrumMode @@ -730,17 +515,7 @@ error_status_set_tuner_registers: return FUNCTION_ERROR; } - - - - -/** - -@brief Set MxL5005S tuner bandwidth in Hz. - -*/ -int -mxl5005s_SetBandwidthHz( +int mxl5005s_SetBandwidthHz( struct dvb_usb_device* dib, TUNER_MODULE *pTuner, unsigned long BandwidthHz @@ -777,48 +552,7 @@ error_status_set_tuner_registers: return FUNCTION_ERROR; } - - - - -/// @} - - - - - -/** - -@defgroup MXL5005S_DEPENDENCE MxL5005S dependence -@ingroup MXL5005S_TUNER_MODULE - -MxL5005S dependence is the related functions for MxL5005S tuner module interface. -One should not use MxL5005S dependence directly. - -*/ -/// @{ - - - - - -/** - -@brief Set I2C bridge module tuner arguments. - -MxL5005S builder will use mxl5005s_SetI2cBridgeModuleTunerArg() to set I2C bridge module tuner arguments. - - -@param [in] pTuner The tuner module pointer - - -@see BuildMxl5005sModule() - -*/ -void -mxl5005s_SetI2cBridgeModuleTunerArg( - TUNER_MODULE *pTuner - ) +void mxl5005s_SetI2cBridgeModuleTunerArg(TUNER_MODULE *pTuner) { I2C_BRIDGE_MODULE *pI2cBridge; @@ -833,51 +567,10 @@ mxl5005s_SetI2cBridgeModuleTunerArg( return; } - - - - - -/// @} - - - - - - - - - - - - - - - - - - - - - - // The following context is source code provided by MaxLinear. - - - - - // MaxLinear source code - MXL5005_Initialize.cpp - - - -//#ifdef _MXL_HEADER -//#include "stdafx.h" -//#endif -//#include "MXL5005_c.h" - -_u16 MXL5005_RegisterInit (Tuner_struct * Tuner) +u16 MXL5005_RegisterInit(Tuner_struct *Tuner) { Tuner->TunerRegs_Num = TUNER_REGS_NUM ; // Tuner->TunerRegs = (TunerReg_struct *) calloc( TUNER_REGS_NUM, sizeof(TunerReg_struct) ) ; @@ -1197,7 +890,7 @@ _u16 MXL5005_RegisterInit (Tuner_struct * Tuner) return 0 ; } -_u16 MXL5005_ControlInit (Tuner_struct *Tuner) +u16 MXL5005_ControlInit(Tuner_struct *Tuner) { Tuner->Init_Ctrl_Num = INITCTRL_NUM ; @@ -2136,34 +1829,10 @@ _u16 MXL5005_ControlInit (Tuner_struct *Tuner) return 0 ; } - - - - - - - - - - - - - - // MaxLinear source code - MXL5005_c.cpp - - - // MXL5005.cpp : Defines the initialization routines for the DLL. // 2.6.12 - -//#ifdef _MXL_HEADER -//#include "stdafx.h" -//#endif -//#include "MXL5005_c.h" - - void InitTunerControls(Tuner_struct *Tuner) { MXL5005_RegisterInit(Tuner) ; @@ -2173,8 +1842,6 @@ void InitTunerControls(Tuner_struct *Tuner) #endif } - - /////////////////////////////////////////////////////////////////////////////// // // // Function: MXL_ConfigTuner // @@ -2184,7 +1851,7 @@ void InitTunerControls(Tuner_struct *Tuner) // // // // // Functions used: // -// MXL_SynthIFLO_Calc // +// MXL_SynthIFLO_Calc // // // // Inputs: // // Tuner_struct: structure defined at higher level // @@ -2193,12 +1860,12 @@ void InitTunerControls(Tuner_struct *Tuner) // Bandwidth: Filter Channel Bandwidth (in Hz) // // IF_out: Desired IF out Frequency (in Hz) // // Fxtal: Crystal Frerquency (in Hz) // -// TOP: 0: Dual AGC; Value: take over point // -// IF_OUT_LOAD: IF out load resistor (200/300 Ohms) // -// CLOCK_OUT: 0: Turn off clock out; 1: turn on clock out // -// DIV_OUT: 0: Div-1; 1: Div-4 // -// CAPSELECT: 0: Disable On-chip pulling cap; 1: Enable // -// EN_RSSI: 0: Disable RSSI; 1: Enable RSSI // +// TOP: 0: Dual AGC; Value: take over point // +// IF_OUT_LOAD: IF out load resistor (200/300 Ohms) // +// CLOCK_OUT: 0: Turn off clock out; 1: turn on clock out // +// DIV_OUT: 0: Div-1; 1: Div-4 // +// CAPSELECT: 0: Disable On-chip pulling cap; 1: Enable // +// EN_RSSI: 0: Disable RSSI; 1: Enable RSSI // // // // Outputs: // // Tuner // @@ -2208,26 +1875,26 @@ void InitTunerControls(Tuner_struct *Tuner) // > 0 : Failed // // // /////////////////////////////////////////////////////////////////////////////// -_u16 MXL5005_TunerConfig(Tuner_struct *Tuner, - _u8 Mode, // 0: Analog Mode ; 1: Digital Mode - _u8 IF_mode, // for Analog Mode, 0: zero IF; 1: low IF - _u32 Bandwidth, // filter channel bandwidth (6, 7, 8) - _u32 IF_out, // Desired IF Out Frequency - _u32 Fxtal, // XTAL Frequency - _u8 AGC_Mode, // AGC Mode - Dual AGC: 0, Single AGC: 1 - _u16 TOP, // 0: Dual AGC; Value: take over point - _u16 IF_OUT_LOAD, // IF Out Load Resistor (200 / 300 Ohms) - _u8 CLOCK_OUT, // 0: turn off clock out; 1: turn on clock out - _u8 DIV_OUT, // 0: Div-1; 1: Div-4 - _u8 CAPSELECT, // 0: disable On-Chip pulling cap; 1: enable - _u8 EN_RSSI, // 0: disable RSSI; 1: enable RSSI - _u8 Mod_Type, // Modulation Type; - // 0 - Default; 1 - DVB-T; 2 - ATSC; 3 - QAM; 4 - Analog Cable - _u8 TF_Type // Tracking Filter - // 0 - Default; 1 - Off; 2 - Type C; 3 - Type C-H +u16 MXL5005_TunerConfig(Tuner_struct *Tuner, + u8 Mode, // 0: Analog Mode ; 1: Digital Mode + u8 IF_mode, // for Analog Mode, 0: zero IF; 1: low IF + u32 Bandwidth, // filter channel bandwidth (6, 7, 8) + u32 IF_out, // Desired IF Out Frequency + u32 Fxtal, // XTAL Frequency + u8 AGC_Mode, // AGC Mode - Dual AGC: 0, Single AGC: 1 + u16 TOP, // 0: Dual AGC; Value: take over point + u16 IF_OUT_LOAD, // IF Out Load Resistor (200 / 300 Ohms) + u8 CLOCK_OUT, // 0: turn off clock out; 1: turn on clock out + u8 DIV_OUT, // 0: Div-1; 1: Div-4 + u8 CAPSELECT, // 0: disable On-Chip pulling cap; 1: enable + u8 EN_RSSI, // 0: disable RSSI; 1: enable RSSI + u8 Mod_Type, // Modulation Type; + // 0 - Default; 1 - DVB-T; 2 - ATSC; 3 - QAM; 4 - Analog Cable + u8 TF_Type // Tracking Filter + // 0 - Default; 1 - Off; 2 - Type C; 3 - Type C-H ) { - _u16 status = 0 ; + u16 status = 0 ; Tuner->Mode = Mode ; Tuner->IF_Mode = IF_mode ; @@ -2244,15 +1911,10 @@ _u16 MXL5005_TunerConfig(Tuner_struct *Tuner, Tuner->Mod_Type = Mod_Type ; Tuner->TF_Type = TF_Type ; - - - // - // Initialize all the controls and registers - // + /* Initialize all the controls and registers */ InitTunerControls (Tuner) ; - // - // Synthesizer LO frequency calculation - // + + /* Synthesizer LO frequency calculation */ MXL_SynthIFLO_Calc( Tuner ) ; return status ; @@ -2366,9 +2028,9 @@ void MXL_SynthRFTGLO_Calc(Tuner_struct *Tuner) // > 0 : Failed // // // /////////////////////////////////////////////////////////////////////////////// -_u16 MXL_OverwriteICDefault( Tuner_struct *Tuner) +u16 MXL_OverwriteICDefault( Tuner_struct *Tuner) { - _u16 status = 0 ; + u16 status = 0 ; status += MXL_ControlWrite(Tuner, OVERRIDE_1, 1) ; status += MXL_ControlWrite(Tuner, OVERRIDE_2, 1) ; @@ -2403,20 +2065,20 @@ _u16 MXL_OverwriteICDefault( Tuner_struct *Tuner) // > 0 : Failed // // // /////////////////////////////////////////////////////////////////////////////// -_u16 MXL_BlockInit( Tuner_struct *Tuner ) +u16 MXL_BlockInit( Tuner_struct *Tuner ) { - _u16 status = 0 ; + u16 status = 0 ; status += MXL_OverwriteICDefault(Tuner) ; // // Downconverter Control - // Dig Ana + // Dig Ana status += MXL_ControlWrite(Tuner, DN_IQTN_AMP_CUT, Tuner->Mode ? 1 : 0) ; // // Filter Control - // Dig Ana + // Dig Ana status += MXL_ControlWrite(Tuner, BB_MODE, Tuner->Mode ? 0 : 1) ; status += MXL_ControlWrite(Tuner, BB_BUF, Tuner->Mode ? 3 : 2) ; status += MXL_ControlWrite(Tuner, BB_BUF_OA, Tuner->Mode ? 1 : 0) ; @@ -2439,7 +2101,7 @@ _u16 MXL_BlockInit( Tuner_struct *Tuner ) } } else { // Analog Mode switch (Tuner->Chan_Bandwidth) { - case 8000000: // Low Zero + case 8000000: // Low Zero status += MXL_ControlWrite(Tuner, BB_ALPF_BANDSELECT, (Tuner->IF_Mode ? 0 : 3)) ; break ; case 7000000: @@ -2453,7 +2115,7 @@ _u16 MXL_BlockInit( Tuner_struct *Tuner ) // // Charge Pump Control - // Dig Ana + // Dig Ana status += MXL_ControlWrite(Tuner, RFSYN_CHP_GAIN, Tuner->Mode ? 5 : 8) ; status += MXL_ControlWrite(Tuner, RFSYN_EN_CHP_HIGAIN, Tuner->Mode ? 1 : 1) ; status += MXL_ControlWrite(Tuner, EN_CHP_LIN_B, Tuner->Mode ? 0 : 0) ; @@ -2621,8 +2283,6 @@ _u16 MXL_BlockInit( Tuner_struct *Tuner ) // Apply Default value to BB_INITSTATE_DLPF_TUNE // - - // // RSSI Control // @@ -2697,7 +2357,7 @@ _u16 MXL_BlockInit( Tuner_struct *Tuner ) //Tuner->AGC_Mode = 1 ; // Single AGC Mode - // Disable RSSI //change here for v2.6.5 + // Disable RSSI //change here for v2.6.5 status += MXL_ControlWrite(Tuner, SEQ_EXTSYNTHCALIF, 1) ; status += MXL_ControlWrite(Tuner, SEQ_EXTDCCAL, 1) ; status += MXL_ControlWrite(Tuner, AGC_EN_RSSI, 0) ; @@ -2787,13 +2447,13 @@ _u16 MXL_BlockInit( Tuner_struct *Tuner ) // > 0 : Failed // // // /////////////////////////////////////////////////////////////////////////////// -_u16 MXL_IFSynthInit( Tuner_struct * Tuner ) +u16 MXL_IFSynthInit(Tuner_struct * Tuner) { - _u16 status = 0 ; + u16 status = 0 ; // Declare Local Variables - _u32 Fref = 0 ; - _u32 Kdbl, intModVal ; - _u32 fracModVal ; + u32 Fref = 0 ; + u32 Kdbl, intModVal ; + u32 fracModVal ; Kdbl = 2 ; if (Tuner->Fxtal >= 12000000UL && Tuner->Fxtal <= 16000000UL) @@ -2999,8 +2659,6 @@ _u16 MXL_IFSynthInit( Tuner_struct * Tuner ) fracModVal = fracModVal / ((Tuner->Fxtal * Kdbl/2)/1000) ; status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_IF, fracModVal) ; - - return status ; } @@ -3008,14 +2666,14 @@ _u16 MXL_IFSynthInit( Tuner_struct * Tuner ) // // // Function: MXL_GetXtalInt // // // -// Description: return the Crystal Integration Value for // -// TG_VCO_BIAS calculation // +// Description: return the Crystal Integration Value for // +// TG_VCO_BIAS calculation // // // // Globals: // // NONE // // // // Functions used: // -// NONE // +// NONE // // // // Inputs: // // Crystal Frequency Value in Hz // @@ -3028,7 +2686,7 @@ _u16 MXL_IFSynthInit( Tuner_struct * Tuner ) // > 0 : Failed // // // /////////////////////////////////////////////////////////////////////////////// -_u32 MXL_GetXtalInt(_u32 Xtal_Freq) +u32 MXL_GetXtalInt(u32 Xtal_Freq) { if ((Xtal_Freq % 1000000) == 0) return (Xtal_Freq / 10000) ; @@ -3048,7 +2706,7 @@ _u32 MXL_GetXtalInt(_u32 Xtal_Freq) // Functions used: // // MXL_SynthRFTGLO_Calc // // MXL5005_ControlWrite // -// MXL_GetXtalInt // +// MXL_GetXtalInt // // // // Inputs: // // Tuner : Tuner structure defined at higher level // @@ -3060,20 +2718,20 @@ _u32 MXL_GetXtalInt(_u32 Xtal_Freq) // 0 : Successful // // 1 : Unsuccessful // /////////////////////////////////////////////////////////////////////////////// -_u16 MXL_TuneRF(Tuner_struct *Tuner, _u32 RF_Freq) +u16 MXL_TuneRF(Tuner_struct *Tuner, u32 RF_Freq) { // Declare Local Variables - _u16 status = 0 ; - _u32 divider_val, E3, E4, E5, E5A ; - _u32 Fmax, Fmin, FmaxBin, FminBin ; - _u32 Kdbl_RF = 2; - _u32 tg_divval ; - _u32 tg_lo ; - _u32 Xtal_Int ; + u16 status = 0 ; + u32 divider_val, E3, E4, E5, E5A ; + u32 Fmax, Fmin, FmaxBin, FminBin ; + u32 Kdbl_RF = 2; + u32 tg_divval ; + u32 tg_lo ; + u32 Xtal_Int ; - _u32 Fref_TG; - _u32 Fvco; -// _u32 temp; + u32 Fref_TG; + u32 Fvco; +// u32 temp; Xtal_Int = MXL_GetXtalInt(Tuner->Fxtal ) ; @@ -3774,7 +3432,8 @@ _u16 MXL_TuneRF(Tuner_struct *Tuner, _u32 RF_Freq) { status += MXL_ControlWrite(Tuner, DAC_DIN_A, 0) ; - if (Tuner->RF_IN >= 471000000 && (Tuner->RF_IN - 471000000)%6000000 != 0) // if UHF and terrestrial => Turn off Tracking Filter + // if UHF and terrestrial => Turn off Tracking Filter + if (Tuner->RF_IN >= 471000000 && (Tuner->RF_IN - 471000000)%6000000 != 0) { // Turn off all the banks status += MXL_SetGPIO(Tuner, 3, 1) ; @@ -4089,7 +3748,8 @@ _u16 MXL_TuneRF(Tuner_struct *Tuner, _u32 RF_Freq) { status += MXL_ControlWrite(Tuner, DAC_DIN_B, 0) ; - if (Tuner->RF_IN >= 471000000 && (Tuner->RF_IN - 471000000)%6000000 != 0) //if UHF and terrestrial=> Turn off Tracking Filter + // if UHF and terrestrial=> Turn off Tracking Filter + if (Tuner->RF_IN >= 471000000 && (Tuner->RF_IN - 471000000)%6000000 != 0) { // Turn off all the banks status += MXL_SetGPIO(Tuner, 3, 1) ; @@ -4181,9 +3841,9 @@ _u16 MXL_TuneRF(Tuner_struct *Tuner, _u32 RF_Freq) return status ; } -_u16 MXL_SetGPIO(Tuner_struct *Tuner, _u8 GPIO_Num, _u8 GPIO_Val) +u16 MXL_SetGPIO(Tuner_struct *Tuner, u8 GPIO_Num, u8 GPIO_Val) { - _u16 status = 0 ; + u16 status = 0 ; if (GPIO_Num == 1) status += MXL_ControlWrite(Tuner, GPIO_1B, GPIO_Val ? 0 : 1) ; @@ -4247,9 +3907,9 @@ _u16 MXL_SetGPIO(Tuner_struct *Tuner, _u8 GPIO_Num, _u8 GPIO_Val) // >0 : Value exceed maximum allowed for control number // // // /////////////////////////////////////////////////////////////////////////////// -_u16 MXL_ControlWrite(Tuner_struct *Tuner, _u16 ControlNum, _u32 value) +u16 MXL_ControlWrite(Tuner_struct *Tuner, u16 ControlNum, u32 value) { - _u16 status = 0 ; + u16 status = 0 ; // Will write ALL Matching Control Name status += MXL_ControlWrite_Group( Tuner, ControlNum, value, 1 ) ; // Write Matching INIT Control status += MXL_ControlWrite_Group( Tuner, ControlNum, value, 2 ) ; // Write Matching CH Control @@ -4287,11 +3947,11 @@ _u16 MXL_ControlWrite(Tuner_struct *Tuner, _u16 ControlNum, _u32 value) // 2 : Control name not found // // // /////////////////////////////////////////////////////////////////////////////// -_u16 MXL_ControlWrite_Group(Tuner_struct *Tuner, _u16 controlNum, _u32 value, _u16 controlGroup) +u16 MXL_ControlWrite_Group(Tuner_struct *Tuner, u16 controlNum, u32 value, u16 controlGroup) { - _u16 i, j, k ; - _u32 highLimit ; - _u32 ctrlVal ; + u16 i, j, k ; + u32 highLimit ; + u32 ctrlVal ; if( controlGroup == 1) // Initial Control { @@ -4304,11 +3964,11 @@ _u16 MXL_ControlWrite_Group(Tuner_struct *Tuner, _u16 controlNum, _u32 value, _u { for( j=0; jInit_Ctrl[i].size; j++) { - Tuner->Init_Ctrl[i].val[j] = (_u8)((value >> j) & 0x01) ; + Tuner->Init_Ctrl[i].val[j] = (u8)((value >> j) & 0x01) ; // change the register map accordingly - MXL_RegWriteBit( Tuner, (_u8)(Tuner->Init_Ctrl[i].addr[j]), - (_u8)(Tuner->Init_Ctrl[i].bit[j]), - (_u8)((value>>j) & 0x01) ) ; + MXL_RegWriteBit( Tuner, (u8)(Tuner->Init_Ctrl[i].addr[j]), + (u8)(Tuner->Init_Ctrl[i].bit[j]), + (u8)((value>>j) & 0x01) ) ; } ctrlVal = 0 ; for(k=0; kInit_Ctrl[i].size; k++) @@ -4334,11 +3994,11 @@ _u16 MXL_ControlWrite_Group(Tuner_struct *Tuner, _u16 controlNum, _u32 value, _u { for( j=0; jCH_Ctrl[i].size; j++) { - Tuner->CH_Ctrl[i].val[j] = (_u8)((value >> j) & 0x01) ; + Tuner->CH_Ctrl[i].val[j] = (u8)((value >> j) & 0x01) ; // change the register map accordingly - MXL_RegWriteBit( Tuner, (_u8)(Tuner->CH_Ctrl[i].addr[j]), - (_u8)(Tuner->CH_Ctrl[i].bit[j]), - (_u8)((value>>j) & 0x01) ) ; + MXL_RegWriteBit( Tuner, (u8)(Tuner->CH_Ctrl[i].addr[j]), + (u8)(Tuner->CH_Ctrl[i].bit[j]), + (u8)((value>>j) & 0x01) ) ; } ctrlVal = 0 ; for(k=0; kCH_Ctrl[i].size; k++) @@ -4365,11 +4025,11 @@ _u16 MXL_ControlWrite_Group(Tuner_struct *Tuner, _u16 controlNum, _u32 value, _u { for( j=0; jMXL_Ctrl[i].size; j++) { - Tuner->MXL_Ctrl[i].val[j] = (_u8)((value >> j) & 0x01) ; + Tuner->MXL_Ctrl[i].val[j] = (u8)((value >> j) & 0x01) ; // change the register map accordingly - MXL_RegWriteBit( Tuner, (_u8)(Tuner->MXL_Ctrl[i].addr[j]), - (_u8)(Tuner->MXL_Ctrl[i].bit[j]), - (_u8)((value>>j) & 0x01) ) ; + MXL_RegWriteBit( Tuner, (u8)(Tuner->MXL_Ctrl[i].addr[j]), + (u8)(Tuner->MXL_Ctrl[i].bit[j]), + (u8)((value>>j) & 0x01) ) ; } ctrlVal = 0 ; for(k=0; kMXL_Ctrl[i].size; k++) @@ -4413,7 +4073,7 @@ _u16 MXL_ControlWrite_Group(Tuner_struct *Tuner, _u16 controlNum, _u32 value, _u // -1 : Invalid Register Address // // // /////////////////////////////////////////////////////////////////////////////// -_u16 MXL_RegWrite(Tuner_struct *Tuner, _u8 RegNum, _u8 RegVal) +u16 MXL_RegWrite(Tuner_struct *Tuner, u8 RegNum, u8 RegVal) { int i ; @@ -4453,7 +4113,7 @@ _u16 MXL_RegWrite(Tuner_struct *Tuner, _u8 RegNum, _u8 RegVal) // -1 : Invalid Register Address // // // /////////////////////////////////////////////////////////////////////////////// -_u16 MXL_RegRead(Tuner_struct *Tuner, _u8 RegNum, _u8 *RegVal) +u16 MXL_RegRead(Tuner_struct *Tuner, u8 RegNum, u8 *RegVal) { int i ; @@ -4461,7 +4121,7 @@ _u16 MXL_RegRead(Tuner_struct *Tuner, _u8 RegNum, _u8 *RegVal) { if (RegNum == Tuner->TunerRegs[i].Reg_Num ) { - *RegVal = (_u8)(Tuner->TunerRegs[i].Reg_Val) ; + *RegVal = (u8)(Tuner->TunerRegs[i].Reg_Val) ; return 0 ; } } @@ -4490,10 +4150,10 @@ _u16 MXL_RegRead(Tuner_struct *Tuner, _u8 RegNum, _u8 *RegVal) // -1 : Invalid control name // // // /////////////////////////////////////////////////////////////////////////////// -_u16 MXL_ControlRead(Tuner_struct *Tuner, _u16 controlNum, _u32 * value) +u16 MXL_ControlRead(Tuner_struct *Tuner, u16 controlNum, u32 * value) { - _u32 ctrlVal ; - _u16 i, k ; + u32 ctrlVal ; + u16 i, k ; for (i=0; iInit_Ctrl_Num ; i++) { @@ -4539,7 +4199,7 @@ _u16 MXL_ControlRead(Tuner_struct *Tuner, _u16 controlNum, _u32 * value) // Function: MXL_ControlRegRead // // // // Description: Retrieve the register addresses and count related to a // -// a specific control name // +// a specific control name // // // // Globals: // // NONE // @@ -4550,24 +4210,24 @@ _u16 MXL_ControlRead(Tuner_struct *Tuner, _u16 controlNum, _u32 * value) // // // Outputs: // // RegNum : returned register address array // -// count : returned register count related to a control // +// count : returned register count related to a control // // // // Return: // // 0 : Successful read // // -1 : Invalid control name // // // /////////////////////////////////////////////////////////////////////////////// -_u16 MXL_ControlRegRead(Tuner_struct *Tuner, _u16 controlNum, _u8 *RegNum, int * count) +u16 MXL_ControlRegRead(Tuner_struct *Tuner, u16 controlNum, u8 *RegNum, int * count) { - _u16 i, j, k ; - _u16 Count ; + u16 i, j, k ; + u16 Count ; for (i=0; iInit_Ctrl_Num ; i++) { if ( controlNum == Tuner->Init_Ctrl[i].Ctrl_Num ) { Count = 1 ; - RegNum[0] = (_u8)(Tuner->Init_Ctrl[i].addr[0]) ; + RegNum[0] = (u8)(Tuner->Init_Ctrl[i].addr[0]) ; for(k=1; kInit_Ctrl[i].size; k++) { @@ -4576,7 +4236,7 @@ _u16 MXL_ControlRegRead(Tuner_struct *Tuner, _u16 controlNum, _u8 *RegNum, int * if (Tuner->Init_Ctrl[i].addr[k] != RegNum[j]) { Count ++ ; - RegNum[Count-1] = (_u8)(Tuner->Init_Ctrl[i].addr[k]) ; + RegNum[Count-1] = (u8)(Tuner->Init_Ctrl[i].addr[k]) ; } } @@ -4590,7 +4250,7 @@ _u16 MXL_ControlRegRead(Tuner_struct *Tuner, _u16 controlNum, _u8 *RegNum, int * if ( controlNum == Tuner->CH_Ctrl[i].Ctrl_Num ) { Count = 1 ; - RegNum[0] = (_u8)(Tuner->CH_Ctrl[i].addr[0]) ; + RegNum[0] = (u8)(Tuner->CH_Ctrl[i].addr[0]) ; for(k=1; kCH_Ctrl[i].size; k++) { @@ -4599,7 +4259,7 @@ _u16 MXL_ControlRegRead(Tuner_struct *Tuner, _u16 controlNum, _u8 *RegNum, int * if (Tuner->CH_Ctrl[i].addr[k] != RegNum[j]) { Count ++ ; - RegNum[Count-1] = (_u8)(Tuner->CH_Ctrl[i].addr[k]) ; + RegNum[Count-1] = (u8)(Tuner->CH_Ctrl[i].addr[k]) ; } } } @@ -4613,7 +4273,7 @@ _u16 MXL_ControlRegRead(Tuner_struct *Tuner, _u16 controlNum, _u8 *RegNum, int * if ( controlNum == Tuner->MXL_Ctrl[i].Ctrl_Num ) { Count = 1 ; - RegNum[0] = (_u8)(Tuner->MXL_Ctrl[i].addr[0]) ; + RegNum[0] = (u8)(Tuner->MXL_Ctrl[i].addr[0]) ; for(k=1; kMXL_Ctrl[i].size; k++) { @@ -4622,7 +4282,7 @@ _u16 MXL_ControlRegRead(Tuner_struct *Tuner, _u16 controlNum, _u8 *RegNum, int * if (Tuner->MXL_Ctrl[i].addr[k] != RegNum[j]) { Count ++ ; - RegNum[Count-1] = (_u8)Tuner->MXL_Ctrl[i].addr[k] ; + RegNum[Count-1] = (u8)Tuner->MXL_Ctrl[i].addr[k] ; } } } @@ -4648,8 +4308,8 @@ _u16 MXL_ControlRegRead(Tuner_struct *Tuner, _u16 controlNum, _u8 *RegNum, int * // Inputs: // // Tuner_struct : structure defined at higher level // // address : register address // -// bit : register bit number // -// bitVal : register bit value // +// bit : register bit number // +// bitVal : register bit value // // // // Outputs: // // NONE // @@ -4659,16 +4319,16 @@ _u16 MXL_ControlRegRead(Tuner_struct *Tuner, _u16 controlNum, _u8 *RegNum, int * // // /////////////////////////////////////////////////////////////////////////////// -void MXL_RegWriteBit(Tuner_struct *Tuner, _u8 address, _u8 bit, _u8 bitVal) +void MXL_RegWriteBit(Tuner_struct *Tuner, u8 address, u8 bit, u8 bitVal) { int i ; // Declare Local Constants - const _u8 AND_MAP[8] = { + const u8 AND_MAP[8] = { 0xFE, 0xFD, 0xFB, 0xF7, 0xEF, 0xDF, 0xBF, 0x7F } ; - const _u8 OR_MAP[8] = { + const u8 OR_MAP[8] = { 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80 } ; @@ -4707,7 +4367,7 @@ void MXL_RegWriteBit(Tuner_struct *Tuner, _u8 address, _u8 bit, _u8 bitVal) // Computed value // // // /////////////////////////////////////////////////////////////////////////////// -_u32 MXL_Ceiling( _u32 value, _u32 resolution ) +u32 MXL_Ceiling( u32 value, u32 resolution ) { return (value/resolution + (value%resolution > 0 ? 1 : 0)) ; }; @@ -4715,15 +4375,15 @@ _u32 MXL_Ceiling( _u32 value, _u32 resolution ) // // Retrieve the Initialzation Registers // -_u16 MXL_GetInitRegister(Tuner_struct *Tuner, _u8 * RegNum, _u8 *RegVal, int *count) +u16 MXL_GetInitRegister(Tuner_struct *Tuner, u8 * RegNum, u8 *RegVal, int *count) { - _u16 status = 0; + u16 status = 0; int i ; - _u8 RegAddr[] = {11, 12, 13, 22, 32, 43, 44, 53, 56, 59, 73, + u8 RegAddr[] = {11, 12, 13, 22, 32, 43, 44, 53, 56, 59, 73, 76, 77, 91, 134, 135, 137, 147, 156, 166, 167, 168, 25 } ; - *count = sizeof(RegAddr) / sizeof(_u8) ; + *count = sizeof(RegAddr) / sizeof(u8) ; status += MXL_BlockInit(Tuner) ; @@ -4736,24 +4396,24 @@ _u16 MXL_GetInitRegister(Tuner_struct *Tuner, _u8 * RegNum, _u8 *RegVal, int *co return status ; } -_u16 MXL_GetCHRegister(Tuner_struct *Tuner, _u8 * RegNum, _u8 *RegVal, int *count) +u16 MXL_GetCHRegister(Tuner_struct *Tuner, u8 * RegNum, u8 *RegVal, int *count) { - _u16 status = 0; + u16 status = 0; int i ; //add 77, 166, 167, 168 register for 2.6.12 #ifdef _MXL_PRODUCTION - _u8 RegAddr[] = {14, 15, 16, 17, 22, 43, 65, 68, 69, 70, 73, 92, 93, 106, - 107, 108, 109, 110, 111, 112, 136, 138, 149, 77, 166, 167, 168 } ; + u8 RegAddr[] = {14, 15, 16, 17, 22, 43, 65, 68, 69, 70, 73, 92, 93, 106, + 107, 108, 109, 110, 111, 112, 136, 138, 149, 77, 166, 167, 168 } ; #else - _u8 RegAddr[] = {14, 15, 16, 17, 22, 43, 68, 69, 70, 73, 92, 93, 106, - 107, 108, 109, 110, 111, 112, 136, 138, 149, 77, 166, 167, 168 } ; - //_u8 RegAddr[171]; + u8 RegAddr[] = {14, 15, 16, 17, 22, 43, 68, 69, 70, 73, 92, 93, 106, + 107, 108, 109, 110, 111, 112, 136, 138, 149, 77, 166, 167, 168 } ; + //u8 RegAddr[171]; //for (i=0; i<=170; i++) // RegAddr[i] = i; #endif - *count = sizeof(RegAddr) / sizeof(_u8) ; + *count = sizeof(RegAddr) / sizeof(u8) ; for (i=0 ; i< *count; i++) { @@ -4765,14 +4425,14 @@ _u16 MXL_GetCHRegister(Tuner_struct *Tuner, _u8 * RegNum, _u8 *RegVal, int *coun } -_u16 MXL_GetCHRegister_ZeroIF(Tuner_struct *Tuner, _u8 * RegNum, _u8 *RegVal, int *count) +u16 MXL_GetCHRegister_ZeroIF(Tuner_struct *Tuner, u8 * RegNum, u8 *RegVal, int *count) { - _u16 status = 0 ; + u16 status = 0 ; int i ; - _u8 RegAddr[] = {43, 136} ; + u8 RegAddr[] = {43, 136} ; - *count = sizeof(RegAddr) / sizeof(_u8) ; + *count = sizeof(RegAddr) / sizeof(u8) ; for (i=0; i<*count; i++) { @@ -4783,14 +4443,14 @@ _u16 MXL_GetCHRegister_ZeroIF(Tuner_struct *Tuner, _u8 * RegNum, _u8 *RegVal, in } -_u16 MXL_GetCHRegister_LowIF(Tuner_struct *Tuner, _u8 * RegNum, _u8 *RegVal, int *count) +u16 MXL_GetCHRegister_LowIF(Tuner_struct *Tuner, u8 * RegNum, u8 *RegVal, int *count) { - _u16 status = 0 ; + u16 status = 0 ; int i ; - _u8 RegAddr[] = {138} ; + u8 RegAddr[] = {138} ; - *count = sizeof(RegAddr) / sizeof(_u8) ; + *count = sizeof(RegAddr) / sizeof(u8) ; for (i=0; i<*count; i++) { @@ -4801,7 +4461,7 @@ _u16 MXL_GetCHRegister_LowIF(Tuner_struct *Tuner, _u8 * RegNum, _u8 *RegVal, int } -_u16 MXL_GetMasterControl(_u8 *MasterReg, int state) +u16 MXL_GetMasterControl(u8 *MasterReg, int state) { if (state == 1) // Load_Start *MasterReg = 0xF3 ; @@ -4816,168 +4476,143 @@ _u16 MXL_GetMasterControl(_u8 *MasterReg, int state) } #ifdef _MXL_PRODUCTION -_u16 MXL_VCORange_Test(Tuner_struct *Tuner, int VCO_Range) -{ - _u16 status = 0 ; - - if (VCO_Range == 1) { - status += MXL_ControlWrite(Tuner, RFSYN_EN_DIV, 1) ; - status += MXL_ControlWrite(Tuner, RFSYN_EN_OUTMUX, 0 ) ; - status += MXL_ControlWrite(Tuner, RFSYN_SEL_DIVM, 0 ) ; - status += MXL_ControlWrite(Tuner, RFSYN_DIVM, 1 ) ; - status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_OUT, 1 ) ; - status += MXL_ControlWrite(Tuner, RFSYN_RF_DIV_BIAS, 1 ) ; - status += MXL_ControlWrite(Tuner, DN_SEL_FREQ, 0 ) ; - if (Tuner->Mode == 0 && Tuner->IF_Mode == 1) // Analog Low IF Mode - { - status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 1 ) ; - status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 8 ) ; - status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 56 ) ; - status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_RF, 180224 ) ; - } - if (Tuner->Mode == 0 && Tuner->IF_Mode == 0) // Analog Zero IF Mode - { - status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 1 ) ; - status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 8 ) ; - status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 56 ) ; - status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_RF, 222822 ) ; - } - if (Tuner->Mode == 1) // Digital Mode - { - status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 1 ) ; - status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 8 ) ; - status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 56 ) ; - status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_RF, 229376 ) ; - } - } - - if (VCO_Range == 2) { - status += MXL_ControlWrite(Tuner, RFSYN_EN_DIV, 1) ; - status += MXL_ControlWrite(Tuner, RFSYN_EN_OUTMUX, 0 ) ; - status += MXL_ControlWrite(Tuner, RFSYN_SEL_DIVM, 0 ) ; - status += MXL_ControlWrite(Tuner, RFSYN_DIVM, 1 ) ; - status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_OUT, 1 ) ; - status += MXL_ControlWrite(Tuner, RFSYN_RF_DIV_BIAS, 1 ) ; - status += MXL_ControlWrite(Tuner, DN_SEL_FREQ, 0 ) ; - status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 1 ) ; - status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 40 ) ; - status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 41 ) ; - if (Tuner->Mode == 0 && Tuner->IF_Mode == 1) // Analog Low IF Mode - { - status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 1 ) ; - status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 40 ) ; - status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 42 ) ; - status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_RF, 206438 ) ; - } - if (Tuner->Mode == 0 && Tuner->IF_Mode == 0) // Analog Zero IF Mode - { - status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 1 ) ; - status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 40 ) ; - status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 42 ) ; - status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_RF, 206438 ) ; - } - if (Tuner->Mode == 1) // Digital Mode - { - status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 1 ) ; - status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 40 ) ; - status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 41 ) ; - status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_RF, 16384 ) ; - } - } - - if (VCO_Range == 3) { - status += MXL_ControlWrite(Tuner, RFSYN_EN_DIV, 1) ; - status += MXL_ControlWrite(Tuner, RFSYN_EN_OUTMUX, 0 ) ; - status += MXL_ControlWrite(Tuner, RFSYN_SEL_DIVM, 0 ) ; - status += MXL_ControlWrite(Tuner, RFSYN_DIVM, 1 ) ; - status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_OUT, 1 ) ; - status += MXL_ControlWrite(Tuner, RFSYN_RF_DIV_BIAS, 1 ) ; - status += MXL_ControlWrite(Tuner, DN_SEL_FREQ, 0 ) ; - status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 0 ) ; - status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 8 ) ; - status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 42 ) ; - if (Tuner->Mode == 0 && Tuner->IF_Mode == 1) // Analog Low IF Mode - { - status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 0 ) ; - status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 8 ) ; - status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 44 ) ; - status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_RF, 173670 ) ; - } - if (Tuner->Mode == 0 && Tuner->IF_Mode == 0) // Analog Zero IF Mode - { - status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 0 ) ; - status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 8 ) ; - status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 44 ) ; - status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_RF, 173670 ) ; - } - if (Tuner->Mode == 1) // Digital Mode - { - status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 0 ) ; - status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 8 ) ; - status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 42 ) ; - status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_RF, 245760 ) ; - } - } - - if (VCO_Range == 4) { - status += MXL_ControlWrite(Tuner, RFSYN_EN_DIV, 1) ; - status += MXL_ControlWrite(Tuner, RFSYN_EN_OUTMUX, 0 ) ; - status += MXL_ControlWrite(Tuner, RFSYN_SEL_DIVM, 0 ) ; - status += MXL_ControlWrite(Tuner, RFSYN_DIVM, 1 ) ; - status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_OUT, 1 ) ; - status += MXL_ControlWrite(Tuner, RFSYN_RF_DIV_BIAS, 1 ) ; - status += MXL_ControlWrite(Tuner, DN_SEL_FREQ, 0 ) ; - status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 0 ) ; - status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 40 ) ; - status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 27 ) ; - if (Tuner->Mode == 0 && Tuner->IF_Mode == 1) // Analog Low IF Mode - { - status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 0 ) ; - status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 40 ) ; - status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 27 ) ; - status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_RF, 206438 ) ; - } - if (Tuner->Mode == 0 && Tuner->IF_Mode == 0) // Analog Zero IF Mode - { - status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 0 ) ; - status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 40 ) ; - status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 27 ) ; - status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_RF, 206438 ) ; - } - if (Tuner->Mode == 1) // Digital Mode - { - status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 0 ) ; - status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 40 ) ; - status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 27 ) ; - status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_RF, 212992 ) ; - } - } - - return status ; -} - -_u16 MXL_Hystersis_Test(Tuner_struct *Tuner, int Hystersis) +u16 MXL_VCORange_Test(Tuner_struct *Tuner, int VCO_Range) { - _u16 status = 0 ; - - if (Hystersis == 1) - status += MXL_ControlWrite(Tuner, DN_BYPASS_AGC_I2C, 1) ; - - return status ; -} -#endif - - - - - - + u16 status = 0 ; + + if (VCO_Range == 1) { + status += MXL_ControlWrite(Tuner, RFSYN_EN_DIV, 1); + status += MXL_ControlWrite(Tuner, RFSYN_EN_OUTMUX, 0); + status += MXL_ControlWrite(Tuner, RFSYN_SEL_DIVM, 0); + status += MXL_ControlWrite(Tuner, RFSYN_DIVM, 1); + status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_OUT, 1); + status += MXL_ControlWrite(Tuner, RFSYN_RF_DIV_BIAS, 1); + status += MXL_ControlWrite(Tuner, DN_SEL_FREQ, 0); + if (Tuner->Mode == 0 && Tuner->IF_Mode == 1) // Analog Low IF Mode { + status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 1); + status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 8); + status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 56); + status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_RF, 180224); + } + if (Tuner->Mode == 0 && Tuner->IF_Mode == 0) // Analog Zero IF Mode { + status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 1 ) ; + status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 8 ) ; + status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 56 ) ; + status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_RF, 222822 ) ; + } + if (Tuner->Mode == 1) // Digital Mode { + status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 1 ) ; + status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 8 ) ; + status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 56 ) ; + status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_RF, 229376 ) ; + } + } + if (VCO_Range == 2) { + status += MXL_ControlWrite(Tuner, RFSYN_EN_DIV, 1); + status += MXL_ControlWrite(Tuner, RFSYN_EN_OUTMUX, 0); + status += MXL_ControlWrite(Tuner, RFSYN_SEL_DIVM, 0); + status += MXL_ControlWrite(Tuner, RFSYN_DIVM, 1); + status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_OUT, 1); + status += MXL_ControlWrite(Tuner, RFSYN_RF_DIV_BIAS, 1); + status += MXL_ControlWrite(Tuner, DN_SEL_FREQ, 0); + status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 1); + status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 40); + status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 41); + if (Tuner->Mode == 0 && Tuner->IF_Mode == 1) // Analog Low IF Mode { + status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 1); + status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 40); + status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 42); + status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_RF, 206438); + } + if (Tuner->Mode == 0 && Tuner->IF_Mode == 0) // Analog Zero IF Mode { + status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 1); + status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 40); + status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 42); + status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_RF, 206438); + } + if (Tuner->Mode == 1) // Digital Mode { + status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 1); + status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 40); + status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 41); + status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_RF, 16384); + } + } + if (VCO_Range == 3) { + status += MXL_ControlWrite(Tuner, RFSYN_EN_DIV, 1); + status += MXL_ControlWrite(Tuner, RFSYN_EN_OUTMUX, 0); + status += MXL_ControlWrite(Tuner, RFSYN_SEL_DIVM, 0); + status += MXL_ControlWrite(Tuner, RFSYN_DIVM, 1); + status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_OUT, 1); + status += MXL_ControlWrite(Tuner, RFSYN_RF_DIV_BIAS, 1); + status += MXL_ControlWrite(Tuner, DN_SEL_FREQ, 0); + status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 0); + status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 8); + status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 42); + if (Tuner->Mode == 0 && Tuner->IF_Mode == 1) // Analog Low IF Mode { + status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 0); + status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 8); + status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 44); + status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_RF, 173670); + } + if (Tuner->Mode == 0 && Tuner->IF_Mode == 0) // Analog Zero IF Mode { + status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 0); + status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 8); + status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 44); + status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_RF, 173670); + } + if (Tuner->Mode == 1) // Digital Mode { + status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 0); + status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 8); + status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 42); + status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_RF, 245760); + } + } + if (VCO_Range == 4) { + status += MXL_ControlWrite(Tuner, RFSYN_EN_DIV, 1); + status += MXL_ControlWrite(Tuner, RFSYN_EN_OUTMUX, 0); + status += MXL_ControlWrite(Tuner, RFSYN_SEL_DIVM, 0); + status += MXL_ControlWrite(Tuner, RFSYN_DIVM, 1); + status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_OUT, 1); + status += MXL_ControlWrite(Tuner, RFSYN_RF_DIV_BIAS, 1); + status += MXL_ControlWrite(Tuner, DN_SEL_FREQ, 0); + status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 0); + status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 40); + status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 27); + if (Tuner->Mode == 0 && Tuner->IF_Mode == 1) // Analog Low IF Mode { + status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 0); + status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 40); + status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 27); + status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_RF, 206438); + } + if (Tuner->Mode == 0 && Tuner->IF_Mode == 0) // Analog Zero IF Mode { + status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 0); + status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 40); + status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 27); + status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_RF, 206438); + } + if (Tuner->Mode == 1) // Digital Mode { + status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 0); + status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 40); + status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 27); + status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_RF, 212992); + } + } + return status; +} +u16 MXL_Hystersis_Test(Tuner_struct *Tuner, int Hystersis) +{ + u16 status = 0; + if (Hystersis == 1) + status += MXL_ControlWrite(Tuner, DN_BYPASS_AGC_I2C, 1); + return status; +} +#endif -- cgit v1.2.3 From 58f79fdbd014c9b95bddedcb001f57e498fefd07 Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Thu, 1 May 2008 01:45:44 -0400 Subject: mxl5005s: Cleanup #3 From: Steven Toth Cleanup #3 Signed-off-by: Steven Toth Signed-off-by: Mauro Carvalho Chehab --- linux/drivers/media/common/tuners/mxl5005s.c | 5376 +++++++++++++------------- linux/drivers/media/common/tuners/mxl5005s.h | 165 - 2 files changed, 2681 insertions(+), 2860 deletions(-) (limited to 'linux/drivers/media/common/tuners') diff --git a/linux/drivers/media/common/tuners/mxl5005s.c b/linux/drivers/media/common/tuners/mxl5005s.c index 2af14de73..619183680 100644 --- a/linux/drivers/media/common/tuners/mxl5005s.c +++ b/linux/drivers/media/common/tuners/mxl5005s.c @@ -24,7 +24,62 @@ #include "mxl5005s.h" +/* MXL5005 Tuner Control Struct */ +typedef struct _TunerControl_struct { + u16 Ctrl_Num; /* Control Number */ + u16 size; /* Number of bits to represent Value */ + u16 addr[25]; /* Array of Tuner Register Address for each bit position */ + u16 bit[25]; /* Array of bit position in Register Address for each bit position */ + u16 val[25]; /* Binary representation of Value */ +} TunerControl_struct; + +/* MXL5005 Tuner Struct */ +struct mxl5005s_state +{ + u8 Mode; /* 0: Analog Mode ; 1: Digital Mode */ + u8 IF_Mode; /* for Analog Mode, 0: zero IF; 1: low IF */ + u32 Chan_Bandwidth; /* filter channel bandwidth (6, 7, 8) */ + u32 IF_OUT; /* Desired IF Out Frequency */ + u16 IF_OUT_LOAD; /* IF Out Load Resistor (200/300 Ohms) */ + u32 RF_IN; /* RF Input Frequency */ + u32 Fxtal; /* XTAL Frequency */ + u8 AGC_Mode; /* AGC Mode 0: Dual AGC; 1: Single AGC */ + u16 TOP; /* Value: take over point */ + u8 CLOCK_OUT; /* 0: turn off clock out; 1: turn on clock out */ + u8 DIV_OUT; /* 4MHz or 16MHz */ + u8 CAPSELECT; /* 0: disable On-Chip pulling cap; 1: enable */ + u8 EN_RSSI; /* 0: disable RSSI; 1: enable RSSI */ + u8 Mod_Type; /* Modulation Type; */ + /* 0 - Default; 1 - DVB-T; 2 - ATSC; 3 - QAM; 4 - Analog Cable */ + u8 TF_Type; /* Tracking Filter Type */ + /* 0 - Default; 1 - Off; 2 - Type C; 3 - Type C-H */ + + /* Calculated Settings */ + u32 RF_LO; /* Synth RF LO Frequency */ + u32 IF_LO; /* Synth IF LO Frequency */ + u32 TG_LO; /* Synth TG_LO Frequency */ + + /* Pointers to ControlName Arrays */ + u16 Init_Ctrl_Num; /* Number of INIT Control Names */ + TunerControl_struct + Init_Ctrl[INITCTRL_NUM]; /* INIT Control Names Array Pointer */ + + u16 CH_Ctrl_Num; /* Number of CH Control Names */ + TunerControl_struct + CH_Ctrl[CHCTRL_NUM]; /* CH Control Name Array Pointer */ + + u16 MXL_Ctrl_Num; /* Number of MXL Control Names */ + TunerControl_struct + MXL_Ctrl[MXLCTRL_NUM]; /* MXL Control Name Array Pointer */ + + /* Pointer to Tuner Register Array */ + u16 TunerRegs_Num; /* Number of Tuner Registers */ + TunerReg_struct + TunerRegs[TUNER_REGS_NUM]; /* Tuner Register Array Pointer */ + +}; +#if 0 void BuildMxl5005sModule( TUNER_MODULE **ppTuner, TUNER_MODULE *pTunerModuleMemory, @@ -182,6 +237,7 @@ int mxl5005s_GetDeviceAddr( error_status_get_tuner_i2c_device_addr: return FUNCTION_ERROR; } +#endif int mxl5005s_Initialize( struct dvb_usb_device* dib, @@ -310,24 +366,19 @@ error_status_set_tuner_registers: return FUNCTION_ERROR; } -int mxl5005s_GetRfFreqHz( - struct dvb_usb_device* dib, - TUNER_MODULE *pTuner, - unsigned long *pRfFreqHz - ) +// DONE +int mxl5005s_GetRfFreqHz(struct dvb_frontend *fe, unsigned long *pRfFreqHz) { - // Get tuner RF frequency in Hz from tuner module. - if(pTuner->IsRfFreqHzSet != YES) - goto error_status_get_tuner_rf_frequency; - - *pRfFreqHz = pTuner->RfFreqHz; - - - return FUNCTION_SUCCESS; + struct mxl5005s_state *state = fe->demodulator_priv; + int ret = -1; + /* Get tuner RF frequency in Hz from tuner module. */ + if(state->IsRfFreqHzSet == YES) { + *pRfFreqHz = state->RfFreqHz; + ret = 0; + } -error_status_get_tuner_rf_frequency: - return FUNCTION_ERROR; + return -1; } int mxl5005s_SetRegsWithTable( @@ -394,14 +445,13 @@ error_status_set_tuner_registers: return FUNCTION_ERROR; } -int mxl5005s_SetRegsWithTable( - struct dvb_usb_device* dib, - TUNER_MODULE *pTuner, +int mxl5005s_SetRegsWithTable(struct dvb_frontend *fe, unsigned char *pAddrTable, unsigned char *pByteTable, int TableLen ) { + struct mxl5005s_state *state = fe->demodulator_priv; int i; u8 end_two_bytes_buf[]={ 0 , 0 }; u8 tuner_addr=0x00; @@ -423,31 +473,21 @@ int mxl5005s_SetRegsWithTable( return FUNCTION_SUCCESS; } -int mxl5005s_SetRegMaskBits( - struct dvb_usb_device* dib, - TUNER_MODULE *pTuner, +int mxl5005s_SetRegMaskBits(struct dvb_frontend *fe, unsigned char RegAddr, unsigned char Msb, unsigned char Lsb, const unsigned char WritingValue ) { - MXL5005S_EXTRA_MODULE *pExtra; - + struct mxl5005s_state *state = fe->demodulator_priv; int i; unsigned char Mask; unsigned char Shift; - unsigned char RegByte; - - - // Get tuner extra module. - pExtra = (MXL5005S_EXTRA_MODULE *)pTuner->pExtra; - - - // Generate mask and shift according to MSB and LSB. + /* Generate mask and shift according to MSB and LSB. */ Mask = 0; for(i = Lsb; i < (unsigned char)(Msb + 1); i++) Mask |= 0x1 << i; @@ -455,20 +495,17 @@ int mxl5005s_SetRegMaskBits( Shift = Lsb; - // Get tuner register byte according to register adddress. + /* Get tuner register byte according to register adddress. */ MXL_RegRead(&pExtra->MxlDefinedTunerStructure, RegAddr, &RegByte); - - // Reserve register byte unmask bit with mask and inlay writing value into it. + /* Reserve register byte unmask bit with mask and inlay writing value into it. */ RegByte &= ~Mask; RegByte |= (WritingValue << Shift) & Mask; - - // Update tuner register byte table. + /* Update tuner register byte table. */ MXL_RegWrite(&pExtra->MxlDefinedTunerStructure, RegAddr, RegByte); - - // Write tuner register byte with writing byte. + /* Write tuner register byte with writing byte. */ if(pExtra->SetRegsWithTable( dib, pTuner, &RegAddr, &RegByte, LEN_1_BYTE) != FUNCTION_SUCCESS) goto error_status_set_tuner_registers; @@ -480,1350 +517,1321 @@ error_status_set_tuner_registers: return FUNCTION_ERROR; } -int mxl5005s_SetSpectrumMode( - struct dvb_usb_device* dib, - TUNER_MODULE *pTuner, - int SpectrumMode - ) +// DONE +int mxl5005s_SetSpectrumMode(struct dvb_frontend *fe, int SpectrumMode) { + struct mxl5005s_state *state = fe->demodulator_priv; static const unsigned char BbIqswapTable[SPECTRUM_MODE_NUM] = { - // BB_IQSWAP - 0, // Normal spectrum - 1, // Inverse spectrum + /* BB_IQSWAP */ + 0, /* Normal spectrum */ + 1, /* Inverse spectrum */ }; - - MXL5005S_EXTRA_MODULE *pExtra; - - - - // Get tuner extra module. - pExtra = (MXL5005S_EXTRA_MODULE *)pTuner->pExtra; - - - // Set BB_IQSWAP according to BB_IQSWAP table and spectrum mode. - if(pExtra->SetRegMaskBits(dib,pTuner, MXL5005S_BB_IQSWAP_ADDR, MXL5005S_BB_IQSWAP_MSB, - MXL5005S_BB_IQSWAP_LSB, BbIqswapTable[SpectrumMode]) != FUNCTION_SUCCESS) - goto error_status_set_tuner_registers; - + /* Set BB_IQSWAP according to BB_IQSWAP table and spectrum mode. */ + mxl5005s_SetRegMaskBits(fe, + MXL5005S_BB_IQSWAP_ADDR, + MXL5005S_BB_IQSWAP_MSB, + MXL5005S_BB_IQSWAP_LSB, + BbIqswapTable[SpectrumMode]); return FUNCTION_SUCCESS; - - -error_status_set_tuner_registers: - return FUNCTION_ERROR; } -int mxl5005s_SetBandwidthHz( - struct dvb_usb_device* dib, - TUNER_MODULE *pTuner, - unsigned long BandwidthHz - ) +// DONE +int mxl5005s_SetBandwidthHz(struct dvb_frontend *fe, unsigned long BandwidthHz) { - MXL5005S_EXTRA_MODULE *pExtra; + struct mxl5005s_state *state = fe->demodulator_priv; unsigned char BbDlpfBandsel; - - - // Get tuner extra module. - pExtra = (MXL5005S_EXTRA_MODULE *)pTuner->pExtra; - - - // Set BB_DLPF_BANDSEL according to bandwidth. + /* Set BB_DLPF_BANDSEL according to bandwidth. */ switch(BandwidthHz) { default: - case MXL5005S_BANDWIDTH_6MHZ: BbDlpfBandsel = 3; break; - case MXL5005S_BANDWIDTH_7MHZ: BbDlpfBandsel = 2; break; - case MXL5005S_BANDWIDTH_8MHZ: BbDlpfBandsel = 0; break; + case MXL5005S_BANDWIDTH_6MHZ: + BbDlpfBandsel = 3; + break; + case MXL5005S_BANDWIDTH_7MHZ: + BbDlpfBandsel = 2; + break; + case MXL5005S_BANDWIDTH_8MHZ: + BbDlpfBandsel = 0; + break; } if(pExtra->SetRegMaskBits(dib,pTuner, MXL5005S_BB_DLPF_BANDSEL_ADDR, MXL5005S_BB_DLPF_BANDSEL_MSB, - MXL5005S_BB_DLPF_BANDSEL_LSB, BbDlpfBandsel) != FUNCTION_SUCCESS) + MXL5005S_BB_DLPF_BANDSEL_LSB, BbDlpfBandsel) != 0) goto error_status_set_tuner_registers; - return FUNCTION_SUCCESS; + return 0; error_status_set_tuner_registers: - return FUNCTION_ERROR; -} - -void mxl5005s_SetI2cBridgeModuleTunerArg(TUNER_MODULE *pTuner) -{ - I2C_BRIDGE_MODULE *pI2cBridge; - - - - // Get I2C bridge module. - pI2cBridge = pTuner->pI2cBridge; - - // Set I2C bridge module tuner arguments. - pI2cBridge->pTunerDeviceAddr = &pTuner->DeviceAddr; - - - return; + return -1; } // The following context is source code provided by MaxLinear. // MaxLinear source code - MXL5005_Initialize.cpp -u16 MXL5005_RegisterInit(Tuner_struct *Tuner) +// DONE +u16 MXL5005_RegisterInit(struct dvb_frontend *fe) { - Tuner->TunerRegs_Num = TUNER_REGS_NUM ; -// Tuner->TunerRegs = (TunerReg_struct *) calloc( TUNER_REGS_NUM, sizeof(TunerReg_struct) ) ; + struct mxl5005s_state *state = fe->demodulator_priv; + state->TunerRegs_Num = TUNER_REGS_NUM ; +// state->TunerRegs = (TunerReg_struct *) calloc( TUNER_REGS_NUM, sizeof(TunerReg_struct) ) ; - Tuner->TunerRegs[0].Reg_Num = 9 ; - Tuner->TunerRegs[0].Reg_Val = 0x40 ; + state->TunerRegs[0].Reg_Num = 9 ; + state->TunerRegs[0].Reg_Val = 0x40 ; - Tuner->TunerRegs[1].Reg_Num = 11 ; - Tuner->TunerRegs[1].Reg_Val = 0x19 ; + state->TunerRegs[1].Reg_Num = 11 ; + state->TunerRegs[1].Reg_Val = 0x19 ; - Tuner->TunerRegs[2].Reg_Num = 12 ; - Tuner->TunerRegs[2].Reg_Val = 0x60 ; + state->TunerRegs[2].Reg_Num = 12 ; + state->TunerRegs[2].Reg_Val = 0x60 ; - Tuner->TunerRegs[3].Reg_Num = 13 ; - Tuner->TunerRegs[3].Reg_Val = 0x00 ; + state->TunerRegs[3].Reg_Num = 13 ; + state->TunerRegs[3].Reg_Val = 0x00 ; - Tuner->TunerRegs[4].Reg_Num = 14 ; - Tuner->TunerRegs[4].Reg_Val = 0x00 ; + state->TunerRegs[4].Reg_Num = 14 ; + state->TunerRegs[4].Reg_Val = 0x00 ; - Tuner->TunerRegs[5].Reg_Num = 15 ; - Tuner->TunerRegs[5].Reg_Val = 0xC0 ; + state->TunerRegs[5].Reg_Num = 15 ; + state->TunerRegs[5].Reg_Val = 0xC0 ; - Tuner->TunerRegs[6].Reg_Num = 16 ; - Tuner->TunerRegs[6].Reg_Val = 0x00 ; + state->TunerRegs[6].Reg_Num = 16 ; + state->TunerRegs[6].Reg_Val = 0x00 ; - Tuner->TunerRegs[7].Reg_Num = 17 ; - Tuner->TunerRegs[7].Reg_Val = 0x00 ; + state->TunerRegs[7].Reg_Num = 17 ; + state->TunerRegs[7].Reg_Val = 0x00 ; - Tuner->TunerRegs[8].Reg_Num = 18 ; - Tuner->TunerRegs[8].Reg_Val = 0x00 ; + state->TunerRegs[8].Reg_Num = 18 ; + state->TunerRegs[8].Reg_Val = 0x00 ; - Tuner->TunerRegs[9].Reg_Num = 19 ; - Tuner->TunerRegs[9].Reg_Val = 0x34 ; + state->TunerRegs[9].Reg_Num = 19 ; + state->TunerRegs[9].Reg_Val = 0x34 ; - Tuner->TunerRegs[10].Reg_Num = 21 ; - Tuner->TunerRegs[10].Reg_Val = 0x00 ; + state->TunerRegs[10].Reg_Num = 21 ; + state->TunerRegs[10].Reg_Val = 0x00 ; - Tuner->TunerRegs[11].Reg_Num = 22 ; - Tuner->TunerRegs[11].Reg_Val = 0x6B ; + state->TunerRegs[11].Reg_Num = 22 ; + state->TunerRegs[11].Reg_Val = 0x6B ; - Tuner->TunerRegs[12].Reg_Num = 23 ; - Tuner->TunerRegs[12].Reg_Val = 0x35 ; + state->TunerRegs[12].Reg_Num = 23 ; + state->TunerRegs[12].Reg_Val = 0x35 ; - Tuner->TunerRegs[13].Reg_Num = 24 ; - Tuner->TunerRegs[13].Reg_Val = 0x70 ; + state->TunerRegs[13].Reg_Num = 24 ; + state->TunerRegs[13].Reg_Val = 0x70 ; - Tuner->TunerRegs[14].Reg_Num = 25 ; - Tuner->TunerRegs[14].Reg_Val = 0x3E ; + state->TunerRegs[14].Reg_Num = 25 ; + state->TunerRegs[14].Reg_Val = 0x3E ; - Tuner->TunerRegs[15].Reg_Num = 26 ; - Tuner->TunerRegs[15].Reg_Val = 0x82 ; + state->TunerRegs[15].Reg_Num = 26 ; + state->TunerRegs[15].Reg_Val = 0x82 ; - Tuner->TunerRegs[16].Reg_Num = 31 ; - Tuner->TunerRegs[16].Reg_Val = 0x00 ; + state->TunerRegs[16].Reg_Num = 31 ; + state->TunerRegs[16].Reg_Val = 0x00 ; - Tuner->TunerRegs[17].Reg_Num = 32 ; - Tuner->TunerRegs[17].Reg_Val = 0x40 ; + state->TunerRegs[17].Reg_Num = 32 ; + state->TunerRegs[17].Reg_Val = 0x40 ; - Tuner->TunerRegs[18].Reg_Num = 33 ; - Tuner->TunerRegs[18].Reg_Val = 0x53 ; + state->TunerRegs[18].Reg_Num = 33 ; + state->TunerRegs[18].Reg_Val = 0x53 ; - Tuner->TunerRegs[19].Reg_Num = 34 ; - Tuner->TunerRegs[19].Reg_Val = 0x81 ; + state->TunerRegs[19].Reg_Num = 34 ; + state->TunerRegs[19].Reg_Val = 0x81 ; - Tuner->TunerRegs[20].Reg_Num = 35 ; - Tuner->TunerRegs[20].Reg_Val = 0xC9 ; + state->TunerRegs[20].Reg_Num = 35 ; + state->TunerRegs[20].Reg_Val = 0xC9 ; - Tuner->TunerRegs[21].Reg_Num = 36 ; - Tuner->TunerRegs[21].Reg_Val = 0x01 ; + state->TunerRegs[21].Reg_Num = 36 ; + state->TunerRegs[21].Reg_Val = 0x01 ; - Tuner->TunerRegs[22].Reg_Num = 37 ; - Tuner->TunerRegs[22].Reg_Val = 0x00 ; + state->TunerRegs[22].Reg_Num = 37 ; + state->TunerRegs[22].Reg_Val = 0x00 ; - Tuner->TunerRegs[23].Reg_Num = 41 ; - Tuner->TunerRegs[23].Reg_Val = 0x00 ; + state->TunerRegs[23].Reg_Num = 41 ; + state->TunerRegs[23].Reg_Val = 0x00 ; - Tuner->TunerRegs[24].Reg_Num = 42 ; - Tuner->TunerRegs[24].Reg_Val = 0xF8 ; + state->TunerRegs[24].Reg_Num = 42 ; + state->TunerRegs[24].Reg_Val = 0xF8 ; - Tuner->TunerRegs[25].Reg_Num = 43 ; - Tuner->TunerRegs[25].Reg_Val = 0x43 ; + state->TunerRegs[25].Reg_Num = 43 ; + state->TunerRegs[25].Reg_Val = 0x43 ; - Tuner->TunerRegs[26].Reg_Num = 44 ; - Tuner->TunerRegs[26].Reg_Val = 0x20 ; + state->TunerRegs[26].Reg_Num = 44 ; + state->TunerRegs[26].Reg_Val = 0x20 ; - Tuner->TunerRegs[27].Reg_Num = 45 ; - Tuner->TunerRegs[27].Reg_Val = 0x80 ; + state->TunerRegs[27].Reg_Num = 45 ; + state->TunerRegs[27].Reg_Val = 0x80 ; - Tuner->TunerRegs[28].Reg_Num = 46 ; - Tuner->TunerRegs[28].Reg_Val = 0x88 ; + state->TunerRegs[28].Reg_Num = 46 ; + state->TunerRegs[28].Reg_Val = 0x88 ; - Tuner->TunerRegs[29].Reg_Num = 47 ; - Tuner->TunerRegs[29].Reg_Val = 0x86 ; + state->TunerRegs[29].Reg_Num = 47 ; + state->TunerRegs[29].Reg_Val = 0x86 ; - Tuner->TunerRegs[30].Reg_Num = 48 ; - Tuner->TunerRegs[30].Reg_Val = 0x00 ; + state->TunerRegs[30].Reg_Num = 48 ; + state->TunerRegs[30].Reg_Val = 0x00 ; - Tuner->TunerRegs[31].Reg_Num = 49 ; - Tuner->TunerRegs[31].Reg_Val = 0x00 ; + state->TunerRegs[31].Reg_Num = 49 ; + state->TunerRegs[31].Reg_Val = 0x00 ; - Tuner->TunerRegs[32].Reg_Num = 53 ; - Tuner->TunerRegs[32].Reg_Val = 0x94 ; + state->TunerRegs[32].Reg_Num = 53 ; + state->TunerRegs[32].Reg_Val = 0x94 ; - Tuner->TunerRegs[33].Reg_Num = 54 ; - Tuner->TunerRegs[33].Reg_Val = 0xFA ; + state->TunerRegs[33].Reg_Num = 54 ; + state->TunerRegs[33].Reg_Val = 0xFA ; - Tuner->TunerRegs[34].Reg_Num = 55 ; - Tuner->TunerRegs[34].Reg_Val = 0x92 ; + state->TunerRegs[34].Reg_Num = 55 ; + state->TunerRegs[34].Reg_Val = 0x92 ; - Tuner->TunerRegs[35].Reg_Num = 56 ; - Tuner->TunerRegs[35].Reg_Val = 0x80 ; + state->TunerRegs[35].Reg_Num = 56 ; + state->TunerRegs[35].Reg_Val = 0x80 ; - Tuner->TunerRegs[36].Reg_Num = 57 ; - Tuner->TunerRegs[36].Reg_Val = 0x41 ; + state->TunerRegs[36].Reg_Num = 57 ; + state->TunerRegs[36].Reg_Val = 0x41 ; - Tuner->TunerRegs[37].Reg_Num = 58 ; - Tuner->TunerRegs[37].Reg_Val = 0xDB ; + state->TunerRegs[37].Reg_Num = 58 ; + state->TunerRegs[37].Reg_Val = 0xDB ; - Tuner->TunerRegs[38].Reg_Num = 59 ; - Tuner->TunerRegs[38].Reg_Val = 0x00 ; + state->TunerRegs[38].Reg_Num = 59 ; + state->TunerRegs[38].Reg_Val = 0x00 ; - Tuner->TunerRegs[39].Reg_Num = 60 ; - Tuner->TunerRegs[39].Reg_Val = 0x00 ; + state->TunerRegs[39].Reg_Num = 60 ; + state->TunerRegs[39].Reg_Val = 0x00 ; - Tuner->TunerRegs[40].Reg_Num = 61 ; - Tuner->TunerRegs[40].Reg_Val = 0x00 ; + state->TunerRegs[40].Reg_Num = 61 ; + state->TunerRegs[40].Reg_Val = 0x00 ; - Tuner->TunerRegs[41].Reg_Num = 62 ; - Tuner->TunerRegs[41].Reg_Val = 0x00 ; + state->TunerRegs[41].Reg_Num = 62 ; + state->TunerRegs[41].Reg_Val = 0x00 ; - Tuner->TunerRegs[42].Reg_Num = 65 ; - Tuner->TunerRegs[42].Reg_Val = 0xF8 ; + state->TunerRegs[42].Reg_Num = 65 ; + state->TunerRegs[42].Reg_Val = 0xF8 ; - Tuner->TunerRegs[43].Reg_Num = 66 ; - Tuner->TunerRegs[43].Reg_Val = 0xE4 ; + state->TunerRegs[43].Reg_Num = 66 ; + state->TunerRegs[43].Reg_Val = 0xE4 ; - Tuner->TunerRegs[44].Reg_Num = 67 ; - Tuner->TunerRegs[44].Reg_Val = 0x90 ; + state->TunerRegs[44].Reg_Num = 67 ; + state->TunerRegs[44].Reg_Val = 0x90 ; - Tuner->TunerRegs[45].Reg_Num = 68 ; - Tuner->TunerRegs[45].Reg_Val = 0xC0 ; + state->TunerRegs[45].Reg_Num = 68 ; + state->TunerRegs[45].Reg_Val = 0xC0 ; - Tuner->TunerRegs[46].Reg_Num = 69 ; - Tuner->TunerRegs[46].Reg_Val = 0x01 ; + state->TunerRegs[46].Reg_Num = 69 ; + state->TunerRegs[46].Reg_Val = 0x01 ; - Tuner->TunerRegs[47].Reg_Num = 70 ; - Tuner->TunerRegs[47].Reg_Val = 0x50 ; + state->TunerRegs[47].Reg_Num = 70 ; + state->TunerRegs[47].Reg_Val = 0x50 ; - Tuner->TunerRegs[48].Reg_Num = 71 ; - Tuner->TunerRegs[48].Reg_Val = 0x06 ; + state->TunerRegs[48].Reg_Num = 71 ; + state->TunerRegs[48].Reg_Val = 0x06 ; - Tuner->TunerRegs[49].Reg_Num = 72 ; - Tuner->TunerRegs[49].Reg_Val = 0x00 ; + state->TunerRegs[49].Reg_Num = 72 ; + state->TunerRegs[49].Reg_Val = 0x00 ; - Tuner->TunerRegs[50].Reg_Num = 73 ; - Tuner->TunerRegs[50].Reg_Val = 0x20 ; + state->TunerRegs[50].Reg_Num = 73 ; + state->TunerRegs[50].Reg_Val = 0x20 ; - Tuner->TunerRegs[51].Reg_Num = 76 ; - Tuner->TunerRegs[51].Reg_Val = 0xBB ; + state->TunerRegs[51].Reg_Num = 76 ; + state->TunerRegs[51].Reg_Val = 0xBB ; - Tuner->TunerRegs[52].Reg_Num = 77 ; - Tuner->TunerRegs[52].Reg_Val = 0x13 ; + state->TunerRegs[52].Reg_Num = 77 ; + state->TunerRegs[52].Reg_Val = 0x13 ; - Tuner->TunerRegs[53].Reg_Num = 81 ; - Tuner->TunerRegs[53].Reg_Val = 0x04 ; + state->TunerRegs[53].Reg_Num = 81 ; + state->TunerRegs[53].Reg_Val = 0x04 ; - Tuner->TunerRegs[54].Reg_Num = 82 ; - Tuner->TunerRegs[54].Reg_Val = 0x75 ; + state->TunerRegs[54].Reg_Num = 82 ; + state->TunerRegs[54].Reg_Val = 0x75 ; - Tuner->TunerRegs[55].Reg_Num = 83 ; - Tuner->TunerRegs[55].Reg_Val = 0x00 ; + state->TunerRegs[55].Reg_Num = 83 ; + state->TunerRegs[55].Reg_Val = 0x00 ; - Tuner->TunerRegs[56].Reg_Num = 84 ; - Tuner->TunerRegs[56].Reg_Val = 0x00 ; + state->TunerRegs[56].Reg_Num = 84 ; + state->TunerRegs[56].Reg_Val = 0x00 ; - Tuner->TunerRegs[57].Reg_Num = 85 ; - Tuner->TunerRegs[57].Reg_Val = 0x00 ; + state->TunerRegs[57].Reg_Num = 85 ; + state->TunerRegs[57].Reg_Val = 0x00 ; - Tuner->TunerRegs[58].Reg_Num = 91 ; - Tuner->TunerRegs[58].Reg_Val = 0x70 ; + state->TunerRegs[58].Reg_Num = 91 ; + state->TunerRegs[58].Reg_Val = 0x70 ; - Tuner->TunerRegs[59].Reg_Num = 92 ; - Tuner->TunerRegs[59].Reg_Val = 0x00 ; + state->TunerRegs[59].Reg_Num = 92 ; + state->TunerRegs[59].Reg_Val = 0x00 ; - Tuner->TunerRegs[60].Reg_Num = 93 ; - Tuner->TunerRegs[60].Reg_Val = 0x00 ; + state->TunerRegs[60].Reg_Num = 93 ; + state->TunerRegs[60].Reg_Val = 0x00 ; - Tuner->TunerRegs[61].Reg_Num = 94 ; - Tuner->TunerRegs[61].Reg_Val = 0x00 ; + state->TunerRegs[61].Reg_Num = 94 ; + state->TunerRegs[61].Reg_Val = 0x00 ; - Tuner->TunerRegs[62].Reg_Num = 95 ; - Tuner->TunerRegs[62].Reg_Val = 0x0C ; + state->TunerRegs[62].Reg_Num = 95 ; + state->TunerRegs[62].Reg_Val = 0x0C ; - Tuner->TunerRegs[63].Reg_Num = 96 ; - Tuner->TunerRegs[63].Reg_Val = 0x00 ; + state->TunerRegs[63].Reg_Num = 96 ; + state->TunerRegs[63].Reg_Val = 0x00 ; - Tuner->TunerRegs[64].Reg_Num = 97 ; - Tuner->TunerRegs[64].Reg_Val = 0x00 ; + state->TunerRegs[64].Reg_Num = 97 ; + state->TunerRegs[64].Reg_Val = 0x00 ; - Tuner->TunerRegs[65].Reg_Num = 98 ; - Tuner->TunerRegs[65].Reg_Val = 0xE2 ; + state->TunerRegs[65].Reg_Num = 98 ; + state->TunerRegs[65].Reg_Val = 0xE2 ; - Tuner->TunerRegs[66].Reg_Num = 99 ; - Tuner->TunerRegs[66].Reg_Val = 0x00 ; + state->TunerRegs[66].Reg_Num = 99 ; + state->TunerRegs[66].Reg_Val = 0x00 ; - Tuner->TunerRegs[67].Reg_Num = 100 ; - Tuner->TunerRegs[67].Reg_Val = 0x00 ; + state->TunerRegs[67].Reg_Num = 100 ; + state->TunerRegs[67].Reg_Val = 0x00 ; - Tuner->TunerRegs[68].Reg_Num = 101 ; - Tuner->TunerRegs[68].Reg_Val = 0x12 ; + state->TunerRegs[68].Reg_Num = 101 ; + state->TunerRegs[68].Reg_Val = 0x12 ; - Tuner->TunerRegs[69].Reg_Num = 102 ; - Tuner->TunerRegs[69].Reg_Val = 0x80 ; + state->TunerRegs[69].Reg_Num = 102 ; + state->TunerRegs[69].Reg_Val = 0x80 ; - Tuner->TunerRegs[70].Reg_Num = 103 ; - Tuner->TunerRegs[70].Reg_Val = 0x32 ; + state->TunerRegs[70].Reg_Num = 103 ; + state->TunerRegs[70].Reg_Val = 0x32 ; - Tuner->TunerRegs[71].Reg_Num = 104 ; - Tuner->TunerRegs[71].Reg_Val = 0xB4 ; + state->TunerRegs[71].Reg_Num = 104 ; + state->TunerRegs[71].Reg_Val = 0xB4 ; - Tuner->TunerRegs[72].Reg_Num = 105 ; - Tuner->TunerRegs[72].Reg_Val = 0x60 ; + state->TunerRegs[72].Reg_Num = 105 ; + state->TunerRegs[72].Reg_Val = 0x60 ; - Tuner->TunerRegs[73].Reg_Num = 106 ; - Tuner->TunerRegs[73].Reg_Val = 0x83 ; + state->TunerRegs[73].Reg_Num = 106 ; + state->TunerRegs[73].Reg_Val = 0x83 ; - Tuner->TunerRegs[74].Reg_Num = 107 ; - Tuner->TunerRegs[74].Reg_Val = 0x84 ; + state->TunerRegs[74].Reg_Num = 107 ; + state->TunerRegs[74].Reg_Val = 0x84 ; - Tuner->TunerRegs[75].Reg_Num = 108 ; - Tuner->TunerRegs[75].Reg_Val = 0x9C ; + state->TunerRegs[75].Reg_Num = 108 ; + state->TunerRegs[75].Reg_Val = 0x9C ; - Tuner->TunerRegs[76].Reg_Num = 109 ; - Tuner->TunerRegs[76].Reg_Val = 0x02 ; + state->TunerRegs[76].Reg_Num = 109 ; + state->TunerRegs[76].Reg_Val = 0x02 ; - Tuner->TunerRegs[77].Reg_Num = 110 ; - Tuner->TunerRegs[77].Reg_Val = 0x81 ; + state->TunerRegs[77].Reg_Num = 110 ; + state->TunerRegs[77].Reg_Val = 0x81 ; - Tuner->TunerRegs[78].Reg_Num = 111 ; - Tuner->TunerRegs[78].Reg_Val = 0xC0 ; + state->TunerRegs[78].Reg_Num = 111 ; + state->TunerRegs[78].Reg_Val = 0xC0 ; - Tuner->TunerRegs[79].Reg_Num = 112 ; - Tuner->TunerRegs[79].Reg_Val = 0x10 ; + state->TunerRegs[79].Reg_Num = 112 ; + state->TunerRegs[79].Reg_Val = 0x10 ; - Tuner->TunerRegs[80].Reg_Num = 131 ; - Tuner->TunerRegs[80].Reg_Val = 0x8A ; + state->TunerRegs[80].Reg_Num = 131 ; + state->TunerRegs[80].Reg_Val = 0x8A ; - Tuner->TunerRegs[81].Reg_Num = 132 ; - Tuner->TunerRegs[81].Reg_Val = 0x10 ; + state->TunerRegs[81].Reg_Num = 132 ; + state->TunerRegs[81].Reg_Val = 0x10 ; - Tuner->TunerRegs[82].Reg_Num = 133 ; - Tuner->TunerRegs[82].Reg_Val = 0x24 ; + state->TunerRegs[82].Reg_Num = 133 ; + state->TunerRegs[82].Reg_Val = 0x24 ; - Tuner->TunerRegs[83].Reg_Num = 134 ; - Tuner->TunerRegs[83].Reg_Val = 0x00 ; + state->TunerRegs[83].Reg_Num = 134 ; + state->TunerRegs[83].Reg_Val = 0x00 ; - Tuner->TunerRegs[84].Reg_Num = 135 ; - Tuner->TunerRegs[84].Reg_Val = 0x00 ; + state->TunerRegs[84].Reg_Num = 135 ; + state->TunerRegs[84].Reg_Val = 0x00 ; - Tuner->TunerRegs[85].Reg_Num = 136 ; - Tuner->TunerRegs[85].Reg_Val = 0x7E ; + state->TunerRegs[85].Reg_Num = 136 ; + state->TunerRegs[85].Reg_Val = 0x7E ; - Tuner->TunerRegs[86].Reg_Num = 137 ; - Tuner->TunerRegs[86].Reg_Val = 0x40 ; + state->TunerRegs[86].Reg_Num = 137 ; + state->TunerRegs[86].Reg_Val = 0x40 ; - Tuner->TunerRegs[87].Reg_Num = 138 ; - Tuner->TunerRegs[87].Reg_Val = 0x38 ; + state->TunerRegs[87].Reg_Num = 138 ; + state->TunerRegs[87].Reg_Val = 0x38 ; - Tuner->TunerRegs[88].Reg_Num = 146 ; - Tuner->TunerRegs[88].Reg_Val = 0xF6 ; + state->TunerRegs[88].Reg_Num = 146 ; + state->TunerRegs[88].Reg_Val = 0xF6 ; - Tuner->TunerRegs[89].Reg_Num = 147 ; - Tuner->TunerRegs[89].Reg_Val = 0x1A ; + state->TunerRegs[89].Reg_Num = 147 ; + state->TunerRegs[89].Reg_Val = 0x1A ; - Tuner->TunerRegs[90].Reg_Num = 148 ; - Tuner->TunerRegs[90].Reg_Val = 0x62 ; + state->TunerRegs[90].Reg_Num = 148 ; + state->TunerRegs[90].Reg_Val = 0x62 ; - Tuner->TunerRegs[91].Reg_Num = 149 ; - Tuner->TunerRegs[91].Reg_Val = 0x33 ; + state->TunerRegs[91].Reg_Num = 149 ; + state->TunerRegs[91].Reg_Val = 0x33 ; - Tuner->TunerRegs[92].Reg_Num = 150 ; - Tuner->TunerRegs[92].Reg_Val = 0x80 ; + state->TunerRegs[92].Reg_Num = 150 ; + state->TunerRegs[92].Reg_Val = 0x80 ; - Tuner->TunerRegs[93].Reg_Num = 156 ; - Tuner->TunerRegs[93].Reg_Val = 0x56 ; + state->TunerRegs[93].Reg_Num = 156 ; + state->TunerRegs[93].Reg_Val = 0x56 ; - Tuner->TunerRegs[94].Reg_Num = 157 ; - Tuner->TunerRegs[94].Reg_Val = 0x17 ; + state->TunerRegs[94].Reg_Num = 157 ; + state->TunerRegs[94].Reg_Val = 0x17 ; - Tuner->TunerRegs[95].Reg_Num = 158 ; - Tuner->TunerRegs[95].Reg_Val = 0xA9 ; + state->TunerRegs[95].Reg_Num = 158 ; + state->TunerRegs[95].Reg_Val = 0xA9 ; - Tuner->TunerRegs[96].Reg_Num = 159 ; - Tuner->TunerRegs[96].Reg_Val = 0x00 ; + state->TunerRegs[96].Reg_Num = 159 ; + state->TunerRegs[96].Reg_Val = 0x00 ; - Tuner->TunerRegs[97].Reg_Num = 160 ; - Tuner->TunerRegs[97].Reg_Val = 0x00 ; + state->TunerRegs[97].Reg_Num = 160 ; + state->TunerRegs[97].Reg_Val = 0x00 ; - Tuner->TunerRegs[98].Reg_Num = 161 ; - Tuner->TunerRegs[98].Reg_Val = 0x00 ; + state->TunerRegs[98].Reg_Num = 161 ; + state->TunerRegs[98].Reg_Val = 0x00 ; - Tuner->TunerRegs[99].Reg_Num = 162 ; - Tuner->TunerRegs[99].Reg_Val = 0x40 ; + state->TunerRegs[99].Reg_Num = 162 ; + state->TunerRegs[99].Reg_Val = 0x40 ; - Tuner->TunerRegs[100].Reg_Num = 166 ; - Tuner->TunerRegs[100].Reg_Val = 0xAE ; + state->TunerRegs[100].Reg_Num = 166 ; + state->TunerRegs[100].Reg_Val = 0xAE ; - Tuner->TunerRegs[101].Reg_Num = 167 ; - Tuner->TunerRegs[101].Reg_Val = 0x1B ; + state->TunerRegs[101].Reg_Num = 167 ; + state->TunerRegs[101].Reg_Val = 0x1B ; - Tuner->TunerRegs[102].Reg_Num = 168 ; - Tuner->TunerRegs[102].Reg_Val = 0xF2 ; + state->TunerRegs[102].Reg_Num = 168 ; + state->TunerRegs[102].Reg_Val = 0xF2 ; - Tuner->TunerRegs[103].Reg_Num = 195 ; - Tuner->TunerRegs[103].Reg_Val = 0x00 ; + state->TunerRegs[103].Reg_Num = 195 ; + state->TunerRegs[103].Reg_Val = 0x00 ; return 0 ; } -u16 MXL5005_ControlInit(Tuner_struct *Tuner) +// DONE +u16 MXL5005_ControlInit(struct dvb_frontend *fe) { - Tuner->Init_Ctrl_Num = INITCTRL_NUM ; - - Tuner->Init_Ctrl[0].Ctrl_Num = DN_IQTN_AMP_CUT ; - Tuner->Init_Ctrl[0].size = 1 ; - Tuner->Init_Ctrl[0].addr[0] = 73; - Tuner->Init_Ctrl[0].bit[0] = 7; - Tuner->Init_Ctrl[0].val[0] = 0; - - Tuner->Init_Ctrl[1].Ctrl_Num = BB_MODE ; - Tuner->Init_Ctrl[1].size = 1 ; - Tuner->Init_Ctrl[1].addr[0] = 53; - Tuner->Init_Ctrl[1].bit[0] = 2; - Tuner->Init_Ctrl[1].val[0] = 1; - - Tuner->Init_Ctrl[2].Ctrl_Num = BB_BUF ; - Tuner->Init_Ctrl[2].size = 2 ; - Tuner->Init_Ctrl[2].addr[0] = 53; - Tuner->Init_Ctrl[2].bit[0] = 1; - Tuner->Init_Ctrl[2].val[0] = 0; - Tuner->Init_Ctrl[2].addr[1] = 57; - Tuner->Init_Ctrl[2].bit[1] = 0; - Tuner->Init_Ctrl[2].val[1] = 1; - - Tuner->Init_Ctrl[3].Ctrl_Num = BB_BUF_OA ; - Tuner->Init_Ctrl[3].size = 1 ; - Tuner->Init_Ctrl[3].addr[0] = 53; - Tuner->Init_Ctrl[3].bit[0] = 0; - Tuner->Init_Ctrl[3].val[0] = 0; - - Tuner->Init_Ctrl[4].Ctrl_Num = BB_ALPF_BANDSELECT ; - Tuner->Init_Ctrl[4].size = 3 ; - Tuner->Init_Ctrl[4].addr[0] = 53; - Tuner->Init_Ctrl[4].bit[0] = 5; - Tuner->Init_Ctrl[4].val[0] = 0; - Tuner->Init_Ctrl[4].addr[1] = 53; - Tuner->Init_Ctrl[4].bit[1] = 6; - Tuner->Init_Ctrl[4].val[1] = 0; - Tuner->Init_Ctrl[4].addr[2] = 53; - Tuner->Init_Ctrl[4].bit[2] = 7; - Tuner->Init_Ctrl[4].val[2] = 1; - - Tuner->Init_Ctrl[5].Ctrl_Num = BB_IQSWAP ; - Tuner->Init_Ctrl[5].size = 1 ; - Tuner->Init_Ctrl[5].addr[0] = 59; - Tuner->Init_Ctrl[5].bit[0] = 0; - Tuner->Init_Ctrl[5].val[0] = 0; - - Tuner->Init_Ctrl[6].Ctrl_Num = BB_DLPF_BANDSEL ; - Tuner->Init_Ctrl[6].size = 2 ; - Tuner->Init_Ctrl[6].addr[0] = 53; - Tuner->Init_Ctrl[6].bit[0] = 3; - Tuner->Init_Ctrl[6].val[0] = 0; - Tuner->Init_Ctrl[6].addr[1] = 53; - Tuner->Init_Ctrl[6].bit[1] = 4; - Tuner->Init_Ctrl[6].val[1] = 1; - - Tuner->Init_Ctrl[7].Ctrl_Num = RFSYN_CHP_GAIN ; - Tuner->Init_Ctrl[7].size = 4 ; - Tuner->Init_Ctrl[7].addr[0] = 22; - Tuner->Init_Ctrl[7].bit[0] = 4; - Tuner->Init_Ctrl[7].val[0] = 0; - Tuner->Init_Ctrl[7].addr[1] = 22; - Tuner->Init_Ctrl[7].bit[1] = 5; - Tuner->Init_Ctrl[7].val[1] = 1; - Tuner->Init_Ctrl[7].addr[2] = 22; - Tuner->Init_Ctrl[7].bit[2] = 6; - Tuner->Init_Ctrl[7].val[2] = 1; - Tuner->Init_Ctrl[7].addr[3] = 22; - Tuner->Init_Ctrl[7].bit[3] = 7; - Tuner->Init_Ctrl[7].val[3] = 0; - - Tuner->Init_Ctrl[8].Ctrl_Num = RFSYN_EN_CHP_HIGAIN ; - Tuner->Init_Ctrl[8].size = 1 ; - Tuner->Init_Ctrl[8].addr[0] = 22; - Tuner->Init_Ctrl[8].bit[0] = 2; - Tuner->Init_Ctrl[8].val[0] = 0; - - Tuner->Init_Ctrl[9].Ctrl_Num = AGC_IF ; - Tuner->Init_Ctrl[9].size = 4 ; - Tuner->Init_Ctrl[9].addr[0] = 76; - Tuner->Init_Ctrl[9].bit[0] = 0; - Tuner->Init_Ctrl[9].val[0] = 1; - Tuner->Init_Ctrl[9].addr[1] = 76; - Tuner->Init_Ctrl[9].bit[1] = 1; - Tuner->Init_Ctrl[9].val[1] = 1; - Tuner->Init_Ctrl[9].addr[2] = 76; - Tuner->Init_Ctrl[9].bit[2] = 2; - Tuner->Init_Ctrl[9].val[2] = 0; - Tuner->Init_Ctrl[9].addr[3] = 76; - Tuner->Init_Ctrl[9].bit[3] = 3; - Tuner->Init_Ctrl[9].val[3] = 1; - - Tuner->Init_Ctrl[10].Ctrl_Num = AGC_RF ; - Tuner->Init_Ctrl[10].size = 4 ; - Tuner->Init_Ctrl[10].addr[0] = 76; - Tuner->Init_Ctrl[10].bit[0] = 4; - Tuner->Init_Ctrl[10].val[0] = 1; - Tuner->Init_Ctrl[10].addr[1] = 76; - Tuner->Init_Ctrl[10].bit[1] = 5; - Tuner->Init_Ctrl[10].val[1] = 1; - Tuner->Init_Ctrl[10].addr[2] = 76; - Tuner->Init_Ctrl[10].bit[2] = 6; - Tuner->Init_Ctrl[10].val[2] = 0; - Tuner->Init_Ctrl[10].addr[3] = 76; - Tuner->Init_Ctrl[10].bit[3] = 7; - Tuner->Init_Ctrl[10].val[3] = 1; - - Tuner->Init_Ctrl[11].Ctrl_Num = IF_DIVVAL ; - Tuner->Init_Ctrl[11].size = 5 ; - Tuner->Init_Ctrl[11].addr[0] = 43; - Tuner->Init_Ctrl[11].bit[0] = 3; - Tuner->Init_Ctrl[11].val[0] = 0; - Tuner->Init_Ctrl[11].addr[1] = 43; - Tuner->Init_Ctrl[11].bit[1] = 4; - Tuner->Init_Ctrl[11].val[1] = 0; - Tuner->Init_Ctrl[11].addr[2] = 43; - Tuner->Init_Ctrl[11].bit[2] = 5; - Tuner->Init_Ctrl[11].val[2] = 0; - Tuner->Init_Ctrl[11].addr[3] = 43; - Tuner->Init_Ctrl[11].bit[3] = 6; - Tuner->Init_Ctrl[11].val[3] = 1; - Tuner->Init_Ctrl[11].addr[4] = 43; - Tuner->Init_Ctrl[11].bit[4] = 7; - Tuner->Init_Ctrl[11].val[4] = 0; - - Tuner->Init_Ctrl[12].Ctrl_Num = IF_VCO_BIAS ; - Tuner->Init_Ctrl[12].size = 6 ; - Tuner->Init_Ctrl[12].addr[0] = 44; - Tuner->Init_Ctrl[12].bit[0] = 2; - Tuner->Init_Ctrl[12].val[0] = 0; - Tuner->Init_Ctrl[12].addr[1] = 44; - Tuner->Init_Ctrl[12].bit[1] = 3; - Tuner->Init_Ctrl[12].val[1] = 0; - Tuner->Init_Ctrl[12].addr[2] = 44; - Tuner->Init_Ctrl[12].bit[2] = 4; - Tuner->Init_Ctrl[12].val[2] = 0; - Tuner->Init_Ctrl[12].addr[3] = 44; - Tuner->Init_Ctrl[12].bit[3] = 5; - Tuner->Init_Ctrl[12].val[3] = 1; - Tuner->Init_Ctrl[12].addr[4] = 44; - Tuner->Init_Ctrl[12].bit[4] = 6; - Tuner->Init_Ctrl[12].val[4] = 0; - Tuner->Init_Ctrl[12].addr[5] = 44; - Tuner->Init_Ctrl[12].bit[5] = 7; - Tuner->Init_Ctrl[12].val[5] = 0; - - Tuner->Init_Ctrl[13].Ctrl_Num = CHCAL_INT_MOD_IF ; - Tuner->Init_Ctrl[13].size = 7 ; - Tuner->Init_Ctrl[13].addr[0] = 11; - Tuner->Init_Ctrl[13].bit[0] = 0; - Tuner->Init_Ctrl[13].val[0] = 1; - Tuner->Init_Ctrl[13].addr[1] = 11; - Tuner->Init_Ctrl[13].bit[1] = 1; - Tuner->Init_Ctrl[13].val[1] = 0; - Tuner->Init_Ctrl[13].addr[2] = 11; - Tuner->Init_Ctrl[13].bit[2] = 2; - Tuner->Init_Ctrl[13].val[2] = 0; - Tuner->Init_Ctrl[13].addr[3] = 11; - Tuner->Init_Ctrl[13].bit[3] = 3; - Tuner->Init_Ctrl[13].val[3] = 1; - Tuner->Init_Ctrl[13].addr[4] = 11; - Tuner->Init_Ctrl[13].bit[4] = 4; - Tuner->Init_Ctrl[13].val[4] = 1; - Tuner->Init_Ctrl[13].addr[5] = 11; - Tuner->Init_Ctrl[13].bit[5] = 5; - Tuner->Init_Ctrl[13].val[5] = 0; - Tuner->Init_Ctrl[13].addr[6] = 11; - Tuner->Init_Ctrl[13].bit[6] = 6; - Tuner->Init_Ctrl[13].val[6] = 0; - - Tuner->Init_Ctrl[14].Ctrl_Num = CHCAL_FRAC_MOD_IF ; - Tuner->Init_Ctrl[14].size = 16 ; - Tuner->Init_Ctrl[14].addr[0] = 13; - Tuner->Init_Ctrl[14].bit[0] = 0; - Tuner->Init_Ctrl[14].val[0] = 0; - Tuner->Init_Ctrl[14].addr[1] = 13; - Tuner->Init_Ctrl[14].bit[1] = 1; - Tuner->Init_Ctrl[14].val[1] = 0; - Tuner->Init_Ctrl[14].addr[2] = 13; - Tuner->Init_Ctrl[14].bit[2] = 2; - Tuner->Init_Ctrl[14].val[2] = 0; - Tuner->Init_Ctrl[14].addr[3] = 13; - Tuner->Init_Ctrl[14].bit[3] = 3; - Tuner->Init_Ctrl[14].val[3] = 0; - Tuner->Init_Ctrl[14].addr[4] = 13; - Tuner->Init_Ctrl[14].bit[4] = 4; - Tuner->Init_Ctrl[14].val[4] = 0; - Tuner->Init_Ctrl[14].addr[5] = 13; - Tuner->Init_Ctrl[14].bit[5] = 5; - Tuner->Init_Ctrl[14].val[5] = 0; - Tuner->Init_Ctrl[14].addr[6] = 13; - Tuner->Init_Ctrl[14].bit[6] = 6; - Tuner->Init_Ctrl[14].val[6] = 0; - Tuner->Init_Ctrl[14].addr[7] = 13; - Tuner->Init_Ctrl[14].bit[7] = 7; - Tuner->Init_Ctrl[14].val[7] = 0; - Tuner->Init_Ctrl[14].addr[8] = 12; - Tuner->Init_Ctrl[14].bit[8] = 0; - Tuner->Init_Ctrl[14].val[8] = 0; - Tuner->Init_Ctrl[14].addr[9] = 12; - Tuner->Init_Ctrl[14].bit[9] = 1; - Tuner->Init_Ctrl[14].val[9] = 0; - Tuner->Init_Ctrl[14].addr[10] = 12; - Tuner->Init_Ctrl[14].bit[10] = 2; - Tuner->Init_Ctrl[14].val[10] = 0; - Tuner->Init_Ctrl[14].addr[11] = 12; - Tuner->Init_Ctrl[14].bit[11] = 3; - Tuner->Init_Ctrl[14].val[11] = 0; - Tuner->Init_Ctrl[14].addr[12] = 12; - Tuner->Init_Ctrl[14].bit[12] = 4; - Tuner->Init_Ctrl[14].val[12] = 0; - Tuner->Init_Ctrl[14].addr[13] = 12; - Tuner->Init_Ctrl[14].bit[13] = 5; - Tuner->Init_Ctrl[14].val[13] = 1; - Tuner->Init_Ctrl[14].addr[14] = 12; - Tuner->Init_Ctrl[14].bit[14] = 6; - Tuner->Init_Ctrl[14].val[14] = 1; - Tuner->Init_Ctrl[14].addr[15] = 12; - Tuner->Init_Ctrl[14].bit[15] = 7; - Tuner->Init_Ctrl[14].val[15] = 0; - - Tuner->Init_Ctrl[15].Ctrl_Num = DRV_RES_SEL ; - Tuner->Init_Ctrl[15].size = 3 ; - Tuner->Init_Ctrl[15].addr[0] = 147; - Tuner->Init_Ctrl[15].bit[0] = 2; - Tuner->Init_Ctrl[15].val[0] = 0; - Tuner->Init_Ctrl[15].addr[1] = 147; - Tuner->Init_Ctrl[15].bit[1] = 3; - Tuner->Init_Ctrl[15].val[1] = 1; - Tuner->Init_Ctrl[15].addr[2] = 147; - Tuner->Init_Ctrl[15].bit[2] = 4; - Tuner->Init_Ctrl[15].val[2] = 1; - - Tuner->Init_Ctrl[16].Ctrl_Num = I_DRIVER ; - Tuner->Init_Ctrl[16].size = 2 ; - Tuner->Init_Ctrl[16].addr[0] = 147; - Tuner->Init_Ctrl[16].bit[0] = 0; - Tuner->Init_Ctrl[16].val[0] = 0; - Tuner->Init_Ctrl[16].addr[1] = 147; - Tuner->Init_Ctrl[16].bit[1] = 1; - Tuner->Init_Ctrl[16].val[1] = 1; - - Tuner->Init_Ctrl[17].Ctrl_Num = EN_AAF ; - Tuner->Init_Ctrl[17].size = 1 ; - Tuner->Init_Ctrl[17].addr[0] = 147; - Tuner->Init_Ctrl[17].bit[0] = 7; - Tuner->Init_Ctrl[17].val[0] = 0; - - Tuner->Init_Ctrl[18].Ctrl_Num = EN_3P ; - Tuner->Init_Ctrl[18].size = 1 ; - Tuner->Init_Ctrl[18].addr[0] = 147; - Tuner->Init_Ctrl[18].bit[0] = 6; - Tuner->Init_Ctrl[18].val[0] = 0; - - Tuner->Init_Ctrl[19].Ctrl_Num = EN_AUX_3P ; - Tuner->Init_Ctrl[19].size = 1 ; - Tuner->Init_Ctrl[19].addr[0] = 156; - Tuner->Init_Ctrl[19].bit[0] = 0; - Tuner->Init_Ctrl[19].val[0] = 0; - - Tuner->Init_Ctrl[20].Ctrl_Num = SEL_AAF_BAND ; - Tuner->Init_Ctrl[20].size = 1 ; - Tuner->Init_Ctrl[20].addr[0] = 147; - Tuner->Init_Ctrl[20].bit[0] = 5; - Tuner->Init_Ctrl[20].val[0] = 0; - - Tuner->Init_Ctrl[21].Ctrl_Num = SEQ_ENCLK16_CLK_OUT ; - Tuner->Init_Ctrl[21].size = 1 ; - Tuner->Init_Ctrl[21].addr[0] = 137; - Tuner->Init_Ctrl[21].bit[0] = 4; - Tuner->Init_Ctrl[21].val[0] = 0; - - Tuner->Init_Ctrl[22].Ctrl_Num = SEQ_SEL4_16B ; - Tuner->Init_Ctrl[22].size = 1 ; - Tuner->Init_Ctrl[22].addr[0] = 137; - Tuner->Init_Ctrl[22].bit[0] = 7; - Tuner->Init_Ctrl[22].val[0] = 0; - - Tuner->Init_Ctrl[23].Ctrl_Num = XTAL_CAPSELECT ; - Tuner->Init_Ctrl[23].size = 1 ; - Tuner->Init_Ctrl[23].addr[0] = 91; - Tuner->Init_Ctrl[23].bit[0] = 5; - Tuner->Init_Ctrl[23].val[0] = 1; - - Tuner->Init_Ctrl[24].Ctrl_Num = IF_SEL_DBL ; - Tuner->Init_Ctrl[24].size = 1 ; - Tuner->Init_Ctrl[24].addr[0] = 43; - Tuner->Init_Ctrl[24].bit[0] = 0; - Tuner->Init_Ctrl[24].val[0] = 1; - - Tuner->Init_Ctrl[25].Ctrl_Num = RFSYN_R_DIV ; - Tuner->Init_Ctrl[25].size = 2 ; - Tuner->Init_Ctrl[25].addr[0] = 22; - Tuner->Init_Ctrl[25].bit[0] = 0; - Tuner->Init_Ctrl[25].val[0] = 1; - Tuner->Init_Ctrl[25].addr[1] = 22; - Tuner->Init_Ctrl[25].bit[1] = 1; - Tuner->Init_Ctrl[25].val[1] = 1; - - Tuner->Init_Ctrl[26].Ctrl_Num = SEQ_EXTSYNTHCALIF ; - Tuner->Init_Ctrl[26].size = 1 ; - Tuner->Init_Ctrl[26].addr[0] = 134; - Tuner->Init_Ctrl[26].bit[0] = 2; - Tuner->Init_Ctrl[26].val[0] = 0; - - Tuner->Init_Ctrl[27].Ctrl_Num = SEQ_EXTDCCAL ; - Tuner->Init_Ctrl[27].size = 1 ; - Tuner->Init_Ctrl[27].addr[0] = 137; - Tuner->Init_Ctrl[27].bit[0] = 3; - Tuner->Init_Ctrl[27].val[0] = 0; - - Tuner->Init_Ctrl[28].Ctrl_Num = AGC_EN_RSSI ; - Tuner->Init_Ctrl[28].size = 1 ; - Tuner->Init_Ctrl[28].addr[0] = 77; - Tuner->Init_Ctrl[28].bit[0] = 7; - Tuner->Init_Ctrl[28].val[0] = 0; - - Tuner->Init_Ctrl[29].Ctrl_Num = RFA_ENCLKRFAGC ; - Tuner->Init_Ctrl[29].size = 1 ; - Tuner->Init_Ctrl[29].addr[0] = 166; - Tuner->Init_Ctrl[29].bit[0] = 7; - Tuner->Init_Ctrl[29].val[0] = 1; - - Tuner->Init_Ctrl[30].Ctrl_Num = RFA_RSSI_REFH ; - Tuner->Init_Ctrl[30].size = 3 ; - Tuner->Init_Ctrl[30].addr[0] = 166; - Tuner->Init_Ctrl[30].bit[0] = 0; - Tuner->Init_Ctrl[30].val[0] = 0; - Tuner->Init_Ctrl[30].addr[1] = 166; - Tuner->Init_Ctrl[30].bit[1] = 1; - Tuner->Init_Ctrl[30].val[1] = 1; - Tuner->Init_Ctrl[30].addr[2] = 166; - Tuner->Init_Ctrl[30].bit[2] = 2; - Tuner->Init_Ctrl[30].val[2] = 1; - - Tuner->Init_Ctrl[31].Ctrl_Num = RFA_RSSI_REF ; - Tuner->Init_Ctrl[31].size = 3 ; - Tuner->Init_Ctrl[31].addr[0] = 166; - Tuner->Init_Ctrl[31].bit[0] = 3; - Tuner->Init_Ctrl[31].val[0] = 1; - Tuner->Init_Ctrl[31].addr[1] = 166; - Tuner->Init_Ctrl[31].bit[1] = 4; - Tuner->Init_Ctrl[31].val[1] = 0; - Tuner->Init_Ctrl[31].addr[2] = 166; - Tuner->Init_Ctrl[31].bit[2] = 5; - Tuner->Init_Ctrl[31].val[2] = 1; - - Tuner->Init_Ctrl[32].Ctrl_Num = RFA_RSSI_REFL ; - Tuner->Init_Ctrl[32].size = 3 ; - Tuner->Init_Ctrl[32].addr[0] = 167; - Tuner->Init_Ctrl[32].bit[0] = 0; - Tuner->Init_Ctrl[32].val[0] = 1; - Tuner->Init_Ctrl[32].addr[1] = 167; - Tuner->Init_Ctrl[32].bit[1] = 1; - Tuner->Init_Ctrl[32].val[1] = 1; - Tuner->Init_Ctrl[32].addr[2] = 167; - Tuner->Init_Ctrl[32].bit[2] = 2; - Tuner->Init_Ctrl[32].val[2] = 0; - - Tuner->Init_Ctrl[33].Ctrl_Num = RFA_FLR ; - Tuner->Init_Ctrl[33].size = 4 ; - Tuner->Init_Ctrl[33].addr[0] = 168; - Tuner->Init_Ctrl[33].bit[0] = 0; - Tuner->Init_Ctrl[33].val[0] = 0; - Tuner->Init_Ctrl[33].addr[1] = 168; - Tuner->Init_Ctrl[33].bit[1] = 1; - Tuner->Init_Ctrl[33].val[1] = 1; - Tuner->Init_Ctrl[33].addr[2] = 168; - Tuner->Init_Ctrl[33].bit[2] = 2; - Tuner->Init_Ctrl[33].val[2] = 0; - Tuner->Init_Ctrl[33].addr[3] = 168; - Tuner->Init_Ctrl[33].bit[3] = 3; - Tuner->Init_Ctrl[33].val[3] = 0; - - Tuner->Init_Ctrl[34].Ctrl_Num = RFA_CEIL ; - Tuner->Init_Ctrl[34].size = 4 ; - Tuner->Init_Ctrl[34].addr[0] = 168; - Tuner->Init_Ctrl[34].bit[0] = 4; - Tuner->Init_Ctrl[34].val[0] = 1; - Tuner->Init_Ctrl[34].addr[1] = 168; - Tuner->Init_Ctrl[34].bit[1] = 5; - Tuner->Init_Ctrl[34].val[1] = 1; - Tuner->Init_Ctrl[34].addr[2] = 168; - Tuner->Init_Ctrl[34].bit[2] = 6; - Tuner->Init_Ctrl[34].val[2] = 1; - Tuner->Init_Ctrl[34].addr[3] = 168; - Tuner->Init_Ctrl[34].bit[3] = 7; - Tuner->Init_Ctrl[34].val[3] = 1; - - Tuner->Init_Ctrl[35].Ctrl_Num = SEQ_EXTIQFSMPULSE ; - Tuner->Init_Ctrl[35].size = 1 ; - Tuner->Init_Ctrl[35].addr[0] = 135; - Tuner->Init_Ctrl[35].bit[0] = 0; - Tuner->Init_Ctrl[35].val[0] = 0; - - Tuner->Init_Ctrl[36].Ctrl_Num = OVERRIDE_1 ; - Tuner->Init_Ctrl[36].size = 1 ; - Tuner->Init_Ctrl[36].addr[0] = 56; - Tuner->Init_Ctrl[36].bit[0] = 3; - Tuner->Init_Ctrl[36].val[0] = 0; - - Tuner->Init_Ctrl[37].Ctrl_Num = BB_INITSTATE_DLPF_TUNE ; - Tuner->Init_Ctrl[37].size = 7 ; - Tuner->Init_Ctrl[37].addr[0] = 59; - Tuner->Init_Ctrl[37].bit[0] = 1; - Tuner->Init_Ctrl[37].val[0] = 0; - Tuner->Init_Ctrl[37].addr[1] = 59; - Tuner->Init_Ctrl[37].bit[1] = 2; - Tuner->Init_Ctrl[37].val[1] = 0; - Tuner->Init_Ctrl[37].addr[2] = 59; - Tuner->Init_Ctrl[37].bit[2] = 3; - Tuner->Init_Ctrl[37].val[2] = 0; - Tuner->Init_Ctrl[37].addr[3] = 59; - Tuner->Init_Ctrl[37].bit[3] = 4; - Tuner->Init_Ctrl[37].val[3] = 0; - Tuner->Init_Ctrl[37].addr[4] = 59; - Tuner->Init_Ctrl[37].bit[4] = 5; - Tuner->Init_Ctrl[37].val[4] = 0; - Tuner->Init_Ctrl[37].addr[5] = 59; - Tuner->Init_Ctrl[37].bit[5] = 6; - Tuner->Init_Ctrl[37].val[5] = 0; - Tuner->Init_Ctrl[37].addr[6] = 59; - Tuner->Init_Ctrl[37].bit[6] = 7; - Tuner->Init_Ctrl[37].val[6] = 0; - - Tuner->Init_Ctrl[38].Ctrl_Num = TG_R_DIV ; - Tuner->Init_Ctrl[38].size = 6 ; - Tuner->Init_Ctrl[38].addr[0] = 32; - Tuner->Init_Ctrl[38].bit[0] = 2; - Tuner->Init_Ctrl[38].val[0] = 0; - Tuner->Init_Ctrl[38].addr[1] = 32; - Tuner->Init_Ctrl[38].bit[1] = 3; - Tuner->Init_Ctrl[38].val[1] = 0; - Tuner->Init_Ctrl[38].addr[2] = 32; - Tuner->Init_Ctrl[38].bit[2] = 4; - Tuner->Init_Ctrl[38].val[2] = 0; - Tuner->Init_Ctrl[38].addr[3] = 32; - Tuner->Init_Ctrl[38].bit[3] = 5; - Tuner->Init_Ctrl[38].val[3] = 0; - Tuner->Init_Ctrl[38].addr[4] = 32; - Tuner->Init_Ctrl[38].bit[4] = 6; - Tuner->Init_Ctrl[38].val[4] = 1; - Tuner->Init_Ctrl[38].addr[5] = 32; - Tuner->Init_Ctrl[38].bit[5] = 7; - Tuner->Init_Ctrl[38].val[5] = 0; - - Tuner->Init_Ctrl[39].Ctrl_Num = EN_CHP_LIN_B ; - Tuner->Init_Ctrl[39].size = 1 ; - Tuner->Init_Ctrl[39].addr[0] = 25; - Tuner->Init_Ctrl[39].bit[0] = 3; - Tuner->Init_Ctrl[39].val[0] = 1; - - - Tuner->CH_Ctrl_Num = CHCTRL_NUM ; - - Tuner->CH_Ctrl[0].Ctrl_Num = DN_POLY ; - Tuner->CH_Ctrl[0].size = 2 ; - Tuner->CH_Ctrl[0].addr[0] = 68; - Tuner->CH_Ctrl[0].bit[0] = 6; - Tuner->CH_Ctrl[0].val[0] = 1; - Tuner->CH_Ctrl[0].addr[1] = 68; - Tuner->CH_Ctrl[0].bit[1] = 7; - Tuner->CH_Ctrl[0].val[1] = 1; - - Tuner->CH_Ctrl[1].Ctrl_Num = DN_RFGAIN ; - Tuner->CH_Ctrl[1].size = 2 ; - Tuner->CH_Ctrl[1].addr[0] = 70; - Tuner->CH_Ctrl[1].bit[0] = 6; - Tuner->CH_Ctrl[1].val[0] = 1; - Tuner->CH_Ctrl[1].addr[1] = 70; - Tuner->CH_Ctrl[1].bit[1] = 7; - Tuner->CH_Ctrl[1].val[1] = 0; - - Tuner->CH_Ctrl[2].Ctrl_Num = DN_CAP_RFLPF ; - Tuner->CH_Ctrl[2].size = 9 ; - Tuner->CH_Ctrl[2].addr[0] = 69; - Tuner->CH_Ctrl[2].bit[0] = 5; - Tuner->CH_Ctrl[2].val[0] = 0; - Tuner->CH_Ctrl[2].addr[1] = 69; - Tuner->CH_Ctrl[2].bit[1] = 6; - Tuner->CH_Ctrl[2].val[1] = 0; - Tuner->CH_Ctrl[2].addr[2] = 69; - Tuner->CH_Ctrl[2].bit[2] = 7; - Tuner->CH_Ctrl[2].val[2] = 0; - Tuner->CH_Ctrl[2].addr[3] = 68; - Tuner->CH_Ctrl[2].bit[3] = 0; - Tuner->CH_Ctrl[2].val[3] = 0; - Tuner->CH_Ctrl[2].addr[4] = 68; - Tuner->CH_Ctrl[2].bit[4] = 1; - Tuner->CH_Ctrl[2].val[4] = 0; - Tuner->CH_Ctrl[2].addr[5] = 68; - Tuner->CH_Ctrl[2].bit[5] = 2; - Tuner->CH_Ctrl[2].val[5] = 0; - Tuner->CH_Ctrl[2].addr[6] = 68; - Tuner->CH_Ctrl[2].bit[6] = 3; - Tuner->CH_Ctrl[2].val[6] = 0; - Tuner->CH_Ctrl[2].addr[7] = 68; - Tuner->CH_Ctrl[2].bit[7] = 4; - Tuner->CH_Ctrl[2].val[7] = 0; - Tuner->CH_Ctrl[2].addr[8] = 68; - Tuner->CH_Ctrl[2].bit[8] = 5; - Tuner->CH_Ctrl[2].val[8] = 0; - - Tuner->CH_Ctrl[3].Ctrl_Num = DN_EN_VHFUHFBAR ; - Tuner->CH_Ctrl[3].size = 1 ; - Tuner->CH_Ctrl[3].addr[0] = 70; - Tuner->CH_Ctrl[3].bit[0] = 5; - Tuner->CH_Ctrl[3].val[0] = 0; - - Tuner->CH_Ctrl[4].Ctrl_Num = DN_GAIN_ADJUST ; - Tuner->CH_Ctrl[4].size = 3 ; - Tuner->CH_Ctrl[4].addr[0] = 73; - Tuner->CH_Ctrl[4].bit[0] = 4; - Tuner->CH_Ctrl[4].val[0] = 0; - Tuner->CH_Ctrl[4].addr[1] = 73; - Tuner->CH_Ctrl[4].bit[1] = 5; - Tuner->CH_Ctrl[4].val[1] = 1; - Tuner->CH_Ctrl[4].addr[2] = 73; - Tuner->CH_Ctrl[4].bit[2] = 6; - Tuner->CH_Ctrl[4].val[2] = 0; - - Tuner->CH_Ctrl[5].Ctrl_Num = DN_IQTNBUF_AMP ; - Tuner->CH_Ctrl[5].size = 4 ; - Tuner->CH_Ctrl[5].addr[0] = 70; - Tuner->CH_Ctrl[5].bit[0] = 0; - Tuner->CH_Ctrl[5].val[0] = 0; - Tuner->CH_Ctrl[5].addr[1] = 70; - Tuner->CH_Ctrl[5].bit[1] = 1; - Tuner->CH_Ctrl[5].val[1] = 0; - Tuner->CH_Ctrl[5].addr[2] = 70; - Tuner->CH_Ctrl[5].bit[2] = 2; - Tuner->CH_Ctrl[5].val[2] = 0; - Tuner->CH_Ctrl[5].addr[3] = 70; - Tuner->CH_Ctrl[5].bit[3] = 3; - Tuner->CH_Ctrl[5].val[3] = 0; - - Tuner->CH_Ctrl[6].Ctrl_Num = DN_IQTNGNBFBIAS_BST ; - Tuner->CH_Ctrl[6].size = 1 ; - Tuner->CH_Ctrl[6].addr[0] = 70; - Tuner->CH_Ctrl[6].bit[0] = 4; - Tuner->CH_Ctrl[6].val[0] = 1; - - Tuner->CH_Ctrl[7].Ctrl_Num = RFSYN_EN_OUTMUX ; - Tuner->CH_Ctrl[7].size = 1 ; - Tuner->CH_Ctrl[7].addr[0] = 111; - Tuner->CH_Ctrl[7].bit[0] = 4; - Tuner->CH_Ctrl[7].val[0] = 0; - - Tuner->CH_Ctrl[8].Ctrl_Num = RFSYN_SEL_VCO_OUT ; - Tuner->CH_Ctrl[8].size = 1 ; - Tuner->CH_Ctrl[8].addr[0] = 111; - Tuner->CH_Ctrl[8].bit[0] = 7; - Tuner->CH_Ctrl[8].val[0] = 1; - - Tuner->CH_Ctrl[9].Ctrl_Num = RFSYN_SEL_VCO_HI ; - Tuner->CH_Ctrl[9].size = 1 ; - Tuner->CH_Ctrl[9].addr[0] = 111; - Tuner->CH_Ctrl[9].bit[0] = 6; - Tuner->CH_Ctrl[9].val[0] = 1; - - Tuner->CH_Ctrl[10].Ctrl_Num = RFSYN_SEL_DIVM ; - Tuner->CH_Ctrl[10].size = 1 ; - Tuner->CH_Ctrl[10].addr[0] = 111; - Tuner->CH_Ctrl[10].bit[0] = 5; - Tuner->CH_Ctrl[10].val[0] = 0; - - Tuner->CH_Ctrl[11].Ctrl_Num = RFSYN_RF_DIV_BIAS ; - Tuner->CH_Ctrl[11].size = 2 ; - Tuner->CH_Ctrl[11].addr[0] = 110; - Tuner->CH_Ctrl[11].bit[0] = 0; - Tuner->CH_Ctrl[11].val[0] = 1; - Tuner->CH_Ctrl[11].addr[1] = 110; - Tuner->CH_Ctrl[11].bit[1] = 1; - Tuner->CH_Ctrl[11].val[1] = 0; - - Tuner->CH_Ctrl[12].Ctrl_Num = DN_SEL_FREQ ; - Tuner->CH_Ctrl[12].size = 3 ; - Tuner->CH_Ctrl[12].addr[0] = 69; - Tuner->CH_Ctrl[12].bit[0] = 2; - Tuner->CH_Ctrl[12].val[0] = 0; - Tuner->CH_Ctrl[12].addr[1] = 69; - Tuner->CH_Ctrl[12].bit[1] = 3; - Tuner->CH_Ctrl[12].val[1] = 0; - Tuner->CH_Ctrl[12].addr[2] = 69; - Tuner->CH_Ctrl[12].bit[2] = 4; - Tuner->CH_Ctrl[12].val[2] = 0; - - Tuner->CH_Ctrl[13].Ctrl_Num = RFSYN_VCO_BIAS ; - Tuner->CH_Ctrl[13].size = 6 ; - Tuner->CH_Ctrl[13].addr[0] = 110; - Tuner->CH_Ctrl[13].bit[0] = 2; - Tuner->CH_Ctrl[13].val[0] = 0; - Tuner->CH_Ctrl[13].addr[1] = 110; - Tuner->CH_Ctrl[13].bit[1] = 3; - Tuner->CH_Ctrl[13].val[1] = 0; - Tuner->CH_Ctrl[13].addr[2] = 110; - Tuner->CH_Ctrl[13].bit[2] = 4; - Tuner->CH_Ctrl[13].val[2] = 0; - Tuner->CH_Ctrl[13].addr[3] = 110; - Tuner->CH_Ctrl[13].bit[3] = 5; - Tuner->CH_Ctrl[13].val[3] = 0; - Tuner->CH_Ctrl[13].addr[4] = 110; - Tuner->CH_Ctrl[13].bit[4] = 6; - Tuner->CH_Ctrl[13].val[4] = 0; - Tuner->CH_Ctrl[13].addr[5] = 110; - Tuner->CH_Ctrl[13].bit[5] = 7; - Tuner->CH_Ctrl[13].val[5] = 1; - - Tuner->CH_Ctrl[14].Ctrl_Num = CHCAL_INT_MOD_RF ; - Tuner->CH_Ctrl[14].size = 7 ; - Tuner->CH_Ctrl[14].addr[0] = 14; - Tuner->CH_Ctrl[14].bit[0] = 0; - Tuner->CH_Ctrl[14].val[0] = 0; - Tuner->CH_Ctrl[14].addr[1] = 14; - Tuner->CH_Ctrl[14].bit[1] = 1; - Tuner->CH_Ctrl[14].val[1] = 0; - Tuner->CH_Ctrl[14].addr[2] = 14; - Tuner->CH_Ctrl[14].bit[2] = 2; - Tuner->CH_Ctrl[14].val[2] = 0; - Tuner->CH_Ctrl[14].addr[3] = 14; - Tuner->CH_Ctrl[14].bit[3] = 3; - Tuner->CH_Ctrl[14].val[3] = 0; - Tuner->CH_Ctrl[14].addr[4] = 14; - Tuner->CH_Ctrl[14].bit[4] = 4; - Tuner->CH_Ctrl[14].val[4] = 0; - Tuner->CH_Ctrl[14].addr[5] = 14; - Tuner->CH_Ctrl[14].bit[5] = 5; - Tuner->CH_Ctrl[14].val[5] = 0; - Tuner->CH_Ctrl[14].addr[6] = 14; - Tuner->CH_Ctrl[14].bit[6] = 6; - Tuner->CH_Ctrl[14].val[6] = 0; - - Tuner->CH_Ctrl[15].Ctrl_Num = CHCAL_FRAC_MOD_RF ; - Tuner->CH_Ctrl[15].size = 18 ; - Tuner->CH_Ctrl[15].addr[0] = 17; - Tuner->CH_Ctrl[15].bit[0] = 6; - Tuner->CH_Ctrl[15].val[0] = 0; - Tuner->CH_Ctrl[15].addr[1] = 17; - Tuner->CH_Ctrl[15].bit[1] = 7; - Tuner->CH_Ctrl[15].val[1] = 0; - Tuner->CH_Ctrl[15].addr[2] = 16; - Tuner->CH_Ctrl[15].bit[2] = 0; - Tuner->CH_Ctrl[15].val[2] = 0; - Tuner->CH_Ctrl[15].addr[3] = 16; - Tuner->CH_Ctrl[15].bit[3] = 1; - Tuner->CH_Ctrl[15].val[3] = 0; - Tuner->CH_Ctrl[15].addr[4] = 16; - Tuner->CH_Ctrl[15].bit[4] = 2; - Tuner->CH_Ctrl[15].val[4] = 0; - Tuner->CH_Ctrl[15].addr[5] = 16; - Tuner->CH_Ctrl[15].bit[5] = 3; - Tuner->CH_Ctrl[15].val[5] = 0; - Tuner->CH_Ctrl[15].addr[6] = 16; - Tuner->CH_Ctrl[15].bit[6] = 4; - Tuner->CH_Ctrl[15].val[6] = 0; - Tuner->CH_Ctrl[15].addr[7] = 16; - Tuner->CH_Ctrl[15].bit[7] = 5; - Tuner->CH_Ctrl[15].val[7] = 0; - Tuner->CH_Ctrl[15].addr[8] = 16; - Tuner->CH_Ctrl[15].bit[8] = 6; - Tuner->CH_Ctrl[15].val[8] = 0; - Tuner->CH_Ctrl[15].addr[9] = 16; - Tuner->CH_Ctrl[15].bit[9] = 7; - Tuner->CH_Ctrl[15].val[9] = 0; - Tuner->CH_Ctrl[15].addr[10] = 15; - Tuner->CH_Ctrl[15].bit[10] = 0; - Tuner->CH_Ctrl[15].val[10] = 0; - Tuner->CH_Ctrl[15].addr[11] = 15; - Tuner->CH_Ctrl[15].bit[11] = 1; - Tuner->CH_Ctrl[15].val[11] = 0; - Tuner->CH_Ctrl[15].addr[12] = 15; - Tuner->CH_Ctrl[15].bit[12] = 2; - Tuner->CH_Ctrl[15].val[12] = 0; - Tuner->CH_Ctrl[15].addr[13] = 15; - Tuner->CH_Ctrl[15].bit[13] = 3; - Tuner->CH_Ctrl[15].val[13] = 0; - Tuner->CH_Ctrl[15].addr[14] = 15; - Tuner->CH_Ctrl[15].bit[14] = 4; - Tuner->CH_Ctrl[15].val[14] = 0; - Tuner->CH_Ctrl[15].addr[15] = 15; - Tuner->CH_Ctrl[15].bit[15] = 5; - Tuner->CH_Ctrl[15].val[15] = 0; - Tuner->CH_Ctrl[15].addr[16] = 15; - Tuner->CH_Ctrl[15].bit[16] = 6; - Tuner->CH_Ctrl[15].val[16] = 1; - Tuner->CH_Ctrl[15].addr[17] = 15; - Tuner->CH_Ctrl[15].bit[17] = 7; - Tuner->CH_Ctrl[15].val[17] = 1; - - Tuner->CH_Ctrl[16].Ctrl_Num = RFSYN_LPF_R ; - Tuner->CH_Ctrl[16].size = 5 ; - Tuner->CH_Ctrl[16].addr[0] = 112; - Tuner->CH_Ctrl[16].bit[0] = 0; - Tuner->CH_Ctrl[16].val[0] = 0; - Tuner->CH_Ctrl[16].addr[1] = 112; - Tuner->CH_Ctrl[16].bit[1] = 1; - Tuner->CH_Ctrl[16].val[1] = 0; - Tuner->CH_Ctrl[16].addr[2] = 112; - Tuner->CH_Ctrl[16].bit[2] = 2; - Tuner->CH_Ctrl[16].val[2] = 0; - Tuner->CH_Ctrl[16].addr[3] = 112; - Tuner->CH_Ctrl[16].bit[3] = 3; - Tuner->CH_Ctrl[16].val[3] = 0; - Tuner->CH_Ctrl[16].addr[4] = 112; - Tuner->CH_Ctrl[16].bit[4] = 4; - Tuner->CH_Ctrl[16].val[4] = 1; - - Tuner->CH_Ctrl[17].Ctrl_Num = CHCAL_EN_INT_RF ; - Tuner->CH_Ctrl[17].size = 1 ; - Tuner->CH_Ctrl[17].addr[0] = 14; - Tuner->CH_Ctrl[17].bit[0] = 7; - Tuner->CH_Ctrl[17].val[0] = 0; - - Tuner->CH_Ctrl[18].Ctrl_Num = TG_LO_DIVVAL ; - Tuner->CH_Ctrl[18].size = 4 ; - Tuner->CH_Ctrl[18].addr[0] = 107; - Tuner->CH_Ctrl[18].bit[0] = 3; - Tuner->CH_Ctrl[18].val[0] = 0; - Tuner->CH_Ctrl[18].addr[1] = 107; - Tuner->CH_Ctrl[18].bit[1] = 4; - Tuner->CH_Ctrl[18].val[1] = 0; - Tuner->CH_Ctrl[18].addr[2] = 107; - Tuner->CH_Ctrl[18].bit[2] = 5; - Tuner->CH_Ctrl[18].val[2] = 0; - Tuner->CH_Ctrl[18].addr[3] = 107; - Tuner->CH_Ctrl[18].bit[3] = 6; - Tuner->CH_Ctrl[18].val[3] = 0; - - Tuner->CH_Ctrl[19].Ctrl_Num = TG_LO_SELVAL ; - Tuner->CH_Ctrl[19].size = 3 ; - Tuner->CH_Ctrl[19].addr[0] = 107; - Tuner->CH_Ctrl[19].bit[0] = 7; - Tuner->CH_Ctrl[19].val[0] = 1; - Tuner->CH_Ctrl[19].addr[1] = 106; - Tuner->CH_Ctrl[19].bit[1] = 0; - Tuner->CH_Ctrl[19].val[1] = 1; - Tuner->CH_Ctrl[19].addr[2] = 106; - Tuner->CH_Ctrl[19].bit[2] = 1; - Tuner->CH_Ctrl[19].val[2] = 1; - - Tuner->CH_Ctrl[20].Ctrl_Num = TG_DIV_VAL ; - Tuner->CH_Ctrl[20].size = 11 ; - Tuner->CH_Ctrl[20].addr[0] = 109; - Tuner->CH_Ctrl[20].bit[0] = 2; - Tuner->CH_Ctrl[20].val[0] = 0; - Tuner->CH_Ctrl[20].addr[1] = 109; - Tuner->CH_Ctrl[20].bit[1] = 3; - Tuner->CH_Ctrl[20].val[1] = 0; - Tuner->CH_Ctrl[20].addr[2] = 109; - Tuner->CH_Ctrl[20].bit[2] = 4; - Tuner->CH_Ctrl[20].val[2] = 0; - Tuner->CH_Ctrl[20].addr[3] = 109; - Tuner->CH_Ctrl[20].bit[3] = 5; - Tuner->CH_Ctrl[20].val[3] = 0; - Tuner->CH_Ctrl[20].addr[4] = 109; - Tuner->CH_Ctrl[20].bit[4] = 6; - Tuner->CH_Ctrl[20].val[4] = 0; - Tuner->CH_Ctrl[20].addr[5] = 109; - Tuner->CH_Ctrl[20].bit[5] = 7; - Tuner->CH_Ctrl[20].val[5] = 0; - Tuner->CH_Ctrl[20].addr[6] = 108; - Tuner->CH_Ctrl[20].bit[6] = 0; - Tuner->CH_Ctrl[20].val[6] = 0; - Tuner->CH_Ctrl[20].addr[7] = 108; - Tuner->CH_Ctrl[20].bit[7] = 1; - Tuner->CH_Ctrl[20].val[7] = 0; - Tuner->CH_Ctrl[20].addr[8] = 108; - Tuner->CH_Ctrl[20].bit[8] = 2; - Tuner->CH_Ctrl[20].val[8] = 1; - Tuner->CH_Ctrl[20].addr[9] = 108; - Tuner->CH_Ctrl[20].bit[9] = 3; - Tuner->CH_Ctrl[20].val[9] = 1; - Tuner->CH_Ctrl[20].addr[10] = 108; - Tuner->CH_Ctrl[20].bit[10] = 4; - Tuner->CH_Ctrl[20].val[10] = 1; - - Tuner->CH_Ctrl[21].Ctrl_Num = TG_VCO_BIAS ; - Tuner->CH_Ctrl[21].size = 6 ; - Tuner->CH_Ctrl[21].addr[0] = 106; - Tuner->CH_Ctrl[21].bit[0] = 2; - Tuner->CH_Ctrl[21].val[0] = 0; - Tuner->CH_Ctrl[21].addr[1] = 106; - Tuner->CH_Ctrl[21].bit[1] = 3; - Tuner->CH_Ctrl[21].val[1] = 0; - Tuner->CH_Ctrl[21].addr[2] = 106; - Tuner->CH_Ctrl[21].bit[2] = 4; - Tuner->CH_Ctrl[21].val[2] = 0; - Tuner->CH_Ctrl[21].addr[3] = 106; - Tuner->CH_Ctrl[21].bit[3] = 5; - Tuner->CH_Ctrl[21].val[3] = 0; - Tuner->CH_Ctrl[21].addr[4] = 106; - Tuner->CH_Ctrl[21].bit[4] = 6; - Tuner->CH_Ctrl[21].val[4] = 0; - Tuner->CH_Ctrl[21].addr[5] = 106; - Tuner->CH_Ctrl[21].bit[5] = 7; - Tuner->CH_Ctrl[21].val[5] = 1; - - Tuner->CH_Ctrl[22].Ctrl_Num = SEQ_EXTPOWERUP ; - Tuner->CH_Ctrl[22].size = 1 ; - Tuner->CH_Ctrl[22].addr[0] = 138; - Tuner->CH_Ctrl[22].bit[0] = 4; - Tuner->CH_Ctrl[22].val[0] = 1; - - Tuner->CH_Ctrl[23].Ctrl_Num = OVERRIDE_2 ; - Tuner->CH_Ctrl[23].size = 1 ; - Tuner->CH_Ctrl[23].addr[0] = 17; - Tuner->CH_Ctrl[23].bit[0] = 5; - Tuner->CH_Ctrl[23].val[0] = 0; - - Tuner->CH_Ctrl[24].Ctrl_Num = OVERRIDE_3 ; - Tuner->CH_Ctrl[24].size = 1 ; - Tuner->CH_Ctrl[24].addr[0] = 111; - Tuner->CH_Ctrl[24].bit[0] = 3; - Tuner->CH_Ctrl[24].val[0] = 0; - - Tuner->CH_Ctrl[25].Ctrl_Num = OVERRIDE_4 ; - Tuner->CH_Ctrl[25].size = 1 ; - Tuner->CH_Ctrl[25].addr[0] = 112; - Tuner->CH_Ctrl[25].bit[0] = 7; - Tuner->CH_Ctrl[25].val[0] = 0; - - Tuner->CH_Ctrl[26].Ctrl_Num = SEQ_FSM_PULSE ; - Tuner->CH_Ctrl[26].size = 1 ; - Tuner->CH_Ctrl[26].addr[0] = 136; - Tuner->CH_Ctrl[26].bit[0] = 7; - Tuner->CH_Ctrl[26].val[0] = 0; - - Tuner->CH_Ctrl[27].Ctrl_Num = GPIO_4B ; - Tuner->CH_Ctrl[27].size = 1 ; - Tuner->CH_Ctrl[27].addr[0] = 149; - Tuner->CH_Ctrl[27].bit[0] = 7; - Tuner->CH_Ctrl[27].val[0] = 0; - - Tuner->CH_Ctrl[28].Ctrl_Num = GPIO_3B ; - Tuner->CH_Ctrl[28].size = 1 ; - Tuner->CH_Ctrl[28].addr[0] = 149; - Tuner->CH_Ctrl[28].bit[0] = 6; - Tuner->CH_Ctrl[28].val[0] = 0; - - Tuner->CH_Ctrl[29].Ctrl_Num = GPIO_4 ; - Tuner->CH_Ctrl[29].size = 1 ; - Tuner->CH_Ctrl[29].addr[0] = 149; - Tuner->CH_Ctrl[29].bit[0] = 5; - Tuner->CH_Ctrl[29].val[0] = 1; - - Tuner->CH_Ctrl[30].Ctrl_Num = GPIO_3 ; - Tuner->CH_Ctrl[30].size = 1 ; - Tuner->CH_Ctrl[30].addr[0] = 149; - Tuner->CH_Ctrl[30].bit[0] = 4; - Tuner->CH_Ctrl[30].val[0] = 1; - - Tuner->CH_Ctrl[31].Ctrl_Num = GPIO_1B ; - Tuner->CH_Ctrl[31].size = 1 ; - Tuner->CH_Ctrl[31].addr[0] = 149; - Tuner->CH_Ctrl[31].bit[0] = 3; - Tuner->CH_Ctrl[31].val[0] = 0; - - Tuner->CH_Ctrl[32].Ctrl_Num = DAC_A_ENABLE ; - Tuner->CH_Ctrl[32].size = 1 ; - Tuner->CH_Ctrl[32].addr[0] = 93; - Tuner->CH_Ctrl[32].bit[0] = 1; - Tuner->CH_Ctrl[32].val[0] = 0; - - Tuner->CH_Ctrl[33].Ctrl_Num = DAC_B_ENABLE ; - Tuner->CH_Ctrl[33].size = 1 ; - Tuner->CH_Ctrl[33].addr[0] = 93; - Tuner->CH_Ctrl[33].bit[0] = 0; - Tuner->CH_Ctrl[33].val[0] = 0; - - Tuner->CH_Ctrl[34].Ctrl_Num = DAC_DIN_A ; - Tuner->CH_Ctrl[34].size = 6 ; - Tuner->CH_Ctrl[34].addr[0] = 92; - Tuner->CH_Ctrl[34].bit[0] = 2; - Tuner->CH_Ctrl[34].val[0] = 0; - Tuner->CH_Ctrl[34].addr[1] = 92; - Tuner->CH_Ctrl[34].bit[1] = 3; - Tuner->CH_Ctrl[34].val[1] = 0; - Tuner->CH_Ctrl[34].addr[2] = 92; - Tuner->CH_Ctrl[34].bit[2] = 4; - Tuner->CH_Ctrl[34].val[2] = 0; - Tuner->CH_Ctrl[34].addr[3] = 92; - Tuner->CH_Ctrl[34].bit[3] = 5; - Tuner->CH_Ctrl[34].val[3] = 0; - Tuner->CH_Ctrl[34].addr[4] = 92; - Tuner->CH_Ctrl[34].bit[4] = 6; - Tuner->CH_Ctrl[34].val[4] = 0; - Tuner->CH_Ctrl[34].addr[5] = 92; - Tuner->CH_Ctrl[34].bit[5] = 7; - Tuner->CH_Ctrl[34].val[5] = 0; - - Tuner->CH_Ctrl[35].Ctrl_Num = DAC_DIN_B ; - Tuner->CH_Ctrl[35].size = 6 ; - Tuner->CH_Ctrl[35].addr[0] = 93; - Tuner->CH_Ctrl[35].bit[0] = 2; - Tuner->CH_Ctrl[35].val[0] = 0; - Tuner->CH_Ctrl[35].addr[1] = 93; - Tuner->CH_Ctrl[35].bit[1] = 3; - Tuner->CH_Ctrl[35].val[1] = 0; - Tuner->CH_Ctrl[35].addr[2] = 93; - Tuner->CH_Ctrl[35].bit[2] = 4; - Tuner->CH_Ctrl[35].val[2] = 0; - Tuner->CH_Ctrl[35].addr[3] = 93; - Tuner->CH_Ctrl[35].bit[3] = 5; - Tuner->CH_Ctrl[35].val[3] = 0; - Tuner->CH_Ctrl[35].addr[4] = 93; - Tuner->CH_Ctrl[35].bit[4] = 6; - Tuner->CH_Ctrl[35].val[4] = 0; - Tuner->CH_Ctrl[35].addr[5] = 93; - Tuner->CH_Ctrl[35].bit[5] = 7; - Tuner->CH_Ctrl[35].val[5] = 0; + struct mxl5005s_state *state = fe->demodulator_priv; + state->Init_Ctrl_Num = INITCTRL_NUM; + + state->Init_Ctrl[0].Ctrl_Num = DN_IQTN_AMP_CUT ; + state->Init_Ctrl[0].size = 1 ; + state->Init_Ctrl[0].addr[0] = 73; + state->Init_Ctrl[0].bit[0] = 7; + state->Init_Ctrl[0].val[0] = 0; + + state->Init_Ctrl[1].Ctrl_Num = BB_MODE ; + state->Init_Ctrl[1].size = 1 ; + state->Init_Ctrl[1].addr[0] = 53; + state->Init_Ctrl[1].bit[0] = 2; + state->Init_Ctrl[1].val[0] = 1; + + state->Init_Ctrl[2].Ctrl_Num = BB_BUF ; + state->Init_Ctrl[2].size = 2 ; + state->Init_Ctrl[2].addr[0] = 53; + state->Init_Ctrl[2].bit[0] = 1; + state->Init_Ctrl[2].val[0] = 0; + state->Init_Ctrl[2].addr[1] = 57; + state->Init_Ctrl[2].bit[1] = 0; + state->Init_Ctrl[2].val[1] = 1; + + state->Init_Ctrl[3].Ctrl_Num = BB_BUF_OA ; + state->Init_Ctrl[3].size = 1 ; + state->Init_Ctrl[3].addr[0] = 53; + state->Init_Ctrl[3].bit[0] = 0; + state->Init_Ctrl[3].val[0] = 0; + + state->Init_Ctrl[4].Ctrl_Num = BB_ALPF_BANDSELECT ; + state->Init_Ctrl[4].size = 3 ; + state->Init_Ctrl[4].addr[0] = 53; + state->Init_Ctrl[4].bit[0] = 5; + state->Init_Ctrl[4].val[0] = 0; + state->Init_Ctrl[4].addr[1] = 53; + state->Init_Ctrl[4].bit[1] = 6; + state->Init_Ctrl[4].val[1] = 0; + state->Init_Ctrl[4].addr[2] = 53; + state->Init_Ctrl[4].bit[2] = 7; + state->Init_Ctrl[4].val[2] = 1; + + state->Init_Ctrl[5].Ctrl_Num = BB_IQSWAP ; + state->Init_Ctrl[5].size = 1 ; + state->Init_Ctrl[5].addr[0] = 59; + state->Init_Ctrl[5].bit[0] = 0; + state->Init_Ctrl[5].val[0] = 0; + + state->Init_Ctrl[6].Ctrl_Num = BB_DLPF_BANDSEL ; + state->Init_Ctrl[6].size = 2 ; + state->Init_Ctrl[6].addr[0] = 53; + state->Init_Ctrl[6].bit[0] = 3; + state->Init_Ctrl[6].val[0] = 0; + state->Init_Ctrl[6].addr[1] = 53; + state->Init_Ctrl[6].bit[1] = 4; + state->Init_Ctrl[6].val[1] = 1; + + state->Init_Ctrl[7].Ctrl_Num = RFSYN_CHP_GAIN ; + state->Init_Ctrl[7].size = 4 ; + state->Init_Ctrl[7].addr[0] = 22; + state->Init_Ctrl[7].bit[0] = 4; + state->Init_Ctrl[7].val[0] = 0; + state->Init_Ctrl[7].addr[1] = 22; + state->Init_Ctrl[7].bit[1] = 5; + state->Init_Ctrl[7].val[1] = 1; + state->Init_Ctrl[7].addr[2] = 22; + state->Init_Ctrl[7].bit[2] = 6; + state->Init_Ctrl[7].val[2] = 1; + state->Init_Ctrl[7].addr[3] = 22; + state->Init_Ctrl[7].bit[3] = 7; + state->Init_Ctrl[7].val[3] = 0; + + state->Init_Ctrl[8].Ctrl_Num = RFSYN_EN_CHP_HIGAIN ; + state->Init_Ctrl[8].size = 1 ; + state->Init_Ctrl[8].addr[0] = 22; + state->Init_Ctrl[8].bit[0] = 2; + state->Init_Ctrl[8].val[0] = 0; + + state->Init_Ctrl[9].Ctrl_Num = AGC_IF ; + state->Init_Ctrl[9].size = 4 ; + state->Init_Ctrl[9].addr[0] = 76; + state->Init_Ctrl[9].bit[0] = 0; + state->Init_Ctrl[9].val[0] = 1; + state->Init_Ctrl[9].addr[1] = 76; + state->Init_Ctrl[9].bit[1] = 1; + state->Init_Ctrl[9].val[1] = 1; + state->Init_Ctrl[9].addr[2] = 76; + state->Init_Ctrl[9].bit[2] = 2; + state->Init_Ctrl[9].val[2] = 0; + state->Init_Ctrl[9].addr[3] = 76; + state->Init_Ctrl[9].bit[3] = 3; + state->Init_Ctrl[9].val[3] = 1; + + state->Init_Ctrl[10].Ctrl_Num = AGC_RF ; + state->Init_Ctrl[10].size = 4 ; + state->Init_Ctrl[10].addr[0] = 76; + state->Init_Ctrl[10].bit[0] = 4; + state->Init_Ctrl[10].val[0] = 1; + state->Init_Ctrl[10].addr[1] = 76; + state->Init_Ctrl[10].bit[1] = 5; + state->Init_Ctrl[10].val[1] = 1; + state->Init_Ctrl[10].addr[2] = 76; + state->Init_Ctrl[10].bit[2] = 6; + state->Init_Ctrl[10].val[2] = 0; + state->Init_Ctrl[10].addr[3] = 76; + state->Init_Ctrl[10].bit[3] = 7; + state->Init_Ctrl[10].val[3] = 1; + + state->Init_Ctrl[11].Ctrl_Num = IF_DIVVAL ; + state->Init_Ctrl[11].size = 5 ; + state->Init_Ctrl[11].addr[0] = 43; + state->Init_Ctrl[11].bit[0] = 3; + state->Init_Ctrl[11].val[0] = 0; + state->Init_Ctrl[11].addr[1] = 43; + state->Init_Ctrl[11].bit[1] = 4; + state->Init_Ctrl[11].val[1] = 0; + state->Init_Ctrl[11].addr[2] = 43; + state->Init_Ctrl[11].bit[2] = 5; + state->Init_Ctrl[11].val[2] = 0; + state->Init_Ctrl[11].addr[3] = 43; + state->Init_Ctrl[11].bit[3] = 6; + state->Init_Ctrl[11].val[3] = 1; + state->Init_Ctrl[11].addr[4] = 43; + state->Init_Ctrl[11].bit[4] = 7; + state->Init_Ctrl[11].val[4] = 0; + + state->Init_Ctrl[12].Ctrl_Num = IF_VCO_BIAS ; + state->Init_Ctrl[12].size = 6 ; + state->Init_Ctrl[12].addr[0] = 44; + state->Init_Ctrl[12].bit[0] = 2; + state->Init_Ctrl[12].val[0] = 0; + state->Init_Ctrl[12].addr[1] = 44; + state->Init_Ctrl[12].bit[1] = 3; + state->Init_Ctrl[12].val[1] = 0; + state->Init_Ctrl[12].addr[2] = 44; + state->Init_Ctrl[12].bit[2] = 4; + state->Init_Ctrl[12].val[2] = 0; + state->Init_Ctrl[12].addr[3] = 44; + state->Init_Ctrl[12].bit[3] = 5; + state->Init_Ctrl[12].val[3] = 1; + state->Init_Ctrl[12].addr[4] = 44; + state->Init_Ctrl[12].bit[4] = 6; + state->Init_Ctrl[12].val[4] = 0; + state->Init_Ctrl[12].addr[5] = 44; + state->Init_Ctrl[12].bit[5] = 7; + state->Init_Ctrl[12].val[5] = 0; + + state->Init_Ctrl[13].Ctrl_Num = CHCAL_INT_MOD_IF ; + state->Init_Ctrl[13].size = 7 ; + state->Init_Ctrl[13].addr[0] = 11; + state->Init_Ctrl[13].bit[0] = 0; + state->Init_Ctrl[13].val[0] = 1; + state->Init_Ctrl[13].addr[1] = 11; + state->Init_Ctrl[13].bit[1] = 1; + state->Init_Ctrl[13].val[1] = 0; + state->Init_Ctrl[13].addr[2] = 11; + state->Init_Ctrl[13].bit[2] = 2; + state->Init_Ctrl[13].val[2] = 0; + state->Init_Ctrl[13].addr[3] = 11; + state->Init_Ctrl[13].bit[3] = 3; + state->Init_Ctrl[13].val[3] = 1; + state->Init_Ctrl[13].addr[4] = 11; + state->Init_Ctrl[13].bit[4] = 4; + state->Init_Ctrl[13].val[4] = 1; + state->Init_Ctrl[13].addr[5] = 11; + state->Init_Ctrl[13].bit[5] = 5; + state->Init_Ctrl[13].val[5] = 0; + state->Init_Ctrl[13].addr[6] = 11; + state->Init_Ctrl[13].bit[6] = 6; + state->Init_Ctrl[13].val[6] = 0; + + state->Init_Ctrl[14].Ctrl_Num = CHCAL_FRAC_MOD_IF ; + state->Init_Ctrl[14].size = 16 ; + state->Init_Ctrl[14].addr[0] = 13; + state->Init_Ctrl[14].bit[0] = 0; + state->Init_Ctrl[14].val[0] = 0; + state->Init_Ctrl[14].addr[1] = 13; + state->Init_Ctrl[14].bit[1] = 1; + state->Init_Ctrl[14].val[1] = 0; + state->Init_Ctrl[14].addr[2] = 13; + state->Init_Ctrl[14].bit[2] = 2; + state->Init_Ctrl[14].val[2] = 0; + state->Init_Ctrl[14].addr[3] = 13; + state->Init_Ctrl[14].bit[3] = 3; + state->Init_Ctrl[14].val[3] = 0; + state->Init_Ctrl[14].addr[4] = 13; + state->Init_Ctrl[14].bit[4] = 4; + state->Init_Ctrl[14].val[4] = 0; + state->Init_Ctrl[14].addr[5] = 13; + state->Init_Ctrl[14].bit[5] = 5; + state->Init_Ctrl[14].val[5] = 0; + state->Init_Ctrl[14].addr[6] = 13; + state->Init_Ctrl[14].bit[6] = 6; + state->Init_Ctrl[14].val[6] = 0; + state->Init_Ctrl[14].addr[7] = 13; + state->Init_Ctrl[14].bit[7] = 7; + state->Init_Ctrl[14].val[7] = 0; + state->Init_Ctrl[14].addr[8] = 12; + state->Init_Ctrl[14].bit[8] = 0; + state->Init_Ctrl[14].val[8] = 0; + state->Init_Ctrl[14].addr[9] = 12; + state->Init_Ctrl[14].bit[9] = 1; + state->Init_Ctrl[14].val[9] = 0; + state->Init_Ctrl[14].addr[10] = 12; + state->Init_Ctrl[14].bit[10] = 2; + state->Init_Ctrl[14].val[10] = 0; + state->Init_Ctrl[14].addr[11] = 12; + state->Init_Ctrl[14].bit[11] = 3; + state->Init_Ctrl[14].val[11] = 0; + state->Init_Ctrl[14].addr[12] = 12; + state->Init_Ctrl[14].bit[12] = 4; + state->Init_Ctrl[14].val[12] = 0; + state->Init_Ctrl[14].addr[13] = 12; + state->Init_Ctrl[14].bit[13] = 5; + state->Init_Ctrl[14].val[13] = 1; + state->Init_Ctrl[14].addr[14] = 12; + state->Init_Ctrl[14].bit[14] = 6; + state->Init_Ctrl[14].val[14] = 1; + state->Init_Ctrl[14].addr[15] = 12; + state->Init_Ctrl[14].bit[15] = 7; + state->Init_Ctrl[14].val[15] = 0; + + state->Init_Ctrl[15].Ctrl_Num = DRV_RES_SEL ; + state->Init_Ctrl[15].size = 3 ; + state->Init_Ctrl[15].addr[0] = 147; + state->Init_Ctrl[15].bit[0] = 2; + state->Init_Ctrl[15].val[0] = 0; + state->Init_Ctrl[15].addr[1] = 147; + state->Init_Ctrl[15].bit[1] = 3; + state->Init_Ctrl[15].val[1] = 1; + state->Init_Ctrl[15].addr[2] = 147; + state->Init_Ctrl[15].bit[2] = 4; + state->Init_Ctrl[15].val[2] = 1; + + state->Init_Ctrl[16].Ctrl_Num = I_DRIVER ; + state->Init_Ctrl[16].size = 2 ; + state->Init_Ctrl[16].addr[0] = 147; + state->Init_Ctrl[16].bit[0] = 0; + state->Init_Ctrl[16].val[0] = 0; + state->Init_Ctrl[16].addr[1] = 147; + state->Init_Ctrl[16].bit[1] = 1; + state->Init_Ctrl[16].val[1] = 1; + + state->Init_Ctrl[17].Ctrl_Num = EN_AAF ; + state->Init_Ctrl[17].size = 1 ; + state->Init_Ctrl[17].addr[0] = 147; + state->Init_Ctrl[17].bit[0] = 7; + state->Init_Ctrl[17].val[0] = 0; + + state->Init_Ctrl[18].Ctrl_Num = EN_3P ; + state->Init_Ctrl[18].size = 1 ; + state->Init_Ctrl[18].addr[0] = 147; + state->Init_Ctrl[18].bit[0] = 6; + state->Init_Ctrl[18].val[0] = 0; + + state->Init_Ctrl[19].Ctrl_Num = EN_AUX_3P ; + state->Init_Ctrl[19].size = 1 ; + state->Init_Ctrl[19].addr[0] = 156; + state->Init_Ctrl[19].bit[0] = 0; + state->Init_Ctrl[19].val[0] = 0; + + state->Init_Ctrl[20].Ctrl_Num = SEL_AAF_BAND ; + state->Init_Ctrl[20].size = 1 ; + state->Init_Ctrl[20].addr[0] = 147; + state->Init_Ctrl[20].bit[0] = 5; + state->Init_Ctrl[20].val[0] = 0; + + state->Init_Ctrl[21].Ctrl_Num = SEQ_ENCLK16_CLK_OUT ; + state->Init_Ctrl[21].size = 1 ; + state->Init_Ctrl[21].addr[0] = 137; + state->Init_Ctrl[21].bit[0] = 4; + state->Init_Ctrl[21].val[0] = 0; + + state->Init_Ctrl[22].Ctrl_Num = SEQ_SEL4_16B ; + state->Init_Ctrl[22].size = 1 ; + state->Init_Ctrl[22].addr[0] = 137; + state->Init_Ctrl[22].bit[0] = 7; + state->Init_Ctrl[22].val[0] = 0; + + state->Init_Ctrl[23].Ctrl_Num = XTAL_CAPSELECT ; + state->Init_Ctrl[23].size = 1 ; + state->Init_Ctrl[23].addr[0] = 91; + state->Init_Ctrl[23].bit[0] = 5; + state->Init_Ctrl[23].val[0] = 1; + + state->Init_Ctrl[24].Ctrl_Num = IF_SEL_DBL ; + state->Init_Ctrl[24].size = 1 ; + state->Init_Ctrl[24].addr[0] = 43; + state->Init_Ctrl[24].bit[0] = 0; + state->Init_Ctrl[24].val[0] = 1; + + state->Init_Ctrl[25].Ctrl_Num = RFSYN_R_DIV ; + state->Init_Ctrl[25].size = 2 ; + state->Init_Ctrl[25].addr[0] = 22; + state->Init_Ctrl[25].bit[0] = 0; + state->Init_Ctrl[25].val[0] = 1; + state->Init_Ctrl[25].addr[1] = 22; + state->Init_Ctrl[25].bit[1] = 1; + state->Init_Ctrl[25].val[1] = 1; + + state->Init_Ctrl[26].Ctrl_Num = SEQ_EXTSYNTHCALIF ; + state->Init_Ctrl[26].size = 1 ; + state->Init_Ctrl[26].addr[0] = 134; + state->Init_Ctrl[26].bit[0] = 2; + state->Init_Ctrl[26].val[0] = 0; + + state->Init_Ctrl[27].Ctrl_Num = SEQ_EXTDCCAL ; + state->Init_Ctrl[27].size = 1 ; + state->Init_Ctrl[27].addr[0] = 137; + state->Init_Ctrl[27].bit[0] = 3; + state->Init_Ctrl[27].val[0] = 0; + + state->Init_Ctrl[28].Ctrl_Num = AGC_EN_RSSI ; + state->Init_Ctrl[28].size = 1 ; + state->Init_Ctrl[28].addr[0] = 77; + state->Init_Ctrl[28].bit[0] = 7; + state->Init_Ctrl[28].val[0] = 0; + + state->Init_Ctrl[29].Ctrl_Num = RFA_ENCLKRFAGC ; + state->Init_Ctrl[29].size = 1 ; + state->Init_Ctrl[29].addr[0] = 166; + state->Init_Ctrl[29].bit[0] = 7; + state->Init_Ctrl[29].val[0] = 1; + + state->Init_Ctrl[30].Ctrl_Num = RFA_RSSI_REFH ; + state->Init_Ctrl[30].size = 3 ; + state->Init_Ctrl[30].addr[0] = 166; + state->Init_Ctrl[30].bit[0] = 0; + state->Init_Ctrl[30].val[0] = 0; + state->Init_Ctrl[30].addr[1] = 166; + state->Init_Ctrl[30].bit[1] = 1; + state->Init_Ctrl[30].val[1] = 1; + state->Init_Ctrl[30].addr[2] = 166; + state->Init_Ctrl[30].bit[2] = 2; + state->Init_Ctrl[30].val[2] = 1; + + state->Init_Ctrl[31].Ctrl_Num = RFA_RSSI_REF ; + state->Init_Ctrl[31].size = 3 ; + state->Init_Ctrl[31].addr[0] = 166; + state->Init_Ctrl[31].bit[0] = 3; + state->Init_Ctrl[31].val[0] = 1; + state->Init_Ctrl[31].addr[1] = 166; + state->Init_Ctrl[31].bit[1] = 4; + state->Init_Ctrl[31].val[1] = 0; + state->Init_Ctrl[31].addr[2] = 166; + state->Init_Ctrl[31].bit[2] = 5; + state->Init_Ctrl[31].val[2] = 1; + + state->Init_Ctrl[32].Ctrl_Num = RFA_RSSI_REFL ; + state->Init_Ctrl[32].size = 3 ; + state->Init_Ctrl[32].addr[0] = 167; + state->Init_Ctrl[32].bit[0] = 0; + state->Init_Ctrl[32].val[0] = 1; + state->Init_Ctrl[32].addr[1] = 167; + state->Init_Ctrl[32].bit[1] = 1; + state->Init_Ctrl[32].val[1] = 1; + state->Init_Ctrl[32].addr[2] = 167; + state->Init_Ctrl[32].bit[2] = 2; + state->Init_Ctrl[32].val[2] = 0; + + state->Init_Ctrl[33].Ctrl_Num = RFA_FLR ; + state->Init_Ctrl[33].size = 4 ; + state->Init_Ctrl[33].addr[0] = 168; + state->Init_Ctrl[33].bit[0] = 0; + state->Init_Ctrl[33].val[0] = 0; + state->Init_Ctrl[33].addr[1] = 168; + state->Init_Ctrl[33].bit[1] = 1; + state->Init_Ctrl[33].val[1] = 1; + state->Init_Ctrl[33].addr[2] = 168; + state->Init_Ctrl[33].bit[2] = 2; + state->Init_Ctrl[33].val[2] = 0; + state->Init_Ctrl[33].addr[3] = 168; + state->Init_Ctrl[33].bit[3] = 3; + state->Init_Ctrl[33].val[3] = 0; + + state->Init_Ctrl[34].Ctrl_Num = RFA_CEIL ; + state->Init_Ctrl[34].size = 4 ; + state->Init_Ctrl[34].addr[0] = 168; + state->Init_Ctrl[34].bit[0] = 4; + state->Init_Ctrl[34].val[0] = 1; + state->Init_Ctrl[34].addr[1] = 168; + state->Init_Ctrl[34].bit[1] = 5; + state->Init_Ctrl[34].val[1] = 1; + state->Init_Ctrl[34].addr[2] = 168; + state->Init_Ctrl[34].bit[2] = 6; + state->Init_Ctrl[34].val[2] = 1; + state->Init_Ctrl[34].addr[3] = 168; + state->Init_Ctrl[34].bit[3] = 7; + state->Init_Ctrl[34].val[3] = 1; + + state->Init_Ctrl[35].Ctrl_Num = SEQ_EXTIQFSMPULSE ; + state->Init_Ctrl[35].size = 1 ; + state->Init_Ctrl[35].addr[0] = 135; + state->Init_Ctrl[35].bit[0] = 0; + state->Init_Ctrl[35].val[0] = 0; + + state->Init_Ctrl[36].Ctrl_Num = OVERRIDE_1 ; + state->Init_Ctrl[36].size = 1 ; + state->Init_Ctrl[36].addr[0] = 56; + state->Init_Ctrl[36].bit[0] = 3; + state->Init_Ctrl[36].val[0] = 0; + + state->Init_Ctrl[37].Ctrl_Num = BB_INITSTATE_DLPF_TUNE ; + state->Init_Ctrl[37].size = 7 ; + state->Init_Ctrl[37].addr[0] = 59; + state->Init_Ctrl[37].bit[0] = 1; + state->Init_Ctrl[37].val[0] = 0; + state->Init_Ctrl[37].addr[1] = 59; + state->Init_Ctrl[37].bit[1] = 2; + state->Init_Ctrl[37].val[1] = 0; + state->Init_Ctrl[37].addr[2] = 59; + state->Init_Ctrl[37].bit[2] = 3; + state->Init_Ctrl[37].val[2] = 0; + state->Init_Ctrl[37].addr[3] = 59; + state->Init_Ctrl[37].bit[3] = 4; + state->Init_Ctrl[37].val[3] = 0; + state->Init_Ctrl[37].addr[4] = 59; + state->Init_Ctrl[37].bit[4] = 5; + state->Init_Ctrl[37].val[4] = 0; + state->Init_Ctrl[37].addr[5] = 59; + state->Init_Ctrl[37].bit[5] = 6; + state->Init_Ctrl[37].val[5] = 0; + state->Init_Ctrl[37].addr[6] = 59; + state->Init_Ctrl[37].bit[6] = 7; + state->Init_Ctrl[37].val[6] = 0; + + state->Init_Ctrl[38].Ctrl_Num = TG_R_DIV ; + state->Init_Ctrl[38].size = 6 ; + state->Init_Ctrl[38].addr[0] = 32; + state->Init_Ctrl[38].bit[0] = 2; + state->Init_Ctrl[38].val[0] = 0; + state->Init_Ctrl[38].addr[1] = 32; + state->Init_Ctrl[38].bit[1] = 3; + state->Init_Ctrl[38].val[1] = 0; + state->Init_Ctrl[38].addr[2] = 32; + state->Init_Ctrl[38].bit[2] = 4; + state->Init_Ctrl[38].val[2] = 0; + state->Init_Ctrl[38].addr[3] = 32; + state->Init_Ctrl[38].bit[3] = 5; + state->Init_Ctrl[38].val[3] = 0; + state->Init_Ctrl[38].addr[4] = 32; + state->Init_Ctrl[38].bit[4] = 6; + state->Init_Ctrl[38].val[4] = 1; + state->Init_Ctrl[38].addr[5] = 32; + state->Init_Ctrl[38].bit[5] = 7; + state->Init_Ctrl[38].val[5] = 0; + + state->Init_Ctrl[39].Ctrl_Num = EN_CHP_LIN_B ; + state->Init_Ctrl[39].size = 1 ; + state->Init_Ctrl[39].addr[0] = 25; + state->Init_Ctrl[39].bit[0] = 3; + state->Init_Ctrl[39].val[0] = 1; + + + state->CH_Ctrl_Num = CHCTRL_NUM ; + + state->CH_Ctrl[0].Ctrl_Num = DN_POLY ; + state->CH_Ctrl[0].size = 2 ; + state->CH_Ctrl[0].addr[0] = 68; + state->CH_Ctrl[0].bit[0] = 6; + state->CH_Ctrl[0].val[0] = 1; + state->CH_Ctrl[0].addr[1] = 68; + state->CH_Ctrl[0].bit[1] = 7; + state->CH_Ctrl[0].val[1] = 1; + + state->CH_Ctrl[1].Ctrl_Num = DN_RFGAIN ; + state->CH_Ctrl[1].size = 2 ; + state->CH_Ctrl[1].addr[0] = 70; + state->CH_Ctrl[1].bit[0] = 6; + state->CH_Ctrl[1].val[0] = 1; + state->CH_Ctrl[1].addr[1] = 70; + state->CH_Ctrl[1].bit[1] = 7; + state->CH_Ctrl[1].val[1] = 0; + + state->CH_Ctrl[2].Ctrl_Num = DN_CAP_RFLPF ; + state->CH_Ctrl[2].size = 9 ; + state->CH_Ctrl[2].addr[0] = 69; + state->CH_Ctrl[2].bit[0] = 5; + state->CH_Ctrl[2].val[0] = 0; + state->CH_Ctrl[2].addr[1] = 69; + state->CH_Ctrl[2].bit[1] = 6; + state->CH_Ctrl[2].val[1] = 0; + state->CH_Ctrl[2].addr[2] = 69; + state->CH_Ctrl[2].bit[2] = 7; + state->CH_Ctrl[2].val[2] = 0; + state->CH_Ctrl[2].addr[3] = 68; + state->CH_Ctrl[2].bit[3] = 0; + state->CH_Ctrl[2].val[3] = 0; + state->CH_Ctrl[2].addr[4] = 68; + state->CH_Ctrl[2].bit[4] = 1; + state->CH_Ctrl[2].val[4] = 0; + state->CH_Ctrl[2].addr[5] = 68; + state->CH_Ctrl[2].bit[5] = 2; + state->CH_Ctrl[2].val[5] = 0; + state->CH_Ctrl[2].addr[6] = 68; + state->CH_Ctrl[2].bit[6] = 3; + state->CH_Ctrl[2].val[6] = 0; + state->CH_Ctrl[2].addr[7] = 68; + state->CH_Ctrl[2].bit[7] = 4; + state->CH_Ctrl[2].val[7] = 0; + state->CH_Ctrl[2].addr[8] = 68; + state->CH_Ctrl[2].bit[8] = 5; + state->CH_Ctrl[2].val[8] = 0; + + state->CH_Ctrl[3].Ctrl_Num = DN_EN_VHFUHFBAR ; + state->CH_Ctrl[3].size = 1 ; + state->CH_Ctrl[3].addr[0] = 70; + state->CH_Ctrl[3].bit[0] = 5; + state->CH_Ctrl[3].val[0] = 0; + + state->CH_Ctrl[4].Ctrl_Num = DN_GAIN_ADJUST ; + state->CH_Ctrl[4].size = 3 ; + state->CH_Ctrl[4].addr[0] = 73; + state->CH_Ctrl[4].bit[0] = 4; + state->CH_Ctrl[4].val[0] = 0; + state->CH_Ctrl[4].addr[1] = 73; + state->CH_Ctrl[4].bit[1] = 5; + state->CH_Ctrl[4].val[1] = 1; + state->CH_Ctrl[4].addr[2] = 73; + state->CH_Ctrl[4].bit[2] = 6; + state->CH_Ctrl[4].val[2] = 0; + + state->CH_Ctrl[5].Ctrl_Num = DN_IQTNBUF_AMP ; + state->CH_Ctrl[5].size = 4 ; + state->CH_Ctrl[5].addr[0] = 70; + state->CH_Ctrl[5].bit[0] = 0; + state->CH_Ctrl[5].val[0] = 0; + state->CH_Ctrl[5].addr[1] = 70; + state->CH_Ctrl[5].bit[1] = 1; + state->CH_Ctrl[5].val[1] = 0; + state->CH_Ctrl[5].addr[2] = 70; + state->CH_Ctrl[5].bit[2] = 2; + state->CH_Ctrl[5].val[2] = 0; + state->CH_Ctrl[5].addr[3] = 70; + state->CH_Ctrl[5].bit[3] = 3; + state->CH_Ctrl[5].val[3] = 0; + + state->CH_Ctrl[6].Ctrl_Num = DN_IQTNGNBFBIAS_BST ; + state->CH_Ctrl[6].size = 1 ; + state->CH_Ctrl[6].addr[0] = 70; + state->CH_Ctrl[6].bit[0] = 4; + state->CH_Ctrl[6].val[0] = 1; + + state->CH_Ctrl[7].Ctrl_Num = RFSYN_EN_OUTMUX ; + state->CH_Ctrl[7].size = 1 ; + state->CH_Ctrl[7].addr[0] = 111; + state->CH_Ctrl[7].bit[0] = 4; + state->CH_Ctrl[7].val[0] = 0; + + state->CH_Ctrl[8].Ctrl_Num = RFSYN_SEL_VCO_OUT ; + state->CH_Ctrl[8].size = 1 ; + state->CH_Ctrl[8].addr[0] = 111; + state->CH_Ctrl[8].bit[0] = 7; + state->CH_Ctrl[8].val[0] = 1; + + state->CH_Ctrl[9].Ctrl_Num = RFSYN_SEL_VCO_HI ; + state->CH_Ctrl[9].size = 1 ; + state->CH_Ctrl[9].addr[0] = 111; + state->CH_Ctrl[9].bit[0] = 6; + state->CH_Ctrl[9].val[0] = 1; + + state->CH_Ctrl[10].Ctrl_Num = RFSYN_SEL_DIVM ; + state->CH_Ctrl[10].size = 1 ; + state->CH_Ctrl[10].addr[0] = 111; + state->CH_Ctrl[10].bit[0] = 5; + state->CH_Ctrl[10].val[0] = 0; + + state->CH_Ctrl[11].Ctrl_Num = RFSYN_RF_DIV_BIAS ; + state->CH_Ctrl[11].size = 2 ; + state->CH_Ctrl[11].addr[0] = 110; + state->CH_Ctrl[11].bit[0] = 0; + state->CH_Ctrl[11].val[0] = 1; + state->CH_Ctrl[11].addr[1] = 110; + state->CH_Ctrl[11].bit[1] = 1; + state->CH_Ctrl[11].val[1] = 0; + + state->CH_Ctrl[12].Ctrl_Num = DN_SEL_FREQ ; + state->CH_Ctrl[12].size = 3 ; + state->CH_Ctrl[12].addr[0] = 69; + state->CH_Ctrl[12].bit[0] = 2; + state->CH_Ctrl[12].val[0] = 0; + state->CH_Ctrl[12].addr[1] = 69; + state->CH_Ctrl[12].bit[1] = 3; + state->CH_Ctrl[12].val[1] = 0; + state->CH_Ctrl[12].addr[2] = 69; + state->CH_Ctrl[12].bit[2] = 4; + state->CH_Ctrl[12].val[2] = 0; + + state->CH_Ctrl[13].Ctrl_Num = RFSYN_VCO_BIAS ; + state->CH_Ctrl[13].size = 6 ; + state->CH_Ctrl[13].addr[0] = 110; + state->CH_Ctrl[13].bit[0] = 2; + state->CH_Ctrl[13].val[0] = 0; + state->CH_Ctrl[13].addr[1] = 110; + state->CH_Ctrl[13].bit[1] = 3; + state->CH_Ctrl[13].val[1] = 0; + state->CH_Ctrl[13].addr[2] = 110; + state->CH_Ctrl[13].bit[2] = 4; + state->CH_Ctrl[13].val[2] = 0; + state->CH_Ctrl[13].addr[3] = 110; + state->CH_Ctrl[13].bit[3] = 5; + state->CH_Ctrl[13].val[3] = 0; + state->CH_Ctrl[13].addr[4] = 110; + state->CH_Ctrl[13].bit[4] = 6; + state->CH_Ctrl[13].val[4] = 0; + state->CH_Ctrl[13].addr[5] = 110; + state->CH_Ctrl[13].bit[5] = 7; + state->CH_Ctrl[13].val[5] = 1; + + state->CH_Ctrl[14].Ctrl_Num = CHCAL_INT_MOD_RF ; + state->CH_Ctrl[14].size = 7 ; + state->CH_Ctrl[14].addr[0] = 14; + state->CH_Ctrl[14].bit[0] = 0; + state->CH_Ctrl[14].val[0] = 0; + state->CH_Ctrl[14].addr[1] = 14; + state->CH_Ctrl[14].bit[1] = 1; + state->CH_Ctrl[14].val[1] = 0; + state->CH_Ctrl[14].addr[2] = 14; + state->CH_Ctrl[14].bit[2] = 2; + state->CH_Ctrl[14].val[2] = 0; + state->CH_Ctrl[14].addr[3] = 14; + state->CH_Ctrl[14].bit[3] = 3; + state->CH_Ctrl[14].val[3] = 0; + state->CH_Ctrl[14].addr[4] = 14; + state->CH_Ctrl[14].bit[4] = 4; + state->CH_Ctrl[14].val[4] = 0; + state->CH_Ctrl[14].addr[5] = 14; + state->CH_Ctrl[14].bit[5] = 5; + state->CH_Ctrl[14].val[5] = 0; + state->CH_Ctrl[14].addr[6] = 14; + state->CH_Ctrl[14].bit[6] = 6; + state->CH_Ctrl[14].val[6] = 0; + + state->CH_Ctrl[15].Ctrl_Num = CHCAL_FRAC_MOD_RF ; + state->CH_Ctrl[15].size = 18 ; + state->CH_Ctrl[15].addr[0] = 17; + state->CH_Ctrl[15].bit[0] = 6; + state->CH_Ctrl[15].val[0] = 0; + state->CH_Ctrl[15].addr[1] = 17; + state->CH_Ctrl[15].bit[1] = 7; + state->CH_Ctrl[15].val[1] = 0; + state->CH_Ctrl[15].addr[2] = 16; + state->CH_Ctrl[15].bit[2] = 0; + state->CH_Ctrl[15].val[2] = 0; + state->CH_Ctrl[15].addr[3] = 16; + state->CH_Ctrl[15].bit[3] = 1; + state->CH_Ctrl[15].val[3] = 0; + state->CH_Ctrl[15].addr[4] = 16; + state->CH_Ctrl[15].bit[4] = 2; + state->CH_Ctrl[15].val[4] = 0; + state->CH_Ctrl[15].addr[5] = 16; + state->CH_Ctrl[15].bit[5] = 3; + state->CH_Ctrl[15].val[5] = 0; + state->CH_Ctrl[15].addr[6] = 16; + state->CH_Ctrl[15].bit[6] = 4; + state->CH_Ctrl[15].val[6] = 0; + state->CH_Ctrl[15].addr[7] = 16; + state->CH_Ctrl[15].bit[7] = 5; + state->CH_Ctrl[15].val[7] = 0; + state->CH_Ctrl[15].addr[8] = 16; + state->CH_Ctrl[15].bit[8] = 6; + state->CH_Ctrl[15].val[8] = 0; + state->CH_Ctrl[15].addr[9] = 16; + state->CH_Ctrl[15].bit[9] = 7; + state->CH_Ctrl[15].val[9] = 0; + state->CH_Ctrl[15].addr[10] = 15; + state->CH_Ctrl[15].bit[10] = 0; + state->CH_Ctrl[15].val[10] = 0; + state->CH_Ctrl[15].addr[11] = 15; + state->CH_Ctrl[15].bit[11] = 1; + state->CH_Ctrl[15].val[11] = 0; + state->CH_Ctrl[15].addr[12] = 15; + state->CH_Ctrl[15].bit[12] = 2; + state->CH_Ctrl[15].val[12] = 0; + state->CH_Ctrl[15].addr[13] = 15; + state->CH_Ctrl[15].bit[13] = 3; + state->CH_Ctrl[15].val[13] = 0; + state->CH_Ctrl[15].addr[14] = 15; + state->CH_Ctrl[15].bit[14] = 4; + state->CH_Ctrl[15].val[14] = 0; + state->CH_Ctrl[15].addr[15] = 15; + state->CH_Ctrl[15].bit[15] = 5; + state->CH_Ctrl[15].val[15] = 0; + state->CH_Ctrl[15].addr[16] = 15; + state->CH_Ctrl[15].bit[16] = 6; + state->CH_Ctrl[15].val[16] = 1; + state->CH_Ctrl[15].addr[17] = 15; + state->CH_Ctrl[15].bit[17] = 7; + state->CH_Ctrl[15].val[17] = 1; + + state->CH_Ctrl[16].Ctrl_Num = RFSYN_LPF_R ; + state->CH_Ctrl[16].size = 5 ; + state->CH_Ctrl[16].addr[0] = 112; + state->CH_Ctrl[16].bit[0] = 0; + state->CH_Ctrl[16].val[0] = 0; + state->CH_Ctrl[16].addr[1] = 112; + state->CH_Ctrl[16].bit[1] = 1; + state->CH_Ctrl[16].val[1] = 0; + state->CH_Ctrl[16].addr[2] = 112; + state->CH_Ctrl[16].bit[2] = 2; + state->CH_Ctrl[16].val[2] = 0; + state->CH_Ctrl[16].addr[3] = 112; + state->CH_Ctrl[16].bit[3] = 3; + state->CH_Ctrl[16].val[3] = 0; + state->CH_Ctrl[16].addr[4] = 112; + state->CH_Ctrl[16].bit[4] = 4; + state->CH_Ctrl[16].val[4] = 1; + + state->CH_Ctrl[17].Ctrl_Num = CHCAL_EN_INT_RF ; + state->CH_Ctrl[17].size = 1 ; + state->CH_Ctrl[17].addr[0] = 14; + state->CH_Ctrl[17].bit[0] = 7; + state->CH_Ctrl[17].val[0] = 0; + + state->CH_Ctrl[18].Ctrl_Num = TG_LO_DIVVAL ; + state->CH_Ctrl[18].size = 4 ; + state->CH_Ctrl[18].addr[0] = 107; + state->CH_Ctrl[18].bit[0] = 3; + state->CH_Ctrl[18].val[0] = 0; + state->CH_Ctrl[18].addr[1] = 107; + state->CH_Ctrl[18].bit[1] = 4; + state->CH_Ctrl[18].val[1] = 0; + state->CH_Ctrl[18].addr[2] = 107; + state->CH_Ctrl[18].bit[2] = 5; + state->CH_Ctrl[18].val[2] = 0; + state->CH_Ctrl[18].addr[3] = 107; + state->CH_Ctrl[18].bit[3] = 6; + state->CH_Ctrl[18].val[3] = 0; + + state->CH_Ctrl[19].Ctrl_Num = TG_LO_SELVAL ; + state->CH_Ctrl[19].size = 3 ; + state->CH_Ctrl[19].addr[0] = 107; + state->CH_Ctrl[19].bit[0] = 7; + state->CH_Ctrl[19].val[0] = 1; + state->CH_Ctrl[19].addr[1] = 106; + state->CH_Ctrl[19].bit[1] = 0; + state->CH_Ctrl[19].val[1] = 1; + state->CH_Ctrl[19].addr[2] = 106; + state->CH_Ctrl[19].bit[2] = 1; + state->CH_Ctrl[19].val[2] = 1; + + state->CH_Ctrl[20].Ctrl_Num = TG_DIV_VAL ; + state->CH_Ctrl[20].size = 11 ; + state->CH_Ctrl[20].addr[0] = 109; + state->CH_Ctrl[20].bit[0] = 2; + state->CH_Ctrl[20].val[0] = 0; + state->CH_Ctrl[20].addr[1] = 109; + state->CH_Ctrl[20].bit[1] = 3; + state->CH_Ctrl[20].val[1] = 0; + state->CH_Ctrl[20].addr[2] = 109; + state->CH_Ctrl[20].bit[2] = 4; + state->CH_Ctrl[20].val[2] = 0; + state->CH_Ctrl[20].addr[3] = 109; + state->CH_Ctrl[20].bit[3] = 5; + state->CH_Ctrl[20].val[3] = 0; + state->CH_Ctrl[20].addr[4] = 109; + state->CH_Ctrl[20].bit[4] = 6; + state->CH_Ctrl[20].val[4] = 0; + state->CH_Ctrl[20].addr[5] = 109; + state->CH_Ctrl[20].bit[5] = 7; + state->CH_Ctrl[20].val[5] = 0; + state->CH_Ctrl[20].addr[6] = 108; + state->CH_Ctrl[20].bit[6] = 0; + state->CH_Ctrl[20].val[6] = 0; + state->CH_Ctrl[20].addr[7] = 108; + state->CH_Ctrl[20].bit[7] = 1; + state->CH_Ctrl[20].val[7] = 0; + state->CH_Ctrl[20].addr[8] = 108; + state->CH_Ctrl[20].bit[8] = 2; + state->CH_Ctrl[20].val[8] = 1; + state->CH_Ctrl[20].addr[9] = 108; + state->CH_Ctrl[20].bit[9] = 3; + state->CH_Ctrl[20].val[9] = 1; + state->CH_Ctrl[20].addr[10] = 108; + state->CH_Ctrl[20].bit[10] = 4; + state->CH_Ctrl[20].val[10] = 1; + + state->CH_Ctrl[21].Ctrl_Num = TG_VCO_BIAS ; + state->CH_Ctrl[21].size = 6 ; + state->CH_Ctrl[21].addr[0] = 106; + state->CH_Ctrl[21].bit[0] = 2; + state->CH_Ctrl[21].val[0] = 0; + state->CH_Ctrl[21].addr[1] = 106; + state->CH_Ctrl[21].bit[1] = 3; + state->CH_Ctrl[21].val[1] = 0; + state->CH_Ctrl[21].addr[2] = 106; + state->CH_Ctrl[21].bit[2] = 4; + state->CH_Ctrl[21].val[2] = 0; + state->CH_Ctrl[21].addr[3] = 106; + state->CH_Ctrl[21].bit[3] = 5; + state->CH_Ctrl[21].val[3] = 0; + state->CH_Ctrl[21].addr[4] = 106; + state->CH_Ctrl[21].bit[4] = 6; + state->CH_Ctrl[21].val[4] = 0; + state->CH_Ctrl[21].addr[5] = 106; + state->CH_Ctrl[21].bit[5] = 7; + state->CH_Ctrl[21].val[5] = 1; + + state->CH_Ctrl[22].Ctrl_Num = SEQ_EXTPOWERUP ; + state->CH_Ctrl[22].size = 1 ; + state->CH_Ctrl[22].addr[0] = 138; + state->CH_Ctrl[22].bit[0] = 4; + state->CH_Ctrl[22].val[0] = 1; + + state->CH_Ctrl[23].Ctrl_Num = OVERRIDE_2 ; + state->CH_Ctrl[23].size = 1 ; + state->CH_Ctrl[23].addr[0] = 17; + state->CH_Ctrl[23].bit[0] = 5; + state->CH_Ctrl[23].val[0] = 0; + + state->CH_Ctrl[24].Ctrl_Num = OVERRIDE_3 ; + state->CH_Ctrl[24].size = 1 ; + state->CH_Ctrl[24].addr[0] = 111; + state->CH_Ctrl[24].bit[0] = 3; + state->CH_Ctrl[24].val[0] = 0; + + state->CH_Ctrl[25].Ctrl_Num = OVERRIDE_4 ; + state->CH_Ctrl[25].size = 1 ; + state->CH_Ctrl[25].addr[0] = 112; + state->CH_Ctrl[25].bit[0] = 7; + state->CH_Ctrl[25].val[0] = 0; + + state->CH_Ctrl[26].Ctrl_Num = SEQ_FSM_PULSE ; + state->CH_Ctrl[26].size = 1 ; + state->CH_Ctrl[26].addr[0] = 136; + state->CH_Ctrl[26].bit[0] = 7; + state->CH_Ctrl[26].val[0] = 0; + + state->CH_Ctrl[27].Ctrl_Num = GPIO_4B ; + state->CH_Ctrl[27].size = 1 ; + state->CH_Ctrl[27].addr[0] = 149; + state->CH_Ctrl[27].bit[0] = 7; + state->CH_Ctrl[27].val[0] = 0; + + state->CH_Ctrl[28].Ctrl_Num = GPIO_3B ; + state->CH_Ctrl[28].size = 1 ; + state->CH_Ctrl[28].addr[0] = 149; + state->CH_Ctrl[28].bit[0] = 6; + state->CH_Ctrl[28].val[0] = 0; + + state->CH_Ctrl[29].Ctrl_Num = GPIO_4 ; + state->CH_Ctrl[29].size = 1 ; + state->CH_Ctrl[29].addr[0] = 149; + state->CH_Ctrl[29].bit[0] = 5; + state->CH_Ctrl[29].val[0] = 1; + + state->CH_Ctrl[30].Ctrl_Num = GPIO_3 ; + state->CH_Ctrl[30].size = 1 ; + state->CH_Ctrl[30].addr[0] = 149; + state->CH_Ctrl[30].bit[0] = 4; + state->CH_Ctrl[30].val[0] = 1; + + state->CH_Ctrl[31].Ctrl_Num = GPIO_1B ; + state->CH_Ctrl[31].size = 1 ; + state->CH_Ctrl[31].addr[0] = 149; + state->CH_Ctrl[31].bit[0] = 3; + state->CH_Ctrl[31].val[0] = 0; + + state->CH_Ctrl[32].Ctrl_Num = DAC_A_ENABLE ; + state->CH_Ctrl[32].size = 1 ; + state->CH_Ctrl[32].addr[0] = 93; + state->CH_Ctrl[32].bit[0] = 1; + state->CH_Ctrl[32].val[0] = 0; + + state->CH_Ctrl[33].Ctrl_Num = DAC_B_ENABLE ; + state->CH_Ctrl[33].size = 1 ; + state->CH_Ctrl[33].addr[0] = 93; + state->CH_Ctrl[33].bit[0] = 0; + state->CH_Ctrl[33].val[0] = 0; + + state->CH_Ctrl[34].Ctrl_Num = DAC_DIN_A ; + state->CH_Ctrl[34].size = 6 ; + state->CH_Ctrl[34].addr[0] = 92; + state->CH_Ctrl[34].bit[0] = 2; + state->CH_Ctrl[34].val[0] = 0; + state->CH_Ctrl[34].addr[1] = 92; + state->CH_Ctrl[34].bit[1] = 3; + state->CH_Ctrl[34].val[1] = 0; + state->CH_Ctrl[34].addr[2] = 92; + state->CH_Ctrl[34].bit[2] = 4; + state->CH_Ctrl[34].val[2] = 0; + state->CH_Ctrl[34].addr[3] = 92; + state->CH_Ctrl[34].bit[3] = 5; + state->CH_Ctrl[34].val[3] = 0; + state->CH_Ctrl[34].addr[4] = 92; + state->CH_Ctrl[34].bit[4] = 6; + state->CH_Ctrl[34].val[4] = 0; + state->CH_Ctrl[34].addr[5] = 92; + state->CH_Ctrl[34].bit[5] = 7; + state->CH_Ctrl[34].val[5] = 0; + + state->CH_Ctrl[35].Ctrl_Num = DAC_DIN_B ; + state->CH_Ctrl[35].size = 6 ; + state->CH_Ctrl[35].addr[0] = 93; + state->CH_Ctrl[35].bit[0] = 2; + state->CH_Ctrl[35].val[0] = 0; + state->CH_Ctrl[35].addr[1] = 93; + state->CH_Ctrl[35].bit[1] = 3; + state->CH_Ctrl[35].val[1] = 0; + state->CH_Ctrl[35].addr[2] = 93; + state->CH_Ctrl[35].bit[2] = 4; + state->CH_Ctrl[35].val[2] = 0; + state->CH_Ctrl[35].addr[3] = 93; + state->CH_Ctrl[35].bit[3] = 5; + state->CH_Ctrl[35].val[3] = 0; + state->CH_Ctrl[35].addr[4] = 93; + state->CH_Ctrl[35].bit[4] = 6; + state->CH_Ctrl[35].val[4] = 0; + state->CH_Ctrl[35].addr[5] = 93; + state->CH_Ctrl[35].bit[5] = 7; + state->CH_Ctrl[35].val[5] = 0; #ifdef _MXL_PRODUCTION - Tuner->CH_Ctrl[36].Ctrl_Num = RFSYN_EN_DIV ; - Tuner->CH_Ctrl[36].size = 1 ; - Tuner->CH_Ctrl[36].addr[0] = 109; - Tuner->CH_Ctrl[36].bit[0] = 1; - Tuner->CH_Ctrl[36].val[0] = 1; - - Tuner->CH_Ctrl[37].Ctrl_Num = RFSYN_DIVM ; - Tuner->CH_Ctrl[37].size = 2 ; - Tuner->CH_Ctrl[37].addr[0] = 112; - Tuner->CH_Ctrl[37].bit[0] = 5; - Tuner->CH_Ctrl[37].val[0] = 0; - Tuner->CH_Ctrl[37].addr[1] = 112; - Tuner->CH_Ctrl[37].bit[1] = 6; - Tuner->CH_Ctrl[37].val[1] = 0; - - Tuner->CH_Ctrl[38].Ctrl_Num = DN_BYPASS_AGC_I2C ; - Tuner->CH_Ctrl[38].size = 1 ; - Tuner->CH_Ctrl[38].addr[0] = 65; - Tuner->CH_Ctrl[38].bit[0] = 1; - Tuner->CH_Ctrl[38].val[0] = 0; + state->CH_Ctrl[36].Ctrl_Num = RFSYN_EN_DIV ; + state->CH_Ctrl[36].size = 1 ; + state->CH_Ctrl[36].addr[0] = 109; + state->CH_Ctrl[36].bit[0] = 1; + state->CH_Ctrl[36].val[0] = 1; + + state->CH_Ctrl[37].Ctrl_Num = RFSYN_DIVM ; + state->CH_Ctrl[37].size = 2 ; + state->CH_Ctrl[37].addr[0] = 112; + state->CH_Ctrl[37].bit[0] = 5; + state->CH_Ctrl[37].val[0] = 0; + state->CH_Ctrl[37].addr[1] = 112; + state->CH_Ctrl[37].bit[1] = 6; + state->CH_Ctrl[37].val[1] = 0; + + state->CH_Ctrl[38].Ctrl_Num = DN_BYPASS_AGC_I2C ; + state->CH_Ctrl[38].size = 1 ; + state->CH_Ctrl[38].addr[0] = 65; + state->CH_Ctrl[38].bit[0] = 1; + state->CH_Ctrl[38].val[0] = 0; #endif return 0 ; @@ -1832,13 +1840,14 @@ u16 MXL5005_ControlInit(Tuner_struct *Tuner) // MaxLinear source code - MXL5005_c.cpp // MXL5005.cpp : Defines the initialization routines for the DLL. // 2.6.12 - -void InitTunerControls(Tuner_struct *Tuner) +// DONE +void InitTunerControls(struct dvb_frontend *fe) { - MXL5005_RegisterInit(Tuner) ; - MXL5005_ControlInit(Tuner) ; + struct mxl5005s_state *state = fe->demodulator_priv; + MXL5005_RegisterInit(fe); + MXL5005_ControlInit(fe); #ifdef _MXL_INTERNAL - MXL5005_MXLControlInit(Tuner) ; + MXL5005_MXLControlInit(fe); #endif } @@ -1857,15 +1866,15 @@ void InitTunerControls(Tuner_struct *Tuner) // Tuner_struct: structure defined at higher level // // Mode: Tuner Mode (Analog/Digital) // // IF_Mode: IF Mode ( Zero/Low ) // -// Bandwidth: Filter Channel Bandwidth (in Hz) // +// Bandwidth: Filter Channel Bandwidth (in Hz) // // IF_out: Desired IF out Frequency (in Hz) // // Fxtal: Crystal Frerquency (in Hz) // -// TOP: 0: Dual AGC; Value: take over point // -// IF_OUT_LOAD: IF out load resistor (200/300 Ohms) // -// CLOCK_OUT: 0: Turn off clock out; 1: turn on clock out // -// DIV_OUT: 0: Div-1; 1: Div-4 // -// CAPSELECT: 0: Disable On-chip pulling cap; 1: Enable // -// EN_RSSI: 0: Disable RSSI; 1: Enable RSSI // +// TOP: 0: Dual AGC; Value: take over point // +// IF_OUT_LOAD: IF out load resistor (200/300 Ohms) // +// CLOCK_OUT: 0: Turn off clock out; 1: turn on clock out // +// DIV_OUT: 0: Div-1; 1: Div-4 // +// CAPSELECT: 0: Disable On-chip pulling cap; 1: Enable // +// EN_RSSI: 0: Disable RSSI; 1: Enable RSSI // // // // Outputs: // // Tuner // @@ -1875,49 +1884,51 @@ void InitTunerControls(Tuner_struct *Tuner) // > 0 : Failed // // // /////////////////////////////////////////////////////////////////////////////// -u16 MXL5005_TunerConfig(Tuner_struct *Tuner, - u8 Mode, // 0: Analog Mode ; 1: Digital Mode - u8 IF_mode, // for Analog Mode, 0: zero IF; 1: low IF - u32 Bandwidth, // filter channel bandwidth (6, 7, 8) - u32 IF_out, // Desired IF Out Frequency - u32 Fxtal, // XTAL Frequency - u8 AGC_Mode, // AGC Mode - Dual AGC: 0, Single AGC: 1 - u16 TOP, // 0: Dual AGC; Value: take over point - u16 IF_OUT_LOAD, // IF Out Load Resistor (200 / 300 Ohms) - u8 CLOCK_OUT, // 0: turn off clock out; 1: turn on clock out - u8 DIV_OUT, // 0: Div-1; 1: Div-4 - u8 CAPSELECT, // 0: disable On-Chip pulling cap; 1: enable - u8 EN_RSSI, // 0: disable RSSI; 1: enable RSSI - u8 Mod_Type, // Modulation Type; - // 0 - Default; 1 - DVB-T; 2 - ATSC; 3 - QAM; 4 - Analog Cable - u8 TF_Type // Tracking Filter - // 0 - Default; 1 - Off; 2 - Type C; 3 - Type C-H +// DONE +u16 MXL5005_TunerConfig(struct dvb_frontend *fe, + u8 Mode, /* 0: Analog Mode ; 1: Digital Mode */ + u8 IF_mode, /* for Analog Mode, 0: zero IF; 1: low IF */ + u32 Bandwidth, /* filter channel bandwidth (6, 7, 8) */ + u32 IF_out, /* Desired IF Out Frequency */ + u32 Fxtal, /* XTAL Frequency */ + u8 AGC_Mode, /* AGC Mode - Dual AGC: 0, Single AGC: 1 */ + u16 TOP, /* 0: Dual AGC; Value: take over point */ + u16 IF_OUT_LOAD, /* IF Out Load Resistor (200 / 300 Ohms) */ + u8 CLOCK_OUT, /* 0: turn off clock out; 1: turn on clock out */ + u8 DIV_OUT, /* 0: Div-1; 1: Div-4 */ + u8 CAPSELECT, /* 0: disable On-Chip pulling cap; 1: enable */ + u8 EN_RSSI, /* 0: disable RSSI; 1: enable RSSI */ + u8 Mod_Type, /* Modulation Type; */ + /* 0 - Default; 1 - DVB-T; 2 - ATSC; 3 - QAM; 4 - Analog Cable */ + u8 TF_Type /* Tracking Filter */ + /* 0 - Default; 1 - Off; 2 - Type C; 3 - Type C-H */ ) { - u16 status = 0 ; + struct mxl5005s_state *state = fe->demodulator_priv; + u16 status = 0; - Tuner->Mode = Mode ; - Tuner->IF_Mode = IF_mode ; - Tuner->Chan_Bandwidth = Bandwidth ; - Tuner->IF_OUT = IF_out ; - Tuner->Fxtal = Fxtal ; - Tuner->AGC_Mode = AGC_Mode ; - Tuner->TOP = TOP ; - Tuner->IF_OUT_LOAD = IF_OUT_LOAD ; - Tuner->CLOCK_OUT = CLOCK_OUT ; - Tuner->DIV_OUT = DIV_OUT ; - Tuner->CAPSELECT = CAPSELECT ; - Tuner->EN_RSSI = EN_RSSI ; - Tuner->Mod_Type = Mod_Type ; - Tuner->TF_Type = TF_Type ; + state->Mode = Mode; + state->IF_Mode = IF_mode; + state->Chan_Bandwidth = Bandwidth; + state->IF_OUT = IF_out; + state->Fxtal = Fxtal; + state->AGC_Mode = AGC_Mode; + state->TOP = TOP; + state->IF_OUT_LOAD = IF_OUT_LOAD; + state->CLOCK_OUT = CLOCK_OUT; + state->DIV_OUT = DIV_OUT; + state->CAPSELECT = CAPSELECT; + state->EN_RSSI = EN_RSSI; + state->Mod_Type = Mod_Type; + state->TF_Type = TF_Type; /* Initialize all the controls and registers */ - InitTunerControls (Tuner) ; + InitTunerControls(fe); /* Synthesizer LO frequency calculation */ - MXL_SynthIFLO_Calc( Tuner ) ; + MXL_SynthIFLO_Calc(fe); - return status ; + return status; } /////////////////////////////////////////////////////////////////////////////// @@ -1943,22 +1954,18 @@ u16 MXL5005_TunerConfig(Tuner_struct *Tuner, // > 0 : Failed // // // /////////////////////////////////////////////////////////////////////////////// -void MXL_SynthIFLO_Calc(Tuner_struct *Tuner) +// DONE +void MXL_SynthIFLO_Calc(struct dvb_frontend *fe) { - if (Tuner->Mode == 1) // Digital Mode + struct mxl5005s_state *state = fe->demodulator_priv; + if (Tuner->Mode == 1) /* Digital Mode */ + state->IF_LO = state->IF_OUT; + else /* Analog Mode */ { - Tuner->IF_LO = Tuner->IF_OUT ; - } - else // Analog Mode - { - if(Tuner->IF_Mode == 0) // Analog Zero IF mode - { - Tuner->IF_LO = Tuner->IF_OUT + 400000 ; - } - else // Analog Low IF mode - { - Tuner->IF_LO = Tuner->IF_OUT + Tuner->Chan_Bandwidth/2 ; - } + if(state->IF_Mode == 0) /* Analog Zero IF mode */ + state->IF_LO = state->IF_OUT + 400000; + else /* Analog Low IF mode */ + state->IF_LO = state->IF_OUT + state->Chan_Bandwidth/2; } } @@ -1986,25 +1993,22 @@ void MXL_SynthIFLO_Calc(Tuner_struct *Tuner) // > 0 : Failed // // // /////////////////////////////////////////////////////////////////////////////// -void MXL_SynthRFTGLO_Calc(Tuner_struct *Tuner) +// DONE +void MXL_SynthRFTGLO_Calc(struct dvb_frontend *fe) { - if (Tuner->Mode == 1) // Digital Mode - { + struct mxl5005s_state *state = fe->demodulator_priv; + + if (state->Mode == 1) /* Digital Mode */ { //remove 20.48MHz setting for 2.6.10 - Tuner->RF_LO = Tuner->RF_IN ; - Tuner->TG_LO = Tuner->RF_IN - 750000 ; //change for 2.6.6 - } - else // Analog Mode - { - if(Tuner->IF_Mode == 0) // Analog Zero IF mode - { - Tuner->RF_LO = Tuner->RF_IN - 400000 ; - Tuner->TG_LO = Tuner->RF_IN - 1750000 ; - } - else // Analog Low IF mode - { - Tuner->RF_LO = Tuner->RF_IN - Tuner->Chan_Bandwidth/2 ; - Tuner->TG_LO = Tuner->RF_IN - Tuner->Chan_Bandwidth + 500000 ; + state->RF_LO = state->RF_IN; + state->TG_LO = state->RF_IN - 750000; //change for 2.6.6 + } else /* Analog Mode */ { + if(state->IF_Mode == 0) /* Analog Zero IF mode */ { + state->RF_LO = state->RF_IN - 400000; + state->TG_LO = state->RF_IN - 1750000; + } else /* Analog Low IF mode */ { + state->RF_LO = state->RF_IN - state->Chan_Bandwidth/2; + state->TG_LO = state->RF_IN - state->Chan_Bandwidth + 500000; } } } @@ -2028,16 +2032,18 @@ void MXL_SynthRFTGLO_Calc(Tuner_struct *Tuner) // > 0 : Failed // // // /////////////////////////////////////////////////////////////////////////////// -u16 MXL_OverwriteICDefault( Tuner_struct *Tuner) +// DONE +u16 MXL_OverwriteICDefault(struct dvb_frontend *fe) { - u16 status = 0 ; + struct mxl5005s_state *state = fe->demodulator_priv; + u16 status = 0; - status += MXL_ControlWrite(Tuner, OVERRIDE_1, 1) ; - status += MXL_ControlWrite(Tuner, OVERRIDE_2, 1) ; - status += MXL_ControlWrite(Tuner, OVERRIDE_3, 1) ; - status += MXL_ControlWrite(Tuner, OVERRIDE_4, 1) ; + status += MXL_ControlWrite(fe, OVERRIDE_1, 1); + status += MXL_ControlWrite(fe, OVERRIDE_2, 1); + status += MXL_ControlWrite(fe, OVERRIDE_3, 1); + status += MXL_ControlWrite(fe, OVERRIDE_4, 1); - return status ; + return status; } /////////////////////////////////////////////////////////////////////////////// @@ -2065,363 +2071,338 @@ u16 MXL_OverwriteICDefault( Tuner_struct *Tuner) // > 0 : Failed // // // /////////////////////////////////////////////////////////////////////////////// -u16 MXL_BlockInit( Tuner_struct *Tuner ) +// DONE +u16 MXL_BlockInit(struct dvb_frontend *fe) { - u16 status = 0 ; + struct mxl5005s_state *state = fe->demodulator_priv; + u16 status = 0; - status += MXL_OverwriteICDefault(Tuner) ; + status += MXL_OverwriteICDefault(fe); - // - // Downconverter Control - // Dig Ana - status += MXL_ControlWrite(Tuner, DN_IQTN_AMP_CUT, Tuner->Mode ? 1 : 0) ; + /* Downconverter Control Dig Ana */ + status += MXL_ControlWrite(fe, DN_IQTN_AMP_CUT, state->Mode ? 1 : 0); - // - // Filter Control - // Dig Ana - status += MXL_ControlWrite(Tuner, BB_MODE, Tuner->Mode ? 0 : 1) ; - status += MXL_ControlWrite(Tuner, BB_BUF, Tuner->Mode ? 3 : 2) ; - status += MXL_ControlWrite(Tuner, BB_BUF_OA, Tuner->Mode ? 1 : 0) ; - - status += MXL_ControlWrite(Tuner, BB_IQSWAP, Tuner->Mode ? 0 : 1) ; - status += MXL_ControlWrite(Tuner, BB_INITSTATE_DLPF_TUNE, 0) ; - - // Initialize Low-Pass Filter - if (Tuner->Mode) { // Digital Mode - switch (Tuner->Chan_Bandwidth) { + /* Filter Control Dig Ana */ + status += MXL_ControlWrite(fe, BB_MODE, state->Mode ? 0 : 1); + status += MXL_ControlWrite(fe, BB_BUF, state->Mode ? 3 : 2); + status += MXL_ControlWrite(fe, BB_BUF_OA, state->Mode ? 1 : 0); + status += MXL_ControlWrite(fe, BB_IQSWAP, state->Mode ? 0 : 1); + status += MXL_ControlWrite(fe, BB_INITSTATE_DLPF_TUNE, 0); + + /* Initialize Low-Pass Filter */ + if (state->Mode) { /* Digital Mode */ + switch (state->Chan_Bandwidth) { case 8000000: - status += MXL_ControlWrite(Tuner, BB_DLPF_BANDSEL, 0) ; - break ; + status += MXL_ControlWrite(fe, BB_DLPF_BANDSEL, 0); + break; case 7000000: - status += MXL_ControlWrite(Tuner, BB_DLPF_BANDSEL, 2) ; - break ; + status += MXL_ControlWrite(fe, BB_DLPF_BANDSEL, 2); + break; case 6000000: - status += MXL_ControlWrite(Tuner, BB_DLPF_BANDSEL, 3) ; - break ; - } - } else { // Analog Mode - switch (Tuner->Chan_Bandwidth) { - case 8000000: // Low Zero - status += MXL_ControlWrite(Tuner, BB_ALPF_BANDSELECT, (Tuner->IF_Mode ? 0 : 3)) ; - break ; + status += MXL_ControlWrite(fe, BB_DLPF_BANDSEL, 3); + break; + } + } else { /* Analog Mode */ + switch (state->Chan_Bandwidth) { + case 8000000: /* Low Zero */ + status += MXL_ControlWrite(fe, BB_ALPF_BANDSELECT, (state->IF_Mode ? 0 : 3)); + break; case 7000000: - status += MXL_ControlWrite(Tuner, BB_ALPF_BANDSELECT, (Tuner->IF_Mode ? 1 : 4)) ; - break ; + status += MXL_ControlWrite(fe, BB_ALPF_BANDSELECT, (state->IF_Mode ? 1 : 4)); + break; case 6000000: - status += MXL_ControlWrite(Tuner, BB_ALPF_BANDSELECT, (Tuner->IF_Mode ? 2 : 5)) ; - break ; + status += MXL_ControlWrite(fe, BB_ALPF_BANDSELECT, (state->IF_Mode ? 2 : 5)); + break; } } - // - // Charge Pump Control - // Dig Ana - status += MXL_ControlWrite(Tuner, RFSYN_CHP_GAIN, Tuner->Mode ? 5 : 8) ; - status += MXL_ControlWrite(Tuner, RFSYN_EN_CHP_HIGAIN, Tuner->Mode ? 1 : 1) ; - status += MXL_ControlWrite(Tuner, EN_CHP_LIN_B, Tuner->Mode ? 0 : 0) ; + /* Charge Pump Control Dig Ana */ + status += MXL_ControlWrite(fe, RFSYN_CHP_GAIN, state->Mode ? 5 : 8); + status += MXL_ControlWrite(fe, RFSYN_EN_CHP_HIGAIN, state->Mode ? 1 : 1); + status += MXL_ControlWrite(fe, EN_CHP_LIN_B, state->Mode ? 0 : 0); - // - // AGC TOP Control - // - if (Tuner->AGC_Mode == 0) // Dual AGC - { - status += MXL_ControlWrite(Tuner, AGC_IF, 15) ; - status += MXL_ControlWrite(Tuner, AGC_RF, 15) ; + /* AGC TOP Control */ + if (state->AGC_Mode == 0) /* Dual AGC */ { + status += MXL_ControlWrite(fe, AGC_IF, 15); + status += MXL_ControlWrite(fe, AGC_RF, 15); } - else // Single AGC Mode Dig Ana - status += MXL_ControlWrite(Tuner, AGC_RF, Tuner->Mode? 15 : 12) ; + else /* Single AGC Mode Dig Ana */ + status += MXL_ControlWrite(fe, AGC_RF, state->Mode ? 15 : 12); - if (Tuner->TOP == 55) // TOP == 5.5 - status += MXL_ControlWrite(Tuner, AGC_IF, 0x0) ; + if (state->TOP == 55) /* TOP == 5.5 */ + status += MXL_ControlWrite(fe, AGC_IF, 0x0); - if (Tuner->TOP == 72) // TOP == 7.2 - status += MXL_ControlWrite(Tuner, AGC_IF, 0x1) ; + if (state->TOP == 72) /* TOP == 7.2 */ + status += MXL_ControlWrite(fe, AGC_IF, 0x1); - if (Tuner->TOP == 92) // TOP == 9.2 - status += MXL_ControlWrite(Tuner, AGC_IF, 0x2) ; + if (state->TOP == 92) /* TOP == 9.2 */ + status += MXL_ControlWrite(fe, AGC_IF, 0x2); - if (Tuner->TOP == 110) // TOP == 11.0 - status += MXL_ControlWrite(Tuner, AGC_IF, 0x3) ; + if (state->TOP == 110) /* TOP == 11.0 */ + status += MXL_ControlWrite(fe, AGC_IF, 0x3); - if (Tuner->TOP == 129) // TOP == 12.9 - status += MXL_ControlWrite(Tuner, AGC_IF, 0x4) ; + if (state->TOP == 129) /* TOP == 12.9 */ + status += MXL_ControlWrite(fe, AGC_IF, 0x4); - if (Tuner->TOP == 147) // TOP == 14.7 - status += MXL_ControlWrite(Tuner, AGC_IF, 0x5) ; + if (state->TOP == 147) /* TOP == 14.7 */ + status += MXL_ControlWrite(fe, AGC_IF, 0x5); - if (Tuner->TOP == 168) // TOP == 16.8 - status += MXL_ControlWrite(Tuner, AGC_IF, 0x6) ; + if (state->TOP == 168) /* TOP == 16.8 */ + status += MXL_ControlWrite(fe, AGC_IF, 0x6); - if (Tuner->TOP == 194) // TOP == 19.4 - status += MXL_ControlWrite(Tuner, AGC_IF, 0x7) ; + if (state->TOP == 194) /* TOP == 19.4 */ + status += MXL_ControlWrite(fe, AGC_IF, 0x7); - if (Tuner->TOP == 212) // TOP == 21.2 - status += MXL_ControlWrite(Tuner, AGC_IF, 0x9) ; + if (state->TOP == 212) /* TOP == 21.2 */ + status += MXL_ControlWrite(fe, AGC_IF, 0x9); - if (Tuner->TOP == 232) // TOP == 23.2 - status += MXL_ControlWrite(Tuner, AGC_IF, 0xA) ; + if (state->TOP == 232) /* TOP == 23.2 */ + status += MXL_ControlWrite(fe, AGC_IF, 0xA); - if (Tuner->TOP == 252) // TOP == 25.2 - status += MXL_ControlWrite(Tuner, AGC_IF, 0xB) ; + if (state->TOP == 252) /* TOP == 25.2 */ + status += MXL_ControlWrite(fe, AGC_IF, 0xB); - if (Tuner->TOP == 271) // TOP == 27.1 - status += MXL_ControlWrite(Tuner, AGC_IF, 0xC) ; + if (state->TOP == 271) /* TOP == 27.1 */ + status += MXL_ControlWrite(fe, AGC_IF, 0xC); - if (Tuner->TOP == 292) // TOP == 29.2 - status += MXL_ControlWrite(Tuner, AGC_IF, 0xD) ; + if (state->TOP == 292) /* TOP == 29.2 */ + status += MXL_ControlWrite(fe, AGC_IF, 0xD); - if (Tuner->TOP == 317) // TOP == 31.7 - status += MXL_ControlWrite(Tuner, AGC_IF, 0xE) ; + if (state->TOP == 317) /* TOP == 31.7 */ + status += MXL_ControlWrite(fe, AGC_IF, 0xE); - if (Tuner->TOP == 349) // TOP == 34.9 - status += MXL_ControlWrite(Tuner, AGC_IF, 0xF) ; + if (state->TOP == 349) /* TOP == 34.9 */ + status += MXL_ControlWrite(fe, AGC_IF, 0xF); - // - // IF Synthesizer Control - // - status += MXL_IFSynthInit( Tuner ) ; + /* IF Synthesizer Control */ + status += MXL_IFSynthInit(fe); - // - // IF UpConverter Control - if (Tuner->IF_OUT_LOAD == 200) - { - status += MXL_ControlWrite(Tuner, DRV_RES_SEL, 6) ; - status += MXL_ControlWrite(Tuner, I_DRIVER, 2) ; + /* IF UpConverter Control */ + if (state->IF_OUT_LOAD == 200) { + status += MXL_ControlWrite(fe, DRV_RES_SEL, 6); + status += MXL_ControlWrite(fe, I_DRIVER, 2); } - if (Tuner->IF_OUT_LOAD == 300) - { - status += MXL_ControlWrite(Tuner, DRV_RES_SEL, 4) ; - status += MXL_ControlWrite(Tuner, I_DRIVER, 1) ; + if (state->IF_OUT_LOAD == 300) { + status += MXL_ControlWrite(fe, DRV_RES_SEL, 4); + status += MXL_ControlWrite(fe, I_DRIVER, 1); } - // - // Anti-Alias Filtering Control - // - // initialise Anti-Aliasing Filter - if (Tuner->Mode) {// Digital Mode - if (Tuner->IF_OUT >= 4000000UL && Tuner->IF_OUT <= 6280000UL) { - status += MXL_ControlWrite(Tuner, EN_AAF, 1) ; - status += MXL_ControlWrite(Tuner, EN_3P, 1) ; - status += MXL_ControlWrite(Tuner, EN_AUX_3P, 1) ; - status += MXL_ControlWrite(Tuner, SEL_AAF_BAND, 0) ; - } - if ((Tuner->IF_OUT == 36125000UL) || (Tuner->IF_OUT == 36150000UL)) { - status += MXL_ControlWrite(Tuner, EN_AAF, 1) ; - status += MXL_ControlWrite(Tuner, EN_3P, 1) ; - status += MXL_ControlWrite(Tuner, EN_AUX_3P, 1) ; - status += MXL_ControlWrite(Tuner, SEL_AAF_BAND, 1) ; - } - if (Tuner->IF_OUT > 36150000UL) { - status += MXL_ControlWrite(Tuner, EN_AAF, 0) ; - status += MXL_ControlWrite(Tuner, EN_3P, 1) ; - status += MXL_ControlWrite(Tuner, EN_AUX_3P, 1) ; - status += MXL_ControlWrite(Tuner, SEL_AAF_BAND, 1) ; - } - } else { // Analog Mode - if (Tuner->IF_OUT >= 4000000UL && Tuner->IF_OUT <= 5000000UL) + /* Anti-Alias Filtering Control + * initialise Anti-Aliasing Filter + */ + if (state->Mode) { /* Digital Mode */ + if (state->IF_OUT >= 4000000UL && state->IF_OUT <= 6280000UL) { + status += MXL_ControlWrite(fe, EN_AAF, 1); + status += MXL_ControlWrite(fe, EN_3P, 1); + status += MXL_ControlWrite(fe, EN_AUX_3P, 1); + status += MXL_ControlWrite(fe, SEL_AAF_BAND, 0); + } + if ((state->IF_OUT == 36125000UL) || (state->IF_OUT == 36150000UL)) { + status += MXL_ControlWrite(fe, EN_AAF, 1); + status += MXL_ControlWrite(fe, EN_3P, 1); + status += MXL_ControlWrite(fe, EN_AUX_3P, 1); + status += MXL_ControlWrite(fe, SEL_AAF_BAND, 1); + } + if (state->IF_OUT > 36150000UL) { + status += MXL_ControlWrite(fe, EN_AAF, 0); + status += MXL_ControlWrite(fe, EN_3P, 1); + status += MXL_ControlWrite(fe, EN_AUX_3P, 1); + status += MXL_ControlWrite(fe, SEL_AAF_BAND, 1); + } + } else { /* Analog Mode */ + if (state->IF_OUT >= 4000000UL && state->IF_OUT <= 5000000UL) { - status += MXL_ControlWrite(Tuner, EN_AAF, 1) ; - status += MXL_ControlWrite(Tuner, EN_3P, 1) ; - status += MXL_ControlWrite(Tuner, EN_AUX_3P, 1) ; - status += MXL_ControlWrite(Tuner, SEL_AAF_BAND, 0) ; + status += MXL_ControlWrite(fe, EN_AAF, 1); + status += MXL_ControlWrite(fe, EN_3P, 1); + status += MXL_ControlWrite(fe, EN_AUX_3P, 1); + status += MXL_ControlWrite(fe, SEL_AAF_BAND, 0); } - if (Tuner->IF_OUT > 5000000UL) + if (state->IF_OUT > 5000000UL) { - status += MXL_ControlWrite(Tuner, EN_AAF, 0) ; - status += MXL_ControlWrite(Tuner, EN_3P, 0) ; - status += MXL_ControlWrite(Tuner, EN_AUX_3P, 0) ; - status += MXL_ControlWrite(Tuner, SEL_AAF_BAND, 0) ; + status += MXL_ControlWrite(fe, EN_AAF, 0); + status += MXL_ControlWrite(fe, EN_3P, 0); + status += MXL_ControlWrite(fe, EN_AUX_3P, 0); + status += MXL_ControlWrite(fe, SEL_AAF_BAND, 0); } } - // - // Demod Clock Out - // - if (Tuner->CLOCK_OUT) - status += MXL_ControlWrite(Tuner, SEQ_ENCLK16_CLK_OUT, 1) ; + /* Demod Clock Out */ + if (state->CLOCK_OUT) + status += MXL_ControlWrite(fe, SEQ_ENCLK16_CLK_OUT, 1); else - status += MXL_ControlWrite(Tuner, SEQ_ENCLK16_CLK_OUT, 0) ; + status += MXL_ControlWrite(fe, SEQ_ENCLK16_CLK_OUT, 0); - if (Tuner->DIV_OUT == 1) - status += MXL_ControlWrite(Tuner, SEQ_SEL4_16B, 1) ; - if (Tuner->DIV_OUT == 0) - status += MXL_ControlWrite(Tuner, SEQ_SEL4_16B, 0) ; + if (state->DIV_OUT == 1) + status += MXL_ControlWrite(fe, SEQ_SEL4_16B, 1); + if (state->DIV_OUT == 0) + status += MXL_ControlWrite(fe, SEQ_SEL4_16B, 0); - // - // Crystal Control - // - if (Tuner->CAPSELECT) - status += MXL_ControlWrite(Tuner, XTAL_CAPSELECT, 1) ; + /* Crystal Control */ + if (state->CAPSELECT) + status += MXL_ControlWrite(fe, XTAL_CAPSELECT, 1); else - status += MXL_ControlWrite(Tuner, XTAL_CAPSELECT, 0) ; + status += MXL_ControlWrite(fe, XTAL_CAPSELECT, 0); - if (Tuner->Fxtal >= 12000000UL && Tuner->Fxtal <= 16000000UL) - status += MXL_ControlWrite(Tuner, IF_SEL_DBL, 1) ; - if (Tuner->Fxtal > 16000000UL && Tuner->Fxtal <= 32000000UL) - status += MXL_ControlWrite(Tuner, IF_SEL_DBL, 0) ; + if (state->Fxtal >= 12000000UL && state->Fxtal <= 16000000UL) + status += MXL_ControlWrite(fe, IF_SEL_DBL, 1); + if (state->Fxtal > 16000000UL && state->Fxtal <= 32000000UL) + status += MXL_ControlWrite(fe, IF_SEL_DBL, 0); - if (Tuner->Fxtal >= 12000000UL && Tuner->Fxtal <= 22000000UL) - status += MXL_ControlWrite(Tuner, RFSYN_R_DIV, 3) ; - if (Tuner->Fxtal > 22000000UL && Tuner->Fxtal <= 32000000UL) - status += MXL_ControlWrite(Tuner, RFSYN_R_DIV, 0) ; + if (state->Fxtal >= 12000000UL && state->Fxtal <= 22000000UL) + status += MXL_ControlWrite(fe, RFSYN_R_DIV, 3); + if (state->Fxtal > 22000000UL && state->Fxtal <= 32000000UL) + status += MXL_ControlWrite(fe, RFSYN_R_DIV, 0); - // - // Misc Controls - // - if (Tuner->Mode == 0 && Tuner->IF_Mode == 1) // Analog LowIF mode - status += MXL_ControlWrite(Tuner, SEQ_EXTIQFSMPULSE, 0); + /* Misc Controls */ + if (state->Mode == 0 && Tuner->IF_Mode == 1) /* Analog LowIF mode */ + status += MXL_ControlWrite(fe, SEQ_EXTIQFSMPULSE, 0); else - status += MXL_ControlWrite(Tuner, SEQ_EXTIQFSMPULSE, 1); + status += MXL_ControlWrite(fe, SEQ_EXTIQFSMPULSE, 1); -// status += MXL_ControlRead(Tuner, IF_DIVVAL, &IF_DIVVAL_Val) ; + /* status += MXL_ControlRead(fe, IF_DIVVAL, &IF_DIVVAL_Val); */ - // Set TG_R_DIV - status += MXL_ControlWrite(Tuner, TG_R_DIV, MXL_Ceiling(Tuner->Fxtal, 1000000)) ; + /* Set TG_R_DIV */ + status += MXL_ControlWrite(fe, TG_R_DIV, MXL_Ceiling(state->Fxtal, 1000000)); - // - // Apply Default value to BB_INITSTATE_DLPF_TUNE - // + /* Apply Default value to BB_INITSTATE_DLPF_TUNE */ - // - // RSSI Control - // - if(Tuner->EN_RSSI) + /* RSSI Control */ + if (state->EN_RSSI) { - status += MXL_ControlWrite(Tuner, SEQ_EXTSYNTHCALIF, 1) ; - status += MXL_ControlWrite(Tuner, SEQ_EXTDCCAL, 1) ; - status += MXL_ControlWrite(Tuner, AGC_EN_RSSI, 1) ; - status += MXL_ControlWrite(Tuner, RFA_ENCLKRFAGC, 1) ; - // RSSI reference point - status += MXL_ControlWrite(Tuner, RFA_RSSI_REF, 2) ; - status += MXL_ControlWrite(Tuner, RFA_RSSI_REFH, 3) ; - status += MXL_ControlWrite(Tuner, RFA_RSSI_REFL, 1) ; - // TOP point - status += MXL_ControlWrite(Tuner, RFA_FLR, 0) ; - status += MXL_ControlWrite(Tuner, RFA_CEIL, 12) ; + status += MXL_ControlWrite(fe, SEQ_EXTSYNTHCALIF, 1); + status += MXL_ControlWrite(fe, SEQ_EXTDCCAL, 1); + status += MXL_ControlWrite(fe, AGC_EN_RSSI, 1); + status += MXL_ControlWrite(fe, RFA_ENCLKRFAGC, 1); + + /* RSSI reference point */ + status += MXL_ControlWrite(fe, RFA_RSSI_REF, 2); + status += MXL_ControlWrite(fe, RFA_RSSI_REFH, 3); + status += MXL_ControlWrite(fe, RFA_RSSI_REFL, 1); + + /* TOP point */ + status += MXL_ControlWrite(fe, RFA_FLR, 0); + status += MXL_ControlWrite(fe, RFA_CEIL, 12); } - // - // Modulation type bit settings - // Override the control values preset - // - if (Tuner->Mod_Type == MXL_DVBT) // DVB-T Mode + /* Modulation type bit settings + * Override the control values preset + */ + if (state->Mod_Type == MXL_DVBT) /* DVB-T Mode */ { - Tuner->AGC_Mode = 1 ; // Single AGC Mode - - // Enable RSSI - status += MXL_ControlWrite(Tuner, SEQ_EXTSYNTHCALIF, 1) ; - status += MXL_ControlWrite(Tuner, SEQ_EXTDCCAL, 1) ; - status += MXL_ControlWrite(Tuner, AGC_EN_RSSI, 1) ; - status += MXL_ControlWrite(Tuner, RFA_ENCLKRFAGC, 1) ; - // RSSI reference point - status += MXL_ControlWrite(Tuner, RFA_RSSI_REF, 3) ; - status += MXL_ControlWrite(Tuner, RFA_RSSI_REFH, 5) ; - status += MXL_ControlWrite(Tuner, RFA_RSSI_REFL, 1) ; - // TOP point - status += MXL_ControlWrite(Tuner, RFA_FLR, 2) ; - status += MXL_ControlWrite(Tuner, RFA_CEIL, 13) ; - if (Tuner->IF_OUT <= 6280000UL) // Low IF - status += MXL_ControlWrite(Tuner, BB_IQSWAP, 0) ; - else // High IF - status += MXL_ControlWrite(Tuner, BB_IQSWAP, 1) ; + state->AGC_Mode = 1; /* Single AGC Mode */ + + /* Enable RSSI */ + status += MXL_ControlWrite(fe, SEQ_EXTSYNTHCALIF, 1); + status += MXL_ControlWrite(fe, SEQ_EXTDCCAL, 1); + status += MXL_ControlWrite(fe, AGC_EN_RSSI, 1); + status += MXL_ControlWrite(fe, RFA_ENCLKRFAGC, 1); + + /* RSSI reference point */ + status += MXL_ControlWrite(fe, RFA_RSSI_REF, 3); + status += MXL_ControlWrite(fe, RFA_RSSI_REFH, 5); + status += MXL_ControlWrite(fe, RFA_RSSI_REFL, 1); + + /* TOP point */ + status += MXL_ControlWrite(fe, RFA_FLR, 2); + status += MXL_ControlWrite(fe, RFA_CEIL, 13); + if (state->IF_OUT <= 6280000UL) /* Low IF */ + status += MXL_ControlWrite(fe, BB_IQSWAP, 0); + else /* High IF */ + status += MXL_ControlWrite(fe, BB_IQSWAP, 1); } - if (Tuner->Mod_Type == MXL_ATSC) // ATSC Mode + if (state->Mod_Type == MXL_ATSC) /* ATSC Mode */ { - Tuner->AGC_Mode = 1 ; // Single AGC Mode - - // Enable RSSI - status += MXL_ControlWrite(Tuner, SEQ_EXTSYNTHCALIF, 1) ; - status += MXL_ControlWrite(Tuner, SEQ_EXTDCCAL, 1) ; - status += MXL_ControlWrite(Tuner, AGC_EN_RSSI, 1) ; - status += MXL_ControlWrite(Tuner, RFA_ENCLKRFAGC, 1) ; - // RSSI reference point - status += MXL_ControlWrite(Tuner, RFA_RSSI_REF, 2) ; - status += MXL_ControlWrite(Tuner, RFA_RSSI_REFH, 4) ; - status += MXL_ControlWrite(Tuner, RFA_RSSI_REFL, 1) ; - // TOP point - status += MXL_ControlWrite(Tuner, RFA_FLR, 2) ; - status += MXL_ControlWrite(Tuner, RFA_CEIL, 13) ; - - status += MXL_ControlWrite(Tuner, BB_INITSTATE_DLPF_TUNE, 1) ; - status += MXL_ControlWrite(Tuner, RFSYN_CHP_GAIN, 5) ; // Low Zero - if (Tuner->IF_OUT <= 6280000UL) // Low IF - status += MXL_ControlWrite(Tuner, BB_IQSWAP, 0) ; - else // High IF - status += MXL_ControlWrite(Tuner, BB_IQSWAP, 1) ; + Tuner->AGC_Mode = 1; /* Single AGC Mode */ + + /* Enable RSSI */ + status += MXL_ControlWrite(fe, SEQ_EXTSYNTHCALIF, 1); + status += MXL_ControlWrite(fe, SEQ_EXTDCCAL, 1); + status += MXL_ControlWrite(fe, AGC_EN_RSSI, 1); + status += MXL_ControlWrite(fe, RFA_ENCLKRFAGC, 1); + + /* RSSI reference point */ + status += MXL_ControlWrite(fe, RFA_RSSI_REF, 2); + status += MXL_ControlWrite(fe, RFA_RSSI_REFH, 4); + status += MXL_ControlWrite(fe, RFA_RSSI_REFL, 1); + + /* TOP point */ + status += MXL_ControlWrite(fe, RFA_FLR, 2); + status += MXL_ControlWrite(fe, RFA_CEIL, 13); + status += MXL_ControlWrite(fe, BB_INITSTATE_DLPF_TUNE, 1); + status += MXL_ControlWrite(fe, RFSYN_CHP_GAIN, 5); /* Low Zero */ + if (state->IF_OUT <= 6280000UL) /* Low IF */ + status += MXL_ControlWrite(fe, BB_IQSWAP, 0); + else /* High IF */ + status += MXL_ControlWrite(fe, BB_IQSWAP, 1); } - if (Tuner->Mod_Type == MXL_QAM) // QAM Mode + if (state->Mod_Type == MXL_QAM) /* QAM Mode */ { - Tuner->Mode = MXL_DIGITAL_MODE; - - //Tuner->AGC_Mode = 1 ; // Single AGC Mode - - // Disable RSSI //change here for v2.6.5 - status += MXL_ControlWrite(Tuner, SEQ_EXTSYNTHCALIF, 1) ; - status += MXL_ControlWrite(Tuner, SEQ_EXTDCCAL, 1) ; - status += MXL_ControlWrite(Tuner, AGC_EN_RSSI, 0) ; - status += MXL_ControlWrite(Tuner, RFA_ENCLKRFAGC, 1) ; - - // RSSI reference point - status += MXL_ControlWrite(Tuner, RFA_RSSI_REFH, 5) ; - status += MXL_ControlWrite(Tuner, RFA_RSSI_REF, 3) ; - status += MXL_ControlWrite(Tuner, RFA_RSSI_REFL, 2) ; - - status += MXL_ControlWrite(Tuner, RFSYN_CHP_GAIN, 3) ; //change here for v2.6.5 - - if (Tuner->IF_OUT <= 6280000UL) // Low IF - status += MXL_ControlWrite(Tuner, BB_IQSWAP, 0) ; - else // High IF - status += MXL_ControlWrite(Tuner, BB_IQSWAP, 1) ; + state->Mode = MXL_DIGITAL_MODE; + + /* state->AGC_Mode = 1; */ /* Single AGC Mode */ + + /* Disable RSSI */ /* change here for v2.6.5 */ + status += MXL_ControlWrite(fe, SEQ_EXTSYNTHCALIF, 1); + status += MXL_ControlWrite(fe, SEQ_EXTDCCAL, 1); + status += MXL_ControlWrite(fe, AGC_EN_RSSI, 0); + status += MXL_ControlWrite(fe, RFA_ENCLKRFAGC, 1); + + /* RSSI reference point */ + status += MXL_ControlWrite(fe, RFA_RSSI_REFH, 5); + status += MXL_ControlWrite(fe, RFA_RSSI_REF, 3); + status += MXL_ControlWrite(fe, RFA_RSSI_REFL, 2); + status += MXL_ControlWrite(fe, RFSYN_CHP_GAIN, 3); /* change here for v2.6.5 */ + + if (state->IF_OUT <= 6280000UL) /* Low IF */ + status += MXL_ControlWrite(fe, BB_IQSWAP, 0); + else /* High IF */ + status += MXL_ControlWrite(fe, BB_IQSWAP, 1); } - if (Tuner->Mod_Type == MXL_ANALOG_CABLE) // Analog Cable Mode - { - //Tuner->Mode = MXL_DIGITAL_MODE ; - Tuner->AGC_Mode = 1 ; // Single AGC Mode - - // Disable RSSI - status += MXL_ControlWrite(Tuner, SEQ_EXTSYNTHCALIF, 1) ; - status += MXL_ControlWrite(Tuner, SEQ_EXTDCCAL, 1) ; - status += MXL_ControlWrite(Tuner, AGC_EN_RSSI, 0) ; - status += MXL_ControlWrite(Tuner, RFA_ENCLKRFAGC, 1) ; - - status += MXL_ControlWrite(Tuner, AGC_IF, 1) ; //change for 2.6.3 - status += MXL_ControlWrite(Tuner, AGC_RF, 15) ; - - status += MXL_ControlWrite(Tuner, BB_IQSWAP, 1) ; + if (state->Mod_Type == MXL_ANALOG_CABLE) { + /* Analog Cable Mode */ + /* Tuner->Mode = MXL_DIGITAL_MODE; */ + + state->AGC_Mode = 1; /* Single AGC Mode */ + + /* Disable RSSI */ + status += MXL_ControlWrite(fe, SEQ_EXTSYNTHCALIF, 1); + status += MXL_ControlWrite(fe, SEQ_EXTDCCAL, 1); + status += MXL_ControlWrite(fe, AGC_EN_RSSI, 0); + status += MXL_ControlWrite(fe, RFA_ENCLKRFAGC, 1); + status += MXL_ControlWrite(fe, AGC_IF, 1); /* change for 2.6.3 */ + status += MXL_ControlWrite(fe, AGC_RF, 15); + status += MXL_ControlWrite(fe, BB_IQSWAP, 1); } - if (Tuner->Mod_Type == MXL_ANALOG_OTA) //Analog OTA Terrestrial mode add for 2.6.7 - { - //Tuner->Mode = MXL_ANALOG_MODE; - - // Enable RSSI - status += MXL_ControlWrite(Tuner, SEQ_EXTSYNTHCALIF, 1) ; - status += MXL_ControlWrite(Tuner, SEQ_EXTDCCAL, 1) ; - status += MXL_ControlWrite(Tuner, AGC_EN_RSSI, 1) ; - status += MXL_ControlWrite(Tuner, RFA_ENCLKRFAGC, 1) ; - - // RSSI reference point - status += MXL_ControlWrite(Tuner, RFA_RSSI_REFH, 5) ; - status += MXL_ControlWrite(Tuner, RFA_RSSI_REF, 3) ; - status += MXL_ControlWrite(Tuner, RFA_RSSI_REFL, 2) ; - - status += MXL_ControlWrite(Tuner, RFSYN_CHP_GAIN, 3) ; - - status += MXL_ControlWrite(Tuner, BB_IQSWAP, 1) ; + if (state->Mod_Type == MXL_ANALOG_OTA) { + /* Analog OTA Terrestrial mode add for 2.6.7 */ + /* state->Mode = MXL_ANALOG_MODE; */ + + /* Enable RSSI */ + status += MXL_ControlWrite(fe, SEQ_EXTSYNTHCALIF, 1); + status += MXL_ControlWrite(fe, SEQ_EXTDCCAL, 1); + status += MXL_ControlWrite(fe, AGC_EN_RSSI, 1); + status += MXL_ControlWrite(fe, RFA_ENCLKRFAGC, 1); + + /* RSSI reference point */ + status += MXL_ControlWrite(fe, RFA_RSSI_REFH, 5); + status += MXL_ControlWrite(fe, RFA_RSSI_REF, 3); + status += MXL_ControlWrite(fe, RFA_RSSI_REFL, 2); + status += MXL_ControlWrite(fe, RFSYN_CHP_GAIN, 3); + status += MXL_ControlWrite(fe, BB_IQSWAP, 1); } - // RSSI disable - if(Tuner->EN_RSSI==0) - { - status += MXL_ControlWrite(Tuner, SEQ_EXTSYNTHCALIF, 1) ; - status += MXL_ControlWrite(Tuner, SEQ_EXTDCCAL, 1) ; - status += MXL_ControlWrite(Tuner, AGC_EN_RSSI, 0) ; - status += MXL_ControlWrite(Tuner, RFA_ENCLKRFAGC, 1) ; + /* RSSI disable */ + if(state->EN_RSSI==0) { + status += MXL_ControlWrite(fe, SEQ_EXTSYNTHCALIF, 1); + status += MXL_ControlWrite(fe, SEQ_EXTDCCAL, 1); + status += MXL_ControlWrite(fe, AGC_EN_RSSI, 0); + status += MXL_ControlWrite(fe, RFA_ENCLKRFAGC, 1); } - return status ; + return status; } /////////////////////////////////////////////////////////////////////////////// @@ -2456,9 +2437,9 @@ u16 MXL_IFSynthInit(Tuner_struct * Tuner) u32 fracModVal ; Kdbl = 2 ; - if (Tuner->Fxtal >= 12000000UL && Tuner->Fxtal <= 16000000UL) + if (state->Fxtal >= 12000000UL && state->Fxtal <= 16000000UL) Kdbl = 2 ; - if (Tuner->Fxtal > 16000000UL && Tuner->Fxtal <= 32000000UL) + if (state->Fxtal > 16000000UL && state->Fxtal <= 32000000UL) Kdbl = 1 ; // @@ -2467,43 +2448,43 @@ u16 MXL_IFSynthInit(Tuner_struct * Tuner) if (Tuner->Mode == 0 && Tuner->IF_Mode == 1) // Analog Low IF mode { if (Tuner->IF_LO == 41000000UL) { - status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x08) ; - status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x0C) ; + status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08) ; + status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C) ; Fref = 328000000UL ; } if (Tuner->IF_LO == 47000000UL) { - status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x08) ; - status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x08) ; + status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08) ; + status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; Fref = 376000000UL ; } if (Tuner->IF_LO == 54000000UL) { - status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x10) ; - status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x0C) ; + status += MXL_ControlWrite(fe, IF_DIVVAL, 0x10) ; + status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C) ; Fref = 324000000UL ; } if (Tuner->IF_LO == 60000000UL) { - status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x10) ; - status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x08) ; + status += MXL_ControlWrite(fe, IF_DIVVAL, 0x10) ; + status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; Fref = 360000000UL ; } if (Tuner->IF_LO == 39250000UL) { - status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x08) ; - status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x0C) ; + status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08) ; + status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C) ; Fref = 314000000UL ; } if (Tuner->IF_LO == 39650000UL) { - status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x08) ; - status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x0C) ; + status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08) ; + status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C) ; Fref = 317200000UL ; } if (Tuner->IF_LO == 40150000UL) { - status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x08) ; - status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x0C) ; + status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08) ; + status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C) ; Fref = 321200000UL ; } if (Tuner->IF_LO == 40650000UL) { - status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x08) ; - status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x0C) ; + status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08) ; + status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C) ; Fref = 325200000UL ; } } @@ -2511,153 +2492,153 @@ u16 MXL_IFSynthInit(Tuner_struct * Tuner) if (Tuner->Mode || (Tuner->Mode == 0 && Tuner->IF_Mode == 0)) { if (Tuner->IF_LO == 57000000UL) { - status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x10) ; - status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x08) ; + status += MXL_ControlWrite(fe, IF_DIVVAL, 0x10) ; + status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; Fref = 342000000UL ; } if (Tuner->IF_LO == 44000000UL) { - status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x08) ; - status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x08) ; + status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08) ; + status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; Fref = 352000000UL ; } if (Tuner->IF_LO == 43750000UL) { - status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x08) ; - status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x08) ; + status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08) ; + status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; Fref = 350000000UL ; } if (Tuner->IF_LO == 36650000UL) { - status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x04) ; - status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x08) ; + status += MXL_ControlWrite(fe, IF_DIVVAL, 0x04) ; + status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; Fref = 366500000UL ; } if (Tuner->IF_LO == 36150000UL) { - status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x04) ; - status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x08) ; + status += MXL_ControlWrite(fe, IF_DIVVAL, 0x04) ; + status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; Fref = 361500000UL ; } if (Tuner->IF_LO == 36000000UL) { - status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x04) ; - status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x08) ; + status += MXL_ControlWrite(fe, IF_DIVVAL, 0x04) ; + status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; Fref = 360000000UL ; } if (Tuner->IF_LO == 35250000UL) { - status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x04) ; - status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x08) ; + status += MXL_ControlWrite(fe, IF_DIVVAL, 0x04) ; + status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; Fref = 352500000UL ; } if (Tuner->IF_LO == 34750000UL) { - status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x04) ; - status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x08) ; + status += MXL_ControlWrite(fe, IF_DIVVAL, 0x04) ; + status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; Fref = 347500000UL ; } if (Tuner->IF_LO == 6280000UL) { - status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x07) ; - status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x08) ; + status += MXL_ControlWrite(fe, IF_DIVVAL, 0x07) ; + status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; Fref = 376800000UL ; } if (Tuner->IF_LO == 5000000UL) { - status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x09) ; - status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x08) ; + status += MXL_ControlWrite(fe, IF_DIVVAL, 0x09) ; + status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; Fref = 360000000UL ; } if (Tuner->IF_LO == 4500000UL) { - status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x06) ; - status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x08) ; + status += MXL_ControlWrite(fe, IF_DIVVAL, 0x06) ; + status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; Fref = 360000000UL ; } if (Tuner->IF_LO == 4570000UL) { - status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x06) ; - status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x08) ; + status += MXL_ControlWrite(fe, IF_DIVVAL, 0x06) ; + status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; Fref = 365600000UL ; } if (Tuner->IF_LO == 4000000UL) { - status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x05) ; - status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x08) ; + status += MXL_ControlWrite(fe, IF_DIVVAL, 0x05) ; + status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; Fref = 360000000UL ; } if (Tuner->IF_LO == 57400000UL) { - status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x10) ; - status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x08) ; + status += MXL_ControlWrite(fe, IF_DIVVAL, 0x10) ; + status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; Fref = 344400000UL ; } if (Tuner->IF_LO == 44400000UL) { - status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x08) ; - status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x08) ; + status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08) ; + status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; Fref = 355200000UL ; } if (Tuner->IF_LO == 44150000UL) { - status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x08) ; - status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x08) ; + status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08) ; + status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; Fref = 353200000UL ; } if (Tuner->IF_LO == 37050000UL) { - status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x04) ; - status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x08) ; + status += MXL_ControlWrite(fe, IF_DIVVAL, 0x04) ; + status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; Fref = 370500000UL ; } if (Tuner->IF_LO == 36550000UL) { - status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x04) ; - status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x08) ; + status += MXL_ControlWrite(fe, IF_DIVVAL, 0x04) ; + status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; Fref = 365500000UL ; } if (Tuner->IF_LO == 36125000UL) { - status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x04) ; - status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x08) ; + status += MXL_ControlWrite(fe, IF_DIVVAL, 0x04) ; + status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; Fref = 361250000UL ; } if (Tuner->IF_LO == 6000000UL) { - status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x07) ; - status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x08) ; + status += MXL_ControlWrite(fe, IF_DIVVAL, 0x07) ; + status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; Fref = 360000000UL ; } if (Tuner->IF_LO == 5400000UL) { - status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x07) ; - status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x0C) ; + status += MXL_ControlWrite(fe, IF_DIVVAL, 0x07) ; + status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C) ; Fref = 324000000UL ; } if (Tuner->IF_LO == 5380000UL) { - status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x07) ; - status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x0C) ; + status += MXL_ControlWrite(fe, IF_DIVVAL, 0x07) ; + status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C) ; Fref = 322800000UL ; } if (Tuner->IF_LO == 5200000UL) { - status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x09) ; - status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x08) ; + status += MXL_ControlWrite(fe, IF_DIVVAL, 0x09) ; + status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; Fref = 374400000UL ; } if (Tuner->IF_LO == 4900000UL) { - status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x09) ; - status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x08) ; + status += MXL_ControlWrite(fe, IF_DIVVAL, 0x09) ; + status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; Fref = 352800000UL ; } if (Tuner->IF_LO == 4400000UL) { - status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x06) ; - status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x08) ; + status += MXL_ControlWrite(fe, IF_DIVVAL, 0x06) ; + status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; Fref = 352000000UL ; } if (Tuner->IF_LO == 4063000UL) //add for 2.6.8 { - status += MXL_ControlWrite(Tuner, IF_DIVVAL, 0x05) ; - status += MXL_ControlWrite(Tuner, IF_VCO_BIAS, 0x08) ; + status += MXL_ControlWrite(fe, IF_DIVVAL, 0x05) ; + status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; Fref = 365670000UL ; } } // CHCAL_INT_MOD_IF // CHCAL_FRAC_MOD_IF - intModVal = Fref / (Tuner->Fxtal * Kdbl/2) ; - status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_IF, intModVal ) ; + intModVal = Fref / (state->Fxtal * Kdbl/2) ; + status += MXL_ControlWrite(fe, CHCAL_INT_MOD_IF, intModVal ) ; - fracModVal = (2<<15)*(Fref/1000 - (Tuner->Fxtal/1000 * Kdbl/2) * intModVal); - fracModVal = fracModVal / ((Tuner->Fxtal * Kdbl/2)/1000) ; - status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_IF, fracModVal) ; + fracModVal = (2<<15)*(Fref/1000 - (state->Fxtal/1000 * Kdbl/2) * intModVal); + fracModVal = fracModVal / ((state->Fxtal * Kdbl/2)/1000) ; + status += MXL_ControlWrite(fe, CHCAL_FRAC_MOD_IF, fracModVal) ; return status ; } @@ -2706,7 +2687,7 @@ u32 MXL_GetXtalInt(u32 Xtal_Freq) // Functions used: // // MXL_SynthRFTGLO_Calc // // MXL5005_ControlWrite // -// MXL_GetXtalInt // +// MXL_GetXtalInt // // // // Inputs: // // Tuner : Tuner structure defined at higher level // @@ -2718,32 +2699,33 @@ u32 MXL_GetXtalInt(u32 Xtal_Freq) // 0 : Successful // // 1 : Unsuccessful // /////////////////////////////////////////////////////////////////////////////// -u16 MXL_TuneRF(Tuner_struct *Tuner, u32 RF_Freq) +u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq) { + struct mxl5005s_state *state = fe->demodulator_priv; // Declare Local Variables - u16 status = 0 ; - u32 divider_val, E3, E4, E5, E5A ; - u32 Fmax, Fmin, FmaxBin, FminBin ; + u16 status = 0; + u32 divider_val, E3, E4, E5, E5A; + u32 Fmax, Fmin, FmaxBin, FminBin; u32 Kdbl_RF = 2; - u32 tg_divval ; - u32 tg_lo ; - u32 Xtal_Int ; + u32 tg_divval; + u32 tg_lo; + u32 Xtal_Int; u32 Fref_TG; u32 Fvco; // u32 temp; - Xtal_Int = MXL_GetXtalInt(Tuner->Fxtal ) ; + Xtal_Int = MXL_GetXtalInt(state->Fxtal); - Tuner->RF_IN = RF_Freq ; + state->RF_IN = RF_Freq; - MXL_SynthRFTGLO_Calc( Tuner ) ; + MXL_SynthRFTGLO_Calc(fe); - if (Tuner->Fxtal >= 12000000UL && Tuner->Fxtal <= 22000000UL) - Kdbl_RF = 2 ; - if (Tuner->Fxtal > 22000000 && Tuner->Fxtal <= 32000000) - Kdbl_RF = 1 ; + if (state->Fxtal >= 12000000UL && state->Fxtal <= 22000000UL) + Kdbl_RF = 2; + if (state->Fxtal > 22000000 && state->Fxtal <= 32000000) + Kdbl_RF = 1; // // Downconverter Controls @@ -2755,133 +2737,133 @@ u16 MXL_TuneRF(Tuner_struct *Tuner, u32 RF_Freq) // DN_EN_VHFUHFBAR // DN_GAIN_ADJUST // Change the boundary reference from RF_IN to RF_LO - if (Tuner->RF_LO < 40000000UL) { + if (state->RF_LO < 40000000UL) { return -1; } - if (Tuner->RF_LO >= 40000000UL && Tuner->RF_LO <= 75000000UL) { + if (state->RF_LO >= 40000000UL && state->RF_LO <= 75000000UL) { // Look-Up Table implementation - status += MXL_ControlWrite(Tuner, DN_POLY, 2) ; - status += MXL_ControlWrite(Tuner, DN_RFGAIN, 3) ; - status += MXL_ControlWrite(Tuner, DN_CAP_RFLPF, 423) ; - status += MXL_ControlWrite(Tuner, DN_EN_VHFUHFBAR, 1) ; - status += MXL_ControlWrite(Tuner, DN_GAIN_ADJUST, 1) ; + status += MXL_ControlWrite(fe, DN_POLY, 2); + status += MXL_ControlWrite(fe, DN_RFGAIN, 3); + status += MXL_ControlWrite(fe, DN_CAP_RFLPF, 423); + status += MXL_ControlWrite(fe, DN_EN_VHFUHFBAR, 1); + status += MXL_ControlWrite(fe, DN_GAIN_ADJUST, 1); } - if (Tuner->RF_LO > 75000000UL && Tuner->RF_LO <= 100000000UL) { + if (state->RF_LO > 75000000UL && state->RF_LO <= 100000000UL) { // Look-Up Table implementation - status += MXL_ControlWrite(Tuner, DN_POLY, 3) ; - status += MXL_ControlWrite(Tuner, DN_RFGAIN, 3) ; - status += MXL_ControlWrite(Tuner, DN_CAP_RFLPF, 222) ; - status += MXL_ControlWrite(Tuner, DN_EN_VHFUHFBAR, 1) ; - status += MXL_ControlWrite(Tuner, DN_GAIN_ADJUST, 1) ; + status += MXL_ControlWrite(fe, DN_POLY, 3); + status += MXL_ControlWrite(fe, DN_RFGAIN, 3); + status += MXL_ControlWrite(fe, DN_CAP_RFLPF, 222); + status += MXL_ControlWrite(fe, DN_EN_VHFUHFBAR, 1); + status += MXL_ControlWrite(fe, DN_GAIN_ADJUST, 1); } - if (Tuner->RF_LO > 100000000UL && Tuner->RF_LO <= 150000000UL) { + if (state->RF_LO > 100000000UL && state->RF_LO <= 150000000UL) { // Look-Up Table implementation - status += MXL_ControlWrite(Tuner, DN_POLY, 3) ; - status += MXL_ControlWrite(Tuner, DN_RFGAIN, 3) ; - status += MXL_ControlWrite(Tuner, DN_CAP_RFLPF, 147) ; - status += MXL_ControlWrite(Tuner, DN_EN_VHFUHFBAR, 1) ; - status += MXL_ControlWrite(Tuner, DN_GAIN_ADJUST, 2) ; + status += MXL_ControlWrite(fe, DN_POLY, 3); + status += MXL_ControlWrite(fe, DN_RFGAIN, 3); + status += MXL_ControlWrite(fe, DN_CAP_RFLPF, 147); + status += MXL_ControlWrite(fe, DN_EN_VHFUHFBAR, 1); + status += MXL_ControlWrite(fe, DN_GAIN_ADJUST, 2); } - if (Tuner->RF_LO > 150000000UL && Tuner->RF_LO <= 200000000UL) { + if (state->RF_LO > 150000000UL && state->RF_LO <= 200000000UL) { // Look-Up Table implementation - status += MXL_ControlWrite(Tuner, DN_POLY, 3) ; - status += MXL_ControlWrite(Tuner, DN_RFGAIN, 3) ; - status += MXL_ControlWrite(Tuner, DN_CAP_RFLPF, 9) ; - status += MXL_ControlWrite(Tuner, DN_EN_VHFUHFBAR, 1) ; - status += MXL_ControlWrite(Tuner, DN_GAIN_ADJUST, 2) ; + status += MXL_ControlWrite(fe, DN_POLY, 3); + status += MXL_ControlWrite(fe, DN_RFGAIN, 3); + status += MXL_ControlWrite(fe, DN_CAP_RFLPF, 9); + status += MXL_ControlWrite(fe, DN_EN_VHFUHFBAR, 1); + status += MXL_ControlWrite(fe, DN_GAIN_ADJUST, 2); } - if (Tuner->RF_LO > 200000000UL && Tuner->RF_LO <= 300000000UL) { + if (state->RF_LO > 200000000UL && state->RF_LO <= 300000000UL) { // Look-Up Table implementation - status += MXL_ControlWrite(Tuner, DN_POLY, 3) ; - status += MXL_ControlWrite(Tuner, DN_RFGAIN, 3) ; - status += MXL_ControlWrite(Tuner, DN_CAP_RFLPF, 0) ; - status += MXL_ControlWrite(Tuner, DN_EN_VHFUHFBAR, 1) ; - status += MXL_ControlWrite(Tuner, DN_GAIN_ADJUST, 3) ; + status += MXL_ControlWrite(fe, DN_POLY, 3) ; + status += MXL_ControlWrite(fe, DN_RFGAIN, 3) ; + status += MXL_ControlWrite(fe, DN_CAP_RFLPF, 0) ; + status += MXL_ControlWrite(fe, DN_EN_VHFUHFBAR, 1) ; + status += MXL_ControlWrite(fe, DN_GAIN_ADJUST, 3) ; } - if (Tuner->RF_LO > 300000000UL && Tuner->RF_LO <= 650000000UL) { + if (state->RF_LO > 300000000UL && state->RF_LO <= 650000000UL) { // Look-Up Table implementation - status += MXL_ControlWrite(Tuner, DN_POLY, 3) ; - status += MXL_ControlWrite(Tuner, DN_RFGAIN, 1) ; - status += MXL_ControlWrite(Tuner, DN_CAP_RFLPF, 0) ; - status += MXL_ControlWrite(Tuner, DN_EN_VHFUHFBAR, 0) ; - status += MXL_ControlWrite(Tuner, DN_GAIN_ADJUST, 3) ; + status += MXL_ControlWrite(fe, DN_POLY, 3) ; + status += MXL_ControlWrite(fe, DN_RFGAIN, 1) ; + status += MXL_ControlWrite(fe, DN_CAP_RFLPF, 0) ; + status += MXL_ControlWrite(fe, DN_EN_VHFUHFBAR, 0) ; + status += MXL_ControlWrite(fe, DN_GAIN_ADJUST, 3) ; } - if (Tuner->RF_LO > 650000000UL && Tuner->RF_LO <= 900000000UL) { + if (state->RF_LO > 650000000UL && state->RF_LO <= 900000000UL) { // Look-Up Table implementation - status += MXL_ControlWrite(Tuner, DN_POLY, 3) ; - status += MXL_ControlWrite(Tuner, DN_RFGAIN, 2) ; - status += MXL_ControlWrite(Tuner, DN_CAP_RFLPF, 0) ; - status += MXL_ControlWrite(Tuner, DN_EN_VHFUHFBAR, 0) ; - status += MXL_ControlWrite(Tuner, DN_GAIN_ADJUST, 3) ; + status += MXL_ControlWrite(fe, DN_POLY, 3) ; + status += MXL_ControlWrite(fe, DN_RFGAIN, 2) ; + status += MXL_ControlWrite(fe, DN_CAP_RFLPF, 0) ; + status += MXL_ControlWrite(fe, DN_EN_VHFUHFBAR, 0) ; + status += MXL_ControlWrite(fe, DN_GAIN_ADJUST, 3) ; } - if (Tuner->RF_LO > 900000000UL) { + if (state->RF_LO > 900000000UL) { return -1; } // DN_IQTNBUF_AMP // DN_IQTNGNBFBIAS_BST - if (Tuner->RF_LO >= 40000000UL && Tuner->RF_LO <= 75000000UL) { - status += MXL_ControlWrite(Tuner, DN_IQTNBUF_AMP, 1) ; - status += MXL_ControlWrite(Tuner, DN_IQTNGNBFBIAS_BST, 0) ; + if (state->RF_LO >= 40000000UL && state->RF_LO <= 75000000UL) { + status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP, 1); + status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST, 0); } - if (Tuner->RF_LO > 75000000UL && Tuner->RF_LO <= 100000000UL) { - status += MXL_ControlWrite(Tuner, DN_IQTNBUF_AMP, 1) ; - status += MXL_ControlWrite(Tuner, DN_IQTNGNBFBIAS_BST, 0) ; + if (state->RF_LO > 75000000UL && state->RF_LO <= 100000000UL) { + status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP, 1); + status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST, 0); } - if (Tuner->RF_LO > 100000000UL && Tuner->RF_LO <= 150000000UL) { - status += MXL_ControlWrite(Tuner, DN_IQTNBUF_AMP, 1) ; - status += MXL_ControlWrite(Tuner, DN_IQTNGNBFBIAS_BST, 0) ; + if (state->RF_LO > 100000000UL && state->RF_LO <= 150000000UL) { + status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP, 1); + status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST, 0); } - if (Tuner->RF_LO > 150000000UL && Tuner->RF_LO <= 200000000UL) { - status += MXL_ControlWrite(Tuner, DN_IQTNBUF_AMP, 1) ; - status += MXL_ControlWrite(Tuner, DN_IQTNGNBFBIAS_BST, 0) ; + if (state->RF_LO > 150000000UL && state->RF_LO <= 200000000UL) { + status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP, 1); + status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST, 0); } - if (Tuner->RF_LO > 200000000UL && Tuner->RF_LO <= 300000000UL) { - status += MXL_ControlWrite(Tuner, DN_IQTNBUF_AMP, 1) ; - status += MXL_ControlWrite(Tuner, DN_IQTNGNBFBIAS_BST, 0) ; + if (state->RF_LO > 200000000UL && state->RF_LO <= 300000000UL) { + status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP, 1); + status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST, 0); } - if (Tuner->RF_LO > 300000000UL && Tuner->RF_LO <= 400000000UL) { - status += MXL_ControlWrite(Tuner, DN_IQTNBUF_AMP, 1) ; - status += MXL_ControlWrite(Tuner, DN_IQTNGNBFBIAS_BST, 0) ; + if (state->RF_LO > 300000000UL && state->RF_LO <= 400000000UL) { + status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP, 1); + status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST, 0); } - if (Tuner->RF_LO > 400000000UL && Tuner->RF_LO <= 450000000UL) { - status += MXL_ControlWrite(Tuner, DN_IQTNBUF_AMP, 1) ; - status += MXL_ControlWrite(Tuner, DN_IQTNGNBFBIAS_BST, 0) ; + if (state->RF_LO > 400000000UL && state->RF_LO <= 450000000UL) { + status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP, 1); + status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST, 0); } - if (Tuner->RF_LO > 450000000UL && Tuner->RF_LO <= 500000000UL) { - status += MXL_ControlWrite(Tuner, DN_IQTNBUF_AMP, 1) ; - status += MXL_ControlWrite(Tuner, DN_IQTNGNBFBIAS_BST, 0) ; + if (state->RF_LO > 450000000UL && state->RF_LO <= 500000000UL) { + status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP, 1); + status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST, 0); } - if (Tuner->RF_LO > 500000000UL && Tuner->RF_LO <= 550000000UL) { - status += MXL_ControlWrite(Tuner, DN_IQTNBUF_AMP, 1) ; - status += MXL_ControlWrite(Tuner, DN_IQTNGNBFBIAS_BST, 0) ; + if (state->RF_LO > 500000000UL && state->RF_LO <= 550000000UL) { + status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP, 1); + status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST, 0); } - if (Tuner->RF_LO > 550000000UL && Tuner->RF_LO <= 600000000UL) { - status += MXL_ControlWrite(Tuner, DN_IQTNBUF_AMP, 1) ; - status += MXL_ControlWrite(Tuner, DN_IQTNGNBFBIAS_BST, 0) ; + if (state->RF_LO > 550000000UL && state->RF_LO <= 600000000UL) { + status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP, 1); + status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST, 0); } - if (Tuner->RF_LO > 600000000UL && Tuner->RF_LO <= 650000000UL) { - status += MXL_ControlWrite(Tuner, DN_IQTNBUF_AMP, 1) ; - status += MXL_ControlWrite(Tuner, DN_IQTNGNBFBIAS_BST, 0) ; + if (state->RF_LO > 600000000UL && state->RF_LO <= 650000000UL) { + status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP, 1); + status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST, 0); } - if (Tuner->RF_LO > 650000000UL && Tuner->RF_LO <= 700000000UL) { - status += MXL_ControlWrite(Tuner, DN_IQTNBUF_AMP, 1) ; - status += MXL_ControlWrite(Tuner, DN_IQTNGNBFBIAS_BST, 0) ; + if (state->RF_LO > 650000000UL && state->RF_LO <= 700000000UL) { + status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP, 1); + status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST, 0); } - if (Tuner->RF_LO > 700000000UL && Tuner->RF_LO <= 750000000UL) { - status += MXL_ControlWrite(Tuner, DN_IQTNBUF_AMP, 1) ; - status += MXL_ControlWrite(Tuner, DN_IQTNGNBFBIAS_BST, 0) ; + if (state->RF_LO > 700000000UL && state->RF_LO <= 750000000UL) { + status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP, 1); + status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST, 0); } - if (Tuner->RF_LO > 750000000UL && Tuner->RF_LO <= 800000000UL) { - status += MXL_ControlWrite(Tuner, DN_IQTNBUF_AMP, 1) ; - status += MXL_ControlWrite(Tuner, DN_IQTNGNBFBIAS_BST, 0) ; + if (state->RF_LO > 750000000UL && state->RF_LO <= 800000000UL) { + status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP, 1); + status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST, 0); } - if (Tuner->RF_LO > 800000000UL && Tuner->RF_LO <= 850000000UL) { - status += MXL_ControlWrite(Tuner, DN_IQTNBUF_AMP, 10) ; - status += MXL_ControlWrite(Tuner, DN_IQTNGNBFBIAS_BST, 1) ; + if (state->RF_LO > 800000000UL && state->RF_LO <= 850000000UL) { + status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP, 10); + status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST, 1); } - if (Tuner->RF_LO > 850000000UL && Tuner->RF_LO <= 900000000UL) { - status += MXL_ControlWrite(Tuner, DN_IQTNBUF_AMP, 10) ; - status += MXL_ControlWrite(Tuner, DN_IQTNGNBFBIAS_BST, 1) ; + if (state->RF_LO > 850000000UL && state->RF_LO <= 900000000UL) { + status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP, 10); + status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST, 1); } // @@ -2898,143 +2880,143 @@ u16 MXL_TuneRF(Tuner_struct *Tuner, u32 RF_Freq) // Set divider_val, Fmax, Fmix to use in Equations FminBin = 28000000UL ; FmaxBin = 42500000UL ; - if (Tuner->RF_LO >= 40000000UL && Tuner->RF_LO <= FmaxBin) { - status += MXL_ControlWrite(Tuner, RFSYN_EN_OUTMUX, 1) ; - status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_OUT, 0) ; - status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 0) ; - status += MXL_ControlWrite(Tuner, RFSYN_SEL_DIVM, 0) ; - status += MXL_ControlWrite(Tuner, RFSYN_RF_DIV_BIAS, 1) ; - status += MXL_ControlWrite(Tuner, DN_SEL_FREQ, 1) ; + if (state->RF_LO >= 40000000UL && state->RF_LO <= FmaxBin) { + status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 1); + status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 0); + status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0); + status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0); + status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1); + status += MXL_ControlWrite(fe, DN_SEL_FREQ, 1); divider_val = 64 ; Fmax = FmaxBin ; Fmin = FminBin ; } FminBin = 42500000UL ; FmaxBin = 56000000UL ; - if (Tuner->RF_LO > FminBin && Tuner->RF_LO <= FmaxBin) { - status += MXL_ControlWrite(Tuner, RFSYN_EN_OUTMUX, 1) ; - status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_OUT, 0) ; - status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 1) ; - status += MXL_ControlWrite(Tuner, RFSYN_SEL_DIVM, 0) ; - status += MXL_ControlWrite(Tuner, RFSYN_RF_DIV_BIAS, 1) ; - status += MXL_ControlWrite(Tuner, DN_SEL_FREQ, 1) ; + if (state->RF_LO > FminBin && state->RF_LO <= FmaxBin) { + status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 1); + status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 0); + status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1); + status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0); + status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1); + status += MXL_ControlWrite(fe, DN_SEL_FREQ, 1); divider_val = 64 ; Fmax = FmaxBin ; Fmin = FminBin ; } FminBin = 56000000UL ; FmaxBin = 85000000UL ; - if (Tuner->RF_LO > FminBin && Tuner->RF_LO <= FmaxBin) { - status += MXL_ControlWrite(Tuner, RFSYN_EN_OUTMUX, 0) ; - status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_OUT, 1) ; - status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 0) ; - status += MXL_ControlWrite(Tuner, RFSYN_SEL_DIVM, 0) ; - status += MXL_ControlWrite(Tuner, RFSYN_RF_DIV_BIAS, 1) ; - status += MXL_ControlWrite(Tuner, DN_SEL_FREQ, 1) ; + if (state->RF_LO > FminBin && state->RF_LO <= FmaxBin) { + status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 0) ; + status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 1) ; + status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0) ; + status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0) ; + status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1) ; + status += MXL_ControlWrite(fe, DN_SEL_FREQ, 1) ; divider_val = 32 ; Fmax = FmaxBin ; Fmin = FminBin ; } FminBin = 85000000UL ; FmaxBin = 112000000UL ; - if (Tuner->RF_LO > FminBin && Tuner->RF_LO <= FmaxBin) { - status += MXL_ControlWrite(Tuner, RFSYN_EN_OUTMUX, 0) ; - status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_OUT, 1) ; - status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 1) ; - status += MXL_ControlWrite(Tuner, RFSYN_SEL_DIVM, 0) ; - status += MXL_ControlWrite(Tuner, RFSYN_RF_DIV_BIAS, 1) ; - status += MXL_ControlWrite(Tuner, DN_SEL_FREQ, 1) ; + if (state->RF_LO > FminBin && state->RF_LO <= FmaxBin) { + status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 0) ; + status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 1) ; + status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1) ; + status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0) ; + status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1) ; + status += MXL_ControlWrite(fe, DN_SEL_FREQ, 1) ; divider_val = 32 ; Fmax = FmaxBin ; Fmin = FminBin ; } FminBin = 112000000UL ; FmaxBin = 170000000UL ; - if (Tuner->RF_LO > FminBin && Tuner->RF_LO <= FmaxBin) { - status += MXL_ControlWrite(Tuner, RFSYN_EN_OUTMUX, 0) ; - status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_OUT, 1) ; - status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 0) ; - status += MXL_ControlWrite(Tuner, RFSYN_SEL_DIVM, 0) ; - status += MXL_ControlWrite(Tuner, RFSYN_RF_DIV_BIAS, 1) ; - status += MXL_ControlWrite(Tuner, DN_SEL_FREQ, 2) ; + if (state->RF_LO > FminBin && state->RF_LO <= FmaxBin) { + status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 0) ; + status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 1) ; + status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0) ; + status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0) ; + status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1) ; + status += MXL_ControlWrite(fe, DN_SEL_FREQ, 2) ; divider_val = 16 ; Fmax = FmaxBin ; Fmin = FminBin ; } FminBin = 170000000UL ; FmaxBin = 225000000UL ; - if (Tuner->RF_LO > FminBin && Tuner->RF_LO <= FmaxBin) { - status += MXL_ControlWrite(Tuner, RFSYN_EN_OUTMUX, 0) ; - status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_OUT, 1) ; - status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 1) ; - status += MXL_ControlWrite(Tuner, RFSYN_SEL_DIVM, 0) ; - status += MXL_ControlWrite(Tuner, RFSYN_RF_DIV_BIAS, 1) ; - status += MXL_ControlWrite(Tuner, DN_SEL_FREQ, 2) ; + if (state->RF_LO > FminBin && state->RF_LO <= FmaxBin) { + status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 0) ; + status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 1) ; + status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1) ; + status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0) ; + status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1) ; + status += MXL_ControlWrite(fe, DN_SEL_FREQ, 2) ; divider_val = 16 ; Fmax = FmaxBin ; Fmin = FminBin ; } FminBin = 225000000UL ; FmaxBin = 300000000UL ; - if (Tuner->RF_LO > FminBin && Tuner->RF_LO <= FmaxBin) { - status += MXL_ControlWrite(Tuner, RFSYN_EN_OUTMUX, 0) ; - status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_OUT, 1) ; - status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 0) ; - status += MXL_ControlWrite(Tuner, RFSYN_SEL_DIVM, 0) ; - status += MXL_ControlWrite(Tuner, RFSYN_RF_DIV_BIAS, 1) ; - status += MXL_ControlWrite(Tuner, DN_SEL_FREQ, 4) ; + if (state->RF_LO > FminBin && state->RF_LO <= FmaxBin) { + status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 0) ; + status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 1) ; + status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0) ; + status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0) ; + status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1) ; + status += MXL_ControlWrite(fe, DN_SEL_FREQ, 4) ; divider_val = 8 ; Fmax = 340000000UL ; Fmin = FminBin ; } FminBin = 300000000UL ; FmaxBin = 340000000UL ; - if (Tuner->RF_LO > FminBin && Tuner->RF_LO <= FmaxBin) { - status += MXL_ControlWrite(Tuner, RFSYN_EN_OUTMUX, 1) ; - status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_OUT, 0) ; - status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 0) ; - status += MXL_ControlWrite(Tuner, RFSYN_SEL_DIVM, 0) ; - status += MXL_ControlWrite(Tuner, RFSYN_RF_DIV_BIAS, 1) ; - status += MXL_ControlWrite(Tuner, DN_SEL_FREQ, 0) ; + if (state->RF_LO > FminBin && state->RF_LO <= FmaxBin) { + status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 1) ; + status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 0) ; + status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0) ; + status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0) ; + status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1) ; + status += MXL_ControlWrite(fe, DN_SEL_FREQ, 0) ; divider_val = 8 ; Fmax = FmaxBin ; Fmin = 225000000UL ; } FminBin = 340000000UL ; FmaxBin = 450000000UL ; - if (Tuner->RF_LO > FminBin && Tuner->RF_LO <= FmaxBin) { - status += MXL_ControlWrite(Tuner, RFSYN_EN_OUTMUX, 1) ; - status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_OUT, 0) ; - status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 1) ; - status += MXL_ControlWrite(Tuner, RFSYN_SEL_DIVM, 0) ; - status += MXL_ControlWrite(Tuner, RFSYN_RF_DIV_BIAS, 2) ; - status += MXL_ControlWrite(Tuner, DN_SEL_FREQ, 0) ; + if (state->RF_LO > FminBin && state->RF_LO <= FmaxBin) { + status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 1) ; + status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 0) ; + status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1) ; + status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0) ; + status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 2) ; + status += MXL_ControlWrite(fe, DN_SEL_FREQ, 0) ; divider_val = 8 ; Fmax = FmaxBin ; Fmin = FminBin ; } FminBin = 450000000UL ; FmaxBin = 680000000UL ; - if (Tuner->RF_LO > FminBin && Tuner->RF_LO <= FmaxBin) { - status += MXL_ControlWrite(Tuner, RFSYN_EN_OUTMUX, 0) ; - status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_OUT, 1) ; - status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 0) ; - status += MXL_ControlWrite(Tuner, RFSYN_SEL_DIVM, 1) ; - status += MXL_ControlWrite(Tuner, RFSYN_RF_DIV_BIAS, 1) ; - status += MXL_ControlWrite(Tuner, DN_SEL_FREQ, 0) ; + if (state->RF_LO > FminBin && state->RF_LO <= FmaxBin) { + status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 0) ; + status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 1) ; + status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0) ; + status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 1) ; + status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1) ; + status += MXL_ControlWrite(fe, DN_SEL_FREQ, 0) ; divider_val = 4 ; Fmax = FmaxBin ; Fmin = FminBin ; } FminBin = 680000000UL ; FmaxBin = 900000000UL ; - if (Tuner->RF_LO > FminBin && Tuner->RF_LO <= FmaxBin) { - status += MXL_ControlWrite(Tuner, RFSYN_EN_OUTMUX, 0) ; - status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_OUT, 1) ; - status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 1) ; - status += MXL_ControlWrite(Tuner, RFSYN_SEL_DIVM, 1) ; - status += MXL_ControlWrite(Tuner, RFSYN_RF_DIV_BIAS, 1) ; - status += MXL_ControlWrite(Tuner, DN_SEL_FREQ, 0) ; + if (state->RF_LO > FminBin && state->RF_LO <= FmaxBin) { + status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 0) ; + status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 1) ; + status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1) ; + status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 1) ; + status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1) ; + status += MXL_ControlWrite(fe, DN_SEL_FREQ, 0) ; divider_val = 4 ; Fmax = FmaxBin ; Fmin = FminBin ; @@ -3047,32 +3029,32 @@ u16 MXL_TuneRF(Tuner_struct *Tuner, u32 RF_Freq) // Equation E3 // RFSYN_VCO_BIAS - E3 = (((Fmax-Tuner->RF_LO)/1000)*32)/((Fmax-Fmin)/1000) + 8 ; - status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, E3) ; + E3 = (((Fmax-state->RF_LO)/1000)*32)/((Fmax-Fmin)/1000) + 8 ; + status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, E3) ; // Equation E4 // CHCAL_INT_MOD_RF - E4 = (Tuner->RF_LO*divider_val/1000)/(2*Tuner->Fxtal*Kdbl_RF/1000) ; - MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, E4) ; + E4 = (state->RF_LO*divider_val/1000)/(2*state->Fxtal*Kdbl_RF/1000) ; + MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, E4) ; // Equation E5 // CHCAL_FRAC_MOD_RF // CHCAL_EN_INT_RF - E5 = ((2<<17)*(Tuner->RF_LO/10000*divider_val - (E4*(2*Tuner->Fxtal*Kdbl_RF)/10000)))/(2*Tuner->Fxtal*Kdbl_RF/10000) ; - status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_RF, E5) ; + E5 = ((2<<17)*(state->RF_LO/10000*divider_val - (E4*(2*state->Fxtal*Kdbl_RF)/10000)))/(2*state->Fxtal*Kdbl_RF/10000) ; + status += MXL_ControlWrite(fe, CHCAL_FRAC_MOD_RF, E5) ; // Equation E5A // RFSYN_LPF_R - E5A = (((Fmax - Tuner->RF_LO)/1000)*4/((Fmax-Fmin)/1000)) + 1 ; - status += MXL_ControlWrite(Tuner, RFSYN_LPF_R, E5A) ; + E5A = (((Fmax - state->RF_LO)/1000)*4/((Fmax-Fmin)/1000)) + 1 ; + status += MXL_ControlWrite(fe, RFSYN_LPF_R, E5A) ; // Euqation E5B // CHCAL_EN_INIT_RF - status += MXL_ControlWrite(Tuner, CHCAL_EN_INT_RF, ((E5 == 0) ? 1 : 0)); + status += MXL_ControlWrite(fe, CHCAL_EN_INT_RF, ((E5 == 0) ? 1 : 0)); //if (E5 == 0) - // status += MXL_ControlWrite(Tuner, CHCAL_EN_INT_RF, 1); + // status += MXL_ControlWrite(fe, CHCAL_EN_INT_RF, 1); //else - // status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_RF, E5) ; + // status += MXL_ControlWrite(fe, CHCAL_FRAC_MOD_RF, E5) ; // // Set TG Synth @@ -3082,98 +3064,98 @@ u16 MXL_TuneRF(Tuner_struct *Tuner, u32 RF_Freq) // TG_LO_SELVAL // // Set divider_val, Fmax, Fmix to use in Equations - if (Tuner->TG_LO < 33000000UL) { + if (state->TG_LO < 33000000UL) { return -1; } FminBin = 33000000UL ; FmaxBin = 50000000UL ; - if (Tuner->TG_LO >= FminBin && Tuner->TG_LO <= FmaxBin) { - status += MXL_ControlWrite(Tuner, TG_LO_DIVVAL, 0x6) ; - status += MXL_ControlWrite(Tuner, TG_LO_SELVAL, 0x0) ; + if (state->TG_LO >= FminBin && state->TG_LO <= FmaxBin) { + status += MXL_ControlWrite(fe, TG_LO_DIVVAL, 0x6) ; + status += MXL_ControlWrite(fe, TG_LO_SELVAL, 0x0) ; divider_val = 36 ; Fmax = FmaxBin ; Fmin = FminBin ; } FminBin = 50000000UL ; FmaxBin = 67000000UL ; - if (Tuner->TG_LO > FminBin && Tuner->TG_LO <= FmaxBin) { - status += MXL_ControlWrite(Tuner, TG_LO_DIVVAL, 0x1) ; - status += MXL_ControlWrite(Tuner, TG_LO_SELVAL, 0x0) ; + if (state->TG_LO > FminBin && state->TG_LO <= FmaxBin) { + status += MXL_ControlWrite(fe, TG_LO_DIVVAL, 0x1) ; + status += MXL_ControlWrite(fe, TG_LO_SELVAL, 0x0) ; divider_val = 24 ; Fmax = FmaxBin ; Fmin = FminBin ; } FminBin = 67000000UL ; FmaxBin = 100000000UL ; - if (Tuner->TG_LO > FminBin && Tuner->TG_LO <= FmaxBin) { - status += MXL_ControlWrite(Tuner, TG_LO_DIVVAL, 0xC) ; - status += MXL_ControlWrite(Tuner, TG_LO_SELVAL, 0x2) ; + if (state->TG_LO > FminBin && state->TG_LO <= FmaxBin) { + status += MXL_ControlWrite(fe, TG_LO_DIVVAL, 0xC) ; + status += MXL_ControlWrite(fe, TG_LO_SELVAL, 0x2) ; divider_val = 18 ; Fmax = FmaxBin ; Fmin = FminBin ; } FminBin = 100000000UL ; FmaxBin = 150000000UL ; - if (Tuner->TG_LO > FminBin && Tuner->TG_LO <= FmaxBin) { - status += MXL_ControlWrite(Tuner, TG_LO_DIVVAL, 0x8) ; - status += MXL_ControlWrite(Tuner, TG_LO_SELVAL, 0x2) ; + if (state->TG_LO > FminBin && state->TG_LO <= FmaxBin) { + status += MXL_ControlWrite(fe, TG_LO_DIVVAL, 0x8) ; + status += MXL_ControlWrite(fe, TG_LO_SELVAL, 0x2) ; divider_val = 12 ; Fmax = FmaxBin ; Fmin = FminBin ; } FminBin = 150000000UL ; FmaxBin = 200000000UL ; - if (Tuner->TG_LO > FminBin && Tuner->TG_LO <= FmaxBin) { - status += MXL_ControlWrite(Tuner, TG_LO_DIVVAL, 0x0) ; - status += MXL_ControlWrite(Tuner, TG_LO_SELVAL, 0x2) ; + if (state->TG_LO > FminBin && state->TG_LO <= FmaxBin) { + status += MXL_ControlWrite(fe, TG_LO_DIVVAL, 0x0) ; + status += MXL_ControlWrite(fe, TG_LO_SELVAL, 0x2) ; divider_val = 8 ; Fmax = FmaxBin ; Fmin = FminBin ; } FminBin = 200000000UL ; FmaxBin = 300000000UL ; - if (Tuner->TG_LO > FminBin && Tuner->TG_LO <= FmaxBin) { - status += MXL_ControlWrite(Tuner, TG_LO_DIVVAL, 0x8) ; - status += MXL_ControlWrite(Tuner, TG_LO_SELVAL, 0x3) ; + if (state->TG_LO > FminBin && state->TG_LO <= FmaxBin) { + status += MXL_ControlWrite(fe, TG_LO_DIVVAL, 0x8) ; + status += MXL_ControlWrite(fe, TG_LO_SELVAL, 0x3) ; divider_val = 6 ; Fmax = FmaxBin ; Fmin = FminBin ; } FminBin = 300000000UL ; FmaxBin = 400000000UL ; - if (Tuner->TG_LO > FminBin && Tuner->TG_LO <= FmaxBin) { - status += MXL_ControlWrite(Tuner, TG_LO_DIVVAL, 0x0) ; - status += MXL_ControlWrite(Tuner, TG_LO_SELVAL, 0x3) ; + if (state->TG_LO > FminBin && state->TG_LO <= FmaxBin) { + status += MXL_ControlWrite(fe, TG_LO_DIVVAL, 0x0) ; + status += MXL_ControlWrite(fe, TG_LO_SELVAL, 0x3) ; divider_val = 4 ; Fmax = FmaxBin ; Fmin = FminBin ; } FminBin = 400000000UL ; FmaxBin = 600000000UL ; - if (Tuner->TG_LO > FminBin && Tuner->TG_LO <= FmaxBin) { - status += MXL_ControlWrite(Tuner, TG_LO_DIVVAL, 0x8) ; - status += MXL_ControlWrite(Tuner, TG_LO_SELVAL, 0x7) ; + if (state->TG_LO > FminBin && state->TG_LO <= FmaxBin) { + status += MXL_ControlWrite(fe, TG_LO_DIVVAL, 0x8) ; + status += MXL_ControlWrite(fe, TG_LO_SELVAL, 0x7) ; divider_val = 3 ; Fmax = FmaxBin ; Fmin = FminBin ; } FminBin = 600000000UL ; FmaxBin = 900000000UL ; - if (Tuner->TG_LO > FminBin && Tuner->TG_LO <= FmaxBin) { - status += MXL_ControlWrite(Tuner, TG_LO_DIVVAL, 0x0) ; - status += MXL_ControlWrite(Tuner, TG_LO_SELVAL, 0x7) ; + if (state->TG_LO > FminBin && state->TG_LO <= FmaxBin) { + status += MXL_ControlWrite(fe, TG_LO_DIVVAL, 0x0) ; + status += MXL_ControlWrite(fe, TG_LO_SELVAL, 0x7) ; divider_val = 2 ; Fmax = FmaxBin ; Fmin = FminBin ; } // TG_DIV_VAL - tg_divval = (Tuner->TG_LO*divider_val/100000) - *(MXL_Ceiling(Tuner->Fxtal,1000000) * 100) / (Tuner->Fxtal/1000) ; - status += MXL_ControlWrite(Tuner, TG_DIV_VAL, tg_divval) ; + tg_divval = (state->TG_LO*divider_val/100000) + *(MXL_Ceiling(state->Fxtal,1000000) * 100) / (state->Fxtal/1000) ; + status += MXL_ControlWrite(fe, TG_DIV_VAL, tg_divval) ; - if (Tuner->TG_LO > 600000000UL) - status += MXL_ControlWrite(Tuner, TG_DIV_VAL, tg_divval + 1 ) ; + if (state->TG_LO > 600000000UL) + status += MXL_ControlWrite(fe, TG_DIV_VAL, tg_divval + 1 ) ; Fmax = 1800000000UL ; Fmin = 1200000000UL ; @@ -3181,28 +3163,28 @@ u16 MXL_TuneRF(Tuner_struct *Tuner, u32 RF_Freq) // to prevent overflow of 32 bit unsigned integer, use following equation. Edit for v2.6.4 - Fref_TG = (Tuner->Fxtal/1000)/ MXL_Ceiling(Tuner->Fxtal, 1000000) ; // Fref_TF = Fref_TG*1000 + Fref_TG = (state->Fxtal/1000)/ MXL_Ceiling(state->Fxtal, 1000000) ; // Fref_TF = Fref_TG*1000 - Fvco = (Tuner->TG_LO/10000) * divider_val * Fref_TG; //Fvco = Fvco/10 + Fvco = (state->TG_LO/10000) * divider_val * Fref_TG; //Fvco = Fvco/10 tg_lo = (((Fmax/10 - Fvco)/100)*32) / ((Fmax-Fmin)/1000)+8; //below equation is same as above but much harder to debug. - //tg_lo = ( ((Fmax/10000 * Xtal_Int)/100) - ((Tuner->TG_LO/10000)*divider_val*(Tuner->Fxtal/10000)/100) )*32/((Fmax-Fmin)/10000 * Xtal_Int/100) + 8 ; + //tg_lo = ( ((Fmax/10000 * Xtal_Int)/100) - ((state->TG_LO/10000)*divider_val*(state->Fxtal/10000)/100) )*32/((Fmax-Fmin)/10000 * Xtal_Int/100) + 8 ; - status += MXL_ControlWrite(Tuner, TG_VCO_BIAS , tg_lo) ; + status += MXL_ControlWrite(fe, TG_VCO_BIAS , tg_lo) ; //add for 2.6.5 //Special setting for QAM - if(Tuner ->Mod_Type == MXL_QAM) + if(state->Mod_Type == MXL_QAM) { - if(Tuner->RF_IN < 680000000) - status += MXL_ControlWrite(Tuner, RFSYN_CHP_GAIN, 3) ; + if(state->RF_IN < 680000000) + status += MXL_ControlWrite(fe, RFSYN_CHP_GAIN, 3) ; else - status += MXL_ControlWrite(Tuner, RFSYN_CHP_GAIN, 2) ; + status += MXL_ControlWrite(fe, RFSYN_CHP_GAIN, 2) ; } @@ -3213,673 +3195,675 @@ u16 MXL_TuneRF(Tuner_struct *Tuner, u32 RF_Freq) // if (Tuner->TF_Type == MXL_TF_OFF) // Tracking Filter Off State; turn off all the banks { - status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 0) ; - status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; + status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0) ; + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; - status += MXL_SetGPIO(Tuner, 3, 1) ; // turn off Bank 1 - status += MXL_SetGPIO(Tuner, 1, 1) ; // turn off Bank 2 - status += MXL_SetGPIO(Tuner, 4, 1) ; // turn off Bank 3 + status += MXL_SetGPIO(fe, 3, 1) ; // turn off Bank 1 + status += MXL_SetGPIO(fe, 1, 1) ; // turn off Bank 2 + status += MXL_SetGPIO(fe, 4, 1) ; // turn off Bank 3 } if (Tuner->TF_Type == MXL_TF_C) // Tracking Filter type C { - status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 1) ; - status += MXL_ControlWrite(Tuner, DAC_DIN_A, 0) ; + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1) ; + status += MXL_ControlWrite(fe, DAC_DIN_A, 0) ; - if (Tuner->RF_IN >= 43000000 && Tuner->RF_IN < 150000000) + if (state->RF_IN >= 43000000 && state->RF_IN < 150000000) { - status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 0) ; // Bank4 Off - status += MXL_ControlWrite(Tuner, DAC_DIN_B, 0) ; - status += MXL_SetGPIO(Tuner, 3, 0) ; // Bank1 On - status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off - status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank3 Off + status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0) ; // Bank4 Off + status += MXL_ControlWrite(fe, DAC_DIN_B, 0) ; + status += MXL_SetGPIO(fe, 3, 0) ; // Bank1 On + status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off + status += MXL_SetGPIO(fe, 4, 1) ; // Bank3 Off } - if (Tuner->RF_IN >= 150000000 && Tuner->RF_IN < 280000000) + if (state->RF_IN >= 150000000 && state->RF_IN < 280000000) { - status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 0) ; // Bank4 Off - status += MXL_ControlWrite(Tuner, DAC_DIN_B, 0) ; - status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank1 Off - status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank2 On - status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank3 Off + status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0) ; // Bank4 Off + status += MXL_ControlWrite(fe, DAC_DIN_B, 0) ; + status += MXL_SetGPIO(fe, 3, 1) ; // Bank1 Off + status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On + status += MXL_SetGPIO(fe, 4, 1) ; // Bank3 Off } - if (Tuner->RF_IN >= 280000000 && Tuner->RF_IN < 360000000) + if (state->RF_IN >= 280000000 && state->RF_IN < 360000000) { - status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 0) ; // Bank4 Off - status += MXL_ControlWrite(Tuner, DAC_DIN_B, 0) ; - status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank1 Off - status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank2 On - status += MXL_SetGPIO(Tuner, 4, 0) ; // Bank3 On + status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0) ; // Bank4 Off + status += MXL_ControlWrite(fe, DAC_DIN_B, 0) ; + status += MXL_SetGPIO(fe, 3, 1) ; // Bank1 Off + status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On + status += MXL_SetGPIO(fe, 4, 0) ; // Bank3 On } - if (Tuner->RF_IN >= 360000000 && Tuner->RF_IN < 560000000) + if (state->RF_IN >= 360000000 && state->RF_IN < 560000000) { - status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 0) ; // Bank4 Off - status += MXL_ControlWrite(Tuner, DAC_DIN_B, 0) ; - status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank1 Off - status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off - status += MXL_SetGPIO(Tuner, 4, 0) ; // Bank3 On + status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0) ; // Bank4 Off + status += MXL_ControlWrite(fe, DAC_DIN_B, 0) ; + status += MXL_SetGPIO(fe, 3, 1) ; // Bank1 Off + status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off + status += MXL_SetGPIO(fe, 4, 0) ; // Bank3 On } - if (Tuner->RF_IN >= 560000000 && Tuner->RF_IN < 580000000) + if (state->RF_IN >= 560000000 && state->RF_IN < 580000000) { - status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 1) ; // Bank4 On - status += MXL_ControlWrite(Tuner, DAC_DIN_B, 29) ; - status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank1 Off - status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off - status += MXL_SetGPIO(Tuner, 4, 0) ; // Bank3 On + status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1) ; // Bank4 On + status += MXL_ControlWrite(fe, DAC_DIN_B, 29) ; + status += MXL_SetGPIO(fe, 3, 1) ; // Bank1 Off + status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off + status += MXL_SetGPIO(fe, 4, 0) ; // Bank3 On } - if (Tuner->RF_IN >= 580000000 && Tuner->RF_IN < 630000000) + if (state->RF_IN >= 580000000 && state->RF_IN < 630000000) { - status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 1) ; // Bank4 On - status += MXL_ControlWrite(Tuner, DAC_DIN_B, 0) ; - status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank1 Off - status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off - status += MXL_SetGPIO(Tuner, 4, 0) ; // Bank3 On + status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1) ; // Bank4 On + status += MXL_ControlWrite(fe, DAC_DIN_B, 0) ; + status += MXL_SetGPIO(fe, 3, 1) ; // Bank1 Off + status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off + status += MXL_SetGPIO(fe, 4, 0) ; // Bank3 On } - if (Tuner->RF_IN >= 630000000 && Tuner->RF_IN < 700000000) + if (state->RF_IN >= 630000000 && state->RF_IN < 700000000) { - status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 1) ; // Bank4 On - status += MXL_ControlWrite(Tuner, DAC_DIN_B, 16) ; - status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank1 Off - status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off - status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank3 Off + status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1) ; // Bank4 On + status += MXL_ControlWrite(fe, DAC_DIN_B, 16) ; + status += MXL_SetGPIO(fe, 3, 1) ; // Bank1 Off + status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off + status += MXL_SetGPIO(fe, 4, 1) ; // Bank3 Off } - if (Tuner->RF_IN >= 700000000 && Tuner->RF_IN < 760000000) + if (state->RF_IN >= 700000000 && state->RF_IN < 760000000) { - status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 1) ; // Bank4 On - status += MXL_ControlWrite(Tuner, DAC_DIN_B, 7) ; - status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank1 Off - status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off - status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank3 Off + status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1) ; // Bank4 On + status += MXL_ControlWrite(fe, DAC_DIN_B, 7) ; + status += MXL_SetGPIO(fe, 3, 1) ; // Bank1 Off + status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off + status += MXL_SetGPIO(fe, 4, 1) ; // Bank3 Off } - if (Tuner->RF_IN >= 760000000 && Tuner->RF_IN <= 900000000) + if (state->RF_IN >= 760000000 && state->RF_IN <= 900000000) { - status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 1) ; // Bank4 On - status += MXL_ControlWrite(Tuner, DAC_DIN_B, 0) ; - status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank1 Off - status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off - status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank3 Off + status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1) ; // Bank4 On + status += MXL_ControlWrite(fe, DAC_DIN_B, 0) ; + status += MXL_SetGPIO(fe, 3, 1) ; // Bank1 Off + status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off + status += MXL_SetGPIO(fe, 4, 1) ; // Bank3 Off } } if (Tuner->TF_Type == MXL_TF_C_H) // Tracking Filter type C-H for Hauppauge only { - status += MXL_ControlWrite(Tuner, DAC_DIN_A, 0) ; + status += MXL_ControlWrite(fe, DAC_DIN_A, 0) ; - if (Tuner->RF_IN >= 43000000 && Tuner->RF_IN < 150000000) + if (state->RF_IN >= 43000000 && state->RF_IN < 150000000) { - status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 0) ; // Bank4 Off - status += MXL_SetGPIO(Tuner, 4, 0) ; // Bank1 On - status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank2 Off - status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank3 Off + status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0) ; // Bank4 Off + status += MXL_SetGPIO(fe, 4, 0) ; // Bank1 On + status += MXL_SetGPIO(fe, 3, 1) ; // Bank2 Off + status += MXL_SetGPIO(fe, 1, 1) ; // Bank3 Off } - if (Tuner->RF_IN >= 150000000 && Tuner->RF_IN < 280000000) + if (state->RF_IN >= 150000000 && state->RF_IN < 280000000) { - status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 0) ; // Bank4 Off - status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(Tuner, 3, 0) ; // Bank2 On - status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank3 Off + status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0) ; // Bank4 Off + status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(fe, 3, 0) ; // Bank2 On + status += MXL_SetGPIO(fe, 1, 1) ; // Bank3 Off } - if (Tuner->RF_IN >= 280000000 && Tuner->RF_IN < 360000000) + if (state->RF_IN >= 280000000 && state->RF_IN < 360000000) { - status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 0) ; // Bank4 Off - status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(Tuner, 3, 0) ; // Bank2 On - status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank3 On + status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0) ; // Bank4 Off + status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(fe, 3, 0) ; // Bank2 On + status += MXL_SetGPIO(fe, 1, 0) ; // Bank3 On } - if (Tuner->RF_IN >= 360000000 && Tuner->RF_IN < 560000000) + if (state->RF_IN >= 360000000 && state->RF_IN < 560000000) { - status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 0) ; // Bank4 Off - status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank2 Off - status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank3 On + status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0) ; // Bank4 Off + status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(fe, 3, 1) ; // Bank2 Off + status += MXL_SetGPIO(fe, 1, 0) ; // Bank3 On } - if (Tuner->RF_IN >= 560000000 && Tuner->RF_IN < 580000000) + if (state->RF_IN >= 560000000 && state->RF_IN < 580000000) { - status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 1) ; // Bank4 On - status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank2 Off - status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank3 On + status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1) ; // Bank4 On + status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(fe, 3, 1) ; // Bank2 Off + status += MXL_SetGPIO(fe, 1, 0) ; // Bank3 On } - if (Tuner->RF_IN >= 580000000 && Tuner->RF_IN < 630000000) + if (state->RF_IN >= 580000000 && state->RF_IN < 630000000) { - status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 1) ; // Bank4 On - status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank2 Off - status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank3 On + status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1) ; // Bank4 On + status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(fe, 3, 1) ; // Bank2 Off + status += MXL_SetGPIO(fe, 1, 0) ; // Bank3 On } - if (Tuner->RF_IN >= 630000000 && Tuner->RF_IN < 700000000) + if (state->RF_IN >= 630000000 && state->RF_IN < 700000000) { - status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 1) ; // Bank4 On - status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank2 Off - status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank3 Off + status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1) ; // Bank4 On + status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(fe, 3, 1) ; // Bank2 Off + status += MXL_SetGPIO(fe, 1, 1) ; // Bank3 Off } - if (Tuner->RF_IN >= 700000000 && Tuner->RF_IN < 760000000) + if (state->RF_IN >= 700000000 && state->RF_IN < 760000000) { - status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 1) ; // Bank4 On - status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank2 Off - status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank3 Off + status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1) ; // Bank4 On + status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(fe, 3, 1) ; // Bank2 Off + status += MXL_SetGPIO(fe, 1, 1) ; // Bank3 Off } - if (Tuner->RF_IN >= 760000000 && Tuner->RF_IN <= 900000000) + if (state->RF_IN >= 760000000 && state->RF_IN <= 900000000) { - status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 1) ; // Bank4 On - status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank2 Off - status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank3 Off + status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1) ; // Bank4 On + status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(fe, 3, 1) ; // Bank2 Off + status += MXL_SetGPIO(fe, 1, 1) ; // Bank3 Off } } if (Tuner->TF_Type == MXL_TF_D) // Tracking Filter type D { - status += MXL_ControlWrite(Tuner, DAC_DIN_B, 0) ; + status += MXL_ControlWrite(fe, DAC_DIN_B, 0) ; - if (Tuner->RF_IN >= 43000000 && Tuner->RF_IN < 174000000) + if (state->RF_IN >= 43000000 && state->RF_IN < 174000000) { - status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off - status += MXL_SetGPIO(Tuner, 4, 0) ; // Bank1 On - status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off - status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off + status += MXL_SetGPIO(fe, 4, 0) ; // Bank1 On + status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off + status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off } - if (Tuner->RF_IN >= 174000000 && Tuner->RF_IN < 250000000) + if (state->RF_IN >= 174000000 && state->RF_IN < 250000000) { - status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off - status += MXL_SetGPIO(Tuner, 4, 0) ; // Bank1 On - status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank2 On - status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off + status += MXL_SetGPIO(fe, 4, 0) ; // Bank1 On + status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On + status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off } - if (Tuner->RF_IN >= 250000000 && Tuner->RF_IN < 310000000) + if (state->RF_IN >= 250000000 && state->RF_IN < 310000000) { - status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off - status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank2 On - status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off + status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On + status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off } - if (Tuner->RF_IN >= 310000000 && Tuner->RF_IN < 360000000) + if (state->RF_IN >= 310000000 && state->RF_IN < 360000000) { - status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off - status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank2 On - status += MXL_SetGPIO(Tuner, 3, 0) ; // Bank3 On + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off + status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On + status += MXL_SetGPIO(fe, 3, 0) ; // Bank3 On } - if (Tuner->RF_IN >= 360000000 && Tuner->RF_IN < 470000000) + if (state->RF_IN >= 360000000 && state->RF_IN < 470000000) { - status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off - status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off - status += MXL_SetGPIO(Tuner, 3, 0) ; // Bank3 On + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off + status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off + status += MXL_SetGPIO(fe, 3, 0) ; // Bank3 On } - if (Tuner->RF_IN >= 470000000 && Tuner->RF_IN < 640000000) + if (state->RF_IN >= 470000000 && state->RF_IN < 640000000) { - status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 1) ; // Bank4 On - status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off - status += MXL_SetGPIO(Tuner, 3, 0) ; // Bank3 On + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1) ; // Bank4 On + status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off + status += MXL_SetGPIO(fe, 3, 0) ; // Bank3 On } - if (Tuner->RF_IN >= 640000000 && Tuner->RF_IN <= 900000000) + if (state->RF_IN >= 640000000 && state->RF_IN <= 900000000) { - status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 1) ; // Bank4 On - status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off - status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1) ; // Bank4 On + status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off + status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off } } if (Tuner->TF_Type == MXL_TF_D_L) // Tracking Filter type D-L for Lumanate ONLY change for 2.6.3 { - status += MXL_ControlWrite(Tuner, DAC_DIN_A, 0) ; + status += MXL_ControlWrite(fe, DAC_DIN_A, 0) ; // if UHF and terrestrial => Turn off Tracking Filter - if (Tuner->RF_IN >= 471000000 && (Tuner->RF_IN - 471000000)%6000000 != 0) + if (state->RF_IN >= 471000000 && (state->RF_IN - 471000000)%6000000 != 0) { // Turn off all the banks - status += MXL_SetGPIO(Tuner, 3, 1) ; - status += MXL_SetGPIO(Tuner, 1, 1) ; - status += MXL_SetGPIO(Tuner, 4, 1) ; - status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 0) ; + status += MXL_SetGPIO(fe, 3, 1) ; + status += MXL_SetGPIO(fe, 1, 1) ; + status += MXL_SetGPIO(fe, 4, 1) ; + status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0) ; - status += MXL_ControlWrite(Tuner, AGC_IF, 10) ; + status += MXL_ControlWrite(fe, AGC_IF, 10) ; } else // if VHF or cable => Turn on Tracking Filter { - if (Tuner->RF_IN >= 43000000 && Tuner->RF_IN < 140000000) + if (state->RF_IN >= 43000000 && state->RF_IN < 140000000) { - status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 0) ; // Bank4 Off - status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 On - status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off - status += MXL_SetGPIO(Tuner, 3, 0) ; // Bank3 Off + status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0) ; // Bank4 Off + status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 On + status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off + status += MXL_SetGPIO(fe, 3, 0) ; // Bank3 Off } - if (Tuner->RF_IN >= 140000000 && Tuner->RF_IN < 240000000) + if (state->RF_IN >= 140000000 && state->RF_IN < 240000000) { - status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 0) ; // Bank4 Off - status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 On - status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank2 On - status += MXL_SetGPIO(Tuner, 3, 0) ; // Bank3 Off + status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0) ; // Bank4 Off + status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 On + status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On + status += MXL_SetGPIO(fe, 3, 0) ; // Bank3 Off } - if (Tuner->RF_IN >= 240000000 && Tuner->RF_IN < 340000000) + if (state->RF_IN >= 240000000 && state->RF_IN < 340000000) { - status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 0) ; // Bank4 Off - status += MXL_SetGPIO(Tuner, 4, 0) ; // Bank1 Off - status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 On - status += MXL_SetGPIO(Tuner, 3, 0) ; // Bank3 Off + status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0) ; // Bank4 Off + status += MXL_SetGPIO(fe, 4, 0) ; // Bank1 Off + status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 On + status += MXL_SetGPIO(fe, 3, 0) ; // Bank3 Off } - if (Tuner->RF_IN >= 340000000 && Tuner->RF_IN < 430000000) + if (state->RF_IN >= 340000000 && state->RF_IN < 430000000) { - status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 0) ; // Bank4 Off - status += MXL_SetGPIO(Tuner, 4, 0) ; // Bank1 Off - status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank2 On - status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 On + status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0) ; // Bank4 Off + status += MXL_SetGPIO(fe, 4, 0) ; // Bank1 Off + status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On + status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 On } - if (Tuner->RF_IN >= 430000000 && Tuner->RF_IN < 470000000) + if (state->RF_IN >= 430000000 && state->RF_IN < 470000000) { - status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 1) ; // Bank4 Off - status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank2 Off - status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 On + status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1) ; // Bank4 Off + status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 Off + status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 On } - if (Tuner->RF_IN >= 470000000 && Tuner->RF_IN < 570000000) + if (state->RF_IN >= 470000000 && state->RF_IN < 570000000) { - status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 1) ; // Bank4 On - status += MXL_SetGPIO(Tuner, 4, 0) ; // Bank1 Off - status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank2 Off - status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 On + status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1) ; // Bank4 On + status += MXL_SetGPIO(fe, 4, 0) ; // Bank1 Off + status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 Off + status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 On } - if (Tuner->RF_IN >= 570000000 && Tuner->RF_IN < 620000000) + if (state->RF_IN >= 570000000 && state->RF_IN < 620000000) { - status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 0) ; // Bank4 On - status += MXL_SetGPIO(Tuner, 4, 0) ; // Bank1 Off - status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off - status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Offq + status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0) ; // Bank4 On + status += MXL_SetGPIO(fe, 4, 0) ; // Bank1 Off + status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off + status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Offq } - if (Tuner->RF_IN >= 620000000 && Tuner->RF_IN < 760000000) + if (state->RF_IN >= 620000000 && state->RF_IN < 760000000) { - status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 1) ; // Bank4 On - status += MXL_SetGPIO(Tuner, 4, 0) ; // Bank1 Off - status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off - status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off + status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1) ; // Bank4 On + status += MXL_SetGPIO(fe, 4, 0) ; // Bank1 Off + status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off + status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off } - if (Tuner->RF_IN >= 760000000 && Tuner->RF_IN <= 900000000) + if (state->RF_IN >= 760000000 && state->RF_IN <= 900000000) { - status += MXL_ControlWrite(Tuner, DAC_A_ENABLE, 1) ; // Bank4 On - status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off - status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off + status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1) ; // Bank4 On + status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off + status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off } } } if (Tuner->TF_Type == MXL_TF_E) // Tracking Filter type E { - status += MXL_ControlWrite(Tuner, DAC_DIN_B, 0) ; + status += MXL_ControlWrite(fe, DAC_DIN_B, 0) ; - if (Tuner->RF_IN >= 43000000 && Tuner->RF_IN < 174000000) + if (state->RF_IN >= 43000000 && state->RF_IN < 174000000) { - status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off - status += MXL_SetGPIO(Tuner, 4, 0) ; // Bank1 On - status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off - status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off + status += MXL_SetGPIO(fe, 4, 0) ; // Bank1 On + status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off + status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off } - if (Tuner->RF_IN >= 174000000 && Tuner->RF_IN < 250000000) + if (state->RF_IN >= 174000000 && state->RF_IN < 250000000) { - status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off - status += MXL_SetGPIO(Tuner, 4, 0) ; // Bank1 On - status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank2 On - status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off + status += MXL_SetGPIO(fe, 4, 0) ; // Bank1 On + status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On + status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off } - if (Tuner->RF_IN >= 250000000 && Tuner->RF_IN < 310000000) + if (state->RF_IN >= 250000000 && state->RF_IN < 310000000) { - status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off - status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank2 On - status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off + status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On + status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off } - if (Tuner->RF_IN >= 310000000 && Tuner->RF_IN < 360000000) + if (state->RF_IN >= 310000000 && state->RF_IN < 360000000) { - status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off - status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank2 On - status += MXL_SetGPIO(Tuner, 3, 0) ; // Bank3 On + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off + status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On + status += MXL_SetGPIO(fe, 3, 0) ; // Bank3 On } - if (Tuner->RF_IN >= 360000000 && Tuner->RF_IN < 470000000) + if (state->RF_IN >= 360000000 && state->RF_IN < 470000000) { - status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off - status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off - status += MXL_SetGPIO(Tuner, 3, 0) ; // Bank3 On + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off + status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off + status += MXL_SetGPIO(fe, 3, 0) ; // Bank3 On } - if (Tuner->RF_IN >= 470000000 && Tuner->RF_IN < 640000000) + if (state->RF_IN >= 470000000 && state->RF_IN < 640000000) { - status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 1) ; // Bank4 On - status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off - status += MXL_SetGPIO(Tuner, 3, 0) ; // Bank3 On + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1) ; // Bank4 On + status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off + status += MXL_SetGPIO(fe, 3, 0) ; // Bank3 On } - if (Tuner->RF_IN >= 640000000 && Tuner->RF_IN <= 900000000) + if (state->RF_IN >= 640000000 && state->RF_IN <= 900000000) { - status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 1) ; // Bank4 On - status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off - status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1) ; // Bank4 On + status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off + status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off } } if (Tuner->TF_Type == MXL_TF_F) // Tracking Filter type F { - status += MXL_ControlWrite(Tuner, DAC_DIN_B, 0) ; + status += MXL_ControlWrite(fe, DAC_DIN_B, 0) ; - if (Tuner->RF_IN >= 43000000 && Tuner->RF_IN < 160000000) + if (state->RF_IN >= 43000000 && state->RF_IN < 160000000) { - status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off - status += MXL_SetGPIO(Tuner, 4, 0) ; // Bank1 On - status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off - status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off + status += MXL_SetGPIO(fe, 4, 0) ; // Bank1 On + status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off + status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off } - if (Tuner->RF_IN >= 160000000 && Tuner->RF_IN < 210000000) + if (state->RF_IN >= 160000000 && state->RF_IN < 210000000) { - status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off - status += MXL_SetGPIO(Tuner, 4, 0) ; // Bank1 On - status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank2 On - status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off + status += MXL_SetGPIO(fe, 4, 0) ; // Bank1 On + status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On + status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off } - if (Tuner->RF_IN >= 210000000 && Tuner->RF_IN < 300000000) + if (state->RF_IN >= 210000000 && state->RF_IN < 300000000) { - status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off - status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank2 On - status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off + status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On + status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off } - if (Tuner->RF_IN >= 300000000 && Tuner->RF_IN < 390000000) + if (state->RF_IN >= 300000000 && state->RF_IN < 390000000) { - status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off - status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank2 On - status += MXL_SetGPIO(Tuner, 3, 0) ; // Bank3 On + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off + status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On + status += MXL_SetGPIO(fe, 3, 0) ; // Bank3 On } - if (Tuner->RF_IN >= 390000000 && Tuner->RF_IN < 515000000) + if (state->RF_IN >= 390000000 && state->RF_IN < 515000000) { - status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off - status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off - status += MXL_SetGPIO(Tuner, 3, 0) ; // Bank3 On + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off + status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off + status += MXL_SetGPIO(fe, 3, 0) ; // Bank3 On } - if (Tuner->RF_IN >= 515000000 && Tuner->RF_IN < 650000000) + if (state->RF_IN >= 515000000 && state->RF_IN < 650000000) { - status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 1) ; // Bank4 On - status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off - status += MXL_SetGPIO(Tuner, 3, 0) ; // Bank3 On + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1) ; // Bank4 On + status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off + status += MXL_SetGPIO(fe, 3, 0) ; // Bank3 On } - if (Tuner->RF_IN >= 650000000 && Tuner->RF_IN <= 900000000) + if (state->RF_IN >= 650000000 && state->RF_IN <= 900000000) { - status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 1) ; // Bank4 On - status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off - status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1) ; // Bank4 On + status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off + status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off } } if (Tuner->TF_Type == MXL_TF_E_2) // Tracking Filter type E_2 { - status += MXL_ControlWrite(Tuner, DAC_DIN_B, 0) ; + status += MXL_ControlWrite(fe, DAC_DIN_B, 0) ; - if (Tuner->RF_IN >= 43000000 && Tuner->RF_IN < 174000000) + if (state->RF_IN >= 43000000 && state->RF_IN < 174000000) { - status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off - status += MXL_SetGPIO(Tuner, 4, 0) ; // Bank1 On - status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off - status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off + status += MXL_SetGPIO(fe, 4, 0) ; // Bank1 On + status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off + status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off } - if (Tuner->RF_IN >= 174000000 && Tuner->RF_IN < 250000000) + if (state->RF_IN >= 174000000 && state->RF_IN < 250000000) { - status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off - status += MXL_SetGPIO(Tuner, 4, 0) ; // Bank1 On - status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank2 On - status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off + status += MXL_SetGPIO(fe, 4, 0) ; // Bank1 On + status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On + status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off } - if (Tuner->RF_IN >= 250000000 && Tuner->RF_IN < 350000000) + if (state->RF_IN >= 250000000 && state->RF_IN < 350000000) { - status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off - status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank2 On - status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off + status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On + status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off } - if (Tuner->RF_IN >= 350000000 && Tuner->RF_IN < 400000000) + if (state->RF_IN >= 350000000 && state->RF_IN < 400000000) { - status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off - status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank2 On - status += MXL_SetGPIO(Tuner, 3, 0) ; // Bank3 On + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off + status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On + status += MXL_SetGPIO(fe, 3, 0) ; // Bank3 On } - if (Tuner->RF_IN >= 400000000 && Tuner->RF_IN < 570000000) + if (state->RF_IN >= 400000000 && state->RF_IN < 570000000) { - status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off - status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off - status += MXL_SetGPIO(Tuner, 3, 0) ; // Bank3 On + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off + status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off + status += MXL_SetGPIO(fe, 3, 0) ; // Bank3 On } - if (Tuner->RF_IN >= 570000000 && Tuner->RF_IN < 770000000) + if (state->RF_IN >= 570000000 && state->RF_IN < 770000000) { - status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 1) ; // Bank4 On - status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off - status += MXL_SetGPIO(Tuner, 3, 0) ; // Bank3 On + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1) ; // Bank4 On + status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off + status += MXL_SetGPIO(fe, 3, 0) ; // Bank3 On } - if (Tuner->RF_IN >= 770000000 && Tuner->RF_IN <= 900000000) + if (state->RF_IN >= 770000000 && state->RF_IN <= 900000000) { - status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 1) ; // Bank4 On - status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off - status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1) ; // Bank4 On + status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off + status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off } } if (Tuner->TF_Type == MXL_TF_G) // Tracking Filter type G add for v2.6.8 { - status += MXL_ControlWrite(Tuner, DAC_DIN_B, 0) ; + status += MXL_ControlWrite(fe, DAC_DIN_B, 0) ; - if (Tuner->RF_IN >= 50000000 && Tuner->RF_IN < 190000000) + if (state->RF_IN >= 50000000 && state->RF_IN < 190000000) { - status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off - status += MXL_SetGPIO(Tuner, 4, 0) ; // Bank1 On - status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off - status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off + status += MXL_SetGPIO(fe, 4, 0) ; // Bank1 On + status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off + status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off } - if (Tuner->RF_IN >= 190000000 && Tuner->RF_IN < 280000000) + if (state->RF_IN >= 190000000 && state->RF_IN < 280000000) { - status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off - status += MXL_SetGPIO(Tuner, 4, 0) ; // Bank1 On - status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank2 On - status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off + status += MXL_SetGPIO(fe, 4, 0) ; // Bank1 On + status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On + status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off } - if (Tuner->RF_IN >= 280000000 && Tuner->RF_IN < 350000000) + if (state->RF_IN >= 280000000 && state->RF_IN < 350000000) { - status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off - status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank2 On - status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off + status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On + status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off } - if (Tuner->RF_IN >= 350000000 && Tuner->RF_IN < 400000000) + if (state->RF_IN >= 350000000 && state->RF_IN < 400000000) { - status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off - status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank2 On - status += MXL_SetGPIO(Tuner, 3, 0) ; // Bank3 On + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off + status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On + status += MXL_SetGPIO(fe, 3, 0) ; // Bank3 On } - if (Tuner->RF_IN >= 400000000 && Tuner->RF_IN < 470000000) //modified for 2.6.11 + if (state->RF_IN >= 400000000 && state->RF_IN < 470000000) //modified for 2.6.11 { - status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 1) ; // Bank4 On - status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 On - status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank2 Off - status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1) ; // Bank4 On + status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 On + status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 Off + status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off } - if (Tuner->RF_IN >= 470000000 && Tuner->RF_IN < 640000000) + if (state->RF_IN >= 470000000 && state->RF_IN < 640000000) { - status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off - status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off - status += MXL_SetGPIO(Tuner, 3, 0) ; // Bank3 On + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off + status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off + status += MXL_SetGPIO(fe, 3, 0) ; // Bank3 On } - if (Tuner->RF_IN >= 640000000 && Tuner->RF_IN < 820000000) + if (state->RF_IN >= 640000000 && state->RF_IN < 820000000) { - status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 1) ; // Bank4 On - status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off - status += MXL_SetGPIO(Tuner, 3, 0) ; // Bank3 On + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1) ; // Bank4 On + status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off + status += MXL_SetGPIO(fe, 3, 0) ; // Bank3 On } - if (Tuner->RF_IN >= 820000000 && Tuner->RF_IN <= 900000000) + if (state->RF_IN >= 820000000 && state->RF_IN <= 900000000) { - status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 1) ; // Bank4 On - status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off - status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1) ; // Bank4 On + status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off + status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off } } if (Tuner->TF_Type == MXL_TF_E_NA) // Tracking Filter type E-NA for Empia ONLY change for 2.6.8 { - status += MXL_ControlWrite(Tuner, DAC_DIN_B, 0) ; + status += MXL_ControlWrite(fe, DAC_DIN_B, 0) ; // if UHF and terrestrial=> Turn off Tracking Filter - if (Tuner->RF_IN >= 471000000 && (Tuner->RF_IN - 471000000)%6000000 != 0) + if (state->RF_IN >= 471000000 && (state->RF_IN - 471000000)%6000000 != 0) { // Turn off all the banks - status += MXL_SetGPIO(Tuner, 3, 1) ; - status += MXL_SetGPIO(Tuner, 1, 1) ; - status += MXL_SetGPIO(Tuner, 4, 1) ; - status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; + status += MXL_SetGPIO(fe, 3, 1) ; + status += MXL_SetGPIO(fe, 1, 1) ; + status += MXL_SetGPIO(fe, 4, 1) ; + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; //2.6.12 //Turn on RSSI - status += MXL_ControlWrite(Tuner, SEQ_EXTSYNTHCALIF, 1) ; - status += MXL_ControlWrite(Tuner, SEQ_EXTDCCAL, 1) ; - status += MXL_ControlWrite(Tuner, AGC_EN_RSSI, 1) ; - status += MXL_ControlWrite(Tuner, RFA_ENCLKRFAGC, 1) ; + status += MXL_ControlWrite(fe, SEQ_EXTSYNTHCALIF, 1) ; + status += MXL_ControlWrite(fe, SEQ_EXTDCCAL, 1) ; + status += MXL_ControlWrite(fe, AGC_EN_RSSI, 1) ; + status += MXL_ControlWrite(fe, RFA_ENCLKRFAGC, 1) ; // RSSI reference point - status += MXL_ControlWrite(Tuner, RFA_RSSI_REFH, 5) ; - status += MXL_ControlWrite(Tuner, RFA_RSSI_REF, 3) ; - status += MXL_ControlWrite(Tuner, RFA_RSSI_REFL, 2) ; + status += MXL_ControlWrite(fe, RFA_RSSI_REFH, 5) ; + status += MXL_ControlWrite(fe, RFA_RSSI_REF, 3) ; + status += MXL_ControlWrite(fe, RFA_RSSI_REFL, 2) ; - //status += MXL_ControlWrite(Tuner, AGC_IF, 10) ; //doesn't matter since RSSI is turn on + //status += MXL_ControlWrite(fe, AGC_IF, 10) ; //doesn't matter since RSSI is turn on //following parameter is from analog OTA mode, can be change to seek better performance - status += MXL_ControlWrite(Tuner, RFSYN_CHP_GAIN, 3) ; + status += MXL_ControlWrite(fe, RFSYN_CHP_GAIN, 3) ; } else //if VHF or Cable => Turn on Tracking Filter { //2.6.12 //Turn off RSSI - status += MXL_ControlWrite(Tuner, AGC_EN_RSSI, 0) ; + status += MXL_ControlWrite(fe, AGC_EN_RSSI, 0) ; //change back from above condition - status += MXL_ControlWrite(Tuner, RFSYN_CHP_GAIN, 5) ; + status += MXL_ControlWrite(fe, RFSYN_CHP_GAIN, 5) ; - if (Tuner->RF_IN >= 43000000 && Tuner->RF_IN < 174000000) + if (state->RF_IN >= 43000000 && state->RF_IN < 174000000) { - status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off - status += MXL_SetGPIO(Tuner, 4, 0) ; // Bank1 On - status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off - status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off + status += MXL_SetGPIO(fe, 4, 0) ; // Bank1 On + status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off + status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off } - if (Tuner->RF_IN >= 174000000 && Tuner->RF_IN < 250000000) + if (state->RF_IN >= 174000000 && state->RF_IN < 250000000) { - status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off - status += MXL_SetGPIO(Tuner, 4, 0) ; // Bank1 On - status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank2 On - status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off + status += MXL_SetGPIO(fe, 4, 0) ; // Bank1 On + status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On + status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off } - if (Tuner->RF_IN >= 250000000 && Tuner->RF_IN < 350000000) + if (state->RF_IN >= 250000000 && state->RF_IN < 350000000) { - status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off - status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank2 On - status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off + status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On + status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off } - if (Tuner->RF_IN >= 350000000 && Tuner->RF_IN < 400000000) + if (state->RF_IN >= 350000000 && state->RF_IN < 400000000) { - status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off - status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(Tuner, 1, 0) ; // Bank2 On - status += MXL_SetGPIO(Tuner, 3, 0) ; // Bank3 On + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off + status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On + status += MXL_SetGPIO(fe, 3, 0) ; // Bank3 On } - if (Tuner->RF_IN >= 400000000 && Tuner->RF_IN < 570000000) + if (state->RF_IN >= 400000000 && state->RF_IN < 570000000) { - status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 0) ; // Bank4 Off - status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off - status += MXL_SetGPIO(Tuner, 3, 0) ; // Bank3 On + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off + status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off + status += MXL_SetGPIO(fe, 3, 0) ; // Bank3 On } - if (Tuner->RF_IN >= 570000000 && Tuner->RF_IN < 770000000) + if (state->RF_IN >= 570000000 && state->RF_IN < 770000000) { - status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 1) ; // Bank4 On - status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off - status += MXL_SetGPIO(Tuner, 3, 0) ; // Bank3 On + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1) ; // Bank4 On + status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off + status += MXL_SetGPIO(fe, 3, 0) ; // Bank3 On } - if (Tuner->RF_IN >= 770000000 && Tuner->RF_IN <= 900000000) + if (state->RF_IN >= 770000000 && state->RF_IN <= 900000000) { - status += MXL_ControlWrite(Tuner, DAC_B_ENABLE, 1) ; // Bank4 On - status += MXL_SetGPIO(Tuner, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(Tuner, 1, 1) ; // Bank2 Off - status += MXL_SetGPIO(Tuner, 3, 1) ; // Bank3 Off + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1) ; // Bank4 On + status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off + status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off + status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off } } } return status ; } -u16 MXL_SetGPIO(Tuner_struct *Tuner, u8 GPIO_Num, u8 GPIO_Val) +// DONE +u16 MXL_SetGPIO(struct dvb_frontend *fe, u8 GPIO_Num, u8 GPIO_Val) { - u16 status = 0 ; + struct mxl5005s_state *state = fe->demodulator_priv; + u16 status = 0; if (GPIO_Num == 1) - status += MXL_ControlWrite(Tuner, GPIO_1B, GPIO_Val ? 0 : 1) ; - // GPIO2 is not available - if (GPIO_Num == 3) - { + status += MXL_ControlWrite(fe, GPIO_1B, GPIO_Val ? 0 : 1); + + /* GPIO2 is not available */ + + if (GPIO_Num == 3) { if (GPIO_Val == 1) { - status += MXL_ControlWrite(Tuner, GPIO_3, 0) ; - status += MXL_ControlWrite(Tuner, GPIO_3B, 0) ; + status += MXL_ControlWrite(fe, GPIO_3, 0); + status += MXL_ControlWrite(fe, GPIO_3B, 0); } if (GPIO_Val == 0) { - status += MXL_ControlWrite(Tuner, GPIO_3, 1) ; - status += MXL_ControlWrite(Tuner, GPIO_3B, 1) ; + status += MXL_ControlWrite(fe, GPIO_3, 1); + status += MXL_ControlWrite(fe, GPIO_3B, 1); } - if (GPIO_Val == 3) { // tri-state - status += MXL_ControlWrite(Tuner, GPIO_3, 0) ; - status += MXL_ControlWrite(Tuner, GPIO_3B, 1) ; + if (GPIO_Val == 3) { /* tri-state */ + status += MXL_ControlWrite(fe, GPIO_3, 0); + status += MXL_ControlWrite(fe, GPIO_3B, 1); } } - if (GPIO_Num == 4) - { + if (GPIO_Num == 4) { if (GPIO_Val == 1) { - status += MXL_ControlWrite(Tuner, GPIO_4, 0) ; - status += MXL_ControlWrite(Tuner, GPIO_4B, 0) ; + status += MXL_ControlWrite(fe, GPIO_4, 0); + status += MXL_ControlWrite(fe, GPIO_4B, 0); } if (GPIO_Val == 0) { - status += MXL_ControlWrite(Tuner, GPIO_4, 1) ; - status += MXL_ControlWrite(Tuner, GPIO_4B, 1) ; + status += MXL_ControlWrite(fe, GPIO_4, 1); + status += MXL_ControlWrite(fe, GPIO_4B, 1); } - if (GPIO_Val == 3) { // tri-state - status += MXL_ControlWrite(Tuner, GPIO_4, 0) ; - status += MXL_ControlWrite(Tuner, GPIO_4B, 1) ; + if (GPIO_Val == 3) { /* tri-state */ + status += MXL_ControlWrite(fe, GPIO_4, 0); + status += MXL_ControlWrite(fe, GPIO_4B, 1); } } - return status ; + return status; } /////////////////////////////////////////////////////////////////////////////// @@ -3907,17 +3891,19 @@ u16 MXL_SetGPIO(Tuner_struct *Tuner, u8 GPIO_Num, u8 GPIO_Val) // >0 : Value exceed maximum allowed for control number // // // /////////////////////////////////////////////////////////////////////////////// -u16 MXL_ControlWrite(Tuner_struct *Tuner, u16 ControlNum, u32 value) +// DONE +u16 MXL_ControlWrite(struct dvb_frontend *fe, u16 ControlNum, u32 value) { - u16 status = 0 ; - // Will write ALL Matching Control Name - status += MXL_ControlWrite_Group( Tuner, ControlNum, value, 1 ) ; // Write Matching INIT Control - status += MXL_ControlWrite_Group( Tuner, ControlNum, value, 2 ) ; // Write Matching CH Control + struct mxl5005s_state *state = fe->demodulator_priv; + u16 status = 0; + + /* Will write ALL Matching Control Name */ + status += MXL_ControlWrite_Group(fe, ControlNum, value, 1); /* Write Matching INIT Control * + status += MXL_ControlWrite_Group(fe, ControlNum, value, 2); /* Write Matching CH Control * #ifdef _MXL_INTERNAL - status += MXL_ControlWrite_Group( Tuner, ControlNum, value, 3 ) ; // Write Matching MXL Control + status += MXL_ControlWrite_Group(fe, ControlNum, value, 3); /* Write Matching MXL Control * #endif - - return status ; + return status; } /////////////////////////////////////////////////////////////////////////////// @@ -3947,105 +3933,86 @@ u16 MXL_ControlWrite(Tuner_struct *Tuner, u16 ControlNum, u32 value) // 2 : Control name not found // // // /////////////////////////////////////////////////////////////////////////////// -u16 MXL_ControlWrite_Group(Tuner_struct *Tuner, u16 controlNum, u32 value, u16 controlGroup) +// DONE +u16 MXL_ControlWrite_Group(struct dvb_frontend *fe, u16 controlNum, u32 value, u16 controlGroup) { - u16 i, j, k ; - u32 highLimit ; - u32 ctrlVal ; + struct mxl5005s_state *state = fe->demodulator_priv; + u16 i, j, k; + u32 highLimit; + u32 ctrlVal; - if( controlGroup == 1) // Initial Control - { - for (i=0; iInit_Ctrl_Num ; i++) - { - if ( controlNum == Tuner->Init_Ctrl[i].Ctrl_Num ) - { // find the control Name - highLimit = 1 << Tuner->Init_Ctrl[i].size ; - if ( value < highLimit) - { - for( j=0; jInit_Ctrl[i].size; j++) - { - Tuner->Init_Ctrl[i].val[j] = (u8)((value >> j) & 0x01) ; - // change the register map accordingly - MXL_RegWriteBit( Tuner, (u8)(Tuner->Init_Ctrl[i].addr[j]), - (u8)(Tuner->Init_Ctrl[i].bit[j]), - (u8)((value>>j) & 0x01) ) ; - } - ctrlVal = 0 ; - for(k=0; kInit_Ctrl[i].size; k++) - { - ctrlVal += Tuner->Init_Ctrl[i].val[k] * (1 << k) ; + if (controlGroup == 1) /* Initial Control */ { + + for (i = 0; i < state->Init_Ctrl_Num; i++) { + + if (controlNum == state->Init_Ctrl[i].Ctrl_Num) { + + highLimit = 1 << state->Init_Ctrl[i].size; + if (value < highLimit) { + for (j = 0; j < state->Init_Ctrl[i].size; j++) { + state->Init_Ctrl[i].val[j] = (u8)((value >> j) & 0x01); + MXL_RegWriteBit(fe, (u8)(state->Init_Ctrl[i].addr[j]), + (u8)(state->Init_Ctrl[i].bit[j]), + (u8)((value>>j) & 0x01) ); } + ctrlVal = 0; + for (k = 0; k < state->Init_Ctrl[i].size; k++) + ctrlVal += state->Init_Ctrl[i].val[k] * (1 << k); } else - { - return -1 ; - } + return -1; } } } - if ( controlGroup == 2) // Chan change Control - { - for (i=0; iCH_Ctrl_Num; i++) - { - if ( controlNum == Tuner->CH_Ctrl[i].Ctrl_Num ) - { // find the control Name - highLimit = 1 << Tuner->CH_Ctrl[i].size ; - if ( value < highLimit) - { - for( j=0; jCH_Ctrl[i].size; j++) - { - Tuner->CH_Ctrl[i].val[j] = (u8)((value >> j) & 0x01) ; - // change the register map accordingly - MXL_RegWriteBit( Tuner, (u8)(Tuner->CH_Ctrl[i].addr[j]), - (u8)(Tuner->CH_Ctrl[i].bit[j]), - (u8)((value>>j) & 0x01) ) ; - } - ctrlVal = 0 ; - for(k=0; kCH_Ctrl[i].size; k++) - { - ctrlVal += Tuner->CH_Ctrl[i].val[k] * (1 << k) ; + if (controlGroup == 2) /* Chan change Control */ { + + for (i = 0; i < state->CH_Ctrl_Num; i++) { + + if (controlNum == state->CH_Ctrl[i].Ctrl_Num ) { + + highLimit = 1 << state->CH_Ctrl[i].size; + if (value < highLimit) { + for (j = 0; j < state->CH_Ctrl[i].size; j++) { + state->CH_Ctrl[i].val[j] = (u8)((value >> j) & 0x01); + MXL_RegWriteBit(fe, (u8)(state->CH_Ctrl[i].addr[j]), + (u8)(state->CH_Ctrl[i].bit[j]), + (u8)((value>>j) & 0x01) ); } + ctrlVal = 0; + for (k = 0; k < state->CH_Ctrl[i].size; k++) + ctrlVal += state->CH_Ctrl[i].val[k] * (1 << k); } else - { - return -1 ; - } + return -1; } } } #ifdef _MXL_INTERNAL - if ( controlGroup == 3) // Maxlinear Control - { - for (i=0; iMXL_Ctrl_Num; i++) - { - if ( controlNum == Tuner->MXL_Ctrl[i].Ctrl_Num ) - { // find the control Name - highLimit = (1 << Tuner->MXL_Ctrl[i].size) ; - if ( value < highLimit) - { - for( j=0; jMXL_Ctrl[i].size; j++) - { - Tuner->MXL_Ctrl[i].val[j] = (u8)((value >> j) & 0x01) ; - // change the register map accordingly - MXL_RegWriteBit( Tuner, (u8)(Tuner->MXL_Ctrl[i].addr[j]), - (u8)(Tuner->MXL_Ctrl[i].bit[j]), - (u8)((value>>j) & 0x01) ) ; - } - ctrlVal = 0 ; - for(k=0; kMXL_Ctrl[i].size; k++) - { - ctrlVal += Tuner->MXL_Ctrl[i].val[k] * (1 << k) ; + if (controlGroup == 3) /* Maxlinear Control */ { + + for (i = 0; i < state->MXL_Ctrl_Num; i++) { + + if (controlNum == state->MXL_Ctrl[i].Ctrl_Num ) { + + highLimit = (1 << state->MXL_Ctrl[i].size) ; + if (value < highLimit) { + for (j = 0; j < state->MXL_Ctrl[i].size; j++) { + state->MXL_Ctrl[i].val[j] = (u8)((value >> j) & 0x01); + MXL_RegWriteBit(fe, (u8)(state->MXL_Ctrl[i].addr[j]), + (u8)(state->MXL_Ctrl[i].bit[j]), + (u8)((value>>j) & 0x01) ); } + ctrlVal = 0; + for(k = 0; k < state->MXL_Ctrl[i].size; k++) + ctrlVal += state->MXL_Ctrl[i].val[k] * (1 << k); } else - { - return -1 ; - } + return -1; } } } #endif - return 0 ; // successful return + return 0 ; /* successful return */ } /////////////////////////////////////////////////////////////////////////////// @@ -4073,20 +4040,20 @@ u16 MXL_ControlWrite_Group(Tuner_struct *Tuner, u16 controlNum, u32 value, u16 c // -1 : Invalid Register Address // // // /////////////////////////////////////////////////////////////////////////////// -u16 MXL_RegWrite(Tuner_struct *Tuner, u8 RegNum, u8 RegVal) +// DONE +u16 MXL_RegWrite(struct dvb_frontend *fe, u8 RegNum, u8 RegVal) { + struct mxl5005s_state *state = fe->demodulator_priv; int i ; - for (i=0; i<104; i++) - { - if (RegNum == Tuner->TunerRegs[i].Reg_Num ) - { - Tuner->TunerRegs[i].Reg_Val = RegVal ; - return 0 ; + for (i = 0; i < 104; i++) { + if (RegNum == state->TunerRegs[i].Reg_Num) { + state->TunerRegs[i].Reg_Val = RegVal; + return 0; } } - return 1 ; + return 1; } /////////////////////////////////////////////////////////////////////////////// @@ -4113,20 +4080,20 @@ u16 MXL_RegWrite(Tuner_struct *Tuner, u8 RegNum, u8 RegVal) // -1 : Invalid Register Address // // // /////////////////////////////////////////////////////////////////////////////// -u16 MXL_RegRead(Tuner_struct *Tuner, u8 RegNum, u8 *RegVal) +// DONE +u16 MXL_RegRead(struct dvb_frontend *fe, u8 RegNum, u8 *RegVal) { + struct mxl5005s_state *state = fe->demodulator_priv; int i ; - for (i=0; i<104; i++) - { - if (RegNum == Tuner->TunerRegs[i].Reg_Num ) - { - *RegVal = (u8)(Tuner->TunerRegs[i].Reg_Val) ; - return 0 ; + for (i = 0; i < 104; i++) { + if (RegNum == state->TunerRegs[i].Reg_Num ) { + *RegVal = (u8)(state->TunerRegs[i].Reg_Val); + return 0; } } - return 1 ; + return 1; } /////////////////////////////////////////////////////////////////////////////// @@ -4150,48 +4117,53 @@ u16 MXL_RegRead(Tuner_struct *Tuner, u8 RegNum, u8 *RegVal) // -1 : Invalid control name // // // /////////////////////////////////////////////////////////////////////////////// -u16 MXL_ControlRead(Tuner_struct *Tuner, u16 controlNum, u32 * value) +// DONE +u16 MXL_ControlRead(struct dvb_frontend *fe, u16 controlNum, u32 * value) { + struct mxl5005s_state *state = fe->demodulator_priv; u32 ctrlVal ; u16 i, k ; - for (i=0; iInit_Ctrl_Num ; i++) - { - if ( controlNum == Tuner->Init_Ctrl[i].Ctrl_Num ) - { - ctrlVal = 0 ; - for(k=0; kInit_Ctrl[i].size; k++) - ctrlVal += Tuner->Init_Ctrl[i].val[k] * (1 << k) ; - *value = ctrlVal ; - return 0 ; + for (i = 0; i < state->Init_Ctrl_Num ; i++) { + + if (controlNum == state->Init_Ctrl[i].Ctrl_Num) { + + ctrlVal = 0; + for (k = 0; k < state->Init_Ctrl[i].size; k++) + ctrlVal += state->Init_Ctrl[i].val[k] * (1 << k); + *value = ctrlVal; + return 0; } } - for (i=0; iCH_Ctrl_Num ; i++) - { - if ( controlNum == Tuner->CH_Ctrl[i].Ctrl_Num ) - { - ctrlVal = 0 ; - for(k=0; kCH_Ctrl[i].size; k++) - ctrlVal += Tuner->CH_Ctrl[i].val[k] * (1 << k) ; - *value = ctrlVal ; - return 0 ; + + for (i = 0; i < state->CH_Ctrl_Num ; i++) { + + if (controlNum == state->CH_Ctrl[i].Ctrl_Num) { + + ctrlVal = 0; + for (k = 0; k < state->CH_Ctrl[i].size; k++) + ctrlVal += state->CH_Ctrl[i].val[k] * (1 << k); + *value = ctrlVal; + return 0; + } } #ifdef _MXL_INTERNAL - for (i=0; iMXL_Ctrl_Num ; i++) - { - if ( controlNum == Tuner->MXL_Ctrl[i].Ctrl_Num ) - { - ctrlVal = 0 ; - for(k=0; kMXL_Ctrl[i].size; k++) - ctrlVal += Tuner->MXL_Ctrl[i].val[k] * (1<MXL_Ctrl_Num ; i++) { + + if (controlNum == state->MXL_Ctrl[i].Ctrl_Num) { + + ctrlVal = 0; + for (k = 0; k < state->MXL_Ctrl[i].size; k++) + ctrlVal += state->MXL_Ctrl[i].val[k] * (1<demodulator_priv; u16 i, j, k ; u16 Count ; - for (i=0; iInit_Ctrl_Num ; i++) - { - if ( controlNum == Tuner->Init_Ctrl[i].Ctrl_Num ) - { - Count = 1 ; - RegNum[0] = (u8)(Tuner->Init_Ctrl[i].addr[0]) ; + for (i = 0; i < state->Init_Ctrl_Num ; i++) { + + if ( controlNum == state->Init_Ctrl[i].Ctrl_Num ) { + + Count = 1; + RegNum[0] = (u8)(state->Init_Ctrl[i].addr[0]); + + for (k = 1; k < state->Init_Ctrl[i].size; k++) { + + for (j = 0; j < Count; j++) { + + if (state->Init_Ctrl[i].addr[k] != RegNum[j]) { + + Count ++; + RegNum[Count-1] = (u8)(state->Init_Ctrl[i].addr[k]); - for(k=1; kInit_Ctrl[i].size; k++) - { - for (j= 0; jInit_Ctrl[i].addr[k] != RegNum[j]) - { - Count ++ ; - RegNum[Count-1] = (u8)(Tuner->Init_Ctrl[i].addr[k]) ; } } } - *count = Count ; - return 0 ; + *count = Count; + return 0; } } - for (i=0; iCH_Ctrl_Num ; i++) - { - if ( controlNum == Tuner->CH_Ctrl[i].Ctrl_Num ) - { - Count = 1 ; - RegNum[0] = (u8)(Tuner->CH_Ctrl[i].addr[0]) ; + for (i = 0; i < state->CH_Ctrl_Num ; i++) { + + if ( controlNum == state->CH_Ctrl[i].Ctrl_Num ) { + + Count = 1; + RegNum[0] = (u8)(state->CH_Ctrl[i].addr[0]); + + for (k = 1; k < state->CH_Ctrl[i].size; k++) { + + for (j= 0; jCH_Ctrl[i].addr[k] != RegNum[j]) { + + Count ++; + RegNum[Count-1] = (u8)(state->CH_Ctrl[i].addr[k]); - for(k=1; kCH_Ctrl[i].size; k++) - { - for (j= 0; jCH_Ctrl[i].addr[k] != RegNum[j]) - { - Count ++ ; - RegNum[Count-1] = (u8)(Tuner->CH_Ctrl[i].addr[k]) ; } } } - *count = Count ; - return 0 ; + *count = Count; + return 0; } } #ifdef _MXL_INTERNAL - for (i=0; iMXL_Ctrl_Num ; i++) - { - if ( controlNum == Tuner->MXL_Ctrl[i].Ctrl_Num ) - { - Count = 1 ; - RegNum[0] = (u8)(Tuner->MXL_Ctrl[i].addr[0]) ; + for (i = 0; i < state->MXL_Ctrl_Num ; i++) { + + if ( controlNum == state->MXL_Ctrl[i].Ctrl_Num ) { + + Count = 1; + RegNum[0] = (u8)(state->MXL_Ctrl[i].addr[0]); + + for (k = 1; k < state->MXL_Ctrl[i].size; k++) { + + for (j = 0; jMXL_Ctrl[i].addr[k] != RegNum[j]) { + + Count ++; + RegNum[Count-1] = (u8)state->MXL_Ctrl[i].addr[k]; - for(k=1; kMXL_Ctrl[i].size; k++) - { - for (j= 0; jMXL_Ctrl[i].addr[k] != RegNum[j]) - { - Count ++ ; - RegNum[Count-1] = (u8)Tuner->MXL_Ctrl[i].addr[k] ; } } } - *count = Count ; - return 0 ; + *count = Count; + return 0; } } #endif - *count = 0 ; - return 1 ; + *count = 0; + return 1; } /////////////////////////////////////////////////////////////////////////////// @@ -4308,7 +4285,7 @@ u16 MXL_ControlRegRead(Tuner_struct *Tuner, u16 controlNum, u8 *RegNum, int * co // Inputs: // // Tuner_struct : structure defined at higher level // // address : register address // -// bit : register bit number // +// bit : register bit number // // bitVal : register bit value // // // // Outputs: // @@ -4318,12 +4295,12 @@ u16 MXL_ControlRegRead(Tuner_struct *Tuner, u16 controlNum, u8 *RegNum, int * co // NONE // // // /////////////////////////////////////////////////////////////////////////////// - -void MXL_RegWriteBit(Tuner_struct *Tuner, u8 address, u8 bit, u8 bitVal) +// DONE +void MXL_RegWriteBit(struct dvb_frontend *fe, u8 address, u8 bit, u8 bitVal) { + struct mxl5005s_state *state = fe->demodulator_priv; int i ; - // Declare Local Constants const u8 AND_MAP[8] = { 0xFE, 0xFD, 0xFB, 0xF7, 0xEF, 0xDF, 0xBF, 0x7F } ; @@ -4332,17 +4309,16 @@ void MXL_RegWriteBit(Tuner_struct *Tuner, u8 address, u8 bit, u8 bitVal) 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80 } ; - for(i=0; iTunerRegs_Num; i++) { - if ( Tuner->TunerRegs[i].Reg_Num == address ) { + for (i = 0; i < state->TunerRegs_Num; i++) { + if (state->TunerRegs[i].Reg_Num == address) { if (bitVal) - Tuner->TunerRegs[i].Reg_Val |= OR_MAP[bit] ; + state->TunerRegs[i].Reg_Val |= OR_MAP[bit]; else - Tuner->TunerRegs[i].Reg_Val &= AND_MAP[bit] ; + state->TunerRegs[i].Reg_Val &= AND_MAP[bit]; break ; } } -} ; - +} /////////////////////////////////////////////////////////////////////////////// // // @@ -4367,37 +4343,43 @@ void MXL_RegWriteBit(Tuner_struct *Tuner, u8 address, u8 bit, u8 bitVal) // Computed value // // // /////////////////////////////////////////////////////////////////////////////// -u32 MXL_Ceiling( u32 value, u32 resolution ) +// DONE +u32 MXL_Ceiling(u32 value, u32 resolution) { - return (value/resolution + (value%resolution > 0 ? 1 : 0)) ; -}; + return (value/resolution + (value % resolution > 0 ? 1 : 0)); +} // // Retrieve the Initialzation Registers // -u16 MXL_GetInitRegister(Tuner_struct *Tuner, u8 * RegNum, u8 *RegVal, int *count) +// DONE +u16 MXL_GetInitRegister(struct dvb_frontend *fe, u8 * RegNum, u8 *RegVal, int *count) { + struct mxl5005s_state *state = fe->demodulator_priv; u16 status = 0; int i ; - u8 RegAddr[] = {11, 12, 13, 22, 32, 43, 44, 53, 56, 59, 73, - 76, 77, 91, 134, 135, 137, 147, - 156, 166, 167, 168, 25 } ; - *count = sizeof(RegAddr) / sizeof(u8) ; + u8 RegAddr[] = { + 11, 12, 13, 22, 32, 43, 44, 53, 56, 59, 73, + 76, 77, 91, 134, 135, 137, 147, + 156, 166, 167, 168, 25 }; - status += MXL_BlockInit(Tuner) ; + *count = sizeof(RegAddr) / sizeof(u8); - for (i=0 ; i< *count; i++) - { - RegNum[i] = RegAddr[i] ; - status += MXL_RegRead(Tuner, RegNum[i], &RegVal[i]) ; + status += MXL_BlockInit(fe); + + for (i = 0 ; i < *count; i++) { + RegNum[i] = RegAddr[i]; + status += MXL_RegRead(fe, RegNum[i], &RegVal[i]); } - return status ; + return status; } -u16 MXL_GetCHRegister(Tuner_struct *Tuner, u8 * RegNum, u8 *RegVal, int *count) +// DONE +u16 MXL_GetCHRegister(struct dvb_frontend *fe, u8 * RegNum, u8 *RegVal, int *count) { + struct mxl5005s_state *state = fe->demodulator_priv; u16 status = 0; int i ; @@ -4413,203 +4395,207 @@ u16 MXL_GetCHRegister(Tuner_struct *Tuner, u8 * RegNum, u8 *RegVal, int *count) // RegAddr[i] = i; #endif - *count = sizeof(RegAddr) / sizeof(u8) ; + *count = sizeof(RegAddr) / sizeof(u8); - for (i=0 ; i< *count; i++) - { - RegNum[i] = RegAddr[i] ; - status += MXL_RegRead(Tuner, RegNum[i], &RegVal[i]) ; + for (i = 0 ; i < *count; i++) { + RegNum[i] = RegAddr[i]; + status += MXL_RegRead(fe, RegNum[i], &RegVal[i]); } - return status ; - + return status; } -u16 MXL_GetCHRegister_ZeroIF(Tuner_struct *Tuner, u8 * RegNum, u8 *RegVal, int *count) +// DONE +u16 MXL_GetCHRegister_ZeroIF(struct dvb_frontend *fe, u8 * RegNum, u8 *RegVal, int *count) { - u16 status = 0 ; - int i ; + struct mxl5005s_state *state = fe->demodulator_priv; + u16 status = 0; + int i; - u8 RegAddr[] = {43, 136} ; + u8 RegAddr[] = {43, 136}; - *count = sizeof(RegAddr) / sizeof(u8) ; + *count = sizeof(RegAddr) / sizeof(u8); - for (i=0; i<*count; i++) - { - RegNum[i] = RegAddr[i] ; - status += MXL_RegRead(Tuner, RegNum[i], &RegVal[i]) ; + for (i = 0; i < *count; i++) { + RegNum[i] = RegAddr[i]; + status += MXL_RegRead(fe, RegNum[i], &RegVal[i]); } - return status ; + return status; } -u16 MXL_GetCHRegister_LowIF(Tuner_struct *Tuner, u8 * RegNum, u8 *RegVal, int *count) +// DONE +u16 MXL_GetCHRegister_LowIF(struct dvb_frontend *fe, u8 * RegNum, u8 *RegVal, int *count) { - u16 status = 0 ; - int i ; + struct mxl5005s_state *state = fe->demodulator_priv; + u16 status = 0; + int i; - u8 RegAddr[] = {138} ; + u8 RegAddr[] = { 138 }; - *count = sizeof(RegAddr) / sizeof(u8) ; + *count = sizeof(RegAddr) / sizeof(u8); - for (i=0; i<*count; i++) - { - RegNum[i] = RegAddr[i] ; - status += MXL_RegRead(Tuner, RegNum[i], &RegVal[i]) ; + for (i = 0; i < *count; i++) { + RegNum[i] = RegAddr[i]; + status += MXL_RegRead(fe, RegNum[i], &RegVal[i]); } - return status ; + return status; } +// DONE u16 MXL_GetMasterControl(u8 *MasterReg, int state) { - if (state == 1) // Load_Start - *MasterReg = 0xF3 ; - if (state == 2) // Power_Down - *MasterReg = 0x41 ; - if (state == 3) // Synth_Reset - *MasterReg = 0xB1 ; - if (state == 4) // Seq_Off - *MasterReg = 0xF1 ; - - return 0 ; + if (state == 1) /* Load_Start */ + *MasterReg = 0xF3; + if (state == 2) /* Power_Down */ + *MasterReg = 0x41; + if (state == 3) /* Synth_Reset */ + *MasterReg = 0xB1; + if (state == 4) /* Seq_Off */ + *MasterReg = 0xF1; + + return 0; } #ifdef _MXL_PRODUCTION -u16 MXL_VCORange_Test(Tuner_struct *Tuner, int VCO_Range) +u16 MXL_VCORange_Test(struct dvb_frontend *fe, int VCO_Range) { + struct mxl5005s_state *state = fe->demodulator_priv; u16 status = 0 ; if (VCO_Range == 1) { - status += MXL_ControlWrite(Tuner, RFSYN_EN_DIV, 1); - status += MXL_ControlWrite(Tuner, RFSYN_EN_OUTMUX, 0); - status += MXL_ControlWrite(Tuner, RFSYN_SEL_DIVM, 0); - status += MXL_ControlWrite(Tuner, RFSYN_DIVM, 1); - status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_OUT, 1); - status += MXL_ControlWrite(Tuner, RFSYN_RF_DIV_BIAS, 1); - status += MXL_ControlWrite(Tuner, DN_SEL_FREQ, 0); - if (Tuner->Mode == 0 && Tuner->IF_Mode == 1) // Analog Low IF Mode { - status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 1); - status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 8); - status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 56); - status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_RF, 180224); - } - if (Tuner->Mode == 0 && Tuner->IF_Mode == 0) // Analog Zero IF Mode { - status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 1 ) ; - status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 8 ) ; - status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 56 ) ; - status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_RF, 222822 ) ; - } - if (Tuner->Mode == 1) // Digital Mode { - status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 1 ) ; - status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 8 ) ; - status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 56 ) ; - status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_RF, 229376 ) ; + status += MXL_ControlWrite(fe, RFSYN_EN_DIV, 1); + status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 0); + status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0); + status += MXL_ControlWrite(fe, RFSYN_DIVM, 1); + status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 1); + status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1); + status += MXL_ControlWrite(fe, DN_SEL_FREQ, 0); + if (state->Mode == 0 && state->IF_Mode == 1) /* Analog Low IF Mode */ { + status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1); + status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 8); + status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 56); + status += MXL_ControlWrite(fe, CHCAL_FRAC_MOD_RF, 180224); + } + if (state->Mode == 0 && state->IF_Mode == 0) /* Analog Zero IF Mode */ { + status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1); + status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 8); + status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 56); + status += MXL_ControlWrite(fe, CHCAL_FRAC_MOD_RF, 222822); + } + if (state->Mode == 1) /* Digital Mode */ { + status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1); + status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 8); + status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 56); + status += MXL_ControlWrite(fe, CHCAL_FRAC_MOD_RF, 229376); } } if (VCO_Range == 2) { - status += MXL_ControlWrite(Tuner, RFSYN_EN_DIV, 1); - status += MXL_ControlWrite(Tuner, RFSYN_EN_OUTMUX, 0); - status += MXL_ControlWrite(Tuner, RFSYN_SEL_DIVM, 0); - status += MXL_ControlWrite(Tuner, RFSYN_DIVM, 1); - status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_OUT, 1); - status += MXL_ControlWrite(Tuner, RFSYN_RF_DIV_BIAS, 1); - status += MXL_ControlWrite(Tuner, DN_SEL_FREQ, 0); - status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 1); - status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 40); - status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 41); - if (Tuner->Mode == 0 && Tuner->IF_Mode == 1) // Analog Low IF Mode { - status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 1); - status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 40); - status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 42); - status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_RF, 206438); - } - if (Tuner->Mode == 0 && Tuner->IF_Mode == 0) // Analog Zero IF Mode { - status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 1); - status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 40); - status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 42); - status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_RF, 206438); - } - if (Tuner->Mode == 1) // Digital Mode { - status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 1); - status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 40); - status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 41); - status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_RF, 16384); + status += MXL_ControlWrite(fe, RFSYN_EN_DIV, 1); + status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 0); + status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0); + status += MXL_ControlWrite(fe, RFSYN_DIVM, 1); + status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 1); + status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1); + status += MXL_ControlWrite(fe, DN_SEL_FREQ, 0); + status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1); + status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 40); + status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 41); + if (state->Mode == 0 && state->IF_Mode == 1) /* Analog Low IF Mode */ { + status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1); + status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 40); + status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 42); + status += MXL_ControlWrite(fe, CHCAL_FRAC_MOD_RF, 206438); + } + if (state->Mode == 0 && state->IF_Mode == 0) /* Analog Zero IF Mode */ { + status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1); + status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 40); + status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 42); + status += MXL_ControlWrite(fe, CHCAL_FRAC_MOD_RF, 206438); + } + if (state->Mode == 1) /* Digital Mode */ { + status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1); + status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 40); + status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 41); + status += MXL_ControlWrite(fe, CHCAL_FRAC_MOD_RF, 16384); } } if (VCO_Range == 3) { - status += MXL_ControlWrite(Tuner, RFSYN_EN_DIV, 1); - status += MXL_ControlWrite(Tuner, RFSYN_EN_OUTMUX, 0); - status += MXL_ControlWrite(Tuner, RFSYN_SEL_DIVM, 0); - status += MXL_ControlWrite(Tuner, RFSYN_DIVM, 1); - status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_OUT, 1); - status += MXL_ControlWrite(Tuner, RFSYN_RF_DIV_BIAS, 1); - status += MXL_ControlWrite(Tuner, DN_SEL_FREQ, 0); - status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 0); - status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 8); - status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 42); - if (Tuner->Mode == 0 && Tuner->IF_Mode == 1) // Analog Low IF Mode { - status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 0); - status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 8); - status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 44); - status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_RF, 173670); - } - if (Tuner->Mode == 0 && Tuner->IF_Mode == 0) // Analog Zero IF Mode { - status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 0); - status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 8); - status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 44); - status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_RF, 173670); - } - if (Tuner->Mode == 1) // Digital Mode { - status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 0); - status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 8); - status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 42); - status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_RF, 245760); + status += MXL_ControlWrite(fe, RFSYN_EN_DIV, 1); + status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 0); + status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0); + status += MXL_ControlWrite(fe, RFSYN_DIVM, 1); + status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 1); + status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1); + status += MXL_ControlWrite(fe, DN_SEL_FREQ, 0); + status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0); + status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 8); + status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 42); + if (state->Mode == 0 && state->IF_Mode == 1) /* Analog Low IF Mode */ { + status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0); + status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 8); + status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 44); + status += MXL_ControlWrite(fe, CHCAL_FRAC_MOD_RF, 173670); + } + if (state->Mode == 0 && state->IF_Mode == 0) /* Analog Zero IF Mode */ { + status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0); + status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 8); + status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 44); + status += MXL_ControlWrite(fe, CHCAL_FRAC_MOD_RF, 173670); + } + if (state->Mode == 1) /* Digital Mode */ { + status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0); + status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 8); + status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 42); + status += MXL_ControlWrite(fe, CHCAL_FRAC_MOD_RF, 245760); } } if (VCO_Range == 4) { - status += MXL_ControlWrite(Tuner, RFSYN_EN_DIV, 1); - status += MXL_ControlWrite(Tuner, RFSYN_EN_OUTMUX, 0); - status += MXL_ControlWrite(Tuner, RFSYN_SEL_DIVM, 0); - status += MXL_ControlWrite(Tuner, RFSYN_DIVM, 1); - status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_OUT, 1); - status += MXL_ControlWrite(Tuner, RFSYN_RF_DIV_BIAS, 1); - status += MXL_ControlWrite(Tuner, DN_SEL_FREQ, 0); - status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 0); - status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 40); - status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 27); - if (Tuner->Mode == 0 && Tuner->IF_Mode == 1) // Analog Low IF Mode { - status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 0); - status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 40); - status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 27); - status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_RF, 206438); - } - if (Tuner->Mode == 0 && Tuner->IF_Mode == 0) // Analog Zero IF Mode { - status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 0); - status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 40); - status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 27); - status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_RF, 206438); - } - if (Tuner->Mode == 1) // Digital Mode { - status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 0); - status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 40); - status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 27); - status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_RF, 212992); + status += MXL_ControlWrite(fe, RFSYN_EN_DIV, 1); + status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 0); + status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0); + status += MXL_ControlWrite(fe, RFSYN_DIVM, 1); + status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 1); + status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1); + status += MXL_ControlWrite(fe, DN_SEL_FREQ, 0); + status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0); + status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 40); + status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 27); + if (state->Mode == 0 && state->IF_Mode == 1) /* Analog Low IF Mode */ { + status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0); + status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 40); + status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 27); + status += MXL_ControlWrite(fe, CHCAL_FRAC_MOD_RF, 206438); + } + if (state->Mode == 0 && state->IF_Mode == 0) /* Analog Zero IF Mode */ { + status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0); + status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 40); + status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 27); + status += MXL_ControlWrite(fe, CHCAL_FRAC_MOD_RF, 206438); + } + if (state->Mode == 1) /* Digital Mode */ { + status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0); + status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 40); + status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 27); + status += MXL_ControlWrite(fe, CHCAL_FRAC_MOD_RF, 212992); } } return status; } -u16 MXL_Hystersis_Test(Tuner_struct *Tuner, int Hystersis) +// DONE +u16 MXL_Hystersis_Test(struct dvb_frontend *fe, int Hystersis) { + struct mxl5005s_state *state = fe->demodulator_priv; u16 status = 0; if (Hystersis == 1) - status += MXL_ControlWrite(Tuner, DN_BYPASS_AGC_I2C, 1); + status += MXL_ControlWrite(fe, DN_BYPASS_AGC_I2C, 1); return status; } diff --git a/linux/drivers/media/common/tuners/mxl5005s.h b/linux/drivers/media/common/tuners/mxl5005s.h index 1944d9e94..df4982681 100644 --- a/linux/drivers/media/common/tuners/mxl5005s.h +++ b/linux/drivers/media/common/tuners/mxl5005s.h @@ -140,61 +140,6 @@ typedef struct _TunerReg_struct u16 Reg_Val; /* Current sofware programmed value waiting to be writen */ } TunerReg_struct; -/* MXL5005 Tuner Control Struct */ -typedef struct _TunerControl_struct { - u16 Ctrl_Num; /* Control Number */ - u16 size; /* Number of bits to represent Value */ - u16 addr[25]; /* Array of Tuner Register Address for each bit position */ - u16 bit[25]; /* Array of bit position in Register Address for each bit position */ - u16 val[25]; /* Binary representation of Value */ -} TunerControl_struct; - -/* MXL5005 Tuner Struct */ -typedef struct _Tuner_struct -{ - u8 Mode; /* 0: Analog Mode ; 1: Digital Mode */ - u8 IF_Mode; /* for Analog Mode, 0: zero IF; 1: low IF */ - u32 Chan_Bandwidth; /* filter channel bandwidth (6, 7, 8) */ - u32 IF_OUT; /* Desired IF Out Frequency */ - u16 IF_OUT_LOAD; /* IF Out Load Resistor (200/300 Ohms) */ - u32 RF_IN; /* RF Input Frequency */ - u32 Fxtal; /* XTAL Frequency */ - u8 AGC_Mode; /* AGC Mode 0: Dual AGC; 1: Single AGC */ - u16 TOP; /* Value: take over point */ - u8 CLOCK_OUT; /* 0: turn off clock out; 1: turn on clock out */ - u8 DIV_OUT; /* 4MHz or 16MHz */ - u8 CAPSELECT; /* 0: disable On-Chip pulling cap; 1: enable */ - u8 EN_RSSI; /* 0: disable RSSI; 1: enable RSSI */ - u8 Mod_Type; /* Modulation Type; */ - /* 0 - Default; 1 - DVB-T; 2 - ATSC; 3 - QAM; 4 - Analog Cable */ - u8 TF_Type; /* Tracking Filter Type */ - /* 0 - Default; 1 - Off; 2 - Type C; 3 - Type C-H */ - - /* Calculated Settings */ - u32 RF_LO; /* Synth RF LO Frequency */ - u32 IF_LO; /* Synth IF LO Frequency */ - u32 TG_LO; /* Synth TG_LO Frequency */ - - /* Pointers to ControlName Arrays */ - u16 Init_Ctrl_Num; /* Number of INIT Control Names */ - TunerControl_struct - Init_Ctrl[INITCTRL_NUM]; /* INIT Control Names Array Pointer */ - - u16 CH_Ctrl_Num; /* Number of CH Control Names */ - TunerControl_struct - CH_Ctrl[CHCTRL_NUM]; /* CH Control Name Array Pointer */ - - u16 MXL_Ctrl_Num; /* Number of MXL Control Names */ - TunerControl_struct - MXL_Ctrl[MXLCTRL_NUM]; /* MXL Control Name Array Pointer */ - - /* Pointer to Tuner Register Array */ - u16 TunerRegs_Num; /* Number of Tuner Registers */ - TunerReg_struct - TunerRegs[TUNER_REGS_NUM]; /* Tuner Register Array Pointer */ - -} Tuner_struct; - typedef enum { /* Initialization Control Names */ @@ -290,60 +235,6 @@ typedef enum * MaxLinear source code - Common_MXL.h (?) */ -void InitTunerControls(Tuner_struct *Tuner); -u16 MXL_BlockInit(Tuner_struct *Tuner); -u16 MXL5005_RegisterInit(Tuner_struct *Tuner); -u16 MXL5005_ControlInit(Tuner_struct *Tuner); -#ifdef _MXL_INTERNAL -u16 MXL5005_MXLControlInit(Tuner_struct *Tuner); -#endif - -u16 MXL5005_TunerConfig(Tuner_struct *Tuner, - u8 Mode, /* 0: Analog Mode ; 1: Digital Mode */ - u8 IF_mode, /* for Analog Mode, 0: zero IF; 1: low IF */ - u32 Bandwidth, /* filter channel bandwidth (6, 7, 8) */ - u32 IF_out, /* Desired IF Out Frequency */ - u32 Fxtal, /* XTAL Frequency */ - u8 AGC_Mode, /* AGC Mode - Dual AGC: 0, Single AGC: 1 */ - u16 TOP, /* 0: Dual AGC; Value: take over point */ - u16 IF_OUT_LOAD, /* IF Out Load Resistor (200 / 300 Ohms) */ - u8 CLOCK_OUT, /* 0: turn off clock out; 1: turn on clock out */ - u8 DIV_OUT, /* 4MHz or 16MHz */ - u8 CAPSELECT, /* 0: disable On-Chip pulling cap; 1: enable */ - u8 EN_RSSI, /* 0: disable RSSI; 1: enable RSSI */ - u8 Mod_Type, /* Modulation Type; */ - /* 0 - Default; 1 - DVB-T; 2 - ATSC; 3 - QAM; 4 - Analog Cable */ - u8 TF_Type /* Tracking Filter Type */ - /* 0 - Default; 1 - Off; 2 - Type C; 3 - Type C-H */ - ); - -void MXL_SynthIFLO_Calc(Tuner_struct *Tuner); -void MXL_SynthRFTGLO_Calc(Tuner_struct *Tuner); -u16 MXL_RegWrite(Tuner_struct *Tuner, u8 RegNum, u8 RegVal); -u16 MXL_RegRead(Tuner_struct *Tuner, u8 RegNum, u8 *RegVal); -u16 MXL_ControlWrite(Tuner_struct *Tuner, u16 ControlNum, u32 value); -u16 MXL_ControlWrite_Group(Tuner_struct *Tuner, u16 ControlNum, u32 value, u16 controlGroup); -u16 MXL_ControlRead(Tuner_struct *Tuner, u16 ControlNum, u32 * value); -u16 MXL_ControlRegRead(Tuner_struct *Tuner, u16 ControlNum, u8 *RegNum, int *count); -void MXL_RegWriteBit(Tuner_struct *Tuner, u8 address, u8 bit, u8 bitVal); -u16 MXL_IFSynthInit(Tuner_struct * Tuner ); -u16 MXL_TuneRF(Tuner_struct *Tuner, u32 RF_Freq); -u16 MXL_OverwriteICDefault(Tuner_struct *Tuner); -u16 MXL_SetGPIO(Tuner_struct *Tuner, u8 GPIO_Num, u8 GPIO_Val); -u32 MXL_Ceiling(u32 value, u32 resolution); -u32 MXL_GetXtalInt(u32 Xtal_Freq); - -u16 MXL_GetInitRegister(Tuner_struct *Tuner, u8 * RegNum, u8 *RegVal, int *count); -u16 MXL_GetCHRegister(Tuner_struct *Tuner, u8 * RegNum, u8 *RegVal, int *count); -u16 MXL_GetCHRegister_ZeroIF(Tuner_struct *Tuner, u8 * RegNum, u8 *RegVal, int *count); -u16 MXL_GetCHRegister_LowIF(Tuner_struct *Tuner, u8 * RegNum, u8 *RegVal, int *count); -u16 MXL_GetMasterControl(u8 *MasterReg, int state); - -#ifdef _MXL_PRODUCTION -u16 MXL_VCORange_Test(Tuner_struct *Tuner, int VCO_Range); -u16 MXL_Hystersis_Test(Tuner_struct *Tuner, int Hystersis); -#endif - /* Constants */ #define MXL5005S_REG_WRITING_TABLE_LEN_MAX 104 #define MXL5005S_LATCH_BYTE 0xfe @@ -401,62 +292,6 @@ enum MXL5005S_IF_OUTPUT_LOAD_300_OHM = 300, }; -/* MxL5005S extra module alias */ -typedef struct MXL5005S_EXTRA_MODULE_TAG MXL5005S_EXTRA_MODULE; - -/* MxL5005S register setting function pointer */ -typedef int -(*MXL5005S_FP_SET_REGS_WITH_TABLE)( - struct dvb_usb_device* dib, - TUNER_MODULE *pTuner, - unsigned char *pAddrTable, - unsigned char *pByteTable, - int TableLen - ); - - -/* MxL5005S register mask bits setting function pointer */ -typedef int -(*MXL5005S_FP_SET_REG_MASK_BITS)( - struct dvb_usb_device* dib, - TUNER_MODULE *pTuner, - unsigned char RegAddr, - unsigned char Msb, - unsigned char Lsb, - const unsigned char WritingValue - ); - -/* MxL5005S spectrum mode setting function pointer */ -typedef int -(*MXL5005S_FP_SET_SPECTRUM_MODE)( - struct dvb_usb_device* dib, - TUNER_MODULE *pTuner, - int SpectrumMode - ); - -/* MxL5005S bandwidth setting function pointer */ -typedef int -(*MXL5005S_FP_SET_BANDWIDTH_HZ)( - struct dvb_usb_device* dib, - TUNER_MODULE *pTuner, - unsigned long BandwidthHz - ); - -/* MxL5005S extra module */ -struct MXL5005S_EXTRA_MODULE_TAG -{ - /* MxL5005S function pointers */ - MXL5005S_FP_SET_REGS_WITH_TABLE SetRegsWithTable; - MXL5005S_FP_SET_REG_MASK_BITS SetRegMaskBits; - MXL5005S_FP_SET_SPECTRUM_MODE SetSpectrumMode; - MXL5005S_FP_SET_BANDWIDTH_HZ SetBandwidthHz; - - /* MxL5005S extra data */ - unsigned char AgcMasterByte; /* Variable name in MaxLinear source code: AGC_MASTER_BYTE */ - - /* MaxLinear defined struct */ - Tuner_struct MxlDefinedTunerStructure; -}; /* End of common_mxl.h (?) */ #endif /* __MXL5005S_H */ -- cgit v1.2.3 From 3732597662f347708916af9a5f8cb840fd382770 Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Thu, 1 May 2008 01:48:14 -0400 Subject: mxl5005s: Cleanup #4 From: Steven Toth Cleanup #4 Signed-off-by: Steven Toth Signed-off-by: Mauro Carvalho Chehab --- linux/drivers/media/common/tuners/mxl5005s.c | 1054 +++++++++++++++----------- linux/drivers/media/common/tuners/mxl5005s.h | 291 +------ 2 files changed, 661 insertions(+), 684 deletions(-) (limited to 'linux/drivers/media/common/tuners') diff --git a/linux/drivers/media/common/tuners/mxl5005s.c b/linux/drivers/media/common/tuners/mxl5005s.c index 619183680..8a20a8657 100644 --- a/linux/drivers/media/common/tuners/mxl5005s.c +++ b/linux/drivers/media/common/tuners/mxl5005s.c @@ -24,6 +24,270 @@ #include "mxl5005s.h" +static int debug; + +#define dprintk(level, arg...) do { \ + if (debug >= level) \ + printk(arg); \ + } while (0) + +#define TUNER_REGS_NUM 104 +#define INITCTRL_NUM 40 + +#ifdef _MXL_PRODUCTION +#define CHCTRL_NUM 39 +#else +#define CHCTRL_NUM 36 +#endif + +#define MXLCTRL_NUM 189 +#define MASTER_CONTROL_ADDR 9 + +/* Enumeration of AGC Mode */ +typedef enum +{ + MXL_DUAL_AGC = 0, + MXL_SINGLE_AGC +} AGC_Mode; + +/* Enumeration of Master Control Register State */ +typedef enum +{ + MC_LOAD_START = 1, + MC_POWER_DOWN, + MC_SYNTH_RESET, + MC_SEQ_OFF +} Master_Control_State; + +/* Enumeration of MXL5005 Tuner Mode */ +typedef enum +{ + MXL_ANALOG_MODE = 0, + MXL_DIGITAL_MODE +} Tuner_Mode; + +/* Enumeration of MXL5005 Tuner IF Mode */ +typedef enum +{ + MXL_ZERO_IF = 0, + MXL_LOW_IF +} Tuner_IF_Mode; + +/* Enumeration of MXL5005 Tuner Clock Out Mode */ +typedef enum +{ + MXL_CLOCK_OUT_DISABLE = 0, + MXL_CLOCK_OUT_ENABLE +} Tuner_Clock_Out; + +/* Enumeration of MXL5005 Tuner Div Out Mode */ +typedef enum +{ + MXL_DIV_OUT_1 = 0, + MXL_DIV_OUT_4 + +} Tuner_Div_Out; + +/* Enumeration of MXL5005 Tuner Pull-up Cap Select Mode */ +typedef enum +{ + MXL_CAP_SEL_DISABLE = 0, + MXL_CAP_SEL_ENABLE + +} Tuner_Cap_Select; + +/* Enumeration of MXL5005 Tuner RSSI Mode */ +typedef enum +{ + MXL_RSSI_DISABLE = 0, + MXL_RSSI_ENABLE + +} Tuner_RSSI; + +/* Enumeration of MXL5005 Tuner Modulation Type */ +typedef enum +{ + MXL_DEFAULT_MODULATION = 0, + MXL_DVBT, + MXL_ATSC, + MXL_QAM, + MXL_ANALOG_CABLE, + MXL_ANALOG_OTA +} Tuner_Modu_Type; + +/* Enumeration of MXL5005 Tuner Tracking Filter Type */ +typedef enum +{ + MXL_TF_DEFAULT = 0, + MXL_TF_OFF, + MXL_TF_C, + MXL_TF_C_H, + MXL_TF_D, + MXL_TF_D_L, + MXL_TF_E, + MXL_TF_F, + MXL_TF_E_2, + MXL_TF_E_NA, + MXL_TF_G +} Tuner_TF_Type; + +/* MXL5005 Tuner Register Struct */ +typedef struct _TunerReg_struct +{ + u16 Reg_Num; /* Tuner Register Address */ + u16 Reg_Val; /* Current sofware programmed value waiting to be writen */ +} TunerReg_struct; + +typedef enum +{ + /* Initialization Control Names */ + DN_IQTN_AMP_CUT = 1, /* 1 */ + BB_MODE, /* 2 */ + BB_BUF, /* 3 */ + BB_BUF_OA, /* 4 */ + BB_ALPF_BANDSELECT, /* 5 */ + BB_IQSWAP, /* 6 */ + BB_DLPF_BANDSEL, /* 7 */ + RFSYN_CHP_GAIN, /* 8 */ + RFSYN_EN_CHP_HIGAIN, /* 9 */ + AGC_IF, /* 10 */ + AGC_RF, /* 11 */ + IF_DIVVAL, /* 12 */ + IF_VCO_BIAS, /* 13 */ + CHCAL_INT_MOD_IF, /* 14 */ + CHCAL_FRAC_MOD_IF, /* 15 */ + DRV_RES_SEL, /* 16 */ + I_DRIVER, /* 17 */ + EN_AAF, /* 18 */ + EN_3P, /* 19 */ + EN_AUX_3P, /* 20 */ + SEL_AAF_BAND, /* 21 */ + SEQ_ENCLK16_CLK_OUT, /* 22 */ + SEQ_SEL4_16B, /* 23 */ + XTAL_CAPSELECT, /* 24 */ + IF_SEL_DBL, /* 25 */ + RFSYN_R_DIV, /* 26 */ + SEQ_EXTSYNTHCALIF, /* 27 */ + SEQ_EXTDCCAL, /* 28 */ + AGC_EN_RSSI, /* 29 */ + RFA_ENCLKRFAGC, /* 30 */ + RFA_RSSI_REFH, /* 31 */ + RFA_RSSI_REF, /* 32 */ + RFA_RSSI_REFL, /* 33 */ + RFA_FLR, /* 34 */ + RFA_CEIL, /* 35 */ + SEQ_EXTIQFSMPULSE, /* 36 */ + OVERRIDE_1, /* 37 */ + BB_INITSTATE_DLPF_TUNE, /* 38 */ + TG_R_DIV, /* 39 */ + EN_CHP_LIN_B, /* 40 */ + + /* Channel Change Control Names */ + DN_POLY = 51, /* 51 */ + DN_RFGAIN, /* 52 */ + DN_CAP_RFLPF, /* 53 */ + DN_EN_VHFUHFBAR, /* 54 */ + DN_GAIN_ADJUST, /* 55 */ + DN_IQTNBUF_AMP, /* 56 */ + DN_IQTNGNBFBIAS_BST, /* 57 */ + RFSYN_EN_OUTMUX, /* 58 */ + RFSYN_SEL_VCO_OUT, /* 59 */ + RFSYN_SEL_VCO_HI, /* 60 */ + RFSYN_SEL_DIVM, /* 61 */ + RFSYN_RF_DIV_BIAS, /* 62 */ + DN_SEL_FREQ, /* 63 */ + RFSYN_VCO_BIAS, /* 64 */ + CHCAL_INT_MOD_RF, /* 65 */ + CHCAL_FRAC_MOD_RF, /* 66 */ + RFSYN_LPF_R, /* 67 */ + CHCAL_EN_INT_RF, /* 68 */ + TG_LO_DIVVAL, /* 69 */ + TG_LO_SELVAL, /* 70 */ + TG_DIV_VAL, /* 71 */ + TG_VCO_BIAS, /* 72 */ + SEQ_EXTPOWERUP, /* 73 */ + OVERRIDE_2, /* 74 */ + OVERRIDE_3, /* 75 */ + OVERRIDE_4, /* 76 */ + SEQ_FSM_PULSE, /* 77 */ + GPIO_4B, /* 78 */ + GPIO_3B, /* 79 */ + GPIO_4, /* 80 */ + GPIO_3, /* 81 */ + GPIO_1B, /* 82 */ + DAC_A_ENABLE, /* 83 */ + DAC_B_ENABLE, /* 84 */ + DAC_DIN_A, /* 85 */ + DAC_DIN_B, /* 86 */ +#ifdef _MXL_PRODUCTION + RFSYN_EN_DIV, /* 87 */ + RFSYN_DIVM, /* 88 */ + DN_BYPASS_AGC_I2C /* 89 */ +#endif +} MXL5005_ControlName; + +/* + * The following context is source code provided by MaxLinear. + * MaxLinear source code - Common_MXL.h (?) + */ + +/* Constants */ +#define MXL5005S_REG_WRITING_TABLE_LEN_MAX 104 +#define MXL5005S_LATCH_BYTE 0xfe + +/* Register address, MSB, and LSB */ +#define MXL5005S_BB_IQSWAP_ADDR 59 +#define MXL5005S_BB_IQSWAP_MSB 0 +#define MXL5005S_BB_IQSWAP_LSB 0 + +#define MXL5005S_BB_DLPF_BANDSEL_ADDR 53 +#define MXL5005S_BB_DLPF_BANDSEL_MSB 4 +#define MXL5005S_BB_DLPF_BANDSEL_LSB 3 + +/* Standard modes */ +enum +{ + MXL5005S_STANDARD_DVBT, + MXL5005S_STANDARD_ATSC, +}; +#define MXL5005S_STANDARD_MODE_NUM 2 + +/* Bandwidth modes */ +enum +{ + MXL5005S_BANDWIDTH_6MHZ = 6000000, + MXL5005S_BANDWIDTH_7MHZ = 7000000, + MXL5005S_BANDWIDTH_8MHZ = 8000000, +}; +#define MXL5005S_BANDWIDTH_MODE_NUM 3 + +/* Top modes */ +enum +{ + MXL5005S_TOP_5P5 = 55, + MXL5005S_TOP_7P2 = 72, + MXL5005S_TOP_9P2 = 92, + MXL5005S_TOP_11P0 = 110, + MXL5005S_TOP_12P9 = 129, + MXL5005S_TOP_14P7 = 147, + MXL5005S_TOP_16P8 = 168, + MXL5005S_TOP_19P4 = 194, + MXL5005S_TOP_21P2 = 212, + MXL5005S_TOP_23P2 = 232, + MXL5005S_TOP_25P2 = 252, + MXL5005S_TOP_27P1 = 271, + MXL5005S_TOP_29P2 = 292, + MXL5005S_TOP_31P7 = 317, + MXL5005S_TOP_34P9 = 349, +}; + +/* IF output load */ +enum +{ + MXL5005S_IF_OUTPUT_LOAD_200_OHM = 200, + MXL5005S_IF_OUTPUT_LOAD_300_OHM = 300, +}; + /* MXL5005 Tuner Control Struct */ typedef struct _TunerControl_struct { u16 Ctrl_Num; /* Control Number */ @@ -77,400 +341,148 @@ struct mxl5005s_state TunerReg_struct TunerRegs[TUNER_REGS_NUM]; /* Tuner Register Array Pointer */ -}; - -#if 0 -void BuildMxl5005sModule( - TUNER_MODULE **ppTuner, - TUNER_MODULE *pTunerModuleMemory, - MXL5005S_EXTRA_MODULE *pMxl5005sExtraModuleMemory, - BASE_INTERFACE_MODULE *pBaseInterfaceModuleMemory, - I2C_BRIDGE_MODULE *pI2cBridgeModuleMemory, - unsigned char DeviceAddr, - int StandardMode - ) -{ - MXL5005S_EXTRA_MODULE *pExtra; - - int MxlModMode; - int MxlIfMode; - unsigned long MxlBandwitdh; - unsigned long MxlIfFreqHz; - unsigned long MxlCrystalFreqHz; - int MxlAgcMode; - unsigned short MxlTop; - unsigned short MxlIfOutputLoad; - int MxlClockOut; - int MxlDivOut; - int MxlCapSel; - int MxlRssiOnOff; - unsigned char MxlStandard; - unsigned char MxlTfType; - - - - // Set tuner module pointer, tuner extra module pointer, and I2C bridge module pointer. - *ppTuner = pTunerModuleMemory; - (*ppTuner)->pExtra = pMxl5005sExtraModuleMemory; - (*ppTuner)->pBaseInterface = pBaseInterfaceModuleMemory; - (*ppTuner)->pI2cBridge = pI2cBridgeModuleMemory; - - // Get tuner extra module pointer. - pExtra = (MXL5005S_EXTRA_MODULE *)(*ppTuner)->pExtra; - - - // Set I2C bridge tuner arguments. - mxl5005s_SetI2cBridgeModuleTunerArg(*ppTuner); - - - // Set tuner module manipulating function pointers. - (*ppTuner)->SetDeviceAddr = mxl5005s_SetDeviceAddr; - - (*ppTuner)->GetTunerType = mxl5005s_GetTunerType; - (*ppTuner)->GetDeviceAddr = mxl5005s_GetDeviceAddr; - - (*ppTuner)->Initialize = mxl5005s_Initialize; - (*ppTuner)->SetRfFreqHz = mxl5005s_SetRfFreqHz; - (*ppTuner)->GetRfFreqHz = mxl5005s_GetRfFreqHz; + /* Linux driver framework specific */ + const struct mxl5005s_config *config; + struct dvb_frontend *frontend; + struct i2c_adapter *i2c; +}; - // Set tuner extra module manipulating function pointers. - pExtra->SetRegsWithTable = mxl5005s_SetRegsWithTable; - pExtra->SetRegMaskBits = mxl5005s_SetRegMaskBits; - pExtra->SetSpectrumMode = mxl5005s_SetSpectrumMode; - pExtra->SetBandwidthHz = mxl5005s_SetBandwidthHz; - - - // Initialize tuner parameter setting status. - (*ppTuner)->IsDeviceAddrSet = NO; - (*ppTuner)->IsRfFreqHzSet = NO; - - - // Set MxL5005S parameters. - MxlModMode = MXL_DIGITAL_MODE; - MxlIfMode = MXL_ZERO_IF; - MxlBandwitdh = MXL5005S_BANDWIDTH_8MHZ; - MxlIfFreqHz = IF_FREQ_4570000HZ; - MxlCrystalFreqHz = CRYSTAL_FREQ_16000000HZ; - MxlAgcMode = MXL_SINGLE_AGC; - MxlTop = MXL5005S_TOP_25P2; - MxlIfOutputLoad = MXL5005S_IF_OUTPUT_LOAD_200_OHM; - MxlClockOut = MXL_CLOCK_OUT_DISABLE; - MxlDivOut = MXL_DIV_OUT_4; - MxlCapSel = MXL_CAP_SEL_ENABLE; - MxlRssiOnOff = MXL_RSSI_ENABLE; - MxlTfType = MXL_TF_C_H; - - - // Set MxL5005S parameters according to standard mode - switch(StandardMode) - { - default: - case MXL5005S_STANDARD_DVBT: MxlStandard = MXL_DVBT; break; - case MXL5005S_STANDARD_ATSC: MxlStandard = MXL_ATSC; break; - } - - - // Set MxL5005S extra module. - pExtra->AgcMasterByte = (MxlAgcMode == MXL_DUAL_AGC) ? 0x4 : 0x0; - - MXL5005_TunerConfig(&pExtra->MxlDefinedTunerStructure, (unsigned char)MxlModMode, (unsigned char)MxlIfMode, - MxlBandwitdh, MxlIfFreqHz, MxlCrystalFreqHz, (unsigned char)MxlAgcMode, MxlTop, MxlIfOutputLoad, - (unsigned char)MxlClockOut, (unsigned char)MxlDivOut, (unsigned char)MxlCapSel, (unsigned char)MxlRssiOnOff, - MxlStandard, MxlTfType); - - - - // Note: Need to set all module arguments before using module functions. - - - // Set tuner type. - (*ppTuner)->TunerType = TUNER_TYPE_MXL5005S; - - // Set tuner I2C device address. - (*ppTuner)->SetDeviceAddr(*ppTuner, DeviceAddr); - - - return; -} - -void mxl5005s_SetDeviceAddr( - TUNER_MODULE *pTuner, - unsigned char DeviceAddr - ) -{ - // Set tuner I2C device address. - pTuner->DeviceAddr = DeviceAddr; - pTuner->IsDeviceAddrSet = YES; - - - return; -} - -void mxl5005s_GetTunerType( - TUNER_MODULE *pTuner, - int *pTunerType - ) -{ - // Get tuner type from tuner module. - *pTunerType = pTuner->TunerType; - - - return; -} - -int mxl5005s_GetDeviceAddr( - TUNER_MODULE *pTuner, - unsigned char *pDeviceAddr - ) -{ - // Get tuner I2C device address from tuner module. - if(pTuner->IsDeviceAddrSet != YES) - goto error_status_get_tuner_i2c_device_addr; - - *pDeviceAddr = pTuner->DeviceAddr; - - - return FUNCTION_SUCCESS; - - -error_status_get_tuner_i2c_device_addr: - return FUNCTION_ERROR; -} -#endif - -int mxl5005s_Initialize( - struct dvb_usb_device* dib, - TUNER_MODULE *pTuner - ) +// funcs +u16 MXL_ControlWrite(struct dvb_frontend *fe, u16 ControlNum, u32 value); +u16 MXL_ControlRead(struct dvb_frontend *fe, u16 controlNum, u32 *value); +u16 MXL_GetMasterControl(u8 *MasterReg, int state); +void MXL_RegWriteBit(struct dvb_frontend *fe, u8 address, u8 bit, u8 bitVal); +u16 MXL_GetCHRegister(struct dvb_frontend *fe, u8 *RegNum, u8 *RegVal, int *count); +u32 MXL_Ceiling(u32 value, u32 resolution); +u16 MXL_RegRead(struct dvb_frontend *fe, u8 RegNum, u8 *RegVal); +u16 MXL_RegWrite(struct dvb_frontend *fe, u8 RegNum, u8 RegVal); +u16 MXL_ControlWrite_Group(struct dvb_frontend *fe, u16 controlNum, u32 value, u16 controlGroup); +u16 MXL_SetGPIO(struct dvb_frontend *fe, u8 GPIO_Num, u8 GPIO_Val); +u16 MXL_GetInitRegister(struct dvb_frontend *fe, u8 * RegNum, u8 *RegVal, int *count); +u32 MXL_GetXtalInt(u32 Xtal_Freq); +u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq); +void MXL_SynthIFLO_Calc(struct dvb_frontend *fe); +void MXL_SynthRFTGLO_Calc(struct dvb_frontend *fe); +u16 MXL_GetCHRegister_ZeroIF(struct dvb_frontend *fe, u8 *RegNum, u8 *RegVal, int *count); +int mxl5005s_SetRegsWithTable(struct dvb_frontend *fe, u8 *pAddrTable, u8 *pByteTable, int TableLen); +u16 MXL_IFSynthInit(struct dvb_frontend *fe); + +int mxl5005s_SetRfFreqHz(struct dvb_frontend *fe, unsigned long RfFreqHz) { - MXL5005S_EXTRA_MODULE *pExtra; - - unsigned char AgcMasterByte; + struct mxl5005s_state *state = fe->tuner_priv; + u8 AgcMasterByte = state->config->AgcMasterByte; unsigned char AddrTable[MXL5005S_REG_WRITING_TABLE_LEN_MAX]; unsigned char ByteTable[MXL5005S_REG_WRITING_TABLE_LEN_MAX]; int TableLen; - // Get tuner extra module. - pExtra = (MXL5005S_EXTRA_MODULE *)pTuner->pExtra; - - // Get AGC master byte - AgcMasterByte = pExtra->AgcMasterByte; - - // Initialize MxL5005S tuner according to MxL5005S tuner example code. - - // Tuner initialization stage 0 - MXL_GetMasterControl(ByteTable, MC_SYNTH_RESET); - AddrTable[0] = MASTER_CONTROL_ADDR; - ByteTable[0] |= AgcMasterByte; - - if(pExtra->SetRegsWithTable( dib,pTuner, AddrTable, ByteTable, LEN_1_BYTE) != FUNCTION_SUCCESS) - goto error_status_set_tuner_registers; - - // Tuner initialization stage 1 - MXL_GetInitRegister(&pExtra->MxlDefinedTunerStructure, AddrTable, ByteTable, &TableLen); - - if(pExtra->SetRegsWithTable( dib,pTuner, AddrTable, ByteTable, TableLen) != FUNCTION_SUCCESS) - goto error_status_set_tuner_registers; - - return FUNCTION_SUCCESS; - -error_status_set_tuner_registers: - return FUNCTION_ERROR; -} - -int mxl5005s_SetRfFreqHz( - struct dvb_usb_device* dib, - TUNER_MODULE *pTuner, - unsigned long RfFreqHz - ) -{ - MXL5005S_EXTRA_MODULE *pExtra; - BASE_INTERFACE_MODULE *pBaseInterface; - - unsigned char AgcMasterByte; - unsigned char AddrTable[MXL5005S_REG_WRITING_TABLE_LEN_MAX]; - unsigned char ByteTable[MXL5005S_REG_WRITING_TABLE_LEN_MAX]; - int TableLen; - - unsigned long IfDivval; + u32 IfDivval; unsigned char MasterControlByte; - // Get tuner extra module and base interface module. - pExtra = (MXL5005S_EXTRA_MODULE *)pTuner->pExtra; - pBaseInterface = pTuner->pBaseInterface; - - - // Get AGC master byte - AgcMasterByte = pExtra->AgcMasterByte; - + dprintk(1, "%s() freq=%ld\n", __func__, RfFreqHz); // Set MxL5005S tuner RF frequency according to MxL5005S tuner example code. // Tuner RF frequency setting stage 0 MXL_GetMasterControl(ByteTable, MC_SYNTH_RESET) ; AddrTable[0] = MASTER_CONTROL_ADDR; - ByteTable[0] |= AgcMasterByte; - - if(pExtra->SetRegsWithTable( dib,pTuner, AddrTable, ByteTable, LEN_1_BYTE) != FUNCTION_SUCCESS) - goto error_status_set_tuner_registers; + ByteTable[0] |= state->config->AgcMasterByte; + mxl5005s_SetRegsWithTable(fe, AddrTable, ByteTable, 1); // Tuner RF frequency setting stage 1 - MXL_TuneRF(&pExtra->MxlDefinedTunerStructure, RfFreqHz); + MXL_TuneRF(fe, RfFreqHz); - MXL_ControlRead(&pExtra->MxlDefinedTunerStructure, IF_DIVVAL, &IfDivval); + MXL_ControlRead(fe, IF_DIVVAL, &IfDivval); - MXL_ControlWrite(&pExtra->MxlDefinedTunerStructure, SEQ_FSM_PULSE, 0); - MXL_ControlWrite(&pExtra->MxlDefinedTunerStructure, SEQ_EXTPOWERUP, 1); - MXL_ControlWrite(&pExtra->MxlDefinedTunerStructure, IF_DIVVAL, 8); - - MXL_GetCHRegister(&pExtra->MxlDefinedTunerStructure, AddrTable, ByteTable, &TableLen) ; + MXL_ControlWrite(fe, SEQ_FSM_PULSE, 0); + MXL_ControlWrite(fe, SEQ_EXTPOWERUP, 1); + MXL_ControlWrite(fe, IF_DIVVAL, 8); + MXL_GetCHRegister(fe, AddrTable, ByteTable, &TableLen) ; MXL_GetMasterControl(&MasterControlByte, MC_LOAD_START) ; AddrTable[TableLen] = MASTER_CONTROL_ADDR ; ByteTable[TableLen] = MasterControlByte | AgcMasterByte; TableLen += 1; - if(pExtra->SetRegsWithTable( dib,pTuner, AddrTable, ByteTable, TableLen) != FUNCTION_SUCCESS) - goto error_status_set_tuner_registers; - + mxl5005s_SetRegsWithTable(fe, AddrTable, ByteTable, TableLen); // Wait 30 ms. - pBaseInterface->WaitMs(pBaseInterface, 30); - + msleep(30); // Tuner RF frequency setting stage 2 - MXL_ControlWrite(&pExtra->MxlDefinedTunerStructure, SEQ_FSM_PULSE, 1) ; - MXL_ControlWrite(&pExtra->MxlDefinedTunerStructure, IF_DIVVAL, IfDivval) ; - MXL_GetCHRegister_ZeroIF(&pExtra->MxlDefinedTunerStructure, AddrTable, ByteTable, &TableLen) ; + MXL_ControlWrite(fe, SEQ_FSM_PULSE, 1) ; + MXL_ControlWrite(fe, IF_DIVVAL, IfDivval) ; + MXL_GetCHRegister_ZeroIF(fe, AddrTable, ByteTable, &TableLen) ; MXL_GetMasterControl(&MasterControlByte, MC_LOAD_START) ; AddrTable[TableLen] = MASTER_CONTROL_ADDR ; ByteTable[TableLen] = MasterControlByte | AgcMasterByte ; TableLen += 1; - if(pExtra->SetRegsWithTable( dib,pTuner, AddrTable, ByteTable, TableLen) != FUNCTION_SUCCESS) - goto error_status_set_tuner_registers; + mxl5005s_SetRegsWithTable(fe, AddrTable, ByteTable, TableLen); - - // Set tuner RF frequency parameter. - pTuner->RfFreqHz = RfFreqHz; - pTuner->IsRfFreqHzSet = YES; - - - return FUNCTION_SUCCESS; - - -error_status_set_tuner_registers: - return FUNCTION_ERROR; + return 0; } -// DONE -int mxl5005s_GetRfFreqHz(struct dvb_frontend *fe, unsigned long *pRfFreqHz) +/* Write a single byte to a single reg */ +static int mxl5005s_writereg(struct dvb_frontend *fe, u8 reg, u8 val) { - struct mxl5005s_state *state = fe->demodulator_priv; - int ret = -1; - - /* Get tuner RF frequency in Hz from tuner module. */ - if(state->IsRfFreqHzSet == YES) { - *pRfFreqHz = state->RfFreqHz; - ret = 0; + struct mxl5005s_state *state = fe->tuner_priv; + u8 buf[2] = { reg, val }; + struct i2c_msg msg = { .addr = state->config->i2c_address, .flags = 0, + .buf = buf, .len = 2 }; + + if (i2c_transfer(state->i2c, &msg, 1) != 1) { + printk(KERN_WARNING "mxl5005s I2C write failed\n"); + return -EREMOTEIO; } - - return -1; + return 0; } -int mxl5005s_SetRegsWithTable( - struct dvb_usb_device* dib, - TUNER_MODULE *pTuner, - unsigned char *pAddrTable, - unsigned char *pByteTable, - int TableLen - ) +/* Write a word to a single reg */ +static int mxl5005s_writereg16(struct dvb_frontend *fe, u8 reg, u16 val) { - BASE_INTERFACE_MODULE *pBaseInterface; - I2C_BRIDGE_MODULE *pI2cBridge; - unsigned char WritingByteNumMax; - - int i; - unsigned char WritingBuffer[I2C_BUFFER_LEN]; - unsigned char WritingIndex; - - - - // Get base interface, I2C bridge, and maximum writing byte number. - pBaseInterface = pTuner->pBaseInterface; - pI2cBridge = pTuner->pI2cBridge; - WritingByteNumMax = pBaseInterface->I2cWritingByteNumMax; - - - // Set registers with table. - // Note: 1. The I2C format of MxL5005S is described as follows: - // start_bit + (device_addr | writing_bit) + (register_addr + writing_byte) * n + stop_bit - // ... - // start_bit + (device_addr | writing_bit) + (register_addr + writing_byte) * m + latch_byte + stop_bit - // 2. The latch_byte is 0xfe. - // 3. The following writing byte separating scheme takes latch_byte as two byte data. - for(i = 0, WritingIndex = 0; i < TableLen; i++) - { - // Put register address and register byte value into writing buffer. - WritingBuffer[WritingIndex] = pAddrTable[i]; - WritingBuffer[WritingIndex + 1] = pByteTable[i]; - WritingIndex += 2; - - // If writing buffer is full, send the I2C writing command with writing buffer. - if(WritingIndex > (WritingByteNumMax - 2)) - { - if(pI2cBridge->ForwardI2cWritingCmd(pI2cBridge, WritingBuffer, WritingIndex) != FUNCTION_SUCCESS) - goto error_status_set_tuner_registers; - - WritingIndex = 0; - } + struct mxl5005s_state *state = fe->tuner_priv; + u8 buf[3] = { reg, val >> 8 , val & 0xff }; + struct i2c_msg msg = { .addr = state->config->i2c_address, .flags = 0, + .buf = buf, .len = 3 }; + + if (i2c_transfer(state->i2c, &msg, 1) != 1) { + printk(KERN_WARNING "mxl5005s I2C write16 failed\n"); + return -EREMOTEIO; } - - - // Send the last I2C writing command with writing buffer and latch byte. - WritingBuffer[WritingIndex] = MXL5005S_LATCH_BYTE; - WritingIndex += 1; - - if(pI2cBridge->ForwardI2cWritingCmd(pI2cBridge, WritingBuffer, WritingIndex) != FUNCTION_SUCCESS) - goto error_status_set_tuner_registers; - - - return FUNCTION_SUCCESS; - - -error_status_set_tuner_registers: - return FUNCTION_ERROR; + return 0; } -int mxl5005s_SetRegsWithTable(struct dvb_frontend *fe, - unsigned char *pAddrTable, - unsigned char *pByteTable, - int TableLen - ) +int mxl5005s_SetRegsWithTable(struct dvb_frontend *fe, u8 *pAddrTable, u8 *pByteTable, int TableLen) { - struct mxl5005s_state *state = fe->demodulator_priv; - int i; + int i, ret; u8 end_two_bytes_buf[]={ 0 , 0 }; - u8 tuner_addr=0x00; - - pTuner->GetDeviceAddr(pTuner , &tuner_addr); for( i = 0 ; i < TableLen - 1 ; i++) { +#if 0 if ( TUNER_WI2C(dib , tuner_addr , pAddrTable[i] , &pByteTable[i] , 1 ) ) return FUNCTION_ERROR; +#else + ret = mxl5005s_writereg(fe, pAddrTable[i], pByteTable[i]); + if (!ret) + return ret; +#endif } end_two_bytes_buf[0] = pByteTable[i]; end_two_bytes_buf[1] = MXL5005S_LATCH_BYTE; +#if 0 if ( TUNER_WI2C(dib , tuner_addr , pAddrTable[i] , end_two_bytes_buf , 2 ) ) return FUNCTION_ERROR; +#else + ret = mxl5005s_writereg16(fe, pAddrTable[i], (end_two_bytes_buf[0] << 8) | end_two_bytes_buf[1]); +#endif - return FUNCTION_SUCCESS; + return ret; } int mxl5005s_SetRegMaskBits(struct dvb_frontend *fe, @@ -480,7 +492,6 @@ int mxl5005s_SetRegMaskBits(struct dvb_frontend *fe, const unsigned char WritingValue ) { - struct mxl5005s_state *state = fe->demodulator_priv; int i; unsigned char Mask; @@ -494,33 +505,24 @@ int mxl5005s_SetRegMaskBits(struct dvb_frontend *fe, Shift = Lsb; - /* Get tuner register byte according to register adddress. */ - MXL_RegRead(&pExtra->MxlDefinedTunerStructure, RegAddr, &RegByte); + MXL_RegRead(fe, RegAddr, &RegByte); /* Reserve register byte unmask bit with mask and inlay writing value into it. */ RegByte &= ~Mask; RegByte |= (WritingValue << Shift) & Mask; /* Update tuner register byte table. */ - MXL_RegWrite(&pExtra->MxlDefinedTunerStructure, RegAddr, RegByte); + MXL_RegWrite(fe, RegAddr, RegByte); /* Write tuner register byte with writing byte. */ - if(pExtra->SetRegsWithTable( dib, pTuner, &RegAddr, &RegByte, LEN_1_BYTE) != FUNCTION_SUCCESS) - goto error_status_set_tuner_registers; - - - return FUNCTION_SUCCESS; - - -error_status_set_tuner_registers: - return FUNCTION_ERROR; + return mxl5005s_SetRegsWithTable(fe, &RegAddr, &RegByte, 1); } - +#if 0 // DONE int mxl5005s_SetSpectrumMode(struct dvb_frontend *fe, int SpectrumMode) { - struct mxl5005s_state *state = fe->demodulator_priv; + struct mxl5005s_state *state = fe->tuner_priv; static const unsigned char BbIqswapTable[SPECTRUM_MODE_NUM] = { /* BB_IQSWAP */ @@ -541,7 +543,7 @@ int mxl5005s_SetSpectrumMode(struct dvb_frontend *fe, int SpectrumMode) // DONE int mxl5005s_SetBandwidthHz(struct dvb_frontend *fe, unsigned long BandwidthHz) { - struct mxl5005s_state *state = fe->demodulator_priv; + struct mxl5005s_state *state = fe->tuner_priv; unsigned char BbDlpfBandsel; @@ -571,13 +573,14 @@ int mxl5005s_SetBandwidthHz(struct dvb_frontend *fe, unsigned long BandwidthHz) error_status_set_tuner_registers: return -1; } +#endif // The following context is source code provided by MaxLinear. // MaxLinear source code - MXL5005_Initialize.cpp // DONE u16 MXL5005_RegisterInit(struct dvb_frontend *fe) { - struct mxl5005s_state *state = fe->demodulator_priv; + struct mxl5005s_state *state = fe->tuner_priv; state->TunerRegs_Num = TUNER_REGS_NUM ; // state->TunerRegs = (TunerReg_struct *) calloc( TUNER_REGS_NUM, sizeof(TunerReg_struct) ) ; @@ -899,7 +902,7 @@ u16 MXL5005_RegisterInit(struct dvb_frontend *fe) // DONE u16 MXL5005_ControlInit(struct dvb_frontend *fe) { - struct mxl5005s_state *state = fe->demodulator_priv; + struct mxl5005s_state *state = fe->tuner_priv; state->Init_Ctrl_Num = INITCTRL_NUM; state->Init_Ctrl[0].Ctrl_Num = DN_IQTN_AMP_CUT ; @@ -1843,7 +1846,6 @@ u16 MXL5005_ControlInit(struct dvb_frontend *fe) // DONE void InitTunerControls(struct dvb_frontend *fe) { - struct mxl5005s_state *state = fe->demodulator_priv; MXL5005_RegisterInit(fe); MXL5005_ControlInit(fe); #ifdef _MXL_INTERNAL @@ -1904,7 +1906,7 @@ u16 MXL5005_TunerConfig(struct dvb_frontend *fe, /* 0 - Default; 1 - Off; 2 - Type C; 3 - Type C-H */ ) { - struct mxl5005s_state *state = fe->demodulator_priv; + struct mxl5005s_state *state = fe->tuner_priv; u16 status = 0; state->Mode = Mode; @@ -1957,8 +1959,8 @@ u16 MXL5005_TunerConfig(struct dvb_frontend *fe, // DONE void MXL_SynthIFLO_Calc(struct dvb_frontend *fe) { - struct mxl5005s_state *state = fe->demodulator_priv; - if (Tuner->Mode == 1) /* Digital Mode */ + struct mxl5005s_state *state = fe->tuner_priv; + if (state->Mode == 1) /* Digital Mode */ state->IF_LO = state->IF_OUT; else /* Analog Mode */ { @@ -1996,7 +1998,7 @@ void MXL_SynthIFLO_Calc(struct dvb_frontend *fe) // DONE void MXL_SynthRFTGLO_Calc(struct dvb_frontend *fe) { - struct mxl5005s_state *state = fe->demodulator_priv; + struct mxl5005s_state *state = fe->tuner_priv; if (state->Mode == 1) /* Digital Mode */ { //remove 20.48MHz setting for 2.6.10 @@ -2035,7 +2037,6 @@ void MXL_SynthRFTGLO_Calc(struct dvb_frontend *fe) // DONE u16 MXL_OverwriteICDefault(struct dvb_frontend *fe) { - struct mxl5005s_state *state = fe->demodulator_priv; u16 status = 0; status += MXL_ControlWrite(fe, OVERRIDE_1, 1); @@ -2074,7 +2075,7 @@ u16 MXL_OverwriteICDefault(struct dvb_frontend *fe) // DONE u16 MXL_BlockInit(struct dvb_frontend *fe) { - struct mxl5005s_state *state = fe->demodulator_priv; + struct mxl5005s_state *state = fe->tuner_priv; u16 status = 0; status += MXL_OverwriteICDefault(fe); @@ -2255,7 +2256,7 @@ u16 MXL_BlockInit(struct dvb_frontend *fe) status += MXL_ControlWrite(fe, RFSYN_R_DIV, 0); /* Misc Controls */ - if (state->Mode == 0 && Tuner->IF_Mode == 1) /* Analog LowIF mode */ + if (state->Mode == 0 && state->IF_Mode == 1) /* Analog LowIF mode */ status += MXL_ControlWrite(fe, SEQ_EXTIQFSMPULSE, 0); else status += MXL_ControlWrite(fe, SEQ_EXTIQFSMPULSE, 1); @@ -2314,7 +2315,7 @@ u16 MXL_BlockInit(struct dvb_frontend *fe) } if (state->Mod_Type == MXL_ATSC) /* ATSC Mode */ { - Tuner->AGC_Mode = 1; /* Single AGC Mode */ + state->AGC_Mode = 1; /* Single AGC Mode */ /* Enable RSSI */ status += MXL_ControlWrite(fe, SEQ_EXTSYNTHCALIF, 1); @@ -2362,7 +2363,7 @@ u16 MXL_BlockInit(struct dvb_frontend *fe) } if (state->Mod_Type == MXL_ANALOG_CABLE) { /* Analog Cable Mode */ - /* Tuner->Mode = MXL_DIGITAL_MODE; */ + /* state->Mode = MXL_DIGITAL_MODE; */ state->AGC_Mode = 1; /* Single AGC Mode */ @@ -2428,8 +2429,9 @@ u16 MXL_BlockInit(struct dvb_frontend *fe) // > 0 : Failed // // // /////////////////////////////////////////////////////////////////////////////// -u16 MXL_IFSynthInit(Tuner_struct * Tuner) +u16 MXL_IFSynthInit(struct dvb_frontend *fe) { + struct mxl5005s_state *state = fe->tuner_priv; u16 status = 0 ; // Declare Local Variables u32 Fref = 0 ; @@ -2445,186 +2447,186 @@ u16 MXL_IFSynthInit(Tuner_struct * Tuner) // // IF Synthesizer Control // - if (Tuner->Mode == 0 && Tuner->IF_Mode == 1) // Analog Low IF mode + if (state->Mode == 0 && state->IF_Mode == 1) // Analog Low IF mode { - if (Tuner->IF_LO == 41000000UL) { + if (state->IF_LO == 41000000UL) { status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08) ; status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C) ; Fref = 328000000UL ; } - if (Tuner->IF_LO == 47000000UL) { + if (state->IF_LO == 47000000UL) { status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08) ; status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; Fref = 376000000UL ; } - if (Tuner->IF_LO == 54000000UL) { + if (state->IF_LO == 54000000UL) { status += MXL_ControlWrite(fe, IF_DIVVAL, 0x10) ; status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C) ; Fref = 324000000UL ; } - if (Tuner->IF_LO == 60000000UL) { + if (state->IF_LO == 60000000UL) { status += MXL_ControlWrite(fe, IF_DIVVAL, 0x10) ; status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; Fref = 360000000UL ; } - if (Tuner->IF_LO == 39250000UL) { + if (state->IF_LO == 39250000UL) { status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08) ; status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C) ; Fref = 314000000UL ; } - if (Tuner->IF_LO == 39650000UL) { + if (state->IF_LO == 39650000UL) { status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08) ; status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C) ; Fref = 317200000UL ; } - if (Tuner->IF_LO == 40150000UL) { + if (state->IF_LO == 40150000UL) { status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08) ; status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C) ; Fref = 321200000UL ; } - if (Tuner->IF_LO == 40650000UL) { + if (state->IF_LO == 40650000UL) { status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08) ; status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C) ; Fref = 325200000UL ; } } - if (Tuner->Mode || (Tuner->Mode == 0 && Tuner->IF_Mode == 0)) + if (state->Mode || (state->Mode == 0 && state->IF_Mode == 0)) { - if (Tuner->IF_LO == 57000000UL) { + if (state->IF_LO == 57000000UL) { status += MXL_ControlWrite(fe, IF_DIVVAL, 0x10) ; status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; Fref = 342000000UL ; } - if (Tuner->IF_LO == 44000000UL) { + if (state->IF_LO == 44000000UL) { status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08) ; status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; Fref = 352000000UL ; } - if (Tuner->IF_LO == 43750000UL) { + if (state->IF_LO == 43750000UL) { status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08) ; status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; Fref = 350000000UL ; } - if (Tuner->IF_LO == 36650000UL) { + if (state->IF_LO == 36650000UL) { status += MXL_ControlWrite(fe, IF_DIVVAL, 0x04) ; status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; Fref = 366500000UL ; } - if (Tuner->IF_LO == 36150000UL) { + if (state->IF_LO == 36150000UL) { status += MXL_ControlWrite(fe, IF_DIVVAL, 0x04) ; status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; Fref = 361500000UL ; } - if (Tuner->IF_LO == 36000000UL) { + if (state->IF_LO == 36000000UL) { status += MXL_ControlWrite(fe, IF_DIVVAL, 0x04) ; status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; Fref = 360000000UL ; } - if (Tuner->IF_LO == 35250000UL) { + if (state->IF_LO == 35250000UL) { status += MXL_ControlWrite(fe, IF_DIVVAL, 0x04) ; status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; Fref = 352500000UL ; } - if (Tuner->IF_LO == 34750000UL) { + if (state->IF_LO == 34750000UL) { status += MXL_ControlWrite(fe, IF_DIVVAL, 0x04) ; status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; Fref = 347500000UL ; } - if (Tuner->IF_LO == 6280000UL) { + if (state->IF_LO == 6280000UL) { status += MXL_ControlWrite(fe, IF_DIVVAL, 0x07) ; status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; Fref = 376800000UL ; } - if (Tuner->IF_LO == 5000000UL) { + if (state->IF_LO == 5000000UL) { status += MXL_ControlWrite(fe, IF_DIVVAL, 0x09) ; status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; Fref = 360000000UL ; } - if (Tuner->IF_LO == 4500000UL) { + if (state->IF_LO == 4500000UL) { status += MXL_ControlWrite(fe, IF_DIVVAL, 0x06) ; status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; Fref = 360000000UL ; } - if (Tuner->IF_LO == 4570000UL) { + if (state->IF_LO == 4570000UL) { status += MXL_ControlWrite(fe, IF_DIVVAL, 0x06) ; status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; Fref = 365600000UL ; } - if (Tuner->IF_LO == 4000000UL) { + if (state->IF_LO == 4000000UL) { status += MXL_ControlWrite(fe, IF_DIVVAL, 0x05) ; status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; Fref = 360000000UL ; } - if (Tuner->IF_LO == 57400000UL) + if (state->IF_LO == 57400000UL) { status += MXL_ControlWrite(fe, IF_DIVVAL, 0x10) ; status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; Fref = 344400000UL ; } - if (Tuner->IF_LO == 44400000UL) + if (state->IF_LO == 44400000UL) { status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08) ; status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; Fref = 355200000UL ; } - if (Tuner->IF_LO == 44150000UL) + if (state->IF_LO == 44150000UL) { status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08) ; status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; Fref = 353200000UL ; } - if (Tuner->IF_LO == 37050000UL) + if (state->IF_LO == 37050000UL) { status += MXL_ControlWrite(fe, IF_DIVVAL, 0x04) ; status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; Fref = 370500000UL ; } - if (Tuner->IF_LO == 36550000UL) + if (state->IF_LO == 36550000UL) { status += MXL_ControlWrite(fe, IF_DIVVAL, 0x04) ; status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; Fref = 365500000UL ; } - if (Tuner->IF_LO == 36125000UL) { + if (state->IF_LO == 36125000UL) { status += MXL_ControlWrite(fe, IF_DIVVAL, 0x04) ; status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; Fref = 361250000UL ; } - if (Tuner->IF_LO == 6000000UL) { + if (state->IF_LO == 6000000UL) { status += MXL_ControlWrite(fe, IF_DIVVAL, 0x07) ; status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; Fref = 360000000UL ; } - if (Tuner->IF_LO == 5400000UL) + if (state->IF_LO == 5400000UL) { status += MXL_ControlWrite(fe, IF_DIVVAL, 0x07) ; status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C) ; Fref = 324000000UL ; } - if (Tuner->IF_LO == 5380000UL) { + if (state->IF_LO == 5380000UL) { status += MXL_ControlWrite(fe, IF_DIVVAL, 0x07) ; status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C) ; Fref = 322800000UL ; } - if (Tuner->IF_LO == 5200000UL) { + if (state->IF_LO == 5200000UL) { status += MXL_ControlWrite(fe, IF_DIVVAL, 0x09) ; status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; Fref = 374400000UL ; } - if (Tuner->IF_LO == 4900000UL) + if (state->IF_LO == 4900000UL) { status += MXL_ControlWrite(fe, IF_DIVVAL, 0x09) ; status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; Fref = 352800000UL ; } - if (Tuner->IF_LO == 4400000UL) + if (state->IF_LO == 4400000UL) { status += MXL_ControlWrite(fe, IF_DIVVAL, 0x06) ; status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; Fref = 352000000UL ; } - if (Tuner->IF_LO == 4063000UL) //add for 2.6.8 + if (state->IF_LO == 4063000UL) //add for 2.6.8 { status += MXL_ControlWrite(fe, IF_DIVVAL, 0x05) ; status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; @@ -2701,7 +2703,7 @@ u32 MXL_GetXtalInt(u32 Xtal_Freq) /////////////////////////////////////////////////////////////////////////////// u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq) { - struct mxl5005s_state *state = fe->demodulator_priv; + struct mxl5005s_state *state = fe->tuner_priv; // Declare Local Variables u16 status = 0; u32 divider_val, E3, E4, E5, E5A; @@ -3193,7 +3195,7 @@ u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq) // // Off Chip Tracking Filter Control // - if (Tuner->TF_Type == MXL_TF_OFF) // Tracking Filter Off State; turn off all the banks + if (state->TF_Type == MXL_TF_OFF) // Tracking Filter Off State; turn off all the banks { status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0) ; status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; @@ -3203,7 +3205,7 @@ u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq) status += MXL_SetGPIO(fe, 4, 1) ; // turn off Bank 3 } - if (Tuner->TF_Type == MXL_TF_C) // Tracking Filter type C + if (state->TF_Type == MXL_TF_C) // Tracking Filter type C { status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1) ; status += MXL_ControlWrite(fe, DAC_DIN_A, 0) ; @@ -3283,7 +3285,7 @@ u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq) } } - if (Tuner->TF_Type == MXL_TF_C_H) // Tracking Filter type C-H for Hauppauge only + if (state->TF_Type == MXL_TF_C_H) // Tracking Filter type C-H for Hauppauge only { status += MXL_ControlWrite(fe, DAC_DIN_A, 0) ; @@ -3353,7 +3355,7 @@ u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq) } } - if (Tuner->TF_Type == MXL_TF_D) // Tracking Filter type D + if (state->TF_Type == MXL_TF_D) // Tracking Filter type D { status += MXL_ControlWrite(fe, DAC_DIN_B, 0) ; @@ -3410,7 +3412,7 @@ u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq) } - if (Tuner->TF_Type == MXL_TF_D_L) // Tracking Filter type D-L for Lumanate ONLY change for 2.6.3 + if (state->TF_Type == MXL_TF_D_L) // Tracking Filter type D-L for Lumanate ONLY change for 2.6.3 { status += MXL_ControlWrite(fe, DAC_DIN_A, 0) ; @@ -3495,7 +3497,7 @@ u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq) } } - if (Tuner->TF_Type == MXL_TF_E) // Tracking Filter type E + if (state->TF_Type == MXL_TF_E) // Tracking Filter type E { status += MXL_ControlWrite(fe, DAC_DIN_B, 0) ; @@ -3551,7 +3553,7 @@ u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq) } } - if (Tuner->TF_Type == MXL_TF_F) // Tracking Filter type F + if (state->TF_Type == MXL_TF_F) // Tracking Filter type F { status += MXL_ControlWrite(fe, DAC_DIN_B, 0) ; @@ -3607,7 +3609,7 @@ u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq) } } - if (Tuner->TF_Type == MXL_TF_E_2) // Tracking Filter type E_2 + if (state->TF_Type == MXL_TF_E_2) // Tracking Filter type E_2 { status += MXL_ControlWrite(fe, DAC_DIN_B, 0) ; @@ -3663,7 +3665,7 @@ u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq) } } - if (Tuner->TF_Type == MXL_TF_G) // Tracking Filter type G add for v2.6.8 + if (state->TF_Type == MXL_TF_G) // Tracking Filter type G add for v2.6.8 { status += MXL_ControlWrite(fe, DAC_DIN_B, 0) ; @@ -3726,7 +3728,7 @@ u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq) } } - if (Tuner->TF_Type == MXL_TF_E_NA) // Tracking Filter type E-NA for Empia ONLY change for 2.6.8 + if (state->TF_Type == MXL_TF_E_NA) // Tracking Filter type E-NA for Empia ONLY change for 2.6.8 { status += MXL_ControlWrite(fe, DAC_DIN_B, 0) ; @@ -3826,7 +3828,6 @@ u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq) // DONE u16 MXL_SetGPIO(struct dvb_frontend *fe, u8 GPIO_Num, u8 GPIO_Val) { - struct mxl5005s_state *state = fe->demodulator_priv; u16 status = 0; if (GPIO_Num == 1) @@ -3894,14 +3895,13 @@ u16 MXL_SetGPIO(struct dvb_frontend *fe, u8 GPIO_Num, u8 GPIO_Val) // DONE u16 MXL_ControlWrite(struct dvb_frontend *fe, u16 ControlNum, u32 value) { - struct mxl5005s_state *state = fe->demodulator_priv; u16 status = 0; /* Will write ALL Matching Control Name */ - status += MXL_ControlWrite_Group(fe, ControlNum, value, 1); /* Write Matching INIT Control * - status += MXL_ControlWrite_Group(fe, ControlNum, value, 2); /* Write Matching CH Control * + status += MXL_ControlWrite_Group(fe, ControlNum, value, 1); /* Write Matching INIT Control */ + status += MXL_ControlWrite_Group(fe, ControlNum, value, 2); /* Write Matching CH Control */ #ifdef _MXL_INTERNAL - status += MXL_ControlWrite_Group(fe, ControlNum, value, 3); /* Write Matching MXL Control * + status += MXL_ControlWrite_Group(fe, ControlNum, value, 3); /* Write Matching MXL Control */ #endif return status; } @@ -3936,7 +3936,7 @@ u16 MXL_ControlWrite(struct dvb_frontend *fe, u16 ControlNum, u32 value) // DONE u16 MXL_ControlWrite_Group(struct dvb_frontend *fe, u16 controlNum, u32 value, u16 controlGroup) { - struct mxl5005s_state *state = fe->demodulator_priv; + struct mxl5005s_state *state = fe->tuner_priv; u16 i, j, k; u32 highLimit; u32 ctrlVal; @@ -4043,7 +4043,7 @@ u16 MXL_ControlWrite_Group(struct dvb_frontend *fe, u16 controlNum, u32 value, u // DONE u16 MXL_RegWrite(struct dvb_frontend *fe, u8 RegNum, u8 RegVal) { - struct mxl5005s_state *state = fe->demodulator_priv; + struct mxl5005s_state *state = fe->tuner_priv; int i ; for (i = 0; i < 104; i++) { @@ -4083,7 +4083,7 @@ u16 MXL_RegWrite(struct dvb_frontend *fe, u8 RegNum, u8 RegVal) // DONE u16 MXL_RegRead(struct dvb_frontend *fe, u8 RegNum, u8 *RegVal) { - struct mxl5005s_state *state = fe->demodulator_priv; + struct mxl5005s_state *state = fe->tuner_priv; int i ; for (i = 0; i < 104; i++) { @@ -4118,9 +4118,9 @@ u16 MXL_RegRead(struct dvb_frontend *fe, u8 RegNum, u8 *RegVal) // // /////////////////////////////////////////////////////////////////////////////// // DONE -u16 MXL_ControlRead(struct dvb_frontend *fe, u16 controlNum, u32 * value) +u16 MXL_ControlRead(struct dvb_frontend *fe, u16 controlNum, u32 *value) { - struct mxl5005s_state *state = fe->demodulator_priv; + struct mxl5005s_state *state = fe->tuner_priv; u32 ctrlVal ; u16 i, k ; @@ -4192,7 +4192,7 @@ u16 MXL_ControlRead(struct dvb_frontend *fe, u16 controlNum, u32 * value) // DONE u16 MXL_ControlRegRead(struct dvb_frontend *fe, u16 controlNum, u8 *RegNum, int * count) { - struct mxl5005s_state *state = fe->demodulator_priv; + struct mxl5005s_state *state = fe->tuner_priv; u16 i, j, k ; u16 Count ; @@ -4298,7 +4298,7 @@ u16 MXL_ControlRegRead(struct dvb_frontend *fe, u16 controlNum, u8 *RegNum, int // DONE void MXL_RegWriteBit(struct dvb_frontend *fe, u8 address, u8 bit, u8 bitVal) { - struct mxl5005s_state *state = fe->demodulator_priv; + struct mxl5005s_state *state = fe->tuner_priv; int i ; const u8 AND_MAP[8] = { @@ -4355,7 +4355,6 @@ u32 MXL_Ceiling(u32 value, u32 resolution) // DONE u16 MXL_GetInitRegister(struct dvb_frontend *fe, u8 * RegNum, u8 *RegVal, int *count) { - struct mxl5005s_state *state = fe->demodulator_priv; u16 status = 0; int i ; @@ -4379,7 +4378,6 @@ u16 MXL_GetInitRegister(struct dvb_frontend *fe, u8 * RegNum, u8 *RegVal, int *c // DONE u16 MXL_GetCHRegister(struct dvb_frontend *fe, u8 * RegNum, u8 *RegVal, int *count) { - struct mxl5005s_state *state = fe->demodulator_priv; u16 status = 0; int i ; @@ -4408,7 +4406,6 @@ u16 MXL_GetCHRegister(struct dvb_frontend *fe, u8 * RegNum, u8 *RegVal, int *cou // DONE u16 MXL_GetCHRegister_ZeroIF(struct dvb_frontend *fe, u8 * RegNum, u8 *RegVal, int *count) { - struct mxl5005s_state *state = fe->demodulator_priv; u16 status = 0; int i; @@ -4427,7 +4424,6 @@ u16 MXL_GetCHRegister_ZeroIF(struct dvb_frontend *fe, u8 * RegNum, u8 *RegVal, i // DONE u16 MXL_GetCHRegister_LowIF(struct dvb_frontend *fe, u8 * RegNum, u8 *RegVal, int *count) { - struct mxl5005s_state *state = fe->demodulator_priv; u16 status = 0; int i; @@ -4461,7 +4457,7 @@ u16 MXL_GetMasterControl(u8 *MasterReg, int state) #ifdef _MXL_PRODUCTION u16 MXL_VCORange_Test(struct dvb_frontend *fe, int VCO_Range) { - struct mxl5005s_state *state = fe->demodulator_priv; + struct mxl5005s_state *state = fe->tuner_priv; u16 status = 0 ; if (VCO_Range == 1) { @@ -4591,7 +4587,7 @@ u16 MXL_VCORange_Test(struct dvb_frontend *fe, int VCO_Range) // DONE u16 MXL_Hystersis_Test(struct dvb_frontend *fe, int Hystersis) { - struct mxl5005s_state *state = fe->demodulator_priv; + struct mxl5005s_state *state = fe->tuner_priv; u16 status = 0; if (Hystersis == 1) @@ -4602,3 +4598,209 @@ u16 MXL_Hystersis_Test(struct dvb_frontend *fe, int Hystersis) #endif +/* Linux driver related functions */ + + +int mxl5005s_init2(struct dvb_frontend *fe) +{ + int MxlModMode; + int MxlIfMode; + unsigned long MxlBandwitdh; + unsigned long MxlIfFreqHz; + unsigned long MxlCrystalFreqHz; + int MxlAgcMode; + unsigned short MxlTop; + unsigned short MxlIfOutputLoad; + int MxlClockOut; + int MxlDivOut; + int MxlCapSel; + int MxlRssiOnOff; + unsigned char MxlStandard; + unsigned char MxlTfType; + + /* Set MxL5005S parameters. */ + MxlModMode = MXL_DIGITAL_MODE; + MxlIfMode = MXL_ZERO_IF; +// steve + //MxlBandwitdh = MXL5005S_BANDWIDTH_8MHZ; + //MxlIfFreqHz = IF_FREQ_4570000HZ; + MxlBandwitdh = MXL5005S_BANDWIDTH_6MHZ; // config + MxlIfFreqHz = IF_FREQ_5380000HZ; // config + MxlCrystalFreqHz = CRYSTAL_FREQ_16000000HZ; // config + MxlAgcMode = MXL_SINGLE_AGC; + MxlTop = MXL5005S_TOP_25P2; + MxlIfOutputLoad = MXL5005S_IF_OUTPUT_LOAD_200_OHM; + MxlClockOut = MXL_CLOCK_OUT_DISABLE; + MxlDivOut = MXL_DIV_OUT_4; + MxlCapSel = MXL_CAP_SEL_ENABLE; + MxlRssiOnOff = MXL_RSSI_ENABLE; // config + MxlTfType = MXL_TF_C_H; // config + +#if 1 + MxlStandard = MXL_ATSC; // config +#else + // Set MxL5005S parameters according to standard mode + switch(StandardMode) + { + default: + case MXL5005S_STANDARD_DVBT: + MxlStandard = MXL_DVBT; + break; + case MXL5005S_STANDARD_ATSC: + MxlStandard = MXL_ATSC; + break; + } +#endif + + // TODO: this is bad, it trashes other configs + // Set MxL5005S extra module. + //pExtra->AgcMasterByte = (MxlAgcMode == MXL_DUAL_AGC) ? 0x4 : 0x0; + + MXL5005_TunerConfig( + fe, + (unsigned char)MxlModMode, + (unsigned char)MxlIfMode, + MxlBandwitdh, + MxlIfFreqHz, + MxlCrystalFreqHz, + (unsigned char)MxlAgcMode, + MxlTop, + MxlIfOutputLoad, + (unsigned char)MxlClockOut, + (unsigned char)MxlDivOut, + (unsigned char)MxlCapSel, + (unsigned char)MxlRssiOnOff, + MxlStandard, MxlTfType); + + return 0; +} + +static int mxl5005s_set_params(struct dvb_frontend *fe, + struct dvb_frontend_parameters *params) +{ + u32 freq; + u32 bw; + + if (fe->ops.info.type == FE_OFDM) + bw = params->u.ofdm.bandwidth; + else + bw = MXL5005S_BANDWIDTH_6MHZ; + + freq = params->frequency; /* Hz */ + dprintk(1, "%s() freq=%d bw=%d\n", __func__, freq, bw); + + return mxl5005s_SetRfFreqHz(fe, freq); +} + +static int mxl5005s_get_frequency(struct dvb_frontend *fe, u32 *frequency) +{ + struct mxl5005s_state *state = fe->tuner_priv; + dprintk(1, "%s()\n", __func__); + + *frequency = state->RF_IN; + + return 0; +} + +static int mxl5005s_get_bandwidth(struct dvb_frontend *fe, u32 *bandwidth) +{ + struct mxl5005s_state *state = fe->tuner_priv; + dprintk(1, "%s()\n", __func__); + + *bandwidth = state->Chan_Bandwidth; + + return 0; +} + +static int mxl5005s_get_status(struct dvb_frontend *fe, u32 *status) +{ + dprintk(1, "%s()\n", __func__); + + *status = 0; + // *status = TUNER_STATUS_LOCKED; + + return 0; +} + +static int mxl5005s_init(struct dvb_frontend *fe) +{ + struct mxl5005s_state *state = fe->tuner_priv; + u8 AddrTable[MXL5005S_REG_WRITING_TABLE_LEN_MAX]; + u8 ByteTable[MXL5005S_REG_WRITING_TABLE_LEN_MAX]; + int TableLen; + + dprintk(1, "%s()\n", __func__); + + /* Initialize MxL5005S tuner according to MxL5005S tuner example code. */ + + /* Tuner initialization stage 0 */ + MXL_GetMasterControl(ByteTable, MC_SYNTH_RESET); + AddrTable[0] = MASTER_CONTROL_ADDR; + ByteTable[0] |= state->config->AgcMasterByte; + + mxl5005s_SetRegsWithTable(fe, AddrTable, ByteTable, 1); + + /* Tuner initialization stage 1 */ + MXL_GetInitRegister(fe, AddrTable, ByteTable, &TableLen); + + mxl5005s_SetRegsWithTable(fe, AddrTable, ByteTable, TableLen); + + return mxl5005s_init2(fe); +} + +static int mxl5005s_release(struct dvb_frontend *fe) +{ + dprintk(1, "%s()\n", __func__); + kfree(fe->tuner_priv); + fe->tuner_priv = NULL; + return 0; +} + +static const struct dvb_tuner_ops mxl5005s_tuner_ops = { + .info = { + .name = "MaxLinear MXL5005S", + .frequency_min = 48000000, + .frequency_max = 860000000, + .frequency_step = 50000, + }, + + .release = mxl5005s_release, + .init = mxl5005s_init, + + .set_params = mxl5005s_set_params, + .get_frequency = mxl5005s_get_frequency, + .get_bandwidth = mxl5005s_get_bandwidth, + .get_status = mxl5005s_get_status +}; + +struct dvb_frontend *mxl5005s_attach(struct dvb_frontend *fe, + struct i2c_adapter *i2c, + struct mxl5005s_config *config) +{ + struct mxl5005s_state *state = NULL; + dprintk(1, "%s()\n", __func__); + + state = kzalloc(sizeof(struct mxl5005s_state), GFP_KERNEL); + if (state == NULL) + return NULL; + + state->frontend = fe; + state->config = config; + state->i2c = i2c; + + printk(KERN_INFO "MXL5005S: Attached at address 0x%02x\n", config->i2c_address); + + memcpy(&fe->ops.tuner_ops, &mxl5005s_tuner_ops, sizeof(struct dvb_tuner_ops)); + + fe->tuner_priv = state; + return fe; +} +EXPORT_SYMBOL(mxl5005s_attach); + +MODULE_DESCRIPTION("MaxLinear MXL5005S silicon tuner driver"); +MODULE_AUTHOR("Jan Hoogenraad"); +MODULE_AUTHOR("Barnaby Shearer"); +MODULE_AUTHOR("Andy Hasper"); +MODULE_AUTHOR("Steven Toth"); +MODULE_LICENSE("GPL"); + diff --git a/linux/drivers/media/common/tuners/mxl5005s.h b/linux/drivers/media/common/tuners/mxl5005s.h index df4982681..1c4d9da8e 100644 --- a/linux/drivers/media/common/tuners/mxl5005s.h +++ b/linux/drivers/media/common/tuners/mxl5005s.h @@ -26,273 +26,48 @@ #ifndef __MXL5005S_H #define __MXL5005S_H -/* - * The following context is source code provided by MaxLinear. - * MaxLinear source code - Common.h - */ - -typedef void *HANDLE; /* Pointer to memory location */ - -#define TUNER_REGS_NUM 104 -#define INITCTRL_NUM 40 - -#ifdef _MXL_PRODUCTION -#define CHCTRL_NUM 39 -#else -#define CHCTRL_NUM 36 -#endif - -#define MXLCTRL_NUM 189 -#define MASTER_CONTROL_ADDR 9 - -/* Enumeration of AGC Mode */ -typedef enum -{ - MXL_DUAL_AGC = 0, - MXL_SINGLE_AGC -} AGC_Mode; - -/* Enumeration of Master Control Register State */ -typedef enum -{ - MC_LOAD_START = 1, - MC_POWER_DOWN, - MC_SYNTH_RESET, - MC_SEQ_OFF -} Master_Control_State; - -/* Enumeration of MXL5005 Tuner Mode */ -typedef enum -{ - MXL_ANALOG_MODE = 0, - MXL_DIGITAL_MODE -} Tuner_Mode; - -/* Enumeration of MXL5005 Tuner IF Mode */ -typedef enum -{ - MXL_ZERO_IF = 0, - MXL_LOW_IF -} Tuner_IF_Mode; - -/* Enumeration of MXL5005 Tuner Clock Out Mode */ -typedef enum -{ - MXL_CLOCK_OUT_DISABLE = 0, - MXL_CLOCK_OUT_ENABLE -} Tuner_Clock_Out; - -/* Enumeration of MXL5005 Tuner Div Out Mode */ -typedef enum -{ - MXL_DIV_OUT_1 = 0, - MXL_DIV_OUT_4 - -} Tuner_Div_Out; - -/* Enumeration of MXL5005 Tuner Pull-up Cap Select Mode */ -typedef enum -{ - MXL_CAP_SEL_DISABLE = 0, - MXL_CAP_SEL_ENABLE - -} Tuner_Cap_Select; - -/* Enumeration of MXL5005 Tuner RSSI Mode */ -typedef enum -{ - MXL_RSSI_DISABLE = 0, - MXL_RSSI_ENABLE - -} Tuner_RSSI; - -/* Enumeration of MXL5005 Tuner Modulation Type */ -typedef enum -{ - MXL_DEFAULT_MODULATION = 0, - MXL_DVBT, - MXL_ATSC, - MXL_QAM, - MXL_ANALOG_CABLE, - MXL_ANALOG_OTA -} Tuner_Modu_Type; - -/* Enumeration of MXL5005 Tuner Tracking Filter Type */ -typedef enum -{ - MXL_TF_DEFAULT = 0, - MXL_TF_OFF, - MXL_TF_C, - MXL_TF_C_H, - MXL_TF_D, - MXL_TF_D_L, - MXL_TF_E, - MXL_TF_F, - MXL_TF_E_2, - MXL_TF_E_NA, - MXL_TF_G -} Tuner_TF_Type; - -/* MXL5005 Tuner Register Struct */ -typedef struct _TunerReg_struct -{ - u16 Reg_Num; /* Tuner Register Address */ - u16 Reg_Val; /* Current sofware programmed value waiting to be writen */ -} TunerReg_struct; - -typedef enum -{ - /* Initialization Control Names */ - DN_IQTN_AMP_CUT = 1, /* 1 */ - BB_MODE, /* 2 */ - BB_BUF, /* 3 */ - BB_BUF_OA, /* 4 */ - BB_ALPF_BANDSELECT, /* 5 */ - BB_IQSWAP, /* 6 */ - BB_DLPF_BANDSEL, /* 7 */ - RFSYN_CHP_GAIN, /* 8 */ - RFSYN_EN_CHP_HIGAIN, /* 9 */ - AGC_IF, /* 10 */ - AGC_RF, /* 11 */ - IF_DIVVAL, /* 12 */ - IF_VCO_BIAS, /* 13 */ - CHCAL_INT_MOD_IF, /* 14 */ - CHCAL_FRAC_MOD_IF, /* 15 */ - DRV_RES_SEL, /* 16 */ - I_DRIVER, /* 17 */ - EN_AAF, /* 18 */ - EN_3P, /* 19 */ - EN_AUX_3P, /* 20 */ - SEL_AAF_BAND, /* 21 */ - SEQ_ENCLK16_CLK_OUT, /* 22 */ - SEQ_SEL4_16B, /* 23 */ - XTAL_CAPSELECT, /* 24 */ - IF_SEL_DBL, /* 25 */ - RFSYN_R_DIV, /* 26 */ - SEQ_EXTSYNTHCALIF, /* 27 */ - SEQ_EXTDCCAL, /* 28 */ - AGC_EN_RSSI, /* 29 */ - RFA_ENCLKRFAGC, /* 30 */ - RFA_RSSI_REFH, /* 31 */ - RFA_RSSI_REF, /* 32 */ - RFA_RSSI_REFL, /* 33 */ - RFA_FLR, /* 34 */ - RFA_CEIL, /* 35 */ - SEQ_EXTIQFSMPULSE, /* 36 */ - OVERRIDE_1, /* 37 */ - BB_INITSTATE_DLPF_TUNE, /* 38 */ - TG_R_DIV, /* 39 */ - EN_CHP_LIN_B, /* 40 */ - - /* Channel Change Control Names */ - DN_POLY = 51, /* 51 */ - DN_RFGAIN, /* 52 */ - DN_CAP_RFLPF, /* 53 */ - DN_EN_VHFUHFBAR, /* 54 */ - DN_GAIN_ADJUST, /* 55 */ - DN_IQTNBUF_AMP, /* 56 */ - DN_IQTNGNBFBIAS_BST, /* 57 */ - RFSYN_EN_OUTMUX, /* 58 */ - RFSYN_SEL_VCO_OUT, /* 59 */ - RFSYN_SEL_VCO_HI, /* 60 */ - RFSYN_SEL_DIVM, /* 61 */ - RFSYN_RF_DIV_BIAS, /* 62 */ - DN_SEL_FREQ, /* 63 */ - RFSYN_VCO_BIAS, /* 64 */ - CHCAL_INT_MOD_RF, /* 65 */ - CHCAL_FRAC_MOD_RF, /* 66 */ - RFSYN_LPF_R, /* 67 */ - CHCAL_EN_INT_RF, /* 68 */ - TG_LO_DIVVAL, /* 69 */ - TG_LO_SELVAL, /* 70 */ - TG_DIV_VAL, /* 71 */ - TG_VCO_BIAS, /* 72 */ - SEQ_EXTPOWERUP, /* 73 */ - OVERRIDE_2, /* 74 */ - OVERRIDE_3, /* 75 */ - OVERRIDE_4, /* 76 */ - SEQ_FSM_PULSE, /* 77 */ - GPIO_4B, /* 78 */ - GPIO_3B, /* 79 */ - GPIO_4, /* 80 */ - GPIO_3, /* 81 */ - GPIO_1B, /* 82 */ - DAC_A_ENABLE, /* 83 */ - DAC_B_ENABLE, /* 84 */ - DAC_DIN_A, /* 85 */ - DAC_DIN_B, /* 86 */ -#ifdef _MXL_PRODUCTION - RFSYN_EN_DIV, /* 87 */ - RFSYN_DIVM, /* 88 */ - DN_BYPASS_AGC_I2C /* 89 */ -#endif -} MXL5005_ControlName; - -/* End of common.h */ - -/* - * The following context is source code provided by MaxLinear. - * MaxLinear source code - Common_MXL.h (?) - */ - -/* Constants */ -#define MXL5005S_REG_WRITING_TABLE_LEN_MAX 104 -#define MXL5005S_LATCH_BYTE 0xfe - -/* Register address, MSB, and LSB */ -#define MXL5005S_BB_IQSWAP_ADDR 59 -#define MXL5005S_BB_IQSWAP_MSB 0 -#define MXL5005S_BB_IQSWAP_LSB 0 - -#define MXL5005S_BB_DLPF_BANDSEL_ADDR 53 -#define MXL5005S_BB_DLPF_BANDSEL_MSB 4 -#define MXL5005S_BB_DLPF_BANDSEL_LSB 3 - -/* Standard modes */ -enum -{ - MXL5005S_STANDARD_DVBT, - MXL5005S_STANDARD_ATSC, +/* IF frequency */ +enum IF_FREQ_HZ +{ + IF_FREQ_4570000HZ = 4570000, ///< IF frequency = 4.57 MHz + IF_FREQ_4571429HZ = 4571429, ///< IF frequency = 4.571 MHz + IF_FREQ_5380000HZ = 5380000, ///< IF frequency = 5.38 MHz + IF_FREQ_36000000HZ = 36000000, ///< IF frequency = 36.000 MHz + IF_FREQ_36125000HZ = 36125000, ///< IF frequency = 36.125 MHz + IF_FREQ_36166667HZ = 36166667, ///< IF frequency = 36.167 MHz + IF_FREQ_44000000HZ = 44000000, ///< IF frequency = 44.000 MHz }; -#define MXL5005S_STANDARD_MODE_NUM 2 -/* Bandwidth modes */ -enum +/* Crystal frequency */ +enum CRYSTAL_FREQ_HZ { - MXL5005S_BANDWIDTH_6MHZ = 6000000, - MXL5005S_BANDWIDTH_7MHZ = 7000000, - MXL5005S_BANDWIDTH_8MHZ = 8000000, + CRYSTAL_FREQ_4000000HZ = 4000000, ///< Crystal frequency = 4.0 MHz + CRYSTAL_FREQ_16000000HZ = 16000000, ///< Crystal frequency = 16.0 MHz + CRYSTAL_FREQ_25000000HZ = 25000000, ///< Crystal frequency = 25.0 MHz + CRYSTAL_FREQ_28800000HZ = 28800000, ///< Crystal frequency = 28.8 MHz }; -#define MXL5005S_BANDWIDTH_MODE_NUM 3 -/* Top modes */ -enum +struct mxl5005s_config { - MXL5005S_TOP_5P5 = 55, - MXL5005S_TOP_7P2 = 72, - MXL5005S_TOP_9P2 = 92, - MXL5005S_TOP_11P0 = 110, - MXL5005S_TOP_12P9 = 129, - MXL5005S_TOP_14P7 = 147, - MXL5005S_TOP_16P8 = 168, - MXL5005S_TOP_19P4 = 194, - MXL5005S_TOP_21P2 = 212, - MXL5005S_TOP_23P2 = 232, - MXL5005S_TOP_25P2 = 252, - MXL5005S_TOP_27P1 = 271, - MXL5005S_TOP_29P2 = 292, - MXL5005S_TOP_31P7 = 317, - MXL5005S_TOP_34P9 = 349, -}; + u8 i2c_address; -/* IF output load */ -enum -{ - MXL5005S_IF_OUTPUT_LOAD_200_OHM = 200, - MXL5005S_IF_OUTPUT_LOAD_300_OHM = 300, + /* Stuff I don't know what to do with */ + u8 AgcMasterByte; }; -/* End of common_mxl.h (?) */ +#if defined(CONFIG_DVB_TUNER_MXL5005S) || (defined(CONFIG_DVB_TUNER_MXL5005S_MODULE) && defined(MODULE)) +extern struct dvb_frontend *mxl5005s_attach(struct dvb_frontend *fe, + struct i2c_adapter *i2c, + struct mxl5005s_config *config); +#else +static inline struct dvb_frontend *mxl5005s_attach(struct dvb_frontend *fe, + struct i2c_adapter *i2c, + struct mxl5005s_config *config); +{ + printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__); + return NULL; +} +#endif /* CONFIG_DVB_TUNER_MXL5005S */ #endif /* __MXL5005S_H */ -- cgit v1.2.3 From ffa5b431c2adb2f0fc064a03587e94ebe8294820 Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Thu, 1 May 2008 02:35:48 -0400 Subject: mxl5005s: Cleanup #5 From: Steven Toth Cleanup #5 Signed-off-by: Steven Toth Signed-off-by: Mauro Carvalho Chehab --- linux/drivers/media/common/tuners/mxl5005s.c | 328 +++++++++------------------ linux/drivers/media/common/tuners/mxl5005s.h | 99 ++++++-- 2 files changed, 182 insertions(+), 245 deletions(-) (limited to 'linux/drivers/media/common/tuners') diff --git a/linux/drivers/media/common/tuners/mxl5005s.c b/linux/drivers/media/common/tuners/mxl5005s.c index 8a20a8657..cdc1ab225 100644 --- a/linux/drivers/media/common/tuners/mxl5005s.c +++ b/linux/drivers/media/common/tuners/mxl5005s.c @@ -24,10 +24,10 @@ #include "mxl5005s.h" -static int debug; +static int debug = 2; #define dprintk(level, arg...) do { \ - if (debug >= level) \ + if (level <= debug) \ printk(arg); \ } while (0) @@ -43,13 +43,6 @@ static int debug; #define MXLCTRL_NUM 189 #define MASTER_CONTROL_ADDR 9 -/* Enumeration of AGC Mode */ -typedef enum -{ - MXL_DUAL_AGC = 0, - MXL_SINGLE_AGC -} AGC_Mode; - /* Enumeration of Master Control Register State */ typedef enum { @@ -59,51 +52,6 @@ typedef enum MC_SEQ_OFF } Master_Control_State; -/* Enumeration of MXL5005 Tuner Mode */ -typedef enum -{ - MXL_ANALOG_MODE = 0, - MXL_DIGITAL_MODE -} Tuner_Mode; - -/* Enumeration of MXL5005 Tuner IF Mode */ -typedef enum -{ - MXL_ZERO_IF = 0, - MXL_LOW_IF -} Tuner_IF_Mode; - -/* Enumeration of MXL5005 Tuner Clock Out Mode */ -typedef enum -{ - MXL_CLOCK_OUT_DISABLE = 0, - MXL_CLOCK_OUT_ENABLE -} Tuner_Clock_Out; - -/* Enumeration of MXL5005 Tuner Div Out Mode */ -typedef enum -{ - MXL_DIV_OUT_1 = 0, - MXL_DIV_OUT_4 - -} Tuner_Div_Out; - -/* Enumeration of MXL5005 Tuner Pull-up Cap Select Mode */ -typedef enum -{ - MXL_CAP_SEL_DISABLE = 0, - MXL_CAP_SEL_ENABLE - -} Tuner_Cap_Select; - -/* Enumeration of MXL5005 Tuner RSSI Mode */ -typedef enum -{ - MXL_RSSI_DISABLE = 0, - MXL_RSSI_ENABLE - -} Tuner_RSSI; - /* Enumeration of MXL5005 Tuner Modulation Type */ typedef enum { @@ -115,22 +63,6 @@ typedef enum MXL_ANALOG_OTA } Tuner_Modu_Type; -/* Enumeration of MXL5005 Tuner Tracking Filter Type */ -typedef enum -{ - MXL_TF_DEFAULT = 0, - MXL_TF_OFF, - MXL_TF_C, - MXL_TF_C_H, - MXL_TF_D, - MXL_TF_D_L, - MXL_TF_E, - MXL_TF_F, - MXL_TF_E_2, - MXL_TF_E_NA, - MXL_TF_G -} Tuner_TF_Type; - /* MXL5005 Tuner Register Struct */ typedef struct _TunerReg_struct { @@ -261,33 +193,6 @@ enum }; #define MXL5005S_BANDWIDTH_MODE_NUM 3 -/* Top modes */ -enum -{ - MXL5005S_TOP_5P5 = 55, - MXL5005S_TOP_7P2 = 72, - MXL5005S_TOP_9P2 = 92, - MXL5005S_TOP_11P0 = 110, - MXL5005S_TOP_12P9 = 129, - MXL5005S_TOP_14P7 = 147, - MXL5005S_TOP_16P8 = 168, - MXL5005S_TOP_19P4 = 194, - MXL5005S_TOP_21P2 = 212, - MXL5005S_TOP_23P2 = 232, - MXL5005S_TOP_25P2 = 252, - MXL5005S_TOP_27P1 = 271, - MXL5005S_TOP_29P2 = 292, - MXL5005S_TOP_31P7 = 317, - MXL5005S_TOP_34P9 = 349, -}; - -/* IF output load */ -enum -{ - MXL5005S_IF_OUTPUT_LOAD_200_OHM = 200, - MXL5005S_IF_OUTPUT_LOAD_300_OHM = 300, -}; - /* MXL5005 Tuner Control Struct */ typedef struct _TunerControl_struct { u16 Ctrl_Num; /* Control Number */ @@ -342,8 +247,7 @@ struct mxl5005s_state TunerRegs[TUNER_REGS_NUM]; /* Tuner Register Array Pointer */ /* Linux driver framework specific */ - const struct mxl5005s_config *config; - + struct mxl5005s_config *config; struct dvb_frontend *frontend; struct i2c_adapter *i2c; }; @@ -367,11 +271,11 @@ void MXL_SynthRFTGLO_Calc(struct dvb_frontend *fe); u16 MXL_GetCHRegister_ZeroIF(struct dvb_frontend *fe, u8 *RegNum, u8 *RegVal, int *count); int mxl5005s_SetRegsWithTable(struct dvb_frontend *fe, u8 *pAddrTable, u8 *pByteTable, int TableLen); u16 MXL_IFSynthInit(struct dvb_frontend *fe); +int mxl5005s_AssignTunerMode(struct dvb_frontend *fe); int mxl5005s_SetRfFreqHz(struct dvb_frontend *fe, unsigned long RfFreqHz) { struct mxl5005s_state *state = fe->tuner_priv; - u8 AgcMasterByte = state->config->AgcMasterByte; unsigned char AddrTable[MXL5005S_REG_WRITING_TABLE_LEN_MAX]; unsigned char ByteTable[MXL5005S_REG_WRITING_TABLE_LEN_MAX]; int TableLen; @@ -402,13 +306,13 @@ int mxl5005s_SetRfFreqHz(struct dvb_frontend *fe, unsigned long RfFreqHz) MXL_GetMasterControl(&MasterControlByte, MC_LOAD_START) ; AddrTable[TableLen] = MASTER_CONTROL_ADDR ; - ByteTable[TableLen] = MasterControlByte | AgcMasterByte; + ByteTable[TableLen] = MasterControlByte | state->config->AgcMasterByte; TableLen += 1; mxl5005s_SetRegsWithTable(fe, AddrTable, ByteTable, TableLen); // Wait 30 ms. - msleep(30); + msleep(150); // Tuner RF frequency setting stage 2 MXL_ControlWrite(fe, SEQ_FSM_PULSE, 1) ; @@ -417,39 +321,56 @@ int mxl5005s_SetRfFreqHz(struct dvb_frontend *fe, unsigned long RfFreqHz) MXL_GetMasterControl(&MasterControlByte, MC_LOAD_START) ; AddrTable[TableLen] = MASTER_CONTROL_ADDR ; - ByteTable[TableLen] = MasterControlByte | AgcMasterByte ; + ByteTable[TableLen] = MasterControlByte | state->config->AgcMasterByte ; TableLen += 1; mxl5005s_SetRegsWithTable(fe, AddrTable, ByteTable, TableLen); + msleep(100); + return 0; } -/* Write a single byte to a single reg */ -static int mxl5005s_writereg(struct dvb_frontend *fe, u8 reg, u8 val) +static int mxl5005s_reset(struct dvb_frontend *fe) { struct mxl5005s_state *state = fe->tuner_priv; - u8 buf[2] = { reg, val }; + int ret = 0; + + u8 buf[2] = { 0xff, 0x00 }; struct i2c_msg msg = { .addr = state->config->i2c_address, .flags = 0, .buf = buf, .len = 2 }; + dprintk(2, "%s()\n", __func__); + + if (fe->ops.i2c_gate_ctrl) + fe->ops.i2c_gate_ctrl(fe, 1); + if (i2c_transfer(state->i2c, &msg, 1) != 1) { - printk(KERN_WARNING "mxl5005s I2C write failed\n"); - return -EREMOTEIO; + printk(KERN_WARNING "mxl5005s I2C reset failed\n"); + ret = -EREMOTEIO; } - return 0; + + if (fe->ops.i2c_gate_ctrl) + fe->ops.i2c_gate_ctrl(fe, 0); + + return ret; } -/* Write a word to a single reg */ -static int mxl5005s_writereg16(struct dvb_frontend *fe, u8 reg, u16 val) +/* Write a single byte to a single reg */ +static int mxl5005s_writereg(struct dvb_frontend *fe, u8 reg, u8 val, int latch) { struct mxl5005s_state *state = fe->tuner_priv; - u8 buf[3] = { reg, val >> 8 , val & 0xff }; + u8 buf[3] = { reg, val, MXL5005S_LATCH_BYTE }; struct i2c_msg msg = { .addr = state->config->i2c_address, .flags = 0, .buf = buf, .len = 3 }; + if(latch == 0) + msg.len = 2; + + dprintk(2, "%s(reg = 0x%x val = 0x%x addr = 0x%x)\n", __func__, reg, val, msg.addr); + if (i2c_transfer(state->i2c, &msg, 1) != 1) { - printk(KERN_WARNING "mxl5005s I2C write16 failed\n"); + printk(KERN_WARNING "mxl5005s I2C write failed\n"); return -EREMOTEIO; } return 0; @@ -457,30 +378,22 @@ static int mxl5005s_writereg16(struct dvb_frontend *fe, u8 reg, u16 val) int mxl5005s_SetRegsWithTable(struct dvb_frontend *fe, u8 *pAddrTable, u8 *pByteTable, int TableLen) { - int i, ret; - u8 end_two_bytes_buf[]={ 0 , 0 }; + int i, ret = 0; + + if (fe->ops.i2c_gate_ctrl) + fe->ops.i2c_gate_ctrl(fe, 1); for( i = 0 ; i < TableLen - 1 ; i++) { -#if 0 - if ( TUNER_WI2C(dib , tuner_addr , pAddrTable[i] , &pByteTable[i] , 1 ) ) - return FUNCTION_ERROR; -#else - ret = mxl5005s_writereg(fe, pAddrTable[i], pByteTable[i]); - if (!ret) - return ret; -#endif + ret = mxl5005s_writereg(fe, pAddrTable[i], pByteTable[i], 0); + if (ret < 0) + break; } - end_two_bytes_buf[0] = pByteTable[i]; - end_two_bytes_buf[1] = MXL5005S_LATCH_BYTE; + ret = mxl5005s_writereg(fe, pAddrTable[i], pByteTable[i], 1); -#if 0 - if ( TUNER_WI2C(dib , tuner_addr , pAddrTable[i] , end_two_bytes_buf , 2 ) ) - return FUNCTION_ERROR; -#else - ret = mxl5005s_writereg16(fe, pAddrTable[i], (end_two_bytes_buf[0] << 8) | end_two_bytes_buf[1]); -#endif + if (fe->ops.i2c_gate_ctrl) + fe->ops.i2c_gate_ctrl(fe, 0); return ret; } @@ -518,6 +431,7 @@ int mxl5005s_SetRegMaskBits(struct dvb_frontend *fe, /* Write tuner register byte with writing byte. */ return mxl5005s_SetRegsWithTable(fe, &RegAddr, &RegByte, 1); } + #if 0 // DONE int mxl5005s_SetSpectrumMode(struct dvb_frontend *fe, int SpectrumMode) @@ -2100,6 +2014,7 @@ u16 MXL_BlockInit(struct dvb_frontend *fe) status += MXL_ControlWrite(fe, BB_DLPF_BANDSEL, 2); break; case 6000000: + printk("%s() doing 6MHz digital\n", __func__); status += MXL_ControlWrite(fe, BB_DLPF_BANDSEL, 3); break; } @@ -2130,7 +2045,6 @@ u16 MXL_BlockInit(struct dvb_frontend *fe) else /* Single AGC Mode Dig Ana */ status += MXL_ControlWrite(fe, AGC_RF, state->Mode ? 15 : 12); - if (state->TOP == 55) /* TOP == 5.5 */ status += MXL_ControlWrite(fe, AGC_IF, 0x0); @@ -2360,6 +2274,10 @@ u16 MXL_BlockInit(struct dvb_frontend *fe) status += MXL_ControlWrite(fe, BB_IQSWAP, 0); else /* High IF */ status += MXL_ControlWrite(fe, BB_IQSWAP, 1); +#if 1 + status += MXL_ControlWrite(fe, RFSYN_CHP_GAIN, 2); +#endif + } if (state->Mod_Type == MXL_ANALOG_CABLE) { /* Analog Cable Mode */ @@ -2396,7 +2314,7 @@ u16 MXL_BlockInit(struct dvb_frontend *fe) } /* RSSI disable */ - if(state->EN_RSSI==0) { + if(state->EN_RSSI == 0) { status += MXL_ControlWrite(fe, SEQ_EXTSYNTHCALIF, 1); status += MXL_ControlWrite(fe, SEQ_EXTDCCAL, 1); status += MXL_ControlWrite(fe, AGC_EN_RSSI, 0); @@ -2605,6 +2523,7 @@ u16 MXL_IFSynthInit(struct dvb_frontend *fe) Fref = 324000000UL ; } if (state->IF_LO == 5380000UL) { + printk("%s() doing 5.38\n", __func__); status += MXL_ControlWrite(fe, IF_DIVVAL, 0x07) ; status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C) ; Fref = 322800000UL ; @@ -3287,6 +3206,7 @@ u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq) if (state->TF_Type == MXL_TF_C_H) // Tracking Filter type C-H for Hauppauge only { + printk("%s() CH filter\n", __func__); status += MXL_ControlWrite(fe, DAC_DIN_A, 0) ; if (state->RF_IN >= 43000000 && state->RF_IN < 150000000) @@ -4600,77 +4520,59 @@ u16 MXL_Hystersis_Test(struct dvb_frontend *fe, int Hystersis) /* Linux driver related functions */ - -int mxl5005s_init2(struct dvb_frontend *fe) +int mxl5005s_init(struct dvb_frontend *fe) { - int MxlModMode; - int MxlIfMode; - unsigned long MxlBandwitdh; - unsigned long MxlIfFreqHz; - unsigned long MxlCrystalFreqHz; - int MxlAgcMode; - unsigned short MxlTop; - unsigned short MxlIfOutputLoad; - int MxlClockOut; - int MxlDivOut; - int MxlCapSel; - int MxlRssiOnOff; - unsigned char MxlStandard; - unsigned char MxlTfType; + struct mxl5005s_state *state = fe->tuner_priv; - /* Set MxL5005S parameters. */ - MxlModMode = MXL_DIGITAL_MODE; - MxlIfMode = MXL_ZERO_IF; -// steve - //MxlBandwitdh = MXL5005S_BANDWIDTH_8MHZ; - //MxlIfFreqHz = IF_FREQ_4570000HZ; - MxlBandwitdh = MXL5005S_BANDWIDTH_6MHZ; // config - MxlIfFreqHz = IF_FREQ_5380000HZ; // config - MxlCrystalFreqHz = CRYSTAL_FREQ_16000000HZ; // config - MxlAgcMode = MXL_SINGLE_AGC; - MxlTop = MXL5005S_TOP_25P2; - MxlIfOutputLoad = MXL5005S_IF_OUTPUT_LOAD_200_OHM; - MxlClockOut = MXL_CLOCK_OUT_DISABLE; - MxlDivOut = MXL_DIV_OUT_4; - MxlCapSel = MXL_CAP_SEL_ENABLE; - MxlRssiOnOff = MXL_RSSI_ENABLE; // config - MxlTfType = MXL_TF_C_H; // config + u8 AddrTable[MXL5005S_REG_WRITING_TABLE_LEN_MAX]; + u8 ByteTable[MXL5005S_REG_WRITING_TABLE_LEN_MAX]; + int TableLen; -#if 1 - MxlStandard = MXL_ATSC; // config -#else - // Set MxL5005S parameters according to standard mode - switch(StandardMode) - { - default: - case MXL5005S_STANDARD_DVBT: - MxlStandard = MXL_DVBT; - break; - case MXL5005S_STANDARD_ATSC: - MxlStandard = MXL_ATSC; - break; - } -#endif + dprintk(1, "%s()\n", __func__); + + mxl5005s_reset(fe); - // TODO: this is bad, it trashes other configs - // Set MxL5005S extra module. - //pExtra->AgcMasterByte = (MxlAgcMode == MXL_DUAL_AGC) ? 0x4 : 0x0; + /* Tuner initialization stage 0 */ + MXL_GetMasterControl(ByteTable, MC_SYNTH_RESET); + AddrTable[0] = MASTER_CONTROL_ADDR; + ByteTable[0] |= state->config->AgcMasterByte; + + mxl5005s_SetRegsWithTable(fe, AddrTable, ByteTable, 1); + + mxl5005s_AssignTunerMode(fe); // tunre_config + + /* Tuner initialization stage 1 */ + MXL_GetInitRegister(fe, AddrTable, ByteTable, &TableLen); + + mxl5005s_SetRegsWithTable(fe, AddrTable, ByteTable, TableLen); + return 0; +} + +int mxl5005s_AssignTunerMode(struct dvb_frontend *fe) +{ + struct mxl5005s_state *state = fe->tuner_priv; + struct mxl5005s_config *c = state->config; + + InitTunerControls(fe); + + /* Set MxL5005S parameters. */ MXL5005_TunerConfig( fe, - (unsigned char)MxlModMode, - (unsigned char)MxlIfMode, - MxlBandwitdh, - MxlIfFreqHz, - MxlCrystalFreqHz, - (unsigned char)MxlAgcMode, - MxlTop, - MxlIfOutputLoad, - (unsigned char)MxlClockOut, - (unsigned char)MxlDivOut, - (unsigned char)MxlCapSel, - (unsigned char)MxlRssiOnOff, - MxlStandard, MxlTfType); + c->mod_mode, + c->if_mode, + MXL5005S_BANDWIDTH_6MHZ, + c->if_freq, + c->xtal_freq, + c->agc_mode, + c->top, + c->output_load, + c->clock_out, + c->div_out, + c->cap_select, + c->rssi_enable, + MXL_QAM, + c->tracking_filter); return 0; } @@ -4689,7 +4591,11 @@ static int mxl5005s_set_params(struct dvb_frontend *fe, freq = params->frequency; /* Hz */ dprintk(1, "%s() freq=%d bw=%d\n", __func__, freq, bw); - return mxl5005s_SetRfFreqHz(fe, freq); + mxl5005s_SetRfFreqHz(fe, freq); + + msleep(350); + + return 0; } static int mxl5005s_get_frequency(struct dvb_frontend *fe, u32 *frequency) @@ -4722,32 +4628,6 @@ static int mxl5005s_get_status(struct dvb_frontend *fe, u32 *status) return 0; } -static int mxl5005s_init(struct dvb_frontend *fe) -{ - struct mxl5005s_state *state = fe->tuner_priv; - u8 AddrTable[MXL5005S_REG_WRITING_TABLE_LEN_MAX]; - u8 ByteTable[MXL5005S_REG_WRITING_TABLE_LEN_MAX]; - int TableLen; - - dprintk(1, "%s()\n", __func__); - - /* Initialize MxL5005S tuner according to MxL5005S tuner example code. */ - - /* Tuner initialization stage 0 */ - MXL_GetMasterControl(ByteTable, MC_SYNTH_RESET); - AddrTable[0] = MASTER_CONTROL_ADDR; - ByteTable[0] |= state->config->AgcMasterByte; - - mxl5005s_SetRegsWithTable(fe, AddrTable, ByteTable, 1); - - /* Tuner initialization stage 1 */ - MXL_GetInitRegister(fe, AddrTable, ByteTable, &TableLen); - - mxl5005s_SetRegsWithTable(fe, AddrTable, ByteTable, TableLen); - - return mxl5005s_init2(fe); -} - static int mxl5005s_release(struct dvb_frontend *fe) { dprintk(1, "%s()\n", __func__); diff --git a/linux/drivers/media/common/tuners/mxl5005s.h b/linux/drivers/media/common/tuners/mxl5005s.h index 1c4d9da8e..2777ecc20 100644 --- a/linux/drivers/media/common/tuners/mxl5005s.h +++ b/linux/drivers/media/common/tuners/mxl5005s.h @@ -26,31 +26,88 @@ #ifndef __MXL5005S_H #define __MXL5005S_H -/* IF frequency */ -enum IF_FREQ_HZ -{ - IF_FREQ_4570000HZ = 4570000, ///< IF frequency = 4.57 MHz - IF_FREQ_4571429HZ = 4571429, ///< IF frequency = 4.571 MHz - IF_FREQ_5380000HZ = 5380000, ///< IF frequency = 5.38 MHz - IF_FREQ_36000000HZ = 36000000, ///< IF frequency = 36.000 MHz - IF_FREQ_36125000HZ = 36125000, ///< IF frequency = 36.125 MHz - IF_FREQ_36166667HZ = 36166667, ///< IF frequency = 36.167 MHz - IF_FREQ_44000000HZ = 44000000, ///< IF frequency = 44.000 MHz -}; - -/* Crystal frequency */ -enum CRYSTAL_FREQ_HZ -{ - CRYSTAL_FREQ_4000000HZ = 4000000, ///< Crystal frequency = 4.0 MHz - CRYSTAL_FREQ_16000000HZ = 16000000, ///< Crystal frequency = 16.0 MHz - CRYSTAL_FREQ_25000000HZ = 25000000, ///< Crystal frequency = 25.0 MHz - CRYSTAL_FREQ_28800000HZ = 28800000, ///< Crystal frequency = 28.8 MHz -}; - struct mxl5005s_config { + /* 7 bit i2c address */ u8 i2c_address; +#define IF_FREQ_4570000HZ 4570000 +#define IF_FREQ_4571429HZ 4571429 +#define IF_FREQ_5380000HZ 5380000 +#define IF_FREQ_36000000HZ 36000000 +#define IF_FREQ_36125000HZ 36125000 +#define IF_FREQ_36166667HZ 36166667 +#define IF_FREQ_44000000HZ 44000000 + u32 if_freq; + +#define CRYSTAL_FREQ_4000000HZ 4000000 +#define CRYSTAL_FREQ_16000000HZ 16000000 +#define CRYSTAL_FREQ_25000000HZ 25000000 +#define CRYSTAL_FREQ_28800000HZ 28800000 + u32 xtal_freq; + +#define MXL_DUAL_AGC 0 +#define MXL_SINGLE_AGC 1 + u8 agc_mode; + +#define MXL_TF_DEFAULT 0 +#define MXL_TF_OFF 1 +#define MXL_TF_C 2 +#define MXL_TF_C_H 3 +#define MXL_TF_D 4 +#define MXL_TF_D_L 5 +#define MXL_TF_E 6 +#define MXL_TF_F 7 +#define MXL_TF_E_2 8 +#define MXL_TF_E_NA 9 +#define MXL_TF_G 10 + u8 tracking_filter; + +#define MXL_RSSI_DISABLE 0 +#define MXL_RSSI_ENABLE 1 + u8 rssi_enable; + +#define MXL_CAP_SEL_DISABLE 0 +#define MXL_CAP_SEL_ENABLE 1 + u8 cap_select; + +#define MXL_DIV_OUT_1 0 +#define MXL_DIV_OUT_4 1 + u8 div_out; + +#define MXL_CLOCK_OUT_DISABLE 0 +#define MXL_CLOCK_OUT_ENABLE 1 + u8 clock_out; + +#define MXL5005S_IF_OUTPUT_LOAD_200_OHM 200 +#define MXL5005S_IF_OUTPUT_LOAD_300_OHM 300 + u32 output_load; + +#define MXL5005S_TOP_5P5 55 +#define MXL5005S_TOP_7P2 72 +#define MXL5005S_TOP_9P2 92 +#define MXL5005S_TOP_11P0 110 +#define MXL5005S_TOP_12P9 129 +#define MXL5005S_TOP_14P7 147 +#define MXL5005S_TOP_16P8 168 +#define MXL5005S_TOP_19P4 194 +#define MXL5005S_TOP_21P2 212 +#define MXL5005S_TOP_23P2 232 +#define MXL5005S_TOP_25P2 252 +#define MXL5005S_TOP_27P1 271 +#define MXL5005S_TOP_29P2 292 +#define MXL5005S_TOP_31P7 317 +#define MXL5005S_TOP_34P9 349 + u32 top; + +#define MXL_ANALOG_MODE 0 +#define MXL_DIGITAL_MODE 1 + u8 mod_mode; + +#define MXL_ZERO_IF 0 +#define MXL_LOW_IF 1 + u8 if_mode; + /* Stuff I don't know what to do with */ u8 AgcMasterByte; }; -- cgit v1.2.3 From 5c1b8536982974d362be32e35f969e1f0ecfb786 Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Thu, 1 May 2008 02:51:36 -0400 Subject: mxl5005s: Cleanup #6 From: Steven Toth Cleanup #6 Signed-off-by: Steven Toth Signed-off-by: Mauro Carvalho Chehab --- linux/drivers/media/common/tuners/mxl5005s.c | 470 +++++++++++++-------------- linux/drivers/media/common/tuners/mxl5005s.h | 48 ++- 2 files changed, 248 insertions(+), 270 deletions(-) (limited to 'linux/drivers/media/common/tuners') diff --git a/linux/drivers/media/common/tuners/mxl5005s.c b/linux/drivers/media/common/tuners/mxl5005s.c index cdc1ab225..daf17eb11 100644 --- a/linux/drivers/media/common/tuners/mxl5005s.c +++ b/linux/drivers/media/common/tuners/mxl5005s.c @@ -1,26 +1,62 @@ /* - * For the Realtek RTL chip RTL2831U - * Realtek Release Date: 2008-03-14, ver 080314 - * Realtek version RTL2831 Linux driver version 080314 - * ver 080314 - * - * for linux kernel version 2.6.21.4 - 2.6.22-14 - * support MXL5005s and MT2060 tuners (support tuner auto-detecting) - * support two IR types -- RC5 and NEC - * - * Known boards with Realtek RTL chip RTL2821U - * Freecom USB stick 14aa:0160 (version 4) - * Conceptronic CTVDIGRCU - * - * Copyright (c) 2008 Realtek - * Copyright (c) 2008 Jan Hoogenraad, Barnaby Shearer, Andy Hasper - * This code is placed under the terms of the GNU General Public License - * - * Released by Realtek under GPLv2. - * Thanks to Realtek for a lot of support we received ! - * - * Revision: 080314 - original version - */ + MaxLinear MXL5005S VSB/QAM/DVBT tuner driver + + Copyright (C) 2008 MaxLinear + Copyright (C) 2006 Steven Toth + Functions: + mxl5005s_reset() + mxl5005s_writereg() + mxl5005s_writeregs() + mxl5005s_init() + mxl5005s_reconfigure() + mxl5005s_AssignTunerMode() + mxl5005s_set_params() + mxl5005s_get_frequency() + mxl5005s_get_bandwidth() + mxl5005s_release() + mxl5005s_attach() + + Copyright (c) 2008 Realtek + Copyright (c) 2008 Jan Hoogenraad, Barnaby Shearer, Andy Hasper + Functions: + mxl5005s_SetRfFreqHz() + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + +*/ + +/* + History of this driver (Steven Toth): + I was given a public release of a linux driver that included + support for the MaxLinear MXL5005S silicon tuner. Analysis of + the tuner driver showed clearly three things. + + 1. The tuner driver didn't support the LinuxTV tuner API + so the code Realtek added had to be removed. + + 2. A significant amount of the driver is reference driver code + from MaxLinear, I felt it was important to identify and + preserve this. + + 3. New code has to be added to interface correctly with the + LinuxTV API, as a regular kernel module. + + Other than the reference driver enum's, I've clearly marked + sections of the code and retained the copyright of the + respective owners. +*/ #include "mxl5005s.h" @@ -250,9 +286,12 @@ struct mxl5005s_state struct mxl5005s_config *config; struct dvb_frontend *frontend; struct i2c_adapter *i2c; + + /* Cache values */ + u32 current_mode; + }; -// funcs u16 MXL_ControlWrite(struct dvb_frontend *fe, u16 ControlNum, u32 value); u16 MXL_ControlRead(struct dvb_frontend *fe, u16 controlNum, u32 *value); u16 MXL_GetMasterControl(u8 *MasterReg, int state); @@ -269,9 +308,22 @@ u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq); void MXL_SynthIFLO_Calc(struct dvb_frontend *fe); void MXL_SynthRFTGLO_Calc(struct dvb_frontend *fe); u16 MXL_GetCHRegister_ZeroIF(struct dvb_frontend *fe, u8 *RegNum, u8 *RegVal, int *count); -int mxl5005s_SetRegsWithTable(struct dvb_frontend *fe, u8 *pAddrTable, u8 *pByteTable, int TableLen); +int mxl5005s_writeregs(struct dvb_frontend *fe, u8 *addrtable, u8 *datatable, u8 len); u16 MXL_IFSynthInit(struct dvb_frontend *fe); -int mxl5005s_AssignTunerMode(struct dvb_frontend *fe); +int mxl5005s_AssignTunerMode(struct dvb_frontend *fe, u32 mod_type, u32 bandwidth); +int mxl5005s_reconfigure(struct dvb_frontend *fe, u32 mod_type, u32 bandwidth); + +/* ---------------------------------------------------------------- + * Begin: Custom code salvaged from the Realtek driver. + * Copyright (c) 2008 Realtek + * Copyright (c) 2008 Jan Hoogenraad, Barnaby Shearer, Andy Hasper + * This code is placed under the terms of the GNU General Public License + * + * Released by Realtek under GPLv2. + * Thanks to Realtek for a lot of support we received ! + * + * Revision: 080314 - original version + */ int mxl5005s_SetRfFreqHz(struct dvb_frontend *fe, unsigned long RfFreqHz) { @@ -292,7 +344,7 @@ int mxl5005s_SetRfFreqHz(struct dvb_frontend *fe, unsigned long RfFreqHz) AddrTable[0] = MASTER_CONTROL_ADDR; ByteTable[0] |= state->config->AgcMasterByte; - mxl5005s_SetRegsWithTable(fe, AddrTable, ByteTable, 1); + mxl5005s_writeregs(fe, AddrTable, ByteTable, 1); // Tuner RF frequency setting stage 1 MXL_TuneRF(fe, RfFreqHz); @@ -309,7 +361,7 @@ int mxl5005s_SetRfFreqHz(struct dvb_frontend *fe, unsigned long RfFreqHz) ByteTable[TableLen] = MasterControlByte | state->config->AgcMasterByte; TableLen += 1; - mxl5005s_SetRegsWithTable(fe, AddrTable, ByteTable, TableLen); + mxl5005s_writeregs(fe, AddrTable, ByteTable, TableLen); // Wait 30 ms. msleep(150); @@ -324,174 +376,18 @@ int mxl5005s_SetRfFreqHz(struct dvb_frontend *fe, unsigned long RfFreqHz) ByteTable[TableLen] = MasterControlByte | state->config->AgcMasterByte ; TableLen += 1; - mxl5005s_SetRegsWithTable(fe, AddrTable, ByteTable, TableLen); + mxl5005s_writeregs(fe, AddrTable, ByteTable, TableLen); msleep(100); return 0; } +/* End: Custom code taken from the Realtek driver */ -static int mxl5005s_reset(struct dvb_frontend *fe) -{ - struct mxl5005s_state *state = fe->tuner_priv; - int ret = 0; - - u8 buf[2] = { 0xff, 0x00 }; - struct i2c_msg msg = { .addr = state->config->i2c_address, .flags = 0, - .buf = buf, .len = 2 }; - - dprintk(2, "%s()\n", __func__); - - if (fe->ops.i2c_gate_ctrl) - fe->ops.i2c_gate_ctrl(fe, 1); - - if (i2c_transfer(state->i2c, &msg, 1) != 1) { - printk(KERN_WARNING "mxl5005s I2C reset failed\n"); - ret = -EREMOTEIO; - } - - if (fe->ops.i2c_gate_ctrl) - fe->ops.i2c_gate_ctrl(fe, 0); - - return ret; -} - -/* Write a single byte to a single reg */ -static int mxl5005s_writereg(struct dvb_frontend *fe, u8 reg, u8 val, int latch) -{ - struct mxl5005s_state *state = fe->tuner_priv; - u8 buf[3] = { reg, val, MXL5005S_LATCH_BYTE }; - struct i2c_msg msg = { .addr = state->config->i2c_address, .flags = 0, - .buf = buf, .len = 3 }; - - if(latch == 0) - msg.len = 2; - - dprintk(2, "%s(reg = 0x%x val = 0x%x addr = 0x%x)\n", __func__, reg, val, msg.addr); - - if (i2c_transfer(state->i2c, &msg, 1) != 1) { - printk(KERN_WARNING "mxl5005s I2C write failed\n"); - return -EREMOTEIO; - } - return 0; -} - -int mxl5005s_SetRegsWithTable(struct dvb_frontend *fe, u8 *pAddrTable, u8 *pByteTable, int TableLen) -{ - int i, ret = 0; - - if (fe->ops.i2c_gate_ctrl) - fe->ops.i2c_gate_ctrl(fe, 1); - - for( i = 0 ; i < TableLen - 1 ; i++) - { - ret = mxl5005s_writereg(fe, pAddrTable[i], pByteTable[i], 0); - if (ret < 0) - break; - } - - ret = mxl5005s_writereg(fe, pAddrTable[i], pByteTable[i], 1); - - if (fe->ops.i2c_gate_ctrl) - fe->ops.i2c_gate_ctrl(fe, 0); - - return ret; -} - -int mxl5005s_SetRegMaskBits(struct dvb_frontend *fe, - unsigned char RegAddr, - unsigned char Msb, - unsigned char Lsb, - const unsigned char WritingValue - ) -{ - int i; - - unsigned char Mask; - unsigned char Shift; - unsigned char RegByte; - - /* Generate mask and shift according to MSB and LSB. */ - Mask = 0; - for(i = Lsb; i < (unsigned char)(Msb + 1); i++) - Mask |= 0x1 << i; - - Shift = Lsb; - - /* Get tuner register byte according to register adddress. */ - MXL_RegRead(fe, RegAddr, &RegByte); - - /* Reserve register byte unmask bit with mask and inlay writing value into it. */ - RegByte &= ~Mask; - RegByte |= (WritingValue << Shift) & Mask; - - /* Update tuner register byte table. */ - MXL_RegWrite(fe, RegAddr, RegByte); - - /* Write tuner register byte with writing byte. */ - return mxl5005s_SetRegsWithTable(fe, &RegAddr, &RegByte, 1); -} - -#if 0 -// DONE -int mxl5005s_SetSpectrumMode(struct dvb_frontend *fe, int SpectrumMode) -{ - struct mxl5005s_state *state = fe->tuner_priv; - static const unsigned char BbIqswapTable[SPECTRUM_MODE_NUM] = - { - /* BB_IQSWAP */ - 0, /* Normal spectrum */ - 1, /* Inverse spectrum */ - }; - - /* Set BB_IQSWAP according to BB_IQSWAP table and spectrum mode. */ - mxl5005s_SetRegMaskBits(fe, - MXL5005S_BB_IQSWAP_ADDR, - MXL5005S_BB_IQSWAP_MSB, - MXL5005S_BB_IQSWAP_LSB, - BbIqswapTable[SpectrumMode]); - - return FUNCTION_SUCCESS; -} - -// DONE -int mxl5005s_SetBandwidthHz(struct dvb_frontend *fe, unsigned long BandwidthHz) -{ - struct mxl5005s_state *state = fe->tuner_priv; - - unsigned char BbDlpfBandsel; - - /* Set BB_DLPF_BANDSEL according to bandwidth. */ - switch(BandwidthHz) - { - default: - case MXL5005S_BANDWIDTH_6MHZ: - BbDlpfBandsel = 3; - break; - case MXL5005S_BANDWIDTH_7MHZ: - BbDlpfBandsel = 2; - break; - case MXL5005S_BANDWIDTH_8MHZ: - BbDlpfBandsel = 0; - break; - } - - if(pExtra->SetRegMaskBits(dib,pTuner, MXL5005S_BB_DLPF_BANDSEL_ADDR, MXL5005S_BB_DLPF_BANDSEL_MSB, - MXL5005S_BB_DLPF_BANDSEL_LSB, BbDlpfBandsel) != 0) - goto error_status_set_tuner_registers; - - - return 0; - - -error_status_set_tuner_registers: - return -1; -} -#endif - -// The following context is source code provided by MaxLinear. -// MaxLinear source code - MXL5005_Initialize.cpp -// DONE +/* ---------------------------------------------------------------- + * Begin: Reference driver code found in the Realtek driver. + * Copyright (c) 2008 MaxLinear + */ u16 MXL5005_RegisterInit(struct dvb_frontend *fe) { struct mxl5005s_state *state = fe->tuner_priv; @@ -813,7 +709,6 @@ u16 MXL5005_RegisterInit(struct dvb_frontend *fe) return 0 ; } -// DONE u16 MXL5005_ControlInit(struct dvb_frontend *fe) { struct mxl5005s_state *state = fe->tuner_priv; @@ -1757,7 +1652,6 @@ u16 MXL5005_ControlInit(struct dvb_frontend *fe) // MaxLinear source code - MXL5005_c.cpp // MXL5005.cpp : Defines the initialization routines for the DLL. // 2.6.12 -// DONE void InitTunerControls(struct dvb_frontend *fe) { MXL5005_RegisterInit(fe); @@ -1800,7 +1694,6 @@ void InitTunerControls(struct dvb_frontend *fe) // > 0 : Failed // // // /////////////////////////////////////////////////////////////////////////////// -// DONE u16 MXL5005_TunerConfig(struct dvb_frontend *fe, u8 Mode, /* 0: Analog Mode ; 1: Digital Mode */ u8 IF_mode, /* for Analog Mode, 0: zero IF; 1: low IF */ @@ -1870,7 +1763,6 @@ u16 MXL5005_TunerConfig(struct dvb_frontend *fe, // > 0 : Failed // // // /////////////////////////////////////////////////////////////////////////////// -// DONE void MXL_SynthIFLO_Calc(struct dvb_frontend *fe) { struct mxl5005s_state *state = fe->tuner_priv; @@ -1909,7 +1801,6 @@ void MXL_SynthIFLO_Calc(struct dvb_frontend *fe) // > 0 : Failed // // // /////////////////////////////////////////////////////////////////////////////// -// DONE void MXL_SynthRFTGLO_Calc(struct dvb_frontend *fe) { struct mxl5005s_state *state = fe->tuner_priv; @@ -1948,7 +1839,6 @@ void MXL_SynthRFTGLO_Calc(struct dvb_frontend *fe) // > 0 : Failed // // // /////////////////////////////////////////////////////////////////////////////// -// DONE u16 MXL_OverwriteICDefault(struct dvb_frontend *fe) { u16 status = 0; @@ -1986,7 +1876,6 @@ u16 MXL_OverwriteICDefault(struct dvb_frontend *fe) // > 0 : Failed // // // /////////////////////////////////////////////////////////////////////////////// -// DONE u16 MXL_BlockInit(struct dvb_frontend *fe) { struct mxl5005s_state *state = fe->tuner_priv; @@ -3745,7 +3634,6 @@ u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq) return status ; } -// DONE u16 MXL_SetGPIO(struct dvb_frontend *fe, u8 GPIO_Num, u8 GPIO_Val) { u16 status = 0; @@ -3812,7 +3700,6 @@ u16 MXL_SetGPIO(struct dvb_frontend *fe, u8 GPIO_Num, u8 GPIO_Val) // >0 : Value exceed maximum allowed for control number // // // /////////////////////////////////////////////////////////////////////////////// -// DONE u16 MXL_ControlWrite(struct dvb_frontend *fe, u16 ControlNum, u32 value) { u16 status = 0; @@ -3853,7 +3740,6 @@ u16 MXL_ControlWrite(struct dvb_frontend *fe, u16 ControlNum, u32 value) // 2 : Control name not found // // // /////////////////////////////////////////////////////////////////////////////// -// DONE u16 MXL_ControlWrite_Group(struct dvb_frontend *fe, u16 controlNum, u32 value, u16 controlGroup) { struct mxl5005s_state *state = fe->tuner_priv; @@ -3960,7 +3846,6 @@ u16 MXL_ControlWrite_Group(struct dvb_frontend *fe, u16 controlNum, u32 value, u // -1 : Invalid Register Address // // // /////////////////////////////////////////////////////////////////////////////// -// DONE u16 MXL_RegWrite(struct dvb_frontend *fe, u8 RegNum, u8 RegVal) { struct mxl5005s_state *state = fe->tuner_priv; @@ -4000,7 +3885,6 @@ u16 MXL_RegWrite(struct dvb_frontend *fe, u8 RegNum, u8 RegVal) // -1 : Invalid Register Address // // // /////////////////////////////////////////////////////////////////////////////// -// DONE u16 MXL_RegRead(struct dvb_frontend *fe, u8 RegNum, u8 *RegVal) { struct mxl5005s_state *state = fe->tuner_priv; @@ -4037,7 +3921,6 @@ u16 MXL_RegRead(struct dvb_frontend *fe, u8 RegNum, u8 *RegVal) // -1 : Invalid control name // // // /////////////////////////////////////////////////////////////////////////////// -// DONE u16 MXL_ControlRead(struct dvb_frontend *fe, u16 controlNum, u32 *value) { struct mxl5005s_state *state = fe->tuner_priv; @@ -4109,7 +3992,6 @@ u16 MXL_ControlRead(struct dvb_frontend *fe, u16 controlNum, u32 *value) // -1 : Invalid control name // // // /////////////////////////////////////////////////////////////////////////////// -// DONE u16 MXL_ControlRegRead(struct dvb_frontend *fe, u16 controlNum, u8 *RegNum, int * count) { struct mxl5005s_state *state = fe->tuner_priv; @@ -4215,7 +4097,6 @@ u16 MXL_ControlRegRead(struct dvb_frontend *fe, u16 controlNum, u8 *RegNum, int // NONE // // // /////////////////////////////////////////////////////////////////////////////// -// DONE void MXL_RegWriteBit(struct dvb_frontend *fe, u8 address, u8 bit, u8 bitVal) { struct mxl5005s_state *state = fe->tuner_priv; @@ -4263,7 +4144,6 @@ void MXL_RegWriteBit(struct dvb_frontend *fe, u8 address, u8 bit, u8 bitVal) // Computed value // // // /////////////////////////////////////////////////////////////////////////////// -// DONE u32 MXL_Ceiling(u32 value, u32 resolution) { return (value/resolution + (value % resolution > 0 ? 1 : 0)); @@ -4272,7 +4152,6 @@ u32 MXL_Ceiling(u32 value, u32 resolution) // // Retrieve the Initialzation Registers // -// DONE u16 MXL_GetInitRegister(struct dvb_frontend *fe, u8 * RegNum, u8 *RegVal, int *count) { u16 status = 0; @@ -4295,7 +4174,6 @@ u16 MXL_GetInitRegister(struct dvb_frontend *fe, u8 * RegNum, u8 *RegVal, int *c return status; } -// DONE u16 MXL_GetCHRegister(struct dvb_frontend *fe, u8 * RegNum, u8 *RegVal, int *count) { u16 status = 0; @@ -4323,7 +4201,6 @@ u16 MXL_GetCHRegister(struct dvb_frontend *fe, u8 * RegNum, u8 *RegVal, int *cou return status; } -// DONE u16 MXL_GetCHRegister_ZeroIF(struct dvb_frontend *fe, u8 * RegNum, u8 *RegVal, int *count) { u16 status = 0; @@ -4341,7 +4218,6 @@ u16 MXL_GetCHRegister_ZeroIF(struct dvb_frontend *fe, u8 * RegNum, u8 *RegVal, i return status; } -// DONE u16 MXL_GetCHRegister_LowIF(struct dvb_frontend *fe, u8 * RegNum, u8 *RegVal, int *count) { u16 status = 0; @@ -4359,7 +4235,6 @@ u16 MXL_GetCHRegister_LowIF(struct dvb_frontend *fe, u8 * RegNum, u8 *RegVal, in return status; } -// DONE u16 MXL_GetMasterControl(u8 *MasterReg, int state) { if (state == 1) /* Load_Start */ @@ -4504,7 +4379,6 @@ u16 MXL_VCORange_Test(struct dvb_frontend *fe, int VCO_Range) return status; } -// DONE u16 MXL_Hystersis_Test(struct dvb_frontend *fe, int Hystersis) { struct mxl5005s_state *state = fe->tuner_priv; @@ -4515,12 +4389,91 @@ u16 MXL_Hystersis_Test(struct dvb_frontend *fe, int Hystersis) return status; } - #endif +/* End: Reference driver code found in the Realtek driver that + * is copyright MaxLinear */ + +/* ---------------------------------------------------------------- + * Begin: Everything after here is new code to adapt the + * proprietary Realtek driver into a Linux API tuner. + * Copyright (C) 2008 Steven Toth + */ +static int mxl5005s_reset(struct dvb_frontend *fe) +{ + struct mxl5005s_state *state = fe->tuner_priv; + int ret = 0; + + u8 buf[2] = { 0xff, 0x00 }; + struct i2c_msg msg = { .addr = state->config->i2c_address, .flags = 0, + .buf = buf, .len = 2 }; + + dprintk(2, "%s()\n", __func__); + + if (fe->ops.i2c_gate_ctrl) + fe->ops.i2c_gate_ctrl(fe, 1); + + if (i2c_transfer(state->i2c, &msg, 1) != 1) { + printk(KERN_WARNING "mxl5005s I2C reset failed\n"); + ret = -EREMOTEIO; + } + + if (fe->ops.i2c_gate_ctrl) + fe->ops.i2c_gate_ctrl(fe, 0); + + return ret; +} + +/* Write a single byte to a single reg, latch the value if required by + * following the transaction with the latch byte. + */ +static int mxl5005s_writereg(struct dvb_frontend *fe, u8 reg, u8 val, int latch) +{ + struct mxl5005s_state *state = fe->tuner_priv; + u8 buf[3] = { reg, val, MXL5005S_LATCH_BYTE }; + struct i2c_msg msg = { .addr = state->config->i2c_address, .flags = 0, + .buf = buf, .len = 3 }; + + if (latch == 0) + msg.len = 2; + + dprintk(2, "%s(reg = 0x%x val = 0x%x addr = 0x%x)\n", __func__, reg, val, msg.addr); + + if (i2c_transfer(state->i2c, &msg, 1) != 1) { + printk(KERN_WARNING "mxl5005s I2C write failed\n"); + return -EREMOTEIO; + } + return 0; +} + +int mxl5005s_writeregs(struct dvb_frontend *fe, u8 *addrtable, u8 *datatable, u8 len) +{ + int ret = 0, i; + + if (fe->ops.i2c_gate_ctrl) + fe->ops.i2c_gate_ctrl(fe, 1); + + for (i = 0 ; i < len-1; i++) { + ret = mxl5005s_writereg(fe, addrtable[i], datatable[i], 0); + if (ret < 0) + break; + } + + ret = mxl5005s_writereg(fe, addrtable[i], datatable[i], 1); + + if (fe->ops.i2c_gate_ctrl) + fe->ops.i2c_gate_ctrl(fe, 0); + + return ret; +} -/* Linux driver related functions */ int mxl5005s_init(struct dvb_frontend *fe) +{ + dprintk(1, "%s()\n", __func__); + return mxl5005s_reconfigure(fe, MXL_QAM, MXL5005S_BANDWIDTH_6MHZ); +} + +int mxl5005s_reconfigure(struct dvb_frontend *fe, u32 mod_type, u32 bandwidth) { struct mxl5005s_state *state = fe->tuner_priv; @@ -4528,7 +4481,7 @@ int mxl5005s_init(struct dvb_frontend *fe) u8 ByteTable[MXL5005S_REG_WRITING_TABLE_LEN_MAX]; int TableLen; - dprintk(1, "%s()\n", __func__); + dprintk(1, "%s(type=%d, bw=%d)\n", __func__, mod_type, bandwidth); mxl5005s_reset(fe); @@ -4537,19 +4490,19 @@ int mxl5005s_init(struct dvb_frontend *fe) AddrTable[0] = MASTER_CONTROL_ADDR; ByteTable[0] |= state->config->AgcMasterByte; - mxl5005s_SetRegsWithTable(fe, AddrTable, ByteTable, 1); + mxl5005s_writeregs(fe, AddrTable, ByteTable, 1); - mxl5005s_AssignTunerMode(fe); // tunre_config + mxl5005s_AssignTunerMode(fe, mod_type, bandwidth); /* Tuner initialization stage 1 */ MXL_GetInitRegister(fe, AddrTable, ByteTable, &TableLen); - mxl5005s_SetRegsWithTable(fe, AddrTable, ByteTable, TableLen); + mxl5005s_writeregs(fe, AddrTable, ByteTable, TableLen); return 0; } -int mxl5005s_AssignTunerMode(struct dvb_frontend *fe) +int mxl5005s_AssignTunerMode(struct dvb_frontend *fe, u32 mod_type, u32 bandwidth) { struct mxl5005s_state *state = fe->tuner_priv; struct mxl5005s_config *c = state->config; @@ -4561,7 +4514,7 @@ int mxl5005s_AssignTunerMode(struct dvb_frontend *fe) fe, c->mod_mode, c->if_mode, - MXL5005S_BANDWIDTH_6MHZ, + bandwidth, c->if_freq, c->xtal_freq, c->agc_mode, @@ -4571,7 +4524,7 @@ int mxl5005s_AssignTunerMode(struct dvb_frontend *fe) c->div_out, c->cap_select, c->rssi_enable, - MXL_QAM, + mod_type, c->tracking_filter); return 0; @@ -4580,22 +4533,62 @@ int mxl5005s_AssignTunerMode(struct dvb_frontend *fe) static int mxl5005s_set_params(struct dvb_frontend *fe, struct dvb_frontend_parameters *params) { - u32 freq; - u32 bw; + struct mxl5005s_state *state = fe->tuner_priv; + u32 req_mode, req_bw = 0; + int ret; - if (fe->ops.info.type == FE_OFDM) - bw = params->u.ofdm.bandwidth; - else - bw = MXL5005S_BANDWIDTH_6MHZ; + dprintk(1, "%s()\n", __func__); - freq = params->frequency; /* Hz */ - dprintk(1, "%s() freq=%d bw=%d\n", __func__, freq, bw); + if (fe->ops.info.type == FE_ATSC) { + switch (params->u.vsb.modulation) { + case VSB_8: + req_mode = MXL_ATSC; break; + default: + case QAM_64: + case QAM_256: + case QAM_AUTO: + req_mode = MXL_QAM; break; + } + } + else req_mode = MXL_DVBT; + + /* Change tuner for new modulation type if reqd */ + if (req_mode != state->current_mode) { + switch (req_mode) { + case VSB_8: + case QAM_64: + case QAM_256: + case QAM_AUTO: + req_bw = MXL5005S_BANDWIDTH_6MHZ; + break; + default: + /* Assume DVB-T */ + switch (params->u.ofdm.bandwidth) { + case BANDWIDTH_6_MHZ: + req_bw = MXL5005S_BANDWIDTH_6MHZ; + break; + case BANDWIDTH_7_MHZ: + req_bw = MXL5005S_BANDWIDTH_7MHZ; + break; + case BANDWIDTH_AUTO: + case BANDWIDTH_8_MHZ: + req_bw = MXL5005S_BANDWIDTH_8MHZ; + break; + } + } - mxl5005s_SetRfFreqHz(fe, freq); + state->current_mode = req_mode; + ret = mxl5005s_reconfigure(fe, req_mode, req_bw); - msleep(350); + } else + ret = 0; - return 0; + if (ret == 0) { + dprintk(1, "%s() freq=%d\n", __func__, params->frequency); + ret = mxl5005s_SetRfFreqHz(fe, params->frequency); + } + + return ret; } static int mxl5005s_get_frequency(struct dvb_frontend *fe, u32 *frequency) @@ -4618,16 +4611,6 @@ static int mxl5005s_get_bandwidth(struct dvb_frontend *fe, u32 *bandwidth) return 0; } -static int mxl5005s_get_status(struct dvb_frontend *fe, u32 *status) -{ - dprintk(1, "%s()\n", __func__); - - *status = 0; - // *status = TUNER_STATUS_LOCKED; - - return 0; -} - static int mxl5005s_release(struct dvb_frontend *fe) { dprintk(1, "%s()\n", __func__); @@ -4650,7 +4633,6 @@ static const struct dvb_tuner_ops mxl5005s_tuner_ops = { .set_params = mxl5005s_set_params, .get_frequency = mxl5005s_get_frequency, .get_bandwidth = mxl5005s_get_bandwidth, - .get_status = mxl5005s_get_status }; struct dvb_frontend *mxl5005s_attach(struct dvb_frontend *fe, @@ -4667,6 +4649,7 @@ struct dvb_frontend *mxl5005s_attach(struct dvb_frontend *fe, state->frontend = fe; state->config = config; state->i2c = i2c; + state->current_mode = MXL_QAM; printk(KERN_INFO "MXL5005S: Attached at address 0x%02x\n", config->i2c_address); @@ -4678,9 +4661,6 @@ struct dvb_frontend *mxl5005s_attach(struct dvb_frontend *fe, EXPORT_SYMBOL(mxl5005s_attach); MODULE_DESCRIPTION("MaxLinear MXL5005S silicon tuner driver"); -MODULE_AUTHOR("Jan Hoogenraad"); -MODULE_AUTHOR("Barnaby Shearer"); -MODULE_AUTHOR("Andy Hasper"); MODULE_AUTHOR("Steven Toth"); MODULE_LICENSE("GPL"); diff --git a/linux/drivers/media/common/tuners/mxl5005s.h b/linux/drivers/media/common/tuners/mxl5005s.h index 2777ecc20..7658401f3 100644 --- a/linux/drivers/media/common/tuners/mxl5005s.h +++ b/linux/drivers/media/common/tuners/mxl5005s.h @@ -1,27 +1,24 @@ /* - * For the Realtek RTL chip RTL2831U - * Realtek Release Date: 2008-03-14, ver 080314 - * Realtek version RTL2831 Linux driver version 080314 - * ver 080314 - * - * for linux kernel version 2.6.21.4 - 2.6.22-14 - * support MXL5005s and MT2060 tuners (support tuner auto-detecting) - * support two IR types -- RC5 and NEC - * - * Known boards with Realtek RTL chip RTL2821U - * Freecom USB stick 14aa:0160 (version 4) - * Conceptronic CTVDIGRCU - * - * Copyright (c) 2008 Realtek - * Copyright (c) 2008 Jan Hoogenraad, Barnaby Shearer, Andy Hasper - * This code is placed under the terms of the GNU General Public License - * - * Released by Realtek under GPLv2. - * Thanks to Realtek for a lot of support we received ! - * - * Revision: 080314 - original version - */ + MaxLinear MXL5005S VSB/QAM/DVBT tuner driver + Copyright (C) 2008 MaxLinear + Copyright (C) 2008 Steven Toth + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + +*/ #ifndef __MXL5005S_H #define __MXL5005S_H @@ -112,14 +109,15 @@ struct mxl5005s_config u8 AgcMasterByte; }; -#if defined(CONFIG_DVB_TUNER_MXL5005S) || (defined(CONFIG_DVB_TUNER_MXL5005S_MODULE) && defined(MODULE)) +#if defined(CONFIG_DVB_TUNER_MXL5005S) || \ + (defined(CONFIG_DVB_TUNER_MXL5005S_MODULE) && defined(MODULE)) extern struct dvb_frontend *mxl5005s_attach(struct dvb_frontend *fe, struct i2c_adapter *i2c, - struct mxl5005s_config *config); + struct mxl5005s_config *config) #else static inline struct dvb_frontend *mxl5005s_attach(struct dvb_frontend *fe, struct i2c_adapter *i2c, - struct mxl5005s_config *config); + struct mxl5005s_config *config) { printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__); return NULL; -- cgit v1.2.3 From 1dda9c2b40396048f4cbcdfeac248d092004ffad Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Thu, 1 May 2008 03:04:09 -0400 Subject: mxl5005s: Basic digital support. From: Steven Toth ATSC and QAM should be working but basic testing is required. Signed-off-by: Steven Toth Signed-off-by: Mauro Carvalho Chehab --- linux/drivers/media/common/tuners/mxl5005s.c | 694 ++++++++++++++++----------- linux/drivers/media/common/tuners/mxl5005s.h | 145 ++---- 2 files changed, 467 insertions(+), 372 deletions(-) (limited to 'linux/drivers/media/common/tuners') diff --git a/linux/drivers/media/common/tuners/mxl5005s.c b/linux/drivers/media/common/tuners/mxl5005s.c index daf17eb11..60c5a7704 100644 --- a/linux/drivers/media/common/tuners/mxl5005s.c +++ b/linux/drivers/media/common/tuners/mxl5005s.c @@ -1,69 +1,40 @@ /* - MaxLinear MXL5005S VSB/QAM/DVBT tuner driver - - Copyright (C) 2008 MaxLinear - Copyright (C) 2006 Steven Toth - Functions: - mxl5005s_reset() - mxl5005s_writereg() - mxl5005s_writeregs() - mxl5005s_init() - mxl5005s_reconfigure() - mxl5005s_AssignTunerMode() - mxl5005s_set_params() - mxl5005s_get_frequency() - mxl5005s_get_bandwidth() - mxl5005s_release() - mxl5005s_attach() - - Copyright (c) 2008 Realtek - Copyright (c) 2008 Jan Hoogenraad, Barnaby Shearer, Andy Hasper - Functions: - mxl5005s_SetRfFreqHz() - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program; if not, write to the Free Software - Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. - -*/ - -/* - History of this driver (Steven Toth): - I was given a public release of a linux driver that included - support for the MaxLinear MXL5005S silicon tuner. Analysis of - the tuner driver showed clearly three things. - - 1. The tuner driver didn't support the LinuxTV tuner API - so the code Realtek added had to be removed. - - 2. A significant amount of the driver is reference driver code - from MaxLinear, I felt it was important to identify and - preserve this. - - 3. New code has to be added to interface correctly with the - LinuxTV API, as a regular kernel module. - - Other than the reference driver enum's, I've clearly marked - sections of the code and retained the copyright of the - respective owners. -*/ + * For the Realtek RTL chip RTL2831U + * Realtek Release Date: 2008-03-14, ver 080314 + * Realtek version RTL2831 Linux driver version 080314 + * ver 080314 + * + * for linux kernel version 2.6.21.4 - 2.6.22-14 + * support MXL5005s and MT2060 tuners (support tuner auto-detecting) + * support two IR types -- RC5 and NEC + * + * Known boards with Realtek RTL chip RTL2821U + * Freecom USB stick 14aa:0160 (version 4) + * Conceptronic CTVDIGRCU + * + * Copyright (c) 2008 Realtek + * Copyright (c) 2008 Jan Hoogenraad, Barnaby Shearer, Andy Hasper + * This code is placed under the terms of the GNU General Public License + * + * Released by Realtek under GPLv2. + * Thanks to Realtek for a lot of support we received ! + * + * Revision: 080314 - original version + */ +#include +#include +#include +#include +#include +#include +#include "dvb_frontend.h" #include "mxl5005s.h" -static int debug = 2; +static int debug; #define dprintk(level, arg...) do { \ - if (level <= debug) \ + if (debug >= level) \ printk(arg); \ } while (0) @@ -79,6 +50,13 @@ static int debug = 2; #define MXLCTRL_NUM 189 #define MASTER_CONTROL_ADDR 9 +/* Enumeration of AGC Mode */ +typedef enum +{ + MXL_DUAL_AGC = 0, + MXL_SINGLE_AGC +} AGC_Mode; + /* Enumeration of Master Control Register State */ typedef enum { @@ -88,6 +66,51 @@ typedef enum MC_SEQ_OFF } Master_Control_State; +/* Enumeration of MXL5005 Tuner Mode */ +typedef enum +{ + MXL_ANALOG_MODE = 0, + MXL_DIGITAL_MODE +} Tuner_Mode; + +/* Enumeration of MXL5005 Tuner IF Mode */ +typedef enum +{ + MXL_ZERO_IF = 0, + MXL_LOW_IF +} Tuner_IF_Mode; + +/* Enumeration of MXL5005 Tuner Clock Out Mode */ +typedef enum +{ + MXL_CLOCK_OUT_DISABLE = 0, + MXL_CLOCK_OUT_ENABLE +} Tuner_Clock_Out; + +/* Enumeration of MXL5005 Tuner Div Out Mode */ +typedef enum +{ + MXL_DIV_OUT_1 = 0, + MXL_DIV_OUT_4 + +} Tuner_Div_Out; + +/* Enumeration of MXL5005 Tuner Pull-up Cap Select Mode */ +typedef enum +{ + MXL_CAP_SEL_DISABLE = 0, + MXL_CAP_SEL_ENABLE + +} Tuner_Cap_Select; + +/* Enumeration of MXL5005 Tuner RSSI Mode */ +typedef enum +{ + MXL_RSSI_DISABLE = 0, + MXL_RSSI_ENABLE + +} Tuner_RSSI; + /* Enumeration of MXL5005 Tuner Modulation Type */ typedef enum { @@ -99,6 +122,22 @@ typedef enum MXL_ANALOG_OTA } Tuner_Modu_Type; +/* Enumeration of MXL5005 Tuner Tracking Filter Type */ +typedef enum +{ + MXL_TF_DEFAULT = 0, + MXL_TF_OFF, + MXL_TF_C, + MXL_TF_C_H, + MXL_TF_D, + MXL_TF_D_L, + MXL_TF_E, + MXL_TF_F, + MXL_TF_E_2, + MXL_TF_E_NA, + MXL_TF_G +} Tuner_TF_Type; + /* MXL5005 Tuner Register Struct */ typedef struct _TunerReg_struct { @@ -229,6 +268,33 @@ enum }; #define MXL5005S_BANDWIDTH_MODE_NUM 3 +/* Top modes */ +enum +{ + MXL5005S_TOP_5P5 = 55, + MXL5005S_TOP_7P2 = 72, + MXL5005S_TOP_9P2 = 92, + MXL5005S_TOP_11P0 = 110, + MXL5005S_TOP_12P9 = 129, + MXL5005S_TOP_14P7 = 147, + MXL5005S_TOP_16P8 = 168, + MXL5005S_TOP_19P4 = 194, + MXL5005S_TOP_21P2 = 212, + MXL5005S_TOP_23P2 = 232, + MXL5005S_TOP_25P2 = 252, + MXL5005S_TOP_27P1 = 271, + MXL5005S_TOP_29P2 = 292, + MXL5005S_TOP_31P7 = 317, + MXL5005S_TOP_34P9 = 349, +}; + +/* IF output load */ +enum +{ + MXL5005S_IF_OUTPUT_LOAD_200_OHM = 200, + MXL5005S_IF_OUTPUT_LOAD_300_OHM = 300, +}; + /* MXL5005 Tuner Control Struct */ typedef struct _TunerControl_struct { u16 Ctrl_Num; /* Control Number */ @@ -283,15 +349,13 @@ struct mxl5005s_state TunerRegs[TUNER_REGS_NUM]; /* Tuner Register Array Pointer */ /* Linux driver framework specific */ - struct mxl5005s_config *config; + const struct mxl5005s_config *config; + struct dvb_frontend *frontend; struct i2c_adapter *i2c; - - /* Cache values */ - u32 current_mode; - }; +// funcs u16 MXL_ControlWrite(struct dvb_frontend *fe, u16 ControlNum, u32 value); u16 MXL_ControlRead(struct dvb_frontend *fe, u16 controlNum, u32 *value); u16 MXL_GetMasterControl(u8 *MasterReg, int state); @@ -308,26 +372,14 @@ u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq); void MXL_SynthIFLO_Calc(struct dvb_frontend *fe); void MXL_SynthRFTGLO_Calc(struct dvb_frontend *fe); u16 MXL_GetCHRegister_ZeroIF(struct dvb_frontend *fe, u8 *RegNum, u8 *RegVal, int *count); -int mxl5005s_writeregs(struct dvb_frontend *fe, u8 *addrtable, u8 *datatable, u8 len); +int mxl5005s_SetRegsWithTable(struct dvb_frontend *fe, u8 *pAddrTable, u8 *pByteTable, int TableLen); u16 MXL_IFSynthInit(struct dvb_frontend *fe); -int mxl5005s_AssignTunerMode(struct dvb_frontend *fe, u32 mod_type, u32 bandwidth); -int mxl5005s_reconfigure(struct dvb_frontend *fe, u32 mod_type, u32 bandwidth); - -/* ---------------------------------------------------------------- - * Begin: Custom code salvaged from the Realtek driver. - * Copyright (c) 2008 Realtek - * Copyright (c) 2008 Jan Hoogenraad, Barnaby Shearer, Andy Hasper - * This code is placed under the terms of the GNU General Public License - * - * Released by Realtek under GPLv2. - * Thanks to Realtek for a lot of support we received ! - * - * Revision: 080314 - original version - */ +static int mxl5005s_init2(struct dvb_frontend *fe); int mxl5005s_SetRfFreqHz(struct dvb_frontend *fe, unsigned long RfFreqHz) { struct mxl5005s_state *state = fe->tuner_priv; + u8 AgcMasterByte = state->config->AgcMasterByte; unsigned char AddrTable[MXL5005S_REG_WRITING_TABLE_LEN_MAX]; unsigned char ByteTable[MXL5005S_REG_WRITING_TABLE_LEN_MAX]; int TableLen; @@ -344,7 +396,7 @@ int mxl5005s_SetRfFreqHz(struct dvb_frontend *fe, unsigned long RfFreqHz) AddrTable[0] = MASTER_CONTROL_ADDR; ByteTable[0] |= state->config->AgcMasterByte; - mxl5005s_writeregs(fe, AddrTable, ByteTable, 1); + mxl5005s_SetRegsWithTable(fe, AddrTable, ByteTable, 1); // Tuner RF frequency setting stage 1 MXL_TuneRF(fe, RfFreqHz); @@ -358,13 +410,13 @@ int mxl5005s_SetRfFreqHz(struct dvb_frontend *fe, unsigned long RfFreqHz) MXL_GetMasterControl(&MasterControlByte, MC_LOAD_START) ; AddrTable[TableLen] = MASTER_CONTROL_ADDR ; - ByteTable[TableLen] = MasterControlByte | state->config->AgcMasterByte; + ByteTable[TableLen] = MasterControlByte | AgcMasterByte; TableLen += 1; - mxl5005s_writeregs(fe, AddrTable, ByteTable, TableLen); + mxl5005s_SetRegsWithTable(fe, AddrTable, ByteTable, TableLen); // Wait 30 ms. - msleep(150); + msleep(30); // Tuner RF frequency setting stage 2 MXL_ControlWrite(fe, SEQ_FSM_PULSE, 1) ; @@ -373,21 +425,167 @@ int mxl5005s_SetRfFreqHz(struct dvb_frontend *fe, unsigned long RfFreqHz) MXL_GetMasterControl(&MasterControlByte, MC_LOAD_START) ; AddrTable[TableLen] = MASTER_CONTROL_ADDR ; - ByteTable[TableLen] = MasterControlByte | state->config->AgcMasterByte ; + ByteTable[TableLen] = MasterControlByte | AgcMasterByte ; TableLen += 1; - mxl5005s_writeregs(fe, AddrTable, ByteTable, TableLen); + mxl5005s_SetRegsWithTable(fe, AddrTable, ByteTable, TableLen); + + return 0; +} - msleep(100); +/* Write a single byte to a single reg */ +static int mxl5005s_writereg(struct dvb_frontend *fe, u8 reg, u8 val) +{ + struct mxl5005s_state *state = fe->tuner_priv; + u8 buf[2] = { reg, val }; + struct i2c_msg msg = { .addr = state->config->i2c_address, .flags = 0, + .buf = buf, .len = 2 }; + if (i2c_transfer(state->i2c, &msg, 1) != 1) { + printk(KERN_WARNING "mxl5005s I2C write failed\n"); + return -EREMOTEIO; + } return 0; } -/* End: Custom code taken from the Realtek driver */ -/* ---------------------------------------------------------------- - * Begin: Reference driver code found in the Realtek driver. - * Copyright (c) 2008 MaxLinear - */ +/* Write a word to a single reg */ +static int mxl5005s_writereg16(struct dvb_frontend *fe, u8 reg, u16 val) +{ + struct mxl5005s_state *state = fe->tuner_priv; + u8 buf[3] = { reg, val >> 8 , val & 0xff }; + struct i2c_msg msg = { .addr = state->config->i2c_address, .flags = 0, + .buf = buf, .len = 3 }; + + if (i2c_transfer(state->i2c, &msg, 1) != 1) { + printk(KERN_WARNING "mxl5005s I2C write16 failed\n"); + return -EREMOTEIO; + } + return 0; +} + +int mxl5005s_SetRegsWithTable(struct dvb_frontend *fe, u8 *pAddrTable, u8 *pByteTable, int TableLen) +{ + int i, ret; + u8 end_two_bytes_buf[]={ 0 , 0 }; + + for( i = 0 ; i < TableLen - 1 ; i++) + { +#if 0 + if ( TUNER_WI2C(dib , tuner_addr , pAddrTable[i] , &pByteTable[i] , 1 ) ) + return FUNCTION_ERROR; +#else + ret = mxl5005s_writereg(fe, pAddrTable[i], pByteTable[i]); + if (!ret) + return ret; +#endif + } + + end_two_bytes_buf[0] = pByteTable[i]; + end_two_bytes_buf[1] = MXL5005S_LATCH_BYTE; + +#if 0 + if ( TUNER_WI2C(dib , tuner_addr , pAddrTable[i] , end_two_bytes_buf , 2 ) ) + return FUNCTION_ERROR; +#else + ret = mxl5005s_writereg16(fe, pAddrTable[i], (end_two_bytes_buf[0] << 8) | end_two_bytes_buf[1]); +#endif + + return ret; +} + +int mxl5005s_SetRegMaskBits(struct dvb_frontend *fe, + unsigned char RegAddr, + unsigned char Msb, + unsigned char Lsb, + const unsigned char WritingValue + ) +{ + int i; + + unsigned char Mask; + unsigned char Shift; + unsigned char RegByte; + + /* Generate mask and shift according to MSB and LSB. */ + Mask = 0; + for(i = Lsb; i < (unsigned char)(Msb + 1); i++) + Mask |= 0x1 << i; + + Shift = Lsb; + + /* Get tuner register byte according to register adddress. */ + MXL_RegRead(fe, RegAddr, &RegByte); + + /* Reserve register byte unmask bit with mask and inlay writing value into it. */ + RegByte &= ~Mask; + RegByte |= (WritingValue << Shift) & Mask; + + /* Update tuner register byte table. */ + MXL_RegWrite(fe, RegAddr, RegByte); + + /* Write tuner register byte with writing byte. */ + return mxl5005s_SetRegsWithTable(fe, &RegAddr, &RegByte, 1); +} +#if 0 +// DONE +int mxl5005s_SetSpectrumMode(struct dvb_frontend *fe, int SpectrumMode) +{ + struct mxl5005s_state *state = fe->tuner_priv; + static const unsigned char BbIqswapTable[SPECTRUM_MODE_NUM] = + { + /* BB_IQSWAP */ + 0, /* Normal spectrum */ + 1, /* Inverse spectrum */ + }; + + /* Set BB_IQSWAP according to BB_IQSWAP table and spectrum mode. */ + mxl5005s_SetRegMaskBits(fe, + MXL5005S_BB_IQSWAP_ADDR, + MXL5005S_BB_IQSWAP_MSB, + MXL5005S_BB_IQSWAP_LSB, + BbIqswapTable[SpectrumMode]); + + return FUNCTION_SUCCESS; +} + +// DONE +int mxl5005s_SetBandwidthHz(struct dvb_frontend *fe, unsigned long BandwidthHz) +{ + struct mxl5005s_state *state = fe->tuner_priv; + + unsigned char BbDlpfBandsel; + + /* Set BB_DLPF_BANDSEL according to bandwidth. */ + switch(BandwidthHz) + { + default: + case MXL5005S_BANDWIDTH_6MHZ: + BbDlpfBandsel = 3; + break; + case MXL5005S_BANDWIDTH_7MHZ: + BbDlpfBandsel = 2; + break; + case MXL5005S_BANDWIDTH_8MHZ: + BbDlpfBandsel = 0; + break; + } + + if(pExtra->SetRegMaskBits(dib,pTuner, MXL5005S_BB_DLPF_BANDSEL_ADDR, MXL5005S_BB_DLPF_BANDSEL_MSB, + MXL5005S_BB_DLPF_BANDSEL_LSB, BbDlpfBandsel) != 0) + goto error_status_set_tuner_registers; + + + return 0; + + +error_status_set_tuner_registers: + return -1; +} +#endif + +// The following context is source code provided by MaxLinear. +// MaxLinear source code - MXL5005_Initialize.cpp +// DONE u16 MXL5005_RegisterInit(struct dvb_frontend *fe) { struct mxl5005s_state *state = fe->tuner_priv; @@ -709,6 +907,7 @@ u16 MXL5005_RegisterInit(struct dvb_frontend *fe) return 0 ; } +// DONE u16 MXL5005_ControlInit(struct dvb_frontend *fe) { struct mxl5005s_state *state = fe->tuner_priv; @@ -1652,6 +1851,7 @@ u16 MXL5005_ControlInit(struct dvb_frontend *fe) // MaxLinear source code - MXL5005_c.cpp // MXL5005.cpp : Defines the initialization routines for the DLL. // 2.6.12 +// DONE void InitTunerControls(struct dvb_frontend *fe) { MXL5005_RegisterInit(fe); @@ -1694,6 +1894,7 @@ void InitTunerControls(struct dvb_frontend *fe) // > 0 : Failed // // // /////////////////////////////////////////////////////////////////////////////// +// DONE u16 MXL5005_TunerConfig(struct dvb_frontend *fe, u8 Mode, /* 0: Analog Mode ; 1: Digital Mode */ u8 IF_mode, /* for Analog Mode, 0: zero IF; 1: low IF */ @@ -1763,6 +1964,7 @@ u16 MXL5005_TunerConfig(struct dvb_frontend *fe, // > 0 : Failed // // // /////////////////////////////////////////////////////////////////////////////// +// DONE void MXL_SynthIFLO_Calc(struct dvb_frontend *fe) { struct mxl5005s_state *state = fe->tuner_priv; @@ -1801,6 +2003,7 @@ void MXL_SynthIFLO_Calc(struct dvb_frontend *fe) // > 0 : Failed // // // /////////////////////////////////////////////////////////////////////////////// +// DONE void MXL_SynthRFTGLO_Calc(struct dvb_frontend *fe) { struct mxl5005s_state *state = fe->tuner_priv; @@ -1839,6 +2042,7 @@ void MXL_SynthRFTGLO_Calc(struct dvb_frontend *fe) // > 0 : Failed // // // /////////////////////////////////////////////////////////////////////////////// +// DONE u16 MXL_OverwriteICDefault(struct dvb_frontend *fe) { u16 status = 0; @@ -1876,6 +2080,7 @@ u16 MXL_OverwriteICDefault(struct dvb_frontend *fe) // > 0 : Failed // // // /////////////////////////////////////////////////////////////////////////////// +// DONE u16 MXL_BlockInit(struct dvb_frontend *fe) { struct mxl5005s_state *state = fe->tuner_priv; @@ -1903,7 +2108,6 @@ u16 MXL_BlockInit(struct dvb_frontend *fe) status += MXL_ControlWrite(fe, BB_DLPF_BANDSEL, 2); break; case 6000000: - printk("%s() doing 6MHz digital\n", __func__); status += MXL_ControlWrite(fe, BB_DLPF_BANDSEL, 3); break; } @@ -1934,6 +2138,7 @@ u16 MXL_BlockInit(struct dvb_frontend *fe) else /* Single AGC Mode Dig Ana */ status += MXL_ControlWrite(fe, AGC_RF, state->Mode ? 15 : 12); + if (state->TOP == 55) /* TOP == 5.5 */ status += MXL_ControlWrite(fe, AGC_IF, 0x0); @@ -2163,10 +2368,6 @@ u16 MXL_BlockInit(struct dvb_frontend *fe) status += MXL_ControlWrite(fe, BB_IQSWAP, 0); else /* High IF */ status += MXL_ControlWrite(fe, BB_IQSWAP, 1); -#if 1 - status += MXL_ControlWrite(fe, RFSYN_CHP_GAIN, 2); -#endif - } if (state->Mod_Type == MXL_ANALOG_CABLE) { /* Analog Cable Mode */ @@ -2203,7 +2404,7 @@ u16 MXL_BlockInit(struct dvb_frontend *fe) } /* RSSI disable */ - if(state->EN_RSSI == 0) { + if(state->EN_RSSI==0) { status += MXL_ControlWrite(fe, SEQ_EXTSYNTHCALIF, 1); status += MXL_ControlWrite(fe, SEQ_EXTDCCAL, 1); status += MXL_ControlWrite(fe, AGC_EN_RSSI, 0); @@ -2412,7 +2613,6 @@ u16 MXL_IFSynthInit(struct dvb_frontend *fe) Fref = 324000000UL ; } if (state->IF_LO == 5380000UL) { - printk("%s() doing 5.38\n", __func__); status += MXL_ControlWrite(fe, IF_DIVVAL, 0x07) ; status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C) ; Fref = 322800000UL ; @@ -3095,7 +3295,6 @@ u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq) if (state->TF_Type == MXL_TF_C_H) // Tracking Filter type C-H for Hauppauge only { - printk("%s() CH filter\n", __func__); status += MXL_ControlWrite(fe, DAC_DIN_A, 0) ; if (state->RF_IN >= 43000000 && state->RF_IN < 150000000) @@ -3634,6 +3833,7 @@ u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq) return status ; } +// DONE u16 MXL_SetGPIO(struct dvb_frontend *fe, u8 GPIO_Num, u8 GPIO_Val) { u16 status = 0; @@ -3700,6 +3900,7 @@ u16 MXL_SetGPIO(struct dvb_frontend *fe, u8 GPIO_Num, u8 GPIO_Val) // >0 : Value exceed maximum allowed for control number // // // /////////////////////////////////////////////////////////////////////////////// +// DONE u16 MXL_ControlWrite(struct dvb_frontend *fe, u16 ControlNum, u32 value) { u16 status = 0; @@ -3740,6 +3941,7 @@ u16 MXL_ControlWrite(struct dvb_frontend *fe, u16 ControlNum, u32 value) // 2 : Control name not found // // // /////////////////////////////////////////////////////////////////////////////// +// DONE u16 MXL_ControlWrite_Group(struct dvb_frontend *fe, u16 controlNum, u32 value, u16 controlGroup) { struct mxl5005s_state *state = fe->tuner_priv; @@ -3846,6 +4048,7 @@ u16 MXL_ControlWrite_Group(struct dvb_frontend *fe, u16 controlNum, u32 value, u // -1 : Invalid Register Address // // // /////////////////////////////////////////////////////////////////////////////// +// DONE u16 MXL_RegWrite(struct dvb_frontend *fe, u8 RegNum, u8 RegVal) { struct mxl5005s_state *state = fe->tuner_priv; @@ -3885,6 +4088,7 @@ u16 MXL_RegWrite(struct dvb_frontend *fe, u8 RegNum, u8 RegVal) // -1 : Invalid Register Address // // // /////////////////////////////////////////////////////////////////////////////// +// DONE u16 MXL_RegRead(struct dvb_frontend *fe, u8 RegNum, u8 *RegVal) { struct mxl5005s_state *state = fe->tuner_priv; @@ -3921,6 +4125,7 @@ u16 MXL_RegRead(struct dvb_frontend *fe, u8 RegNum, u8 *RegVal) // -1 : Invalid control name // // // /////////////////////////////////////////////////////////////////////////////// +// DONE u16 MXL_ControlRead(struct dvb_frontend *fe, u16 controlNum, u32 *value) { struct mxl5005s_state *state = fe->tuner_priv; @@ -3992,6 +4197,7 @@ u16 MXL_ControlRead(struct dvb_frontend *fe, u16 controlNum, u32 *value) // -1 : Invalid control name // // // /////////////////////////////////////////////////////////////////////////////// +// DONE u16 MXL_ControlRegRead(struct dvb_frontend *fe, u16 controlNum, u8 *RegNum, int * count) { struct mxl5005s_state *state = fe->tuner_priv; @@ -4097,6 +4303,7 @@ u16 MXL_ControlRegRead(struct dvb_frontend *fe, u16 controlNum, u8 *RegNum, int // NONE // // // /////////////////////////////////////////////////////////////////////////////// +// DONE void MXL_RegWriteBit(struct dvb_frontend *fe, u8 address, u8 bit, u8 bitVal) { struct mxl5005s_state *state = fe->tuner_priv; @@ -4144,6 +4351,7 @@ void MXL_RegWriteBit(struct dvb_frontend *fe, u8 address, u8 bit, u8 bitVal) // Computed value // // // /////////////////////////////////////////////////////////////////////////////// +// DONE u32 MXL_Ceiling(u32 value, u32 resolution) { return (value/resolution + (value % resolution > 0 ? 1 : 0)); @@ -4152,6 +4360,7 @@ u32 MXL_Ceiling(u32 value, u32 resolution) // // Retrieve the Initialzation Registers // +// DONE u16 MXL_GetInitRegister(struct dvb_frontend *fe, u8 * RegNum, u8 *RegVal, int *count) { u16 status = 0; @@ -4174,6 +4383,7 @@ u16 MXL_GetInitRegister(struct dvb_frontend *fe, u8 * RegNum, u8 *RegVal, int *c return status; } +// DONE u16 MXL_GetCHRegister(struct dvb_frontend *fe, u8 * RegNum, u8 *RegVal, int *count) { u16 status = 0; @@ -4201,6 +4411,7 @@ u16 MXL_GetCHRegister(struct dvb_frontend *fe, u8 * RegNum, u8 *RegVal, int *cou return status; } +// DONE u16 MXL_GetCHRegister_ZeroIF(struct dvb_frontend *fe, u8 * RegNum, u8 *RegVal, int *count) { u16 status = 0; @@ -4218,6 +4429,7 @@ u16 MXL_GetCHRegister_ZeroIF(struct dvb_frontend *fe, u8 * RegNum, u8 *RegVal, i return status; } +// DONE u16 MXL_GetCHRegister_LowIF(struct dvb_frontend *fe, u8 * RegNum, u8 *RegVal, int *count) { u16 status = 0; @@ -4235,6 +4447,7 @@ u16 MXL_GetCHRegister_LowIF(struct dvb_frontend *fe, u8 * RegNum, u8 *RegVal, in return status; } +// DONE u16 MXL_GetMasterControl(u8 *MasterReg, int state) { if (state == 1) /* Load_Start */ @@ -4379,6 +4592,7 @@ u16 MXL_VCORange_Test(struct dvb_frontend *fe, int VCO_Range) return status; } +// DONE u16 MXL_Hystersis_Test(struct dvb_frontend *fe, int Hystersis) { struct mxl5005s_state *state = fe->tuner_priv; @@ -4389,224 +4603,155 @@ u16 MXL_Hystersis_Test(struct dvb_frontend *fe, int Hystersis) return status; } + #endif -/* End: Reference driver code found in the Realtek driver that - * is copyright MaxLinear */ -/* ---------------------------------------------------------------- - * Begin: Everything after here is new code to adapt the - * proprietary Realtek driver into a Linux API tuner. - * Copyright (C) 2008 Steven Toth - */ -static int mxl5005s_reset(struct dvb_frontend *fe) -{ - struct mxl5005s_state *state = fe->tuner_priv; - int ret = 0; +/* Linux driver related functions */ - u8 buf[2] = { 0xff, 0x00 }; - struct i2c_msg msg = { .addr = state->config->i2c_address, .flags = 0, - .buf = buf, .len = 2 }; - dprintk(2, "%s()\n", __func__); +int mxl5005s_init(struct dvb_frontend *fe) +{ + int MxlModMode; + int MxlIfMode; + unsigned long MxlBandwitdh; + unsigned long MxlIfFreqHz; + unsigned long MxlCrystalFreqHz; + int MxlAgcMode; + unsigned short MxlTop; + unsigned short MxlIfOutputLoad; + int MxlClockOut; + int MxlDivOut; + int MxlCapSel; + int MxlRssiOnOff; + unsigned char MxlStandard; + unsigned char MxlTfType; - if (fe->ops.i2c_gate_ctrl) - fe->ops.i2c_gate_ctrl(fe, 1); + /* Set MxL5005S parameters. */ + MxlModMode = MXL_DIGITAL_MODE; + MxlIfMode = MXL_ZERO_IF; +// steve + //MxlBandwitdh = MXL5005S_BANDWIDTH_8MHZ; + //MxlIfFreqHz = IF_FREQ_4570000HZ; + MxlBandwitdh = MXL5005S_BANDWIDTH_6MHZ; // config + MxlIfFreqHz = IF_FREQ_5380000HZ; // config + MxlCrystalFreqHz = CRYSTAL_FREQ_16000000HZ; // config + MxlAgcMode = MXL_SINGLE_AGC; + MxlTop = MXL5005S_TOP_25P2; + MxlIfOutputLoad = MXL5005S_IF_OUTPUT_LOAD_200_OHM; + MxlClockOut = MXL_CLOCK_OUT_DISABLE; + MxlDivOut = MXL_DIV_OUT_4; + MxlCapSel = MXL_CAP_SEL_ENABLE; + MxlRssiOnOff = MXL_RSSI_ENABLE; // config + MxlTfType = MXL_TF_C_H; // config - if (i2c_transfer(state->i2c, &msg, 1) != 1) { - printk(KERN_WARNING "mxl5005s I2C reset failed\n"); - ret = -EREMOTEIO; +#if 1 + MxlStandard = MXL_ATSC; // config +#else + // Set MxL5005S parameters according to standard mode + switch(StandardMode) + { + default: + case MXL5005S_STANDARD_DVBT: + MxlStandard = MXL_DVBT; + break; + case MXL5005S_STANDARD_ATSC: + MxlStandard = MXL_ATSC; + break; } +#endif - if (fe->ops.i2c_gate_ctrl) - fe->ops.i2c_gate_ctrl(fe, 0); + // TODO: this is bad, it trashes other configs + // Set MxL5005S extra module. + //pExtra->AgcMasterByte = (MxlAgcMode == MXL_DUAL_AGC) ? 0x4 : 0x0; - return ret; + MXL5005_TunerConfig( + fe, + (unsigned char)MxlModMode, + (unsigned char)MxlIfMode, + MxlBandwitdh, + MxlIfFreqHz, + MxlCrystalFreqHz, + (unsigned char)MxlAgcMode, + MxlTop, + MxlIfOutputLoad, + (unsigned char)MxlClockOut, + (unsigned char)MxlDivOut, + (unsigned char)MxlCapSel, + (unsigned char)MxlRssiOnOff, + MxlStandard, MxlTfType); + + return mxl5005s_init2(fe); } -/* Write a single byte to a single reg, latch the value if required by - * following the transaction with the latch byte. - */ -static int mxl5005s_writereg(struct dvb_frontend *fe, u8 reg, u8 val, int latch) +static int mxl5005s_set_params(struct dvb_frontend *fe, + struct dvb_frontend_parameters *params) { - struct mxl5005s_state *state = fe->tuner_priv; - u8 buf[3] = { reg, val, MXL5005S_LATCH_BYTE }; - struct i2c_msg msg = { .addr = state->config->i2c_address, .flags = 0, - .buf = buf, .len = 3 }; + u32 freq; + u32 bw; - if (latch == 0) - msg.len = 2; + if (fe->ops.info.type == FE_OFDM) + bw = params->u.ofdm.bandwidth; + else + bw = MXL5005S_BANDWIDTH_6MHZ; - dprintk(2, "%s(reg = 0x%x val = 0x%x addr = 0x%x)\n", __func__, reg, val, msg.addr); + freq = params->frequency; /* Hz */ + dprintk(1, "%s() freq=%d bw=%d\n", __func__, freq, bw); - if (i2c_transfer(state->i2c, &msg, 1) != 1) { - printk(KERN_WARNING "mxl5005s I2C write failed\n"); - return -EREMOTEIO; - } - return 0; + return mxl5005s_SetRfFreqHz(fe, freq); } -int mxl5005s_writeregs(struct dvb_frontend *fe, u8 *addrtable, u8 *datatable, u8 len) +static int mxl5005s_get_frequency(struct dvb_frontend *fe, u32 *frequency) { - int ret = 0, i; + struct mxl5005s_state *state = fe->tuner_priv; + dprintk(1, "%s()\n", __func__); - if (fe->ops.i2c_gate_ctrl) - fe->ops.i2c_gate_ctrl(fe, 1); + *frequency = state->RF_IN; - for (i = 0 ; i < len-1; i++) { - ret = mxl5005s_writereg(fe, addrtable[i], datatable[i], 0); - if (ret < 0) - break; - } + return 0; +} - ret = mxl5005s_writereg(fe, addrtable[i], datatable[i], 1); +static int mxl5005s_get_bandwidth(struct dvb_frontend *fe, u32 *bandwidth) +{ + struct mxl5005s_state *state = fe->tuner_priv; + dprintk(1, "%s()\n", __func__); - if (fe->ops.i2c_gate_ctrl) - fe->ops.i2c_gate_ctrl(fe, 0); + *bandwidth = state->Chan_Bandwidth; - return ret; + return 0; } - -int mxl5005s_init(struct dvb_frontend *fe) +static int mxl5005s_get_status(struct dvb_frontend *fe, u32 *status) { dprintk(1, "%s()\n", __func__); - return mxl5005s_reconfigure(fe, MXL_QAM, MXL5005S_BANDWIDTH_6MHZ); + + *status = 0; + // *status = TUNER_STATUS_LOCKED; + + return 0; } -int mxl5005s_reconfigure(struct dvb_frontend *fe, u32 mod_type, u32 bandwidth) +static int mxl5005s_init2(struct dvb_frontend *fe) { struct mxl5005s_state *state = fe->tuner_priv; - u8 AddrTable[MXL5005S_REG_WRITING_TABLE_LEN_MAX]; u8 ByteTable[MXL5005S_REG_WRITING_TABLE_LEN_MAX]; int TableLen; - dprintk(1, "%s(type=%d, bw=%d)\n", __func__, mod_type, bandwidth); + dprintk(1, "%s()\n", __func__); - mxl5005s_reset(fe); + /* Initialize MxL5005S tuner according to MxL5005S tuner example code. */ /* Tuner initialization stage 0 */ MXL_GetMasterControl(ByteTable, MC_SYNTH_RESET); AddrTable[0] = MASTER_CONTROL_ADDR; ByteTable[0] |= state->config->AgcMasterByte; - mxl5005s_writeregs(fe, AddrTable, ByteTable, 1); - - mxl5005s_AssignTunerMode(fe, mod_type, bandwidth); + mxl5005s_SetRegsWithTable(fe, AddrTable, ByteTable, 1); /* Tuner initialization stage 1 */ MXL_GetInitRegister(fe, AddrTable, ByteTable, &TableLen); - mxl5005s_writeregs(fe, AddrTable, ByteTable, TableLen); - - return 0; -} - -int mxl5005s_AssignTunerMode(struct dvb_frontend *fe, u32 mod_type, u32 bandwidth) -{ - struct mxl5005s_state *state = fe->tuner_priv; - struct mxl5005s_config *c = state->config; - - InitTunerControls(fe); - - /* Set MxL5005S parameters. */ - MXL5005_TunerConfig( - fe, - c->mod_mode, - c->if_mode, - bandwidth, - c->if_freq, - c->xtal_freq, - c->agc_mode, - c->top, - c->output_load, - c->clock_out, - c->div_out, - c->cap_select, - c->rssi_enable, - mod_type, - c->tracking_filter); - - return 0; -} - -static int mxl5005s_set_params(struct dvb_frontend *fe, - struct dvb_frontend_parameters *params) -{ - struct mxl5005s_state *state = fe->tuner_priv; - u32 req_mode, req_bw = 0; - int ret; - - dprintk(1, "%s()\n", __func__); - - if (fe->ops.info.type == FE_ATSC) { - switch (params->u.vsb.modulation) { - case VSB_8: - req_mode = MXL_ATSC; break; - default: - case QAM_64: - case QAM_256: - case QAM_AUTO: - req_mode = MXL_QAM; break; - } - } - else req_mode = MXL_DVBT; - - /* Change tuner for new modulation type if reqd */ - if (req_mode != state->current_mode) { - switch (req_mode) { - case VSB_8: - case QAM_64: - case QAM_256: - case QAM_AUTO: - req_bw = MXL5005S_BANDWIDTH_6MHZ; - break; - default: - /* Assume DVB-T */ - switch (params->u.ofdm.bandwidth) { - case BANDWIDTH_6_MHZ: - req_bw = MXL5005S_BANDWIDTH_6MHZ; - break; - case BANDWIDTH_7_MHZ: - req_bw = MXL5005S_BANDWIDTH_7MHZ; - break; - case BANDWIDTH_AUTO: - case BANDWIDTH_8_MHZ: - req_bw = MXL5005S_BANDWIDTH_8MHZ; - break; - } - } - - state->current_mode = req_mode; - ret = mxl5005s_reconfigure(fe, req_mode, req_bw); - - } else - ret = 0; - - if (ret == 0) { - dprintk(1, "%s() freq=%d\n", __func__, params->frequency); - ret = mxl5005s_SetRfFreqHz(fe, params->frequency); - } - - return ret; -} - -static int mxl5005s_get_frequency(struct dvb_frontend *fe, u32 *frequency) -{ - struct mxl5005s_state *state = fe->tuner_priv; - dprintk(1, "%s()\n", __func__); - - *frequency = state->RF_IN; - - return 0; -} - -static int mxl5005s_get_bandwidth(struct dvb_frontend *fe, u32 *bandwidth) -{ - struct mxl5005s_state *state = fe->tuner_priv; - dprintk(1, "%s()\n", __func__); - - *bandwidth = state->Chan_Bandwidth; + mxl5005s_SetRegsWithTable(fe, AddrTable, ByteTable, TableLen); return 0; } @@ -4633,6 +4778,7 @@ static const struct dvb_tuner_ops mxl5005s_tuner_ops = { .set_params = mxl5005s_set_params, .get_frequency = mxl5005s_get_frequency, .get_bandwidth = mxl5005s_get_bandwidth, + .get_status = mxl5005s_get_status }; struct dvb_frontend *mxl5005s_attach(struct dvb_frontend *fe, @@ -4649,7 +4795,6 @@ struct dvb_frontend *mxl5005s_attach(struct dvb_frontend *fe, state->frontend = fe; state->config = config; state->i2c = i2c; - state->current_mode = MXL_QAM; printk(KERN_INFO "MXL5005S: Attached at address 0x%02x\n", config->i2c_address); @@ -4661,6 +4806,9 @@ struct dvb_frontend *mxl5005s_attach(struct dvb_frontend *fe, EXPORT_SYMBOL(mxl5005s_attach); MODULE_DESCRIPTION("MaxLinear MXL5005S silicon tuner driver"); +MODULE_AUTHOR("Jan Hoogenraad"); +MODULE_AUTHOR("Barnaby Shearer"); +MODULE_AUTHOR("Andy Hasper"); MODULE_AUTHOR("Steven Toth"); MODULE_LICENSE("GPL"); diff --git a/linux/drivers/media/common/tuners/mxl5005s.h b/linux/drivers/media/common/tuners/mxl5005s.h index 7658401f3..7d0727d44 100644 --- a/linux/drivers/media/common/tuners/mxl5005s.h +++ b/linux/drivers/media/common/tuners/mxl5005s.h @@ -1,119 +1,66 @@ /* - MaxLinear MXL5005S VSB/QAM/DVBT tuner driver + * For the Realtek RTL chip RTL2831U + * Realtek Release Date: 2008-03-14, ver 080314 + * Realtek version RTL2831 Linux driver version 080314 + * ver 080314 + * + * for linux kernel version 2.6.21.4 - 2.6.22-14 + * support MXL5005s and MT2060 tuners (support tuner auto-detecting) + * support two IR types -- RC5 and NEC + * + * Known boards with Realtek RTL chip RTL2821U + * Freecom USB stick 14aa:0160 (version 4) + * Conceptronic CTVDIGRCU + * + * Copyright (c) 2008 Realtek + * Copyright (c) 2008 Jan Hoogenraad, Barnaby Shearer, Andy Hasper + * This code is placed under the terms of the GNU General Public License + * + * Released by Realtek under GPLv2. + * Thanks to Realtek for a lot of support we received ! + * + * Revision: 080314 - original version + */ - Copyright (C) 2008 MaxLinear - Copyright (C) 2008 Steven Toth - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. +#ifndef __MXL5005S_H +#define __MXL5005S_H - You should have received a copy of the GNU General Public License - along with this program; if not, write to the Free Software - Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. +#include -*/ +/* IF frequency */ +enum IF_FREQ_HZ +{ + IF_FREQ_4570000HZ = 4570000, ///< IF frequency = 4.57 MHz + IF_FREQ_4571429HZ = 4571429, ///< IF frequency = 4.571 MHz + IF_FREQ_5380000HZ = 5380000, ///< IF frequency = 5.38 MHz + IF_FREQ_36000000HZ = 36000000, ///< IF frequency = 36.000 MHz + IF_FREQ_36125000HZ = 36125000, ///< IF frequency = 36.125 MHz + IF_FREQ_36166667HZ = 36166667, ///< IF frequency = 36.167 MHz + IF_FREQ_44000000HZ = 44000000, ///< IF frequency = 44.000 MHz +}; -#ifndef __MXL5005S_H -#define __MXL5005S_H +/* Crystal frequency */ +enum CRYSTAL_FREQ_HZ +{ + CRYSTAL_FREQ_4000000HZ = 4000000, ///< Crystal frequency = 4.0 MHz + CRYSTAL_FREQ_16000000HZ = 16000000, ///< Crystal frequency = 16.0 MHz + CRYSTAL_FREQ_25000000HZ = 25000000, ///< Crystal frequency = 25.0 MHz + CRYSTAL_FREQ_28800000HZ = 28800000, ///< Crystal frequency = 28.8 MHz +}; struct mxl5005s_config { - /* 7 bit i2c address */ u8 i2c_address; -#define IF_FREQ_4570000HZ 4570000 -#define IF_FREQ_4571429HZ 4571429 -#define IF_FREQ_5380000HZ 5380000 -#define IF_FREQ_36000000HZ 36000000 -#define IF_FREQ_36125000HZ 36125000 -#define IF_FREQ_36166667HZ 36166667 -#define IF_FREQ_44000000HZ 44000000 - u32 if_freq; - -#define CRYSTAL_FREQ_4000000HZ 4000000 -#define CRYSTAL_FREQ_16000000HZ 16000000 -#define CRYSTAL_FREQ_25000000HZ 25000000 -#define CRYSTAL_FREQ_28800000HZ 28800000 - u32 xtal_freq; - -#define MXL_DUAL_AGC 0 -#define MXL_SINGLE_AGC 1 - u8 agc_mode; - -#define MXL_TF_DEFAULT 0 -#define MXL_TF_OFF 1 -#define MXL_TF_C 2 -#define MXL_TF_C_H 3 -#define MXL_TF_D 4 -#define MXL_TF_D_L 5 -#define MXL_TF_E 6 -#define MXL_TF_F 7 -#define MXL_TF_E_2 8 -#define MXL_TF_E_NA 9 -#define MXL_TF_G 10 - u8 tracking_filter; - -#define MXL_RSSI_DISABLE 0 -#define MXL_RSSI_ENABLE 1 - u8 rssi_enable; - -#define MXL_CAP_SEL_DISABLE 0 -#define MXL_CAP_SEL_ENABLE 1 - u8 cap_select; - -#define MXL_DIV_OUT_1 0 -#define MXL_DIV_OUT_4 1 - u8 div_out; - -#define MXL_CLOCK_OUT_DISABLE 0 -#define MXL_CLOCK_OUT_ENABLE 1 - u8 clock_out; - -#define MXL5005S_IF_OUTPUT_LOAD_200_OHM 200 -#define MXL5005S_IF_OUTPUT_LOAD_300_OHM 300 - u32 output_load; - -#define MXL5005S_TOP_5P5 55 -#define MXL5005S_TOP_7P2 72 -#define MXL5005S_TOP_9P2 92 -#define MXL5005S_TOP_11P0 110 -#define MXL5005S_TOP_12P9 129 -#define MXL5005S_TOP_14P7 147 -#define MXL5005S_TOP_16P8 168 -#define MXL5005S_TOP_19P4 194 -#define MXL5005S_TOP_21P2 212 -#define MXL5005S_TOP_23P2 232 -#define MXL5005S_TOP_25P2 252 -#define MXL5005S_TOP_27P1 271 -#define MXL5005S_TOP_29P2 292 -#define MXL5005S_TOP_31P7 317 -#define MXL5005S_TOP_34P9 349 - u32 top; - -#define MXL_ANALOG_MODE 0 -#define MXL_DIGITAL_MODE 1 - u8 mod_mode; - -#define MXL_ZERO_IF 0 -#define MXL_LOW_IF 1 - u8 if_mode; - /* Stuff I don't know what to do with */ u8 AgcMasterByte; }; -#if defined(CONFIG_DVB_TUNER_MXL5005S) || \ - (defined(CONFIG_DVB_TUNER_MXL5005S_MODULE) && defined(MODULE)) +#if defined(CONFIG_MEDIA_TUNER_MXL5005S) || (defined(CONFIG_MEDIA_TUNER_MXL5005S_MODULE) && defined(MODULE)) extern struct dvb_frontend *mxl5005s_attach(struct dvb_frontend *fe, struct i2c_adapter *i2c, - struct mxl5005s_config *config) + struct mxl5005s_config *config); #else static inline struct dvb_frontend *mxl5005s_attach(struct dvb_frontend *fe, struct i2c_adapter *i2c, -- cgit v1.2.3 From ca2193821bf223d0e8e1add2ede0a26fc8209c92 Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Thu, 1 May 2008 03:15:38 -0400 Subject: mxl5005s: Re-org code and update copyrights From: Steven Toth Re-org code and update copyrights Signed-off-by: Steven Toth Signed-off-by: Mauro Carvalho Chehab --- linux/drivers/media/common/tuners/mxl5005s.c | 686 +++++++++++---------------- linux/drivers/media/common/tuners/mxl5005s.h | 143 ++++-- 2 files changed, 371 insertions(+), 458 deletions(-) (limited to 'linux/drivers/media/common/tuners') diff --git a/linux/drivers/media/common/tuners/mxl5005s.c b/linux/drivers/media/common/tuners/mxl5005s.c index 60c5a7704..0e0a5b3fa 100644 --- a/linux/drivers/media/common/tuners/mxl5005s.c +++ b/linux/drivers/media/common/tuners/mxl5005s.c @@ -1,27 +1,62 @@ /* - * For the Realtek RTL chip RTL2831U - * Realtek Release Date: 2008-03-14, ver 080314 - * Realtek version RTL2831 Linux driver version 080314 - * ver 080314 - * - * for linux kernel version 2.6.21.4 - 2.6.22-14 - * support MXL5005s and MT2060 tuners (support tuner auto-detecting) - * support two IR types -- RC5 and NEC - * - * Known boards with Realtek RTL chip RTL2821U - * Freecom USB stick 14aa:0160 (version 4) - * Conceptronic CTVDIGRCU - * - * Copyright (c) 2008 Realtek - * Copyright (c) 2008 Jan Hoogenraad, Barnaby Shearer, Andy Hasper - * This code is placed under the terms of the GNU General Public License - * - * Released by Realtek under GPLv2. - * Thanks to Realtek for a lot of support we received ! - * - * Revision: 080314 - original version - */ + MaxLinear MXL5005S VSB/QAM/DVBT tuner driver + + Copyright (C) 2008 MaxLinear + Copyright (C) 2006 Steven Toth + Functions: + mxl5005s_reset() + mxl5005s_writereg() + mxl5005s_writeregs() + mxl5005s_init() + mxl5005s_reconfigure() + mxl5005s_AssignTunerMode() + mxl5005s_set_params() + mxl5005s_get_frequency() + mxl5005s_get_bandwidth() + mxl5005s_release() + mxl5005s_attach() + + Copyright (c) 2008 Realtek + Copyright (c) 2008 Jan Hoogenraad, Barnaby Shearer, Andy Hasper + Functions: + mxl5005s_SetRfFreqHz() + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + +*/ + +/* + History of this driver (Steven Toth): + I was given a public release of a linux driver that included + support for the MaxLinear MXL5005S silicon tuner. Analysis of + the tuner driver showed clearly three things. + + 1. The tuner driver didn't support the LinuxTV tuner API + so the code Realtek added had to be removed. + + 2. A significant amount of the driver is reference driver code + from MaxLinear, I felt it was important to identify and + preserve this. + 3. New code has to be added to interface correctly with the + LinuxTV API, as a regular kernel module. + + Other than the reference driver enum's, I've clearly marked + sections of the code and retained the copyright of the + respective owners. +*/ #include #include #include @@ -31,10 +66,10 @@ #include "dvb_frontend.h" #include "mxl5005s.h" -static int debug; +static int debug = 2; #define dprintk(level, arg...) do { \ - if (debug >= level) \ + if (level <= debug) \ printk(arg); \ } while (0) @@ -50,13 +85,6 @@ static int debug; #define MXLCTRL_NUM 189 #define MASTER_CONTROL_ADDR 9 -/* Enumeration of AGC Mode */ -typedef enum -{ - MXL_DUAL_AGC = 0, - MXL_SINGLE_AGC -} AGC_Mode; - /* Enumeration of Master Control Register State */ typedef enum { @@ -66,51 +94,6 @@ typedef enum MC_SEQ_OFF } Master_Control_State; -/* Enumeration of MXL5005 Tuner Mode */ -typedef enum -{ - MXL_ANALOG_MODE = 0, - MXL_DIGITAL_MODE -} Tuner_Mode; - -/* Enumeration of MXL5005 Tuner IF Mode */ -typedef enum -{ - MXL_ZERO_IF = 0, - MXL_LOW_IF -} Tuner_IF_Mode; - -/* Enumeration of MXL5005 Tuner Clock Out Mode */ -typedef enum -{ - MXL_CLOCK_OUT_DISABLE = 0, - MXL_CLOCK_OUT_ENABLE -} Tuner_Clock_Out; - -/* Enumeration of MXL5005 Tuner Div Out Mode */ -typedef enum -{ - MXL_DIV_OUT_1 = 0, - MXL_DIV_OUT_4 - -} Tuner_Div_Out; - -/* Enumeration of MXL5005 Tuner Pull-up Cap Select Mode */ -typedef enum -{ - MXL_CAP_SEL_DISABLE = 0, - MXL_CAP_SEL_ENABLE - -} Tuner_Cap_Select; - -/* Enumeration of MXL5005 Tuner RSSI Mode */ -typedef enum -{ - MXL_RSSI_DISABLE = 0, - MXL_RSSI_ENABLE - -} Tuner_RSSI; - /* Enumeration of MXL5005 Tuner Modulation Type */ typedef enum { @@ -122,22 +105,6 @@ typedef enum MXL_ANALOG_OTA } Tuner_Modu_Type; -/* Enumeration of MXL5005 Tuner Tracking Filter Type */ -typedef enum -{ - MXL_TF_DEFAULT = 0, - MXL_TF_OFF, - MXL_TF_C, - MXL_TF_C_H, - MXL_TF_D, - MXL_TF_D_L, - MXL_TF_E, - MXL_TF_F, - MXL_TF_E_2, - MXL_TF_E_NA, - MXL_TF_G -} Tuner_TF_Type; - /* MXL5005 Tuner Register Struct */ typedef struct _TunerReg_struct { @@ -268,33 +235,6 @@ enum }; #define MXL5005S_BANDWIDTH_MODE_NUM 3 -/* Top modes */ -enum -{ - MXL5005S_TOP_5P5 = 55, - MXL5005S_TOP_7P2 = 72, - MXL5005S_TOP_9P2 = 92, - MXL5005S_TOP_11P0 = 110, - MXL5005S_TOP_12P9 = 129, - MXL5005S_TOP_14P7 = 147, - MXL5005S_TOP_16P8 = 168, - MXL5005S_TOP_19P4 = 194, - MXL5005S_TOP_21P2 = 212, - MXL5005S_TOP_23P2 = 232, - MXL5005S_TOP_25P2 = 252, - MXL5005S_TOP_27P1 = 271, - MXL5005S_TOP_29P2 = 292, - MXL5005S_TOP_31P7 = 317, - MXL5005S_TOP_34P9 = 349, -}; - -/* IF output load */ -enum -{ - MXL5005S_IF_OUTPUT_LOAD_200_OHM = 200, - MXL5005S_IF_OUTPUT_LOAD_300_OHM = 300, -}; - /* MXL5005 Tuner Control Struct */ typedef struct _TunerControl_struct { u16 Ctrl_Num; /* Control Number */ @@ -349,13 +289,15 @@ struct mxl5005s_state TunerRegs[TUNER_REGS_NUM]; /* Tuner Register Array Pointer */ /* Linux driver framework specific */ - const struct mxl5005s_config *config; - + struct mxl5005s_config *config; struct dvb_frontend *frontend; struct i2c_adapter *i2c; + + /* Cache values */ + u32 current_mode; + }; -// funcs u16 MXL_ControlWrite(struct dvb_frontend *fe, u16 ControlNum, u32 value); u16 MXL_ControlRead(struct dvb_frontend *fe, u16 controlNum, u32 *value); u16 MXL_GetMasterControl(u8 *MasterReg, int state); @@ -372,14 +314,26 @@ u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq); void MXL_SynthIFLO_Calc(struct dvb_frontend *fe); void MXL_SynthRFTGLO_Calc(struct dvb_frontend *fe); u16 MXL_GetCHRegister_ZeroIF(struct dvb_frontend *fe, u8 *RegNum, u8 *RegVal, int *count); -int mxl5005s_SetRegsWithTable(struct dvb_frontend *fe, u8 *pAddrTable, u8 *pByteTable, int TableLen); +int mxl5005s_writeregs(struct dvb_frontend *fe, u8 *addrtable, u8 *datatable, u8 len); u16 MXL_IFSynthInit(struct dvb_frontend *fe); -static int mxl5005s_init2(struct dvb_frontend *fe); +int mxl5005s_AssignTunerMode(struct dvb_frontend *fe, u32 mod_type, u32 bandwidth); +int mxl5005s_reconfigure(struct dvb_frontend *fe, u32 mod_type, u32 bandwidth); + +/* ---------------------------------------------------------------- + * Begin: Custom code salvaged from the Realtek driver. + * Copyright (c) 2008 Realtek + * Copyright (c) 2008 Jan Hoogenraad, Barnaby Shearer, Andy Hasper + * This code is placed under the terms of the GNU General Public License + * + * Released by Realtek under GPLv2. + * Thanks to Realtek for a lot of support we received ! + * + * Revision: 080314 - original version + */ int mxl5005s_SetRfFreqHz(struct dvb_frontend *fe, unsigned long RfFreqHz) { struct mxl5005s_state *state = fe->tuner_priv; - u8 AgcMasterByte = state->config->AgcMasterByte; unsigned char AddrTable[MXL5005S_REG_WRITING_TABLE_LEN_MAX]; unsigned char ByteTable[MXL5005S_REG_WRITING_TABLE_LEN_MAX]; int TableLen; @@ -396,7 +350,7 @@ int mxl5005s_SetRfFreqHz(struct dvb_frontend *fe, unsigned long RfFreqHz) AddrTable[0] = MASTER_CONTROL_ADDR; ByteTable[0] |= state->config->AgcMasterByte; - mxl5005s_SetRegsWithTable(fe, AddrTable, ByteTable, 1); + mxl5005s_writeregs(fe, AddrTable, ByteTable, 1); // Tuner RF frequency setting stage 1 MXL_TuneRF(fe, RfFreqHz); @@ -410,13 +364,13 @@ int mxl5005s_SetRfFreqHz(struct dvb_frontend *fe, unsigned long RfFreqHz) MXL_GetMasterControl(&MasterControlByte, MC_LOAD_START) ; AddrTable[TableLen] = MASTER_CONTROL_ADDR ; - ByteTable[TableLen] = MasterControlByte | AgcMasterByte; + ByteTable[TableLen] = MasterControlByte | state->config->AgcMasterByte; TableLen += 1; - mxl5005s_SetRegsWithTable(fe, AddrTable, ByteTable, TableLen); + mxl5005s_writeregs(fe, AddrTable, ByteTable, TableLen); // Wait 30 ms. - msleep(30); + msleep(150); // Tuner RF frequency setting stage 2 MXL_ControlWrite(fe, SEQ_FSM_PULSE, 1) ; @@ -425,167 +379,21 @@ int mxl5005s_SetRfFreqHz(struct dvb_frontend *fe, unsigned long RfFreqHz) MXL_GetMasterControl(&MasterControlByte, MC_LOAD_START) ; AddrTable[TableLen] = MASTER_CONTROL_ADDR ; - ByteTable[TableLen] = MasterControlByte | AgcMasterByte ; + ByteTable[TableLen] = MasterControlByte | state->config->AgcMasterByte ; TableLen += 1; - mxl5005s_SetRegsWithTable(fe, AddrTable, ByteTable, TableLen); - - return 0; -} - -/* Write a single byte to a single reg */ -static int mxl5005s_writereg(struct dvb_frontend *fe, u8 reg, u8 val) -{ - struct mxl5005s_state *state = fe->tuner_priv; - u8 buf[2] = { reg, val }; - struct i2c_msg msg = { .addr = state->config->i2c_address, .flags = 0, - .buf = buf, .len = 2 }; - - if (i2c_transfer(state->i2c, &msg, 1) != 1) { - printk(KERN_WARNING "mxl5005s I2C write failed\n"); - return -EREMOTEIO; - } - return 0; -} - -/* Write a word to a single reg */ -static int mxl5005s_writereg16(struct dvb_frontend *fe, u8 reg, u16 val) -{ - struct mxl5005s_state *state = fe->tuner_priv; - u8 buf[3] = { reg, val >> 8 , val & 0xff }; - struct i2c_msg msg = { .addr = state->config->i2c_address, .flags = 0, - .buf = buf, .len = 3 }; - - if (i2c_transfer(state->i2c, &msg, 1) != 1) { - printk(KERN_WARNING "mxl5005s I2C write16 failed\n"); - return -EREMOTEIO; - } - return 0; -} - -int mxl5005s_SetRegsWithTable(struct dvb_frontend *fe, u8 *pAddrTable, u8 *pByteTable, int TableLen) -{ - int i, ret; - u8 end_two_bytes_buf[]={ 0 , 0 }; - - for( i = 0 ; i < TableLen - 1 ; i++) - { -#if 0 - if ( TUNER_WI2C(dib , tuner_addr , pAddrTable[i] , &pByteTable[i] , 1 ) ) - return FUNCTION_ERROR; -#else - ret = mxl5005s_writereg(fe, pAddrTable[i], pByteTable[i]); - if (!ret) - return ret; -#endif - } - - end_two_bytes_buf[0] = pByteTable[i]; - end_two_bytes_buf[1] = MXL5005S_LATCH_BYTE; - -#if 0 - if ( TUNER_WI2C(dib , tuner_addr , pAddrTable[i] , end_two_bytes_buf , 2 ) ) - return FUNCTION_ERROR; -#else - ret = mxl5005s_writereg16(fe, pAddrTable[i], (end_two_bytes_buf[0] << 8) | end_two_bytes_buf[1]); -#endif - - return ret; -} - -int mxl5005s_SetRegMaskBits(struct dvb_frontend *fe, - unsigned char RegAddr, - unsigned char Msb, - unsigned char Lsb, - const unsigned char WritingValue - ) -{ - int i; - - unsigned char Mask; - unsigned char Shift; - unsigned char RegByte; - - /* Generate mask and shift according to MSB and LSB. */ - Mask = 0; - for(i = Lsb; i < (unsigned char)(Msb + 1); i++) - Mask |= 0x1 << i; - - Shift = Lsb; - - /* Get tuner register byte according to register adddress. */ - MXL_RegRead(fe, RegAddr, &RegByte); - - /* Reserve register byte unmask bit with mask and inlay writing value into it. */ - RegByte &= ~Mask; - RegByte |= (WritingValue << Shift) & Mask; - - /* Update tuner register byte table. */ - MXL_RegWrite(fe, RegAddr, RegByte); - - /* Write tuner register byte with writing byte. */ - return mxl5005s_SetRegsWithTable(fe, &RegAddr, &RegByte, 1); -} -#if 0 -// DONE -int mxl5005s_SetSpectrumMode(struct dvb_frontend *fe, int SpectrumMode) -{ - struct mxl5005s_state *state = fe->tuner_priv; - static const unsigned char BbIqswapTable[SPECTRUM_MODE_NUM] = - { - /* BB_IQSWAP */ - 0, /* Normal spectrum */ - 1, /* Inverse spectrum */ - }; - - /* Set BB_IQSWAP according to BB_IQSWAP table and spectrum mode. */ - mxl5005s_SetRegMaskBits(fe, - MXL5005S_BB_IQSWAP_ADDR, - MXL5005S_BB_IQSWAP_MSB, - MXL5005S_BB_IQSWAP_LSB, - BbIqswapTable[SpectrumMode]); - - return FUNCTION_SUCCESS; -} - -// DONE -int mxl5005s_SetBandwidthHz(struct dvb_frontend *fe, unsigned long BandwidthHz) -{ - struct mxl5005s_state *state = fe->tuner_priv; - - unsigned char BbDlpfBandsel; - - /* Set BB_DLPF_BANDSEL according to bandwidth. */ - switch(BandwidthHz) - { - default: - case MXL5005S_BANDWIDTH_6MHZ: - BbDlpfBandsel = 3; - break; - case MXL5005S_BANDWIDTH_7MHZ: - BbDlpfBandsel = 2; - break; - case MXL5005S_BANDWIDTH_8MHZ: - BbDlpfBandsel = 0; - break; - } - - if(pExtra->SetRegMaskBits(dib,pTuner, MXL5005S_BB_DLPF_BANDSEL_ADDR, MXL5005S_BB_DLPF_BANDSEL_MSB, - MXL5005S_BB_DLPF_BANDSEL_LSB, BbDlpfBandsel) != 0) - goto error_status_set_tuner_registers; + mxl5005s_writeregs(fe, AddrTable, ByteTable, TableLen); + msleep(100); return 0; - - -error_status_set_tuner_registers: - return -1; } -#endif +/* End: Custom code taken from the Realtek driver */ -// The following context is source code provided by MaxLinear. -// MaxLinear source code - MXL5005_Initialize.cpp -// DONE +/* ---------------------------------------------------------------- + * Begin: Reference driver code found in the Realtek driver. + * Copyright (c) 2008 MaxLinear + */ u16 MXL5005_RegisterInit(struct dvb_frontend *fe) { struct mxl5005s_state *state = fe->tuner_priv; @@ -907,7 +715,6 @@ u16 MXL5005_RegisterInit(struct dvb_frontend *fe) return 0 ; } -// DONE u16 MXL5005_ControlInit(struct dvb_frontend *fe) { struct mxl5005s_state *state = fe->tuner_priv; @@ -1851,7 +1658,6 @@ u16 MXL5005_ControlInit(struct dvb_frontend *fe) // MaxLinear source code - MXL5005_c.cpp // MXL5005.cpp : Defines the initialization routines for the DLL. // 2.6.12 -// DONE void InitTunerControls(struct dvb_frontend *fe) { MXL5005_RegisterInit(fe); @@ -1894,7 +1700,6 @@ void InitTunerControls(struct dvb_frontend *fe) // > 0 : Failed // // // /////////////////////////////////////////////////////////////////////////////// -// DONE u16 MXL5005_TunerConfig(struct dvb_frontend *fe, u8 Mode, /* 0: Analog Mode ; 1: Digital Mode */ u8 IF_mode, /* for Analog Mode, 0: zero IF; 1: low IF */ @@ -1964,7 +1769,6 @@ u16 MXL5005_TunerConfig(struct dvb_frontend *fe, // > 0 : Failed // // // /////////////////////////////////////////////////////////////////////////////// -// DONE void MXL_SynthIFLO_Calc(struct dvb_frontend *fe) { struct mxl5005s_state *state = fe->tuner_priv; @@ -2003,7 +1807,6 @@ void MXL_SynthIFLO_Calc(struct dvb_frontend *fe) // > 0 : Failed // // // /////////////////////////////////////////////////////////////////////////////// -// DONE void MXL_SynthRFTGLO_Calc(struct dvb_frontend *fe) { struct mxl5005s_state *state = fe->tuner_priv; @@ -2042,7 +1845,6 @@ void MXL_SynthRFTGLO_Calc(struct dvb_frontend *fe) // > 0 : Failed // // // /////////////////////////////////////////////////////////////////////////////// -// DONE u16 MXL_OverwriteICDefault(struct dvb_frontend *fe) { u16 status = 0; @@ -2080,7 +1882,6 @@ u16 MXL_OverwriteICDefault(struct dvb_frontend *fe) // > 0 : Failed // // // /////////////////////////////////////////////////////////////////////////////// -// DONE u16 MXL_BlockInit(struct dvb_frontend *fe) { struct mxl5005s_state *state = fe->tuner_priv; @@ -2108,6 +1909,7 @@ u16 MXL_BlockInit(struct dvb_frontend *fe) status += MXL_ControlWrite(fe, BB_DLPF_BANDSEL, 2); break; case 6000000: + printk("%s() doing 6MHz digital\n", __func__); status += MXL_ControlWrite(fe, BB_DLPF_BANDSEL, 3); break; } @@ -2138,7 +1940,6 @@ u16 MXL_BlockInit(struct dvb_frontend *fe) else /* Single AGC Mode Dig Ana */ status += MXL_ControlWrite(fe, AGC_RF, state->Mode ? 15 : 12); - if (state->TOP == 55) /* TOP == 5.5 */ status += MXL_ControlWrite(fe, AGC_IF, 0x0); @@ -2368,6 +2169,10 @@ u16 MXL_BlockInit(struct dvb_frontend *fe) status += MXL_ControlWrite(fe, BB_IQSWAP, 0); else /* High IF */ status += MXL_ControlWrite(fe, BB_IQSWAP, 1); +#if 1 + status += MXL_ControlWrite(fe, RFSYN_CHP_GAIN, 2); +#endif + } if (state->Mod_Type == MXL_ANALOG_CABLE) { /* Analog Cable Mode */ @@ -2404,7 +2209,7 @@ u16 MXL_BlockInit(struct dvb_frontend *fe) } /* RSSI disable */ - if(state->EN_RSSI==0) { + if(state->EN_RSSI == 0) { status += MXL_ControlWrite(fe, SEQ_EXTSYNTHCALIF, 1); status += MXL_ControlWrite(fe, SEQ_EXTDCCAL, 1); status += MXL_ControlWrite(fe, AGC_EN_RSSI, 0); @@ -2613,6 +2418,7 @@ u16 MXL_IFSynthInit(struct dvb_frontend *fe) Fref = 324000000UL ; } if (state->IF_LO == 5380000UL) { + printk("%s() doing 5.38\n", __func__); status += MXL_ControlWrite(fe, IF_DIVVAL, 0x07) ; status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C) ; Fref = 322800000UL ; @@ -3295,6 +3101,7 @@ u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq) if (state->TF_Type == MXL_TF_C_H) // Tracking Filter type C-H for Hauppauge only { + printk("%s() CH filter\n", __func__); status += MXL_ControlWrite(fe, DAC_DIN_A, 0) ; if (state->RF_IN >= 43000000 && state->RF_IN < 150000000) @@ -3833,7 +3640,6 @@ u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq) return status ; } -// DONE u16 MXL_SetGPIO(struct dvb_frontend *fe, u8 GPIO_Num, u8 GPIO_Val) { u16 status = 0; @@ -3900,7 +3706,6 @@ u16 MXL_SetGPIO(struct dvb_frontend *fe, u8 GPIO_Num, u8 GPIO_Val) // >0 : Value exceed maximum allowed for control number // // // /////////////////////////////////////////////////////////////////////////////// -// DONE u16 MXL_ControlWrite(struct dvb_frontend *fe, u16 ControlNum, u32 value) { u16 status = 0; @@ -3941,7 +3746,6 @@ u16 MXL_ControlWrite(struct dvb_frontend *fe, u16 ControlNum, u32 value) // 2 : Control name not found // // // /////////////////////////////////////////////////////////////////////////////// -// DONE u16 MXL_ControlWrite_Group(struct dvb_frontend *fe, u16 controlNum, u32 value, u16 controlGroup) { struct mxl5005s_state *state = fe->tuner_priv; @@ -4048,7 +3852,6 @@ u16 MXL_ControlWrite_Group(struct dvb_frontend *fe, u16 controlNum, u32 value, u // -1 : Invalid Register Address // // // /////////////////////////////////////////////////////////////////////////////// -// DONE u16 MXL_RegWrite(struct dvb_frontend *fe, u8 RegNum, u8 RegVal) { struct mxl5005s_state *state = fe->tuner_priv; @@ -4088,7 +3891,6 @@ u16 MXL_RegWrite(struct dvb_frontend *fe, u8 RegNum, u8 RegVal) // -1 : Invalid Register Address // // // /////////////////////////////////////////////////////////////////////////////// -// DONE u16 MXL_RegRead(struct dvb_frontend *fe, u8 RegNum, u8 *RegVal) { struct mxl5005s_state *state = fe->tuner_priv; @@ -4125,7 +3927,6 @@ u16 MXL_RegRead(struct dvb_frontend *fe, u8 RegNum, u8 *RegVal) // -1 : Invalid control name // // // /////////////////////////////////////////////////////////////////////////////// -// DONE u16 MXL_ControlRead(struct dvb_frontend *fe, u16 controlNum, u32 *value) { struct mxl5005s_state *state = fe->tuner_priv; @@ -4197,7 +3998,6 @@ u16 MXL_ControlRead(struct dvb_frontend *fe, u16 controlNum, u32 *value) // -1 : Invalid control name // // // /////////////////////////////////////////////////////////////////////////////// -// DONE u16 MXL_ControlRegRead(struct dvb_frontend *fe, u16 controlNum, u8 *RegNum, int * count) { struct mxl5005s_state *state = fe->tuner_priv; @@ -4303,7 +4103,6 @@ u16 MXL_ControlRegRead(struct dvb_frontend *fe, u16 controlNum, u8 *RegNum, int // NONE // // // /////////////////////////////////////////////////////////////////////////////// -// DONE void MXL_RegWriteBit(struct dvb_frontend *fe, u8 address, u8 bit, u8 bitVal) { struct mxl5005s_state *state = fe->tuner_priv; @@ -4351,7 +4150,6 @@ void MXL_RegWriteBit(struct dvb_frontend *fe, u8 address, u8 bit, u8 bitVal) // Computed value // // // /////////////////////////////////////////////////////////////////////////////// -// DONE u32 MXL_Ceiling(u32 value, u32 resolution) { return (value/resolution + (value % resolution > 0 ? 1 : 0)); @@ -4360,7 +4158,6 @@ u32 MXL_Ceiling(u32 value, u32 resolution) // // Retrieve the Initialzation Registers // -// DONE u16 MXL_GetInitRegister(struct dvb_frontend *fe, u8 * RegNum, u8 *RegVal, int *count) { u16 status = 0; @@ -4383,7 +4180,6 @@ u16 MXL_GetInitRegister(struct dvb_frontend *fe, u8 * RegNum, u8 *RegVal, int *c return status; } -// DONE u16 MXL_GetCHRegister(struct dvb_frontend *fe, u8 * RegNum, u8 *RegVal, int *count) { u16 status = 0; @@ -4411,7 +4207,6 @@ u16 MXL_GetCHRegister(struct dvb_frontend *fe, u8 * RegNum, u8 *RegVal, int *cou return status; } -// DONE u16 MXL_GetCHRegister_ZeroIF(struct dvb_frontend *fe, u8 * RegNum, u8 *RegVal, int *count) { u16 status = 0; @@ -4429,7 +4224,6 @@ u16 MXL_GetCHRegister_ZeroIF(struct dvb_frontend *fe, u8 * RegNum, u8 *RegVal, i return status; } -// DONE u16 MXL_GetCHRegister_LowIF(struct dvb_frontend *fe, u8 * RegNum, u8 *RegVal, int *count) { u16 status = 0; @@ -4447,7 +4241,6 @@ u16 MXL_GetCHRegister_LowIF(struct dvb_frontend *fe, u8 * RegNum, u8 *RegVal, in return status; } -// DONE u16 MXL_GetMasterControl(u8 *MasterReg, int state) { if (state == 1) /* Load_Start */ @@ -4592,7 +4385,6 @@ u16 MXL_VCORange_Test(struct dvb_frontend *fe, int VCO_Range) return status; } -// DONE u16 MXL_Hystersis_Test(struct dvb_frontend *fe, int Hystersis) { struct mxl5005s_state *state = fe->tuner_priv; @@ -4603,155 +4395,224 @@ u16 MXL_Hystersis_Test(struct dvb_frontend *fe, int Hystersis) return status; } - #endif +/* End: Reference driver code found in the Realtek driver that + * is copyright MaxLinear */ -/* Linux driver related functions */ +/* ---------------------------------------------------------------- + * Begin: Everything after here is new code to adapt the + * proprietary Realtek driver into a Linux API tuner. + * Copyright (C) 2008 Steven Toth + */ +static int mxl5005s_reset(struct dvb_frontend *fe) +{ + struct mxl5005s_state *state = fe->tuner_priv; + int ret = 0; + u8 buf[2] = { 0xff, 0x00 }; + struct i2c_msg msg = { .addr = state->config->i2c_address, .flags = 0, + .buf = buf, .len = 2 }; -int mxl5005s_init(struct dvb_frontend *fe) -{ - int MxlModMode; - int MxlIfMode; - unsigned long MxlBandwitdh; - unsigned long MxlIfFreqHz; - unsigned long MxlCrystalFreqHz; - int MxlAgcMode; - unsigned short MxlTop; - unsigned short MxlIfOutputLoad; - int MxlClockOut; - int MxlDivOut; - int MxlCapSel; - int MxlRssiOnOff; - unsigned char MxlStandard; - unsigned char MxlTfType; + dprintk(2, "%s()\n", __func__); - /* Set MxL5005S parameters. */ - MxlModMode = MXL_DIGITAL_MODE; - MxlIfMode = MXL_ZERO_IF; -// steve - //MxlBandwitdh = MXL5005S_BANDWIDTH_8MHZ; - //MxlIfFreqHz = IF_FREQ_4570000HZ; - MxlBandwitdh = MXL5005S_BANDWIDTH_6MHZ; // config - MxlIfFreqHz = IF_FREQ_5380000HZ; // config - MxlCrystalFreqHz = CRYSTAL_FREQ_16000000HZ; // config - MxlAgcMode = MXL_SINGLE_AGC; - MxlTop = MXL5005S_TOP_25P2; - MxlIfOutputLoad = MXL5005S_IF_OUTPUT_LOAD_200_OHM; - MxlClockOut = MXL_CLOCK_OUT_DISABLE; - MxlDivOut = MXL_DIV_OUT_4; - MxlCapSel = MXL_CAP_SEL_ENABLE; - MxlRssiOnOff = MXL_RSSI_ENABLE; // config - MxlTfType = MXL_TF_C_H; // config + if (fe->ops.i2c_gate_ctrl) + fe->ops.i2c_gate_ctrl(fe, 1); -#if 1 - MxlStandard = MXL_ATSC; // config -#else - // Set MxL5005S parameters according to standard mode - switch(StandardMode) - { - default: - case MXL5005S_STANDARD_DVBT: - MxlStandard = MXL_DVBT; - break; - case MXL5005S_STANDARD_ATSC: - MxlStandard = MXL_ATSC; - break; + if (i2c_transfer(state->i2c, &msg, 1) != 1) { + printk(KERN_WARNING "mxl5005s I2C reset failed\n"); + ret = -EREMOTEIO; } -#endif - // TODO: this is bad, it trashes other configs - // Set MxL5005S extra module. - //pExtra->AgcMasterByte = (MxlAgcMode == MXL_DUAL_AGC) ? 0x4 : 0x0; + if (fe->ops.i2c_gate_ctrl) + fe->ops.i2c_gate_ctrl(fe, 0); - MXL5005_TunerConfig( - fe, - (unsigned char)MxlModMode, - (unsigned char)MxlIfMode, - MxlBandwitdh, - MxlIfFreqHz, - MxlCrystalFreqHz, - (unsigned char)MxlAgcMode, - MxlTop, - MxlIfOutputLoad, - (unsigned char)MxlClockOut, - (unsigned char)MxlDivOut, - (unsigned char)MxlCapSel, - (unsigned char)MxlRssiOnOff, - MxlStandard, MxlTfType); - - return mxl5005s_init2(fe); + return ret; } -static int mxl5005s_set_params(struct dvb_frontend *fe, - struct dvb_frontend_parameters *params) +/* Write a single byte to a single reg, latch the value if required by + * following the transaction with the latch byte. + */ +static int mxl5005s_writereg(struct dvb_frontend *fe, u8 reg, u8 val, int latch) { - u32 freq; - u32 bw; + struct mxl5005s_state *state = fe->tuner_priv; + u8 buf[3] = { reg, val, MXL5005S_LATCH_BYTE }; + struct i2c_msg msg = { .addr = state->config->i2c_address, .flags = 0, + .buf = buf, .len = 3 }; - if (fe->ops.info.type == FE_OFDM) - bw = params->u.ofdm.bandwidth; - else - bw = MXL5005S_BANDWIDTH_6MHZ; + if (latch == 0) + msg.len = 2; - freq = params->frequency; /* Hz */ - dprintk(1, "%s() freq=%d bw=%d\n", __func__, freq, bw); + dprintk(2, "%s(reg = 0x%x val = 0x%x addr = 0x%x)\n", __func__, reg, val, msg.addr); - return mxl5005s_SetRfFreqHz(fe, freq); + if (i2c_transfer(state->i2c, &msg, 1) != 1) { + printk(KERN_WARNING "mxl5005s I2C write failed\n"); + return -EREMOTEIO; + } + return 0; } -static int mxl5005s_get_frequency(struct dvb_frontend *fe, u32 *frequency) +int mxl5005s_writeregs(struct dvb_frontend *fe, u8 *addrtable, u8 *datatable, u8 len) { - struct mxl5005s_state *state = fe->tuner_priv; - dprintk(1, "%s()\n", __func__); + int ret = 0, i; - *frequency = state->RF_IN; + if (fe->ops.i2c_gate_ctrl) + fe->ops.i2c_gate_ctrl(fe, 1); - return 0; -} + for (i = 0 ; i < len-1; i++) { + ret = mxl5005s_writereg(fe, addrtable[i], datatable[i], 0); + if (ret < 0) + break; + } -static int mxl5005s_get_bandwidth(struct dvb_frontend *fe, u32 *bandwidth) -{ - struct mxl5005s_state *state = fe->tuner_priv; - dprintk(1, "%s()\n", __func__); + ret = mxl5005s_writereg(fe, addrtable[i], datatable[i], 1); - *bandwidth = state->Chan_Bandwidth; + if (fe->ops.i2c_gate_ctrl) + fe->ops.i2c_gate_ctrl(fe, 0); - return 0; + return ret; } -static int mxl5005s_get_status(struct dvb_frontend *fe, u32 *status) + +int mxl5005s_init(struct dvb_frontend *fe) { dprintk(1, "%s()\n", __func__); - - *status = 0; - // *status = TUNER_STATUS_LOCKED; - - return 0; + return mxl5005s_reconfigure(fe, MXL_QAM, MXL5005S_BANDWIDTH_6MHZ); } -static int mxl5005s_init2(struct dvb_frontend *fe) +int mxl5005s_reconfigure(struct dvb_frontend *fe, u32 mod_type, u32 bandwidth) { struct mxl5005s_state *state = fe->tuner_priv; + u8 AddrTable[MXL5005S_REG_WRITING_TABLE_LEN_MAX]; u8 ByteTable[MXL5005S_REG_WRITING_TABLE_LEN_MAX]; int TableLen; - dprintk(1, "%s()\n", __func__); + dprintk(1, "%s(type=%d, bw=%d)\n", __func__, mod_type, bandwidth); - /* Initialize MxL5005S tuner according to MxL5005S tuner example code. */ + mxl5005s_reset(fe); /* Tuner initialization stage 0 */ MXL_GetMasterControl(ByteTable, MC_SYNTH_RESET); AddrTable[0] = MASTER_CONTROL_ADDR; ByteTable[0] |= state->config->AgcMasterByte; - mxl5005s_SetRegsWithTable(fe, AddrTable, ByteTable, 1); + mxl5005s_writeregs(fe, AddrTable, ByteTable, 1); + + mxl5005s_AssignTunerMode(fe, mod_type, bandwidth); /* Tuner initialization stage 1 */ MXL_GetInitRegister(fe, AddrTable, ByteTable, &TableLen); - mxl5005s_SetRegsWithTable(fe, AddrTable, ByteTable, TableLen); + mxl5005s_writeregs(fe, AddrTable, ByteTable, TableLen); + + return 0; +} + +int mxl5005s_AssignTunerMode(struct dvb_frontend *fe, u32 mod_type, u32 bandwidth) +{ + struct mxl5005s_state *state = fe->tuner_priv; + struct mxl5005s_config *c = state->config; + + InitTunerControls(fe); + + /* Set MxL5005S parameters. */ + MXL5005_TunerConfig( + fe, + c->mod_mode, + c->if_mode, + bandwidth, + c->if_freq, + c->xtal_freq, + c->agc_mode, + c->top, + c->output_load, + c->clock_out, + c->div_out, + c->cap_select, + c->rssi_enable, + mod_type, + c->tracking_filter); + + return 0; +} + +static int mxl5005s_set_params(struct dvb_frontend *fe, + struct dvb_frontend_parameters *params) +{ + struct mxl5005s_state *state = fe->tuner_priv; + u32 req_mode, req_bw = 0; + int ret; + + dprintk(1, "%s()\n", __func__); + + if (fe->ops.info.type == FE_ATSC) { + switch (params->u.vsb.modulation) { + case VSB_8: + req_mode = MXL_ATSC; break; + default: + case QAM_64: + case QAM_256: + case QAM_AUTO: + req_mode = MXL_QAM; break; + } + } + else req_mode = MXL_DVBT; + + /* Change tuner for new modulation type if reqd */ + if (req_mode != state->current_mode) { + switch (req_mode) { + case VSB_8: + case QAM_64: + case QAM_256: + case QAM_AUTO: + req_bw = MXL5005S_BANDWIDTH_6MHZ; + break; + default: + /* Assume DVB-T */ + switch (params->u.ofdm.bandwidth) { + case BANDWIDTH_6_MHZ: + req_bw = MXL5005S_BANDWIDTH_6MHZ; + break; + case BANDWIDTH_7_MHZ: + req_bw = MXL5005S_BANDWIDTH_7MHZ; + break; + case BANDWIDTH_AUTO: + case BANDWIDTH_8_MHZ: + req_bw = MXL5005S_BANDWIDTH_8MHZ; + break; + } + } + + state->current_mode = req_mode; + ret = mxl5005s_reconfigure(fe, req_mode, req_bw); + + } else + ret = 0; + + if (ret == 0) { + dprintk(1, "%s() freq=%d\n", __func__, params->frequency); + ret = mxl5005s_SetRfFreqHz(fe, params->frequency); + } + + return ret; +} + +static int mxl5005s_get_frequency(struct dvb_frontend *fe, u32 *frequency) +{ + struct mxl5005s_state *state = fe->tuner_priv; + dprintk(1, "%s()\n", __func__); + + *frequency = state->RF_IN; + + return 0; +} + +static int mxl5005s_get_bandwidth(struct dvb_frontend *fe, u32 *bandwidth) +{ + struct mxl5005s_state *state = fe->tuner_priv; + dprintk(1, "%s()\n", __func__); + + *bandwidth = state->Chan_Bandwidth; return 0; } @@ -4778,7 +4639,6 @@ static const struct dvb_tuner_ops mxl5005s_tuner_ops = { .set_params = mxl5005s_set_params, .get_frequency = mxl5005s_get_frequency, .get_bandwidth = mxl5005s_get_bandwidth, - .get_status = mxl5005s_get_status }; struct dvb_frontend *mxl5005s_attach(struct dvb_frontend *fe, @@ -4795,6 +4655,7 @@ struct dvb_frontend *mxl5005s_attach(struct dvb_frontend *fe, state->frontend = fe; state->config = config; state->i2c = i2c; + state->current_mode = MXL_QAM; printk(KERN_INFO "MXL5005S: Attached at address 0x%02x\n", config->i2c_address); @@ -4806,9 +4667,6 @@ struct dvb_frontend *mxl5005s_attach(struct dvb_frontend *fe, EXPORT_SYMBOL(mxl5005s_attach); MODULE_DESCRIPTION("MaxLinear MXL5005S silicon tuner driver"); -MODULE_AUTHOR("Jan Hoogenraad"); -MODULE_AUTHOR("Barnaby Shearer"); -MODULE_AUTHOR("Andy Hasper"); MODULE_AUTHOR("Steven Toth"); MODULE_LICENSE("GPL"); diff --git a/linux/drivers/media/common/tuners/mxl5005s.h b/linux/drivers/media/common/tuners/mxl5005s.h index 7d0727d44..687cf146c 100644 --- a/linux/drivers/media/common/tuners/mxl5005s.h +++ b/linux/drivers/media/common/tuners/mxl5005s.h @@ -1,63 +1,118 @@ /* - * For the Realtek RTL chip RTL2831U - * Realtek Release Date: 2008-03-14, ver 080314 - * Realtek version RTL2831 Linux driver version 080314 - * ver 080314 - * - * for linux kernel version 2.6.21.4 - 2.6.22-14 - * support MXL5005s and MT2060 tuners (support tuner auto-detecting) - * support two IR types -- RC5 and NEC - * - * Known boards with Realtek RTL chip RTL2821U - * Freecom USB stick 14aa:0160 (version 4) - * Conceptronic CTVDIGRCU - * - * Copyright (c) 2008 Realtek - * Copyright (c) 2008 Jan Hoogenraad, Barnaby Shearer, Andy Hasper - * This code is placed under the terms of the GNU General Public License - * - * Released by Realtek under GPLv2. - * Thanks to Realtek for a lot of support we received ! - * - * Revision: 080314 - original version - */ + MaxLinear MXL5005S VSB/QAM/DVBT tuner driver + Copyright (C) 2008 MaxLinear + Copyright (C) 2008 Steven Toth + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + +*/ #ifndef __MXL5005S_H #define __MXL5005S_H #include -/* IF frequency */ -enum IF_FREQ_HZ -{ - IF_FREQ_4570000HZ = 4570000, ///< IF frequency = 4.57 MHz - IF_FREQ_4571429HZ = 4571429, ///< IF frequency = 4.571 MHz - IF_FREQ_5380000HZ = 5380000, ///< IF frequency = 5.38 MHz - IF_FREQ_36000000HZ = 36000000, ///< IF frequency = 36.000 MHz - IF_FREQ_36125000HZ = 36125000, ///< IF frequency = 36.125 MHz - IF_FREQ_36166667HZ = 36166667, ///< IF frequency = 36.167 MHz - IF_FREQ_44000000HZ = 44000000, ///< IF frequency = 44.000 MHz -}; - -/* Crystal frequency */ -enum CRYSTAL_FREQ_HZ -{ - CRYSTAL_FREQ_4000000HZ = 4000000, ///< Crystal frequency = 4.0 MHz - CRYSTAL_FREQ_16000000HZ = 16000000, ///< Crystal frequency = 16.0 MHz - CRYSTAL_FREQ_25000000HZ = 25000000, ///< Crystal frequency = 25.0 MHz - CRYSTAL_FREQ_28800000HZ = 28800000, ///< Crystal frequency = 28.8 MHz -}; - struct mxl5005s_config { + /* 7 bit i2c address */ u8 i2c_address; +#define IF_FREQ_4570000HZ 4570000 +#define IF_FREQ_4571429HZ 4571429 +#define IF_FREQ_5380000HZ 5380000 +#define IF_FREQ_36000000HZ 36000000 +#define IF_FREQ_36125000HZ 36125000 +#define IF_FREQ_36166667HZ 36166667 +#define IF_FREQ_44000000HZ 44000000 + u32 if_freq; + +#define CRYSTAL_FREQ_4000000HZ 4000000 +#define CRYSTAL_FREQ_16000000HZ 16000000 +#define CRYSTAL_FREQ_25000000HZ 25000000 +#define CRYSTAL_FREQ_28800000HZ 28800000 + u32 xtal_freq; + +#define MXL_DUAL_AGC 0 +#define MXL_SINGLE_AGC 1 + u8 agc_mode; + +#define MXL_TF_DEFAULT 0 +#define MXL_TF_OFF 1 +#define MXL_TF_C 2 +#define MXL_TF_C_H 3 +#define MXL_TF_D 4 +#define MXL_TF_D_L 5 +#define MXL_TF_E 6 +#define MXL_TF_F 7 +#define MXL_TF_E_2 8 +#define MXL_TF_E_NA 9 +#define MXL_TF_G 10 + u8 tracking_filter; + +#define MXL_RSSI_DISABLE 0 +#define MXL_RSSI_ENABLE 1 + u8 rssi_enable; + +#define MXL_CAP_SEL_DISABLE 0 +#define MXL_CAP_SEL_ENABLE 1 + u8 cap_select; + +#define MXL_DIV_OUT_1 0 +#define MXL_DIV_OUT_4 1 + u8 div_out; + +#define MXL_CLOCK_OUT_DISABLE 0 +#define MXL_CLOCK_OUT_ENABLE 1 + u8 clock_out; + +#define MXL5005S_IF_OUTPUT_LOAD_200_OHM 200 +#define MXL5005S_IF_OUTPUT_LOAD_300_OHM 300 + u32 output_load; + +#define MXL5005S_TOP_5P5 55 +#define MXL5005S_TOP_7P2 72 +#define MXL5005S_TOP_9P2 92 +#define MXL5005S_TOP_11P0 110 +#define MXL5005S_TOP_12P9 129 +#define MXL5005S_TOP_14P7 147 +#define MXL5005S_TOP_16P8 168 +#define MXL5005S_TOP_19P4 194 +#define MXL5005S_TOP_21P2 212 +#define MXL5005S_TOP_23P2 232 +#define MXL5005S_TOP_25P2 252 +#define MXL5005S_TOP_27P1 271 +#define MXL5005S_TOP_29P2 292 +#define MXL5005S_TOP_31P7 317 +#define MXL5005S_TOP_34P9 349 + u32 top; + +#define MXL_ANALOG_MODE 0 +#define MXL_DIGITAL_MODE 1 + u8 mod_mode; + +#define MXL_ZERO_IF 0 +#define MXL_LOW_IF 1 + u8 if_mode; + /* Stuff I don't know what to do with */ u8 AgcMasterByte; }; -#if defined(CONFIG_MEDIA_TUNER_MXL5005S) || (defined(CONFIG_MEDIA_TUNER_MXL5005S_MODULE) && defined(MODULE)) +#if defined(CONFIG_MEDIA_TUNER_MXL5005S) || \ + (defined(CONFIG_MEDIA_TUNER_MXL5005S_MODULE) && defined(MODULE)) extern struct dvb_frontend *mxl5005s_attach(struct dvb_frontend *fe, struct i2c_adapter *i2c, struct mxl5005s_config *config); -- cgit v1.2.3 From 92db331b87dc3cfc653c8f4fafbd8a2382b1c75e Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Thu, 1 May 2008 15:35:54 -0400 Subject: mxl5005s: checkpatch.pl compliance From: Steven Toth 4 exceptions where the code would read very ugly otherwise. Signed-off-by: Steven Toth Signed-off-by: Mauro Carvalho Chehab --- linux/drivers/media/common/tuners/mxl5005s.c | 2496 +++++++++++--------------- linux/drivers/media/common/tuners/mxl5005s.h | 4 +- 2 files changed, 1029 insertions(+), 1471 deletions(-) (limited to 'linux/drivers/media/common/tuners') diff --git a/linux/drivers/media/common/tuners/mxl5005s.c b/linux/drivers/media/common/tuners/mxl5005s.c index 0e0a5b3fa..18a976c7e 100644 --- a/linux/drivers/media/common/tuners/mxl5005s.c +++ b/linux/drivers/media/common/tuners/mxl5005s.c @@ -86,34 +86,30 @@ static int debug = 2; #define MASTER_CONTROL_ADDR 9 /* Enumeration of Master Control Register State */ -typedef enum -{ +enum master_control_state { MC_LOAD_START = 1, MC_POWER_DOWN, MC_SYNTH_RESET, MC_SEQ_OFF -} Master_Control_State; +}; /* Enumeration of MXL5005 Tuner Modulation Type */ -typedef enum -{ +enum { MXL_DEFAULT_MODULATION = 0, MXL_DVBT, MXL_ATSC, MXL_QAM, MXL_ANALOG_CABLE, MXL_ANALOG_OTA -} Tuner_Modu_Type; +} tuner_modu_type; /* MXL5005 Tuner Register Struct */ -typedef struct _TunerReg_struct -{ +struct TunerReg { u16 Reg_Num; /* Tuner Register Address */ - u16 Reg_Val; /* Current sofware programmed value waiting to be writen */ -} TunerReg_struct; + u16 Reg_Val; /* Current sw programmed value waiting to be writen */ +}; -typedef enum -{ +enum { /* Initialization Control Names */ DN_IQTN_AMP_CUT = 1, /* 1 */ BB_MODE, /* 2 */ @@ -219,16 +215,14 @@ typedef enum #define MXL5005S_BB_DLPF_BANDSEL_LSB 3 /* Standard modes */ -enum -{ +enum { MXL5005S_STANDARD_DVBT, MXL5005S_STANDARD_ATSC, }; #define MXL5005S_STANDARD_MODE_NUM 2 /* Bandwidth modes */ -enum -{ +enum { MXL5005S_BANDWIDTH_6MHZ = 6000000, MXL5005S_BANDWIDTH_7MHZ = 7000000, MXL5005S_BANDWIDTH_8MHZ = 8000000, @@ -236,17 +230,16 @@ enum #define MXL5005S_BANDWIDTH_MODE_NUM 3 /* MXL5005 Tuner Control Struct */ -typedef struct _TunerControl_struct { +struct TunerControl { u16 Ctrl_Num; /* Control Number */ u16 size; /* Number of bits to represent Value */ - u16 addr[25]; /* Array of Tuner Register Address for each bit position */ - u16 bit[25]; /* Array of bit position in Register Address for each bit position */ + u16 addr[25]; /* Array of Tuner Register Address for each bit pos */ + u16 bit[25]; /* Array of bit pos in Reg Addr for each bit pos */ u16 val[25]; /* Binary representation of Value */ -} TunerControl_struct; +}; /* MXL5005 Tuner Struct */ -struct mxl5005s_state -{ +struct mxl5005s_state { u8 Mode; /* 0: Analog Mode ; 1: Digital Mode */ u8 IF_Mode; /* for Analog Mode, 0: zero IF; 1: low IF */ u32 Chan_Bandwidth; /* filter channel bandwidth (6, 7, 8) */ @@ -256,14 +249,18 @@ struct mxl5005s_state u32 Fxtal; /* XTAL Frequency */ u8 AGC_Mode; /* AGC Mode 0: Dual AGC; 1: Single AGC */ u16 TOP; /* Value: take over point */ - u8 CLOCK_OUT; /* 0: turn off clock out; 1: turn on clock out */ + u8 CLOCK_OUT; /* 0: turn off clk out; 1: turn on clock out */ u8 DIV_OUT; /* 4MHz or 16MHz */ u8 CAPSELECT; /* 0: disable On-Chip pulling cap; 1: enable */ u8 EN_RSSI; /* 0: disable RSSI; 1: enable RSSI */ - u8 Mod_Type; /* Modulation Type; */ - /* 0 - Default; 1 - DVB-T; 2 - ATSC; 3 - QAM; 4 - Analog Cable */ - u8 TF_Type; /* Tracking Filter Type */ - /* 0 - Default; 1 - Off; 2 - Type C; 3 - Type C-H */ + + /* Modulation Type; */ + /* 0 - Default; 1 - DVB-T; 2 - ATSC; 3 - QAM; 4 - Analog Cable */ + u8 Mod_Type; + + /* Tracking Filter Type */ + /* 0 - Default; 1 - Off; 2 - Type C; 3 - Type C-H */ + u8 TF_Type; /* Calculated Settings */ u32 RF_LO; /* Synth RF LO Frequency */ @@ -271,22 +268,22 @@ struct mxl5005s_state u32 TG_LO; /* Synth TG_LO Frequency */ /* Pointers to ControlName Arrays */ - u16 Init_Ctrl_Num; /* Number of INIT Control Names */ - TunerControl_struct - Init_Ctrl[INITCTRL_NUM]; /* INIT Control Names Array Pointer */ + u16 Init_Ctrl_Num; /* Number of INIT Control Names */ + struct TunerControl + Init_Ctrl[INITCTRL_NUM]; /* INIT Control Names Array Pointer */ - u16 CH_Ctrl_Num; /* Number of CH Control Names */ - TunerControl_struct - CH_Ctrl[CHCTRL_NUM]; /* CH Control Name Array Pointer */ + u16 CH_Ctrl_Num; /* Number of CH Control Names */ + struct TunerControl + CH_Ctrl[CHCTRL_NUM]; /* CH Control Name Array Pointer */ - u16 MXL_Ctrl_Num; /* Number of MXL Control Names */ - TunerControl_struct - MXL_Ctrl[MXLCTRL_NUM]; /* MXL Control Name Array Pointer */ + u16 MXL_Ctrl_Num; /* Number of MXL Control Names */ + struct TunerControl + MXL_Ctrl[MXLCTRL_NUM]; /* MXL Control Name Array Pointer */ /* Pointer to Tuner Register Array */ - u16 TunerRegs_Num; /* Number of Tuner Registers */ - TunerReg_struct - TunerRegs[TUNER_REGS_NUM]; /* Tuner Register Array Pointer */ + u16 TunerRegs_Num; /* Number of Tuner Registers */ + struct TunerReg + TunerRegs[TUNER_REGS_NUM]; /* Tuner Register Array Pointer */ /* Linux driver framework specific */ struct mxl5005s_config *config; @@ -302,21 +299,27 @@ u16 MXL_ControlWrite(struct dvb_frontend *fe, u16 ControlNum, u32 value); u16 MXL_ControlRead(struct dvb_frontend *fe, u16 controlNum, u32 *value); u16 MXL_GetMasterControl(u8 *MasterReg, int state); void MXL_RegWriteBit(struct dvb_frontend *fe, u8 address, u8 bit, u8 bitVal); -u16 MXL_GetCHRegister(struct dvb_frontend *fe, u8 *RegNum, u8 *RegVal, int *count); +u16 MXL_GetCHRegister(struct dvb_frontend *fe, u8 *RegNum, + u8 *RegVal, int *count); u32 MXL_Ceiling(u32 value, u32 resolution); u16 MXL_RegRead(struct dvb_frontend *fe, u8 RegNum, u8 *RegVal); u16 MXL_RegWrite(struct dvb_frontend *fe, u8 RegNum, u8 RegVal); -u16 MXL_ControlWrite_Group(struct dvb_frontend *fe, u16 controlNum, u32 value, u16 controlGroup); +u16 MXL_ControlWrite_Group(struct dvb_frontend *fe, u16 controlNum, + u32 value, u16 controlGroup); u16 MXL_SetGPIO(struct dvb_frontend *fe, u8 GPIO_Num, u8 GPIO_Val); -u16 MXL_GetInitRegister(struct dvb_frontend *fe, u8 * RegNum, u8 *RegVal, int *count); +u16 MXL_GetInitRegister(struct dvb_frontend *fe, u8 *RegNum, + u8 *RegVal, int *count); u32 MXL_GetXtalInt(u32 Xtal_Freq); u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq); void MXL_SynthIFLO_Calc(struct dvb_frontend *fe); void MXL_SynthRFTGLO_Calc(struct dvb_frontend *fe); -u16 MXL_GetCHRegister_ZeroIF(struct dvb_frontend *fe, u8 *RegNum, u8 *RegVal, int *count); -int mxl5005s_writeregs(struct dvb_frontend *fe, u8 *addrtable, u8 *datatable, u8 len); +u16 MXL_GetCHRegister_ZeroIF(struct dvb_frontend *fe, u8 *RegNum, + u8 *RegVal, int *count); +int mxl5005s_writeregs(struct dvb_frontend *fe, u8 *addrtable, + u8 *datatable, u8 len); u16 MXL_IFSynthInit(struct dvb_frontend *fe); -int mxl5005s_AssignTunerMode(struct dvb_frontend *fe, u32 mod_type, u32 bandwidth); +int mxl5005s_AssignTunerMode(struct dvb_frontend *fe, u32 mod_type, + u32 bandwidth); int mxl5005s_reconfigure(struct dvb_frontend *fe, u32 mod_type, u32 bandwidth); /* ---------------------------------------------------------------- @@ -343,16 +346,16 @@ int mxl5005s_SetRfFreqHz(struct dvb_frontend *fe, unsigned long RfFreqHz) dprintk(1, "%s() freq=%ld\n", __func__, RfFreqHz); - // Set MxL5005S tuner RF frequency according to MxL5005S tuner example code. + /* Set MxL5005S tuner RF frequency according to example code. */ - // Tuner RF frequency setting stage 0 - MXL_GetMasterControl(ByteTable, MC_SYNTH_RESET) ; + /* Tuner RF frequency setting stage 0 */ + MXL_GetMasterControl(ByteTable, MC_SYNTH_RESET); AddrTable[0] = MASTER_CONTROL_ADDR; ByteTable[0] |= state->config->AgcMasterByte; mxl5005s_writeregs(fe, AddrTable, ByteTable, 1); - // Tuner RF frequency setting stage 1 + /* Tuner RF frequency setting stage 1 */ MXL_TuneRF(fe, RfFreqHz); MXL_ControlRead(fe, IF_DIVVAL, &IfDivval); @@ -360,26 +363,28 @@ int mxl5005s_SetRfFreqHz(struct dvb_frontend *fe, unsigned long RfFreqHz) MXL_ControlWrite(fe, SEQ_FSM_PULSE, 0); MXL_ControlWrite(fe, SEQ_EXTPOWERUP, 1); MXL_ControlWrite(fe, IF_DIVVAL, 8); - MXL_GetCHRegister(fe, AddrTable, ByteTable, &TableLen) ; + MXL_GetCHRegister(fe, AddrTable, ByteTable, &TableLen); - MXL_GetMasterControl(&MasterControlByte, MC_LOAD_START) ; + MXL_GetMasterControl(&MasterControlByte, MC_LOAD_START); AddrTable[TableLen] = MASTER_CONTROL_ADDR ; - ByteTable[TableLen] = MasterControlByte | state->config->AgcMasterByte; + ByteTable[TableLen] = MasterControlByte | + state->config->AgcMasterByte; TableLen += 1; mxl5005s_writeregs(fe, AddrTable, ByteTable, TableLen); - // Wait 30 ms. + /* Wait 30 ms. */ msleep(150); - // Tuner RF frequency setting stage 2 - MXL_ControlWrite(fe, SEQ_FSM_PULSE, 1) ; - MXL_ControlWrite(fe, IF_DIVVAL, IfDivval) ; - MXL_GetCHRegister_ZeroIF(fe, AddrTable, ByteTable, &TableLen) ; + /* Tuner RF frequency setting stage 2 */ + MXL_ControlWrite(fe, SEQ_FSM_PULSE, 1); + MXL_ControlWrite(fe, IF_DIVVAL, IfDivval); + MXL_GetCHRegister_ZeroIF(fe, AddrTable, ByteTable, &TableLen); - MXL_GetMasterControl(&MasterControlByte, MC_LOAD_START) ; + MXL_GetMasterControl(&MasterControlByte, MC_LOAD_START); AddrTable[TableLen] = MASTER_CONTROL_ADDR ; - ByteTable[TableLen] = MasterControlByte | state->config->AgcMasterByte ; + ByteTable[TableLen] = MasterControlByte | + state->config->AgcMasterByte ; TableLen += 1; mxl5005s_writeregs(fe, AddrTable, ByteTable, TableLen); @@ -398,7 +403,6 @@ u16 MXL5005_RegisterInit(struct dvb_frontend *fe) { struct mxl5005s_state *state = fe->tuner_priv; state->TunerRegs_Num = TUNER_REGS_NUM ; -// state->TunerRegs = (TunerReg_struct *) calloc( TUNER_REGS_NUM, sizeof(TunerReg_struct) ) ; state->TunerRegs[0].Reg_Num = 9 ; state->TunerRegs[0].Reg_Val = 0x40 ; @@ -1655,9 +1659,6 @@ u16 MXL5005_ControlInit(struct dvb_frontend *fe) return 0 ; } -// MaxLinear source code - MXL5005_c.cpp -// MXL5005.cpp : Defines the initialization routines for the DLL. -// 2.6.12 void InitTunerControls(struct dvb_frontend *fe) { MXL5005_RegisterInit(fe); @@ -1667,57 +1668,28 @@ void InitTunerControls(struct dvb_frontend *fe) #endif } -/////////////////////////////////////////////////////////////////////////////// -// // -// Function: MXL_ConfigTuner // -// // -// Description: Configure MXL5005Tuner structure for desired // -// Channel Bandwidth/Channel Frequency // -// // -// // -// Functions used: // -// MXL_SynthIFLO_Calc // -// // -// Inputs: // -// Tuner_struct: structure defined at higher level // -// Mode: Tuner Mode (Analog/Digital) // -// IF_Mode: IF Mode ( Zero/Low ) // -// Bandwidth: Filter Channel Bandwidth (in Hz) // -// IF_out: Desired IF out Frequency (in Hz) // -// Fxtal: Crystal Frerquency (in Hz) // -// TOP: 0: Dual AGC; Value: take over point // -// IF_OUT_LOAD: IF out load resistor (200/300 Ohms) // -// CLOCK_OUT: 0: Turn off clock out; 1: turn on clock out // -// DIV_OUT: 0: Div-1; 1: Div-4 // -// CAPSELECT: 0: Disable On-chip pulling cap; 1: Enable // -// EN_RSSI: 0: Disable RSSI; 1: Enable RSSI // -// // -// Outputs: // -// Tuner // -// // -// Return: // -// 0 : Successful // -// > 0 : Failed // -// // -/////////////////////////////////////////////////////////////////////////////// u16 MXL5005_TunerConfig(struct dvb_frontend *fe, - u8 Mode, /* 0: Analog Mode ; 1: Digital Mode */ - u8 IF_mode, /* for Analog Mode, 0: zero IF; 1: low IF */ - u32 Bandwidth, /* filter channel bandwidth (6, 7, 8) */ - u32 IF_out, /* Desired IF Out Frequency */ - u32 Fxtal, /* XTAL Frequency */ - u8 AGC_Mode, /* AGC Mode - Dual AGC: 0, Single AGC: 1 */ - u16 TOP, /* 0: Dual AGC; Value: take over point */ - u16 IF_OUT_LOAD, /* IF Out Load Resistor (200 / 300 Ohms) */ - u8 CLOCK_OUT, /* 0: turn off clock out; 1: turn on clock out */ - u8 DIV_OUT, /* 0: Div-1; 1: Div-4 */ - u8 CAPSELECT, /* 0: disable On-Chip pulling cap; 1: enable */ - u8 EN_RSSI, /* 0: disable RSSI; 1: enable RSSI */ - u8 Mod_Type, /* Modulation Type; */ - /* 0 - Default; 1 - DVB-T; 2 - ATSC; 3 - QAM; 4 - Analog Cable */ - u8 TF_Type /* Tracking Filter */ - /* 0 - Default; 1 - Off; 2 - Type C; 3 - Type C-H */ - ) + u8 Mode, /* 0: Analog Mode ; 1: Digital Mode */ + u8 IF_mode, /* for Analog Mode, 0: zero IF; 1: low IF */ + u32 Bandwidth, /* filter channel bandwidth (6, 7, 8) */ + u32 IF_out, /* Desired IF Out Frequency */ + u32 Fxtal, /* XTAL Frequency */ + u8 AGC_Mode, /* AGC Mode - Dual AGC: 0, Single AGC: 1 */ + u16 TOP, /* 0: Dual AGC; Value: take over point */ + u16 IF_OUT_LOAD, /* IF Out Load Resistor (200 / 300 Ohms) */ + u8 CLOCK_OUT, /* 0: turn off clk out; 1: turn on clock out */ + u8 DIV_OUT, /* 0: Div-1; 1: Div-4 */ + u8 CAPSELECT, /* 0: disable On-Chip pulling cap; 1: enable */ + u8 EN_RSSI, /* 0: disable RSSI; 1: enable RSSI */ + + /* Modulation Type; */ + /* 0 - Default; 1 - DVB-T; 2 - ATSC; 3 - QAM; 4 - Analog Cable */ + u8 Mod_Type, + + /* Tracking Filter */ + /* 0 - Default; 1 - Off; 2 - Type C; 3 - Type C-H */ + u8 TF_Type + ) { struct mxl5005s_state *state = fe->tuner_priv; u16 status = 0; @@ -1746,105 +1718,40 @@ u16 MXL5005_TunerConfig(struct dvb_frontend *fe, return status; } -/////////////////////////////////////////////////////////////////////////////// -// // -// Function: MXL_SynthIFLO_Calc // -// // -// Description: Calculate Internal IF-LO Frequency // -// // -// Globals: // -// NONE // -// // -// Functions used: // -// NONE // -// // -// Inputs: // -// Tuner_struct: structure defined at higher level // -// // -// Outputs: // -// Tuner // -// // -// Return: // -// 0 : Successful // -// > 0 : Failed // -// // -/////////////////////////////////////////////////////////////////////////////// void MXL_SynthIFLO_Calc(struct dvb_frontend *fe) { struct mxl5005s_state *state = fe->tuner_priv; if (state->Mode == 1) /* Digital Mode */ state->IF_LO = state->IF_OUT; - else /* Analog Mode */ - { - if(state->IF_Mode == 0) /* Analog Zero IF mode */ + else /* Analog Mode */ { + if (state->IF_Mode == 0) /* Analog Zero IF mode */ state->IF_LO = state->IF_OUT + 400000; else /* Analog Low IF mode */ state->IF_LO = state->IF_OUT + state->Chan_Bandwidth/2; } } -/////////////////////////////////////////////////////////////////////////////// -// // -// Function: MXL_SynthRFTGLO_Calc // -// // -// Description: Calculate Internal RF-LO frequency and // -// internal Tone-Gen(TG)-LO frequency // -// // -// Globals: // -// NONE // -// // -// Functions used: // -// NONE // -// // -// Inputs: // -// Tuner_struct: structure defined at higher level // -// // -// Outputs: // -// Tuner // -// // -// Return: // -// 0 : Successful // -// > 0 : Failed // -// // -/////////////////////////////////////////////////////////////////////////////// void MXL_SynthRFTGLO_Calc(struct dvb_frontend *fe) { struct mxl5005s_state *state = fe->tuner_priv; if (state->Mode == 1) /* Digital Mode */ { - //remove 20.48MHz setting for 2.6.10 + /* remove 20.48MHz setting for 2.6.10 */ state->RF_LO = state->RF_IN; - state->TG_LO = state->RF_IN - 750000; //change for 2.6.6 + /* change for 2.6.6 */ + state->TG_LO = state->RF_IN - 750000; } else /* Analog Mode */ { - if(state->IF_Mode == 0) /* Analog Zero IF mode */ { + if (state->IF_Mode == 0) /* Analog Zero IF mode */ { state->RF_LO = state->RF_IN - 400000; state->TG_LO = state->RF_IN - 1750000; } else /* Analog Low IF mode */ { state->RF_LO = state->RF_IN - state->Chan_Bandwidth/2; - state->TG_LO = state->RF_IN - state->Chan_Bandwidth + 500000; + state->TG_LO = state->RF_IN - + state->Chan_Bandwidth + 500000; } } } -/////////////////////////////////////////////////////////////////////////////// -// // -// Function: MXL_OverwriteICDefault // -// // -// Description: Overwrite the Default Register Setting // -// // -// // -// Functions used: // -// // -// Inputs: // -// Tuner_struct: structure defined at higher level // -// Outputs: // -// Tuner // -// // -// Return: // -// 0 : Successful // -// > 0 : Failed // -// // -/////////////////////////////////////////////////////////////////////////////// u16 MXL_OverwriteICDefault(struct dvb_frontend *fe) { u16 status = 0; @@ -1857,31 +1764,6 @@ u16 MXL_OverwriteICDefault(struct dvb_frontend *fe) return status; } -/////////////////////////////////////////////////////////////////////////////// -// // -// Function: MXL_BlockInit // -// // -// Description: Tuner Initialization as a function of 'User Settings' // -// * User settings in Tuner strcuture must be assigned // -// first // -// // -// Globals: // -// NONE // -// // -// Functions used: // -// Tuner_struct: structure defined at higher level // -// // -// Inputs: // -// Tuner : Tuner structure defined at higher level // -// // -// Outputs: // -// Tuner // -// // -// Return: // -// 0 : Successful // -// > 0 : Failed // -// // -/////////////////////////////////////////////////////////////////////////////// u16 MXL_BlockInit(struct dvb_frontend *fe) { struct mxl5005s_state *state = fe->tuner_priv; @@ -1902,42 +1784,45 @@ u16 MXL_BlockInit(struct dvb_frontend *fe) /* Initialize Low-Pass Filter */ if (state->Mode) { /* Digital Mode */ switch (state->Chan_Bandwidth) { - case 8000000: - status += MXL_ControlWrite(fe, BB_DLPF_BANDSEL, 0); - break; - case 7000000: - status += MXL_ControlWrite(fe, BB_DLPF_BANDSEL, 2); - break; - case 6000000: - printk("%s() doing 6MHz digital\n", __func__); - status += MXL_ControlWrite(fe, BB_DLPF_BANDSEL, 3); - break; + case 8000000: + status += MXL_ControlWrite(fe, BB_DLPF_BANDSEL, 0); + break; + case 7000000: + status += MXL_ControlWrite(fe, BB_DLPF_BANDSEL, 2); + break; + case 6000000: + status += MXL_ControlWrite(fe, + BB_DLPF_BANDSEL, 3); + break; } } else { /* Analog Mode */ switch (state->Chan_Bandwidth) { - case 8000000: /* Low Zero */ - status += MXL_ControlWrite(fe, BB_ALPF_BANDSELECT, (state->IF_Mode ? 0 : 3)); - break; - case 7000000: - status += MXL_ControlWrite(fe, BB_ALPF_BANDSELECT, (state->IF_Mode ? 1 : 4)); - break; - case 6000000: - status += MXL_ControlWrite(fe, BB_ALPF_BANDSELECT, (state->IF_Mode ? 2 : 5)); - break; + case 8000000: /* Low Zero */ + status += MXL_ControlWrite(fe, BB_ALPF_BANDSELECT, + (state->IF_Mode ? 0 : 3)); + break; + case 7000000: + status += MXL_ControlWrite(fe, BB_ALPF_BANDSELECT, + (state->IF_Mode ? 1 : 4)); + break; + case 6000000: + status += MXL_ControlWrite(fe, BB_ALPF_BANDSELECT, + (state->IF_Mode ? 2 : 5)); + break; } } /* Charge Pump Control Dig Ana */ - status += MXL_ControlWrite(fe, RFSYN_CHP_GAIN, state->Mode ? 5 : 8); - status += MXL_ControlWrite(fe, RFSYN_EN_CHP_HIGAIN, state->Mode ? 1 : 1); + status += MXL_ControlWrite(fe, RFSYN_CHP_GAIN, state->Mode ? 5 : 8); + status += MXL_ControlWrite(fe, + RFSYN_EN_CHP_HIGAIN, state->Mode ? 1 : 1); status += MXL_ControlWrite(fe, EN_CHP_LIN_B, state->Mode ? 0 : 0); /* AGC TOP Control */ if (state->AGC_Mode == 0) /* Dual AGC */ { status += MXL_ControlWrite(fe, AGC_IF, 15); status += MXL_ControlWrite(fe, AGC_RF, 15); - } - else /* Single AGC Mode Dig Ana */ + } else /* Single AGC Mode Dig Ana */ status += MXL_ControlWrite(fe, AGC_RF, state->Mode ? 15 : 12); if (state->TOP == 55) /* TOP == 5.5 */ @@ -2008,7 +1893,8 @@ u16 MXL_BlockInit(struct dvb_frontend *fe) status += MXL_ControlWrite(fe, EN_AUX_3P, 1); status += MXL_ControlWrite(fe, SEL_AAF_BAND, 0); } - if ((state->IF_OUT == 36125000UL) || (state->IF_OUT == 36150000UL)) { + if ((state->IF_OUT == 36125000UL) || + (state->IF_OUT == 36150000UL)) { status += MXL_ControlWrite(fe, EN_AAF, 1); status += MXL_ControlWrite(fe, EN_3P, 1); status += MXL_ControlWrite(fe, EN_AUX_3P, 1); @@ -2021,15 +1907,13 @@ u16 MXL_BlockInit(struct dvb_frontend *fe) status += MXL_ControlWrite(fe, SEL_AAF_BAND, 1); } } else { /* Analog Mode */ - if (state->IF_OUT >= 4000000UL && state->IF_OUT <= 5000000UL) - { + if (state->IF_OUT >= 4000000UL && state->IF_OUT <= 5000000UL) { status += MXL_ControlWrite(fe, EN_AAF, 1); status += MXL_ControlWrite(fe, EN_3P, 1); status += MXL_ControlWrite(fe, EN_AUX_3P, 1); status += MXL_ControlWrite(fe, SEL_AAF_BAND, 0); } - if (state->IF_OUT > 5000000UL) - { + if (state->IF_OUT > 5000000UL) { status += MXL_ControlWrite(fe, EN_AAF, 0); status += MXL_ControlWrite(fe, EN_3P, 0); status += MXL_ControlWrite(fe, EN_AUX_3P, 0); @@ -2073,13 +1957,13 @@ u16 MXL_BlockInit(struct dvb_frontend *fe) /* status += MXL_ControlRead(fe, IF_DIVVAL, &IF_DIVVAL_Val); */ /* Set TG_R_DIV */ - status += MXL_ControlWrite(fe, TG_R_DIV, MXL_Ceiling(state->Fxtal, 1000000)); + status += MXL_ControlWrite(fe, TG_R_DIV, + MXL_Ceiling(state->Fxtal, 1000000)); /* Apply Default value to BB_INITSTATE_DLPF_TUNE */ /* RSSI Control */ - if (state->EN_RSSI) - { + if (state->EN_RSSI) { status += MXL_ControlWrite(fe, SEQ_EXTSYNTHCALIF, 1); status += MXL_ControlWrite(fe, SEQ_EXTDCCAL, 1); status += MXL_ControlWrite(fe, AGC_EN_RSSI, 1); @@ -2098,8 +1982,7 @@ u16 MXL_BlockInit(struct dvb_frontend *fe) /* Modulation type bit settings * Override the control values preset */ - if (state->Mod_Type == MXL_DVBT) /* DVB-T Mode */ - { + if (state->Mod_Type == MXL_DVBT) /* DVB-T Mode */ { state->AGC_Mode = 1; /* Single AGC Mode */ /* Enable RSSI */ @@ -2122,8 +2005,7 @@ u16 MXL_BlockInit(struct dvb_frontend *fe) status += MXL_ControlWrite(fe, BB_IQSWAP, 1); } - if (state->Mod_Type == MXL_ATSC) /* ATSC Mode */ - { + if (state->Mod_Type == MXL_ATSC) /* ATSC Mode */ { state->AGC_Mode = 1; /* Single AGC Mode */ /* Enable RSSI */ @@ -2141,14 +2023,15 @@ u16 MXL_BlockInit(struct dvb_frontend *fe) status += MXL_ControlWrite(fe, RFA_FLR, 2); status += MXL_ControlWrite(fe, RFA_CEIL, 13); status += MXL_ControlWrite(fe, BB_INITSTATE_DLPF_TUNE, 1); - status += MXL_ControlWrite(fe, RFSYN_CHP_GAIN, 5); /* Low Zero */ + /* Low Zero */ + status += MXL_ControlWrite(fe, RFSYN_CHP_GAIN, 5); + if (state->IF_OUT <= 6280000UL) /* Low IF */ status += MXL_ControlWrite(fe, BB_IQSWAP, 0); else /* High IF */ status += MXL_ControlWrite(fe, BB_IQSWAP, 1); } - if (state->Mod_Type == MXL_QAM) /* QAM Mode */ - { + if (state->Mod_Type == MXL_QAM) /* QAM Mode */ { state->Mode = MXL_DIGITAL_MODE; /* state->AGC_Mode = 1; */ /* Single AGC Mode */ @@ -2163,7 +2046,8 @@ u16 MXL_BlockInit(struct dvb_frontend *fe) status += MXL_ControlWrite(fe, RFA_RSSI_REFH, 5); status += MXL_ControlWrite(fe, RFA_RSSI_REF, 3); status += MXL_ControlWrite(fe, RFA_RSSI_REFL, 2); - status += MXL_ControlWrite(fe, RFSYN_CHP_GAIN, 3); /* change here for v2.6.5 */ + /* change here for v2.6.5 */ + status += MXL_ControlWrite(fe, RFSYN_CHP_GAIN, 3); if (state->IF_OUT <= 6280000UL) /* Low IF */ status += MXL_ControlWrite(fe, BB_IQSWAP, 0); @@ -2185,7 +2069,8 @@ u16 MXL_BlockInit(struct dvb_frontend *fe) status += MXL_ControlWrite(fe, SEQ_EXTDCCAL, 1); status += MXL_ControlWrite(fe, AGC_EN_RSSI, 0); status += MXL_ControlWrite(fe, RFA_ENCLKRFAGC, 1); - status += MXL_ControlWrite(fe, AGC_IF, 1); /* change for 2.6.3 */ + /* change for 2.6.3 */ + status += MXL_ControlWrite(fe, AGC_IF, 1); status += MXL_ControlWrite(fe, AGC_RF, 15); status += MXL_ControlWrite(fe, BB_IQSWAP, 1); } @@ -2209,7 +2094,7 @@ u16 MXL_BlockInit(struct dvb_frontend *fe) } /* RSSI disable */ - if(state->EN_RSSI == 0) { + if (state->EN_RSSI == 0) { status += MXL_ControlWrite(fe, SEQ_EXTSYNTHCALIF, 1); status += MXL_ControlWrite(fe, SEQ_EXTDCCAL, 1); status += MXL_ControlWrite(fe, AGC_EN_RSSI, 0); @@ -2219,34 +2104,10 @@ u16 MXL_BlockInit(struct dvb_frontend *fe) return status; } -/////////////////////////////////////////////////////////////////////////////// -// // -// Function: MXL_IFSynthInit // -// // -// Description: Tuner IF Synthesizer related register initialization // -// // -// Globals: // -// NONE // -// // -// Functions used: // -// Tuner_struct: structure defined at higher level // -// // -// Inputs: // -// Tuner : Tuner structure defined at higher level // -// // -// Outputs: // -// Tuner // -// // -// Return: // -// 0 : Successful // -// > 0 : Failed // -// // -/////////////////////////////////////////////////////////////////////////////// u16 MXL_IFSynthInit(struct dvb_frontend *fe) { struct mxl5005s_state *state = fe->tuner_priv; u16 status = 0 ; - // Declare Local Variables u32 Fref = 0 ; u32 Kdbl, intModVal ; u32 fracModVal ; @@ -2257,268 +2118,207 @@ u16 MXL_IFSynthInit(struct dvb_frontend *fe) if (state->Fxtal > 16000000UL && state->Fxtal <= 32000000UL) Kdbl = 1 ; - // - // IF Synthesizer Control - // - if (state->Mode == 0 && state->IF_Mode == 1) // Analog Low IF mode - { + /* IF Synthesizer Control */ + if (state->Mode == 0 && state->IF_Mode == 1) /* Analog Low IF mode */ { if (state->IF_LO == 41000000UL) { - status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08) ; - status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C) ; + status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08); + status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C); Fref = 328000000UL ; } if (state->IF_LO == 47000000UL) { - status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08) ; - status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; + status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08); + status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08); Fref = 376000000UL ; } if (state->IF_LO == 54000000UL) { - status += MXL_ControlWrite(fe, IF_DIVVAL, 0x10) ; - status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C) ; + status += MXL_ControlWrite(fe, IF_DIVVAL, 0x10); + status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C); Fref = 324000000UL ; } if (state->IF_LO == 60000000UL) { - status += MXL_ControlWrite(fe, IF_DIVVAL, 0x10) ; - status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; + status += MXL_ControlWrite(fe, IF_DIVVAL, 0x10); + status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08); Fref = 360000000UL ; } if (state->IF_LO == 39250000UL) { - status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08) ; - status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C) ; + status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08); + status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C); Fref = 314000000UL ; } if (state->IF_LO == 39650000UL) { - status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08) ; - status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C) ; + status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08); + status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C); Fref = 317200000UL ; } if (state->IF_LO == 40150000UL) { - status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08) ; - status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C) ; + status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08); + status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C); Fref = 321200000UL ; } if (state->IF_LO == 40650000UL) { - status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08) ; - status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C) ; + status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08); + status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C); Fref = 325200000UL ; } } - if (state->Mode || (state->Mode == 0 && state->IF_Mode == 0)) - { + if (state->Mode || (state->Mode == 0 && state->IF_Mode == 0)) { if (state->IF_LO == 57000000UL) { - status += MXL_ControlWrite(fe, IF_DIVVAL, 0x10) ; - status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; + status += MXL_ControlWrite(fe, IF_DIVVAL, 0x10); + status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08); Fref = 342000000UL ; } if (state->IF_LO == 44000000UL) { - status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08) ; - status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; + status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08); + status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08); Fref = 352000000UL ; } if (state->IF_LO == 43750000UL) { - status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08) ; - status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; + status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08); + status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08); Fref = 350000000UL ; } if (state->IF_LO == 36650000UL) { - status += MXL_ControlWrite(fe, IF_DIVVAL, 0x04) ; - status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; + status += MXL_ControlWrite(fe, IF_DIVVAL, 0x04); + status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08); Fref = 366500000UL ; } if (state->IF_LO == 36150000UL) { - status += MXL_ControlWrite(fe, IF_DIVVAL, 0x04) ; - status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; + status += MXL_ControlWrite(fe, IF_DIVVAL, 0x04); + status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08); Fref = 361500000UL ; } if (state->IF_LO == 36000000UL) { - status += MXL_ControlWrite(fe, IF_DIVVAL, 0x04) ; - status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; + status += MXL_ControlWrite(fe, IF_DIVVAL, 0x04); + status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08); Fref = 360000000UL ; } if (state->IF_LO == 35250000UL) { - status += MXL_ControlWrite(fe, IF_DIVVAL, 0x04) ; - status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; + status += MXL_ControlWrite(fe, IF_DIVVAL, 0x04); + status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08); Fref = 352500000UL ; } if (state->IF_LO == 34750000UL) { - status += MXL_ControlWrite(fe, IF_DIVVAL, 0x04) ; - status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; + status += MXL_ControlWrite(fe, IF_DIVVAL, 0x04); + status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08); Fref = 347500000UL ; } if (state->IF_LO == 6280000UL) { - status += MXL_ControlWrite(fe, IF_DIVVAL, 0x07) ; - status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; + status += MXL_ControlWrite(fe, IF_DIVVAL, 0x07); + status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08); Fref = 376800000UL ; } if (state->IF_LO == 5000000UL) { - status += MXL_ControlWrite(fe, IF_DIVVAL, 0x09) ; - status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; + status += MXL_ControlWrite(fe, IF_DIVVAL, 0x09); + status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08); Fref = 360000000UL ; } if (state->IF_LO == 4500000UL) { - status += MXL_ControlWrite(fe, IF_DIVVAL, 0x06) ; - status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; + status += MXL_ControlWrite(fe, IF_DIVVAL, 0x06); + status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08); Fref = 360000000UL ; } if (state->IF_LO == 4570000UL) { - status += MXL_ControlWrite(fe, IF_DIVVAL, 0x06) ; - status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; + status += MXL_ControlWrite(fe, IF_DIVVAL, 0x06); + status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08); Fref = 365600000UL ; } if (state->IF_LO == 4000000UL) { - status += MXL_ControlWrite(fe, IF_DIVVAL, 0x05) ; - status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; + status += MXL_ControlWrite(fe, IF_DIVVAL, 0x05); + status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08); Fref = 360000000UL ; } - if (state->IF_LO == 57400000UL) - { - status += MXL_ControlWrite(fe, IF_DIVVAL, 0x10) ; - status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; + if (state->IF_LO == 57400000UL) { + status += MXL_ControlWrite(fe, IF_DIVVAL, 0x10); + status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08); Fref = 344400000UL ; } - if (state->IF_LO == 44400000UL) - { - status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08) ; - status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; + if (state->IF_LO == 44400000UL) { + status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08); + status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08); Fref = 355200000UL ; } - if (state->IF_LO == 44150000UL) - { - status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08) ; - status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; + if (state->IF_LO == 44150000UL) { + status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08); + status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08); Fref = 353200000UL ; } - if (state->IF_LO == 37050000UL) - { - status += MXL_ControlWrite(fe, IF_DIVVAL, 0x04) ; - status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; + if (state->IF_LO == 37050000UL) { + status += MXL_ControlWrite(fe, IF_DIVVAL, 0x04); + status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08); Fref = 370500000UL ; } - if (state->IF_LO == 36550000UL) - { - status += MXL_ControlWrite(fe, IF_DIVVAL, 0x04) ; - status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; + if (state->IF_LO == 36550000UL) { + status += MXL_ControlWrite(fe, IF_DIVVAL, 0x04); + status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08); Fref = 365500000UL ; } if (state->IF_LO == 36125000UL) { - status += MXL_ControlWrite(fe, IF_DIVVAL, 0x04) ; - status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; + status += MXL_ControlWrite(fe, IF_DIVVAL, 0x04); + status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08); Fref = 361250000UL ; } if (state->IF_LO == 6000000UL) { - status += MXL_ControlWrite(fe, IF_DIVVAL, 0x07) ; - status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; + status += MXL_ControlWrite(fe, IF_DIVVAL, 0x07); + status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08); Fref = 360000000UL ; } - if (state->IF_LO == 5400000UL) - { - status += MXL_ControlWrite(fe, IF_DIVVAL, 0x07) ; - status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C) ; + if (state->IF_LO == 5400000UL) { + status += MXL_ControlWrite(fe, IF_DIVVAL, 0x07); + status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C); Fref = 324000000UL ; } if (state->IF_LO == 5380000UL) { - printk("%s() doing 5.38\n", __func__); - status += MXL_ControlWrite(fe, IF_DIVVAL, 0x07) ; - status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C) ; + status += MXL_ControlWrite(fe, IF_DIVVAL, 0x07); + status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C); Fref = 322800000UL ; } if (state->IF_LO == 5200000UL) { - status += MXL_ControlWrite(fe, IF_DIVVAL, 0x09) ; - status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; + status += MXL_ControlWrite(fe, IF_DIVVAL, 0x09); + status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08); Fref = 374400000UL ; } - if (state->IF_LO == 4900000UL) - { - status += MXL_ControlWrite(fe, IF_DIVVAL, 0x09) ; - status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; + if (state->IF_LO == 4900000UL) { + status += MXL_ControlWrite(fe, IF_DIVVAL, 0x09); + status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08); Fref = 352800000UL ; } - if (state->IF_LO == 4400000UL) - { - status += MXL_ControlWrite(fe, IF_DIVVAL, 0x06) ; - status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; + if (state->IF_LO == 4400000UL) { + status += MXL_ControlWrite(fe, IF_DIVVAL, 0x06); + status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08); Fref = 352000000UL ; } - if (state->IF_LO == 4063000UL) //add for 2.6.8 - { - status += MXL_ControlWrite(fe, IF_DIVVAL, 0x05) ; - status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ; + if (state->IF_LO == 4063000UL) /* add for 2.6.8 */ { + status += MXL_ControlWrite(fe, IF_DIVVAL, 0x05); + status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08); Fref = 365670000UL ; } } - // CHCAL_INT_MOD_IF - // CHCAL_FRAC_MOD_IF - intModVal = Fref / (state->Fxtal * Kdbl/2) ; - status += MXL_ControlWrite(fe, CHCAL_INT_MOD_IF, intModVal ) ; + /* CHCAL_INT_MOD_IF */ + /* CHCAL_FRAC_MOD_IF */ + intModVal = Fref / (state->Fxtal * Kdbl/2); + status += MXL_ControlWrite(fe, CHCAL_INT_MOD_IF, intModVal); + + fracModVal = (2<<15)*(Fref/1000 - (state->Fxtal/1000 * Kdbl/2) * + intModVal); - fracModVal = (2<<15)*(Fref/1000 - (state->Fxtal/1000 * Kdbl/2) * intModVal); - fracModVal = fracModVal / ((state->Fxtal * Kdbl/2)/1000) ; - status += MXL_ControlWrite(fe, CHCAL_FRAC_MOD_IF, fracModVal) ; + fracModVal = fracModVal / ((state->Fxtal * Kdbl/2)/1000); + status += MXL_ControlWrite(fe, CHCAL_FRAC_MOD_IF, fracModVal); return status ; } -/////////////////////////////////////////////////////////////////////////////// -// // -// Function: MXL_GetXtalInt // -// // -// Description: return the Crystal Integration Value for // -// TG_VCO_BIAS calculation // -// // -// Globals: // -// NONE // -// // -// Functions used: // -// NONE // -// // -// Inputs: // -// Crystal Frequency Value in Hz // -// // -// Outputs: // -// Calculated Crystal Frequency Integration Value // -// // -// Return: // -// 0 : Successful // -// > 0 : Failed // -// // -/////////////////////////////////////////////////////////////////////////////// u32 MXL_GetXtalInt(u32 Xtal_Freq) { if ((Xtal_Freq % 1000000) == 0) - return (Xtal_Freq / 10000) ; + return (Xtal_Freq / 10000); else - return (((Xtal_Freq / 1000000) + 1)*100) ; + return (((Xtal_Freq / 1000000) + 1)*100); } -/////////////////////////////////////////////////////////////////////////////// -// // -// Function: MXL5005_TuneRF // -// // -// Description: Set control names to tune to requested RF_IN frequency // -// // -// Globals: // -// None // -// // -// Functions used: // -// MXL_SynthRFTGLO_Calc // -// MXL5005_ControlWrite // -// MXL_GetXtalInt // -// // -// Inputs: // -// Tuner : Tuner structure defined at higher level // -// // -// Outputs: // -// Tuner // -// // -// Return: // -// 0 : Successful // -// 1 : Unsuccessful // -/////////////////////////////////////////////////////////////////////////////// u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq) { struct mxl5005s_state *state = fe->tuner_priv; - // Declare Local Variables u16 status = 0; u32 divider_val, E3, E4, E5, E5A; u32 Fmax, Fmin, FmaxBin, FminBin; @@ -2529,8 +2329,6 @@ u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq) u32 Fref_TG; u32 Fvco; -// u32 temp; - Xtal_Int = MXL_GetXtalInt(state->Fxtal); @@ -2543,21 +2341,19 @@ u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq) if (state->Fxtal > 22000000 && state->Fxtal <= 32000000) Kdbl_RF = 1; - // - // Downconverter Controls - // - // Look-Up Table Implementation for: - // DN_POLY - // DN_RFGAIN - // DN_CAP_RFLPF - // DN_EN_VHFUHFBAR - // DN_GAIN_ADJUST - // Change the boundary reference from RF_IN to RF_LO - if (state->RF_LO < 40000000UL) { + /* Downconverter Controls + * Look-Up Table Implementation for: + * DN_POLY + * DN_RFGAIN + * DN_CAP_RFLPF + * DN_EN_VHFUHFBAR + * DN_GAIN_ADJUST + * Change the boundary reference from RF_IN to RF_LO + */ + if (state->RF_LO < 40000000UL) return -1; - } + if (state->RF_LO >= 40000000UL && state->RF_LO <= 75000000UL) { - // Look-Up Table implementation status += MXL_ControlWrite(fe, DN_POLY, 2); status += MXL_ControlWrite(fe, DN_RFGAIN, 3); status += MXL_ControlWrite(fe, DN_CAP_RFLPF, 423); @@ -2565,7 +2361,6 @@ u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq) status += MXL_ControlWrite(fe, DN_GAIN_ADJUST, 1); } if (state->RF_LO > 75000000UL && state->RF_LO <= 100000000UL) { - // Look-Up Table implementation status += MXL_ControlWrite(fe, DN_POLY, 3); status += MXL_ControlWrite(fe, DN_RFGAIN, 3); status += MXL_ControlWrite(fe, DN_CAP_RFLPF, 222); @@ -2573,7 +2368,6 @@ u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq) status += MXL_ControlWrite(fe, DN_GAIN_ADJUST, 1); } if (state->RF_LO > 100000000UL && state->RF_LO <= 150000000UL) { - // Look-Up Table implementation status += MXL_ControlWrite(fe, DN_POLY, 3); status += MXL_ControlWrite(fe, DN_RFGAIN, 3); status += MXL_ControlWrite(fe, DN_CAP_RFLPF, 147); @@ -2581,7 +2375,6 @@ u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq) status += MXL_ControlWrite(fe, DN_GAIN_ADJUST, 2); } if (state->RF_LO > 150000000UL && state->RF_LO <= 200000000UL) { - // Look-Up Table implementation status += MXL_ControlWrite(fe, DN_POLY, 3); status += MXL_ControlWrite(fe, DN_RFGAIN, 3); status += MXL_ControlWrite(fe, DN_CAP_RFLPF, 9); @@ -2589,34 +2382,31 @@ u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq) status += MXL_ControlWrite(fe, DN_GAIN_ADJUST, 2); } if (state->RF_LO > 200000000UL && state->RF_LO <= 300000000UL) { - // Look-Up Table implementation - status += MXL_ControlWrite(fe, DN_POLY, 3) ; - status += MXL_ControlWrite(fe, DN_RFGAIN, 3) ; - status += MXL_ControlWrite(fe, DN_CAP_RFLPF, 0) ; - status += MXL_ControlWrite(fe, DN_EN_VHFUHFBAR, 1) ; - status += MXL_ControlWrite(fe, DN_GAIN_ADJUST, 3) ; + status += MXL_ControlWrite(fe, DN_POLY, 3); + status += MXL_ControlWrite(fe, DN_RFGAIN, 3); + status += MXL_ControlWrite(fe, DN_CAP_RFLPF, 0); + status += MXL_ControlWrite(fe, DN_EN_VHFUHFBAR, 1); + status += MXL_ControlWrite(fe, DN_GAIN_ADJUST, 3); } if (state->RF_LO > 300000000UL && state->RF_LO <= 650000000UL) { - // Look-Up Table implementation - status += MXL_ControlWrite(fe, DN_POLY, 3) ; - status += MXL_ControlWrite(fe, DN_RFGAIN, 1) ; - status += MXL_ControlWrite(fe, DN_CAP_RFLPF, 0) ; - status += MXL_ControlWrite(fe, DN_EN_VHFUHFBAR, 0) ; - status += MXL_ControlWrite(fe, DN_GAIN_ADJUST, 3) ; + status += MXL_ControlWrite(fe, DN_POLY, 3); + status += MXL_ControlWrite(fe, DN_RFGAIN, 1); + status += MXL_ControlWrite(fe, DN_CAP_RFLPF, 0); + status += MXL_ControlWrite(fe, DN_EN_VHFUHFBAR, 0); + status += MXL_ControlWrite(fe, DN_GAIN_ADJUST, 3); } if (state->RF_LO > 650000000UL && state->RF_LO <= 900000000UL) { - // Look-Up Table implementation - status += MXL_ControlWrite(fe, DN_POLY, 3) ; - status += MXL_ControlWrite(fe, DN_RFGAIN, 2) ; - status += MXL_ControlWrite(fe, DN_CAP_RFLPF, 0) ; - status += MXL_ControlWrite(fe, DN_EN_VHFUHFBAR, 0) ; - status += MXL_ControlWrite(fe, DN_GAIN_ADJUST, 3) ; + status += MXL_ControlWrite(fe, DN_POLY, 3); + status += MXL_ControlWrite(fe, DN_RFGAIN, 2); + status += MXL_ControlWrite(fe, DN_CAP_RFLPF, 0); + status += MXL_ControlWrite(fe, DN_EN_VHFUHFBAR, 0); + status += MXL_ControlWrite(fe, DN_GAIN_ADJUST, 3); } - if (state->RF_LO > 900000000UL) { + if (state->RF_LO > 900000000UL) return -1; - } - // DN_IQTNBUF_AMP - // DN_IQTNGNBFBIAS_BST + + /* DN_IQTNBUF_AMP */ + /* DN_IQTNGNBFBIAS_BST */ if (state->RF_LO >= 40000000UL && state->RF_LO <= 75000000UL) { status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP, 1); status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST, 0); @@ -2682,18 +2472,19 @@ u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq) status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST, 1); } - // - // Set RF Synth and LO Path Control - // - // Look-Up table implementation for: - // RFSYN_EN_OUTMUX - // RFSYN_SEL_VCO_OUT - // RFSYN_SEL_VCO_HI - // RFSYN_SEL_DIVM - // RFSYN_RF_DIV_BIAS - // DN_SEL_FREQ - // - // Set divider_val, Fmax, Fmix to use in Equations + /* + * Set RF Synth and LO Path Control + * + * Look-Up table implementation for: + * RFSYN_EN_OUTMUX + * RFSYN_SEL_VCO_OUT + * RFSYN_SEL_VCO_HI + * RFSYN_SEL_DIVM + * RFSYN_RF_DIV_BIAS + * DN_SEL_FREQ + * + * Set divider_val, Fmax, Fmix to use in Equations + */ FminBin = 28000000UL ; FmaxBin = 42500000UL ; if (state->RF_LO >= 40000000UL && state->RF_LO <= FmaxBin) { @@ -2723,12 +2514,12 @@ u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq) FminBin = 56000000UL ; FmaxBin = 85000000UL ; if (state->RF_LO > FminBin && state->RF_LO <= FmaxBin) { - status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 0) ; - status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 1) ; - status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0) ; - status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0) ; - status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1) ; - status += MXL_ControlWrite(fe, DN_SEL_FREQ, 1) ; + status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 0); + status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 1); + status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0); + status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0); + status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1); + status += MXL_ControlWrite(fe, DN_SEL_FREQ, 1); divider_val = 32 ; Fmax = FmaxBin ; Fmin = FminBin ; @@ -2736,12 +2527,12 @@ u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq) FminBin = 85000000UL ; FmaxBin = 112000000UL ; if (state->RF_LO > FminBin && state->RF_LO <= FmaxBin) { - status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 0) ; - status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 1) ; - status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1) ; - status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0) ; - status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1) ; - status += MXL_ControlWrite(fe, DN_SEL_FREQ, 1) ; + status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 0); + status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 1); + status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1); + status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0); + status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1); + status += MXL_ControlWrite(fe, DN_SEL_FREQ, 1); divider_val = 32 ; Fmax = FmaxBin ; Fmin = FminBin ; @@ -2749,12 +2540,12 @@ u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq) FminBin = 112000000UL ; FmaxBin = 170000000UL ; if (state->RF_LO > FminBin && state->RF_LO <= FmaxBin) { - status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 0) ; - status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 1) ; - status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0) ; - status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0) ; - status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1) ; - status += MXL_ControlWrite(fe, DN_SEL_FREQ, 2) ; + status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 0); + status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 1); + status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0); + status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0); + status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1); + status += MXL_ControlWrite(fe, DN_SEL_FREQ, 2); divider_val = 16 ; Fmax = FmaxBin ; Fmin = FminBin ; @@ -2762,12 +2553,12 @@ u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq) FminBin = 170000000UL ; FmaxBin = 225000000UL ; if (state->RF_LO > FminBin && state->RF_LO <= FmaxBin) { - status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 0) ; - status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 1) ; - status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1) ; - status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0) ; - status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1) ; - status += MXL_ControlWrite(fe, DN_SEL_FREQ, 2) ; + status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 0); + status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 1); + status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1); + status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0); + status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1); + status += MXL_ControlWrite(fe, DN_SEL_FREQ, 2); divider_val = 16 ; Fmax = FmaxBin ; Fmin = FminBin ; @@ -2775,12 +2566,12 @@ u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq) FminBin = 225000000UL ; FmaxBin = 300000000UL ; if (state->RF_LO > FminBin && state->RF_LO <= FmaxBin) { - status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 0) ; - status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 1) ; - status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0) ; - status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0) ; - status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1) ; - status += MXL_ControlWrite(fe, DN_SEL_FREQ, 4) ; + status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 0); + status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 1); + status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0); + status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0); + status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1); + status += MXL_ControlWrite(fe, DN_SEL_FREQ, 4); divider_val = 8 ; Fmax = 340000000UL ; Fmin = FminBin ; @@ -2788,12 +2579,12 @@ u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq) FminBin = 300000000UL ; FmaxBin = 340000000UL ; if (state->RF_LO > FminBin && state->RF_LO <= FmaxBin) { - status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 1) ; - status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 0) ; - status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0) ; - status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0) ; - status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1) ; - status += MXL_ControlWrite(fe, DN_SEL_FREQ, 0) ; + status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 1); + status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 0); + status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0); + status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0); + status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1); + status += MXL_ControlWrite(fe, DN_SEL_FREQ, 0); divider_val = 8 ; Fmax = FmaxBin ; Fmin = 225000000UL ; @@ -2801,12 +2592,12 @@ u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq) FminBin = 340000000UL ; FmaxBin = 450000000UL ; if (state->RF_LO > FminBin && state->RF_LO <= FmaxBin) { - status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 1) ; - status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 0) ; - status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1) ; - status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0) ; - status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 2) ; - status += MXL_ControlWrite(fe, DN_SEL_FREQ, 0) ; + status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 1); + status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 0); + status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1); + status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0); + status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 2); + status += MXL_ControlWrite(fe, DN_SEL_FREQ, 0); divider_val = 8 ; Fmax = FmaxBin ; Fmin = FminBin ; @@ -2814,12 +2605,12 @@ u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq) FminBin = 450000000UL ; FmaxBin = 680000000UL ; if (state->RF_LO > FminBin && state->RF_LO <= FmaxBin) { - status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 0) ; - status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 1) ; - status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0) ; - status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 1) ; - status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1) ; - status += MXL_ControlWrite(fe, DN_SEL_FREQ, 0) ; + status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 0); + status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 1); + status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0); + status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 1); + status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1); + status += MXL_ControlWrite(fe, DN_SEL_FREQ, 0); divider_val = 4 ; Fmax = FmaxBin ; Fmin = FminBin ; @@ -2827,67 +2618,66 @@ u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq) FminBin = 680000000UL ; FmaxBin = 900000000UL ; if (state->RF_LO > FminBin && state->RF_LO <= FmaxBin) { - status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 0) ; - status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 1) ; - status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1) ; - status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 1) ; - status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1) ; - status += MXL_ControlWrite(fe, DN_SEL_FREQ, 0) ; + status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 0); + status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 1); + status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1); + status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 1); + status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1); + status += MXL_ControlWrite(fe, DN_SEL_FREQ, 0); divider_val = 4 ; Fmax = FmaxBin ; Fmin = FminBin ; } - // CHCAL_INT_MOD_RF - // CHCAL_FRAC_MOD_RF - // RFSYN_LPF_R - // CHCAL_EN_INT_RF - - // Equation E3 - // RFSYN_VCO_BIAS + /* CHCAL_INT_MOD_RF + * CHCAL_FRAC_MOD_RF + * RFSYN_LPF_R + * CHCAL_EN_INT_RF + */ + /* Equation E3 RFSYN_VCO_BIAS */ E3 = (((Fmax-state->RF_LO)/1000)*32)/((Fmax-Fmin)/1000) + 8 ; - status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, E3) ; + status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, E3); - // Equation E4 - // CHCAL_INT_MOD_RF - E4 = (state->RF_LO*divider_val/1000)/(2*state->Fxtal*Kdbl_RF/1000) ; - MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, E4) ; + /* Equation E4 CHCAL_INT_MOD_RF */ + E4 = (state->RF_LO*divider_val/1000)/(2*state->Fxtal*Kdbl_RF/1000); + MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, E4); - // Equation E5 - // CHCAL_FRAC_MOD_RF - // CHCAL_EN_INT_RF - E5 = ((2<<17)*(state->RF_LO/10000*divider_val - (E4*(2*state->Fxtal*Kdbl_RF)/10000)))/(2*state->Fxtal*Kdbl_RF/10000) ; - status += MXL_ControlWrite(fe, CHCAL_FRAC_MOD_RF, E5) ; + /* Equation E5 CHCAL_FRAC_MOD_RF CHCAL_EN_INT_RF */ + E5 = ((2<<17)*(state->RF_LO/10000*divider_val - + (E4*(2*state->Fxtal*Kdbl_RF)/10000))) / + (2*state->Fxtal*Kdbl_RF/10000); - // Equation E5A - // RFSYN_LPF_R + status += MXL_ControlWrite(fe, CHCAL_FRAC_MOD_RF, E5); + + /* Equation E5A RFSYN_LPF_R */ E5A = (((Fmax - state->RF_LO)/1000)*4/((Fmax-Fmin)/1000)) + 1 ; - status += MXL_ControlWrite(fe, RFSYN_LPF_R, E5A) ; + status += MXL_ControlWrite(fe, RFSYN_LPF_R, E5A); - // Euqation E5B - // CHCAL_EN_INIT_RF + /* Euqation E5B CHCAL_EN_INIT_RF */ status += MXL_ControlWrite(fe, CHCAL_EN_INT_RF, ((E5 == 0) ? 1 : 0)); - //if (E5 == 0) - // status += MXL_ControlWrite(fe, CHCAL_EN_INT_RF, 1); - //else - // status += MXL_ControlWrite(fe, CHCAL_FRAC_MOD_RF, E5) ; - - // - // Set TG Synth - // - // Look-Up table implementation for: - // TG_LO_DIVVAL - // TG_LO_SELVAL - // - // Set divider_val, Fmax, Fmix to use in Equations - if (state->TG_LO < 33000000UL) { + /*if (E5 == 0) + * status += MXL_ControlWrite(fe, CHCAL_EN_INT_RF, 1); + *else + * status += MXL_ControlWrite(fe, CHCAL_FRAC_MOD_RF, E5); + */ + + /* + * Set TG Synth + * + * Look-Up table implementation for: + * TG_LO_DIVVAL + * TG_LO_SELVAL + * + * Set divider_val, Fmax, Fmix to use in Equations + */ + if (state->TG_LO < 33000000UL) return -1; - } + FminBin = 33000000UL ; FmaxBin = 50000000UL ; if (state->TG_LO >= FminBin && state->TG_LO <= FmaxBin) { - status += MXL_ControlWrite(fe, TG_LO_DIVVAL, 0x6) ; - status += MXL_ControlWrite(fe, TG_LO_SELVAL, 0x0) ; + status += MXL_ControlWrite(fe, TG_LO_DIVVAL, 0x6); + status += MXL_ControlWrite(fe, TG_LO_SELVAL, 0x0); divider_val = 36 ; Fmax = FmaxBin ; Fmin = FminBin ; @@ -2895,8 +2685,8 @@ u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq) FminBin = 50000000UL ; FmaxBin = 67000000UL ; if (state->TG_LO > FminBin && state->TG_LO <= FmaxBin) { - status += MXL_ControlWrite(fe, TG_LO_DIVVAL, 0x1) ; - status += MXL_ControlWrite(fe, TG_LO_SELVAL, 0x0) ; + status += MXL_ControlWrite(fe, TG_LO_DIVVAL, 0x1); + status += MXL_ControlWrite(fe, TG_LO_SELVAL, 0x0); divider_val = 24 ; Fmax = FmaxBin ; Fmin = FminBin ; @@ -2904,8 +2694,8 @@ u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq) FminBin = 67000000UL ; FmaxBin = 100000000UL ; if (state->TG_LO > FminBin && state->TG_LO <= FmaxBin) { - status += MXL_ControlWrite(fe, TG_LO_DIVVAL, 0xC) ; - status += MXL_ControlWrite(fe, TG_LO_SELVAL, 0x2) ; + status += MXL_ControlWrite(fe, TG_LO_DIVVAL, 0xC); + status += MXL_ControlWrite(fe, TG_LO_SELVAL, 0x2); divider_val = 18 ; Fmax = FmaxBin ; Fmin = FminBin ; @@ -2913,8 +2703,8 @@ u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq) FminBin = 100000000UL ; FmaxBin = 150000000UL ; if (state->TG_LO > FminBin && state->TG_LO <= FmaxBin) { - status += MXL_ControlWrite(fe, TG_LO_DIVVAL, 0x8) ; - status += MXL_ControlWrite(fe, TG_LO_SELVAL, 0x2) ; + status += MXL_ControlWrite(fe, TG_LO_DIVVAL, 0x8); + status += MXL_ControlWrite(fe, TG_LO_SELVAL, 0x2); divider_val = 12 ; Fmax = FmaxBin ; Fmin = FminBin ; @@ -2922,8 +2712,8 @@ u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq) FminBin = 150000000UL ; FmaxBin = 200000000UL ; if (state->TG_LO > FminBin && state->TG_LO <= FmaxBin) { - status += MXL_ControlWrite(fe, TG_LO_DIVVAL, 0x0) ; - status += MXL_ControlWrite(fe, TG_LO_SELVAL, 0x2) ; + status += MXL_ControlWrite(fe, TG_LO_DIVVAL, 0x0); + status += MXL_ControlWrite(fe, TG_LO_SELVAL, 0x2); divider_val = 8 ; Fmax = FmaxBin ; Fmin = FminBin ; @@ -2931,8 +2721,8 @@ u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq) FminBin = 200000000UL ; FmaxBin = 300000000UL ; if (state->TG_LO > FminBin && state->TG_LO <= FmaxBin) { - status += MXL_ControlWrite(fe, TG_LO_DIVVAL, 0x8) ; - status += MXL_ControlWrite(fe, TG_LO_SELVAL, 0x3) ; + status += MXL_ControlWrite(fe, TG_LO_DIVVAL, 0x8); + status += MXL_ControlWrite(fe, TG_LO_SELVAL, 0x3); divider_val = 6 ; Fmax = FmaxBin ; Fmin = FminBin ; @@ -2940,8 +2730,8 @@ u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq) FminBin = 300000000UL ; FmaxBin = 400000000UL ; if (state->TG_LO > FminBin && state->TG_LO <= FmaxBin) { - status += MXL_ControlWrite(fe, TG_LO_DIVVAL, 0x0) ; - status += MXL_ControlWrite(fe, TG_LO_SELVAL, 0x3) ; + status += MXL_ControlWrite(fe, TG_LO_DIVVAL, 0x0); + status += MXL_ControlWrite(fe, TG_LO_SELVAL, 0x3); divider_val = 4 ; Fmax = FmaxBin ; Fmin = FminBin ; @@ -2949,8 +2739,8 @@ u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq) FminBin = 400000000UL ; FmaxBin = 600000000UL ; if (state->TG_LO > FminBin && state->TG_LO <= FmaxBin) { - status += MXL_ControlWrite(fe, TG_LO_DIVVAL, 0x8) ; - status += MXL_ControlWrite(fe, TG_LO_SELVAL, 0x7) ; + status += MXL_ControlWrite(fe, TG_LO_DIVVAL, 0x8); + status += MXL_ControlWrite(fe, TG_LO_SELVAL, 0x7); divider_val = 3 ; Fmax = FmaxBin ; Fmin = FminBin ; @@ -2958,682 +2748,608 @@ u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq) FminBin = 600000000UL ; FmaxBin = 900000000UL ; if (state->TG_LO > FminBin && state->TG_LO <= FmaxBin) { - status += MXL_ControlWrite(fe, TG_LO_DIVVAL, 0x0) ; - status += MXL_ControlWrite(fe, TG_LO_SELVAL, 0x7) ; + status += MXL_ControlWrite(fe, TG_LO_DIVVAL, 0x0); + status += MXL_ControlWrite(fe, TG_LO_SELVAL, 0x7); divider_val = 2 ; Fmax = FmaxBin ; Fmin = FminBin ; } - // TG_DIV_VAL - tg_divval = (state->TG_LO*divider_val/100000) - *(MXL_Ceiling(state->Fxtal,1000000) * 100) / (state->Fxtal/1000) ; - status += MXL_ControlWrite(fe, TG_DIV_VAL, tg_divval) ; + /* TG_DIV_VAL */ + tg_divval = (state->TG_LO*divider_val/100000) * + (MXL_Ceiling(state->Fxtal, 1000000) * 100) / + (state->Fxtal/1000); + + status += MXL_ControlWrite(fe, TG_DIV_VAL, tg_divval); if (state->TG_LO > 600000000UL) - status += MXL_ControlWrite(fe, TG_DIV_VAL, tg_divval + 1 ) ; + status += MXL_ControlWrite(fe, TG_DIV_VAL, tg_divval + 1); Fmax = 1800000000UL ; Fmin = 1200000000UL ; + /* prevent overflow of 32 bit unsigned integer, use + * following equation. Edit for v2.6.4 + */ + /* Fref_TF = Fref_TG * 1000 */ + Fref_TG = (state->Fxtal/1000) / MXL_Ceiling(state->Fxtal, 1000000); - - // to prevent overflow of 32 bit unsigned integer, use following equation. Edit for v2.6.4 - Fref_TG = (state->Fxtal/1000)/ MXL_Ceiling(state->Fxtal, 1000000) ; // Fref_TF = Fref_TG*1000 - - Fvco = (state->TG_LO/10000) * divider_val * Fref_TG; //Fvco = Fvco/10 + /* Fvco = Fvco/10 */ + Fvco = (state->TG_LO/10000) * divider_val * Fref_TG; tg_lo = (((Fmax/10 - Fvco)/100)*32) / ((Fmax-Fmin)/1000)+8; - //below equation is same as above but much harder to debug. - //tg_lo = ( ((Fmax/10000 * Xtal_Int)/100) - ((state->TG_LO/10000)*divider_val*(state->Fxtal/10000)/100) )*32/((Fmax-Fmin)/10000 * Xtal_Int/100) + 8 ; - - - status += MXL_ControlWrite(fe, TG_VCO_BIAS , tg_lo) ; - + /* below equation is same as above but much harder to debug. + * tg_lo = ( ((Fmax/10000 * Xtal_Int)/100) - + * ((state->TG_LO/10000)*divider_val * + * (state->Fxtal/10000)/100) )*32/((Fmax-Fmin)/10000 * + * Xtal_Int/100) + 8; + */ + status += MXL_ControlWrite(fe, TG_VCO_BIAS , tg_lo); - //add for 2.6.5 - //Special setting for QAM - if(state->Mod_Type == MXL_QAM) - { - if(state->RF_IN < 680000000) - status += MXL_ControlWrite(fe, RFSYN_CHP_GAIN, 3) ; - else - status += MXL_ControlWrite(fe, RFSYN_CHP_GAIN, 2) ; + /* add for 2.6.5 Special setting for QAM */ + if (state->Mod_Type == MXL_QAM) { + if (state->RF_IN < 680000000) + status += MXL_ControlWrite(fe, RFSYN_CHP_GAIN, 3); + else + status += MXL_ControlWrite(fe, RFSYN_CHP_GAIN, 2); } - - //remove 20.48MHz setting for 2.6.10 - - // - // Off Chip Tracking Filter Control - // - if (state->TF_Type == MXL_TF_OFF) // Tracking Filter Off State; turn off all the banks - { - status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0) ; - status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; - - status += MXL_SetGPIO(fe, 3, 1) ; // turn off Bank 1 - status += MXL_SetGPIO(fe, 1, 1) ; // turn off Bank 2 - status += MXL_SetGPIO(fe, 4, 1) ; // turn off Bank 3 + /* Off Chip Tracking Filter Control */ + if (state->TF_Type == MXL_TF_OFF) { + /* Tracking Filter Off State; turn off all the banks */ + status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0); + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0); + status += MXL_SetGPIO(fe, 3, 1); /* Bank1 Off */ + status += MXL_SetGPIO(fe, 1, 1); /* Bank2 Off */ + status += MXL_SetGPIO(fe, 4, 1); /* Bank3 Off */ } - if (state->TF_Type == MXL_TF_C) // Tracking Filter type C - { - status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1) ; - status += MXL_ControlWrite(fe, DAC_DIN_A, 0) ; - - if (state->RF_IN >= 43000000 && state->RF_IN < 150000000) - { - - status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0) ; // Bank4 Off - status += MXL_ControlWrite(fe, DAC_DIN_B, 0) ; - status += MXL_SetGPIO(fe, 3, 0) ; // Bank1 On - status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off - status += MXL_SetGPIO(fe, 4, 1) ; // Bank3 Off - } - if (state->RF_IN >= 150000000 && state->RF_IN < 280000000) - { - status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0) ; // Bank4 Off - status += MXL_ControlWrite(fe, DAC_DIN_B, 0) ; - status += MXL_SetGPIO(fe, 3, 1) ; // Bank1 Off - status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On - status += MXL_SetGPIO(fe, 4, 1) ; // Bank3 Off - } - if (state->RF_IN >= 280000000 && state->RF_IN < 360000000) - { - status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0) ; // Bank4 Off - status += MXL_ControlWrite(fe, DAC_DIN_B, 0) ; - status += MXL_SetGPIO(fe, 3, 1) ; // Bank1 Off - status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On - status += MXL_SetGPIO(fe, 4, 0) ; // Bank3 On - } - if (state->RF_IN >= 360000000 && state->RF_IN < 560000000) - { - status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0) ; // Bank4 Off - status += MXL_ControlWrite(fe, DAC_DIN_B, 0) ; - status += MXL_SetGPIO(fe, 3, 1) ; // Bank1 Off - status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off - status += MXL_SetGPIO(fe, 4, 0) ; // Bank3 On - } - if (state->RF_IN >= 560000000 && state->RF_IN < 580000000) - { - status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1) ; // Bank4 On - status += MXL_ControlWrite(fe, DAC_DIN_B, 29) ; - status += MXL_SetGPIO(fe, 3, 1) ; // Bank1 Off - status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off - status += MXL_SetGPIO(fe, 4, 0) ; // Bank3 On - } - if (state->RF_IN >= 580000000 && state->RF_IN < 630000000) - { - status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1) ; // Bank4 On - status += MXL_ControlWrite(fe, DAC_DIN_B, 0) ; - status += MXL_SetGPIO(fe, 3, 1) ; // Bank1 Off - status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off - status += MXL_SetGPIO(fe, 4, 0) ; // Bank3 On - } - if (state->RF_IN >= 630000000 && state->RF_IN < 700000000) - { - status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1) ; // Bank4 On - status += MXL_ControlWrite(fe, DAC_DIN_B, 16) ; - status += MXL_SetGPIO(fe, 3, 1) ; // Bank1 Off - status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off - status += MXL_SetGPIO(fe, 4, 1) ; // Bank3 Off - } - if (state->RF_IN >= 700000000 && state->RF_IN < 760000000) - { - status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1) ; // Bank4 On - status += MXL_ControlWrite(fe, DAC_DIN_B, 7) ; - status += MXL_SetGPIO(fe, 3, 1) ; // Bank1 Off - status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off - status += MXL_SetGPIO(fe, 4, 1) ; // Bank3 Off - } - if (state->RF_IN >= 760000000 && state->RF_IN <= 900000000) - { - status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1) ; // Bank4 On - status += MXL_ControlWrite(fe, DAC_DIN_B, 0) ; - status += MXL_SetGPIO(fe, 3, 1) ; // Bank1 Off - status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off - status += MXL_SetGPIO(fe, 4, 1) ; // Bank3 Off + if (state->TF_Type == MXL_TF_C) /* Tracking Filter type C */ { + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1); + status += MXL_ControlWrite(fe, DAC_DIN_A, 0); + + if (state->RF_IN >= 43000000 && state->RF_IN < 150000000) { + status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0); + status += MXL_ControlWrite(fe, DAC_DIN_B, 0); + status += MXL_SetGPIO(fe, 3, 0); + status += MXL_SetGPIO(fe, 1, 1); + status += MXL_SetGPIO(fe, 4, 1); + } + if (state->RF_IN >= 150000000 && state->RF_IN < 280000000) { + status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0); + status += MXL_ControlWrite(fe, DAC_DIN_B, 0); + status += MXL_SetGPIO(fe, 3, 1); + status += MXL_SetGPIO(fe, 1, 0); + status += MXL_SetGPIO(fe, 4, 1); + } + if (state->RF_IN >= 280000000 && state->RF_IN < 360000000) { + status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0); + status += MXL_ControlWrite(fe, DAC_DIN_B, 0); + status += MXL_SetGPIO(fe, 3, 1); + status += MXL_SetGPIO(fe, 1, 0); + status += MXL_SetGPIO(fe, 4, 0); + } + if (state->RF_IN >= 360000000 && state->RF_IN < 560000000) { + status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0); + status += MXL_ControlWrite(fe, DAC_DIN_B, 0); + status += MXL_SetGPIO(fe, 3, 1); + status += MXL_SetGPIO(fe, 1, 1); + status += MXL_SetGPIO(fe, 4, 0); + } + if (state->RF_IN >= 560000000 && state->RF_IN < 580000000) { + status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1); + status += MXL_ControlWrite(fe, DAC_DIN_B, 29); + status += MXL_SetGPIO(fe, 3, 1); + status += MXL_SetGPIO(fe, 1, 1); + status += MXL_SetGPIO(fe, 4, 0); + } + if (state->RF_IN >= 580000000 && state->RF_IN < 630000000) { + status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1); + status += MXL_ControlWrite(fe, DAC_DIN_B, 0); + status += MXL_SetGPIO(fe, 3, 1); + status += MXL_SetGPIO(fe, 1, 1); + status += MXL_SetGPIO(fe, 4, 0); + } + if (state->RF_IN >= 630000000 && state->RF_IN < 700000000) { + status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1); + status += MXL_ControlWrite(fe, DAC_DIN_B, 16); + status += MXL_SetGPIO(fe, 3, 1); + status += MXL_SetGPIO(fe, 1, 1); + status += MXL_SetGPIO(fe, 4, 1); + } + if (state->RF_IN >= 700000000 && state->RF_IN < 760000000) { + status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1); + status += MXL_ControlWrite(fe, DAC_DIN_B, 7); + status += MXL_SetGPIO(fe, 3, 1); + status += MXL_SetGPIO(fe, 1, 1); + status += MXL_SetGPIO(fe, 4, 1); + } + if (state->RF_IN >= 760000000 && state->RF_IN <= 900000000) { + status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1); + status += MXL_ControlWrite(fe, DAC_DIN_B, 0); + status += MXL_SetGPIO(fe, 3, 1); + status += MXL_SetGPIO(fe, 1, 1); + status += MXL_SetGPIO(fe, 4, 1); } } - if (state->TF_Type == MXL_TF_C_H) // Tracking Filter type C-H for Hauppauge only - { - printk("%s() CH filter\n", __func__); - status += MXL_ControlWrite(fe, DAC_DIN_A, 0) ; - - if (state->RF_IN >= 43000000 && state->RF_IN < 150000000) - { - - status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0) ; // Bank4 Off - status += MXL_SetGPIO(fe, 4, 0) ; // Bank1 On - status += MXL_SetGPIO(fe, 3, 1) ; // Bank2 Off - status += MXL_SetGPIO(fe, 1, 1) ; // Bank3 Off - } - if (state->RF_IN >= 150000000 && state->RF_IN < 280000000) - { - status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0) ; // Bank4 Off - status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(fe, 3, 0) ; // Bank2 On - status += MXL_SetGPIO(fe, 1, 1) ; // Bank3 Off - } - if (state->RF_IN >= 280000000 && state->RF_IN < 360000000) - { - status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0) ; // Bank4 Off - status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(fe, 3, 0) ; // Bank2 On - status += MXL_SetGPIO(fe, 1, 0) ; // Bank3 On - } - if (state->RF_IN >= 360000000 && state->RF_IN < 560000000) - { - status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0) ; // Bank4 Off - status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(fe, 3, 1) ; // Bank2 Off - status += MXL_SetGPIO(fe, 1, 0) ; // Bank3 On - } - if (state->RF_IN >= 560000000 && state->RF_IN < 580000000) - { - status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1) ; // Bank4 On - status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(fe, 3, 1) ; // Bank2 Off - status += MXL_SetGPIO(fe, 1, 0) ; // Bank3 On - } - if (state->RF_IN >= 580000000 && state->RF_IN < 630000000) - { - status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1) ; // Bank4 On - status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(fe, 3, 1) ; // Bank2 Off - status += MXL_SetGPIO(fe, 1, 0) ; // Bank3 On - } - if (state->RF_IN >= 630000000 && state->RF_IN < 700000000) - { - status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1) ; // Bank4 On - status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(fe, 3, 1) ; // Bank2 Off - status += MXL_SetGPIO(fe, 1, 1) ; // Bank3 Off - } - if (state->RF_IN >= 700000000 && state->RF_IN < 760000000) - { - status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1) ; // Bank4 On - status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(fe, 3, 1) ; // Bank2 Off - status += MXL_SetGPIO(fe, 1, 1) ; // Bank3 Off - } - if (state->RF_IN >= 760000000 && state->RF_IN <= 900000000) - { - status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1) ; // Bank4 On - status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(fe, 3, 1) ; // Bank2 Off - status += MXL_SetGPIO(fe, 1, 1) ; // Bank3 Off + if (state->TF_Type == MXL_TF_C_H) { + + /* Tracking Filter type C-H for Hauppauge only */ + status += MXL_ControlWrite(fe, DAC_DIN_A, 0); + + if (state->RF_IN >= 43000000 && state->RF_IN < 150000000) { + status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0); + status += MXL_SetGPIO(fe, 4, 0); + status += MXL_SetGPIO(fe, 3, 1); + status += MXL_SetGPIO(fe, 1, 1); + } + if (state->RF_IN >= 150000000 && state->RF_IN < 280000000) { + status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0); + status += MXL_SetGPIO(fe, 4, 1); + status += MXL_SetGPIO(fe, 3, 0); + status += MXL_SetGPIO(fe, 1, 1); + } + if (state->RF_IN >= 280000000 && state->RF_IN < 360000000) { + status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0); + status += MXL_SetGPIO(fe, 4, 1); + status += MXL_SetGPIO(fe, 3, 0); + status += MXL_SetGPIO(fe, 1, 0); + } + if (state->RF_IN >= 360000000 && state->RF_IN < 560000000) { + status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0); + status += MXL_SetGPIO(fe, 4, 1); + status += MXL_SetGPIO(fe, 3, 1); + status += MXL_SetGPIO(fe, 1, 0); + } + if (state->RF_IN >= 560000000 && state->RF_IN < 580000000) { + status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1); + status += MXL_SetGPIO(fe, 4, 1); + status += MXL_SetGPIO(fe, 3, 1); + status += MXL_SetGPIO(fe, 1, 0); + } + if (state->RF_IN >= 580000000 && state->RF_IN < 630000000) { + status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1); + status += MXL_SetGPIO(fe, 4, 1); + status += MXL_SetGPIO(fe, 3, 1); + status += MXL_SetGPIO(fe, 1, 0); + } + if (state->RF_IN >= 630000000 && state->RF_IN < 700000000) { + status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1); + status += MXL_SetGPIO(fe, 4, 1); + status += MXL_SetGPIO(fe, 3, 1); + status += MXL_SetGPIO(fe, 1, 1); + } + if (state->RF_IN >= 700000000 && state->RF_IN < 760000000) { + status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1); + status += MXL_SetGPIO(fe, 4, 1); + status += MXL_SetGPIO(fe, 3, 1); + status += MXL_SetGPIO(fe, 1, 1); + } + if (state->RF_IN >= 760000000 && state->RF_IN <= 900000000) { + status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1); + status += MXL_SetGPIO(fe, 4, 1); + status += MXL_SetGPIO(fe, 3, 1); + status += MXL_SetGPIO(fe, 1, 1); } } - if (state->TF_Type == MXL_TF_D) // Tracking Filter type D - { - status += MXL_ControlWrite(fe, DAC_DIN_B, 0) ; - - if (state->RF_IN >= 43000000 && state->RF_IN < 174000000) - { - - status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off - status += MXL_SetGPIO(fe, 4, 0) ; // Bank1 On - status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off - status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off - } - if (state->RF_IN >= 174000000 && state->RF_IN < 250000000) - { - status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off - status += MXL_SetGPIO(fe, 4, 0) ; // Bank1 On - status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On - status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off - } - if (state->RF_IN >= 250000000 && state->RF_IN < 310000000) - { - status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off - status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On - status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off - } - if (state->RF_IN >= 310000000 && state->RF_IN < 360000000) - { - status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off - status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On - status += MXL_SetGPIO(fe, 3, 0) ; // Bank3 On - } - if (state->RF_IN >= 360000000 && state->RF_IN < 470000000) - { - status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off - status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off - status += MXL_SetGPIO(fe, 3, 0) ; // Bank3 On - } - if (state->RF_IN >= 470000000 && state->RF_IN < 640000000) - { - status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1) ; // Bank4 On - status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off - status += MXL_SetGPIO(fe, 3, 0) ; // Bank3 On - } - if (state->RF_IN >= 640000000 && state->RF_IN <= 900000000) - { - status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1) ; // Bank4 On - status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off - status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off + if (state->TF_Type == MXL_TF_D) { /* Tracking Filter type D */ + + status += MXL_ControlWrite(fe, DAC_DIN_B, 0); + + if (state->RF_IN >= 43000000 && state->RF_IN < 174000000) { + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0); + status += MXL_SetGPIO(fe, 4, 0); + status += MXL_SetGPIO(fe, 1, 1); + status += MXL_SetGPIO(fe, 3, 1); + } + if (state->RF_IN >= 174000000 && state->RF_IN < 250000000) { + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0); + status += MXL_SetGPIO(fe, 4, 0); + status += MXL_SetGPIO(fe, 1, 0); + status += MXL_SetGPIO(fe, 3, 1); + } + if (state->RF_IN >= 250000000 && state->RF_IN < 310000000) { + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0); + status += MXL_SetGPIO(fe, 4, 1); + status += MXL_SetGPIO(fe, 1, 0); + status += MXL_SetGPIO(fe, 3, 1); + } + if (state->RF_IN >= 310000000 && state->RF_IN < 360000000) { + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0); + status += MXL_SetGPIO(fe, 4, 1); + status += MXL_SetGPIO(fe, 1, 0); + status += MXL_SetGPIO(fe, 3, 0); + } + if (state->RF_IN >= 360000000 && state->RF_IN < 470000000) { + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0); + status += MXL_SetGPIO(fe, 4, 1); + status += MXL_SetGPIO(fe, 1, 1); + status += MXL_SetGPIO(fe, 3, 0); + } + if (state->RF_IN >= 470000000 && state->RF_IN < 640000000) { + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1); + status += MXL_SetGPIO(fe, 4, 1); + status += MXL_SetGPIO(fe, 1, 1); + status += MXL_SetGPIO(fe, 3, 0); + } + if (state->RF_IN >= 640000000 && state->RF_IN <= 900000000) { + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1); + status += MXL_SetGPIO(fe, 4, 1); + status += MXL_SetGPIO(fe, 1, 1); + status += MXL_SetGPIO(fe, 3, 1); } } - - if (state->TF_Type == MXL_TF_D_L) // Tracking Filter type D-L for Lumanate ONLY change for 2.6.3 - { - status += MXL_ControlWrite(fe, DAC_DIN_A, 0) ; - - // if UHF and terrestrial => Turn off Tracking Filter - if (state->RF_IN >= 471000000 && (state->RF_IN - 471000000)%6000000 != 0) - { - // Turn off all the banks - status += MXL_SetGPIO(fe, 3, 1) ; - status += MXL_SetGPIO(fe, 1, 1) ; - status += MXL_SetGPIO(fe, 4, 1) ; - status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0) ; - - status += MXL_ControlWrite(fe, AGC_IF, 10) ; - } - - else // if VHF or cable => Turn on Tracking Filter - { - if (state->RF_IN >= 43000000 && state->RF_IN < 140000000) - { - - status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0) ; // Bank4 Off - status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 On - status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off - status += MXL_SetGPIO(fe, 3, 0) ; // Bank3 Off + if (state->TF_Type == MXL_TF_D_L) { + + /* Tracking Filter type D-L for Lumanate ONLY change 2.6.3 */ + status += MXL_ControlWrite(fe, DAC_DIN_A, 0); + + /* if UHF and terrestrial => Turn off Tracking Filter */ + if (state->RF_IN >= 471000000 && + (state->RF_IN - 471000000)%6000000 != 0) { + /* Turn off all the banks */ + status += MXL_SetGPIO(fe, 3, 1); + status += MXL_SetGPIO(fe, 1, 1); + status += MXL_SetGPIO(fe, 4, 1); + status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0); + status += MXL_ControlWrite(fe, AGC_IF, 10); + } else { + /* if VHF or cable => Turn on Tracking Filter */ + if (state->RF_IN >= 43000000 && + state->RF_IN < 140000000) { + + status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0); + status += MXL_SetGPIO(fe, 4, 1); + status += MXL_SetGPIO(fe, 1, 1); + status += MXL_SetGPIO(fe, 3, 0); } - if (state->RF_IN >= 140000000 && state->RF_IN < 240000000) - { - status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0) ; // Bank4 Off - status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 On - status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On - status += MXL_SetGPIO(fe, 3, 0) ; // Bank3 Off + if (state->RF_IN >= 140000000 && + state->RF_IN < 240000000) { + status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0); + status += MXL_SetGPIO(fe, 4, 1); + status += MXL_SetGPIO(fe, 1, 0); + status += MXL_SetGPIO(fe, 3, 0); } - if (state->RF_IN >= 240000000 && state->RF_IN < 340000000) - { - status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0) ; // Bank4 Off - status += MXL_SetGPIO(fe, 4, 0) ; // Bank1 Off - status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 On - status += MXL_SetGPIO(fe, 3, 0) ; // Bank3 Off + if (state->RF_IN >= 240000000 && + state->RF_IN < 340000000) { + status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0); + status += MXL_SetGPIO(fe, 4, 0); + status += MXL_SetGPIO(fe, 1, 1); + status += MXL_SetGPIO(fe, 3, 0); } - if (state->RF_IN >= 340000000 && state->RF_IN < 430000000) - { - status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0) ; // Bank4 Off - status += MXL_SetGPIO(fe, 4, 0) ; // Bank1 Off - status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On - status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 On + if (state->RF_IN >= 340000000 && + state->RF_IN < 430000000) { + status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0); + status += MXL_SetGPIO(fe, 4, 0); + status += MXL_SetGPIO(fe, 1, 0); + status += MXL_SetGPIO(fe, 3, 1); } - if (state->RF_IN >= 430000000 && state->RF_IN < 470000000) - { - status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1) ; // Bank4 Off - status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 Off - status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 On + if (state->RF_IN >= 430000000 && + state->RF_IN < 470000000) { + status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1); + status += MXL_SetGPIO(fe, 4, 1); + status += MXL_SetGPIO(fe, 1, 0); + status += MXL_SetGPIO(fe, 3, 1); } - if (state->RF_IN >= 470000000 && state->RF_IN < 570000000) - { - status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1) ; // Bank4 On - status += MXL_SetGPIO(fe, 4, 0) ; // Bank1 Off - status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 Off - status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 On + if (state->RF_IN >= 470000000 && + state->RF_IN < 570000000) { + status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1); + status += MXL_SetGPIO(fe, 4, 0); + status += MXL_SetGPIO(fe, 1, 0); + status += MXL_SetGPIO(fe, 3, 1); } - if (state->RF_IN >= 570000000 && state->RF_IN < 620000000) - { - status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0) ; // Bank4 On - status += MXL_SetGPIO(fe, 4, 0) ; // Bank1 Off - status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off - status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Offq + if (state->RF_IN >= 570000000 && + state->RF_IN < 620000000) { + status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0); + status += MXL_SetGPIO(fe, 4, 0); + status += MXL_SetGPIO(fe, 1, 1); + status += MXL_SetGPIO(fe, 3, 1); } - if (state->RF_IN >= 620000000 && state->RF_IN < 760000000) - { - status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1) ; // Bank4 On - status += MXL_SetGPIO(fe, 4, 0) ; // Bank1 Off - status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off - status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off + if (state->RF_IN >= 620000000 && + state->RF_IN < 760000000) { + status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1); + status += MXL_SetGPIO(fe, 4, 0); + status += MXL_SetGPIO(fe, 1, 1); + status += MXL_SetGPIO(fe, 3, 1); } - if (state->RF_IN >= 760000000 && state->RF_IN <= 900000000) - { - status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1) ; // Bank4 On - status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off - status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off + if (state->RF_IN >= 760000000 && + state->RF_IN <= 900000000) { + status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1); + status += MXL_SetGPIO(fe, 4, 1); + status += MXL_SetGPIO(fe, 1, 1); + status += MXL_SetGPIO(fe, 3, 1); } } } - if (state->TF_Type == MXL_TF_E) // Tracking Filter type E - { - status += MXL_ControlWrite(fe, DAC_DIN_B, 0) ; - - if (state->RF_IN >= 43000000 && state->RF_IN < 174000000) - { - - status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off - status += MXL_SetGPIO(fe, 4, 0) ; // Bank1 On - status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off - status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off - } - if (state->RF_IN >= 174000000 && state->RF_IN < 250000000) - { - status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off - status += MXL_SetGPIO(fe, 4, 0) ; // Bank1 On - status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On - status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off - } - if (state->RF_IN >= 250000000 && state->RF_IN < 310000000) - { - status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off - status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On - status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off - } - if (state->RF_IN >= 310000000 && state->RF_IN < 360000000) - { - status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off - status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On - status += MXL_SetGPIO(fe, 3, 0) ; // Bank3 On - } - if (state->RF_IN >= 360000000 && state->RF_IN < 470000000) - { - status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off - status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off - status += MXL_SetGPIO(fe, 3, 0) ; // Bank3 On - } - if (state->RF_IN >= 470000000 && state->RF_IN < 640000000) - { - status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1) ; // Bank4 On - status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off - status += MXL_SetGPIO(fe, 3, 0) ; // Bank3 On - } - if (state->RF_IN >= 640000000 && state->RF_IN <= 900000000) - { - status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1) ; // Bank4 On - status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off - status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off + if (state->TF_Type == MXL_TF_E) /* Tracking Filter type E */ { + + status += MXL_ControlWrite(fe, DAC_DIN_B, 0); + + if (state->RF_IN >= 43000000 && state->RF_IN < 174000000) { + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0); + status += MXL_SetGPIO(fe, 4, 0); + status += MXL_SetGPIO(fe, 1, 1); + status += MXL_SetGPIO(fe, 3, 1); + } + if (state->RF_IN >= 174000000 && state->RF_IN < 250000000) { + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0); + status += MXL_SetGPIO(fe, 4, 0); + status += MXL_SetGPIO(fe, 1, 0); + status += MXL_SetGPIO(fe, 3, 1); + } + if (state->RF_IN >= 250000000 && state->RF_IN < 310000000) { + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0); + status += MXL_SetGPIO(fe, 4, 1); + status += MXL_SetGPIO(fe, 1, 0); + status += MXL_SetGPIO(fe, 3, 1); + } + if (state->RF_IN >= 310000000 && state->RF_IN < 360000000) { + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0); + status += MXL_SetGPIO(fe, 4, 1); + status += MXL_SetGPIO(fe, 1, 0); + status += MXL_SetGPIO(fe, 3, 0); + } + if (state->RF_IN >= 360000000 && state->RF_IN < 470000000) { + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0); + status += MXL_SetGPIO(fe, 4, 1); + status += MXL_SetGPIO(fe, 1, 1); + status += MXL_SetGPIO(fe, 3, 0); + } + if (state->RF_IN >= 470000000 && state->RF_IN < 640000000) { + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1); + status += MXL_SetGPIO(fe, 4, 1); + status += MXL_SetGPIO(fe, 1, 1); + status += MXL_SetGPIO(fe, 3, 0); + } + if (state->RF_IN >= 640000000 && state->RF_IN <= 900000000) { + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1); + status += MXL_SetGPIO(fe, 4, 1); + status += MXL_SetGPIO(fe, 1, 1); + status += MXL_SetGPIO(fe, 3, 1); } } - if (state->TF_Type == MXL_TF_F) // Tracking Filter type F - { - status += MXL_ControlWrite(fe, DAC_DIN_B, 0) ; - - if (state->RF_IN >= 43000000 && state->RF_IN < 160000000) - { - - status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off - status += MXL_SetGPIO(fe, 4, 0) ; // Bank1 On - status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off - status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off - } - if (state->RF_IN >= 160000000 && state->RF_IN < 210000000) - { - status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off - status += MXL_SetGPIO(fe, 4, 0) ; // Bank1 On - status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On - status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off - } - if (state->RF_IN >= 210000000 && state->RF_IN < 300000000) - { - status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off - status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On - status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off - } - if (state->RF_IN >= 300000000 && state->RF_IN < 390000000) - { - status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off - status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On - status += MXL_SetGPIO(fe, 3, 0) ; // Bank3 On - } - if (state->RF_IN >= 390000000 && state->RF_IN < 515000000) - { - status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off - status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off - status += MXL_SetGPIO(fe, 3, 0) ; // Bank3 On - } - if (state->RF_IN >= 515000000 && state->RF_IN < 650000000) - { - status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1) ; // Bank4 On - status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off - status += MXL_SetGPIO(fe, 3, 0) ; // Bank3 On - } - if (state->RF_IN >= 650000000 && state->RF_IN <= 900000000) - { - status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1) ; // Bank4 On - status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off - status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off + if (state->TF_Type == MXL_TF_F) { + + /* Tracking Filter type F */ + status += MXL_ControlWrite(fe, DAC_DIN_B, 0); + + if (state->RF_IN >= 43000000 && state->RF_IN < 160000000) { + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0); + status += MXL_SetGPIO(fe, 4, 0); + status += MXL_SetGPIO(fe, 1, 1); + status += MXL_SetGPIO(fe, 3, 1); + } + if (state->RF_IN >= 160000000 && state->RF_IN < 210000000) { + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0); + status += MXL_SetGPIO(fe, 4, 0); + status += MXL_SetGPIO(fe, 1, 0); + status += MXL_SetGPIO(fe, 3, 1); + } + if (state->RF_IN >= 210000000 && state->RF_IN < 300000000) { + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0); + status += MXL_SetGPIO(fe, 4, 1); + status += MXL_SetGPIO(fe, 1, 0); + status += MXL_SetGPIO(fe, 3, 1); + } + if (state->RF_IN >= 300000000 && state->RF_IN < 390000000) { + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0); + status += MXL_SetGPIO(fe, 4, 1); + status += MXL_SetGPIO(fe, 1, 0); + status += MXL_SetGPIO(fe, 3, 0); + } + if (state->RF_IN >= 390000000 && state->RF_IN < 515000000) { + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0); + status += MXL_SetGPIO(fe, 4, 1); + status += MXL_SetGPIO(fe, 1, 1); + status += MXL_SetGPIO(fe, 3, 0); + } + if (state->RF_IN >= 515000000 && state->RF_IN < 650000000) { + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1); + status += MXL_SetGPIO(fe, 4, 1); + status += MXL_SetGPIO(fe, 1, 1); + status += MXL_SetGPIO(fe, 3, 0); + } + if (state->RF_IN >= 650000000 && state->RF_IN <= 900000000) { + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1); + status += MXL_SetGPIO(fe, 4, 1); + status += MXL_SetGPIO(fe, 1, 1); + status += MXL_SetGPIO(fe, 3, 1); } } - if (state->TF_Type == MXL_TF_E_2) // Tracking Filter type E_2 - { - status += MXL_ControlWrite(fe, DAC_DIN_B, 0) ; - - if (state->RF_IN >= 43000000 && state->RF_IN < 174000000) - { - - status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off - status += MXL_SetGPIO(fe, 4, 0) ; // Bank1 On - status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off - status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off - } - if (state->RF_IN >= 174000000 && state->RF_IN < 250000000) - { - status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off - status += MXL_SetGPIO(fe, 4, 0) ; // Bank1 On - status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On - status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off - } - if (state->RF_IN >= 250000000 && state->RF_IN < 350000000) - { - status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off - status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On - status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off - } - if (state->RF_IN >= 350000000 && state->RF_IN < 400000000) - { - status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off - status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On - status += MXL_SetGPIO(fe, 3, 0) ; // Bank3 On - } - if (state->RF_IN >= 400000000 && state->RF_IN < 570000000) - { - status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off - status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off - status += MXL_SetGPIO(fe, 3, 0) ; // Bank3 On - } - if (state->RF_IN >= 570000000 && state->RF_IN < 770000000) - { - status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1) ; // Bank4 On - status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off - status += MXL_SetGPIO(fe, 3, 0) ; // Bank3 On - } - if (state->RF_IN >= 770000000 && state->RF_IN <= 900000000) - { - status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1) ; // Bank4 On - status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off - status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off + if (state->TF_Type == MXL_TF_E_2) { + + /* Tracking Filter type E_2 */ + status += MXL_ControlWrite(fe, DAC_DIN_B, 0); + + if (state->RF_IN >= 43000000 && state->RF_IN < 174000000) { + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0); + status += MXL_SetGPIO(fe, 4, 0); + status += MXL_SetGPIO(fe, 1, 1); + status += MXL_SetGPIO(fe, 3, 1); + } + if (state->RF_IN >= 174000000 && state->RF_IN < 250000000) { + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0); + status += MXL_SetGPIO(fe, 4, 0); + status += MXL_SetGPIO(fe, 1, 0); + status += MXL_SetGPIO(fe, 3, 1); + } + if (state->RF_IN >= 250000000 && state->RF_IN < 350000000) { + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0); + status += MXL_SetGPIO(fe, 4, 1); + status += MXL_SetGPIO(fe, 1, 0); + status += MXL_SetGPIO(fe, 3, 1); + } + if (state->RF_IN >= 350000000 && state->RF_IN < 400000000) { + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0); + status += MXL_SetGPIO(fe, 4, 1); + status += MXL_SetGPIO(fe, 1, 0); + status += MXL_SetGPIO(fe, 3, 0); + } + if (state->RF_IN >= 400000000 && state->RF_IN < 570000000) { + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0); + status += MXL_SetGPIO(fe, 4, 1); + status += MXL_SetGPIO(fe, 1, 1); + status += MXL_SetGPIO(fe, 3, 0); + } + if (state->RF_IN >= 570000000 && state->RF_IN < 770000000) { + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1); + status += MXL_SetGPIO(fe, 4, 1); + status += MXL_SetGPIO(fe, 1, 1); + status += MXL_SetGPIO(fe, 3, 0); + } + if (state->RF_IN >= 770000000 && state->RF_IN <= 900000000) { + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1); + status += MXL_SetGPIO(fe, 4, 1); + status += MXL_SetGPIO(fe, 1, 1); + status += MXL_SetGPIO(fe, 3, 1); } } - if (state->TF_Type == MXL_TF_G) // Tracking Filter type G add for v2.6.8 - { - status += MXL_ControlWrite(fe, DAC_DIN_B, 0) ; - - if (state->RF_IN >= 50000000 && state->RF_IN < 190000000) - { - - status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off - status += MXL_SetGPIO(fe, 4, 0) ; // Bank1 On - status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off - status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off - } - if (state->RF_IN >= 190000000 && state->RF_IN < 280000000) - { - status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off - status += MXL_SetGPIO(fe, 4, 0) ; // Bank1 On - status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On - status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off - } - if (state->RF_IN >= 280000000 && state->RF_IN < 350000000) - { - status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off - status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On - status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off - } - if (state->RF_IN >= 350000000 && state->RF_IN < 400000000) - { - status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off - status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On - status += MXL_SetGPIO(fe, 3, 0) ; // Bank3 On - } - if (state->RF_IN >= 400000000 && state->RF_IN < 470000000) //modified for 2.6.11 - { - status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1) ; // Bank4 On - status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 On - status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 Off - status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off - } - if (state->RF_IN >= 470000000 && state->RF_IN < 640000000) - { - status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off - status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off - status += MXL_SetGPIO(fe, 3, 0) ; // Bank3 On - } - if (state->RF_IN >= 640000000 && state->RF_IN < 820000000) - { - status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1) ; // Bank4 On - status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off - status += MXL_SetGPIO(fe, 3, 0) ; // Bank3 On - } - if (state->RF_IN >= 820000000 && state->RF_IN <= 900000000) - { - status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1) ; // Bank4 On - status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off - status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off + if (state->TF_Type == MXL_TF_G) { + + /* Tracking Filter type G add for v2.6.8 */ + status += MXL_ControlWrite(fe, DAC_DIN_B, 0); + + if (state->RF_IN >= 50000000 && state->RF_IN < 190000000) { + + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0); + status += MXL_SetGPIO(fe, 4, 0); + status += MXL_SetGPIO(fe, 1, 1); + status += MXL_SetGPIO(fe, 3, 1); + } + if (state->RF_IN >= 190000000 && state->RF_IN < 280000000) { + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0); + status += MXL_SetGPIO(fe, 4, 0); + status += MXL_SetGPIO(fe, 1, 0); + status += MXL_SetGPIO(fe, 3, 1); + } + if (state->RF_IN >= 280000000 && state->RF_IN < 350000000) { + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0); + status += MXL_SetGPIO(fe, 4, 1); + status += MXL_SetGPIO(fe, 1, 0); + status += MXL_SetGPIO(fe, 3, 1); + } + if (state->RF_IN >= 350000000 && state->RF_IN < 400000000) { + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0); + status += MXL_SetGPIO(fe, 4, 1); + status += MXL_SetGPIO(fe, 1, 0); + status += MXL_SetGPIO(fe, 3, 0); + } + if (state->RF_IN >= 400000000 && state->RF_IN < 470000000) { + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1); + status += MXL_SetGPIO(fe, 4, 1); + status += MXL_SetGPIO(fe, 1, 0); + status += MXL_SetGPIO(fe, 3, 1); + } + if (state->RF_IN >= 470000000 && state->RF_IN < 640000000) { + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0); + status += MXL_SetGPIO(fe, 4, 1); + status += MXL_SetGPIO(fe, 1, 1); + status += MXL_SetGPIO(fe, 3, 0); + } + if (state->RF_IN >= 640000000 && state->RF_IN < 820000000) { + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1); + status += MXL_SetGPIO(fe, 4, 1); + status += MXL_SetGPIO(fe, 1, 1); + status += MXL_SetGPIO(fe, 3, 0); + } + if (state->RF_IN >= 820000000 && state->RF_IN <= 900000000) { + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1); + status += MXL_SetGPIO(fe, 4, 1); + status += MXL_SetGPIO(fe, 1, 1); + status += MXL_SetGPIO(fe, 3, 1); } } - if (state->TF_Type == MXL_TF_E_NA) // Tracking Filter type E-NA for Empia ONLY change for 2.6.8 - { - status += MXL_ControlWrite(fe, DAC_DIN_B, 0) ; - - // if UHF and terrestrial=> Turn off Tracking Filter - if (state->RF_IN >= 471000000 && (state->RF_IN - 471000000)%6000000 != 0) - { - // Turn off all the banks - status += MXL_SetGPIO(fe, 3, 1) ; - status += MXL_SetGPIO(fe, 1, 1) ; - status += MXL_SetGPIO(fe, 4, 1) ; - status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; - - //2.6.12 - //Turn on RSSI - status += MXL_ControlWrite(fe, SEQ_EXTSYNTHCALIF, 1) ; - status += MXL_ControlWrite(fe, SEQ_EXTDCCAL, 1) ; - status += MXL_ControlWrite(fe, AGC_EN_RSSI, 1) ; - status += MXL_ControlWrite(fe, RFA_ENCLKRFAGC, 1) ; - - // RSSI reference point - status += MXL_ControlWrite(fe, RFA_RSSI_REFH, 5) ; - status += MXL_ControlWrite(fe, RFA_RSSI_REF, 3) ; - status += MXL_ControlWrite(fe, RFA_RSSI_REFL, 2) ; - - - //status += MXL_ControlWrite(fe, AGC_IF, 10) ; //doesn't matter since RSSI is turn on - - //following parameter is from analog OTA mode, can be change to seek better performance - status += MXL_ControlWrite(fe, RFSYN_CHP_GAIN, 3) ; - } - - else //if VHF or Cable => Turn on Tracking Filter - { - //2.6.12 - //Turn off RSSI - status += MXL_ControlWrite(fe, AGC_EN_RSSI, 0) ; - - //change back from above condition - status += MXL_ControlWrite(fe, RFSYN_CHP_GAIN, 5) ; - - - if (state->RF_IN >= 43000000 && state->RF_IN < 174000000) - { - - status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off - status += MXL_SetGPIO(fe, 4, 0) ; // Bank1 On - status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off - status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off - } - if (state->RF_IN >= 174000000 && state->RF_IN < 250000000) - { - status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off - status += MXL_SetGPIO(fe, 4, 0) ; // Bank1 On - status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On - status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off - } - if (state->RF_IN >= 250000000 && state->RF_IN < 350000000) - { - status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off - status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On - status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off - } - if (state->RF_IN >= 350000000 && state->RF_IN < 400000000) - { - status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off - status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On - status += MXL_SetGPIO(fe, 3, 0) ; // Bank3 On - } - if (state->RF_IN >= 400000000 && state->RF_IN < 570000000) - { - status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off - status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off - status += MXL_SetGPIO(fe, 3, 0) ; // Bank3 On - } - if (state->RF_IN >= 570000000 && state->RF_IN < 770000000) - { - status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1) ; // Bank4 On - status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off - status += MXL_SetGPIO(fe, 3, 0) ; // Bank3 On - } - if (state->RF_IN >= 770000000 && state->RF_IN <= 900000000) - { - status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1) ; // Bank4 On - status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off - status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off - status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off + if (state->TF_Type == MXL_TF_E_NA) { + + /* Tracking Filter type E-NA for Empia ONLY change for 2.6.8 */ + status += MXL_ControlWrite(fe, DAC_DIN_B, 0); + + /* if UHF and terrestrial=> Turn off Tracking Filter */ + if (state->RF_IN >= 471000000 && + (state->RF_IN - 471000000)%6000000 != 0) { + + /* Turn off all the banks */ + status += MXL_SetGPIO(fe, 3, 1); + status += MXL_SetGPIO(fe, 1, 1); + status += MXL_SetGPIO(fe, 4, 1); + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0); + + /* 2.6.12 Turn on RSSI */ + status += MXL_ControlWrite(fe, SEQ_EXTSYNTHCALIF, 1); + status += MXL_ControlWrite(fe, SEQ_EXTDCCAL, 1); + status += MXL_ControlWrite(fe, AGC_EN_RSSI, 1); + status += MXL_ControlWrite(fe, RFA_ENCLKRFAGC, 1); + + /* RSSI reference point */ + status += MXL_ControlWrite(fe, RFA_RSSI_REFH, 5); + status += MXL_ControlWrite(fe, RFA_RSSI_REF, 3); + status += MXL_ControlWrite(fe, RFA_RSSI_REFL, 2); + + /* following parameter is from analog OTA mode, + * can be change to seek better performance */ + status += MXL_ControlWrite(fe, RFSYN_CHP_GAIN, 3); + } else { + /* if VHF or Cable => Turn on Tracking Filter */ + + /* 2.6.12 Turn off RSSI */ + status += MXL_ControlWrite(fe, AGC_EN_RSSI, 0); + + /* change back from above condition */ + status += MXL_ControlWrite(fe, RFSYN_CHP_GAIN, 5); + + + if (state->RF_IN >= 43000000 && state->RF_IN < 174000000) { + + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0); + status += MXL_SetGPIO(fe, 4, 0); + status += MXL_SetGPIO(fe, 1, 1); + status += MXL_SetGPIO(fe, 3, 1); + } + if (state->RF_IN >= 174000000 && state->RF_IN < 250000000) { + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0); + status += MXL_SetGPIO(fe, 4, 0); + status += MXL_SetGPIO(fe, 1, 0); + status += MXL_SetGPIO(fe, 3, 1); + } + if (state->RF_IN >= 250000000 && state->RF_IN < 350000000) { + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0); + status += MXL_SetGPIO(fe, 4, 1); + status += MXL_SetGPIO(fe, 1, 0); + status += MXL_SetGPIO(fe, 3, 1); + } + if (state->RF_IN >= 350000000 && state->RF_IN < 400000000) { + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0); + status += MXL_SetGPIO(fe, 4, 1); + status += MXL_SetGPIO(fe, 1, 0); + status += MXL_SetGPIO(fe, 3, 0); + } + if (state->RF_IN >= 400000000 && state->RF_IN < 570000000) { + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0); + status += MXL_SetGPIO(fe, 4, 1); + status += MXL_SetGPIO(fe, 1, 1); + status += MXL_SetGPIO(fe, 3, 0); + } + if (state->RF_IN >= 570000000 && state->RF_IN < 770000000) { + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1); + status += MXL_SetGPIO(fe, 4, 1); + status += MXL_SetGPIO(fe, 1, 1); + status += MXL_SetGPIO(fe, 3, 0); + } + if (state->RF_IN >= 770000000 && state->RF_IN <= 900000000) { + status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1); + status += MXL_SetGPIO(fe, 4, 1); + status += MXL_SetGPIO(fe, 1, 1); + status += MXL_SetGPIO(fe, 3, 1); } } } @@ -3681,72 +3397,24 @@ u16 MXL_SetGPIO(struct dvb_frontend *fe, u8 GPIO_Num, u8 GPIO_Val) return status; } -/////////////////////////////////////////////////////////////////////////////// -// // -// Function: MXL_ControlWrite // -// // -// Description: Update control name value // -// // -// Globals: // -// NONE // -// // -// Functions used: // -// MXL_ControlWrite( Tuner, controlName, value, Group ) // -// // -// Inputs: // -// Tuner : Tuner structure // -// ControlName : Control name to be updated // -// value : Value to be written // -// // -// Outputs: // -// Tuner : Tuner structure defined at higher level // -// // -// Return: // -// 0 : Successful write // -// >0 : Value exceed maximum allowed for control number // -// // -/////////////////////////////////////////////////////////////////////////////// u16 MXL_ControlWrite(struct dvb_frontend *fe, u16 ControlNum, u32 value) { u16 status = 0; /* Will write ALL Matching Control Name */ - status += MXL_ControlWrite_Group(fe, ControlNum, value, 1); /* Write Matching INIT Control */ - status += MXL_ControlWrite_Group(fe, ControlNum, value, 2); /* Write Matching CH Control */ + /* Write Matching INIT Control */ + status += MXL_ControlWrite_Group(fe, ControlNum, value, 1); + /* Write Matching CH Control */ + status += MXL_ControlWrite_Group(fe, ControlNum, value, 2); #ifdef _MXL_INTERNAL - status += MXL_ControlWrite_Group(fe, ControlNum, value, 3); /* Write Matching MXL Control */ + /* Write Matching MXL Control */ + status += MXL_ControlWrite_Group(fe, ControlNum, value, 3); #endif return status; } -/////////////////////////////////////////////////////////////////////////////// -// // -// Function: MXL_ControlWrite // -// // -// Description: Update control name value // -// // -// Globals: // -// NONE // -// // -// Functions used: // -// strcmp // -// // -// Inputs: // -// Tuner_struct: structure defined at higher level // -// ControlName : Control Name // -// value : Value Assigned to Control Name // -// controlGroup : Control Register Group // -// // -// Outputs: // -// NONE // -// // -// Return: // -// 0 : Successful write // -// 1 : Value exceed maximum allowed for control name // -// 2 : Control name not found // -// // -/////////////////////////////////////////////////////////////////////////////// -u16 MXL_ControlWrite_Group(struct dvb_frontend *fe, u16 controlNum, u32 value, u16 controlGroup) +u16 MXL_ControlWrite_Group(struct dvb_frontend *fe, u16 controlNum, u32 value, + u16 controlGroup) { struct mxl5005s_state *state = fe->tuner_priv; u16 i, j, k; @@ -3765,13 +3433,12 @@ u16 MXL_ControlWrite_Group(struct dvb_frontend *fe, u16 controlNum, u32 value, u state->Init_Ctrl[i].val[j] = (u8)((value >> j) & 0x01); MXL_RegWriteBit(fe, (u8)(state->Init_Ctrl[i].addr[j]), (u8)(state->Init_Ctrl[i].bit[j]), - (u8)((value>>j) & 0x01) ); + (u8)((value>>j) & 0x01)); } ctrlVal = 0; for (k = 0; k < state->Init_Ctrl[i].size; k++) ctrlVal += state->Init_Ctrl[i].val[k] * (1 << k); - } - else + } else return -1; } } @@ -3780,7 +3447,7 @@ u16 MXL_ControlWrite_Group(struct dvb_frontend *fe, u16 controlNum, u32 value, u for (i = 0; i < state->CH_Ctrl_Num; i++) { - if (controlNum == state->CH_Ctrl[i].Ctrl_Num ) { + if (controlNum == state->CH_Ctrl[i].Ctrl_Num) { highLimit = 1 << state->CH_Ctrl[i].size; if (value < highLimit) { @@ -3788,13 +3455,12 @@ u16 MXL_ControlWrite_Group(struct dvb_frontend *fe, u16 controlNum, u32 value, u state->CH_Ctrl[i].val[j] = (u8)((value >> j) & 0x01); MXL_RegWriteBit(fe, (u8)(state->CH_Ctrl[i].addr[j]), (u8)(state->CH_Ctrl[i].bit[j]), - (u8)((value>>j) & 0x01) ); + (u8)((value>>j) & 0x01)); } ctrlVal = 0; for (k = 0; k < state->CH_Ctrl[i].size; k++) ctrlVal += state->CH_Ctrl[i].val[k] * (1 << k); - } - else + } else return -1; } } @@ -3804,21 +3470,20 @@ u16 MXL_ControlWrite_Group(struct dvb_frontend *fe, u16 controlNum, u32 value, u for (i = 0; i < state->MXL_Ctrl_Num; i++) { - if (controlNum == state->MXL_Ctrl[i].Ctrl_Num ) { + if (controlNum == state->MXL_Ctrl[i].Ctrl_Num) { - highLimit = (1 << state->MXL_Ctrl[i].size) ; + highLimit = (1 << state->MXL_Ctrl[i].size); if (value < highLimit) { for (j = 0; j < state->MXL_Ctrl[i].size; j++) { state->MXL_Ctrl[i].val[j] = (u8)((value >> j) & 0x01); MXL_RegWriteBit(fe, (u8)(state->MXL_Ctrl[i].addr[j]), (u8)(state->MXL_Ctrl[i].bit[j]), - (u8)((value>>j) & 0x01) ); + (u8)((value>>j) & 0x01)); } ctrlVal = 0; - for(k = 0; k < state->MXL_Ctrl[i].size; k++) + for (k = 0; k < state->MXL_Ctrl[i].size; k++) ctrlVal += state->MXL_Ctrl[i].val[k] * (1 << k); - } - else + } else return -1; } } @@ -3827,31 +3492,6 @@ u16 MXL_ControlWrite_Group(struct dvb_frontend *fe, u16 controlNum, u32 value, u return 0 ; /* successful return */ } -/////////////////////////////////////////////////////////////////////////////// -// // -// Function: MXL_RegWrite // -// // -// Description: Update tuner register value // -// // -// Globals: // -// NONE // -// // -// Functions used: // -// NONE // -// // -// Inputs: // -// Tuner_struct: structure defined at higher level // -// RegNum : Register address to be assigned a value // -// RegVal : Register value to write // -// // -// Outputs: // -// NONE // -// // -// Return: // -// 0 : Successful write // -// -1 : Invalid Register Address // -// // -/////////////////////////////////////////////////////////////////////////////// u16 MXL_RegWrite(struct dvb_frontend *fe, u8 RegNum, u8 RegVal) { struct mxl5005s_state *state = fe->tuner_priv; @@ -3867,37 +3507,13 @@ u16 MXL_RegWrite(struct dvb_frontend *fe, u8 RegNum, u8 RegVal) return 1; } -/////////////////////////////////////////////////////////////////////////////// -// // -// Function: MXL_RegRead // -// // -// Description: Retrieve tuner register value // -// // -// Globals: // -// NONE // -// // -// Functions used: // -// NONE // -// // -// Inputs: // -// Tuner_struct: structure defined at higher level // -// RegNum : Register address to be assigned a value // -// // -// Outputs: // -// RegVal : Retrieved register value // -// // -// Return: // -// 0 : Successful read // -// -1 : Invalid Register Address // -// // -/////////////////////////////////////////////////////////////////////////////// u16 MXL_RegRead(struct dvb_frontend *fe, u8 RegNum, u8 *RegVal) { struct mxl5005s_state *state = fe->tuner_priv; int i ; for (i = 0; i < 104; i++) { - if (RegNum == state->TunerRegs[i].Reg_Num ) { + if (RegNum == state->TunerRegs[i].Reg_Num) { *RegVal = (u8)(state->TunerRegs[i].Reg_Val); return 0; } @@ -3906,27 +3522,6 @@ u16 MXL_RegRead(struct dvb_frontend *fe, u8 RegNum, u8 *RegVal) return 1; } -/////////////////////////////////////////////////////////////////////////////// -// // -// Function: MXL_ControlRead // -// // -// Description: Retrieve the control value based on the control name // -// // -// Globals: // -// NONE // -// // -// Inputs: // -// Tuner_struct : structure defined at higher level // -// ControlName : Control Name // -// // -// Outputs: // -// value : returned control value // -// // -// Return: // -// 0 : Successful read // -// -1 : Invalid control name // -// // -/////////////////////////////////////////////////////////////////////////////// u16 MXL_ControlRead(struct dvb_frontend *fe, u16 controlNum, u32 *value) { struct mxl5005s_state *state = fe->tuner_priv; @@ -3939,7 +3534,7 @@ u16 MXL_ControlRead(struct dvb_frontend *fe, u16 controlNum, u32 *value) ctrlVal = 0; for (k = 0; k < state->Init_Ctrl[i].size; k++) - ctrlVal += state->Init_Ctrl[i].val[k] * (1 << k); + ctrlVal += state->Init_Ctrl[i].val[k] * (1<tuner_priv; u16 i, j, k ; @@ -4006,7 +3579,7 @@ u16 MXL_ControlRegRead(struct dvb_frontend *fe, u16 controlNum, u8 *RegNum, int for (i = 0; i < state->Init_Ctrl_Num ; i++) { - if ( controlNum == state->Init_Ctrl[i].Ctrl_Num ) { + if (controlNum == state->Init_Ctrl[i].Ctrl_Num) { Count = 1; RegNum[0] = (u8)(state->Init_Ctrl[i].addr[0]); @@ -4015,9 +3588,10 @@ u16 MXL_ControlRegRead(struct dvb_frontend *fe, u16 controlNum, u8 *RegNum, int for (j = 0; j < Count; j++) { - if (state->Init_Ctrl[i].addr[k] != RegNum[j]) { + if (state->Init_Ctrl[i].addr[k] != + RegNum[j]) { - Count ++; + Count++; RegNum[Count-1] = (u8)(state->Init_Ctrl[i].addr[k]); } @@ -4030,18 +3604,19 @@ u16 MXL_ControlRegRead(struct dvb_frontend *fe, u16 controlNum, u8 *RegNum, int } for (i = 0; i < state->CH_Ctrl_Num ; i++) { - if ( controlNum == state->CH_Ctrl[i].Ctrl_Num ) { + if (controlNum == state->CH_Ctrl[i].Ctrl_Num) { Count = 1; RegNum[0] = (u8)(state->CH_Ctrl[i].addr[0]); for (k = 1; k < state->CH_Ctrl[i].size; k++) { - for (j= 0; jCH_Ctrl[i].addr[k] != RegNum[j]) { + if (state->CH_Ctrl[i].addr[k] != + RegNum[j]) { - Count ++; + Count++; RegNum[Count-1] = (u8)(state->CH_Ctrl[i].addr[k]); } @@ -4054,18 +3629,19 @@ u16 MXL_ControlRegRead(struct dvb_frontend *fe, u16 controlNum, u8 *RegNum, int #ifdef _MXL_INTERNAL for (i = 0; i < state->MXL_Ctrl_Num ; i++) { - if ( controlNum == state->MXL_Ctrl[i].Ctrl_Num ) { + if (controlNum == state->MXL_Ctrl[i].Ctrl_Num) { Count = 1; RegNum[0] = (u8)(state->MXL_Ctrl[i].addr[0]); for (k = 1; k < state->MXL_Ctrl[i].size; k++) { - for (j = 0; jMXL_Ctrl[i].addr[k] != RegNum[j]) { + if (state->MXL_Ctrl[i].addr[k] != + RegNum[j]) { - Count ++; + Count++; RegNum[Count-1] = (u8)state->MXL_Ctrl[i].addr[k]; } @@ -4080,29 +3656,6 @@ u16 MXL_ControlRegRead(struct dvb_frontend *fe, u16 controlNum, u8 *RegNum, int return 1; } -/////////////////////////////////////////////////////////////////////////////// -// // -// Function: MXL_RegWriteBit // -// // -// Description: Write a register for specified register address, // -// register bit and register bit value // -// // -// Globals: // -// NONE // -// // -// Inputs: // -// Tuner_struct : structure defined at higher level // -// address : register address // -// bit : register bit number // -// bitVal : register bit value // -// // -// Outputs: // -// NONE // -// // -// Return: // -// NONE // -// // -/////////////////////////////////////////////////////////////////////////////// void MXL_RegWriteBit(struct dvb_frontend *fe, u8 address, u8 bit, u8 bitVal) { struct mxl5005s_state *state = fe->tuner_priv; @@ -4127,38 +3680,14 @@ void MXL_RegWriteBit(struct dvb_frontend *fe, u8 address, u8 bit, u8 bitVal) } } -/////////////////////////////////////////////////////////////////////////////// -// // -// Function: MXL_Ceiling // -// // -// Description: Complete to closest increment of resolution // -// // -// Globals: // -// NONE // -// // -// Functions used: // -// NONE // -// // -// Inputs: // -// value : Input number to compute // -// resolution : Increment step // -// // -// Outputs: // -// NONE // -// // -// Return: // -// Computed value // -// // -/////////////////////////////////////////////////////////////////////////////// u32 MXL_Ceiling(u32 value, u32 resolution) { return (value/resolution + (value % resolution > 0 ? 1 : 0)); } -// -// Retrieve the Initialzation Registers -// -u16 MXL_GetInitRegister(struct dvb_frontend *fe, u8 * RegNum, u8 *RegVal, int *count) +/* Retrieve the Initialzation Registers */ +u16 MXL_GetInitRegister(struct dvb_frontend *fe, u8 *RegNum, + u8 *RegVal, int *count) { u16 status = 0; int i ; @@ -4180,21 +3709,24 @@ u16 MXL_GetInitRegister(struct dvb_frontend *fe, u8 * RegNum, u8 *RegVal, int *c return status; } -u16 MXL_GetCHRegister(struct dvb_frontend *fe, u8 * RegNum, u8 *RegVal, int *count) +u16 MXL_GetCHRegister(struct dvb_frontend *fe, u8 *RegNum, u8 *RegVal, + int *count) { u16 status = 0; int i ; -//add 77, 166, 167, 168 register for 2.6.12 +/* add 77, 166, 167, 168 register for 2.6.12 */ #ifdef _MXL_PRODUCTION u8 RegAddr[] = {14, 15, 16, 17, 22, 43, 65, 68, 69, 70, 73, 92, 93, 106, 107, 108, 109, 110, 111, 112, 136, 138, 149, 77, 166, 167, 168 } ; #else u8 RegAddr[] = {14, 15, 16, 17, 22, 43, 68, 69, 70, 73, 92, 93, 106, 107, 108, 109, 110, 111, 112, 136, 138, 149, 77, 166, 167, 168 } ; - //u8 RegAddr[171]; - //for (i=0; i<=170; i++) - // RegAddr[i] = i; + /* + u8 RegAddr[171]; + for (i = 0; i <= 170; i++) + RegAddr[i] = i; + */ #endif *count = sizeof(RegAddr) / sizeof(u8); @@ -4207,7 +3739,8 @@ u16 MXL_GetCHRegister(struct dvb_frontend *fe, u8 * RegNum, u8 *RegVal, int *cou return status; } -u16 MXL_GetCHRegister_ZeroIF(struct dvb_frontend *fe, u8 * RegNum, u8 *RegVal, int *count) +u16 MXL_GetCHRegister_ZeroIF(struct dvb_frontend *fe, u8 *RegNum, u8 *RegVal, + int *count) { u16 status = 0; int i; @@ -4224,7 +3757,8 @@ u16 MXL_GetCHRegister_ZeroIF(struct dvb_frontend *fe, u8 * RegNum, u8 *RegVal, i return status; } -u16 MXL_GetCHRegister_LowIF(struct dvb_frontend *fe, u8 * RegNum, u8 *RegVal, int *count) +u16 MXL_GetCHRegister_LowIF(struct dvb_frontend *fe, u8 *RegNum, u8 *RegVal, + int *count) { u16 status = 0; int i; @@ -4269,23 +3803,28 @@ u16 MXL_VCORange_Test(struct dvb_frontend *fe, int VCO_Range) status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 1); status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1); status += MXL_ControlWrite(fe, DN_SEL_FREQ, 0); - if (state->Mode == 0 && state->IF_Mode == 1) /* Analog Low IF Mode */ { + if (state->Mode == 0 && state->IF_Mode == 1) { + /* Analog Low IF Mode */ status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1); status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 8); status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 56); - status += MXL_ControlWrite(fe, CHCAL_FRAC_MOD_RF, 180224); + status += MXL_ControlWrite(fe, + CHCAL_FRAC_MOD_RF, 180224); } - if (state->Mode == 0 && state->IF_Mode == 0) /* Analog Zero IF Mode */ { + if (state->Mode == 0 && state->IF_Mode == 0) { + /* Analog Zero IF Mode */ status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1); status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 8); status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 56); - status += MXL_ControlWrite(fe, CHCAL_FRAC_MOD_RF, 222822); + status += MXL_ControlWrite(fe, + CHCAL_FRAC_MOD_RF, 222822); } if (state->Mode == 1) /* Digital Mode */ { status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1); status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 8); status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 56); - status += MXL_ControlWrite(fe, CHCAL_FRAC_MOD_RF, 229376); + status += MXL_ControlWrite(fe, + CHCAL_FRAC_MOD_RF, 229376); } } @@ -4300,23 +3839,28 @@ u16 MXL_VCORange_Test(struct dvb_frontend *fe, int VCO_Range) status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1); status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 40); status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 41); - if (state->Mode == 0 && state->IF_Mode == 1) /* Analog Low IF Mode */ { + if (state->Mode == 0 && state->IF_Mode == 1) { + /* Analog Low IF Mode */ status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1); status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 40); status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 42); - status += MXL_ControlWrite(fe, CHCAL_FRAC_MOD_RF, 206438); + status += MXL_ControlWrite(fe, + CHCAL_FRAC_MOD_RF, 206438); } - if (state->Mode == 0 && state->IF_Mode == 0) /* Analog Zero IF Mode */ { + if (state->Mode == 0 && state->IF_Mode == 0) { + /* Analog Zero IF Mode */ status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1); status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 40); status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 42); - status += MXL_ControlWrite(fe, CHCAL_FRAC_MOD_RF, 206438); + status += MXL_ControlWrite(fe, + CHCAL_FRAC_MOD_RF, 206438); } if (state->Mode == 1) /* Digital Mode */ { status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1); status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 40); status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 41); - status += MXL_ControlWrite(fe, CHCAL_FRAC_MOD_RF, 16384); + status += MXL_ControlWrite(fe, + CHCAL_FRAC_MOD_RF, 16384); } } @@ -4331,23 +3875,28 @@ u16 MXL_VCORange_Test(struct dvb_frontend *fe, int VCO_Range) status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0); status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 8); status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 42); - if (state->Mode == 0 && state->IF_Mode == 1) /* Analog Low IF Mode */ { + if (state->Mode == 0 && state->IF_Mode == 1) { + /* Analog Low IF Mode */ status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0); status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 8); status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 44); - status += MXL_ControlWrite(fe, CHCAL_FRAC_MOD_RF, 173670); + status += MXL_ControlWrite(fe, + CHCAL_FRAC_MOD_RF, 173670); } - if (state->Mode == 0 && state->IF_Mode == 0) /* Analog Zero IF Mode */ { + if (state->Mode == 0 && state->IF_Mode == 0) { + /* Analog Zero IF Mode */ status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0); status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 8); status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 44); - status += MXL_ControlWrite(fe, CHCAL_FRAC_MOD_RF, 173670); + status += MXL_ControlWrite(fe, + CHCAL_FRAC_MOD_RF, 173670); } if (state->Mode == 1) /* Digital Mode */ { status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0); status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 8); status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 42); - status += MXL_ControlWrite(fe, CHCAL_FRAC_MOD_RF, 245760); + status += MXL_ControlWrite(fe, + CHCAL_FRAC_MOD_RF, 245760); } } @@ -4362,23 +3911,28 @@ u16 MXL_VCORange_Test(struct dvb_frontend *fe, int VCO_Range) status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0); status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 40); status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 27); - if (state->Mode == 0 && state->IF_Mode == 1) /* Analog Low IF Mode */ { + if (state->Mode == 0 && state->IF_Mode == 1) { + /* Analog Low IF Mode */ status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0); status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 40); status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 27); - status += MXL_ControlWrite(fe, CHCAL_FRAC_MOD_RF, 206438); + status += MXL_ControlWrite(fe, + CHCAL_FRAC_MOD_RF, 206438); } - if (state->Mode == 0 && state->IF_Mode == 0) /* Analog Zero IF Mode */ { + if (state->Mode == 0 && state->IF_Mode == 0) { + /* Analog Zero IF Mode */ status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0); status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 40); status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 27); - status += MXL_ControlWrite(fe, CHCAL_FRAC_MOD_RF, 206438); + status += MXL_ControlWrite(fe, + CHCAL_FRAC_MOD_RF, 206438); } if (state->Mode == 1) /* Digital Mode */ { status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0); status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 40); status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 27); - status += MXL_ControlWrite(fe, CHCAL_FRAC_MOD_RF, 212992); + status += MXL_ControlWrite(fe, + CHCAL_FRAC_MOD_RF, 212992); } } @@ -4442,7 +3996,7 @@ static int mxl5005s_writereg(struct dvb_frontend *fe, u8 reg, u8 val, int latch) if (latch == 0) msg.len = 2; - dprintk(2, "%s(reg = 0x%x val = 0x%x addr = 0x%x)\n", __func__, reg, val, msg.addr); + dprintk(2, "%s(0x%x, 0x%x, 0x%x)\n", __func__, reg, val, msg.addr); if (i2c_transfer(state->i2c, &msg, 1) != 1) { printk(KERN_WARNING "mxl5005s I2C write failed\n"); @@ -4451,7 +4005,8 @@ static int mxl5005s_writereg(struct dvb_frontend *fe, u8 reg, u8 val, int latch) return 0; } -int mxl5005s_writeregs(struct dvb_frontend *fe, u8 *addrtable, u8 *datatable, u8 len) +int mxl5005s_writeregs(struct dvb_frontend *fe, u8 *addrtable, u8 *datatable, + u8 len) { int ret = 0, i; @@ -4508,7 +4063,8 @@ int mxl5005s_reconfigure(struct dvb_frontend *fe, u32 mod_type, u32 bandwidth) return 0; } -int mxl5005s_AssignTunerMode(struct dvb_frontend *fe, u32 mod_type, u32 bandwidth) +int mxl5005s_AssignTunerMode(struct dvb_frontend *fe, u32 mod_type, + u32 bandwidth) { struct mxl5005s_state *state = fe->tuner_priv; struct mxl5005s_config *c = state->config; @@ -4555,8 +4111,8 @@ static int mxl5005s_set_params(struct dvb_frontend *fe, case QAM_AUTO: req_mode = MXL_QAM; break; } - } - else req_mode = MXL_DVBT; + } else + req_mode = MXL_DVBT; /* Change tuner for new modulation type if reqd */ if (req_mode != state->current_mode) { @@ -4657,9 +4213,11 @@ struct dvb_frontend *mxl5005s_attach(struct dvb_frontend *fe, state->i2c = i2c; state->current_mode = MXL_QAM; - printk(KERN_INFO "MXL5005S: Attached at address 0x%02x\n", config->i2c_address); + printk(KERN_INFO "MXL5005S: Attached at address 0x%02x\n", + config->i2c_address); - memcpy(&fe->ops.tuner_ops, &mxl5005s_tuner_ops, sizeof(struct dvb_tuner_ops)); + memcpy(&fe->ops.tuner_ops, &mxl5005s_tuner_ops, + sizeof(struct dvb_tuner_ops)); fe->tuner_priv = state; return fe; diff --git a/linux/drivers/media/common/tuners/mxl5005s.h b/linux/drivers/media/common/tuners/mxl5005s.h index 687cf146c..0027d1e03 100644 --- a/linux/drivers/media/common/tuners/mxl5005s.h +++ b/linux/drivers/media/common/tuners/mxl5005s.h @@ -25,8 +25,8 @@ #include -struct mxl5005s_config -{ +struct mxl5005s_config { + /* 7 bit i2c address */ u8 i2c_address; -- cgit v1.2.3 From b8d73d6737650979dbfc9ed8c6ebee9952db932d Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Sat, 3 May 2008 09:51:11 -0400 Subject: mxl5005s: Fix header includes. From: Steven Toth Ensure we have the correct .h dependencies included. Signed-off-by: Steven Toth Signed-off-by: Mauro Carvalho Chehab --- linux/drivers/media/common/tuners/mxl5005s.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'linux/drivers/media/common/tuners') diff --git a/linux/drivers/media/common/tuners/mxl5005s.h b/linux/drivers/media/common/tuners/mxl5005s.h index 0027d1e03..396db150b 100644 --- a/linux/drivers/media/common/tuners/mxl5005s.h +++ b/linux/drivers/media/common/tuners/mxl5005s.h @@ -23,7 +23,8 @@ #ifndef __MXL5005S_H #define __MXL5005S_H -#include +#include +#include "dvb_frontend.h" struct mxl5005s_config { -- cgit v1.2.3 From 6b4d6032e18b6f7a97862e432b47106ffd5de1d6 Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Sat, 3 May 2008 10:14:54 -0400 Subject: mxl5005s: Fix function statics From: Steven Toth Fix function statics Signed-off-by: Steven Toth Signed-off-by: Mauro Carvalho Chehab --- linux/drivers/media/common/tuners/mxl5005s.c | 121 ++++++++++++++------------- 1 file changed, 62 insertions(+), 59 deletions(-) (limited to 'linux/drivers/media/common/tuners') diff --git a/linux/drivers/media/common/tuners/mxl5005s.c b/linux/drivers/media/common/tuners/mxl5005s.c index 18a976c7e..bce141862 100644 --- a/linux/drivers/media/common/tuners/mxl5005s.c +++ b/linux/drivers/media/common/tuners/mxl5005s.c @@ -295,32 +295,34 @@ struct mxl5005s_state { }; -u16 MXL_ControlWrite(struct dvb_frontend *fe, u16 ControlNum, u32 value); -u16 MXL_ControlRead(struct dvb_frontend *fe, u16 controlNum, u32 *value); -u16 MXL_GetMasterControl(u8 *MasterReg, int state); -void MXL_RegWriteBit(struct dvb_frontend *fe, u8 address, u8 bit, u8 bitVal); -u16 MXL_GetCHRegister(struct dvb_frontend *fe, u8 *RegNum, +static u16 MXL_GetMasterControl(u8 *MasterReg, int state); +static u16 MXL_ControlWrite(struct dvb_frontend *fe, u16 ControlNum, u32 value); +static u16 MXL_ControlRead(struct dvb_frontend *fe, u16 controlNum, u32 *value); +static void MXL_RegWriteBit(struct dvb_frontend *fe, u8 address, u8 bit, + u8 bitVal); +static u16 MXL_GetCHRegister(struct dvb_frontend *fe, u8 *RegNum, u8 *RegVal, int *count); -u32 MXL_Ceiling(u32 value, u32 resolution); -u16 MXL_RegRead(struct dvb_frontend *fe, u8 RegNum, u8 *RegVal); -u16 MXL_RegWrite(struct dvb_frontend *fe, u8 RegNum, u8 RegVal); -u16 MXL_ControlWrite_Group(struct dvb_frontend *fe, u16 controlNum, +static u32 MXL_Ceiling(u32 value, u32 resolution); +static u16 MXL_RegRead(struct dvb_frontend *fe, u8 RegNum, u8 *RegVal); +static u16 MXL_RegWrite(struct dvb_frontend *fe, u8 RegNum, u8 RegVal); +static u16 MXL_ControlWrite_Group(struct dvb_frontend *fe, u16 controlNum, u32 value, u16 controlGroup); -u16 MXL_SetGPIO(struct dvb_frontend *fe, u8 GPIO_Num, u8 GPIO_Val); -u16 MXL_GetInitRegister(struct dvb_frontend *fe, u8 *RegNum, +static u16 MXL_SetGPIO(struct dvb_frontend *fe, u8 GPIO_Num, u8 GPIO_Val); +static u16 MXL_GetInitRegister(struct dvb_frontend *fe, u8 *RegNum, u8 *RegVal, int *count); -u32 MXL_GetXtalInt(u32 Xtal_Freq); -u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq); -void MXL_SynthIFLO_Calc(struct dvb_frontend *fe); -void MXL_SynthRFTGLO_Calc(struct dvb_frontend *fe); -u16 MXL_GetCHRegister_ZeroIF(struct dvb_frontend *fe, u8 *RegNum, +static u32 MXL_GetXtalInt(u32 Xtal_Freq); +static u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq); +static void MXL_SynthIFLO_Calc(struct dvb_frontend *fe); +static void MXL_SynthRFTGLO_Calc(struct dvb_frontend *fe); +static u16 MXL_GetCHRegister_ZeroIF(struct dvb_frontend *fe, u8 *RegNum, u8 *RegVal, int *count); -int mxl5005s_writeregs(struct dvb_frontend *fe, u8 *addrtable, +static int mxl5005s_writeregs(struct dvb_frontend *fe, u8 *addrtable, u8 *datatable, u8 len); -u16 MXL_IFSynthInit(struct dvb_frontend *fe); -int mxl5005s_AssignTunerMode(struct dvb_frontend *fe, u32 mod_type, +static u16 MXL_IFSynthInit(struct dvb_frontend *fe); +static int mxl5005s_AssignTunerMode(struct dvb_frontend *fe, u32 mod_type, + u32 bandwidth); +static int mxl5005s_reconfigure(struct dvb_frontend *fe, u32 mod_type, u32 bandwidth); -int mxl5005s_reconfigure(struct dvb_frontend *fe, u32 mod_type, u32 bandwidth); /* ---------------------------------------------------------------- * Begin: Custom code salvaged from the Realtek driver. @@ -334,14 +336,14 @@ int mxl5005s_reconfigure(struct dvb_frontend *fe, u32 mod_type, u32 bandwidth); * Revision: 080314 - original version */ -int mxl5005s_SetRfFreqHz(struct dvb_frontend *fe, unsigned long RfFreqHz) +static int mxl5005s_SetRfFreqHz(struct dvb_frontend *fe, unsigned long RfFreqHz) { struct mxl5005s_state *state = fe->tuner_priv; unsigned char AddrTable[MXL5005S_REG_WRITING_TABLE_LEN_MAX]; unsigned char ByteTable[MXL5005S_REG_WRITING_TABLE_LEN_MAX]; int TableLen; - u32 IfDivval; + u32 IfDivval = 0; unsigned char MasterControlByte; dprintk(1, "%s() freq=%ld\n", __func__, RfFreqHz); @@ -399,7 +401,7 @@ int mxl5005s_SetRfFreqHz(struct dvb_frontend *fe, unsigned long RfFreqHz) * Begin: Reference driver code found in the Realtek driver. * Copyright (c) 2008 MaxLinear */ -u16 MXL5005_RegisterInit(struct dvb_frontend *fe) +static u16 MXL5005_RegisterInit(struct dvb_frontend *fe) { struct mxl5005s_state *state = fe->tuner_priv; state->TunerRegs_Num = TUNER_REGS_NUM ; @@ -719,7 +721,7 @@ u16 MXL5005_RegisterInit(struct dvb_frontend *fe) return 0 ; } -u16 MXL5005_ControlInit(struct dvb_frontend *fe) +static u16 MXL5005_ControlInit(struct dvb_frontend *fe) { struct mxl5005s_state *state = fe->tuner_priv; state->Init_Ctrl_Num = INITCTRL_NUM; @@ -1659,7 +1661,7 @@ u16 MXL5005_ControlInit(struct dvb_frontend *fe) return 0 ; } -void InitTunerControls(struct dvb_frontend *fe) +static void InitTunerControls(struct dvb_frontend *fe) { MXL5005_RegisterInit(fe); MXL5005_ControlInit(fe); @@ -1668,7 +1670,7 @@ void InitTunerControls(struct dvb_frontend *fe) #endif } -u16 MXL5005_TunerConfig(struct dvb_frontend *fe, +static u16 MXL5005_TunerConfig(struct dvb_frontend *fe, u8 Mode, /* 0: Analog Mode ; 1: Digital Mode */ u8 IF_mode, /* for Analog Mode, 0: zero IF; 1: low IF */ u32 Bandwidth, /* filter channel bandwidth (6, 7, 8) */ @@ -1718,7 +1720,7 @@ u16 MXL5005_TunerConfig(struct dvb_frontend *fe, return status; } -void MXL_SynthIFLO_Calc(struct dvb_frontend *fe) +static void MXL_SynthIFLO_Calc(struct dvb_frontend *fe) { struct mxl5005s_state *state = fe->tuner_priv; if (state->Mode == 1) /* Digital Mode */ @@ -1731,7 +1733,7 @@ void MXL_SynthIFLO_Calc(struct dvb_frontend *fe) } } -void MXL_SynthRFTGLO_Calc(struct dvb_frontend *fe) +static void MXL_SynthRFTGLO_Calc(struct dvb_frontend *fe) { struct mxl5005s_state *state = fe->tuner_priv; @@ -1752,7 +1754,7 @@ void MXL_SynthRFTGLO_Calc(struct dvb_frontend *fe) } } -u16 MXL_OverwriteICDefault(struct dvb_frontend *fe) +static u16 MXL_OverwriteICDefault(struct dvb_frontend *fe) { u16 status = 0; @@ -1764,7 +1766,7 @@ u16 MXL_OverwriteICDefault(struct dvb_frontend *fe) return status; } -u16 MXL_BlockInit(struct dvb_frontend *fe) +static u16 MXL_BlockInit(struct dvb_frontend *fe) { struct mxl5005s_state *state = fe->tuner_priv; u16 status = 0; @@ -2104,7 +2106,7 @@ u16 MXL_BlockInit(struct dvb_frontend *fe) return status; } -u16 MXL_IFSynthInit(struct dvb_frontend *fe) +static u16 MXL_IFSynthInit(struct dvb_frontend *fe) { struct mxl5005s_state *state = fe->tuner_priv; u16 status = 0 ; @@ -2308,7 +2310,7 @@ u16 MXL_IFSynthInit(struct dvb_frontend *fe) return status ; } -u32 MXL_GetXtalInt(u32 Xtal_Freq) +static u32 MXL_GetXtalInt(u32 Xtal_Freq) { if ((Xtal_Freq % 1000000) == 0) return (Xtal_Freq / 10000); @@ -2316,7 +2318,7 @@ u32 MXL_GetXtalInt(u32 Xtal_Freq) return (((Xtal_Freq / 1000000) + 1)*100); } -u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq) +static u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq) { struct mxl5005s_state *state = fe->tuner_priv; u16 status = 0; @@ -3356,7 +3358,7 @@ u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq) return status ; } -u16 MXL_SetGPIO(struct dvb_frontend *fe, u8 GPIO_Num, u8 GPIO_Val) +static u16 MXL_SetGPIO(struct dvb_frontend *fe, u8 GPIO_Num, u8 GPIO_Val) { u16 status = 0; @@ -3397,7 +3399,7 @@ u16 MXL_SetGPIO(struct dvb_frontend *fe, u8 GPIO_Num, u8 GPIO_Val) return status; } -u16 MXL_ControlWrite(struct dvb_frontend *fe, u16 ControlNum, u32 value) +static u16 MXL_ControlWrite(struct dvb_frontend *fe, u16 ControlNum, u32 value) { u16 status = 0; @@ -3413,8 +3415,8 @@ u16 MXL_ControlWrite(struct dvb_frontend *fe, u16 ControlNum, u32 value) return status; } -u16 MXL_ControlWrite_Group(struct dvb_frontend *fe, u16 controlNum, u32 value, - u16 controlGroup) +static u16 MXL_ControlWrite_Group(struct dvb_frontend *fe, u16 controlNum, + u32 value, u16 controlGroup) { struct mxl5005s_state *state = fe->tuner_priv; u16 i, j, k; @@ -3492,7 +3494,7 @@ u16 MXL_ControlWrite_Group(struct dvb_frontend *fe, u16 controlNum, u32 value, return 0 ; /* successful return */ } -u16 MXL_RegWrite(struct dvb_frontend *fe, u8 RegNum, u8 RegVal) +static u16 MXL_RegWrite(struct dvb_frontend *fe, u8 RegNum, u8 RegVal) { struct mxl5005s_state *state = fe->tuner_priv; int i ; @@ -3507,7 +3509,7 @@ u16 MXL_RegWrite(struct dvb_frontend *fe, u8 RegNum, u8 RegVal) return 1; } -u16 MXL_RegRead(struct dvb_frontend *fe, u8 RegNum, u8 *RegVal) +static u16 MXL_RegRead(struct dvb_frontend *fe, u8 RegNum, u8 *RegVal) { struct mxl5005s_state *state = fe->tuner_priv; int i ; @@ -3522,7 +3524,7 @@ u16 MXL_RegRead(struct dvb_frontend *fe, u8 RegNum, u8 *RegVal) return 1; } -u16 MXL_ControlRead(struct dvb_frontend *fe, u16 controlNum, u32 *value) +static u16 MXL_ControlRead(struct dvb_frontend *fe, u16 controlNum, u32 *value) { struct mxl5005s_state *state = fe->tuner_priv; u32 ctrlVal ; @@ -3570,8 +3572,8 @@ u16 MXL_ControlRead(struct dvb_frontend *fe, u16 controlNum, u32 *value) return 1; } -u16 MXL_ControlRegRead(struct dvb_frontend *fe, u16 controlNum, u8 *RegNum, - int *count) +static u16 MXL_ControlRegRead(struct dvb_frontend *fe, u16 controlNum, + u8 *RegNum, int *count) { struct mxl5005s_state *state = fe->tuner_priv; u16 i, j, k ; @@ -3656,7 +3658,8 @@ u16 MXL_ControlRegRead(struct dvb_frontend *fe, u16 controlNum, u8 *RegNum, return 1; } -void MXL_RegWriteBit(struct dvb_frontend *fe, u8 address, u8 bit, u8 bitVal) +static void MXL_RegWriteBit(struct dvb_frontend *fe, u8 address, u8 bit, + u8 bitVal) { struct mxl5005s_state *state = fe->tuner_priv; int i ; @@ -3680,13 +3683,13 @@ void MXL_RegWriteBit(struct dvb_frontend *fe, u8 address, u8 bit, u8 bitVal) } } -u32 MXL_Ceiling(u32 value, u32 resolution) +static u32 MXL_Ceiling(u32 value, u32 resolution) { return (value/resolution + (value % resolution > 0 ? 1 : 0)); } /* Retrieve the Initialzation Registers */ -u16 MXL_GetInitRegister(struct dvb_frontend *fe, u8 *RegNum, +static u16 MXL_GetInitRegister(struct dvb_frontend *fe, u8 *RegNum, u8 *RegVal, int *count) { u16 status = 0; @@ -3709,7 +3712,7 @@ u16 MXL_GetInitRegister(struct dvb_frontend *fe, u8 *RegNum, return status; } -u16 MXL_GetCHRegister(struct dvb_frontend *fe, u8 *RegNum, u8 *RegVal, +static u16 MXL_GetCHRegister(struct dvb_frontend *fe, u8 *RegNum, u8 *RegVal, int *count) { u16 status = 0; @@ -3739,8 +3742,8 @@ u16 MXL_GetCHRegister(struct dvb_frontend *fe, u8 *RegNum, u8 *RegVal, return status; } -u16 MXL_GetCHRegister_ZeroIF(struct dvb_frontend *fe, u8 *RegNum, u8 *RegVal, - int *count) +static u16 MXL_GetCHRegister_ZeroIF(struct dvb_frontend *fe, u8 *RegNum, + u8 *RegVal, int *count) { u16 status = 0; int i; @@ -3757,8 +3760,8 @@ u16 MXL_GetCHRegister_ZeroIF(struct dvb_frontend *fe, u8 *RegNum, u8 *RegVal, return status; } -u16 MXL_GetCHRegister_LowIF(struct dvb_frontend *fe, u8 *RegNum, u8 *RegVal, - int *count) +static u16 MXL_GetCHRegister_LowIF(struct dvb_frontend *fe, u8 *RegNum, + u8 *RegVal, int *count) { u16 status = 0; int i; @@ -3775,7 +3778,7 @@ u16 MXL_GetCHRegister_LowIF(struct dvb_frontend *fe, u8 *RegNum, u8 *RegVal, return status; } -u16 MXL_GetMasterControl(u8 *MasterReg, int state) +static u16 MXL_GetMasterControl(u8 *MasterReg, int state) { if (state == 1) /* Load_Start */ *MasterReg = 0xF3; @@ -3790,7 +3793,7 @@ u16 MXL_GetMasterControl(u8 *MasterReg, int state) } #ifdef _MXL_PRODUCTION -u16 MXL_VCORange_Test(struct dvb_frontend *fe, int VCO_Range) +static u16 MXL_VCORange_Test(struct dvb_frontend *fe, int VCO_Range) { struct mxl5005s_state *state = fe->tuner_priv; u16 status = 0 ; @@ -3939,7 +3942,7 @@ u16 MXL_VCORange_Test(struct dvb_frontend *fe, int VCO_Range) return status; } -u16 MXL_Hystersis_Test(struct dvb_frontend *fe, int Hystersis) +static u16 MXL_Hystersis_Test(struct dvb_frontend *fe, int Hystersis) { struct mxl5005s_state *state = fe->tuner_priv; u16 status = 0; @@ -4005,8 +4008,8 @@ static int mxl5005s_writereg(struct dvb_frontend *fe, u8 reg, u8 val, int latch) return 0; } -int mxl5005s_writeregs(struct dvb_frontend *fe, u8 *addrtable, u8 *datatable, - u8 len) +static int mxl5005s_writeregs(struct dvb_frontend *fe, u8 *addrtable, + u8 *datatable, u8 len) { int ret = 0, i; @@ -4027,14 +4030,14 @@ int mxl5005s_writeregs(struct dvb_frontend *fe, u8 *addrtable, u8 *datatable, return ret; } - -int mxl5005s_init(struct dvb_frontend *fe) +static int mxl5005s_init(struct dvb_frontend *fe) { dprintk(1, "%s()\n", __func__); return mxl5005s_reconfigure(fe, MXL_QAM, MXL5005S_BANDWIDTH_6MHZ); } -int mxl5005s_reconfigure(struct dvb_frontend *fe, u32 mod_type, u32 bandwidth) +static int mxl5005s_reconfigure(struct dvb_frontend *fe, u32 mod_type, + u32 bandwidth) { struct mxl5005s_state *state = fe->tuner_priv; @@ -4063,7 +4066,7 @@ int mxl5005s_reconfigure(struct dvb_frontend *fe, u32 mod_type, u32 bandwidth) return 0; } -int mxl5005s_AssignTunerMode(struct dvb_frontend *fe, u32 mod_type, +static int mxl5005s_AssignTunerMode(struct dvb_frontend *fe, u32 mod_type, u32 bandwidth) { struct mxl5005s_state *state = fe->tuner_priv; -- cgit v1.2.3 From 885d32a75adfdc848933fff632f459476bf302d6 Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Sat, 3 May 2008 10:21:58 -0400 Subject: mxl5005s: Remove redundant functions From: Steven Toth Remove redundant functions Signed-off-by: Steven Toth Signed-off-by: Mauro Carvalho Chehab --- linux/drivers/media/common/tuners/mxl5005s.c | 120 --------------------------- 1 file changed, 120 deletions(-) (limited to 'linux/drivers/media/common/tuners') diff --git a/linux/drivers/media/common/tuners/mxl5005s.c b/linux/drivers/media/common/tuners/mxl5005s.c index bce141862..2e5c2e434 100644 --- a/linux/drivers/media/common/tuners/mxl5005s.c +++ b/linux/drivers/media/common/tuners/mxl5005s.c @@ -304,7 +304,6 @@ static u16 MXL_GetCHRegister(struct dvb_frontend *fe, u8 *RegNum, u8 *RegVal, int *count); static u32 MXL_Ceiling(u32 value, u32 resolution); static u16 MXL_RegRead(struct dvb_frontend *fe, u8 RegNum, u8 *RegVal); -static u16 MXL_RegWrite(struct dvb_frontend *fe, u8 RegNum, u8 RegVal); static u16 MXL_ControlWrite_Group(struct dvb_frontend *fe, u16 controlNum, u32 value, u16 controlGroup); static u16 MXL_SetGPIO(struct dvb_frontend *fe, u8 GPIO_Num, u8 GPIO_Val); @@ -3494,21 +3493,6 @@ static u16 MXL_ControlWrite_Group(struct dvb_frontend *fe, u16 controlNum, return 0 ; /* successful return */ } -static u16 MXL_RegWrite(struct dvb_frontend *fe, u8 RegNum, u8 RegVal) -{ - struct mxl5005s_state *state = fe->tuner_priv; - int i ; - - for (i = 0; i < 104; i++) { - if (RegNum == state->TunerRegs[i].Reg_Num) { - state->TunerRegs[i].Reg_Val = RegVal; - return 0; - } - } - - return 1; -} - static u16 MXL_RegRead(struct dvb_frontend *fe, u8 RegNum, u8 *RegVal) { struct mxl5005s_state *state = fe->tuner_priv; @@ -3572,92 +3556,6 @@ static u16 MXL_ControlRead(struct dvb_frontend *fe, u16 controlNum, u32 *value) return 1; } -static u16 MXL_ControlRegRead(struct dvb_frontend *fe, u16 controlNum, - u8 *RegNum, int *count) -{ - struct mxl5005s_state *state = fe->tuner_priv; - u16 i, j, k ; - u16 Count ; - - for (i = 0; i < state->Init_Ctrl_Num ; i++) { - - if (controlNum == state->Init_Ctrl[i].Ctrl_Num) { - - Count = 1; - RegNum[0] = (u8)(state->Init_Ctrl[i].addr[0]); - - for (k = 1; k < state->Init_Ctrl[i].size; k++) { - - for (j = 0; j < Count; j++) { - - if (state->Init_Ctrl[i].addr[k] != - RegNum[j]) { - - Count++; - RegNum[Count-1] = (u8)(state->Init_Ctrl[i].addr[k]); - - } - } - - } - *count = Count; - return 0; - } - } - for (i = 0; i < state->CH_Ctrl_Num ; i++) { - - if (controlNum == state->CH_Ctrl[i].Ctrl_Num) { - - Count = 1; - RegNum[0] = (u8)(state->CH_Ctrl[i].addr[0]); - - for (k = 1; k < state->CH_Ctrl[i].size; k++) { - - for (j = 0; j < Count; j++) { - - if (state->CH_Ctrl[i].addr[k] != - RegNum[j]) { - - Count++; - RegNum[Count-1] = (u8)(state->CH_Ctrl[i].addr[k]); - - } - } - } - *count = Count; - return 0; - } - } -#ifdef _MXL_INTERNAL - for (i = 0; i < state->MXL_Ctrl_Num ; i++) { - - if (controlNum == state->MXL_Ctrl[i].Ctrl_Num) { - - Count = 1; - RegNum[0] = (u8)(state->MXL_Ctrl[i].addr[0]); - - for (k = 1; k < state->MXL_Ctrl[i].size; k++) { - - for (j = 0; j < Count; j++) { - - if (state->MXL_Ctrl[i].addr[k] != - RegNum[j]) { - - Count++; - RegNum[Count-1] = (u8)state->MXL_Ctrl[i].addr[k]; - - } - } - } - *count = Count; - return 0; - } - } -#endif - *count = 0; - return 1; -} - static void MXL_RegWriteBit(struct dvb_frontend *fe, u8 address, u8 bit, u8 bitVal) { @@ -3760,24 +3658,6 @@ static u16 MXL_GetCHRegister_ZeroIF(struct dvb_frontend *fe, u8 *RegNum, return status; } -static u16 MXL_GetCHRegister_LowIF(struct dvb_frontend *fe, u8 *RegNum, - u8 *RegVal, int *count) -{ - u16 status = 0; - int i; - - u8 RegAddr[] = { 138 }; - - *count = sizeof(RegAddr) / sizeof(u8); - - for (i = 0; i < *count; i++) { - RegNum[i] = RegAddr[i]; - status += MXL_RegRead(fe, RegNum[i], &RegVal[i]); - } - - return status; -} - static u16 MXL_GetMasterControl(u8 *MasterReg, int state) { if (state == 1) /* Load_Start */ -- cgit v1.2.3 From 87f7eb75a313b5ee8deece78b8ae72ab3f9ef771 Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Sat, 3 May 2008 10:25:55 -0400 Subject: mxl5005s: Remove incorrect copyright holders From: Steven Toth I was informed by Jan Hoogenraad that two people needed to be removed from the original copyright comments. Signed-off-by: Steven Toth Signed-off-by: Mauro Carvalho Chehab --- linux/drivers/media/common/tuners/mxl5005s.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) (limited to 'linux/drivers/media/common/tuners') diff --git a/linux/drivers/media/common/tuners/mxl5005s.c b/linux/drivers/media/common/tuners/mxl5005s.c index 2e5c2e434..fddf17cc7 100644 --- a/linux/drivers/media/common/tuners/mxl5005s.c +++ b/linux/drivers/media/common/tuners/mxl5005s.c @@ -16,8 +16,8 @@ mxl5005s_release() mxl5005s_attach() - Copyright (c) 2008 Realtek - Copyright (c) 2008 Jan Hoogenraad, Barnaby Shearer, Andy Hasper + Copyright (C) 2008 Realtek + Copyright (C) 2008 Jan Hoogenraad Functions: mxl5005s_SetRfFreqHz() @@ -325,8 +325,8 @@ static int mxl5005s_reconfigure(struct dvb_frontend *fe, u32 mod_type, /* ---------------------------------------------------------------- * Begin: Custom code salvaged from the Realtek driver. - * Copyright (c) 2008 Realtek - * Copyright (c) 2008 Jan Hoogenraad, Barnaby Shearer, Andy Hasper + * Copyright (C) 2008 Realtek + * Copyright (C) 2008 Jan Hoogenraad * This code is placed under the terms of the GNU General Public License * * Released by Realtek under GPLv2. @@ -398,7 +398,7 @@ static int mxl5005s_SetRfFreqHz(struct dvb_frontend *fe, unsigned long RfFreqHz) /* ---------------------------------------------------------------- * Begin: Reference driver code found in the Realtek driver. - * Copyright (c) 2008 MaxLinear + * Copyright (C) 2008 MaxLinear */ static u16 MXL5005_RegisterInit(struct dvb_frontend *fe) { -- cgit v1.2.3 From eddc1be9cda6dccc5fe0b5f129d1d69e254ea309 Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Sat, 3 May 2008 10:28:43 -0400 Subject: mxl5005s: Ensure debug is off From: Steven Toth Ensure debug is off Signed-off-by: Steven Toth Signed-off-by: Mauro Carvalho Chehab --- linux/drivers/media/common/tuners/mxl5005s.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'linux/drivers/media/common/tuners') diff --git a/linux/drivers/media/common/tuners/mxl5005s.c b/linux/drivers/media/common/tuners/mxl5005s.c index fddf17cc7..961a8af08 100644 --- a/linux/drivers/media/common/tuners/mxl5005s.c +++ b/linux/drivers/media/common/tuners/mxl5005s.c @@ -66,7 +66,7 @@ #include "dvb_frontend.h" #include "mxl5005s.h" -static int debug = 2; +static int debug; #define dprintk(level, arg...) do { \ if (level <= debug) \ -- cgit v1.2.3 From 6ee8bd891628a89e27f84d23a7ce4c94e8bda064 Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Thu, 8 May 2008 09:14:40 -0300 Subject: mxl55005s: Makefile and Kconfig additions From: Steven Toth Makefile and Kconfig additions Signed-off-by: Steven Toth Signed-off-by: Mauro Carvalho Chehab --- linux/drivers/media/common/tuners/Kconfig | 7 +++++++ linux/drivers/media/common/tuners/Makefile | 1 + 2 files changed, 8 insertions(+) (limited to 'linux/drivers/media/common/tuners') diff --git a/linux/drivers/media/common/tuners/Kconfig b/linux/drivers/media/common/tuners/Kconfig index 10f12bad1..394cb050b 100644 --- a/linux/drivers/media/common/tuners/Kconfig +++ b/linux/drivers/media/common/tuners/Kconfig @@ -139,4 +139,11 @@ config MEDIA_TUNER_XC5000 This device is only used inside a SiP called togther with a demodulator for now. +config MEDIA_TUNER_MXL5005S + tristate "MaxLinear MSL5005S silicon tuner" + depends on I2C + default m if DVB_FE_CUSTOMISE + help + A driver for the silicon tuner MXL5005S from MaxLinear. + endif # MEDIA_TUNER_CUSTOMIZE diff --git a/linux/drivers/media/common/tuners/Makefile b/linux/drivers/media/common/tuners/Makefile index 236d9932f..55f7e6706 100644 --- a/linux/drivers/media/common/tuners/Makefile +++ b/linux/drivers/media/common/tuners/Makefile @@ -20,6 +20,7 @@ obj-$(CONFIG_MEDIA_TUNER_MT2060) += mt2060.o obj-$(CONFIG_MEDIA_TUNER_MT2266) += mt2266.o obj-$(CONFIG_MEDIA_TUNER_QT1010) += qt1010.o obj-$(CONFIG_MEDIA_TUNER_MT2131) += mt2131.o +obj-$(CONFIG_MEDIA_TUNER_MXL5005S) += mxl5005s.o EXTRA_CFLAGS += -Idrivers/media/dvb/dvb-core EXTRA_CFLAGS += -Idrivers/media/dvb/frontends -- cgit v1.2.3 From 4969b6d8d0847eb8f756b4424f6eef2f2fe85677 Mon Sep 17 00:00:00 2001 From: Michael Krufky Date: Sat, 10 May 2008 10:34:09 -0400 Subject: xc5000: bug-fix: allow multiple devices in a single system From: Michael Krufky The current code passes a context pointer in the xc5000_config struct. This context pointer is used in the tuner_callback function, used to reset the device after firmware download. The xc5000_config struct is a static structure, whose .priv member was being assigned before calling xc5000_attach(). If there are more than one of the same device type installed on a single system, the last one to assign xc5000_config.priv will "win", and all others will cease to function properly. This patch passes the context pointer in xc5000_attach() rather that storing it within the static struct xc5000_config. Signed-off-by: Michael Krufky --- linux/drivers/media/common/tuners/xc5000.c | 9 +++++---- linux/drivers/media/common/tuners/xc5000.h | 22 ++++++++++++---------- linux/drivers/media/common/tuners/xc5000_priv.h | 2 ++ 3 files changed, 19 insertions(+), 14 deletions(-) (limited to 'linux/drivers/media/common/tuners') diff --git a/linux/drivers/media/common/tuners/xc5000.c b/linux/drivers/media/common/tuners/xc5000.c index c832f39ab..b35640824 100644 --- a/linux/drivers/media/common/tuners/xc5000.c +++ b/linux/drivers/media/common/tuners/xc5000.c @@ -212,7 +212,7 @@ static void xc5000_TunerReset(struct dvb_frontend *fe) dprintk(1, "%s()\n", __func__); if (priv->cfg->tuner_callback) { - ret = priv->cfg->tuner_callback(priv->cfg->priv, + ret = priv->cfg->tuner_callback(priv->devptr, XC5000_TUNER_RESET, 0); if (ret) printk(KERN_ERR "xc5000: reset failed\n"); @@ -919,9 +919,9 @@ static const struct dvb_tuner_ops xc5000_tuner_ops = { .get_status = xc5000_get_status }; -struct dvb_frontend * xc5000_attach(struct dvb_frontend *fe, - struct i2c_adapter *i2c, - struct xc5000_config *cfg) +struct dvb_frontend *xc5000_attach(struct dvb_frontend *fe, + struct i2c_adapter *i2c, + struct xc5000_config *cfg, void *devptr) { struct xc5000_priv *priv = NULL; u16 id = 0; @@ -935,6 +935,7 @@ struct dvb_frontend * xc5000_attach(struct dvb_frontend *fe, priv->cfg = cfg; priv->bandwidth = BANDWIDTH_6_MHZ; priv->i2c = i2c; + priv->devptr = devptr; /* Check if firmware has been loaded. It is possible that another instance of the driver has loaded the firmware. diff --git a/linux/drivers/media/common/tuners/xc5000.h b/linux/drivers/media/common/tuners/xc5000.h index 0ee80f9d1..c910715ad 100644 --- a/linux/drivers/media/common/tuners/xc5000.h +++ b/linux/drivers/media/common/tuners/xc5000.h @@ -31,29 +31,31 @@ struct xc5000_config { u8 i2c_address; u32 if_khz; - /* For each bridge framework, when it attaches either analog or digital, - * it has to store a reference back to its _core equivalent structure, - * so that it can service the hardware by steering gpio's etc. - * Each bridge implementation is different so cast priv accordingly. - * The xc5000 driver cares not for this value, other than ensuring - * it's passed back to a bridge during tuner_callback(). - */ - void *priv; int (*tuner_callback) (void *priv, int command, int arg); }; /* xc5000 callback command */ #define XC5000_TUNER_RESET 0 +/* For each bridge framework, when it attaches either analog or digital, + * it has to store a reference back to its _core equivalent structure, + * so that it can service the hardware by steering gpio's etc. + * Each bridge implementation is different so cast devptr accordingly. + * The xc5000 driver cares not for this value, other than ensuring + * it's passed back to a bridge during tuner_callback(). + */ + #if defined(CONFIG_MEDIA_TUNER_XC5000) || \ (defined(CONFIG_MEDIA_TUNER_XC5000_MODULE) && defined(MODULE)) extern struct dvb_frontend* xc5000_attach(struct dvb_frontend *fe, struct i2c_adapter *i2c, - struct xc5000_config *cfg); + struct xc5000_config *cfg, + void *devptr); #else static inline struct dvb_frontend* xc5000_attach(struct dvb_frontend *fe, struct i2c_adapter *i2c, - struct xc5000_config *cfg) + struct xc5000_config *cfg, + void *devptr) { printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__); return NULL; diff --git a/linux/drivers/media/common/tuners/xc5000_priv.h b/linux/drivers/media/common/tuners/xc5000_priv.h index 13b2d1934..ecebfe474 100644 --- a/linux/drivers/media/common/tuners/xc5000_priv.h +++ b/linux/drivers/media/common/tuners/xc5000_priv.h @@ -31,6 +31,8 @@ struct xc5000_priv { u8 video_standard; u8 rf_mode; u8 fwloaded; + + void *devptr; }; #endif -- cgit v1.2.3 From 428a966f445b92d487c999aa2bd4e1f1c558ad7a Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Sun, 11 May 2008 19:51:07 +0000 Subject: fix handling of tea5761_autodetection return value From: Marcin Slusarz tea5761_autodetection returns -EINVAL on error Signed-off-by: Marcin Slusarz Signed-off-by: Mauro Carvalho Chehab --- linux/drivers/media/common/tuners/tea5761.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'linux/drivers/media/common/tuners') diff --git a/linux/drivers/media/common/tuners/tea5761.c b/linux/drivers/media/common/tuners/tea5761.c index 11e2991ef..f5fadcd4b 100644 --- a/linux/drivers/media/common/tuners/tea5761.c +++ b/linux/drivers/media/common/tuners/tea5761.c @@ -301,7 +301,7 @@ struct dvb_frontend *tea5761_attach(struct dvb_frontend *fe, { struct tea5761_priv *priv = NULL; - if (tea5761_autodetection(i2c_adap, i2c_addr) == EINVAL) + if (tea5761_autodetection(i2c_adap, i2c_addr) != 0) return NULL; priv = kzalloc(sizeof(struct tea5761_priv), GFP_KERNEL); -- cgit v1.2.3 From b5c02b090a0e7ba47eaef5eabe6480508adcb829 Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Wed, 14 May 2008 01:57:36 -0300 Subject: Fixes a few remaining Kbuild issues at common/tuners From: Mauro Carvalho Chehab - MEDIA_ATTACH now applies also for V4L; - select a FW_LOADER dependent driver should happen only if HOTPLUG; - apply the common tuner dependency to all tuners. This helps to avoid latter issues. Signed-off-by: Mauro Carvalho Chehab --- linux/drivers/media/common/tuners/Kconfig | 20 +++++++++++++++++--- 1 file changed, 17 insertions(+), 3 deletions(-) (limited to 'linux/drivers/media/common/tuners') diff --git a/linux/drivers/media/common/tuners/Kconfig b/linux/drivers/media/common/tuners/Kconfig index 394cb050b..d62065404 100644 --- a/linux/drivers/media/common/tuners/Kconfig +++ b/linux/drivers/media/common/tuners/Kconfig @@ -1,6 +1,6 @@ config MEDIA_ATTACH bool "Load and attach frontend and tuner driver modules as needed" - depends on DVB_CORE + depends on VIDEO_MEDIA depends on MODULES help Remove the static dependency of DVB card drivers on all @@ -22,7 +22,7 @@ config MEDIA_TUNER default VIDEO_MEDIA && I2C depends on VIDEO_MEDIA && I2C select MEDIA_TUNER_XC2028 if !MEDIA_TUNER_CUSTOMIZE && HOTPLUG - select MEDIA_TUNER_XC5000 if !MEDIA_TUNER_CUSTOMIZE + select MEDIA_TUNER_XC5000 if !MEDIA_TUNER_CUSTOMIZE && HOTPLUG select MEDIA_TUNER_MT20XX if !MEDIA_TUNER_CUSTOMIZE select MEDIA_TUNER_TDA8290 if !MEDIA_TUNER_CUSTOMIZE select MEDIA_TUNER_TEA5761 if !MEDIA_TUNER_CUSTOMIZE @@ -46,6 +46,7 @@ if MEDIA_TUNER_CUSTOMIZE config MEDIA_TUNER_SIMPLE tristate "Simple tuner support" + depends on VIDEO_MEDIA && I2C select MEDIA_TUNER_TDA9887 default m if MEDIA_TUNER_CUSTOMIZE help @@ -53,6 +54,7 @@ config MEDIA_TUNER_SIMPLE config MEDIA_TUNER_TDA8290 tristate "TDA 8290/8295 + 8275(a)/18271 tuner combo" + depends on VIDEO_MEDIA && I2C select MEDIA_TUNER_TDA827X select MEDIA_TUNER_TDA18271 default m if MEDIA_TUNER_CUSTOMIZE @@ -61,18 +63,21 @@ config MEDIA_TUNER_TDA8290 config MEDIA_TUNER_TDA827X tristate "Philips TDA827X silicon tuner" + depends on VIDEO_MEDIA && I2C default m if DVB_FE_CUSTOMISE help A DVB-T silicon tuner module. Say Y when you want to support this tuner. config MEDIA_TUNER_TDA18271 tristate "NXP TDA18271 silicon tuner" + depends on VIDEO_MEDIA && I2C default m if DVB_FE_CUSTOMISE help A silicon tuner module. Say Y when you want to support this tuner. config MEDIA_TUNER_TDA9887 tristate "TDA 9885/6/7 analog IF demodulator" + depends on VIDEO_MEDIA && I2C default m if MEDIA_TUNER_CUSTOMIZE help Say Y here to include support for Philips TDA9885/6/7 @@ -80,6 +85,7 @@ config MEDIA_TUNER_TDA9887 config MEDIA_TUNER_TEA5761 tristate "TEA 5761 radio tuner (EXPERIMENTAL)" + depends on VIDEO_MEDIA && I2C depends on EXPERIMENTAL default m if MEDIA_TUNER_CUSTOMIZE help @@ -87,42 +93,49 @@ config MEDIA_TUNER_TEA5761 config MEDIA_TUNER_TEA5767 tristate "TEA 5767 radio tuner" + depends on VIDEO_MEDIA && I2C default m if MEDIA_TUNER_CUSTOMIZE help Say Y here to include support for the Philips TEA5767 radio tuner. config MEDIA_TUNER_MT20XX tristate "Microtune 2032 / 2050 tuners" + depends on VIDEO_MEDIA && I2C default m if MEDIA_TUNER_CUSTOMIZE help Say Y here to include support for the MT2032 / MT2050 tuner. config MEDIA_TUNER_MT2060 tristate "Microtune MT2060 silicon IF tuner" + depends on VIDEO_MEDIA && I2C default m if DVB_FE_CUSTOMISE help A driver for the silicon IF tuner MT2060 from Microtune. config MEDIA_TUNER_MT2266 tristate "Microtune MT2266 silicon tuner" + depends on VIDEO_MEDIA && I2C default m if DVB_FE_CUSTOMISE help A driver for the silicon baseband tuner MT2266 from Microtune. config MEDIA_TUNER_MT2131 tristate "Microtune MT2131 silicon tuner" + depends on VIDEO_MEDIA && I2C default m if DVB_FE_CUSTOMISE help A driver for the silicon baseband tuner MT2131 from Microtune. config MEDIA_TUNER_QT1010 tristate "Quantek QT1010 silicon tuner" + depends on VIDEO_MEDIA && I2C default m if DVB_FE_CUSTOMISE help A driver for the silicon tuner QT1010 from Quantek. config MEDIA_TUNER_XC2028 tristate "XCeive xc2028/xc3028 tuners" + depends on VIDEO_MEDIA && I2C depends on HOTPLUG select FW_LOADER default m if MEDIA_TUNER_CUSTOMIZE @@ -131,6 +144,7 @@ config MEDIA_TUNER_XC2028 config MEDIA_TUNER_XC5000 tristate "Xceive XC5000 silicon tuner" + depends on VIDEO_MEDIA && I2C depends on HOTPLUG select FW_LOADER default m if DVB_FE_CUSTOMISE @@ -141,7 +155,7 @@ config MEDIA_TUNER_XC5000 config MEDIA_TUNER_MXL5005S tristate "MaxLinear MSL5005S silicon tuner" - depends on I2C + depends on VIDEO_MEDIA && I2C default m if DVB_FE_CUSTOMISE help A driver for the silicon tuner MXL5005S from MaxLinear. -- cgit v1.2.3 From 775ba6a274cfac356d94849e5f33cd937a581d02 Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Fri, 16 May 2008 00:15:53 +0000 Subject: tuners/mxl5005s.c: don't define variables for enums From: Adrian Bunk It doesn't seem to be intended that "tuner_modu_type" and "MXL5005_ControlName" were global variables. Signed-off-by: Adrian Bunk Signed-off-by: Mauro Carvalho Chehab --- linux/drivers/media/common/tuners/mxl5005s.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'linux/drivers/media/common/tuners') diff --git a/linux/drivers/media/common/tuners/mxl5005s.c b/linux/drivers/media/common/tuners/mxl5005s.c index 961a8af08..80f87c19f 100644 --- a/linux/drivers/media/common/tuners/mxl5005s.c +++ b/linux/drivers/media/common/tuners/mxl5005s.c @@ -101,7 +101,7 @@ enum { MXL_QAM, MXL_ANALOG_CABLE, MXL_ANALOG_OTA -} tuner_modu_type; +}; /* MXL5005 Tuner Register Struct */ struct TunerReg { @@ -194,7 +194,7 @@ enum { RFSYN_DIVM, /* 88 */ DN_BYPASS_AGC_I2C /* 89 */ #endif -} MXL5005_ControlName; +}; /* * The following context is source code provided by MaxLinear. -- cgit v1.2.3 From 7ac2a0cdca5bb0c9c31c2691c298becb8d777077 Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Mon, 26 May 2008 11:21:45 -0300 Subject: Backport some miscelaneous trivial fixes from mainstream From: Mauro Carvalho Chehab Summary of changes: linux/drivers/media/Makefile | 2 ++ linux/drivers/media/common/tuners/mxl5005s.c | 1 - linux/drivers/media/video/cx18/cx18-driver.c | 2 +- linux/drivers/media/video/saa7134/saa7134-video.c | 2 +- 4 files changed, 4 insertions(+), 3 deletions(-) Signed-off-by: Mauro Carvalho Chehab --- linux/drivers/media/common/tuners/mxl5005s.c | 1 - 1 file changed, 1 deletion(-) (limited to 'linux/drivers/media/common/tuners') diff --git a/linux/drivers/media/common/tuners/mxl5005s.c b/linux/drivers/media/common/tuners/mxl5005s.c index 80f87c19f..e356db855 100644 --- a/linux/drivers/media/common/tuners/mxl5005s.c +++ b/linux/drivers/media/common/tuners/mxl5005s.c @@ -4110,4 +4110,3 @@ EXPORT_SYMBOL(mxl5005s_attach); MODULE_DESCRIPTION("MaxLinear MXL5005S silicon tuner driver"); MODULE_AUTHOR("Steven Toth"); MODULE_LICENSE("GPL"); - -- cgit v1.2.3 From 272b8714337c3df423122eacc657451ebd0c1982 Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Tue, 20 May 2008 19:34:09 +0000 Subject: fix MEDIA_TUNER && FW_LOADER build error From: Ingo Molnar -tip testing found the following build failure: LD .tmp_vmlinux1 drivers/built-in.o: In function `generic_set_freq': tuner-xc2028.c:(.text+0xbd896): undefined reference to `request_firmware' tuner-xc2028.c:(.text+0xbdd7a): undefined reference to `release_firmware' drivers/built-in.o: In function `xc_load_fw_and_init_tuner': xc5000.c:(.text+0xc68e6): undefined reference to `request_firmware' xc5000.c:(.text+0xc6abe): undefined reference to `release_firmware' with this config: http://redhat.com/~mingo/misc/config-Tue_May_20_18_11_34_CEST_2008.bad the reason is another kconfig tool bug that has to be worked around in the driver's Kconfig file: if FW_LOADER is selected in a second dependency, that is not properly propagated up the dependencies. in this case, FW_LOADER is selected from MEDIA_TUNER_XC2028: config MEDIA_TUNER_XC2028 tristate "XCeive xc2028/xc3028 tuners" depends on VIDEO_MEDIA && I2C depends on HOTPLUG select FW_LOADER which got selected by MEDIA_TUNER: config MEDIA_TUNER tristate default VIDEO_MEDIA && I2C depends on VIDEO_MEDIA && I2C select FW_LOADER if !MEDIA_TUNER_CUSTOMIZE && HOTPLUG but the kconfig tool did not pick up this second-order dependency and allowed CONFIG_FW_LOADER=m to be selected - in which case the build fails. the workaround i found was to move the select of FW_LOADER one level up, so that the buggy kconfig tool can notice it and can act appropriately. This problem can probably be worked around in other ways as well, i went for the minimal fix. Obviously, the kconfig tool should be fixed, it is not reasonable to expect driver authors to do manual dependency resolution (that kconfig itself already does) and uglify the Kconfig files. The kconfig tool did nothing to warn about this situation and did not prevent this faulty .config from being constructed. Signed-off-by: Ingo Molnar Signed-off-by: Mauro Carvalho Chehab --- linux/drivers/media/common/tuners/Kconfig | 1 + 1 file changed, 1 insertion(+) (limited to 'linux/drivers/media/common/tuners') diff --git a/linux/drivers/media/common/tuners/Kconfig b/linux/drivers/media/common/tuners/Kconfig index d62065404..85482960d 100644 --- a/linux/drivers/media/common/tuners/Kconfig +++ b/linux/drivers/media/common/tuners/Kconfig @@ -21,6 +21,7 @@ config MEDIA_TUNER tristate default VIDEO_MEDIA && I2C depends on VIDEO_MEDIA && I2C + select FW_LOADER if !MEDIA_TUNER_CUSTOMIZE && HOTPLUG select MEDIA_TUNER_XC2028 if !MEDIA_TUNER_CUSTOMIZE && HOTPLUG select MEDIA_TUNER_XC5000 if !MEDIA_TUNER_CUSTOMIZE && HOTPLUG select MEDIA_TUNER_MT20XX if !MEDIA_TUNER_CUSTOMIZE -- cgit v1.2.3 From b47d82cb176427c78627d8791cc1361be9c0e971 Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Wed, 21 May 2008 00:30:31 +0000 Subject: cinergyT2: endianness annotations, endianness and race fixes From: Al Viro Endianness annotations and fixes + fixing the handling of ->uncorrected_block_count Signed-off-by: Al Viro Signed-off-by: Mauro Carvalho Chehab --- linux/drivers/media/common/tuners/tuner-simple.c | 2 ++ linux/drivers/media/common/tuners/tuner-types.c | 22 ++++++++++++++++++++++ 2 files changed, 24 insertions(+) (limited to 'linux/drivers/media/common/tuners') diff --git a/linux/drivers/media/common/tuners/tuner-simple.c b/linux/drivers/media/common/tuners/tuner-simple.c index c9d70e4b2..b4a95cc5b 100644 --- a/linux/drivers/media/common/tuners/tuner-simple.c +++ b/linux/drivers/media/common/tuners/tuner-simple.c @@ -150,6 +150,7 @@ static inline int tuner_stereo(const int type, const int status) case TUNER_PHILIPS_FM1236_MK3: case TUNER_PHILIPS_FM1256_IH3: case TUNER_LG_NTSC_TAPE: + case TUNER_TCL_MF02GIP_5N: return ((status & TUNER_SIGNAL) == TUNER_STEREO_MK3); default: return status & TUNER_STEREO; @@ -521,6 +522,7 @@ static int simple_radio_bandswitch(struct dvb_frontend *fe, u8 *buffer) case TUNER_PHILIPS_FMD1216ME_MK3: case TUNER_LG_NTSC_TAPE: case TUNER_PHILIPS_FM1256_IH3: + case TUNER_TCL_MF02GIP_5N: buffer[3] = 0x19; break; case TUNER_TNF_5335MF: diff --git a/linux/drivers/media/common/tuners/tuner-types.c b/linux/drivers/media/common/tuners/tuner-types.c index b3f0f62e0..861d23872 100644 --- a/linux/drivers/media/common/tuners/tuner-types.c +++ b/linux/drivers/media/common/tuners/tuner-types.c @@ -1217,6 +1217,23 @@ static struct tuner_params tuner_samsung_tcpg_6121p30a_params[] = { }, }; +/* ------------ TUNER_TCL_MF02GIP-5N-E - TCL MF02GIP-5N ------------ */ + +static struct tuner_range tuner_tcl_mf02gip_5n_ntsc_ranges[] = { + { 16 * 172.00 /*MHz*/, 0x8e, 0x01, }, + { 16 * 448.00 /*MHz*/, 0x8e, 0x02, }, + { 16 * 999.99 , 0x8e, 0x04, }, +}; + +static struct tuner_params tuner_tcl_mf02gip_5n_params[] = { + { + .type = TUNER_PARAM_TYPE_NTSC, + .ranges = tuner_tcl_mf02gip_5n_ntsc_ranges, + .count = ARRAY_SIZE(tuner_tcl_mf02gip_5n_ntsc_ranges), + .cb_first_if_lower_freq = 1, + }, +}; + /* --------------------------------------------------------------------- */ struct tunertype tuners[] = { @@ -1642,6 +1659,11 @@ struct tunertype tuners[] = { .name = "Xceive 5000 tuner", /* see xc5000.c for details */ }, + [TUNER_TCL_MF02GIP_5N] = { /* TCL tuner MF02GIP-5N-E */ + .name = "TCL tuner MF02GIP-5N-E", + .params = tuner_tcl_mf02gip_5n_params, + .count = ARRAY_SIZE(tuner_tcl_mf02gip_5n_params), + }, }; EXPORT_SYMBOL(tuners); -- cgit v1.2.3 From 6c704b27377af4d7802223b3e7a7ec4f154fb158 Mon Sep 17 00:00:00 2001 From: Michael Krufky Date: Sun, 25 May 2008 21:31:17 -0400 Subject: tuner-simple: fix tuner_warn() induced kernel oops in simple_tuner_attach() From: Andy Walls The tuner_warn() macro relies on the local variable "priv" to be a valid pointer. There was a case in simple_tuner_attach() where this cannot be the case yet, so tuner_warn() would dereference a NULL "priv" pointer. Changed the tuner_warn() to a printk() with the originally intended output format. Signed-off-by: Andy Walls Signed-off-by: Michael Krufky --- linux/drivers/media/common/tuners/tuner-simple.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) (limited to 'linux/drivers/media/common/tuners') diff --git a/linux/drivers/media/common/tuners/tuner-simple.c b/linux/drivers/media/common/tuners/tuner-simple.c index 29c14a4c6..c9d70e4b2 100644 --- a/linux/drivers/media/common/tuners/tuner-simple.c +++ b/linux/drivers/media/common/tuners/tuner-simple.c @@ -1053,8 +1053,10 @@ struct dvb_frontend *simple_tuner_attach(struct dvb_frontend *fe, fe->ops.i2c_gate_ctrl(fe, 1); if (1 != i2c_transfer(i2c_adap, &msg, 1)) - tuner_warn("unable to probe %s, proceeding anyway.", - tuners[type].name); + printk(KERN_WARNING "tuner-simple %d-%04x: " + "unable to probe %s, proceeding anyway.", + i2c_adapter_id(i2c_adap), i2c_addr, + tuners[type].name); if (fe->ops.i2c_gate_ctrl) fe->ops.i2c_gate_ctrl(fe, 0); -- cgit v1.2.3 From d684e25698da5fd4ff9ed93bc67a22f213af6eb2 Mon Sep 17 00:00:00 2001 From: Michael Krufky Date: Sat, 31 May 2008 14:18:55 -0400 Subject: tda18271_calc_rf_cal must return the return value of tda18271_lookup_map From: Michael Krufky On the TDA18271HD/C1, we perform RF tracking filter correction for VHF low band, only. If supplied a frequency out of range, the error must be returned to the caller (tda18271c1_rf_tracking_filter_calibration) so that it can decide whether or not to write to register EB14, RFC_CPROG[7:0] Signed-off-by: Michael Krufky --- linux/drivers/media/common/tuners/tda18271-common.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'linux/drivers/media/common/tuners') diff --git a/linux/drivers/media/common/tuners/tda18271-common.c b/linux/drivers/media/common/tuners/tda18271-common.c index 5bdab8181..1eaff90da 100644 --- a/linux/drivers/media/common/tuners/tda18271-common.c +++ b/linux/drivers/media/common/tuners/tda18271-common.c @@ -716,11 +716,11 @@ int tda18271_calc_rf_cal(struct dvb_frontend *fe, u32 *freq) unsigned char *regs = priv->tda18271_regs; u8 val; - tda18271_lookup_map(fe, RF_CAL, freq, &val); + int ret = tda18271_lookup_map(fe, RF_CAL, freq, &val); regs[R_EB14] = val; - return 0; + return ret; } /* -- cgit v1.2.3 From 7288f7ce4c594f7332bd451b8a97888b695b5ce6 Mon Sep 17 00:00:00 2001 From: Michael Krufky Date: Tue, 3 Jun 2008 01:16:37 -0400 Subject: tda18271: update filename in comments From: Michael Krufky This file was renamed but we forgot to change it in the comments. Signed-off-by: Michael Krufky --- linux/drivers/media/common/tuners/tda18271-maps.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'linux/drivers/media/common/tuners') diff --git a/linux/drivers/media/common/tuners/tda18271-maps.c b/linux/drivers/media/common/tuners/tda18271-maps.c index 83e756196..ab14ceb9e 100644 --- a/linux/drivers/media/common/tuners/tda18271-maps.c +++ b/linux/drivers/media/common/tuners/tda18271-maps.c @@ -1,5 +1,5 @@ /* - tda18271-tables.c - driver for the Philips / NXP TDA18271 silicon tuner + tda18271-maps.c - driver for the Philips / NXP TDA18271 silicon tuner Copyright (C) 2007, 2008 Michael Krufky -- cgit v1.2.3 From e92f78bc63e71d1572225b93b4ea0c31e6e6efc0 Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Tue, 3 Jun 2008 14:50:32 -0300 Subject: backout changeset e30f9c367fabf6227e17c5191c62f886d55eb2d7 From: Mauro Carvalho Chehab Unfortunately, this patch were mixed with an experimental patch I'm working with. Signed-off-by: Mauro Carvalho Chehab --- linux/drivers/media/common/tuners/tuner-simple.c | 2 -- linux/drivers/media/common/tuners/tuner-types.c | 22 ---------------------- 2 files changed, 24 deletions(-) (limited to 'linux/drivers/media/common/tuners') diff --git a/linux/drivers/media/common/tuners/tuner-simple.c b/linux/drivers/media/common/tuners/tuner-simple.c index b4a95cc5b..c9d70e4b2 100644 --- a/linux/drivers/media/common/tuners/tuner-simple.c +++ b/linux/drivers/media/common/tuners/tuner-simple.c @@ -150,7 +150,6 @@ static inline int tuner_stereo(const int type, const int status) case TUNER_PHILIPS_FM1236_MK3: case TUNER_PHILIPS_FM1256_IH3: case TUNER_LG_NTSC_TAPE: - case TUNER_TCL_MF02GIP_5N: return ((status & TUNER_SIGNAL) == TUNER_STEREO_MK3); default: return status & TUNER_STEREO; @@ -522,7 +521,6 @@ static int simple_radio_bandswitch(struct dvb_frontend *fe, u8 *buffer) case TUNER_PHILIPS_FMD1216ME_MK3: case TUNER_LG_NTSC_TAPE: case TUNER_PHILIPS_FM1256_IH3: - case TUNER_TCL_MF02GIP_5N: buffer[3] = 0x19; break; case TUNER_TNF_5335MF: diff --git a/linux/drivers/media/common/tuners/tuner-types.c b/linux/drivers/media/common/tuners/tuner-types.c index 861d23872..b3f0f62e0 100644 --- a/linux/drivers/media/common/tuners/tuner-types.c +++ b/linux/drivers/media/common/tuners/tuner-types.c @@ -1217,23 +1217,6 @@ static struct tuner_params tuner_samsung_tcpg_6121p30a_params[] = { }, }; -/* ------------ TUNER_TCL_MF02GIP-5N-E - TCL MF02GIP-5N ------------ */ - -static struct tuner_range tuner_tcl_mf02gip_5n_ntsc_ranges[] = { - { 16 * 172.00 /*MHz*/, 0x8e, 0x01, }, - { 16 * 448.00 /*MHz*/, 0x8e, 0x02, }, - { 16 * 999.99 , 0x8e, 0x04, }, -}; - -static struct tuner_params tuner_tcl_mf02gip_5n_params[] = { - { - .type = TUNER_PARAM_TYPE_NTSC, - .ranges = tuner_tcl_mf02gip_5n_ntsc_ranges, - .count = ARRAY_SIZE(tuner_tcl_mf02gip_5n_ntsc_ranges), - .cb_first_if_lower_freq = 1, - }, -}; - /* --------------------------------------------------------------------- */ struct tunertype tuners[] = { @@ -1659,11 +1642,6 @@ struct tunertype tuners[] = { .name = "Xceive 5000 tuner", /* see xc5000.c for details */ }, - [TUNER_TCL_MF02GIP_5N] = { /* TCL tuner MF02GIP-5N-E */ - .name = "TCL tuner MF02GIP-5N-E", - .params = tuner_tcl_mf02gip_5n_params, - .count = ARRAY_SIZE(tuner_tcl_mf02gip_5n_params), - }, }; EXPORT_SYMBOL(tuners); -- cgit v1.2.3 From c947470ba24a5e6c98288255e85880a6ba0c82aa Mon Sep 17 00:00:00 2001 From: Michael Krufky Date: Thu, 5 Jun 2008 08:53:08 -0400 Subject: tda827x: fix NULL pointer in tda827xa_lna_gain From: Sigmund Augdal Check that tda827x_config is defined before attempting to use it. Signed-off-by: Sigmund Augdal Signed-off-by: Michael Krufky --- linux/drivers/media/common/tuners/tda827x.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'linux/drivers/media/common/tuners') diff --git a/linux/drivers/media/common/tuners/tda827x.c b/linux/drivers/media/common/tuners/tda827x.c index 2d39f9be5..763b0dd95 100644 --- a/linux/drivers/media/common/tuners/tda827x.c +++ b/linux/drivers/media/common/tuners/tda827x.c @@ -419,13 +419,13 @@ static void tda827xa_lna_gain(struct dvb_frontend *fe, int high, unsigned char buf[] = {0x22, 0x01}; int arg; int gp_func; - struct i2c_msg msg = { .addr = priv->cfg->switch_addr, .flags = 0, - .buf = buf, .len = sizeof(buf) }; + struct i2c_msg msg = { .flags = 0, .buf = buf, .len = sizeof(buf) }; if (NULL == priv->cfg) { dprintk("tda827x_config not defined, cannot set LNA gain!\n"); return; } + msg.addr = priv->cfg->switch_addr; if (priv->cfg->config) { if (high) dprintk("setting LNA to high gain\n"); -- cgit v1.2.3