From c33556713c14419683e262c03a7280f8d9fb88bd Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Tue, 3 Mar 2009 14:37:50 -0300 Subject: Add cx231xx USB driver From: Sri Deevi Signed-off-by: Srinivasa Deevi Signed-off-by: Mauro Carvalho Chehab --- linux/drivers/media/video/cx231xx/cx231xx-avcore.c | 2289 ++++++++++++++++++++ 1 file changed, 2289 insertions(+) create mode 100644 linux/drivers/media/video/cx231xx/cx231xx-avcore.c (limited to 'linux/drivers/media/video/cx231xx/cx231xx-avcore.c') diff --git a/linux/drivers/media/video/cx231xx/cx231xx-avcore.c b/linux/drivers/media/video/cx231xx/cx231xx-avcore.c new file mode 100644 index 000000000..833967f46 --- /dev/null +++ b/linux/drivers/media/video/cx231xx/cx231xx-avcore.c @@ -0,0 +1,2289 @@ +/* + cx231xx_avcore.c - driver for Conexant Cx23100/101/102 USB video capture devices + + Copyright (C) 2008 + + This program contains the specific code to control the avdecoder chip and + other related usb control functions for cx231xx based chipset. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include "cx231xx.h" + + +/************************************************************************************* + * C O L I B R I - B L O C K C O N T R O L functions * + *************************************************************************************/ +int cx231xx_colibri_init_super_block(struct cx231xx *dev, u32 ref_count) +{ + int status = 0; + u8 temp = 0; + u32 colibri_power_status = 0; + int i = 0; + + /* super block initialize */ + temp = (u8)(ref_count & 0xff); + status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, SUP_BLK_TUNE2, 2, temp, 1); + + status = cx231xx_read_i2c_data(dev, Colibri_DEVICE_ADDRESS, SUP_BLK_TUNE2, 2, &colibri_power_status, 1); + + temp = (u8)((ref_count & 0x300) >> 8); + temp |= 0x40; + status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, SUP_BLK_TUNE1, 2, temp, 1); + status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, SUP_BLK_PLL2, 2, 0x0f, 1); + + /* enable pll */ + while(colibri_power_status != 0x18) + { + status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, SUP_BLK_PWRDN, 2, 0x18, 1); + status = cx231xx_read_i2c_data(dev, Colibri_DEVICE_ADDRESS, SUP_BLK_PWRDN, 2, &colibri_power_status, 1); + colibri_power_status &= 0xff; + if(status < 0) { + cx231xx_info(": Init Super Block failed in sending/receiving cmds\n"); + break; + } + i++; + if( i == 10) { + cx231xx_info(": Init Super Block force break in loop !!!!\n"); + status = -1; + break; + } + } + + if(status < 0 ) + return status; + + /* start tuning filter */ + status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, SUP_BLK_TUNE3, 2, 0x40, 1); + msleep(5); + + /* exit tuning */ + status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, SUP_BLK_TUNE3, 2, 0x00, 1); + + return status; +} + +int cx231xx_colibri_init_channels(struct cx231xx *dev) +{ + int status = 0; + + /* power up all 3 channels, clear pd_buffer */ + status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, ADC_PWRDN_CLAMP_CH1, 2, 0x00, 1); + status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, ADC_PWRDN_CLAMP_CH2, 2, 0x00, 1); + status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, ADC_PWRDN_CLAMP_CH3, 2, 0x00, 1); + + /* Enable quantizer calibration */ + status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, ADC_COM_QUANT, 2, 0x02, 1); + + /* channel initialize, force modulator (fb) reset */ + status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, ADC_FB_FRCRST_CH1, 2, 0x17, 1); + status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, ADC_FB_FRCRST_CH2, 2, 0x17, 1); + status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, ADC_FB_FRCRST_CH3, 2, 0x17, 1); + + /* start quantilizer calibration */ + status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, ADC_CAL_ATEST_CH1, 2, 0x10, 1); + status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, ADC_CAL_ATEST_CH2, 2, 0x10, 1); + status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, ADC_CAL_ATEST_CH3, 2, 0x10, 1); + msleep(5); + + /* exit modulator (fb) reset */ + status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, ADC_FB_FRCRST_CH1, 2, 0x07, 1); + status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, ADC_FB_FRCRST_CH2, 2, 0x07, 1); + status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, ADC_FB_FRCRST_CH3, 2, 0x07, 1); + + /* enable the pre_clamp in each channel for single-ended input */ + status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, ADC_NTF_PRECLMP_EN_CH1, 2, 0xf0, 1); + status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, ADC_NTF_PRECLMP_EN_CH2, 2, 0xf0, 1); + status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, ADC_NTF_PRECLMP_EN_CH3, 2, 0xf0, 1); + + /* use diode instead of resistor, so set term_en to 0, res_en to 0 */ + status = cx231xx_reg_mask_write(dev, Colibri_DEVICE_ADDRESS, 8, ADC_QGAIN_RES_TRM_CH1, 3, 7, 0x00); + status = cx231xx_reg_mask_write(dev, Colibri_DEVICE_ADDRESS, 8, ADC_QGAIN_RES_TRM_CH2, 3, 7, 0x00); + status = cx231xx_reg_mask_write(dev, Colibri_DEVICE_ADDRESS, 8, ADC_QGAIN_RES_TRM_CH3, 3, 7, 0x00); + + /* dynamic element matching off */ + status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, ADC_DCSERVO_DEM_CH1, 2, 0x03, 1); + status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, ADC_DCSERVO_DEM_CH2, 2, 0x03, 1); + status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, ADC_DCSERVO_DEM_CH3, 2, 0x03, 1); + + return status; +} + +int cx231xx_colibri_setup_AFE_for_baseband(struct cx231xx *dev) +{ + u32 c_value = 0; + int status = 0; + + status = cx231xx_read_i2c_data(dev, Colibri_DEVICE_ADDRESS, ADC_PWRDN_CLAMP_CH2, 2, &c_value, 1); + c_value &= (~(0x50)); + status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, ADC_PWRDN_CLAMP_CH2, 2, c_value, 1); + + return status; +} + +/* + we have 3 channel + channel 1 ----- pin 1 to pin4(in reg is 1-4) + channel 2 ----- pin 5 to pin8(in reg is 5-8) + channel 3 ----- pin 9 to pin 12(in reg is 9-11) +*/ +int cx231xx_colibri_set_input_mux(struct cx231xx *dev, u32 input_mux) +{ + u8 ch1_setting = (u8)input_mux; + u8 ch2_setting = (u8)(input_mux >> 8); + u8 ch3_setting = (u8)(input_mux >> 16); + int status = 0; + u32 value = 0; + + if(ch1_setting != 0) + { + status = cx231xx_read_i2c_data(dev, Colibri_DEVICE_ADDRESS, ADC_INPUT_CH1, 2, &value, 1); + value &= (!INPUT_SEL_MASK); + value |= (ch1_setting-1)<<4; + value &= 0xff; + status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, ADC_INPUT_CH1, 2, value, 1); + } + + if(ch2_setting != 0) + { + status = cx231xx_read_i2c_data(dev, Colibri_DEVICE_ADDRESS, ADC_INPUT_CH2, 2, &value, 1); + value &= (!INPUT_SEL_MASK); + value |= (ch2_setting-1)<<4; + value &= 0xff; + status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, ADC_INPUT_CH2, 2, value, 1); + } + + /* For ch3_setting, the value to put in the register is 7 less than the input number */ + if(ch3_setting != 0) + { + status = cx231xx_read_i2c_data(dev, Colibri_DEVICE_ADDRESS, ADC_INPUT_CH3, 2, &value, 1); + value &= (!INPUT_SEL_MASK); + value |= (ch3_setting-1)<<4; + value &= 0xff; + status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, ADC_INPUT_CH3, 2, value, 1); + } + + return status; +} + +int cx231xx_colibri_set_mode(struct cx231xx *dev, enum AFE_MODE mode) +{ + int status = 0; + + switch(mode) { + case AFE_MODE_LOW_IF: + /* SetupAFEforLowIF(); */ + break; + case AFE_MODE_BASEBAND: + status = cx231xx_colibri_setup_AFE_for_baseband(dev); + break; + case AFE_MODE_EU_HI_IF: + /* SetupAFEforEuHiIF(); */ + break; + case AFE_MODE_US_HI_IF: + /* SetupAFEforUsHiIF(); */ + break; + case AFE_MODE_JAPAN_HI_IF: + /* SetupAFEforJapanHiIF(); */ + break; + } + + if((mode != dev->colibri_mode) && (dev->video_input == CX231XX_VMUX_TELEVISION)) { + status = cx231xx_colibri_adjust_ref_count(dev, CX231XX_VMUX_TELEVISION); + } + + dev->colibri_mode = mode; + + return status; +} + +/* For power saving in the EVK */ +int cx231xx_colibri_update_power_control(struct cx231xx *dev, AV_MODE avmode) +{ + u32 colibri_power_status = 0; + int status = 0; + + switch (dev->model) { + case CX231XX_BOARD_CNXT_RDE_250: + case CX231XX_BOARD_CNXT_RDU_250: + + if(avmode==POLARIS_AVMODE_ANALOGT_TV) + { + while(colibri_power_status != 0x18) { + status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, + SUP_BLK_PWRDN, 2, 0x18, 1); + status = cx231xx_read_i2c_data(dev, Colibri_DEVICE_ADDRESS, + SUP_BLK_PWRDN, 2, &colibri_power_status, 1); + if(status < 0 ) + break; + } + + status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, + ADC_PWRDN_CLAMP_CH1, 2, 0x00, 1); + status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, + ADC_PWRDN_CLAMP_CH2, 2, 0x00, 1); + status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, + ADC_PWRDN_CLAMP_CH3, 2, 0x00, 1); + } + else if(avmode==POLARIS_AVMODE_DIGITAL) { + status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, + ADC_PWRDN_CLAMP_CH1, 2, 0x70, 1); + status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, + ADC_PWRDN_CLAMP_CH2, 2, 0x70, 1); + status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, + ADC_PWRDN_CLAMP_CH3, 2, 0x70, 1); + + status = cx231xx_read_i2c_data(dev, Colibri_DEVICE_ADDRESS, + SUP_BLK_PWRDN, 2, &colibri_power_status, 1); + colibri_power_status |=0x07; + status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, + SUP_BLK_PWRDN, 2, colibri_power_status, 1); + } + else if(avmode==POLARIS_AVMODE_ENXTERNAL_AV) { + + while(colibri_power_status != 0x18) { + status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, + SUP_BLK_PWRDN, 2, 0x18, 1); + status = cx231xx_read_i2c_data(dev, Colibri_DEVICE_ADDRESS, + SUP_BLK_PWRDN, 2, &colibri_power_status, 1); + if(status < 0 ) + break; + } + + status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, + ADC_PWRDN_CLAMP_CH1, 2, 0x00, 1); + status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, + ADC_PWRDN_CLAMP_CH2, 2, 0x00, 1); + status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, + ADC_PWRDN_CLAMP_CH3, 2, 0x00, 1); + } + else { + cx231xx_info("Invalid AV mode input\n"); + status = -1; + } + break; + default: + if(avmode==POLARIS_AVMODE_ANALOGT_TV) + { + while(colibri_power_status != 0x18) { + status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, + SUP_BLK_PWRDN, 2, 0x18, 1); + status = cx231xx_read_i2c_data(dev, Colibri_DEVICE_ADDRESS, + SUP_BLK_PWRDN, 2, &colibri_power_status, 1); + if(status < 0 ) + break; + } + + status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, + ADC_PWRDN_CLAMP_CH1, 2, 0x40, 1); + status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, + ADC_PWRDN_CLAMP_CH2, 2, 0x40, 1); + status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, + ADC_PWRDN_CLAMP_CH3, 2, 0x00, 1); + } + else if(avmode==POLARIS_AVMODE_DIGITAL) { + status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, + ADC_PWRDN_CLAMP_CH1, 2, 0x70, 1); + status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, + ADC_PWRDN_CLAMP_CH2, 2, 0x70, 1); + status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, + ADC_PWRDN_CLAMP_CH3, 2, 0x70, 1); + + status = cx231xx_read_i2c_data(dev, Colibri_DEVICE_ADDRESS, + SUP_BLK_PWRDN, 2, &colibri_power_status, 1); + colibri_power_status |=0x07; + status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, + SUP_BLK_PWRDN, 2, colibri_power_status, 1); + } + else if(avmode==POLARIS_AVMODE_ENXTERNAL_AV) { + while(colibri_power_status != 0x18) { + status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, + SUP_BLK_PWRDN, 2, 0x18, 1); + status = cx231xx_read_i2c_data(dev, Colibri_DEVICE_ADDRESS, + SUP_BLK_PWRDN, 2, &colibri_power_status, 1); + if(status < 0 ) + break; + } + + status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, + ADC_PWRDN_CLAMP_CH1, 2, 0x00, 1); + status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, + ADC_PWRDN_CLAMP_CH2, 2, 0x00, 1); + status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, + ADC_PWRDN_CLAMP_CH3, 2, 0x40, 1); + } + else { + cx231xx_info("Invalid AV mode input\n"); + status = -1; + } + } /* switch */ + + return status; +} + +int cx231xx_colibri_adjust_ref_count(struct cx231xx *dev, u32 video_input) +{ + u32 input_mode = 0; + u32 ntf_mode = 0; + int status = 0; + + dev->video_input = video_input; + + if(video_input == CX231XX_VMUX_TELEVISION) { + status = cx231xx_read_i2c_data(dev, Colibri_DEVICE_ADDRESS, ADC_INPUT_CH3, 2, &input_mode, 1); + status = cx231xx_read_i2c_data(dev, Colibri_DEVICE_ADDRESS, + ADC_NTF_PRECLMP_EN_CH3, 2, &ntf_mode, 1); + } + else { + status = cx231xx_read_i2c_data(dev, Colibri_DEVICE_ADDRESS, ADC_INPUT_CH1, 2, &input_mode, 1); + status = cx231xx_read_i2c_data(dev, Colibri_DEVICE_ADDRESS, + ADC_NTF_PRECLMP_EN_CH1, 2, &ntf_mode, 1); + } + + input_mode = (ntf_mode & 0x3) | ((input_mode & 0x6) << 1); + + switch(input_mode) + { + case SINGLE_ENDED: + dev->colibri_ref_count = 0x23C; + break; + case LOW_IF: + dev->colibri_ref_count = 0x24C; + break; + case EU_IF: + dev->colibri_ref_count = 0x258; + break; + case US_IF: + dev->colibri_ref_count = 0x260; + break; + default: + break; + } + + status = cx231xx_colibri_init_super_block(dev, dev->colibri_ref_count); + + return status; +} + + + +/************************************************************************************* + * V I D E O / A U D I O D E C O D E R C O N T R O L functions * + *************************************************************************************/ +int cx231xx_set_video_input_mux(struct cx231xx *dev, u8 input) +{ + int status = 0; + + switch(INPUT(input)->type) { + case CX231XX_VMUX_COMPOSITE1: + case CX231XX_VMUX_SVIDEO: + if((dev->current_pcb_config.type == USB_BUS_POWER) && + (dev->power_mode != POLARIS_AVMODE_ENXTERNAL_AV)) { + status = cx231xx_set_power_mode(dev, POLARIS_AVMODE_ENXTERNAL_AV); /* External AV */ + if (status < 0) { + cx231xx_errdev("%s: cx231xx_set_power_mode : Failed to set Power - errCode [%d]!\n", + __func__, status); + return status; + } + } + status = cx231xx_set_decoder_video_input(dev, INPUT(input)->type, INPUT(input)->vmux); + break; + case CX231XX_VMUX_TELEVISION: + case CX231XX_VMUX_CABLE: + if((dev->current_pcb_config.type == USB_BUS_POWER) && + (dev->power_mode != POLARIS_AVMODE_ANALOGT_TV)) { + status = cx231xx_set_power_mode(dev, POLARIS_AVMODE_ANALOGT_TV); /* Tuner */ + if (status < 0) { + cx231xx_errdev("%s: cx231xx_set_power_mode : Failed to set Power - errCode [%d]!\n", + __func__, status); + return status; + } + } + status = cx231xx_set_decoder_video_input(dev, CX231XX_VMUX_COMPOSITE1, INPUT(input)->vmux); + break; + default: + cx231xx_errdev("%s: cx231xx_set_power_mode : Unknown Input %d !\n", + __func__, INPUT(input)->type); + break; + } + + /* save the selection */ + dev->video_input = input; + + return status; +} + +int cx231xx_set_decoder_video_input(struct cx231xx *dev, u8 pin_type, u8 input) +{ + int status = 0; + u32 value = 0; + + if(pin_type != dev->video_input) { + status = cx231xx_colibri_adjust_ref_count(dev, pin_type); + if(status < 0 ) { + cx231xx_errdev("%s: cx231xx_colibri_adjust_ref_count :Failed to set Colibri input mux - errCode [%d]!\n", + __func__, status); + return status; + } + } + + /* call colibri block to set video inputs */ + status = cx231xx_colibri_set_input_mux(dev, input); + if(status < 0 ) { + cx231xx_errdev("%s: cx231xx_colibri_set_input_mux :Failed to set Colibri input mux - errCode [%d]!\n", + __func__, status); + return status; + } + + switch(pin_type) { + case CX231XX_VMUX_COMPOSITE1: + { + status = cx231xx_read_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, AFE_CTRL, 2, &value, 4); + value |= (0<<13)|(1<<4); + value &= ~(1<<5); + + value &= (~(0x1FF8000)); /* set [24:23] [22:15] to 0 */ + value |= 0x1000000; /* set FUNC_MODE[24:23] = 2 IF_MOD[22:15] = 0 */ + status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, AFE_CTRL, 2, value, 4); + + status = cx231xx_read_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, OUT_CTRL1, 2, &value, 4); + value |= (1<<7); + status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, OUT_CTRL1, 2, value, 4); + + /* Set vip 1.1 output mode */ + status = cx231xx_read_modify_write_i2c_dword(dev, HAMMERHEAD_I2C_ADDRESS, + OUT_CTRL1, FLD_OUT_MODE, OUT_MODE_VIP11); + + /* Tell DIF object to go to baseband mode */ + status = cx231xx_dif_set_standard(dev, DIF_USE_BASEBAND); + if (status < 0) { + cx231xx_errdev("%s: cx231xx_dif set to By pass mode - errCode [%d]!\n", + __func__, status); + return status; + } + + /* Read the DFE_CTRL1 register */ + status = cx231xx_read_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, DFE_CTRL1, 2, &value, 4); + + /* enable the VBI_GATE_EN */ + value |= FLD_VBI_GATE_EN; + + /* Enable the auto-VGA enable */ + value |= FLD_VGA_AUTO_EN; + + /* Write it back */ + status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, DFE_CTRL1, 2, value, 4); + + /* Disable auto config of registers */ + status = cx231xx_read_modify_write_i2c_dword(dev, HAMMERHEAD_I2C_ADDRESS, + MODE_CTRL, FLD_ACFG_DIS, cx231xx_set_field(FLD_ACFG_DIS, 1)); + + /* Set CVBS input mode */ + status = cx231xx_read_modify_write_i2c_dword(dev, HAMMERHEAD_I2C_ADDRESS, + MODE_CTRL, FLD_INPUT_MODE, + cx231xx_set_field(FLD_INPUT_MODE, INPUT_MODE_CVBS_0)); + } + break; + case CX231XX_VMUX_SVIDEO: + { + /* Disable the use of DIF */ + + status = cx231xx_read_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, AFE_CTRL, 2, &value, 4); + + value &= (~(0x1FF8000)); /* set [24:23] [22:15] to 0 */ + value |= 0x1000010; /* set FUNC_MODE[24:23] = 2 + IF_MOD[22:15] = 0 DCR_BYP_CH2[4:4] = 1; */ + status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, AFE_CTRL, 2, value, 4); + + /* Tell DIF object to go to baseband mode */ + status = cx231xx_dif_set_standard(dev, DIF_USE_BASEBAND); + if (status < 0) { + cx231xx_errdev("%s: cx231xx_dif set to By pass mode - errCode [%d]!\n", + __func__, status); + return status; + } + + /* Read the DFE_CTRL1 register */ + status = cx231xx_read_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, DFE_CTRL1, 2, &value, 4); + + /* enable the VBI_GATE_EN */ + value |= FLD_VBI_GATE_EN; + + /* Enable the auto-VGA enable */ + value |= FLD_VGA_AUTO_EN; + + /* Write it back */ + status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, DFE_CTRL1, 2, value, 4); + + /* Disable auto config of registers */ + status = cx231xx_read_modify_write_i2c_dword(dev, HAMMERHEAD_I2C_ADDRESS, + MODE_CTRL, FLD_ACFG_DIS, cx231xx_set_field(FLD_ACFG_DIS, 1)); + + /* Set YC input mode */ + status = cx231xx_read_modify_write_i2c_dword(dev, HAMMERHEAD_I2C_ADDRESS, + MODE_CTRL, FLD_INPUT_MODE, + cx231xx_set_field(FLD_INPUT_MODE, INPUT_MODE_YC_1)); + + /* Chroma to ADC2 */ + status = cx231xx_read_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, AFE_CTRL, 2, &value, 4); + value |= FLD_CHROMA_IN_SEL; /* set the chroma in select */ + + /* Clear VGA_SEL_CH2 and VGA_SEL_CH3 (bits 7 and 8) This sets them to use video + rather than audio. Only one of the two will be in use. */ + value &= ~(FLD_VGA_SEL_CH2 | FLD_VGA_SEL_CH3); + + status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, AFE_CTRL, 2, value, 4); + + status = cx231xx_colibri_set_mode(dev, AFE_MODE_BASEBAND); + } + break; + case CX231XX_VMUX_TELEVISION: + case CX231XX_VMUX_CABLE: + default: + { + switch(dev->model) { + case CX231XX_BOARD_CNXT_RDE_250: + case CX231XX_BOARD_CNXT_RDU_250: + { + /* Disable the use of DIF */ + + status = cx231xx_read_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, AFE_CTRL, 2, &value, 4); + value |= (0<<13)|(1<<4); + value &= ~(1<<5); + + value &= (~(0x1FF8000)); /* set [24:23] [22:15] to 0 */ + value |= 0x1000000; /* set FUNC_MODE[24:23] = 2 IF_MOD[22:15] = 0 */ + status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, AFE_CTRL, 2, value, 4); + + status = cx231xx_read_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, OUT_CTRL1, 2, &value, 4); + value |= (1<<7); + status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, OUT_CTRL1, 2, value, 4); + + /* Set vip 1.1 output mode */ + status = cx231xx_read_modify_write_i2c_dword(dev, HAMMERHEAD_I2C_ADDRESS, + OUT_CTRL1, FLD_OUT_MODE, OUT_MODE_VIP11); + + /* Tell DIF object to go to baseband mode */ + status = cx231xx_dif_set_standard(dev, DIF_USE_BASEBAND); + if (status < 0) { + cx231xx_errdev("%s: cx231xx_dif set to By pass mode - errCode [%d]!\n", + __func__, status); + return status; + } + + /* Read the DFE_CTRL1 register */ + status = cx231xx_read_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, DFE_CTRL1, 2, &value, 4); + + /* enable the VBI_GATE_EN */ + value |= FLD_VBI_GATE_EN; + + /* Enable the auto-VGA enable */ + value |= FLD_VGA_AUTO_EN; + + /* Write it back */ + status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, DFE_CTRL1, 2, value, 4); + + /* Disable auto config of registers */ + status = cx231xx_read_modify_write_i2c_dword(dev, HAMMERHEAD_I2C_ADDRESS, + MODE_CTRL, FLD_ACFG_DIS, cx231xx_set_field(FLD_ACFG_DIS, 1)); + + /* Set CVBS input mode */ + status = cx231xx_read_modify_write_i2c_dword(dev, HAMMERHEAD_I2C_ADDRESS, + MODE_CTRL, FLD_INPUT_MODE, + cx231xx_set_field(FLD_INPUT_MODE, INPUT_MODE_CVBS_0)); + } + break; + default: + { + /* Enable the DIF for the tuner */ + + /* Reinitialize the DIF */ + status = cx231xx_dif_set_standard(dev, dev->norm); + if (status < 0) { + cx231xx_errdev("%s: cx231xx_dif set to By pass mode - errCode [%d]!\n", + __func__, status); + return status; + } + + /* Make sure bypass is cleared */ + status = cx231xx_read_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, DIF_MISC_CTRL, 2, &value, 4); + + /* Clear the bypass bit */ + value &= ~FLD_DIF_DIF_BYPASS; + + /* Enable the use of the DIF block */ + status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, DIF_MISC_CTRL, 2, value, 4); + + /* Read the DFE_CTRL1 register */ + status = cx231xx_read_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, DFE_CTRL1, 2, &value, 4); + + /* Disable the VBI_GATE_EN */ + value &= ~FLD_VBI_GATE_EN; + + /* Enable the auto-VGA enable, AGC, and set the skip count to 2 */ + value |= FLD_VGA_AUTO_EN | FLD_AGC_AUTO_EN | 0x00200000; + + /* Write it back */ + status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, DFE_CTRL1, 2, value, 4); + + /* Wait 15 ms */ + msleep(1); + + /* Disable the auto-VGA enable AGC */ + value &= ~(FLD_VGA_AUTO_EN); + + /* Write it back */ + status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, DFE_CTRL1, 2, value, 4); + + /* Enable Polaris B0 AGC output */ + status = cx231xx_read_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, PIN_CTRL, 2, &value, 4); + value |=(FLD_OEF_AGC_RF)|(FLD_OEF_AGC_IFVGA)|(FLD_OEF_AGC_IF); + status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, PIN_CTRL, 2, value, 4); + + /* Set vip 1.1 output mode */ + status = cx231xx_read_modify_write_i2c_dword(dev, HAMMERHEAD_I2C_ADDRESS, + OUT_CTRL1, FLD_OUT_MODE, OUT_MODE_VIP11); + + /* Disable auto config of registers */ + status = cx231xx_read_modify_write_i2c_dword(dev, HAMMERHEAD_I2C_ADDRESS, + MODE_CTRL, FLD_ACFG_DIS, cx231xx_set_field(FLD_ACFG_DIS, 1)); + + /* Set CVBS input mode */ + status = cx231xx_read_modify_write_i2c_dword(dev, HAMMERHEAD_I2C_ADDRESS, + MODE_CTRL, FLD_INPUT_MODE, + cx231xx_set_field(FLD_INPUT_MODE, INPUT_MODE_CVBS_0)); + + /* Set some bits in AFE_CTRL so that channel 2 or 3 is ready to receive audio */ + /* Clear clamp for channels 2 and 3 (bit 16-17) */ + /* Clear droop comp (bit 19-20) */ + /* Set VGA_SEL (for audio control) (bit 7-8) */ + status = cx231xx_read_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, AFE_CTRL, 2, &value, 4); + + value |= FLD_VGA_SEL_CH3 | FLD_VGA_SEL_CH2; + + status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, AFE_CTRL, 2, value, 4); + } + break; + + } + } + break; + } + + /* Set raw VBI mode */ + status = cx231xx_read_modify_write_i2c_dword(dev, HAMMERHEAD_I2C_ADDRESS, + OUT_CTRL1, FLD_VBIHACTRAW_EN, + cx231xx_set_field(FLD_VBIHACTRAW_EN, 1)); + + status = cx231xx_read_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, OUT_CTRL1, 2, &value, 4); + if(value & 0x02) { + value |=(1<<19); + status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, OUT_CTRL1, 2, value, 4); + } + + return status; +} + +/* + * Handle any video-mode specific overrides that are different on a per video standards + * basis after touching the MODE_CTRL register which resets many values for autodetect + */ +int cx231xx_do_mode_ctrl_overrides(struct cx231xx *dev) +{ + int status = 0; + + cx231xx_info("do_mode_ctrl_overrides : 0x%x\n", (unsigned int)dev->norm); + + /* Change the DFE_CTRL3 bp_percent to fix flagging */ + status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, DFE_CTRL3, 2, 0xCD3F0280, 4); + + if( dev->norm & (V4L2_STD_NTSC_M | V4L2_STD_NTSC_M_JP | V4L2_STD_PAL_M) ) { + cx231xx_info("do_mode_ctrl_overrides NTSC\n"); + + /* Move the close caption lines out of active video, adjust the active video start point */ + status = cx231xx_read_modify_write_i2c_dword(dev, HAMMERHEAD_I2C_ADDRESS, + VERT_TIM_CTRL, FLD_VBLANK_CNT,0x18); + status = cx231xx_read_modify_write_i2c_dword(dev, HAMMERHEAD_I2C_ADDRESS, + VERT_TIM_CTRL, FLD_VACTIVE_CNT,0x1E6000); + status = cx231xx_read_modify_write_i2c_dword(dev, HAMMERHEAD_I2C_ADDRESS, + VERT_TIM_CTRL, FLD_V656BLANK_CNT,0x1E000000); + + status = cx231xx_read_modify_write_i2c_dword(dev, HAMMERHEAD_I2C_ADDRESS, + HORIZ_TIM_CTRL, FLD_HBLANK_CNT, + cx231xx_set_field(FLD_HBLANK_CNT, 0x79)); + } else if ( dev->norm & ( V4L2_STD_PAL_B | V4L2_STD_PAL_G | V4L2_STD_PAL_D | + V4L2_STD_PAL_I | V4L2_STD_PAL_N | V4L2_STD_PAL_Nc) ) { + cx231xx_info("do_mode_ctrl_overrides PAL\n"); + status = cx231xx_read_modify_write_i2c_dword(dev, HAMMERHEAD_I2C_ADDRESS, + VERT_TIM_CTRL, FLD_VBLANK_CNT,0x24); + /* Adjust the active video horizontal start point */ + status = cx231xx_read_modify_write_i2c_dword(dev, HAMMERHEAD_I2C_ADDRESS, + HORIZ_TIM_CTRL, FLD_HBLANK_CNT, + cx231xx_set_field(FLD_HBLANK_CNT, 0x85)); + } else if (dev->norm & ( V4L2_STD_SECAM_B | V4L2_STD_SECAM_D | V4L2_STD_SECAM_G | + V4L2_STD_SECAM_K | V4L2_STD_SECAM_K1 | V4L2_STD_SECAM_L | + V4L2_STD_SECAM_LC) ) { + cx231xx_info("do_mode_ctrl_overrides SECAM\n"); + status = cx231xx_read_modify_write_i2c_dword(dev, HAMMERHEAD_I2C_ADDRESS, + VERT_TIM_CTRL, FLD_VBLANK_CNT,0x24); + /* Adjust the active video horizontal start point */ + status = cx231xx_read_modify_write_i2c_dword(dev, HAMMERHEAD_I2C_ADDRESS, + HORIZ_TIM_CTRL, FLD_HBLANK_CNT, + cx231xx_set_field(FLD_HBLANK_CNT, 0x85)); + } + + return status; +} + +int cx231xx_set_audio_input(struct cx231xx *dev, u8 input) +{ + int status = 0; + enum AUDIO_INPUT ainput = AUDIO_INPUT_LINE; + + switch(INPUT(input)->amux) { + case CX231XX_AMUX_VIDEO: + ainput = AUDIO_INPUT_TUNER_TV; + break; + case CX231XX_AMUX_LINE_IN: + status = cx231xx_flatiron_set_audio_input(dev, input); + ainput = AUDIO_INPUT_LINE; + break; + default: + break; + } + + status = cx231xx_set_audio_decoder_input(dev, ainput); + + return status; +} + +int cx231xx_set_audio_decoder_input(struct cx231xx *dev, enum AUDIO_INPUT audio_input) +{ + u32 dwval; + int status; + u32 gen_ctrl; + u32 value = 0; + + /* Put it in soft reset */ + status = cx231xx_read_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, GENERAL_CTL, 2, &gen_ctrl, 1); + gen_ctrl |= 1; + status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, GENERAL_CTL, 2, gen_ctrl, 1); + + switch(audio_input) + { + case AUDIO_INPUT_LINE: + + /* setup AUD_IO control from Merlin paralle output */ + value = cx231xx_set_field(FLD_AUD_CHAN1_SRC, AUD_CHAN_SRC_PARALLEL); + status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, AUD_IO_CTRL, 2, value, 4); + + /* setup input to Merlin, SRC2 connect to AC97 + bypass upsample-by-2, slave mode, sony mode, left justify + adr 091c, dat 01000000 */ + status = cx231xx_read_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, AC97_CTL, 2, &dwval, 4); + + status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, AC97_CTL, 2, (dwval | FLD_AC97_UP2X_BYPASS), 4); + + /* select the parallel1 and SRC3 */ + status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, BAND_OUT_SEL, 2, + cx231xx_set_field(FLD_SRC3_IN_SEL, 0x0)| + cx231xx_set_field(FLD_SRC3_CLK_SEL, 0x0)| + cx231xx_set_field(FLD_PARALLEL1_SRC_SEL, 0x0), 4); + + /* unmute all, AC97 in, independence mode + adr 08d0, data 0x00063073 */ + status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, PATH1_CTL1, 2, 0x00063073, 4); + + /* set AVC maximum threshold, adr 08d4, dat ffff0024 */ + status = cx231xx_read_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, PATH1_VOL_CTL, 2, &dwval, 4); + status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, PATH1_VOL_CTL, 2, + (dwval | FLD_PATH1_AVC_THRESHOLD), 4); + + /* set SC maximum threshold, adr 08ec, dat ffffb3a3 */ + status = cx231xx_read_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, PATH1_SC_CTL, 2, &dwval, 4); + status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, PATH1_SC_CTL, 2, + (dwval | FLD_PATH1_SC_THRESHOLD), 4); + break; + + case AUDIO_INPUT_TUNER_TV: + default: + + /* Setup SRC sources and clocks */ + status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, BAND_OUT_SEL, 2, + cx231xx_set_field(FLD_SRC6_IN_SEL, 0x00)| + cx231xx_set_field(FLD_SRC6_CLK_SEL, 0x01)| + cx231xx_set_field(FLD_SRC5_IN_SEL, 0x00)| + cx231xx_set_field(FLD_SRC5_CLK_SEL, 0x02)| + cx231xx_set_field(FLD_SRC4_IN_SEL, 0x02)| + cx231xx_set_field(FLD_SRC4_CLK_SEL, 0x03)| + cx231xx_set_field(FLD_SRC3_IN_SEL, 0x00)| + cx231xx_set_field(FLD_SRC3_CLK_SEL, 0x00)| + cx231xx_set_field(FLD_BASEBAND_BYPASS_CTL, 0x00)| + cx231xx_set_field(FLD_AC97_SRC_SEL, 0x03)| + cx231xx_set_field(FLD_I2S_SRC_SEL, 0x00)| + cx231xx_set_field(FLD_PARALLEL2_SRC_SEL, 0x02)| + cx231xx_set_field(FLD_PARALLEL1_SRC_SEL, 0x01) , 4); + + /* Setup the AUD_IO control */ + status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, AUD_IO_CTRL, 2, + cx231xx_set_field(FLD_I2S_PORT_DIR, 0x00)| + cx231xx_set_field(FLD_I2S_OUT_SRC, 0x00)| + cx231xx_set_field(FLD_AUD_CHAN3_SRC,0x00)| + cx231xx_set_field(FLD_AUD_CHAN2_SRC, 0x00)| + cx231xx_set_field(FLD_AUD_CHAN1_SRC,0x03 ), 4); + + status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, PATH1_CTL1, 2, 0x1F063870, 4); + + /* setAudioStandard(_audio_standard); */ + + status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, PATH1_CTL1, 2, 0x00063870, 4); + switch(dev->model) + { + case CX231XX_BOARD_CNXT_RDE_250: + case CX231XX_BOARD_CNXT_RDU_250: + status = cx231xx_read_modify_write_i2c_dword(dev, HAMMERHEAD_I2C_ADDRESS, + CHIP_CTRL, FLD_SIF_EN, + cx231xx_set_field(FLD_SIF_EN, 1)); + break; + default: + break; + } + break; + + case AUDIO_INPUT_TUNER_FM: + /* use SIF for FM radio + setupFM(); + setAudioStandard(_audio_standard); + */ + break; + + case AUDIO_INPUT_MUTE: + status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, PATH1_CTL1, 2, 0x1F011012, 4); + break; + } + + /* Take it out of soft reset */ + status = cx231xx_read_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, GENERAL_CTL, 2, &gen_ctrl, 1); + gen_ctrl &= ~1; + status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, GENERAL_CTL, 2, gen_ctrl, 1); + + return status; +} + + + +/* Set resolution of the video */ +int cx231xx_resolution_set(struct cx231xx *dev) +{ + int width, height; + u32 hscale, vscale; + int status = 0; + + width = dev->width; + height = dev->height; + + get_scale(dev,width, height,&hscale, &vscale); + + /* set horzontal scale */ + status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, HSCALE_CTRL, 2, hscale, 4); + + /* set vertical scale */ + status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, VSCALE_CTRL, 2, vscale, 4); + + return status; +} + +/************************************************************************************* + * C H I P Specific C O N T R O L functions * + *************************************************************************************/ +int cx231xx_init_ctrl_pin_status(struct cx231xx *dev) +{ + u32 value; + int status = 0; + + status = cx231xx_read_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, PIN_CTRL, 2, &value, 4); + value |=(~dev->board.ctl_pin_status_mask); + status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, PIN_CTRL, 2, value, 4); + + return status; +} + +int cx231xx_set_agc_analog_digital_mux_select(struct cx231xx *dev, u8 analog_or_digital) +{ + int status = 0; + + /* first set the direction to output */ + status = cx231xx_set_gpio_direction(dev, dev->board.agc_analog_digital_select_gpio, 1); + + /* 0 - demod ; 1 - Analog mode */ + status = cx231xx_set_gpio_value(dev, dev->board.agc_analog_digital_select_gpio, + analog_or_digital); + + return status; +} + +int cx231xx_enable_i2c_for_tuner(struct cx231xx *dev, u8 I2CIndex) +{ + u8 value[4] ={0,0,0,0}; + int status = 0; + + cx231xx_info("Changing the i2c port for tuner to %d\n",I2CIndex); + + status = cx231xx_read_ctrl_reg(dev,VRT_GET_REGISTER, PWR_CTL_EN, value, 4); + if(status < 0) + return status; + + if(I2CIndex==I2C_1) { + if(value[0] & I2C_DEMOD_EN) { + value[0] &= ~I2C_DEMOD_EN; + status = cx231xx_write_ctrl_reg(dev,VRT_SET_REGISTER, PWR_CTL_EN,value,4); + } + } else { + if(!(value[0] & I2C_DEMOD_EN)) { + value[0] |= I2C_DEMOD_EN; + status = cx231xx_write_ctrl_reg(dev,VRT_SET_REGISTER, PWR_CTL_EN,value,4); + } + } + + return status; + +} + + +/************************************************************************************* + * D I F - B L O C K C O N T R O L functions * + *************************************************************************************/ +int cx231xx_dif_configure_C2HH_for_low_IF(struct cx231xx *dev, u32 mode, + u32 function_mode, u32 standard) +{ + int status = 0; + + if(mode == V4L2_TUNER_RADIO) { + /* C2HH */ + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + AFE_CTRL_C2HH_SRC_CTRL, 30, 31, 0x1); /* lo if big signal */ + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + AFE_CTRL_C2HH_SRC_CTRL, 23, 24, function_mode); /* FUNC_MODE = DIF */ + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + AFE_CTRL_C2HH_SRC_CTRL, 15, 22, 0xFF); /* IF_MODE */ + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + AFE_CTRL_C2HH_SRC_CTRL, 9, 9, 0x1); /* no inv */ + } + else { + switch(standard) { + case V4L2_STD_NTSC_M: /* 75 IRE Setup */ + case V4L2_STD_NTSC_M_JP: /* Japan, 0 IRE Setup */ + case V4L2_STD_PAL_M: + case V4L2_STD_PAL_N: + case V4L2_STD_PAL_Nc: + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + AFE_CTRL_C2HH_SRC_CTRL, 30, 31, 0x1); /* lo if big signal */ + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + AFE_CTRL_C2HH_SRC_CTRL, 23, 24, function_mode); /* FUNC_MODE = DIF */ + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + AFE_CTRL_C2HH_SRC_CTRL, 15, 22, 0xb); /* IF_MODE */ + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + AFE_CTRL_C2HH_SRC_CTRL, 9, 9, 0x1); /* no inv */ + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + AUD_IO_CTRL, 0, 31, 0x00000003); /* 0x124, AUD_CHAN1_SRC = 0x3 */ + break; + + case V4L2_STD_PAL_B: + case V4L2_STD_PAL_G: + /* C2HH setup */ + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + AFE_CTRL_C2HH_SRC_CTRL, 30, 31, 0x1); /* lo if big signal */ + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + AFE_CTRL_C2HH_SRC_CTRL, 23, 24, function_mode); /* FUNC_MODE = DIF */ + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + AFE_CTRL_C2HH_SRC_CTRL, 15, 22, 0xE); /* IF_MODE */ + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + AFE_CTRL_C2HH_SRC_CTRL, 9, 9, 0x1); /* no inv */ + break; + + case V4L2_STD_PAL_D: + case V4L2_STD_PAL_I: + case V4L2_STD_SECAM_L: + case V4L2_STD_SECAM_LC: + case V4L2_STD_SECAM_B: + case V4L2_STD_SECAM_D: + case V4L2_STD_SECAM_G: + case V4L2_STD_SECAM_K: + case V4L2_STD_SECAM_K1: + /* C2HH setup */ + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + AFE_CTRL_C2HH_SRC_CTRL, 30, 31, 0x1); /* lo if big signal */ + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + AFE_CTRL_C2HH_SRC_CTRL, 23, 24, function_mode); /* FUNC_MODE = DIF */ + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + AFE_CTRL_C2HH_SRC_CTRL, 15, 22, 0xF); /* IF_MODE */ + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + AFE_CTRL_C2HH_SRC_CTRL, 9, 9, 0x1); /* no inv */ + break; + + case DIF_USE_BASEBAND: + default: + /* do nothing to config C2HH for baseband */ + break; + } + } + + return status; +} + +int cx231xx_dif_set_standard(struct cx231xx *dev, u32 standard) +{ + int status = 0; + u32 dif_misc_ctrl_value = 0; + u32 func_mode = 0; + + cx231xx_info("%s: setStandard to %x\n",__func__,standard); + + status = cx231xx_read_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, + DIF_MISC_CTRL, 2, &dif_misc_ctrl_value, 4); + if(standard != DIF_USE_BASEBAND ) + dev->norm = standard; + + switch (dev->model) { + case CX231XX_BOARD_CNXT_RDE_250: + case CX231XX_BOARD_CNXT_RDU_250: + func_mode=0x03; + break; + default: + func_mode=0x01; + } + + status = cx231xx_dif_configure_C2HH_for_low_IF(dev, dev->active_mode, func_mode, standard); + + + if(standard == DIF_USE_BASEBAND ) { /* base band */ + + /* There is a different SRC_PHASE_INC value for baseband vs. DIF */ + status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, + DIF_SRC_PHASE_INC, 2, 0xDF7DF83, 4); + status = cx231xx_read_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, + DIF_MISC_CTRL, 2, &dif_misc_ctrl_value, 4); + dif_misc_ctrl_value |= FLD_DIF_DIF_BYPASS; + status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, + DIF_MISC_CTRL, 2, dif_misc_ctrl_value, 4); + + } else if ( standard & (V4L2_STD_PAL_B | V4L2_STD_PAL_G) ) { + + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_PLL_CTRL, 0, 31, 0x6503bc0c); + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_PLL_CTRL1, 0, 31, 0xbd038c85); + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_PLL_CTRL2, 0, 31, 0x1db4640a); + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_PLL_CTRL3, 0, 31, 0x00008800); + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_AGC_IF_REF, 0, 31, 0x444C1380); + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_AGC_CTRL_IF, 0, 31, 0xDA302600); + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_AGC_CTRL_INT, 0, 31, 0xDA261700); + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_AGC_CTRL_RF, 0, 31, 0xDA262600); + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_AGC_IF_INT_CURRENT, 0, 31, 0x26001700); + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_AGC_RF_CURRENT, 0, 31, 0x00002660); + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_VIDEO_AGC_CTRL, 0, 31, 0x72500800); + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_VID_AUD_OVERRIDE, 0, 31, 0x27000100); + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_AV_SEP_CTRL, 0, 31, 0x3F3530EC); + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_COMP_FLT_CTRL, 0, 31, 0x00A653A8); + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_SRC_PHASE_INC, 0, 31, 0x1befbf06); + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_SRC_GAIN_CONTROL, 0, 31, 0x000035e8); + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_RPT_VARIANCE, 0, 31, 0x00000000); + /* Save the Spec Inversion value */ + dif_misc_ctrl_value &= FLD_DIF_SPEC_INV; + dif_misc_ctrl_value |=0x3a013F11; + + } else if( standard & V4L2_STD_PAL_D ) { + + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_PLL_CTRL, 0, 31, 0x6503bc0c); + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_PLL_CTRL1, 0, 31, 0xbd038c85); + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_PLL_CTRL2, 0, 31, 0x1db4640a); + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_PLL_CTRL3, 0, 31, 0x00008800); + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_AGC_IF_REF, 0, 31, 0x444C1380); + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_AGC_CTRL_IF, 0, 31, 0xDA302600); + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_AGC_CTRL_INT, 0, 31, 0xDA261700); + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_AGC_CTRL_RF, 0, 31, 0xDA262600); + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_AGC_IF_INT_CURRENT, 0, 31, 0x26001700); + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_AGC_RF_CURRENT, 0, 31, 0x00002660); + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_VIDEO_AGC_CTRL, 0, 31, 0x72500800); + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_VID_AUD_OVERRIDE, 0, 31, 0x27000100); + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_AV_SEP_CTRL, 0, 31, 0x3F3934EA); + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_COMP_FLT_CTRL, 0, 31, 0x00000000); + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_SRC_PHASE_INC, 0, 31, 0x1befbf06); + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_SRC_GAIN_CONTROL, 0, 31, 0x000035e8); + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_RPT_VARIANCE, 0, 31, 0x00000000); + /* Save the Spec Inversion value */ + dif_misc_ctrl_value &= FLD_DIF_SPEC_INV; + dif_misc_ctrl_value |=0x3a023F11; + + } else if( standard & V4L2_STD_PAL_I ) { + + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_PLL_CTRL, 0, 31, 0x6503bc0c); + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_PLL_CTRL1, 0, 31, 0xbd038c85); + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_PLL_CTRL2, 0, 31, 0x1db4640a); + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_PLL_CTRL3, 0, 31, 0x00008800); + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_AGC_IF_REF, 0, 31, 0x444C1380); + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_AGC_CTRL_IF, 0, 31, 0xDA302600); + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_AGC_CTRL_INT, 0, 31, 0xDA261700); + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_AGC_CTRL_RF, 0, 31, 0xDA262600); + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_AGC_IF_INT_CURRENT, 0, 31, 0x26001700); + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_AGC_RF_CURRENT, 0, 31, 0x00002660); + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_VIDEO_AGC_CTRL, 0, 31, 0x72500800); + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_VID_AUD_OVERRIDE, 0, 31, 0x27000100); + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_AV_SEP_CTRL, 0, 31, 0x5F39A934); + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_COMP_FLT_CTRL, 0, 31, 0x00000000); + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_SRC_PHASE_INC, 0, 31, 0x1befbf06); + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_SRC_GAIN_CONTROL, 0, 31, 0x000035e8); + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_RPT_VARIANCE, 0, 31, 0x00000000); + /* Save the Spec Inversion value */ + dif_misc_ctrl_value &= FLD_DIF_SPEC_INV; + dif_misc_ctrl_value |=0x3a033F11; + + } else if( standard & V4L2_STD_PAL_M ) { + + /* improved Low Frequency Phase Noise */ + status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, + DIF_PLL_CTRL, 2, 0xFF01FF0C, 4); + status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, + DIF_PLL_CTRL1, 2, 0xbd038c85, 4); + status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, + DIF_PLL_CTRL2, 2, 0x1db4640a, 4); + status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, + DIF_PLL_CTRL3, 2, 0x00008800, 4); + status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, + DIF_AGC_IF_REF, 2, 0x444C1380, 4); + status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, + DIF_AGC_IF_INT_CURRENT, 2, 0x26001700, 4); + status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, + DIF_AGC_RF_CURRENT, 2, 0x00002660, 4); + status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, + DIF_VIDEO_AGC_CTRL, 2, 0x72500800, 4); + status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, + DIF_VID_AUD_OVERRIDE, 2, 0x27000100, 4); + status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, + DIF_AV_SEP_CTRL, 2, 0x012c405d, 4); + status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, + DIF_COMP_FLT_CTRL, 2, 0x009f50c1, 4); + status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, + DIF_SRC_PHASE_INC, 2, 0x1befbf06, 4); + status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, + DIF_SRC_GAIN_CONTROL, 2, 0x000035e8, 4); + status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, + DIF_SOFT_RST_CTRL_REVB, 2, 0x00000000, 4); + + /* Save the Spec Inversion value */ + dif_misc_ctrl_value &= FLD_DIF_SPEC_INV; + dif_misc_ctrl_value |= 0x3A0A3F10; + + } else if( standard & (V4L2_STD_PAL_N | V4L2_STD_PAL_Nc) ) { + + /* improved Low Frequency Phase Noise */ + status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, DIF_PLL_CTRL, 2, 0xFF01FF0C, 4); + status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, DIF_PLL_CTRL1, 2, 0xbd038c85, 4); + status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, DIF_PLL_CTRL2, 2, 0x1db4640a, 4); + status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, DIF_PLL_CTRL3, 2, 0x00008800, 4); + status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, DIF_AGC_IF_REF, 2, 0x444C1380, 4); + status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, DIF_AGC_IF_INT_CURRENT, 2, 0x26001700, 4); + status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, DIF_AGC_RF_CURRENT, 2, 0x00002660, 4); + status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, DIF_VIDEO_AGC_CTRL, 2, 0x72500800, 4); + status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, DIF_VID_AUD_OVERRIDE, 2, 0x27000100, 4); + status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, DIF_AV_SEP_CTRL, 2, 0x012c405d, 4); + status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, DIF_COMP_FLT_CTRL, 2, 0x009f50c1, 4); + status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, DIF_SRC_PHASE_INC, 2, 0x1befbf06, 4); + status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, DIF_SRC_GAIN_CONTROL, 2, 0x000035e8, 4); + status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, DIF_SOFT_RST_CTRL_REVB, 2, 0x00000000, 4); + + /* Save the Spec Inversion value */ + dif_misc_ctrl_value &= FLD_DIF_SPEC_INV; + dif_misc_ctrl_value = 0x3A093F10; + + } else if( standard & ( V4L2_STD_SECAM_B | V4L2_STD_SECAM_D | V4L2_STD_SECAM_G | + V4L2_STD_SECAM_K | V4L2_STD_SECAM_K1) ) { + + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_PLL_CTRL, 0, 31, 0x6503bc0c); + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_PLL_CTRL1, 0, 31, 0xbd038c85); + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_PLL_CTRL2, 0, 31, 0x1db4640a); + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_PLL_CTRL3, 0, 31, 0x00008800); + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_AGC_IF_REF, 0, 31, 0x888C0380); + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_AGC_CTRL_IF, 0, 31, 0xe0262600); + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_AGC_CTRL_INT, 0, 31, 0xc2171700); + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_AGC_CTRL_RF, 0, 31, 0xc2262600); + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_AGC_IF_INT_CURRENT, 0, 31, 0x26001700); + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_AGC_RF_CURRENT, 0, 31, 0x00002660); + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_VID_AUD_OVERRIDE, 0, 31, 0x27000100); + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_AV_SEP_CTRL, 0, 31, 0x3F3530ec); + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_COMP_FLT_CTRL, 0, 31, 0x00000000); + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_SRC_PHASE_INC, 0, 31, 0x1befbf06); + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_SRC_GAIN_CONTROL, 0, 31, 0x000035e8); + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_RPT_VARIANCE, 0, 31, 0x00000000); + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_VIDEO_AGC_CTRL, 0, 31, 0xf4000000); + + /* Save the Spec Inversion value */ + dif_misc_ctrl_value &= FLD_DIF_SPEC_INV; + dif_misc_ctrl_value |=0x3a023F11; + + } else if( standard & (V4L2_STD_SECAM_L | V4L2_STD_SECAM_LC) ) { + + /* Is it SECAM_L1? */ + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_PLL_CTRL, 0, 31, 0x6503bc0c); + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_PLL_CTRL1, 0, 31, 0xbd038c85); + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_PLL_CTRL2, 0, 31, 0x1db4640a); + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_PLL_CTRL3, 0, 31, 0x00008800); + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_AGC_IF_REF, 0, 31, 0x888C0380); + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_AGC_CTRL_IF, 0, 31, 0xe0262600); + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_AGC_CTRL_INT, 0, 31, 0xc2171700); + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_AGC_CTRL_RF, 0, 31, 0xc2262600); + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_AGC_IF_INT_CURRENT, 0, 31, 0x26001700); + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_AGC_RF_CURRENT, 0, 31, 0x00002660); + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_VID_AUD_OVERRIDE, 0, 31, 0x27000100); + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_AV_SEP_CTRL, 0, 31, 0x3F3530ec); + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_COMP_FLT_CTRL, 0, 31, 0x00000000); + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_SRC_PHASE_INC, 0, 31, 0x1befbf06); + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_SRC_GAIN_CONTROL, 0, 31, 0x000035e8); + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_RPT_VARIANCE, 0, 31, 0x00000000); + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_VIDEO_AGC_CTRL, 0, 31, 0xf2560000); + + /* Save the Spec Inversion value */ + dif_misc_ctrl_value &= FLD_DIF_SPEC_INV; + dif_misc_ctrl_value |=0x3a023F11; + + } else { /* V4L2_STD_NTSC_M (75 IRE Setup) Or V4L2_STD_NTSC_M_JP (Japan, 0 IRE Setup) */ + + /* For NTSC the centre frequency of video coming out of sidewinder is + around 7.1MHz or 3.6MHz depending on the spectral inversion. + so for a non spectrally inverted channel the pll freq word is 0x03420c49 + */ + + status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, DIF_PLL_CTRL, 2, 0x6503BC0C, 4); + status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, DIF_PLL_CTRL1, 2, 0xBD038C85, 4); + status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, DIF_PLL_CTRL2, 2, 0x1DB4640A, 4); + status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, DIF_PLL_CTRL3, 2, 0x00008800, 4); + status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, DIF_AGC_IF_REF, 2, 0x444C0380, 4); + status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, DIF_AGC_IF_INT_CURRENT, 2, 0x26001700, 4); + status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, DIF_AGC_RF_CURRENT, 2, 0x00002660, 4); + status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, DIF_VIDEO_AGC_CTRL, 2, 0x04000800, 4); + status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, DIF_VID_AUD_OVERRIDE, 2, 0x27000100, 4); + status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, DIF_AV_SEP_CTRL, 2, 0x01296e1f, 4); + + status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, DIF_COMP_FLT_CTRL, 2, 0x009f50c1, 4); + status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, DIF_SRC_PHASE_INC, 2, 0x1befbf06, 4); + status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, DIF_SRC_GAIN_CONTROL, 2, 0x000035e8, 4); + + status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, DIF_AGC_CTRL_IF, 2, 0xC2262600, 4); + status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, DIF_AGC_CTRL_INT, 2, 0xC2262600, 4); + status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, DIF_AGC_CTRL_RF, 2, 0xC2262600, 4); + + /* Save the Spec Inversion value */ + dif_misc_ctrl_value &= FLD_DIF_SPEC_INV; + dif_misc_ctrl_value |= 0x3a003F10; + + } + + /* The AGC values should be the same for all standards, + AUD_SRC_SEL[19] should always be disabled */ + dif_misc_ctrl_value &= ~FLD_DIF_AUD_SRC_SEL; + + /* It is still possible to get Set Standard calls even when we are in FM mode + This is done to override the value for FM. */ + if (dev->active_mode == V4L2_TUNER_RADIO) + dif_misc_ctrl_value = 0x7a080000; + + /* Write the calculated value for misc ontrol register */ + status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, DIF_MISC_CTRL, 2, dif_misc_ctrl_value, 4); + + return status; +} + +int cx231xx_tuner_pre_channel_change(struct cx231xx *dev) +{ + int status = 0; + u32 dwval; + + /* Set the RF and IF k_agc values to 3 */ + status = cx231xx_read_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, + DIF_AGC_IF_REF, 2, &dwval, 4); + dwval &= ~(FLD_DIF_K_AGC_RF | FLD_DIF_K_AGC_IF); + dwval |= 0x33000000; + + status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, + DIF_AGC_IF_REF, 2, dwval, 4); + + return status; +} + +int cx231xx_tuner_post_channel_change(struct cx231xx *dev) +{ + int status = 0; + u32 dwval; + + /* Set the RF and IF k_agc values to 4 for PAL/NTSC and 8 for SECAM */ + status = cx231xx_read_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, + DIF_AGC_IF_REF, 2, &dwval, 4); + dwval &= ~(FLD_DIF_K_AGC_RF | FLD_DIF_K_AGC_IF); + + if(dev->norm & ( V4L2_STD_SECAM_L | V4L2_STD_SECAM_B | V4L2_STD_SECAM_D) ) { + dwval |= 0x88000000; + } else { + dwval |= 0x44000000; + } + + status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, + DIF_AGC_IF_REF, 2, dwval, 4); + + return status; +} + + + +/************************************************************************************* + * F L A T I R O N - B L O C K C O N T R O L functions * + *************************************************************************************/ +int cx231xx_flatiron_initialize(struct cx231xx *dev) +{ + int status = 0; + u32 value; + + status = cx231xx_read_i2c_data(dev, Flatrion_DEVICE_ADDRESS, CH_PWR_CTRL1, 1, &value, 1); + /* enables clock to delta-sigma and decimation filter */ + value |= 0x80; + status = cx231xx_write_i2c_data(dev, Flatrion_DEVICE_ADDRESS, + CH_PWR_CTRL1, 1, value, 1); + /* power up all channel */ + status = cx231xx_write_i2c_data(dev, Flatrion_DEVICE_ADDRESS, + CH_PWR_CTRL2, 1, 0x00, 1); + + return status; +} + +int cx231xx_flatiron_update_power_control(struct cx231xx *dev, AV_MODE avmode) +{ + int status = 0; + u32 value=0; + + if(avmode!=POLARIS_AVMODE_ENXTERNAL_AV) { + status = cx231xx_read_i2c_data(dev, Flatrion_DEVICE_ADDRESS, CH_PWR_CTRL2, 1, &value, 1); + value |= 0xfe; + status = cx231xx_write_i2c_data(dev, Flatrion_DEVICE_ADDRESS, + CH_PWR_CTRL2, 1, value, 1); + } + else { + status = cx231xx_write_i2c_data(dev, Flatrion_DEVICE_ADDRESS, + CH_PWR_CTRL2, 1, 0x00, 1); + } + + return status; +} + +/* set flatiron for audio input types */ +int cx231xx_flatiron_set_audio_input(struct cx231xx *dev, u8 audio_input) +{ + int status = 0; + + switch(audio_input) { + case CX231XX_AMUX_LINE_IN: + + status = cx231xx_write_i2c_data(dev, Flatrion_DEVICE_ADDRESS, + CH_PWR_CTRL2, 1, 0x00, 1); + status = cx231xx_write_i2c_data(dev, Flatrion_DEVICE_ADDRESS, + CH_PWR_CTRL1, 1, 0x80, 1); + break; + case CX231XX_AMUX_VIDEO: + default: + break; + } + + dev->ctl_ainput = audio_input; + + return status; +} + +/************************************************************************************* + * P O W E R C O N T R O L functions * + *************************************************************************************/ +int cx231xx_set_power_mode(struct cx231xx *dev, AV_MODE mode) +{ + u8 value[4] ={0,0,0,0}; + u32 tmp = 0; + int status = 0; + + if(dev->power_mode != mode) + dev->power_mode = mode; + else { + cx231xx_info(" setPowerMode::mode = %d, No Change req.\n",mode); + return 0; + } + + cx231xx_info(" setPowerMode::mode = %d\n",mode); + + status = cx231xx_read_ctrl_reg(dev,VRT_GET_REGISTER, PWR_CTL_EN, value, 4); + if(status < 0) + return status; + + tmp = *((u32 *)value); + + switch(mode) { + case POLARIS_AVMODE_ENXTERNAL_AV: + + tmp &= (~PWR_MODE_MASK); + + tmp |= PWR_AV_EN; + value[0]=(u8)tmp; + value[1]=(u8)(tmp>>8); + value[2]=(u8)(tmp>>16); + value[3]=(u8)(tmp>>24); + status = cx231xx_write_ctrl_reg(dev,VRT_SET_REGISTER, PWR_CTL_EN,value,4); + msleep(PWR_SLEEP_INTERVAL); + + tmp |= PWR_ISO_EN; + value[0]=(u8)tmp; + value[1]=(u8)(tmp>>8); + value[2]=(u8)(tmp>>16); + value[3]=(u8)(tmp>>24); + status = cx231xx_write_ctrl_reg(dev,VRT_SET_REGISTER, PWR_CTL_EN,value,4); + msleep(PWR_SLEEP_INTERVAL); + + tmp |=POLARIS_AVMODE_ENXTERNAL_AV; + value[0]=(u8)tmp; + value[1]=(u8)(tmp>>8); + value[2]=(u8)(tmp>>16); + value[3]=(u8)(tmp>>24); + status = cx231xx_write_ctrl_reg(dev,VRT_SET_REGISTER, PWR_CTL_EN,value,4); + + dev->xc_fw_load_done = 0; /* reset state of xceive tuner */ + break; + + case POLARIS_AVMODE_ANALOGT_TV: + + tmp &= (~PWR_DEMOD_EN); + tmp |= (I2C_DEMOD_EN); + value[0]=(u8)tmp; + value[1]=(u8)(tmp>>8); + value[2]=(u8)(tmp>>16); + value[3]=(u8)(tmp>>24); + status = cx231xx_write_ctrl_reg(dev,VRT_SET_REGISTER, PWR_CTL_EN,value,4); + msleep(PWR_SLEEP_INTERVAL); + + if(!(tmp & PWR_TUNER_EN)) { + tmp |= (PWR_TUNER_EN); + value[0]=(u8)tmp; + value[1]=(u8)(tmp>>8); + value[2]=(u8)(tmp>>16); + value[3]=(u8)(tmp>>24); + status = cx231xx_write_ctrl_reg(dev,VRT_SET_REGISTER, PWR_CTL_EN,value,4); + msleep(PWR_SLEEP_INTERVAL); + } + + if(!(tmp & PWR_AV_EN)) { + tmp |= PWR_AV_EN; + value[0]=(u8)tmp; + value[1]=(u8)(tmp>>8); + value[2]=(u8)(tmp>>16); + value[3]=(u8)(tmp>>24); + status = cx231xx_write_ctrl_reg(dev,VRT_SET_REGISTER, PWR_CTL_EN,value,4); + msleep(PWR_SLEEP_INTERVAL); + } + if(!(tmp & PWR_ISO_EN )) { + tmp |= PWR_ISO_EN; + value[0]=(u8)tmp; + value[1]=(u8)(tmp>>8); + value[2]=(u8)(tmp>>16); + value[3]=(u8)(tmp>>24); + status = cx231xx_write_ctrl_reg(dev,VRT_SET_REGISTER, PWR_CTL_EN,value,4); + msleep(PWR_SLEEP_INTERVAL); + } + + if(!(tmp & POLARIS_AVMODE_ANALOGT_TV )) { + tmp |= POLARIS_AVMODE_ANALOGT_TV; + value[0]=(u8)tmp; + value[1]=(u8)(tmp>>8); + value[2]=(u8)(tmp>>16); + value[3]=(u8)(tmp>>24); + status = cx231xx_write_ctrl_reg(dev,VRT_SET_REGISTER, PWR_CTL_EN,value,4); + msleep(PWR_SLEEP_INTERVAL); + } + + if( (dev->model == CX231XX_BOARD_CNXT_RDE_250) || + (dev->model == CX231XX_BOARD_CNXT_RDU_250)) { + + /* tuner path to channel 1 from port 3 */ + cx231xx_enable_i2c_for_tuner(dev, I2C_3); + + if(dev->cx231xx_reset_analog_tuner) + dev->cx231xx_reset_analog_tuner(dev); + } + break; + + case POLARIS_AVMODE_DIGITAL: + + if(!(tmp & PWR_TUNER_EN)) { + tmp |= (PWR_TUNER_EN); + value[0]=(u8)tmp; + value[1]=(u8)(tmp>>8); + value[2]=(u8)(tmp>>16); + value[3]=(u8)(tmp>>24); + status = cx231xx_write_ctrl_reg(dev,VRT_SET_REGISTER, PWR_CTL_EN,value,4); + msleep(PWR_SLEEP_INTERVAL); + } + if(!(tmp & PWR_AV_EN)) { + tmp |= PWR_AV_EN; + value[0]=(u8)tmp; + value[1]=(u8)(tmp>>8); + value[2]=(u8)(tmp>>16); + value[3]=(u8)(tmp>>24); + status = cx231xx_write_ctrl_reg(dev,VRT_SET_REGISTER, PWR_CTL_EN,value,4); + msleep(PWR_SLEEP_INTERVAL); + } + if(!(tmp & PWR_ISO_EN)) { + tmp |= PWR_ISO_EN; + value[0]=(u8)tmp; + value[1]=(u8)(tmp>>8); + value[2]=(u8)(tmp>>16); + value[3]=(u8)(tmp>>24); + status = cx231xx_write_ctrl_reg(dev,VRT_SET_REGISTER, PWR_CTL_EN,value,4); + msleep(PWR_SLEEP_INTERVAL); + } + + tmp |= POLARIS_AVMODE_DIGITAL|I2C_DEMOD_EN; + value[0]=(u8)tmp; + value[1]=(u8)(tmp>>8); + value[2]=(u8)(tmp>>16); + value[3]=(u8)(tmp>>24); + status = cx231xx_write_ctrl_reg(dev,VRT_SET_REGISTER, PWR_CTL_EN,value,4); + msleep(PWR_SLEEP_INTERVAL); + + if(!(tmp & PWR_DEMOD_EN)) { + tmp |= PWR_DEMOD_EN; + value[0]=(u8)tmp; + value[1]=(u8)(tmp>>8); + value[2]=(u8)(tmp>>16); + value[3]=(u8)(tmp>>24); + status = cx231xx_write_ctrl_reg(dev,VRT_SET_REGISTER, PWR_CTL_EN,value,4); + msleep(PWR_SLEEP_INTERVAL); + } + + if( (dev->model == CX231XX_BOARD_CNXT_RDE_250) || + (dev->model == CX231XX_BOARD_CNXT_RDU_250)) { + + /* tuner path to channel 1 from port 3 */ + cx231xx_enable_i2c_for_tuner(dev, I2C_3); + + if(dev->cx231xx_reset_analog_tuner) + dev->cx231xx_reset_analog_tuner(dev); + } + break; + + default: + break; + } + + msleep(PWR_SLEEP_INTERVAL); + + /* For power saving, only enable Pwr_resetout_n when digital TV is selected. */ + if(mode == POLARIS_AVMODE_DIGITAL) { + tmp |= PWR_RESETOUT_EN; + value[0]=(u8)tmp; + value[1]=(u8)(tmp>>8); + value[2]=(u8)(tmp>>16); + value[3]=(u8)(tmp>>24); + status = cx231xx_write_ctrl_reg(dev,VRT_SET_REGISTER, PWR_CTL_EN,value,4); + msleep(PWR_SLEEP_INTERVAL); + } + + /* update power control for colibri */ + status = cx231xx_colibri_update_power_control(dev, mode); + + /* update power control for flatiron */ + status = cx231xx_flatiron_update_power_control(dev, mode); + + status = cx231xx_read_ctrl_reg(dev,VRT_GET_REGISTER, PWR_CTL_EN, value, 4); + cx231xx_info(" The data of PWR_CTL_EN register 0x74=0x%0x,0x%0x,0x%0x,0x%0x\n",value[0],value[1],value[2],value[3]); + + return status; +} + +int cx231xx_power_suspend(struct cx231xx *dev) +{ + u8 value[4] ={0,0,0,0}; + u32 tmp = 0; + int status = 0; + + status = cx231xx_read_ctrl_reg(dev,VRT_GET_REGISTER, PWR_CTL_EN, value, 4); + if(status > 0) + return status; + + tmp = *((u32 *)value); + tmp &= (~PWR_MODE_MASK); + + value[0]=(u8)tmp; + value[1]=(u8)(tmp>>8); + value[2]=(u8)(tmp>>16); + value[3]=(u8)(tmp>>24); + status = cx231xx_write_ctrl_reg(dev,VRT_SET_REGISTER, PWR_CTL_EN,value,4); + + return status; +} + + +/************************************************************************************* + * S T R E A M C O N T R O L functions * + *************************************************************************************/ +int cx231xx_start_stream(struct cx231xx *dev, u32 ep_mask) +{ + u8 value[4] = {0x0, 0x0, 0x0, 0x0}; + u32 tmp =0; + int status = 0; + + cx231xx_info("cx231xx_start_stream():: ep_mask = %x\n", ep_mask); + status = cx231xx_read_ctrl_reg(dev,VRT_GET_REGISTER, EP_MODE_SET,value,4); + if(status < 0) + return status; + + tmp = *((u32 *)value); + tmp |= ep_mask; + value[0]=(u8) tmp; + value[1]=(u8)(tmp>>8); + value[2]=(u8)(tmp>>16); + value[3]=(u8)(tmp>>24); + + status = cx231xx_write_ctrl_reg(dev,VRT_SET_REGISTER, EP_MODE_SET,value,4); + + return status; +} + +int cx231xx_stop_stream(struct cx231xx *dev, u32 ep_mask) +{ + u8 value[4] = {0x0, 0x0, 0x0, 0x0}; + u32 tmp =0; + int status = 0; + + cx231xx_info("cx231xx_stop_stream():: ep_mask = %x\n", ep_mask); + status = cx231xx_read_ctrl_reg(dev,VRT_GET_REGISTER, EP_MODE_SET,value,4); + if(status < 0) + return status; + + tmp = *((u32 *)value); + tmp&= (~ep_mask); + value[0]=(u8) tmp; + value[1]=(u8)(tmp>>8); + value[2]=(u8)(tmp>>16); + value[3]=(u8)(tmp>>24); + + status = cx231xx_write_ctrl_reg(dev,VRT_SET_REGISTER, EP_MODE_SET,value,4); + + return status; +} + +int cx231xx_initialize_stream_xfer(struct cx231xx *dev, u32 media_type) +{ + int status = 0; + + if(dev->udev->speed == USB_SPEED_HIGH) + { + switch(media_type) + { + case 81: /* audio */ + cx231xx_info("%s: Audio enter HANC\n",__func__); + status = cx231xx_mode_register(dev, TS_MODE_REG, 0x9300); + break; + + case 2: /* vbi */ + cx231xx_info("%s: set vanc registers\n",__func__); + status = cx231xx_mode_register(dev, TS_MODE_REG, 0x300); + break; + + case 3: /* sliced cc */ + cx231xx_info("%s: set hanc registers\n",__func__); + status = cx231xx_mode_register(dev, TS_MODE_REG, 0x1300); + break; + + case 0: /* video */ + cx231xx_info("%s: set video registers\n",__func__); + status = cx231xx_mode_register(dev, TS_MODE_REG, 0x100); + break; + + case 4: /* ts1 */ + cx231xx_info("%s: set ts1 registers\n",__func__); + status = cx231xx_mode_register(dev, TS_MODE_REG, 0x101); + status = cx231xx_mode_register(dev, TS1_CFG_REG, 0x400); + break; + case 6: /* ts1 parallel mode */ + cx231xx_info("%s: set ts1 parrallel mode registers\n",__func__); + status = cx231xx_mode_register(dev, TS_MODE_REG, 0x100); + status = cx231xx_mode_register(dev, TS1_CFG_REG, 0x400); + break; + } + } + else + { + status = cx231xx_mode_register(dev, TS_MODE_REG, 0x101); + } + + return status; +} + + + + +int cx231xx_capture_start(struct cx231xx *dev, int start, u8 media_type) +{ + int rc; + u32 ep_mask = -1; + PPCB_CONFIG pcb_config; + + /* get EP for media type */ + pcb_config = &dev->current_pcb_config; + + if(pcb_config->config_num==1) + { + switch (media_type) + { + case 0: /* Video */ + ep_mask =ENABLE_EP4; /* ep4 [00:1000] */ + break; + case 1: /* Audio */ + ep_mask =ENABLE_EP3; /* ep3 [00:0100] */ + break; + case 2: /* Vbi */ + ep_mask = ENABLE_EP5; /* ep5 [01:0000] */ + break; + case 3: /* Sliced_cc */ + ep_mask = ENABLE_EP6; /* ep6 [10:0000] */ + break; + case 4: /* ts1 */ + case 6: /* ts1 parallel mode */ + ep_mask = ENABLE_EP1; /* ep1 [00:0001] */ + break; + case 5: /* ts2 */ + ep_mask = ENABLE_EP2; /* ep2 [00:0010] */ + break; + } + + } + else if(pcb_config->config_num>1) + { + switch (media_type) + { + case 0: /* Video */ + ep_mask = ENABLE_EP4; /* ep4 [00:1000] */ + break; + case 1: /* Audio */ + ep_mask = ENABLE_EP3; /* ep3 [00:0100] */ + break; + case 2: /* Vbi */ + ep_mask = ENABLE_EP5; /* ep5 [01:0000] */ + break; + case 3: /* Sliced_cc */ + ep_mask = ENABLE_EP6; /* ep6 [10:0000] */ + break; + case 4: /* ts1 */ + case 6: /* ts1 parallel mode */ + ep_mask = ENABLE_EP1; /* ep1 [00:0001] */ + break; + case 5: /* ts2 */ + ep_mask = ENABLE_EP2; /* ep2 [00:0010] */ + break; + } + + } + + if(start) { + rc = cx231xx_initialize_stream_xfer(dev, media_type); + + if(rc < 0) { + return rc; + } + + /* enable video capture */ + if(ep_mask > 0 ) + rc = cx231xx_start_stream(dev, ep_mask); + } + else { + /* disable video capture */ + if(ep_mask > 0 ) + rc = cx231xx_stop_stream(dev, ep_mask); + } + + if (dev->mode == CX231XX_ANALOG_MODE){ + /* do any in Analog mode */ + } + else { + /* do any in digital mode */ + } + + return rc; +} +EXPORT_SYMBOL_GPL(cx231xx_capture_start); + + +/************************************************************************************ +* G P I O B I T control functions * +*************************************************************************************/ +int cx231xx_set_gpio_bit(struct cx231xx *dev, u32 gpio_bit, u8* gpio_val) +{ + int status = 0; + + status = cx231xx_send_gpio_cmd(dev, gpio_bit, gpio_val, 4, 0, 0); + + return status; +} + +int cx231xx_get_gpio_bit(struct cx231xx *dev, u32 gpio_bit, u8* gpio_val) +{ + int status = 0; + + status = cx231xx_send_gpio_cmd(dev, gpio_bit, gpio_val, 4, 0, 1); + + return status; +} + +/* +* cx231xx_set_gpio_direction +* Sets the direction of the GPIO pin to input or output +* +* Parameters : +* pin_number : The GPIO Pin number to program the direction for +* from 0 to 31 +* pin_value : The Direction of the GPIO Pin under reference. +* 0 = Input direction +* 1 = Output direction +*/ +int cx231xx_set_gpio_direction(struct cx231xx *dev, + int pin_number, + int pin_value) +{ + int status = 0; + u32 value = 0; + + /* Check for valid pin_number - if 32 , bail out */ + if (pin_number >= 32) { + return -EINVAL; + } + + if (pin_value == 0) { /* input */ + value = dev->gpio_dir &(~(1<gpio_dir | (1<gpio_val); + + /* cache the value for future */ + dev->gpio_dir = value; + + return status; +} + + +/* +* SetGpioPinLogicValue +* Sets the value of the GPIO pin to Logic high or low. The Pin under +* reference should ALREADY BE SET IN OUTPUT MODE !!!!!!!!! +* +* Parameters : +* pin_number : The GPIO Pin number to program the direction for +* pin_value : The value of the GPIO Pin under reference. +* 0 = set it to 0 +* 1 = set it to 1 +*/ +int cx231xx_set_gpio_value(struct cx231xx *dev, + int pin_number, + int pin_value) +{ + int status = 0; + u32 value = 0; + + /* Check for valid pin_number - if 0xFF , bail out */ + if (pin_number >= 32) + return -EINVAL; + + /* first do a sanity check - if the Pin is not output, make it output */ + if ((dev->gpio_dir & (1<gpio_dir | (1<gpio_dir = value; + status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8*) &dev->gpio_val); + value = 0; + } + + if (pin_value == 0) { + value = dev->gpio_val & (~(1<gpio_val | (1<gpio_val=value; + + /* toggle bit0 of GP_IO */ + status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8*) &dev->gpio_val); + + return status; +} + + +/************************************************************************************ +* G P I O I2C related functions * +*************************************************************************************/ +int cx231xx_gpio_i2c_start(struct cx231xx *dev) +{ + int status = 0; + + /* set SCL to output 1 ; set SDA to output 1 */ + dev->gpio_dir |= 1<< dev->board.tuner_scl_gpio; + dev->gpio_dir |= 1<board.tuner_sda_gpio; + dev->gpio_val |= 1<board.tuner_scl_gpio; + dev->gpio_val |= 1<board.tuner_sda_gpio; + + status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8*) &dev->gpio_val); + if(status < 0){ + return -EINVAL; + } + + /* set SCL to output 1; set SDA to output 0 */ + dev->gpio_val |= 1<board.tuner_scl_gpio; + dev->gpio_val &= ~(1<board.tuner_sda_gpio); + + status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8*) &dev->gpio_val); + if(status < 0){ + return -EINVAL; + } + + /* set SCL to output 0; set SDA to output 0 */ + dev->gpio_val &= ~(1<board.tuner_scl_gpio); + dev->gpio_val &= ~(1<board.tuner_sda_gpio); + + status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8*) &dev->gpio_val); + if(status < 0){ + return -EINVAL; + } + + return status; +} + + +int cx231xx_gpio_i2c_end(struct cx231xx *dev) +{ + int status = 0; + + /* set SCL to output 0; set SDA to output 0 */ + dev->gpio_dir |= 1<board.tuner_scl_gpio; + dev->gpio_dir |= 1<board.tuner_sda_gpio; + + dev->gpio_val &= ~(1<board.tuner_scl_gpio); + dev->gpio_val &= ~(1<board.tuner_sda_gpio); + + status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8*) &dev->gpio_val); + if(status < 0){ + return -EINVAL; + } + + /* set SCL to output 1; set SDA to output 0 */ + dev->gpio_val |= 1<board.tuner_scl_gpio; + dev->gpio_val &= ~(1<board.tuner_sda_gpio); + + status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8*) &dev->gpio_val); + if(status < 0){ + return -EINVAL; + } + + /* set SCL to input ,release SCL cable control + set SDA to input ,release SDA cable control */ + dev->gpio_dir &= ~(1<board.tuner_scl_gpio); + dev->gpio_dir &= ~(1<board.tuner_sda_gpio); + + status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8*) &dev->gpio_val); + if(status < 0){ + return -EINVAL; + } + return status; +} + + +int cx231xx_gpio_i2c_write_byte(struct cx231xx *dev, u8 data) +{ + int status = 0; + u8 i; + + /* set SCL to output ; set SDA to output */ + dev->gpio_dir |= 1<board.tuner_scl_gpio; + dev->gpio_dir |= 1<board.tuner_sda_gpio; + + for(i = 0;i<8;i++) { + if(((data<gpio_val &= ~(1<board.tuner_scl_gpio); + dev->gpio_val &= ~(1<board.tuner_sda_gpio); + status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8*) &dev->gpio_val); + + /* set SCL to output 1; set SDA to output 0 */ + dev->gpio_val |= 1<board.tuner_scl_gpio; + status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8*) &dev->gpio_val); + + /* set SCL to output 0; set SDA to output 0 */ + dev->gpio_val &= ~(1<board.tuner_scl_gpio); + status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8*) &dev->gpio_val); + } else { + /* set SCL to output 0; set SDA to output 1 */ + dev->gpio_val &= ~(1<board.tuner_scl_gpio); + dev->gpio_val |= 1<board.tuner_sda_gpio; + status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8*) &dev->gpio_val); + + /* set SCL to output 1; set SDA to output 1 */ + dev->gpio_val |= 1<board.tuner_scl_gpio; + status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8*) &dev->gpio_val); + + /* set SCL to output 0; set SDA to output 1 */ + dev->gpio_val &= ~(1<board.tuner_scl_gpio); + status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8*) &dev->gpio_val); + } + } + return status; +} + +int cx231xx_gpio_i2c_read_byte(struct cx231xx *dev, u8 *buf) +{ + u8 value = 0; + int status = 0; + u32 gpio_logic_value =0; + u8 i; + + /* read byte */ + for(i=0;i<8;i++) { /* send write I2c addr */ + + /* set SCL to output 0; set SDA to input */ + dev->gpio_val &= ~(1<board.tuner_scl_gpio); + status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8*) &dev->gpio_val); + + /* set SCL to output 1; set SDA to input */ + dev->gpio_val |= 1<board.tuner_scl_gpio; + status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8*) &dev->gpio_val); + + /* get SDA data bit */ + gpio_logic_value = dev->gpio_val; + status = cx231xx_get_gpio_bit(dev, dev->gpio_dir, (u8*) &dev->gpio_val); + if((dev->gpio_val & (1<board.tuner_sda_gpio)) != 0) { + value |= (1<<(8-i-1)); + } + + dev->gpio_val = gpio_logic_value; + } + + /* set SCL to output 0,finish the read latest SCL signal. + !!!set SDA to input,never to modify SDA direction at the same times */ + dev->gpio_val &= ~(1<board.tuner_scl_gpio); + status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8*) &dev->gpio_val); + + /* store the value */ + *buf = value & 0xff; + + return status; +} + +int cx231xx_gpio_i2c_read_ack(struct cx231xx *dev) +{ + int status = 0; + u32 gpio_logic_value = 0; + int nCnt=10; + int nInit=nCnt; + + /* clock stretch; set SCL to input; set SDA to input; get SCL value till SCL = 1 */ + dev->gpio_dir &= ~(1<board.tuner_sda_gpio); + dev->gpio_dir &= ~(1<board.tuner_scl_gpio); + + gpio_logic_value = dev->gpio_val; + status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8*) &dev->gpio_val); + + do{ + msleep(2); + status = cx231xx_get_gpio_bit(dev, dev->gpio_dir, (u8*) &dev->gpio_val); + nCnt--; + }while(((dev->gpio_val & (1<board.tuner_scl_gpio)) == 0) && (nCnt>0)); + + if(nCnt==0) { + cx231xx_info("No ACK after %d msec for clock stretch. GPIO I2C operation failed!",nInit*10); + } + + /* readAck + throuth clock stretch ,slave has given a SCL signal,so the SDA data can be directly read. */ + status = cx231xx_get_gpio_bit(dev, dev->gpio_dir, (u8*) &dev->gpio_val); + + if((dev->gpio_val & 1<< dev->board.tuner_sda_gpio) == 0){ + dev->gpio_val = gpio_logic_value; + dev->gpio_val &= ~(1<< dev->board.tuner_sda_gpio); + status = 0; + } else { + dev->gpio_val = gpio_logic_value; + dev->gpio_val |= (1<< dev->board.tuner_sda_gpio); + } + + /* read SDA end, set the SCL to output 0, after this operation, SDA direction can be changed. */ + dev->gpio_val = gpio_logic_value; + dev->gpio_dir |= (1<board.tuner_scl_gpio); + dev->gpio_val &= ~(1<board.tuner_scl_gpio); + status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8*) &dev->gpio_val); + + return status; +} + + +int cx231xx_gpio_i2c_write_ack(struct cx231xx *dev) +{ + int status = 0; + + /* set SDA to ouput */ + dev->gpio_dir |= 1<board.tuner_sda_gpio; + status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8*) &dev->gpio_val); + + /* set SCL = 0 (output); set SDA = 0 (output) */ + dev->gpio_val &= ~(1<board.tuner_sda_gpio); + dev->gpio_val &= ~(1<board.tuner_scl_gpio); + status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8*) &dev->gpio_val); + + /* set SCL = 1 (output); set SDA = 0 (output) */ + dev->gpio_val |= 1<board.tuner_scl_gpio; + status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8*) &dev->gpio_val); + + /* set SCL = 0 (output); set SDA = 0 (output) */ + dev->gpio_val &= ~(1<board.tuner_scl_gpio); + status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8*) &dev->gpio_val); + + /* set SDA to input,and then the slave will read data from SDA. */ + dev->gpio_dir &= ~(1<board.tuner_sda_gpio); + status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8*) &dev->gpio_val); + + return status; +} + +int cx231xx_gpio_i2c_write_nak(struct cx231xx *dev) +{ + int status = 0; + + /* set scl to output ; set sda to input */ + dev->gpio_dir |= 1<board.tuner_scl_gpio; + dev->gpio_dir &= ~(1<board.tuner_sda_gpio); + status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8*) &dev->gpio_val); + + /* set scl to output 0; set sda to input */ + dev->gpio_val &= ~(1<board.tuner_scl_gpio); + status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8*) &dev->gpio_val); + + /* set scl to output 1; set sda to input */ + dev->gpio_val |= 1<board.tuner_scl_gpio; + status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8*) &dev->gpio_val); + + return status; +} + + + +/************************************************************************************ +* G P I O I2C related functions * +*************************************************************************************/ +/* cx231xx_gpio_i2c_read + * Function to read data from gpio based I2C interface + */ +int cx231xx_gpio_i2c_read(struct cx231xx *dev, u8 dev_addr, u8 *buf ,u8 len) +{ + int status = 0; + int i = 0; + + /* get the lock */ + mutex_lock(&dev->gpio_i2c_lock); + + /* start */ + status = cx231xx_gpio_i2c_start(dev); + + /* write dev_addr */ + status = cx231xx_gpio_i2c_write_byte(dev, (dev_addr << 1) +1); + + /* readAck */ + status = cx231xx_gpio_i2c_read_ack(dev); + + /* read data */ + for(i = 0; i < len; i++ ) { + /* read data */ + buf[i] = 0; + status = cx231xx_gpio_i2c_read_byte(dev, & buf[i]); + + if( (i+1) != len) { + /* only do write ack if we more length */ + status = cx231xx_gpio_i2c_write_ack(dev); + } + } + + /* write NAK - inform reads are complete */ + status = cx231xx_gpio_i2c_write_nak(dev); + + /* write end */ + status = cx231xx_gpio_i2c_end(dev); + + /* release the lock */ + mutex_unlock(&dev->gpio_i2c_lock); + + return status; +} + + +/* cx231xx_gpio_i2c_write + * Function to write data to gpio based I2C interface + */ +int cx231xx_gpio_i2c_write(struct cx231xx *dev, u8 dev_addr, u8 *buf ,u8 len) +{ + int status = 0; + int i=0; + + /* get the lock */ + mutex_lock(&dev->gpio_i2c_lock); + + /* start */ + status = cx231xx_gpio_i2c_start(dev); + + /* write dev_addr */ + status = cx231xx_gpio_i2c_write_byte(dev, dev_addr << 1); + + /* read Ack */ + status = cx231xx_gpio_i2c_read_ack(dev); + + for(i = 0; i < len; i++ ) { + /* Write data */ + status = cx231xx_gpio_i2c_write_byte(dev, buf[i]); + + /* read Ack */ + status = cx231xx_gpio_i2c_read_ack(dev); + } + + /* write End */ + status = cx231xx_gpio_i2c_end(dev); + + /* release the lock */ + mutex_unlock(&dev->gpio_i2c_lock); + + return 0; +} + -- cgit v1.2.3 From 92ce95e9f4fce5fb4deea9cd33e0723190d93498 Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Tue, 3 Mar 2009 06:14:34 -0300 Subject: cx231xx: CodingStyle automatic fixes with Lindent From: Mauro Carvalho Chehab Signed-off-by: Mauro Carvalho Chehab --- linux/drivers/media/video/cx231xx/cx231xx-avcore.c | 4531 ++++++++++++-------- 1 file changed, 2652 insertions(+), 1879 deletions(-) (limited to 'linux/drivers/media/video/cx231xx/cx231xx-avcore.c') diff --git a/linux/drivers/media/video/cx231xx/cx231xx-avcore.c b/linux/drivers/media/video/cx231xx/cx231xx-avcore.c index 833967f46..3c09b9473 100644 --- a/linux/drivers/media/video/cx231xx/cx231xx-avcore.c +++ b/linux/drivers/media/video/cx231xx/cx231xx-avcore.c @@ -1,7 +1,7 @@ /* cx231xx_avcore.c - driver for Conexant Cx23100/101/102 USB video capture devices - Copyright (C) 2008 + Copyright (C) 2008 This program contains the specific code to control the avdecoder chip and other related usb control functions for cx231xx based chipset. @@ -38,115 +38,180 @@ #include "cx231xx.h" - /************************************************************************************* * C O L I B R I - B L O C K C O N T R O L functions * *************************************************************************************/ int cx231xx_colibri_init_super_block(struct cx231xx *dev, u32 ref_count) { - int status = 0; - u8 temp = 0; - u32 colibri_power_status = 0; - int i = 0; - - /* super block initialize */ - temp = (u8)(ref_count & 0xff); - status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, SUP_BLK_TUNE2, 2, temp, 1); - - status = cx231xx_read_i2c_data(dev, Colibri_DEVICE_ADDRESS, SUP_BLK_TUNE2, 2, &colibri_power_status, 1); - - temp = (u8)((ref_count & 0x300) >> 8); - temp |= 0x40; - status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, SUP_BLK_TUNE1, 2, temp, 1); - status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, SUP_BLK_PLL2, 2, 0x0f, 1); - - /* enable pll */ - while(colibri_power_status != 0x18) - { - status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, SUP_BLK_PWRDN, 2, 0x18, 1); - status = cx231xx_read_i2c_data(dev, Colibri_DEVICE_ADDRESS, SUP_BLK_PWRDN, 2, &colibri_power_status, 1); - colibri_power_status &= 0xff; - if(status < 0) { - cx231xx_info(": Init Super Block failed in sending/receiving cmds\n"); - break; - } - i++; - if( i == 10) { - cx231xx_info(": Init Super Block force break in loop !!!!\n"); - status = -1; - break; - } - } - - if(status < 0 ) - return status; - - /* start tuning filter */ - status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, SUP_BLK_TUNE3, 2, 0x40, 1); - msleep(5); - - /* exit tuning */ - status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, SUP_BLK_TUNE3, 2, 0x00, 1); - - return status; + int status = 0; + u8 temp = 0; + u32 colibri_power_status = 0; + int i = 0; + + /* super block initialize */ + temp = (u8) (ref_count & 0xff); + status = + cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, SUP_BLK_TUNE2, + 2, temp, 1); + + status = + cx231xx_read_i2c_data(dev, Colibri_DEVICE_ADDRESS, SUP_BLK_TUNE2, 2, + &colibri_power_status, 1); + + temp = (u8) ((ref_count & 0x300) >> 8); + temp |= 0x40; + status = + cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, SUP_BLK_TUNE1, + 2, temp, 1); + status = + cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, SUP_BLK_PLL2, 2, + 0x0f, 1); + + /* enable pll */ + while (colibri_power_status != 0x18) { + status = + cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, + SUP_BLK_PWRDN, 2, 0x18, 1); + status = + cx231xx_read_i2c_data(dev, Colibri_DEVICE_ADDRESS, + SUP_BLK_PWRDN, 2, + &colibri_power_status, 1); + colibri_power_status &= 0xff; + if (status < 0) { + cx231xx_info + (": Init Super Block failed in sending/receiving cmds\n"); + break; + } + i++; + if (i == 10) { + cx231xx_info + (": Init Super Block force break in loop !!!!\n"); + status = -1; + break; + } + } + + if (status < 0) + return status; + + /* start tuning filter */ + status = + cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, SUP_BLK_TUNE3, + 2, 0x40, 1); + msleep(5); + + /* exit tuning */ + status = + cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, SUP_BLK_TUNE3, + 2, 0x00, 1); + + return status; } int cx231xx_colibri_init_channels(struct cx231xx *dev) { - int status = 0; - - /* power up all 3 channels, clear pd_buffer */ - status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, ADC_PWRDN_CLAMP_CH1, 2, 0x00, 1); - status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, ADC_PWRDN_CLAMP_CH2, 2, 0x00, 1); - status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, ADC_PWRDN_CLAMP_CH3, 2, 0x00, 1); - - /* Enable quantizer calibration */ - status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, ADC_COM_QUANT, 2, 0x02, 1); - - /* channel initialize, force modulator (fb) reset */ - status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, ADC_FB_FRCRST_CH1, 2, 0x17, 1); - status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, ADC_FB_FRCRST_CH2, 2, 0x17, 1); - status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, ADC_FB_FRCRST_CH3, 2, 0x17, 1); - - /* start quantilizer calibration */ - status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, ADC_CAL_ATEST_CH1, 2, 0x10, 1); - status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, ADC_CAL_ATEST_CH2, 2, 0x10, 1); - status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, ADC_CAL_ATEST_CH3, 2, 0x10, 1); - msleep(5); - - /* exit modulator (fb) reset */ - status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, ADC_FB_FRCRST_CH1, 2, 0x07, 1); - status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, ADC_FB_FRCRST_CH2, 2, 0x07, 1); - status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, ADC_FB_FRCRST_CH3, 2, 0x07, 1); - - /* enable the pre_clamp in each channel for single-ended input */ - status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, ADC_NTF_PRECLMP_EN_CH1, 2, 0xf0, 1); - status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, ADC_NTF_PRECLMP_EN_CH2, 2, 0xf0, 1); - status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, ADC_NTF_PRECLMP_EN_CH3, 2, 0xf0, 1); - - /* use diode instead of resistor, so set term_en to 0, res_en to 0 */ - status = cx231xx_reg_mask_write(dev, Colibri_DEVICE_ADDRESS, 8, ADC_QGAIN_RES_TRM_CH1, 3, 7, 0x00); - status = cx231xx_reg_mask_write(dev, Colibri_DEVICE_ADDRESS, 8, ADC_QGAIN_RES_TRM_CH2, 3, 7, 0x00); - status = cx231xx_reg_mask_write(dev, Colibri_DEVICE_ADDRESS, 8, ADC_QGAIN_RES_TRM_CH3, 3, 7, 0x00); - - /* dynamic element matching off */ - status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, ADC_DCSERVO_DEM_CH1, 2, 0x03, 1); - status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, ADC_DCSERVO_DEM_CH2, 2, 0x03, 1); - status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, ADC_DCSERVO_DEM_CH3, 2, 0x03, 1); - - return status; + int status = 0; + + /* power up all 3 channels, clear pd_buffer */ + status = + cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, + ADC_PWRDN_CLAMP_CH1, 2, 0x00, 1); + status = + cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, + ADC_PWRDN_CLAMP_CH2, 2, 0x00, 1); + status = + cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, + ADC_PWRDN_CLAMP_CH3, 2, 0x00, 1); + + /* Enable quantizer calibration */ + status = + cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, ADC_COM_QUANT, + 2, 0x02, 1); + + /* channel initialize, force modulator (fb) reset */ + status = + cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, + ADC_FB_FRCRST_CH1, 2, 0x17, 1); + status = + cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, + ADC_FB_FRCRST_CH2, 2, 0x17, 1); + status = + cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, + ADC_FB_FRCRST_CH3, 2, 0x17, 1); + + /* start quantilizer calibration */ + status = + cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, + ADC_CAL_ATEST_CH1, 2, 0x10, 1); + status = + cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, + ADC_CAL_ATEST_CH2, 2, 0x10, 1); + status = + cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, + ADC_CAL_ATEST_CH3, 2, 0x10, 1); + msleep(5); + + /* exit modulator (fb) reset */ + status = + cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, + ADC_FB_FRCRST_CH1, 2, 0x07, 1); + status = + cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, + ADC_FB_FRCRST_CH2, 2, 0x07, 1); + status = + cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, + ADC_FB_FRCRST_CH3, 2, 0x07, 1); + + /* enable the pre_clamp in each channel for single-ended input */ + status = + cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, + ADC_NTF_PRECLMP_EN_CH1, 2, 0xf0, 1); + status = + cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, + ADC_NTF_PRECLMP_EN_CH2, 2, 0xf0, 1); + status = + cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, + ADC_NTF_PRECLMP_EN_CH3, 2, 0xf0, 1); + + /* use diode instead of resistor, so set term_en to 0, res_en to 0 */ + status = + cx231xx_reg_mask_write(dev, Colibri_DEVICE_ADDRESS, 8, + ADC_QGAIN_RES_TRM_CH1, 3, 7, 0x00); + status = + cx231xx_reg_mask_write(dev, Colibri_DEVICE_ADDRESS, 8, + ADC_QGAIN_RES_TRM_CH2, 3, 7, 0x00); + status = + cx231xx_reg_mask_write(dev, Colibri_DEVICE_ADDRESS, 8, + ADC_QGAIN_RES_TRM_CH3, 3, 7, 0x00); + + /* dynamic element matching off */ + status = + cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, + ADC_DCSERVO_DEM_CH1, 2, 0x03, 1); + status = + cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, + ADC_DCSERVO_DEM_CH2, 2, 0x03, 1); + status = + cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, + ADC_DCSERVO_DEM_CH3, 2, 0x03, 1); + + return status; } int cx231xx_colibri_setup_AFE_for_baseband(struct cx231xx *dev) -{ - u32 c_value = 0; - int status = 0; +{ + u32 c_value = 0; + int status = 0; - status = cx231xx_read_i2c_data(dev, Colibri_DEVICE_ADDRESS, ADC_PWRDN_CLAMP_CH2, 2, &c_value, 1); - c_value &= (~(0x50)); - status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, ADC_PWRDN_CLAMP_CH2, 2, c_value, 1); + status = + cx231xx_read_i2c_data(dev, Colibri_DEVICE_ADDRESS, + ADC_PWRDN_CLAMP_CH2, 2, &c_value, 1); + c_value &= (~(0x50)); + status = + cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, + ADC_PWRDN_CLAMP_CH2, 2, c_value, 1); - return status; + return status; } /* @@ -157,559 +222,802 @@ int cx231xx_colibri_setup_AFE_for_baseband(struct cx231xx *dev) */ int cx231xx_colibri_set_input_mux(struct cx231xx *dev, u32 input_mux) { - u8 ch1_setting = (u8)input_mux; - u8 ch2_setting = (u8)(input_mux >> 8); - u8 ch3_setting = (u8)(input_mux >> 16); - int status = 0; - u32 value = 0; - - if(ch1_setting != 0) - { - status = cx231xx_read_i2c_data(dev, Colibri_DEVICE_ADDRESS, ADC_INPUT_CH1, 2, &value, 1); - value &= (!INPUT_SEL_MASK); - value |= (ch1_setting-1)<<4; - value &= 0xff; - status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, ADC_INPUT_CH1, 2, value, 1); - } - - if(ch2_setting != 0) - { - status = cx231xx_read_i2c_data(dev, Colibri_DEVICE_ADDRESS, ADC_INPUT_CH2, 2, &value, 1); - value &= (!INPUT_SEL_MASK); - value |= (ch2_setting-1)<<4; - value &= 0xff; - status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, ADC_INPUT_CH2, 2, value, 1); - } - - /* For ch3_setting, the value to put in the register is 7 less than the input number */ - if(ch3_setting != 0) - { - status = cx231xx_read_i2c_data(dev, Colibri_DEVICE_ADDRESS, ADC_INPUT_CH3, 2, &value, 1); - value &= (!INPUT_SEL_MASK); - value |= (ch3_setting-1)<<4; - value &= 0xff; - status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, ADC_INPUT_CH3, 2, value, 1); - } - - return status; + u8 ch1_setting = (u8) input_mux; + u8 ch2_setting = (u8) (input_mux >> 8); + u8 ch3_setting = (u8) (input_mux >> 16); + int status = 0; + u32 value = 0; + + if (ch1_setting != 0) { + status = + cx231xx_read_i2c_data(dev, Colibri_DEVICE_ADDRESS, + ADC_INPUT_CH1, 2, &value, 1); + value &= (!INPUT_SEL_MASK); + value |= (ch1_setting - 1) << 4; + value &= 0xff; + status = + cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, + ADC_INPUT_CH1, 2, value, 1); + } + + if (ch2_setting != 0) { + status = + cx231xx_read_i2c_data(dev, Colibri_DEVICE_ADDRESS, + ADC_INPUT_CH2, 2, &value, 1); + value &= (!INPUT_SEL_MASK); + value |= (ch2_setting - 1) << 4; + value &= 0xff; + status = + cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, + ADC_INPUT_CH2, 2, value, 1); + } + + /* For ch3_setting, the value to put in the register is 7 less than the input number */ + if (ch3_setting != 0) { + status = + cx231xx_read_i2c_data(dev, Colibri_DEVICE_ADDRESS, + ADC_INPUT_CH3, 2, &value, 1); + value &= (!INPUT_SEL_MASK); + value |= (ch3_setting - 1) << 4; + value &= 0xff; + status = + cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, + ADC_INPUT_CH3, 2, value, 1); + } + + return status; } int cx231xx_colibri_set_mode(struct cx231xx *dev, enum AFE_MODE mode) { - int status = 0; - - switch(mode) { - case AFE_MODE_LOW_IF: - /* SetupAFEforLowIF(); */ - break; - case AFE_MODE_BASEBAND: - status = cx231xx_colibri_setup_AFE_for_baseband(dev); - break; - case AFE_MODE_EU_HI_IF: - /* SetupAFEforEuHiIF(); */ - break; - case AFE_MODE_US_HI_IF: - /* SetupAFEforUsHiIF(); */ - break; - case AFE_MODE_JAPAN_HI_IF: - /* SetupAFEforJapanHiIF(); */ - break; - } - - if((mode != dev->colibri_mode) && (dev->video_input == CX231XX_VMUX_TELEVISION)) { - status = cx231xx_colibri_adjust_ref_count(dev, CX231XX_VMUX_TELEVISION); - } - - dev->colibri_mode = mode; - - return status; + int status = 0; + + switch (mode) { + case AFE_MODE_LOW_IF: + /* SetupAFEforLowIF(); */ + break; + case AFE_MODE_BASEBAND: + status = cx231xx_colibri_setup_AFE_for_baseband(dev); + break; + case AFE_MODE_EU_HI_IF: + /* SetupAFEforEuHiIF(); */ + break; + case AFE_MODE_US_HI_IF: + /* SetupAFEforUsHiIF(); */ + break; + case AFE_MODE_JAPAN_HI_IF: + /* SetupAFEforJapanHiIF(); */ + break; + } + + if ((mode != dev->colibri_mode) + && (dev->video_input == CX231XX_VMUX_TELEVISION)) { + status = + cx231xx_colibri_adjust_ref_count(dev, + CX231XX_VMUX_TELEVISION); + } + + dev->colibri_mode = mode; + + return status; } /* For power saving in the EVK */ int cx231xx_colibri_update_power_control(struct cx231xx *dev, AV_MODE avmode) { - u32 colibri_power_status = 0; - int status = 0; - - switch (dev->model) { - case CX231XX_BOARD_CNXT_RDE_250: - case CX231XX_BOARD_CNXT_RDU_250: - - if(avmode==POLARIS_AVMODE_ANALOGT_TV) - { - while(colibri_power_status != 0x18) { - status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, - SUP_BLK_PWRDN, 2, 0x18, 1); - status = cx231xx_read_i2c_data(dev, Colibri_DEVICE_ADDRESS, - SUP_BLK_PWRDN, 2, &colibri_power_status, 1); - if(status < 0 ) - break; - } - - status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, - ADC_PWRDN_CLAMP_CH1, 2, 0x00, 1); - status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, - ADC_PWRDN_CLAMP_CH2, 2, 0x00, 1); - status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, - ADC_PWRDN_CLAMP_CH3, 2, 0x00, 1); - } - else if(avmode==POLARIS_AVMODE_DIGITAL) { - status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, - ADC_PWRDN_CLAMP_CH1, 2, 0x70, 1); - status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, - ADC_PWRDN_CLAMP_CH2, 2, 0x70, 1); - status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, - ADC_PWRDN_CLAMP_CH3, 2, 0x70, 1); - - status = cx231xx_read_i2c_data(dev, Colibri_DEVICE_ADDRESS, - SUP_BLK_PWRDN, 2, &colibri_power_status, 1); - colibri_power_status |=0x07; - status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, - SUP_BLK_PWRDN, 2, colibri_power_status, 1); - } - else if(avmode==POLARIS_AVMODE_ENXTERNAL_AV) { - - while(colibri_power_status != 0x18) { - status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, - SUP_BLK_PWRDN, 2, 0x18, 1); - status = cx231xx_read_i2c_data(dev, Colibri_DEVICE_ADDRESS, - SUP_BLK_PWRDN, 2, &colibri_power_status, 1); - if(status < 0 ) - break; - } - - status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, - ADC_PWRDN_CLAMP_CH1, 2, 0x00, 1); - status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, - ADC_PWRDN_CLAMP_CH2, 2, 0x00, 1); - status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, - ADC_PWRDN_CLAMP_CH3, 2, 0x00, 1); - } - else { - cx231xx_info("Invalid AV mode input\n"); - status = -1; - } - break; - default: - if(avmode==POLARIS_AVMODE_ANALOGT_TV) - { - while(colibri_power_status != 0x18) { - status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, - SUP_BLK_PWRDN, 2, 0x18, 1); - status = cx231xx_read_i2c_data(dev, Colibri_DEVICE_ADDRESS, - SUP_BLK_PWRDN, 2, &colibri_power_status, 1); - if(status < 0 ) - break; - } - - status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, - ADC_PWRDN_CLAMP_CH1, 2, 0x40, 1); - status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, - ADC_PWRDN_CLAMP_CH2, 2, 0x40, 1); - status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, - ADC_PWRDN_CLAMP_CH3, 2, 0x00, 1); - } - else if(avmode==POLARIS_AVMODE_DIGITAL) { - status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, - ADC_PWRDN_CLAMP_CH1, 2, 0x70, 1); - status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, - ADC_PWRDN_CLAMP_CH2, 2, 0x70, 1); - status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, - ADC_PWRDN_CLAMP_CH3, 2, 0x70, 1); - - status = cx231xx_read_i2c_data(dev, Colibri_DEVICE_ADDRESS, - SUP_BLK_PWRDN, 2, &colibri_power_status, 1); - colibri_power_status |=0x07; - status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, - SUP_BLK_PWRDN, 2, colibri_power_status, 1); - } - else if(avmode==POLARIS_AVMODE_ENXTERNAL_AV) { - while(colibri_power_status != 0x18) { - status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, - SUP_BLK_PWRDN, 2, 0x18, 1); - status = cx231xx_read_i2c_data(dev, Colibri_DEVICE_ADDRESS, - SUP_BLK_PWRDN, 2, &colibri_power_status, 1); - if(status < 0 ) - break; - } - - status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, - ADC_PWRDN_CLAMP_CH1, 2, 0x00, 1); - status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, - ADC_PWRDN_CLAMP_CH2, 2, 0x00, 1); - status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, - ADC_PWRDN_CLAMP_CH3, 2, 0x40, 1); - } - else { - cx231xx_info("Invalid AV mode input\n"); - status = -1; - } - } /* switch */ - - return status; + u32 colibri_power_status = 0; + int status = 0; + + switch (dev->model) { + case CX231XX_BOARD_CNXT_RDE_250: + case CX231XX_BOARD_CNXT_RDU_250: + + if (avmode == POLARIS_AVMODE_ANALOGT_TV) { + while (colibri_power_status != 0x18) { + status = + cx231xx_write_i2c_data(dev, + Colibri_DEVICE_ADDRESS, + SUP_BLK_PWRDN, 2, + 0x18, 1); + status = + cx231xx_read_i2c_data(dev, + Colibri_DEVICE_ADDRESS, + SUP_BLK_PWRDN, 2, + &colibri_power_status, + 1); + if (status < 0) + break; + } + + status = + cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, + ADC_PWRDN_CLAMP_CH1, 2, 0x00, + 1); + status = + cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, + ADC_PWRDN_CLAMP_CH2, 2, 0x00, + 1); + status = + cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, + ADC_PWRDN_CLAMP_CH3, 2, 0x00, + 1); + } else if (avmode == POLARIS_AVMODE_DIGITAL) { + status = + cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, + ADC_PWRDN_CLAMP_CH1, 2, 0x70, + 1); + status = + cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, + ADC_PWRDN_CLAMP_CH2, 2, 0x70, + 1); + status = + cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, + ADC_PWRDN_CLAMP_CH3, 2, 0x70, + 1); + + status = + cx231xx_read_i2c_data(dev, Colibri_DEVICE_ADDRESS, + SUP_BLK_PWRDN, 2, + &colibri_power_status, 1); + colibri_power_status |= 0x07; + status = + cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, + SUP_BLK_PWRDN, 2, + colibri_power_status, 1); + } else if (avmode == POLARIS_AVMODE_ENXTERNAL_AV) { + + while (colibri_power_status != 0x18) { + status = + cx231xx_write_i2c_data(dev, + Colibri_DEVICE_ADDRESS, + SUP_BLK_PWRDN, 2, + 0x18, 1); + status = + cx231xx_read_i2c_data(dev, + Colibri_DEVICE_ADDRESS, + SUP_BLK_PWRDN, 2, + &colibri_power_status, + 1); + if (status < 0) + break; + } + + status = + cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, + ADC_PWRDN_CLAMP_CH1, 2, 0x00, + 1); + status = + cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, + ADC_PWRDN_CLAMP_CH2, 2, 0x00, + 1); + status = + cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, + ADC_PWRDN_CLAMP_CH3, 2, 0x00, + 1); + } else { + cx231xx_info("Invalid AV mode input\n"); + status = -1; + } + break; + default: + if (avmode == POLARIS_AVMODE_ANALOGT_TV) { + while (colibri_power_status != 0x18) { + status = + cx231xx_write_i2c_data(dev, + Colibri_DEVICE_ADDRESS, + SUP_BLK_PWRDN, 2, + 0x18, 1); + status = + cx231xx_read_i2c_data(dev, + Colibri_DEVICE_ADDRESS, + SUP_BLK_PWRDN, 2, + &colibri_power_status, + 1); + if (status < 0) + break; + } + + status = + cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, + ADC_PWRDN_CLAMP_CH1, 2, 0x40, + 1); + status = + cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, + ADC_PWRDN_CLAMP_CH2, 2, 0x40, + 1); + status = + cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, + ADC_PWRDN_CLAMP_CH3, 2, 0x00, + 1); + } else if (avmode == POLARIS_AVMODE_DIGITAL) { + status = + cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, + ADC_PWRDN_CLAMP_CH1, 2, 0x70, + 1); + status = + cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, + ADC_PWRDN_CLAMP_CH2, 2, 0x70, + 1); + status = + cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, + ADC_PWRDN_CLAMP_CH3, 2, 0x70, + 1); + + status = + cx231xx_read_i2c_data(dev, Colibri_DEVICE_ADDRESS, + SUP_BLK_PWRDN, 2, + &colibri_power_status, 1); + colibri_power_status |= 0x07; + status = + cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, + SUP_BLK_PWRDN, 2, + colibri_power_status, 1); + } else if (avmode == POLARIS_AVMODE_ENXTERNAL_AV) { + while (colibri_power_status != 0x18) { + status = + cx231xx_write_i2c_data(dev, + Colibri_DEVICE_ADDRESS, + SUP_BLK_PWRDN, 2, + 0x18, 1); + status = + cx231xx_read_i2c_data(dev, + Colibri_DEVICE_ADDRESS, + SUP_BLK_PWRDN, 2, + &colibri_power_status, + 1); + if (status < 0) + break; + } + + status = + cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, + ADC_PWRDN_CLAMP_CH1, 2, 0x00, + 1); + status = + cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, + ADC_PWRDN_CLAMP_CH2, 2, 0x00, + 1); + status = + cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, + ADC_PWRDN_CLAMP_CH3, 2, 0x40, + 1); + } else { + cx231xx_info("Invalid AV mode input\n"); + status = -1; + } + } /* switch */ + + return status; } int cx231xx_colibri_adjust_ref_count(struct cx231xx *dev, u32 video_input) -{ - u32 input_mode = 0; - u32 ntf_mode = 0; - int status = 0; - - dev->video_input = video_input; - - if(video_input == CX231XX_VMUX_TELEVISION) { - status = cx231xx_read_i2c_data(dev, Colibri_DEVICE_ADDRESS, ADC_INPUT_CH3, 2, &input_mode, 1); - status = cx231xx_read_i2c_data(dev, Colibri_DEVICE_ADDRESS, - ADC_NTF_PRECLMP_EN_CH3, 2, &ntf_mode, 1); - } - else { - status = cx231xx_read_i2c_data(dev, Colibri_DEVICE_ADDRESS, ADC_INPUT_CH1, 2, &input_mode, 1); - status = cx231xx_read_i2c_data(dev, Colibri_DEVICE_ADDRESS, - ADC_NTF_PRECLMP_EN_CH1, 2, &ntf_mode, 1); - } - - input_mode = (ntf_mode & 0x3) | ((input_mode & 0x6) << 1); - - switch(input_mode) - { - case SINGLE_ENDED: - dev->colibri_ref_count = 0x23C; - break; - case LOW_IF: - dev->colibri_ref_count = 0x24C; - break; - case EU_IF: - dev->colibri_ref_count = 0x258; - break; - case US_IF: - dev->colibri_ref_count = 0x260; - break; - default: - break; - } - - status = cx231xx_colibri_init_super_block(dev, dev->colibri_ref_count); - - return status; -} +{ + u32 input_mode = 0; + u32 ntf_mode = 0; + int status = 0; + dev->video_input = video_input; + + if (video_input == CX231XX_VMUX_TELEVISION) { + status = + cx231xx_read_i2c_data(dev, Colibri_DEVICE_ADDRESS, + ADC_INPUT_CH3, 2, &input_mode, 1); + status = + cx231xx_read_i2c_data(dev, Colibri_DEVICE_ADDRESS, + ADC_NTF_PRECLMP_EN_CH3, 2, &ntf_mode, + 1); + } else { + status = + cx231xx_read_i2c_data(dev, Colibri_DEVICE_ADDRESS, + ADC_INPUT_CH1, 2, &input_mode, 1); + status = + cx231xx_read_i2c_data(dev, Colibri_DEVICE_ADDRESS, + ADC_NTF_PRECLMP_EN_CH1, 2, &ntf_mode, + 1); + } + + input_mode = (ntf_mode & 0x3) | ((input_mode & 0x6) << 1); + + switch (input_mode) { + case SINGLE_ENDED: + dev->colibri_ref_count = 0x23C; + break; + case LOW_IF: + dev->colibri_ref_count = 0x24C; + break; + case EU_IF: + dev->colibri_ref_count = 0x258; + break; + case US_IF: + dev->colibri_ref_count = 0x260; + break; + default: + break; + } + status = cx231xx_colibri_init_super_block(dev, dev->colibri_ref_count); + + return status; +} /************************************************************************************* * V I D E O / A U D I O D E C O D E R C O N T R O L functions * *************************************************************************************/ int cx231xx_set_video_input_mux(struct cx231xx *dev, u8 input) { - int status = 0; - - switch(INPUT(input)->type) { - case CX231XX_VMUX_COMPOSITE1: - case CX231XX_VMUX_SVIDEO: - if((dev->current_pcb_config.type == USB_BUS_POWER) && - (dev->power_mode != POLARIS_AVMODE_ENXTERNAL_AV)) { - status = cx231xx_set_power_mode(dev, POLARIS_AVMODE_ENXTERNAL_AV); /* External AV */ - if (status < 0) { - cx231xx_errdev("%s: cx231xx_set_power_mode : Failed to set Power - errCode [%d]!\n", - __func__, status); - return status; - } - } - status = cx231xx_set_decoder_video_input(dev, INPUT(input)->type, INPUT(input)->vmux); - break; - case CX231XX_VMUX_TELEVISION: - case CX231XX_VMUX_CABLE: - if((dev->current_pcb_config.type == USB_BUS_POWER) && - (dev->power_mode != POLARIS_AVMODE_ANALOGT_TV)) { - status = cx231xx_set_power_mode(dev, POLARIS_AVMODE_ANALOGT_TV); /* Tuner */ - if (status < 0) { - cx231xx_errdev("%s: cx231xx_set_power_mode : Failed to set Power - errCode [%d]!\n", - __func__, status); - return status; - } - } - status = cx231xx_set_decoder_video_input(dev, CX231XX_VMUX_COMPOSITE1, INPUT(input)->vmux); - break; - default: - cx231xx_errdev("%s: cx231xx_set_power_mode : Unknown Input %d !\n", - __func__, INPUT(input)->type); - break; - } - - /* save the selection */ - dev->video_input = input; - - return status; + int status = 0; + + switch (INPUT(input)->type) { + case CX231XX_VMUX_COMPOSITE1: + case CX231XX_VMUX_SVIDEO: + if ((dev->current_pcb_config.type == USB_BUS_POWER) && + (dev->power_mode != POLARIS_AVMODE_ENXTERNAL_AV)) { + status = cx231xx_set_power_mode(dev, POLARIS_AVMODE_ENXTERNAL_AV); /* External AV */ + if (status < 0) { + cx231xx_errdev + ("%s: cx231xx_set_power_mode : Failed to set Power - errCode [%d]!\n", + __func__, status); + return status; + } + } + status = + cx231xx_set_decoder_video_input(dev, INPUT(input)->type, + INPUT(input)->vmux); + break; + case CX231XX_VMUX_TELEVISION: + case CX231XX_VMUX_CABLE: + if ((dev->current_pcb_config.type == USB_BUS_POWER) && + (dev->power_mode != POLARIS_AVMODE_ANALOGT_TV)) { + status = cx231xx_set_power_mode(dev, POLARIS_AVMODE_ANALOGT_TV); /* Tuner */ + if (status < 0) { + cx231xx_errdev + ("%s: cx231xx_set_power_mode : Failed to set Power - errCode [%d]!\n", + __func__, status); + return status; + } + } + status = + cx231xx_set_decoder_video_input(dev, + CX231XX_VMUX_COMPOSITE1, + INPUT(input)->vmux); + break; + default: + cx231xx_errdev + ("%s: cx231xx_set_power_mode : Unknown Input %d !\n", + __func__, INPUT(input)->type); + break; + } + + /* save the selection */ + dev->video_input = input; + + return status; } int cx231xx_set_decoder_video_input(struct cx231xx *dev, u8 pin_type, u8 input) { - int status = 0; - u32 value = 0; - - if(pin_type != dev->video_input) { - status = cx231xx_colibri_adjust_ref_count(dev, pin_type); - if(status < 0 ) { - cx231xx_errdev("%s: cx231xx_colibri_adjust_ref_count :Failed to set Colibri input mux - errCode [%d]!\n", - __func__, status); - return status; - } - } - - /* call colibri block to set video inputs */ - status = cx231xx_colibri_set_input_mux(dev, input); - if(status < 0 ) { - cx231xx_errdev("%s: cx231xx_colibri_set_input_mux :Failed to set Colibri input mux - errCode [%d]!\n", - __func__, status); - return status; - } - - switch(pin_type) { - case CX231XX_VMUX_COMPOSITE1: - { - status = cx231xx_read_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, AFE_CTRL, 2, &value, 4); - value |= (0<<13)|(1<<4); - value &= ~(1<<5); - - value &= (~(0x1FF8000)); /* set [24:23] [22:15] to 0 */ - value |= 0x1000000; /* set FUNC_MODE[24:23] = 2 IF_MOD[22:15] = 0 */ - status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, AFE_CTRL, 2, value, 4); - - status = cx231xx_read_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, OUT_CTRL1, 2, &value, 4); - value |= (1<<7); - status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, OUT_CTRL1, 2, value, 4); - - /* Set vip 1.1 output mode */ - status = cx231xx_read_modify_write_i2c_dword(dev, HAMMERHEAD_I2C_ADDRESS, - OUT_CTRL1, FLD_OUT_MODE, OUT_MODE_VIP11); - - /* Tell DIF object to go to baseband mode */ - status = cx231xx_dif_set_standard(dev, DIF_USE_BASEBAND); - if (status < 0) { - cx231xx_errdev("%s: cx231xx_dif set to By pass mode - errCode [%d]!\n", - __func__, status); - return status; - } - - /* Read the DFE_CTRL1 register */ - status = cx231xx_read_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, DFE_CTRL1, 2, &value, 4); - - /* enable the VBI_GATE_EN */ - value |= FLD_VBI_GATE_EN; - - /* Enable the auto-VGA enable */ - value |= FLD_VGA_AUTO_EN; - - /* Write it back */ - status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, DFE_CTRL1, 2, value, 4); - - /* Disable auto config of registers */ - status = cx231xx_read_modify_write_i2c_dword(dev, HAMMERHEAD_I2C_ADDRESS, - MODE_CTRL, FLD_ACFG_DIS, cx231xx_set_field(FLD_ACFG_DIS, 1)); - - /* Set CVBS input mode */ - status = cx231xx_read_modify_write_i2c_dword(dev, HAMMERHEAD_I2C_ADDRESS, - MODE_CTRL, FLD_INPUT_MODE, - cx231xx_set_field(FLD_INPUT_MODE, INPUT_MODE_CVBS_0)); - } - break; - case CX231XX_VMUX_SVIDEO: - { - /* Disable the use of DIF */ - - status = cx231xx_read_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, AFE_CTRL, 2, &value, 4); - - value &= (~(0x1FF8000)); /* set [24:23] [22:15] to 0 */ - value |= 0x1000010; /* set FUNC_MODE[24:23] = 2 - IF_MOD[22:15] = 0 DCR_BYP_CH2[4:4] = 1; */ - status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, AFE_CTRL, 2, value, 4); - - /* Tell DIF object to go to baseband mode */ - status = cx231xx_dif_set_standard(dev, DIF_USE_BASEBAND); - if (status < 0) { - cx231xx_errdev("%s: cx231xx_dif set to By pass mode - errCode [%d]!\n", - __func__, status); - return status; - } - - /* Read the DFE_CTRL1 register */ - status = cx231xx_read_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, DFE_CTRL1, 2, &value, 4); - - /* enable the VBI_GATE_EN */ - value |= FLD_VBI_GATE_EN; - - /* Enable the auto-VGA enable */ - value |= FLD_VGA_AUTO_EN; - - /* Write it back */ - status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, DFE_CTRL1, 2, value, 4); - - /* Disable auto config of registers */ - status = cx231xx_read_modify_write_i2c_dword(dev, HAMMERHEAD_I2C_ADDRESS, - MODE_CTRL, FLD_ACFG_DIS, cx231xx_set_field(FLD_ACFG_DIS, 1)); - - /* Set YC input mode */ - status = cx231xx_read_modify_write_i2c_dword(dev, HAMMERHEAD_I2C_ADDRESS, - MODE_CTRL, FLD_INPUT_MODE, - cx231xx_set_field(FLD_INPUT_MODE, INPUT_MODE_YC_1)); - - /* Chroma to ADC2 */ - status = cx231xx_read_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, AFE_CTRL, 2, &value, 4); - value |= FLD_CHROMA_IN_SEL; /* set the chroma in select */ - - /* Clear VGA_SEL_CH2 and VGA_SEL_CH3 (bits 7 and 8) This sets them to use video - rather than audio. Only one of the two will be in use. */ - value &= ~(FLD_VGA_SEL_CH2 | FLD_VGA_SEL_CH3); - - status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, AFE_CTRL, 2, value, 4); - - status = cx231xx_colibri_set_mode(dev, AFE_MODE_BASEBAND); - } - break; - case CX231XX_VMUX_TELEVISION: - case CX231XX_VMUX_CABLE: - default: - { - switch(dev->model) { - case CX231XX_BOARD_CNXT_RDE_250: - case CX231XX_BOARD_CNXT_RDU_250: - { - /* Disable the use of DIF */ - - status = cx231xx_read_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, AFE_CTRL, 2, &value, 4); - value |= (0<<13)|(1<<4); - value &= ~(1<<5); - - value &= (~(0x1FF8000)); /* set [24:23] [22:15] to 0 */ - value |= 0x1000000; /* set FUNC_MODE[24:23] = 2 IF_MOD[22:15] = 0 */ - status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, AFE_CTRL, 2, value, 4); - - status = cx231xx_read_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, OUT_CTRL1, 2, &value, 4); - value |= (1<<7); - status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, OUT_CTRL1, 2, value, 4); - - /* Set vip 1.1 output mode */ - status = cx231xx_read_modify_write_i2c_dword(dev, HAMMERHEAD_I2C_ADDRESS, - OUT_CTRL1, FLD_OUT_MODE, OUT_MODE_VIP11); - - /* Tell DIF object to go to baseband mode */ - status = cx231xx_dif_set_standard(dev, DIF_USE_BASEBAND); - if (status < 0) { - cx231xx_errdev("%s: cx231xx_dif set to By pass mode - errCode [%d]!\n", - __func__, status); - return status; - } - - /* Read the DFE_CTRL1 register */ - status = cx231xx_read_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, DFE_CTRL1, 2, &value, 4); - - /* enable the VBI_GATE_EN */ - value |= FLD_VBI_GATE_EN; - - /* Enable the auto-VGA enable */ - value |= FLD_VGA_AUTO_EN; - - /* Write it back */ - status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, DFE_CTRL1, 2, value, 4); - - /* Disable auto config of registers */ - status = cx231xx_read_modify_write_i2c_dword(dev, HAMMERHEAD_I2C_ADDRESS, - MODE_CTRL, FLD_ACFG_DIS, cx231xx_set_field(FLD_ACFG_DIS, 1)); - - /* Set CVBS input mode */ - status = cx231xx_read_modify_write_i2c_dword(dev, HAMMERHEAD_I2C_ADDRESS, - MODE_CTRL, FLD_INPUT_MODE, - cx231xx_set_field(FLD_INPUT_MODE, INPUT_MODE_CVBS_0)); - } - break; - default: - { - /* Enable the DIF for the tuner */ - - /* Reinitialize the DIF */ - status = cx231xx_dif_set_standard(dev, dev->norm); - if (status < 0) { - cx231xx_errdev("%s: cx231xx_dif set to By pass mode - errCode [%d]!\n", - __func__, status); - return status; - } - - /* Make sure bypass is cleared */ - status = cx231xx_read_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, DIF_MISC_CTRL, 2, &value, 4); - - /* Clear the bypass bit */ - value &= ~FLD_DIF_DIF_BYPASS; - - /* Enable the use of the DIF block */ - status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, DIF_MISC_CTRL, 2, value, 4); - - /* Read the DFE_CTRL1 register */ - status = cx231xx_read_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, DFE_CTRL1, 2, &value, 4); - - /* Disable the VBI_GATE_EN */ - value &= ~FLD_VBI_GATE_EN; - - /* Enable the auto-VGA enable, AGC, and set the skip count to 2 */ - value |= FLD_VGA_AUTO_EN | FLD_AGC_AUTO_EN | 0x00200000; - - /* Write it back */ - status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, DFE_CTRL1, 2, value, 4); - - /* Wait 15 ms */ - msleep(1); - - /* Disable the auto-VGA enable AGC */ - value &= ~(FLD_VGA_AUTO_EN); - - /* Write it back */ - status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, DFE_CTRL1, 2, value, 4); - - /* Enable Polaris B0 AGC output */ - status = cx231xx_read_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, PIN_CTRL, 2, &value, 4); - value |=(FLD_OEF_AGC_RF)|(FLD_OEF_AGC_IFVGA)|(FLD_OEF_AGC_IF); - status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, PIN_CTRL, 2, value, 4); - - /* Set vip 1.1 output mode */ - status = cx231xx_read_modify_write_i2c_dword(dev, HAMMERHEAD_I2C_ADDRESS, - OUT_CTRL1, FLD_OUT_MODE, OUT_MODE_VIP11); - - /* Disable auto config of registers */ - status = cx231xx_read_modify_write_i2c_dword(dev, HAMMERHEAD_I2C_ADDRESS, - MODE_CTRL, FLD_ACFG_DIS, cx231xx_set_field(FLD_ACFG_DIS, 1)); - - /* Set CVBS input mode */ - status = cx231xx_read_modify_write_i2c_dword(dev, HAMMERHEAD_I2C_ADDRESS, - MODE_CTRL, FLD_INPUT_MODE, - cx231xx_set_field(FLD_INPUT_MODE, INPUT_MODE_CVBS_0)); - - /* Set some bits in AFE_CTRL so that channel 2 or 3 is ready to receive audio */ - /* Clear clamp for channels 2 and 3 (bit 16-17) */ - /* Clear droop comp (bit 19-20) */ - /* Set VGA_SEL (for audio control) (bit 7-8) */ - status = cx231xx_read_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, AFE_CTRL, 2, &value, 4); - - value |= FLD_VGA_SEL_CH3 | FLD_VGA_SEL_CH2; - - status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, AFE_CTRL, 2, value, 4); - } - break; - - } - } - break; - } - - /* Set raw VBI mode */ - status = cx231xx_read_modify_write_i2c_dword(dev, HAMMERHEAD_I2C_ADDRESS, - OUT_CTRL1, FLD_VBIHACTRAW_EN, - cx231xx_set_field(FLD_VBIHACTRAW_EN, 1)); - - status = cx231xx_read_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, OUT_CTRL1, 2, &value, 4); - if(value & 0x02) { - value |=(1<<19); - status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, OUT_CTRL1, 2, value, 4); - } - - return status; + int status = 0; + u32 value = 0; + + if (pin_type != dev->video_input) { + status = cx231xx_colibri_adjust_ref_count(dev, pin_type); + if (status < 0) { + cx231xx_errdev + ("%s: cx231xx_colibri_adjust_ref_count :Failed to set Colibri input mux - errCode [%d]!\n", + __func__, status); + return status; + } + } + + /* call colibri block to set video inputs */ + status = cx231xx_colibri_set_input_mux(dev, input); + if (status < 0) { + cx231xx_errdev + ("%s: cx231xx_colibri_set_input_mux :Failed to set Colibri input mux - errCode [%d]!\n", + __func__, status); + return status; + } + + switch (pin_type) { + case CX231XX_VMUX_COMPOSITE1: + { + status = + cx231xx_read_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, + AFE_CTRL, 2, &value, 4); + value |= (0 << 13) | (1 << 4); + value &= ~(1 << 5); + + value &= (~(0x1FF8000)); /* set [24:23] [22:15] to 0 */ + value |= 0x1000000; /* set FUNC_MODE[24:23] = 2 IF_MOD[22:15] = 0 */ + status = + cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, + AFE_CTRL, 2, value, 4); + + status = + cx231xx_read_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, + OUT_CTRL1, 2, &value, 4); + value |= (1 << 7); + status = + cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, + OUT_CTRL1, 2, value, 4); + + /* Set vip 1.1 output mode */ + status = + cx231xx_read_modify_write_i2c_dword(dev, + HAMMERHEAD_I2C_ADDRESS, + OUT_CTRL1, + FLD_OUT_MODE, + OUT_MODE_VIP11); + + /* Tell DIF object to go to baseband mode */ + status = + cx231xx_dif_set_standard(dev, DIF_USE_BASEBAND); + if (status < 0) { + cx231xx_errdev + ("%s: cx231xx_dif set to By pass mode - errCode [%d]!\n", + __func__, status); + return status; + } + + /* Read the DFE_CTRL1 register */ + status = + cx231xx_read_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, + DFE_CTRL1, 2, &value, 4); + + /* enable the VBI_GATE_EN */ + value |= FLD_VBI_GATE_EN; + + /* Enable the auto-VGA enable */ + value |= FLD_VGA_AUTO_EN; + + /* Write it back */ + status = + cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, + DFE_CTRL1, 2, value, 4); + + /* Disable auto config of registers */ + status = + cx231xx_read_modify_write_i2c_dword(dev, + HAMMERHEAD_I2C_ADDRESS, + MODE_CTRL, + FLD_ACFG_DIS, + cx231xx_set_field + (FLD_ACFG_DIS, + 1)); + + /* Set CVBS input mode */ + status = + cx231xx_read_modify_write_i2c_dword(dev, + HAMMERHEAD_I2C_ADDRESS, + MODE_CTRL, + FLD_INPUT_MODE, + cx231xx_set_field + (FLD_INPUT_MODE, + INPUT_MODE_CVBS_0)); + } + break; + case CX231XX_VMUX_SVIDEO: + { + /* Disable the use of DIF */ + + status = + cx231xx_read_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, + AFE_CTRL, 2, &value, 4); + + value &= (~(0x1FF8000)); /* set [24:23] [22:15] to 0 */ + value |= 0x1000010; /* set FUNC_MODE[24:23] = 2 + IF_MOD[22:15] = 0 DCR_BYP_CH2[4:4] = 1; */ + status = + cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, + AFE_CTRL, 2, value, 4); + + /* Tell DIF object to go to baseband mode */ + status = + cx231xx_dif_set_standard(dev, DIF_USE_BASEBAND); + if (status < 0) { + cx231xx_errdev + ("%s: cx231xx_dif set to By pass mode - errCode [%d]!\n", + __func__, status); + return status; + } + + /* Read the DFE_CTRL1 register */ + status = + cx231xx_read_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, + DFE_CTRL1, 2, &value, 4); + + /* enable the VBI_GATE_EN */ + value |= FLD_VBI_GATE_EN; + + /* Enable the auto-VGA enable */ + value |= FLD_VGA_AUTO_EN; + + /* Write it back */ + status = + cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, + DFE_CTRL1, 2, value, 4); + + /* Disable auto config of registers */ + status = + cx231xx_read_modify_write_i2c_dword(dev, + HAMMERHEAD_I2C_ADDRESS, + MODE_CTRL, + FLD_ACFG_DIS, + cx231xx_set_field + (FLD_ACFG_DIS, + 1)); + + /* Set YC input mode */ + status = + cx231xx_read_modify_write_i2c_dword(dev, + HAMMERHEAD_I2C_ADDRESS, + MODE_CTRL, + FLD_INPUT_MODE, + cx231xx_set_field + (FLD_INPUT_MODE, + INPUT_MODE_YC_1)); + + /* Chroma to ADC2 */ + status = + cx231xx_read_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, + AFE_CTRL, 2, &value, 4); + value |= FLD_CHROMA_IN_SEL; /* set the chroma in select */ + + /* Clear VGA_SEL_CH2 and VGA_SEL_CH3 (bits 7 and 8) This sets them to use video + rather than audio. Only one of the two will be in use. */ + value &= ~(FLD_VGA_SEL_CH2 | FLD_VGA_SEL_CH3); + + status = + cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, + AFE_CTRL, 2, value, 4); + + status = + cx231xx_colibri_set_mode(dev, AFE_MODE_BASEBAND); + } + break; + case CX231XX_VMUX_TELEVISION: + case CX231XX_VMUX_CABLE: + default: + { + switch (dev->model) { + case CX231XX_BOARD_CNXT_RDE_250: + case CX231XX_BOARD_CNXT_RDU_250: + { + /* Disable the use of DIF */ + + status = + cx231xx_read_i2c_data(dev, + HAMMERHEAD_I2C_ADDRESS, + AFE_CTRL, 2, + &value, 4); + value |= (0 << 13) | (1 << 4); + value &= ~(1 << 5); + + value &= (~(0x1FF8000)); /* set [24:23] [22:15] to 0 */ + value |= 0x1000000; /* set FUNC_MODE[24:23] = 2 IF_MOD[22:15] = 0 */ + status = + cx231xx_write_i2c_data(dev, + HAMMERHEAD_I2C_ADDRESS, + AFE_CTRL, 2, + value, 4); + + status = + cx231xx_read_i2c_data(dev, + HAMMERHEAD_I2C_ADDRESS, + OUT_CTRL1, 2, + &value, 4); + value |= (1 << 7); + status = + cx231xx_write_i2c_data(dev, + HAMMERHEAD_I2C_ADDRESS, + OUT_CTRL1, 2, + value, 4); + + /* Set vip 1.1 output mode */ + status = + cx231xx_read_modify_write_i2c_dword + (dev, HAMMERHEAD_I2C_ADDRESS, + OUT_CTRL1, FLD_OUT_MODE, + OUT_MODE_VIP11); + + /* Tell DIF object to go to baseband mode */ + status = + cx231xx_dif_set_standard(dev, + DIF_USE_BASEBAND); + if (status < 0) { + cx231xx_errdev + ("%s: cx231xx_dif set to By pass mode - errCode [%d]!\n", + __func__, status); + return status; + } + + /* Read the DFE_CTRL1 register */ + status = + cx231xx_read_i2c_data(dev, + HAMMERHEAD_I2C_ADDRESS, + DFE_CTRL1, 2, + &value, 4); + + /* enable the VBI_GATE_EN */ + value |= FLD_VBI_GATE_EN; + + /* Enable the auto-VGA enable */ + value |= FLD_VGA_AUTO_EN; + + /* Write it back */ + status = + cx231xx_write_i2c_data(dev, + HAMMERHEAD_I2C_ADDRESS, + DFE_CTRL1, 2, + value, 4); + + /* Disable auto config of registers */ + status = + cx231xx_read_modify_write_i2c_dword + (dev, HAMMERHEAD_I2C_ADDRESS, + MODE_CTRL, FLD_ACFG_DIS, + cx231xx_set_field(FLD_ACFG_DIS, + 1)); + + /* Set CVBS input mode */ + status = + cx231xx_read_modify_write_i2c_dword + (dev, HAMMERHEAD_I2C_ADDRESS, + MODE_CTRL, FLD_INPUT_MODE, + cx231xx_set_field(FLD_INPUT_MODE, + INPUT_MODE_CVBS_0)); + } + break; + default: + { + /* Enable the DIF for the tuner */ + + /* Reinitialize the DIF */ + status = + cx231xx_dif_set_standard(dev, + dev->norm); + if (status < 0) { + cx231xx_errdev + ("%s: cx231xx_dif set to By pass mode - errCode [%d]!\n", + __func__, status); + return status; + } + + /* Make sure bypass is cleared */ + status = + cx231xx_read_i2c_data(dev, + HAMMERHEAD_I2C_ADDRESS, + DIF_MISC_CTRL, + 2, &value, 4); + + /* Clear the bypass bit */ + value &= ~FLD_DIF_DIF_BYPASS; + + /* Enable the use of the DIF block */ + status = + cx231xx_write_i2c_data(dev, + HAMMERHEAD_I2C_ADDRESS, + DIF_MISC_CTRL, + 2, value, 4); + + /* Read the DFE_CTRL1 register */ + status = + cx231xx_read_i2c_data(dev, + HAMMERHEAD_I2C_ADDRESS, + DFE_CTRL1, 2, + &value, 4); + + /* Disable the VBI_GATE_EN */ + value &= ~FLD_VBI_GATE_EN; + + /* Enable the auto-VGA enable, AGC, and set the skip count to 2 */ + value |= + FLD_VGA_AUTO_EN | FLD_AGC_AUTO_EN | + 0x00200000; + + /* Write it back */ + status = + cx231xx_write_i2c_data(dev, + HAMMERHEAD_I2C_ADDRESS, + DFE_CTRL1, 2, + value, 4); + + /* Wait 15 ms */ + msleep(1); + + /* Disable the auto-VGA enable AGC */ + value &= ~(FLD_VGA_AUTO_EN); + + /* Write it back */ + status = + cx231xx_write_i2c_data(dev, + HAMMERHEAD_I2C_ADDRESS, + DFE_CTRL1, 2, + value, 4); + + /* Enable Polaris B0 AGC output */ + status = + cx231xx_read_i2c_data(dev, + HAMMERHEAD_I2C_ADDRESS, + PIN_CTRL, 2, + &value, 4); + value |= + (FLD_OEF_AGC_RF) | + (FLD_OEF_AGC_IFVGA) | + (FLD_OEF_AGC_IF); + status = + cx231xx_write_i2c_data(dev, + HAMMERHEAD_I2C_ADDRESS, + PIN_CTRL, 2, + value, 4); + + /* Set vip 1.1 output mode */ + status = + cx231xx_read_modify_write_i2c_dword + (dev, HAMMERHEAD_I2C_ADDRESS, + OUT_CTRL1, FLD_OUT_MODE, + OUT_MODE_VIP11); + + /* Disable auto config of registers */ + status = + cx231xx_read_modify_write_i2c_dword + (dev, HAMMERHEAD_I2C_ADDRESS, + MODE_CTRL, FLD_ACFG_DIS, + cx231xx_set_field(FLD_ACFG_DIS, + 1)); + + /* Set CVBS input mode */ + status = + cx231xx_read_modify_write_i2c_dword + (dev, HAMMERHEAD_I2C_ADDRESS, + MODE_CTRL, FLD_INPUT_MODE, + cx231xx_set_field(FLD_INPUT_MODE, + INPUT_MODE_CVBS_0)); + + /* Set some bits in AFE_CTRL so that channel 2 or 3 is ready to receive audio */ + /* Clear clamp for channels 2 and 3 (bit 16-17) */ + /* Clear droop comp (bit 19-20) */ + /* Set VGA_SEL (for audio control) (bit 7-8) */ + status = + cx231xx_read_i2c_data(dev, + HAMMERHEAD_I2C_ADDRESS, + AFE_CTRL, 2, + &value, 4); + + value |= + FLD_VGA_SEL_CH3 | FLD_VGA_SEL_CH2; + + status = + cx231xx_write_i2c_data(dev, + HAMMERHEAD_I2C_ADDRESS, + AFE_CTRL, 2, + value, 4); + } + break; + + } + } + break; + } + + /* Set raw VBI mode */ + status = + cx231xx_read_modify_write_i2c_dword(dev, HAMMERHEAD_I2C_ADDRESS, + OUT_CTRL1, FLD_VBIHACTRAW_EN, + cx231xx_set_field + (FLD_VBIHACTRAW_EN, 1)); + + status = + cx231xx_read_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, OUT_CTRL1, 2, + &value, 4); + if (value & 0x02) { + value |= (1 << 19); + status = + cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, + OUT_CTRL1, 2, value, 4); + } + + return status; } /* @@ -718,207 +1026,310 @@ int cx231xx_set_decoder_video_input(struct cx231xx *dev, u8 pin_type, u8 input) */ int cx231xx_do_mode_ctrl_overrides(struct cx231xx *dev) { - int status = 0; - - cx231xx_info("do_mode_ctrl_overrides : 0x%x\n", (unsigned int)dev->norm); - - /* Change the DFE_CTRL3 bp_percent to fix flagging */ - status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, DFE_CTRL3, 2, 0xCD3F0280, 4); - - if( dev->norm & (V4L2_STD_NTSC_M | V4L2_STD_NTSC_M_JP | V4L2_STD_PAL_M) ) { - cx231xx_info("do_mode_ctrl_overrides NTSC\n"); - - /* Move the close caption lines out of active video, adjust the active video start point */ - status = cx231xx_read_modify_write_i2c_dword(dev, HAMMERHEAD_I2C_ADDRESS, - VERT_TIM_CTRL, FLD_VBLANK_CNT,0x18); - status = cx231xx_read_modify_write_i2c_dword(dev, HAMMERHEAD_I2C_ADDRESS, - VERT_TIM_CTRL, FLD_VACTIVE_CNT,0x1E6000); - status = cx231xx_read_modify_write_i2c_dword(dev, HAMMERHEAD_I2C_ADDRESS, - VERT_TIM_CTRL, FLD_V656BLANK_CNT,0x1E000000); - - status = cx231xx_read_modify_write_i2c_dword(dev, HAMMERHEAD_I2C_ADDRESS, - HORIZ_TIM_CTRL, FLD_HBLANK_CNT, - cx231xx_set_field(FLD_HBLANK_CNT, 0x79)); - } else if ( dev->norm & ( V4L2_STD_PAL_B | V4L2_STD_PAL_G | V4L2_STD_PAL_D | - V4L2_STD_PAL_I | V4L2_STD_PAL_N | V4L2_STD_PAL_Nc) ) { - cx231xx_info("do_mode_ctrl_overrides PAL\n"); - status = cx231xx_read_modify_write_i2c_dword(dev, HAMMERHEAD_I2C_ADDRESS, - VERT_TIM_CTRL, FLD_VBLANK_CNT,0x24); - /* Adjust the active video horizontal start point */ - status = cx231xx_read_modify_write_i2c_dword(dev, HAMMERHEAD_I2C_ADDRESS, - HORIZ_TIM_CTRL, FLD_HBLANK_CNT, - cx231xx_set_field(FLD_HBLANK_CNT, 0x85)); - } else if (dev->norm & ( V4L2_STD_SECAM_B | V4L2_STD_SECAM_D | V4L2_STD_SECAM_G | - V4L2_STD_SECAM_K | V4L2_STD_SECAM_K1 | V4L2_STD_SECAM_L | - V4L2_STD_SECAM_LC) ) { - cx231xx_info("do_mode_ctrl_overrides SECAM\n"); - status = cx231xx_read_modify_write_i2c_dword(dev, HAMMERHEAD_I2C_ADDRESS, - VERT_TIM_CTRL, FLD_VBLANK_CNT,0x24); - /* Adjust the active video horizontal start point */ - status = cx231xx_read_modify_write_i2c_dword(dev, HAMMERHEAD_I2C_ADDRESS, - HORIZ_TIM_CTRL, FLD_HBLANK_CNT, - cx231xx_set_field(FLD_HBLANK_CNT, 0x85)); - } - - return status; + int status = 0; + + cx231xx_info("do_mode_ctrl_overrides : 0x%x\n", + (unsigned int)dev->norm); + + /* Change the DFE_CTRL3 bp_percent to fix flagging */ + status = + cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, DFE_CTRL3, 2, + 0xCD3F0280, 4); + + if (dev->norm & (V4L2_STD_NTSC_M | V4L2_STD_NTSC_M_JP | V4L2_STD_PAL_M)) { + cx231xx_info("do_mode_ctrl_overrides NTSC\n"); + + /* Move the close caption lines out of active video, adjust the active video start point */ + status = + cx231xx_read_modify_write_i2c_dword(dev, + HAMMERHEAD_I2C_ADDRESS, + VERT_TIM_CTRL, + FLD_VBLANK_CNT, 0x18); + status = + cx231xx_read_modify_write_i2c_dword(dev, + HAMMERHEAD_I2C_ADDRESS, + VERT_TIM_CTRL, + FLD_VACTIVE_CNT, + 0x1E6000); + status = + cx231xx_read_modify_write_i2c_dword(dev, + HAMMERHEAD_I2C_ADDRESS, + VERT_TIM_CTRL, + FLD_V656BLANK_CNT, + 0x1E000000); + + status = + cx231xx_read_modify_write_i2c_dword(dev, + HAMMERHEAD_I2C_ADDRESS, + HORIZ_TIM_CTRL, + FLD_HBLANK_CNT, + cx231xx_set_field + (FLD_HBLANK_CNT, 0x79)); + } else if (dev-> + norm & (V4L2_STD_PAL_B | V4L2_STD_PAL_G | V4L2_STD_PAL_D | + V4L2_STD_PAL_I | V4L2_STD_PAL_N | V4L2_STD_PAL_Nc)) { + cx231xx_info("do_mode_ctrl_overrides PAL\n"); + status = + cx231xx_read_modify_write_i2c_dword(dev, + HAMMERHEAD_I2C_ADDRESS, + VERT_TIM_CTRL, + FLD_VBLANK_CNT, 0x24); + /* Adjust the active video horizontal start point */ + status = + cx231xx_read_modify_write_i2c_dword(dev, + HAMMERHEAD_I2C_ADDRESS, + HORIZ_TIM_CTRL, + FLD_HBLANK_CNT, + cx231xx_set_field + (FLD_HBLANK_CNT, 0x85)); + } else if (dev-> + norm & (V4L2_STD_SECAM_B | V4L2_STD_SECAM_D | + V4L2_STD_SECAM_G | V4L2_STD_SECAM_K | + V4L2_STD_SECAM_K1 | V4L2_STD_SECAM_L | + V4L2_STD_SECAM_LC)) { + cx231xx_info("do_mode_ctrl_overrides SECAM\n"); + status = + cx231xx_read_modify_write_i2c_dword(dev, + HAMMERHEAD_I2C_ADDRESS, + VERT_TIM_CTRL, + FLD_VBLANK_CNT, 0x24); + /* Adjust the active video horizontal start point */ + status = + cx231xx_read_modify_write_i2c_dword(dev, + HAMMERHEAD_I2C_ADDRESS, + HORIZ_TIM_CTRL, + FLD_HBLANK_CNT, + cx231xx_set_field + (FLD_HBLANK_CNT, 0x85)); + } + + return status; } int cx231xx_set_audio_input(struct cx231xx *dev, u8 input) { - int status = 0; - enum AUDIO_INPUT ainput = AUDIO_INPUT_LINE; - - switch(INPUT(input)->amux) { - case CX231XX_AMUX_VIDEO: - ainput = AUDIO_INPUT_TUNER_TV; - break; - case CX231XX_AMUX_LINE_IN: - status = cx231xx_flatiron_set_audio_input(dev, input); - ainput = AUDIO_INPUT_LINE; - break; - default: - break; - } - - status = cx231xx_set_audio_decoder_input(dev, ainput); - - return status; + int status = 0; + enum AUDIO_INPUT ainput = AUDIO_INPUT_LINE; + + switch (INPUT(input)->amux) { + case CX231XX_AMUX_VIDEO: + ainput = AUDIO_INPUT_TUNER_TV; + break; + case CX231XX_AMUX_LINE_IN: + status = cx231xx_flatiron_set_audio_input(dev, input); + ainput = AUDIO_INPUT_LINE; + break; + default: + break; + } + + status = cx231xx_set_audio_decoder_input(dev, ainput); + + return status; } -int cx231xx_set_audio_decoder_input(struct cx231xx *dev, enum AUDIO_INPUT audio_input) +int cx231xx_set_audio_decoder_input(struct cx231xx *dev, + enum AUDIO_INPUT audio_input) { - u32 dwval; - int status; - u32 gen_ctrl; - u32 value = 0; - - /* Put it in soft reset */ - status = cx231xx_read_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, GENERAL_CTL, 2, &gen_ctrl, 1); - gen_ctrl |= 1; - status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, GENERAL_CTL, 2, gen_ctrl, 1); - - switch(audio_input) - { - case AUDIO_INPUT_LINE: - - /* setup AUD_IO control from Merlin paralle output */ - value = cx231xx_set_field(FLD_AUD_CHAN1_SRC, AUD_CHAN_SRC_PARALLEL); - status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, AUD_IO_CTRL, 2, value, 4); - - /* setup input to Merlin, SRC2 connect to AC97 - bypass upsample-by-2, slave mode, sony mode, left justify - adr 091c, dat 01000000 */ - status = cx231xx_read_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, AC97_CTL, 2, &dwval, 4); - - status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, AC97_CTL, 2, (dwval | FLD_AC97_UP2X_BYPASS), 4); - - /* select the parallel1 and SRC3 */ - status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, BAND_OUT_SEL, 2, - cx231xx_set_field(FLD_SRC3_IN_SEL, 0x0)| - cx231xx_set_field(FLD_SRC3_CLK_SEL, 0x0)| - cx231xx_set_field(FLD_PARALLEL1_SRC_SEL, 0x0), 4); - - /* unmute all, AC97 in, independence mode - adr 08d0, data 0x00063073 */ - status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, PATH1_CTL1, 2, 0x00063073, 4); - - /* set AVC maximum threshold, adr 08d4, dat ffff0024 */ - status = cx231xx_read_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, PATH1_VOL_CTL, 2, &dwval, 4); - status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, PATH1_VOL_CTL, 2, - (dwval | FLD_PATH1_AVC_THRESHOLD), 4); - - /* set SC maximum threshold, adr 08ec, dat ffffb3a3 */ - status = cx231xx_read_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, PATH1_SC_CTL, 2, &dwval, 4); - status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, PATH1_SC_CTL, 2, - (dwval | FLD_PATH1_SC_THRESHOLD), 4); - break; - - case AUDIO_INPUT_TUNER_TV: - default: - - /* Setup SRC sources and clocks */ - status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, BAND_OUT_SEL, 2, - cx231xx_set_field(FLD_SRC6_IN_SEL, 0x00)| - cx231xx_set_field(FLD_SRC6_CLK_SEL, 0x01)| - cx231xx_set_field(FLD_SRC5_IN_SEL, 0x00)| - cx231xx_set_field(FLD_SRC5_CLK_SEL, 0x02)| - cx231xx_set_field(FLD_SRC4_IN_SEL, 0x02)| - cx231xx_set_field(FLD_SRC4_CLK_SEL, 0x03)| - cx231xx_set_field(FLD_SRC3_IN_SEL, 0x00)| - cx231xx_set_field(FLD_SRC3_CLK_SEL, 0x00)| - cx231xx_set_field(FLD_BASEBAND_BYPASS_CTL, 0x00)| - cx231xx_set_field(FLD_AC97_SRC_SEL, 0x03)| - cx231xx_set_field(FLD_I2S_SRC_SEL, 0x00)| - cx231xx_set_field(FLD_PARALLEL2_SRC_SEL, 0x02)| - cx231xx_set_field(FLD_PARALLEL1_SRC_SEL, 0x01) , 4); - - /* Setup the AUD_IO control */ - status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, AUD_IO_CTRL, 2, - cx231xx_set_field(FLD_I2S_PORT_DIR, 0x00)| - cx231xx_set_field(FLD_I2S_OUT_SRC, 0x00)| - cx231xx_set_field(FLD_AUD_CHAN3_SRC,0x00)| - cx231xx_set_field(FLD_AUD_CHAN2_SRC, 0x00)| - cx231xx_set_field(FLD_AUD_CHAN1_SRC,0x03 ), 4); - - status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, PATH1_CTL1, 2, 0x1F063870, 4); - - /* setAudioStandard(_audio_standard); */ - - status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, PATH1_CTL1, 2, 0x00063870, 4); - switch(dev->model) - { - case CX231XX_BOARD_CNXT_RDE_250: - case CX231XX_BOARD_CNXT_RDU_250: - status = cx231xx_read_modify_write_i2c_dword(dev, HAMMERHEAD_I2C_ADDRESS, - CHIP_CTRL, FLD_SIF_EN, - cx231xx_set_field(FLD_SIF_EN, 1)); - break; - default: - break; - } - break; - - case AUDIO_INPUT_TUNER_FM: - /* use SIF for FM radio - setupFM(); - setAudioStandard(_audio_standard); - */ - break; - - case AUDIO_INPUT_MUTE: - status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, PATH1_CTL1, 2, 0x1F011012, 4); - break; - } - - /* Take it out of soft reset */ - status = cx231xx_read_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, GENERAL_CTL, 2, &gen_ctrl, 1); - gen_ctrl &= ~1; - status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, GENERAL_CTL, 2, gen_ctrl, 1); - - return status; -} + u32 dwval; + int status; + u32 gen_ctrl; + u32 value = 0; + + /* Put it in soft reset */ + status = + cx231xx_read_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, GENERAL_CTL, 2, + &gen_ctrl, 1); + gen_ctrl |= 1; + status = + cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, GENERAL_CTL, 2, + gen_ctrl, 1); + + switch (audio_input) { + case AUDIO_INPUT_LINE: + + /* setup AUD_IO control from Merlin paralle output */ + value = + cx231xx_set_field(FLD_AUD_CHAN1_SRC, AUD_CHAN_SRC_PARALLEL); + status = + cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, + AUD_IO_CTRL, 2, value, 4); + + /* setup input to Merlin, SRC2 connect to AC97 + bypass upsample-by-2, slave mode, sony mode, left justify + adr 091c, dat 01000000 */ + status = + cx231xx_read_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, AC97_CTL, + 2, &dwval, 4); + + status = + cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, + AC97_CTL, 2, + (dwval | FLD_AC97_UP2X_BYPASS), 4); + + /* select the parallel1 and SRC3 */ + status = + cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, + BAND_OUT_SEL, 2, + cx231xx_set_field(FLD_SRC3_IN_SEL, + 0x0) | + cx231xx_set_field(FLD_SRC3_CLK_SEL, + 0x0) | + cx231xx_set_field + (FLD_PARALLEL1_SRC_SEL, 0x0), 4); + + /* unmute all, AC97 in, independence mode + adr 08d0, data 0x00063073 */ + status = + cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, + PATH1_CTL1, 2, 0x00063073, 4); + + /* set AVC maximum threshold, adr 08d4, dat ffff0024 */ + status = + cx231xx_read_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, + PATH1_VOL_CTL, 2, &dwval, 4); + status = + cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, + PATH1_VOL_CTL, 2, + (dwval | FLD_PATH1_AVC_THRESHOLD), + 4); + + /* set SC maximum threshold, adr 08ec, dat ffffb3a3 */ + status = + cx231xx_read_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, + PATH1_SC_CTL, 2, &dwval, 4); + status = + cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, + PATH1_SC_CTL, 2, + (dwval | FLD_PATH1_SC_THRESHOLD), 4); + break; + + case AUDIO_INPUT_TUNER_TV: + default: + + /* Setup SRC sources and clocks */ + status = + cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, + BAND_OUT_SEL, 2, + cx231xx_set_field(FLD_SRC6_IN_SEL, + 0x00) | + cx231xx_set_field(FLD_SRC6_CLK_SEL, + 0x01) | + cx231xx_set_field(FLD_SRC5_IN_SEL, + 0x00) | + cx231xx_set_field(FLD_SRC5_CLK_SEL, + 0x02) | + cx231xx_set_field(FLD_SRC4_IN_SEL, + 0x02) | + cx231xx_set_field(FLD_SRC4_CLK_SEL, + 0x03) | + cx231xx_set_field(FLD_SRC3_IN_SEL, + 0x00) | + cx231xx_set_field(FLD_SRC3_CLK_SEL, + 0x00) | + cx231xx_set_field + (FLD_BASEBAND_BYPASS_CTL, + 0x00) | + cx231xx_set_field(FLD_AC97_SRC_SEL, + 0x03) | + cx231xx_set_field(FLD_I2S_SRC_SEL, + 0x00) | + cx231xx_set_field + (FLD_PARALLEL2_SRC_SEL, + 0x02) | + cx231xx_set_field + (FLD_PARALLEL1_SRC_SEL, 0x01), 4); + + /* Setup the AUD_IO control */ + status = + cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, + AUD_IO_CTRL, 2, + cx231xx_set_field(FLD_I2S_PORT_DIR, + 0x00) | + cx231xx_set_field(FLD_I2S_OUT_SRC, + 0x00) | + cx231xx_set_field(FLD_AUD_CHAN3_SRC, + 0x00) | + cx231xx_set_field(FLD_AUD_CHAN2_SRC, + 0x00) | + cx231xx_set_field(FLD_AUD_CHAN1_SRC, + 0x03), 4); + + status = + cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, + PATH1_CTL1, 2, 0x1F063870, 4); + + /* setAudioStandard(_audio_standard); */ + + status = + cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, + PATH1_CTL1, 2, 0x00063870, 4); + switch (dev->model) { + case CX231XX_BOARD_CNXT_RDE_250: + case CX231XX_BOARD_CNXT_RDU_250: + status = + cx231xx_read_modify_write_i2c_dword(dev, + HAMMERHEAD_I2C_ADDRESS, + CHIP_CTRL, + FLD_SIF_EN, + cx231xx_set_field + (FLD_SIF_EN, + 1)); + break; + default: + break; + } + break; + + case AUDIO_INPUT_TUNER_FM: + /* use SIF for FM radio + setupFM(); + setAudioStandard(_audio_standard); + */ + break; + + case AUDIO_INPUT_MUTE: + status = + cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, + PATH1_CTL1, 2, 0x1F011012, 4); + break; + } + /* Take it out of soft reset */ + status = + cx231xx_read_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, GENERAL_CTL, 2, + &gen_ctrl, 1); + gen_ctrl &= ~1; + status = + cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, GENERAL_CTL, 2, + gen_ctrl, 1); + return status; +} /* Set resolution of the video */ int cx231xx_resolution_set(struct cx231xx *dev) { int width, height; - u32 hscale, vscale; - int status = 0; + u32 hscale, vscale; + int status = 0; width = dev->width; height = dev->height; - get_scale(dev,width, height,&hscale, &vscale); + get_scale(dev, width, height, &hscale, &vscale); - /* set horzontal scale */ - status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, HSCALE_CTRL, 2, hscale, 4); + /* set horzontal scale */ + status = + cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, HSCALE_CTRL, 2, + hscale, 4); - /* set vertical scale */ - status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, VSCALE_CTRL, 2, vscale, 4); + /* set vertical scale */ + status = + cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, VSCALE_CTRL, 2, + vscale, 4); - return status; + return status; } /************************************************************************************* @@ -926,397 +1337,697 @@ int cx231xx_resolution_set(struct cx231xx *dev) *************************************************************************************/ int cx231xx_init_ctrl_pin_status(struct cx231xx *dev) { - u32 value; - int status = 0; + u32 value; + int status = 0; - status = cx231xx_read_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, PIN_CTRL, 2, &value, 4); - value |=(~dev->board.ctl_pin_status_mask); - status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, PIN_CTRL, 2, value, 4); + status = + cx231xx_read_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, PIN_CTRL, 2, + &value, 4); + value |= (~dev->board.ctl_pin_status_mask); + status = + cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, PIN_CTRL, 2, + value, 4); - return status; + return status; } -int cx231xx_set_agc_analog_digital_mux_select(struct cx231xx *dev, u8 analog_or_digital) +int cx231xx_set_agc_analog_digital_mux_select(struct cx231xx *dev, + u8 analog_or_digital) { - int status = 0; + int status = 0; - /* first set the direction to output */ - status = cx231xx_set_gpio_direction(dev, dev->board.agc_analog_digital_select_gpio, 1); + /* first set the direction to output */ + status = + cx231xx_set_gpio_direction(dev, + dev->board. + agc_analog_digital_select_gpio, 1); - /* 0 - demod ; 1 - Analog mode */ - status = cx231xx_set_gpio_value(dev, dev->board.agc_analog_digital_select_gpio, - analog_or_digital); + /* 0 - demod ; 1 - Analog mode */ + status = + cx231xx_set_gpio_value(dev, + dev->board.agc_analog_digital_select_gpio, + analog_or_digital); - return status; + return status; } int cx231xx_enable_i2c_for_tuner(struct cx231xx *dev, u8 I2CIndex) { - u8 value[4] ={0,0,0,0}; - int status = 0; + u8 value[4] = { 0, 0, 0, 0 }; + int status = 0; - cx231xx_info("Changing the i2c port for tuner to %d\n",I2CIndex); + cx231xx_info("Changing the i2c port for tuner to %d\n", I2CIndex); - status = cx231xx_read_ctrl_reg(dev,VRT_GET_REGISTER, PWR_CTL_EN, value, 4); - if(status < 0) - return status; + status = + cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, PWR_CTL_EN, value, 4); + if (status < 0) + return status; - if(I2CIndex==I2C_1) { - if(value[0] & I2C_DEMOD_EN) { - value[0] &= ~I2C_DEMOD_EN; - status = cx231xx_write_ctrl_reg(dev,VRT_SET_REGISTER, PWR_CTL_EN,value,4); - } - } else { - if(!(value[0] & I2C_DEMOD_EN)) { - value[0] |= I2C_DEMOD_EN; - status = cx231xx_write_ctrl_reg(dev,VRT_SET_REGISTER, PWR_CTL_EN,value,4); - } - } + if (I2CIndex == I2C_1) { + if (value[0] & I2C_DEMOD_EN) { + value[0] &= ~I2C_DEMOD_EN; + status = + cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, + PWR_CTL_EN, value, 4); + } + } else { + if (!(value[0] & I2C_DEMOD_EN)) { + value[0] |= I2C_DEMOD_EN; + status = + cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, + PWR_CTL_EN, value, 4); + } + } - return status; + return status; } - /************************************************************************************* * D I F - B L O C K C O N T R O L functions * *************************************************************************************/ -int cx231xx_dif_configure_C2HH_for_low_IF(struct cx231xx *dev, u32 mode, - u32 function_mode, u32 standard) -{ - int status = 0; - - if(mode == V4L2_TUNER_RADIO) { - /* C2HH */ - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, - AFE_CTRL_C2HH_SRC_CTRL, 30, 31, 0x1); /* lo if big signal */ - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, - AFE_CTRL_C2HH_SRC_CTRL, 23, 24, function_mode); /* FUNC_MODE = DIF */ - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, - AFE_CTRL_C2HH_SRC_CTRL, 15, 22, 0xFF); /* IF_MODE */ - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, - AFE_CTRL_C2HH_SRC_CTRL, 9, 9, 0x1); /* no inv */ - } - else { - switch(standard) { - case V4L2_STD_NTSC_M: /* 75 IRE Setup */ - case V4L2_STD_NTSC_M_JP: /* Japan, 0 IRE Setup */ - case V4L2_STD_PAL_M: - case V4L2_STD_PAL_N: - case V4L2_STD_PAL_Nc: - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, - AFE_CTRL_C2HH_SRC_CTRL, 30, 31, 0x1); /* lo if big signal */ - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, - AFE_CTRL_C2HH_SRC_CTRL, 23, 24, function_mode); /* FUNC_MODE = DIF */ - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, - AFE_CTRL_C2HH_SRC_CTRL, 15, 22, 0xb); /* IF_MODE */ - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, - AFE_CTRL_C2HH_SRC_CTRL, 9, 9, 0x1); /* no inv */ - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, - AUD_IO_CTRL, 0, 31, 0x00000003); /* 0x124, AUD_CHAN1_SRC = 0x3 */ - break; - - case V4L2_STD_PAL_B: - case V4L2_STD_PAL_G: - /* C2HH setup */ - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, - AFE_CTRL_C2HH_SRC_CTRL, 30, 31, 0x1); /* lo if big signal */ - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, - AFE_CTRL_C2HH_SRC_CTRL, 23, 24, function_mode); /* FUNC_MODE = DIF */ - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, - AFE_CTRL_C2HH_SRC_CTRL, 15, 22, 0xE); /* IF_MODE */ - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, - AFE_CTRL_C2HH_SRC_CTRL, 9, 9, 0x1); /* no inv */ - break; - - case V4L2_STD_PAL_D: - case V4L2_STD_PAL_I: - case V4L2_STD_SECAM_L: - case V4L2_STD_SECAM_LC: - case V4L2_STD_SECAM_B: - case V4L2_STD_SECAM_D: - case V4L2_STD_SECAM_G: - case V4L2_STD_SECAM_K: - case V4L2_STD_SECAM_K1: - /* C2HH setup */ - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, - AFE_CTRL_C2HH_SRC_CTRL, 30, 31, 0x1); /* lo if big signal */ - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, - AFE_CTRL_C2HH_SRC_CTRL, 23, 24, function_mode); /* FUNC_MODE = DIF */ - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, - AFE_CTRL_C2HH_SRC_CTRL, 15, 22, 0xF); /* IF_MODE */ - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, - AFE_CTRL_C2HH_SRC_CTRL, 9, 9, 0x1); /* no inv */ - break; - - case DIF_USE_BASEBAND: - default: - /* do nothing to config C2HH for baseband */ - break; - } - } - - return status; +int cx231xx_dif_configure_C2HH_for_low_IF(struct cx231xx *dev, u32 mode, + u32 function_mode, u32 standard) +{ + int status = 0; + + if (mode == V4L2_TUNER_RADIO) { + /* C2HH */ + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, AFE_CTRL_C2HH_SRC_CTRL, 30, 31, 0x1); /* lo if big signal */ + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, AFE_CTRL_C2HH_SRC_CTRL, 23, 24, function_mode); /* FUNC_MODE = DIF */ + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, AFE_CTRL_C2HH_SRC_CTRL, 15, 22, 0xFF); /* IF_MODE */ + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, AFE_CTRL_C2HH_SRC_CTRL, 9, 9, 0x1); /* no inv */ + } else { + switch (standard) { + case V4L2_STD_NTSC_M: /* 75 IRE Setup */ + case V4L2_STD_NTSC_M_JP: /* Japan, 0 IRE Setup */ + case V4L2_STD_PAL_M: + case V4L2_STD_PAL_N: + case V4L2_STD_PAL_Nc: + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, AFE_CTRL_C2HH_SRC_CTRL, 30, 31, 0x1); /* lo if big signal */ + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, AFE_CTRL_C2HH_SRC_CTRL, 23, 24, function_mode); /* FUNC_MODE = DIF */ + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, AFE_CTRL_C2HH_SRC_CTRL, 15, 22, 0xb); /* IF_MODE */ + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, AFE_CTRL_C2HH_SRC_CTRL, 9, 9, 0x1); /* no inv */ + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, AUD_IO_CTRL, 0, 31, 0x00000003); /* 0x124, AUD_CHAN1_SRC = 0x3 */ + break; + + case V4L2_STD_PAL_B: + case V4L2_STD_PAL_G: + /* C2HH setup */ + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, AFE_CTRL_C2HH_SRC_CTRL, 30, 31, 0x1); /* lo if big signal */ + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, AFE_CTRL_C2HH_SRC_CTRL, 23, 24, function_mode); /* FUNC_MODE = DIF */ + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, AFE_CTRL_C2HH_SRC_CTRL, 15, 22, 0xE); /* IF_MODE */ + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, AFE_CTRL_C2HH_SRC_CTRL, 9, 9, 0x1); /* no inv */ + break; + + case V4L2_STD_PAL_D: + case V4L2_STD_PAL_I: + case V4L2_STD_SECAM_L: + case V4L2_STD_SECAM_LC: + case V4L2_STD_SECAM_B: + case V4L2_STD_SECAM_D: + case V4L2_STD_SECAM_G: + case V4L2_STD_SECAM_K: + case V4L2_STD_SECAM_K1: + /* C2HH setup */ + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, AFE_CTRL_C2HH_SRC_CTRL, 30, 31, 0x1); /* lo if big signal */ + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, AFE_CTRL_C2HH_SRC_CTRL, 23, 24, function_mode); /* FUNC_MODE = DIF */ + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, AFE_CTRL_C2HH_SRC_CTRL, 15, 22, 0xF); /* IF_MODE */ + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, AFE_CTRL_C2HH_SRC_CTRL, 9, 9, 0x1); /* no inv */ + break; + + case DIF_USE_BASEBAND: + default: + /* do nothing to config C2HH for baseband */ + break; + } + } + + return status; } int cx231xx_dif_set_standard(struct cx231xx *dev, u32 standard) { - int status = 0; - u32 dif_misc_ctrl_value = 0; - u32 func_mode = 0; - - cx231xx_info("%s: setStandard to %x\n",__func__,standard); - - status = cx231xx_read_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, - DIF_MISC_CTRL, 2, &dif_misc_ctrl_value, 4); - if(standard != DIF_USE_BASEBAND ) - dev->norm = standard; - - switch (dev->model) { - case CX231XX_BOARD_CNXT_RDE_250: - case CX231XX_BOARD_CNXT_RDU_250: - func_mode=0x03; - break; - default: - func_mode=0x01; - } - - status = cx231xx_dif_configure_C2HH_for_low_IF(dev, dev->active_mode, func_mode, standard); - - - if(standard == DIF_USE_BASEBAND ) { /* base band */ - - /* There is a different SRC_PHASE_INC value for baseband vs. DIF */ - status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, - DIF_SRC_PHASE_INC, 2, 0xDF7DF83, 4); - status = cx231xx_read_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, - DIF_MISC_CTRL, 2, &dif_misc_ctrl_value, 4); - dif_misc_ctrl_value |= FLD_DIF_DIF_BYPASS; - status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, - DIF_MISC_CTRL, 2, dif_misc_ctrl_value, 4); - - } else if ( standard & (V4L2_STD_PAL_B | V4L2_STD_PAL_G) ) { - - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_PLL_CTRL, 0, 31, 0x6503bc0c); - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_PLL_CTRL1, 0, 31, 0xbd038c85); - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_PLL_CTRL2, 0, 31, 0x1db4640a); - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_PLL_CTRL3, 0, 31, 0x00008800); - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_AGC_IF_REF, 0, 31, 0x444C1380); - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_AGC_CTRL_IF, 0, 31, 0xDA302600); - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_AGC_CTRL_INT, 0, 31, 0xDA261700); - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_AGC_CTRL_RF, 0, 31, 0xDA262600); - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_AGC_IF_INT_CURRENT, 0, 31, 0x26001700); - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_AGC_RF_CURRENT, 0, 31, 0x00002660); - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_VIDEO_AGC_CTRL, 0, 31, 0x72500800); - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_VID_AUD_OVERRIDE, 0, 31, 0x27000100); - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_AV_SEP_CTRL, 0, 31, 0x3F3530EC); - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_COMP_FLT_CTRL, 0, 31, 0x00A653A8); - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_SRC_PHASE_INC, 0, 31, 0x1befbf06); - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_SRC_GAIN_CONTROL, 0, 31, 0x000035e8); - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_RPT_VARIANCE, 0, 31, 0x00000000); - /* Save the Spec Inversion value */ - dif_misc_ctrl_value &= FLD_DIF_SPEC_INV; - dif_misc_ctrl_value |=0x3a013F11; - - } else if( standard & V4L2_STD_PAL_D ) { - - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_PLL_CTRL, 0, 31, 0x6503bc0c); - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_PLL_CTRL1, 0, 31, 0xbd038c85); - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_PLL_CTRL2, 0, 31, 0x1db4640a); - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_PLL_CTRL3, 0, 31, 0x00008800); - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_AGC_IF_REF, 0, 31, 0x444C1380); - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_AGC_CTRL_IF, 0, 31, 0xDA302600); - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_AGC_CTRL_INT, 0, 31, 0xDA261700); - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_AGC_CTRL_RF, 0, 31, 0xDA262600); - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_AGC_IF_INT_CURRENT, 0, 31, 0x26001700); - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_AGC_RF_CURRENT, 0, 31, 0x00002660); - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_VIDEO_AGC_CTRL, 0, 31, 0x72500800); - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_VID_AUD_OVERRIDE, 0, 31, 0x27000100); - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_AV_SEP_CTRL, 0, 31, 0x3F3934EA); - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_COMP_FLT_CTRL, 0, 31, 0x00000000); - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_SRC_PHASE_INC, 0, 31, 0x1befbf06); - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_SRC_GAIN_CONTROL, 0, 31, 0x000035e8); - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_RPT_VARIANCE, 0, 31, 0x00000000); - /* Save the Spec Inversion value */ - dif_misc_ctrl_value &= FLD_DIF_SPEC_INV; - dif_misc_ctrl_value |=0x3a023F11; - - } else if( standard & V4L2_STD_PAL_I ) { - - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_PLL_CTRL, 0, 31, 0x6503bc0c); - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_PLL_CTRL1, 0, 31, 0xbd038c85); - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_PLL_CTRL2, 0, 31, 0x1db4640a); - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_PLL_CTRL3, 0, 31, 0x00008800); - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_AGC_IF_REF, 0, 31, 0x444C1380); - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_AGC_CTRL_IF, 0, 31, 0xDA302600); - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_AGC_CTRL_INT, 0, 31, 0xDA261700); - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_AGC_CTRL_RF, 0, 31, 0xDA262600); - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_AGC_IF_INT_CURRENT, 0, 31, 0x26001700); - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_AGC_RF_CURRENT, 0, 31, 0x00002660); - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_VIDEO_AGC_CTRL, 0, 31, 0x72500800); - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_VID_AUD_OVERRIDE, 0, 31, 0x27000100); - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_AV_SEP_CTRL, 0, 31, 0x5F39A934); - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_COMP_FLT_CTRL, 0, 31, 0x00000000); - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_SRC_PHASE_INC, 0, 31, 0x1befbf06); - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_SRC_GAIN_CONTROL, 0, 31, 0x000035e8); - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_RPT_VARIANCE, 0, 31, 0x00000000); - /* Save the Spec Inversion value */ - dif_misc_ctrl_value &= FLD_DIF_SPEC_INV; - dif_misc_ctrl_value |=0x3a033F11; - - } else if( standard & V4L2_STD_PAL_M ) { - - /* improved Low Frequency Phase Noise */ - status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, - DIF_PLL_CTRL, 2, 0xFF01FF0C, 4); - status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, - DIF_PLL_CTRL1, 2, 0xbd038c85, 4); - status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, - DIF_PLL_CTRL2, 2, 0x1db4640a, 4); - status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, - DIF_PLL_CTRL3, 2, 0x00008800, 4); - status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, - DIF_AGC_IF_REF, 2, 0x444C1380, 4); - status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, - DIF_AGC_IF_INT_CURRENT, 2, 0x26001700, 4); - status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, - DIF_AGC_RF_CURRENT, 2, 0x00002660, 4); - status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, - DIF_VIDEO_AGC_CTRL, 2, 0x72500800, 4); - status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, - DIF_VID_AUD_OVERRIDE, 2, 0x27000100, 4); - status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, - DIF_AV_SEP_CTRL, 2, 0x012c405d, 4); - status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, - DIF_COMP_FLT_CTRL, 2, 0x009f50c1, 4); - status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, - DIF_SRC_PHASE_INC, 2, 0x1befbf06, 4); - status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, - DIF_SRC_GAIN_CONTROL, 2, 0x000035e8, 4); - status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, - DIF_SOFT_RST_CTRL_REVB, 2, 0x00000000, 4); - - /* Save the Spec Inversion value */ - dif_misc_ctrl_value &= FLD_DIF_SPEC_INV; - dif_misc_ctrl_value |= 0x3A0A3F10; - - } else if( standard & (V4L2_STD_PAL_N | V4L2_STD_PAL_Nc) ) { - - /* improved Low Frequency Phase Noise */ - status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, DIF_PLL_CTRL, 2, 0xFF01FF0C, 4); - status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, DIF_PLL_CTRL1, 2, 0xbd038c85, 4); - status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, DIF_PLL_CTRL2, 2, 0x1db4640a, 4); - status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, DIF_PLL_CTRL3, 2, 0x00008800, 4); - status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, DIF_AGC_IF_REF, 2, 0x444C1380, 4); - status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, DIF_AGC_IF_INT_CURRENT, 2, 0x26001700, 4); - status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, DIF_AGC_RF_CURRENT, 2, 0x00002660, 4); - status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, DIF_VIDEO_AGC_CTRL, 2, 0x72500800, 4); - status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, DIF_VID_AUD_OVERRIDE, 2, 0x27000100, 4); - status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, DIF_AV_SEP_CTRL, 2, 0x012c405d, 4); - status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, DIF_COMP_FLT_CTRL, 2, 0x009f50c1, 4); - status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, DIF_SRC_PHASE_INC, 2, 0x1befbf06, 4); - status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, DIF_SRC_GAIN_CONTROL, 2, 0x000035e8, 4); - status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, DIF_SOFT_RST_CTRL_REVB, 2, 0x00000000, 4); - - /* Save the Spec Inversion value */ - dif_misc_ctrl_value &= FLD_DIF_SPEC_INV; - dif_misc_ctrl_value = 0x3A093F10; - - } else if( standard & ( V4L2_STD_SECAM_B | V4L2_STD_SECAM_D | V4L2_STD_SECAM_G | - V4L2_STD_SECAM_K | V4L2_STD_SECAM_K1) ) { - - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_PLL_CTRL, 0, 31, 0x6503bc0c); - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_PLL_CTRL1, 0, 31, 0xbd038c85); - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_PLL_CTRL2, 0, 31, 0x1db4640a); - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_PLL_CTRL3, 0, 31, 0x00008800); - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_AGC_IF_REF, 0, 31, 0x888C0380); - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_AGC_CTRL_IF, 0, 31, 0xe0262600); - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_AGC_CTRL_INT, 0, 31, 0xc2171700); - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_AGC_CTRL_RF, 0, 31, 0xc2262600); - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_AGC_IF_INT_CURRENT, 0, 31, 0x26001700); - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_AGC_RF_CURRENT, 0, 31, 0x00002660); - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_VID_AUD_OVERRIDE, 0, 31, 0x27000100); - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_AV_SEP_CTRL, 0, 31, 0x3F3530ec); - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_COMP_FLT_CTRL, 0, 31, 0x00000000); - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_SRC_PHASE_INC, 0, 31, 0x1befbf06); - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_SRC_GAIN_CONTROL, 0, 31, 0x000035e8); - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_RPT_VARIANCE, 0, 31, 0x00000000); - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_VIDEO_AGC_CTRL, 0, 31, 0xf4000000); - - /* Save the Spec Inversion value */ - dif_misc_ctrl_value &= FLD_DIF_SPEC_INV; - dif_misc_ctrl_value |=0x3a023F11; - - } else if( standard & (V4L2_STD_SECAM_L | V4L2_STD_SECAM_LC) ) { - - /* Is it SECAM_L1? */ - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_PLL_CTRL, 0, 31, 0x6503bc0c); - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_PLL_CTRL1, 0, 31, 0xbd038c85); - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_PLL_CTRL2, 0, 31, 0x1db4640a); - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_PLL_CTRL3, 0, 31, 0x00008800); - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_AGC_IF_REF, 0, 31, 0x888C0380); - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_AGC_CTRL_IF, 0, 31, 0xe0262600); - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_AGC_CTRL_INT, 0, 31, 0xc2171700); - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_AGC_CTRL_RF, 0, 31, 0xc2262600); - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_AGC_IF_INT_CURRENT, 0, 31, 0x26001700); - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_AGC_RF_CURRENT, 0, 31, 0x00002660); - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_VID_AUD_OVERRIDE, 0, 31, 0x27000100); - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_AV_SEP_CTRL, 0, 31, 0x3F3530ec); - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_COMP_FLT_CTRL, 0, 31, 0x00000000); - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_SRC_PHASE_INC, 0, 31, 0x1befbf06); - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_SRC_GAIN_CONTROL, 0, 31, 0x000035e8); - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_RPT_VARIANCE, 0, 31, 0x00000000); - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_VIDEO_AGC_CTRL, 0, 31, 0xf2560000); - - /* Save the Spec Inversion value */ - dif_misc_ctrl_value &= FLD_DIF_SPEC_INV; - dif_misc_ctrl_value |=0x3a023F11; - - } else { /* V4L2_STD_NTSC_M (75 IRE Setup) Or V4L2_STD_NTSC_M_JP (Japan, 0 IRE Setup) */ - - /* For NTSC the centre frequency of video coming out of sidewinder is - around 7.1MHz or 3.6MHz depending on the spectral inversion. - so for a non spectrally inverted channel the pll freq word is 0x03420c49 - */ - - status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, DIF_PLL_CTRL, 2, 0x6503BC0C, 4); - status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, DIF_PLL_CTRL1, 2, 0xBD038C85, 4); - status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, DIF_PLL_CTRL2, 2, 0x1DB4640A, 4); - status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, DIF_PLL_CTRL3, 2, 0x00008800, 4); - status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, DIF_AGC_IF_REF, 2, 0x444C0380, 4); - status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, DIF_AGC_IF_INT_CURRENT, 2, 0x26001700, 4); - status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, DIF_AGC_RF_CURRENT, 2, 0x00002660, 4); - status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, DIF_VIDEO_AGC_CTRL, 2, 0x04000800, 4); - status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, DIF_VID_AUD_OVERRIDE, 2, 0x27000100, 4); - status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, DIF_AV_SEP_CTRL, 2, 0x01296e1f, 4); - - status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, DIF_COMP_FLT_CTRL, 2, 0x009f50c1, 4); - status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, DIF_SRC_PHASE_INC, 2, 0x1befbf06, 4); - status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, DIF_SRC_GAIN_CONTROL, 2, 0x000035e8, 4); - - status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, DIF_AGC_CTRL_IF, 2, 0xC2262600, 4); - status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, DIF_AGC_CTRL_INT, 2, 0xC2262600, 4); - status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, DIF_AGC_CTRL_RF, 2, 0xC2262600, 4); - - /* Save the Spec Inversion value */ - dif_misc_ctrl_value &= FLD_DIF_SPEC_INV; - dif_misc_ctrl_value |= 0x3a003F10; - - } - - /* The AGC values should be the same for all standards, - AUD_SRC_SEL[19] should always be disabled */ - dif_misc_ctrl_value &= ~FLD_DIF_AUD_SRC_SEL; - - /* It is still possible to get Set Standard calls even when we are in FM mode - This is done to override the value for FM. */ - if (dev->active_mode == V4L2_TUNER_RADIO) - dif_misc_ctrl_value = 0x7a080000; - - /* Write the calculated value for misc ontrol register */ - status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, DIF_MISC_CTRL, 2, dif_misc_ctrl_value, 4); - - return status; + int status = 0; + u32 dif_misc_ctrl_value = 0; + u32 func_mode = 0; + + cx231xx_info("%s: setStandard to %x\n", __func__, standard); + + status = cx231xx_read_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, + DIF_MISC_CTRL, 2, &dif_misc_ctrl_value, + 4); + if (standard != DIF_USE_BASEBAND) + dev->norm = standard; + + switch (dev->model) { + case CX231XX_BOARD_CNXT_RDE_250: + case CX231XX_BOARD_CNXT_RDU_250: + func_mode = 0x03; + break; + default: + func_mode = 0x01; + } + + status = + cx231xx_dif_configure_C2HH_for_low_IF(dev, dev->active_mode, + func_mode, standard); + + if (standard == DIF_USE_BASEBAND) { /* base band */ + + /* There is a different SRC_PHASE_INC value for baseband vs. DIF */ + status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, + DIF_SRC_PHASE_INC, 2, 0xDF7DF83, + 4); + status = + cx231xx_read_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, + DIF_MISC_CTRL, 2, + &dif_misc_ctrl_value, 4); + dif_misc_ctrl_value |= FLD_DIF_DIF_BYPASS; + status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, + DIF_MISC_CTRL, 2, + dif_misc_ctrl_value, 4); + + } else if (standard & (V4L2_STD_PAL_B | V4L2_STD_PAL_G)) { + + status = + cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + DIF_PLL_CTRL, 0, 31, 0x6503bc0c); + status = + cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + DIF_PLL_CTRL1, 0, 31, 0xbd038c85); + status = + cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + DIF_PLL_CTRL2, 0, 31, 0x1db4640a); + status = + cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + DIF_PLL_CTRL3, 0, 31, 0x00008800); + status = + cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + DIF_AGC_IF_REF, 0, 31, 0x444C1380); + status = + cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + DIF_AGC_CTRL_IF, 0, 31, 0xDA302600); + status = + cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + DIF_AGC_CTRL_INT, 0, 31, 0xDA261700); + status = + cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + DIF_AGC_CTRL_RF, 0, 31, 0xDA262600); + status = + cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + DIF_AGC_IF_INT_CURRENT, 0, 31, + 0x26001700); + status = + cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + DIF_AGC_RF_CURRENT, 0, 31, + 0x00002660); + status = + cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + DIF_VIDEO_AGC_CTRL, 0, 31, + 0x72500800); + status = + cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + DIF_VID_AUD_OVERRIDE, 0, 31, + 0x27000100); + status = + cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + DIF_AV_SEP_CTRL, 0, 31, 0x3F3530EC); + status = + cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + DIF_COMP_FLT_CTRL, 0, 31, + 0x00A653A8); + status = + cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + DIF_SRC_PHASE_INC, 0, 31, + 0x1befbf06); + status = + cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + DIF_SRC_GAIN_CONTROL, 0, 31, + 0x000035e8); + status = + cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + DIF_RPT_VARIANCE, 0, 31, 0x00000000); + /* Save the Spec Inversion value */ + dif_misc_ctrl_value &= FLD_DIF_SPEC_INV; + dif_misc_ctrl_value |= 0x3a013F11; + + } else if (standard & V4L2_STD_PAL_D) { + + status = + cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + DIF_PLL_CTRL, 0, 31, 0x6503bc0c); + status = + cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + DIF_PLL_CTRL1, 0, 31, 0xbd038c85); + status = + cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + DIF_PLL_CTRL2, 0, 31, 0x1db4640a); + status = + cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + DIF_PLL_CTRL3, 0, 31, 0x00008800); + status = + cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + DIF_AGC_IF_REF, 0, 31, 0x444C1380); + status = + cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + DIF_AGC_CTRL_IF, 0, 31, 0xDA302600); + status = + cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + DIF_AGC_CTRL_INT, 0, 31, 0xDA261700); + status = + cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + DIF_AGC_CTRL_RF, 0, 31, 0xDA262600); + status = + cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + DIF_AGC_IF_INT_CURRENT, 0, 31, + 0x26001700); + status = + cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + DIF_AGC_RF_CURRENT, 0, 31, + 0x00002660); + status = + cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + DIF_VIDEO_AGC_CTRL, 0, 31, + 0x72500800); + status = + cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + DIF_VID_AUD_OVERRIDE, 0, 31, + 0x27000100); + status = + cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + DIF_AV_SEP_CTRL, 0, 31, 0x3F3934EA); + status = + cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + DIF_COMP_FLT_CTRL, 0, 31, + 0x00000000); + status = + cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + DIF_SRC_PHASE_INC, 0, 31, + 0x1befbf06); + status = + cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + DIF_SRC_GAIN_CONTROL, 0, 31, + 0x000035e8); + status = + cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + DIF_RPT_VARIANCE, 0, 31, 0x00000000); + /* Save the Spec Inversion value */ + dif_misc_ctrl_value &= FLD_DIF_SPEC_INV; + dif_misc_ctrl_value |= 0x3a023F11; + + } else if (standard & V4L2_STD_PAL_I) { + + status = + cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + DIF_PLL_CTRL, 0, 31, 0x6503bc0c); + status = + cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + DIF_PLL_CTRL1, 0, 31, 0xbd038c85); + status = + cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + DIF_PLL_CTRL2, 0, 31, 0x1db4640a); + status = + cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + DIF_PLL_CTRL3, 0, 31, 0x00008800); + status = + cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + DIF_AGC_IF_REF, 0, 31, 0x444C1380); + status = + cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + DIF_AGC_CTRL_IF, 0, 31, 0xDA302600); + status = + cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + DIF_AGC_CTRL_INT, 0, 31, 0xDA261700); + status = + cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + DIF_AGC_CTRL_RF, 0, 31, 0xDA262600); + status = + cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + DIF_AGC_IF_INT_CURRENT, 0, 31, + 0x26001700); + status = + cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + DIF_AGC_RF_CURRENT, 0, 31, + 0x00002660); + status = + cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + DIF_VIDEO_AGC_CTRL, 0, 31, + 0x72500800); + status = + cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + DIF_VID_AUD_OVERRIDE, 0, 31, + 0x27000100); + status = + cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + DIF_AV_SEP_CTRL, 0, 31, 0x5F39A934); + status = + cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + DIF_COMP_FLT_CTRL, 0, 31, + 0x00000000); + status = + cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + DIF_SRC_PHASE_INC, 0, 31, + 0x1befbf06); + status = + cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + DIF_SRC_GAIN_CONTROL, 0, 31, + 0x000035e8); + status = + cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + DIF_RPT_VARIANCE, 0, 31, 0x00000000); + /* Save the Spec Inversion value */ + dif_misc_ctrl_value &= FLD_DIF_SPEC_INV; + dif_misc_ctrl_value |= 0x3a033F11; + + } else if (standard & V4L2_STD_PAL_M) { + + /* improved Low Frequency Phase Noise */ + status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, + DIF_PLL_CTRL, 2, 0xFF01FF0C, 4); + status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, + DIF_PLL_CTRL1, 2, 0xbd038c85, + 4); + status = + cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, + DIF_PLL_CTRL2, 2, 0x1db4640a, 4); + status = + cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, + DIF_PLL_CTRL3, 2, 0x00008800, 4); + status = + cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, + DIF_AGC_IF_REF, 2, 0x444C1380, 4); + status = + cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, + DIF_AGC_IF_INT_CURRENT, 2, + 0x26001700, 4); + status = + cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, + DIF_AGC_RF_CURRENT, 2, 0x00002660, + 4); + status = + cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, + DIF_VIDEO_AGC_CTRL, 2, 0x72500800, + 4); + status = + cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, + DIF_VID_AUD_OVERRIDE, 2, 0x27000100, + 4); + status = + cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, + DIF_AV_SEP_CTRL, 2, 0x012c405d, 4); + status = + cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, + DIF_COMP_FLT_CTRL, 2, 0x009f50c1, 4); + status = + cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, + DIF_SRC_PHASE_INC, 2, 0x1befbf06, 4); + status = + cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, + DIF_SRC_GAIN_CONTROL, 2, 0x000035e8, + 4); + status = + cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, + DIF_SOFT_RST_CTRL_REVB, 2, + 0x00000000, 4); + + /* Save the Spec Inversion value */ + dif_misc_ctrl_value &= FLD_DIF_SPEC_INV; + dif_misc_ctrl_value |= 0x3A0A3F10; + + } else if (standard & (V4L2_STD_PAL_N | V4L2_STD_PAL_Nc)) { + + /* improved Low Frequency Phase Noise */ + status = + cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, + DIF_PLL_CTRL, 2, 0xFF01FF0C, 4); + status = + cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, + DIF_PLL_CTRL1, 2, 0xbd038c85, 4); + status = + cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, + DIF_PLL_CTRL2, 2, 0x1db4640a, 4); + status = + cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, + DIF_PLL_CTRL3, 2, 0x00008800, 4); + status = + cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, + DIF_AGC_IF_REF, 2, 0x444C1380, 4); + status = + cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, + DIF_AGC_IF_INT_CURRENT, 2, + 0x26001700, 4); + status = + cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, + DIF_AGC_RF_CURRENT, 2, 0x00002660, + 4); + status = + cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, + DIF_VIDEO_AGC_CTRL, 2, 0x72500800, + 4); + status = + cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, + DIF_VID_AUD_OVERRIDE, 2, 0x27000100, + 4); + status = + cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, + DIF_AV_SEP_CTRL, 2, 0x012c405d, 4); + status = + cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, + DIF_COMP_FLT_CTRL, 2, 0x009f50c1, 4); + status = + cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, + DIF_SRC_PHASE_INC, 2, 0x1befbf06, 4); + status = + cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, + DIF_SRC_GAIN_CONTROL, 2, 0x000035e8, + 4); + status = + cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, + DIF_SOFT_RST_CTRL_REVB, 2, + 0x00000000, 4); + + /* Save the Spec Inversion value */ + dif_misc_ctrl_value &= FLD_DIF_SPEC_INV; + dif_misc_ctrl_value = 0x3A093F10; + + } else if (standard & + (V4L2_STD_SECAM_B | V4L2_STD_SECAM_D | V4L2_STD_SECAM_G | + V4L2_STD_SECAM_K | V4L2_STD_SECAM_K1)) { + + status = + cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + DIF_PLL_CTRL, 0, 31, 0x6503bc0c); + status = + cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + DIF_PLL_CTRL1, 0, 31, 0xbd038c85); + status = + cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + DIF_PLL_CTRL2, 0, 31, 0x1db4640a); + status = + cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + DIF_PLL_CTRL3, 0, 31, 0x00008800); + status = + cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + DIF_AGC_IF_REF, 0, 31, 0x888C0380); + status = + cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + DIF_AGC_CTRL_IF, 0, 31, 0xe0262600); + status = + cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + DIF_AGC_CTRL_INT, 0, 31, 0xc2171700); + status = + cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + DIF_AGC_CTRL_RF, 0, 31, 0xc2262600); + status = + cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + DIF_AGC_IF_INT_CURRENT, 0, 31, + 0x26001700); + status = + cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + DIF_AGC_RF_CURRENT, 0, 31, + 0x00002660); + status = + cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + DIF_VID_AUD_OVERRIDE, 0, 31, + 0x27000100); + status = + cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + DIF_AV_SEP_CTRL, 0, 31, 0x3F3530ec); + status = + cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + DIF_COMP_FLT_CTRL, 0, 31, + 0x00000000); + status = + cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + DIF_SRC_PHASE_INC, 0, 31, + 0x1befbf06); + status = + cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + DIF_SRC_GAIN_CONTROL, 0, 31, + 0x000035e8); + status = + cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + DIF_RPT_VARIANCE, 0, 31, 0x00000000); + status = + cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + DIF_VIDEO_AGC_CTRL, 0, 31, + 0xf4000000); + + /* Save the Spec Inversion value */ + dif_misc_ctrl_value &= FLD_DIF_SPEC_INV; + dif_misc_ctrl_value |= 0x3a023F11; + + } else if (standard & (V4L2_STD_SECAM_L | V4L2_STD_SECAM_LC)) { + + /* Is it SECAM_L1? */ + status = + cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + DIF_PLL_CTRL, 0, 31, 0x6503bc0c); + status = + cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + DIF_PLL_CTRL1, 0, 31, 0xbd038c85); + status = + cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + DIF_PLL_CTRL2, 0, 31, 0x1db4640a); + status = + cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + DIF_PLL_CTRL3, 0, 31, 0x00008800); + status = + cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + DIF_AGC_IF_REF, 0, 31, 0x888C0380); + status = + cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + DIF_AGC_CTRL_IF, 0, 31, 0xe0262600); + status = + cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + DIF_AGC_CTRL_INT, 0, 31, 0xc2171700); + status = + cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + DIF_AGC_CTRL_RF, 0, 31, 0xc2262600); + status = + cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + DIF_AGC_IF_INT_CURRENT, 0, 31, + 0x26001700); + status = + cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + DIF_AGC_RF_CURRENT, 0, 31, + 0x00002660); + status = + cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + DIF_VID_AUD_OVERRIDE, 0, 31, + 0x27000100); + status = + cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + DIF_AV_SEP_CTRL, 0, 31, 0x3F3530ec); + status = + cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + DIF_COMP_FLT_CTRL, 0, 31, + 0x00000000); + status = + cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + DIF_SRC_PHASE_INC, 0, 31, + 0x1befbf06); + status = + cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + DIF_SRC_GAIN_CONTROL, 0, 31, + 0x000035e8); + status = + cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + DIF_RPT_VARIANCE, 0, 31, 0x00000000); + status = + cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + DIF_VIDEO_AGC_CTRL, 0, 31, + 0xf2560000); + + /* Save the Spec Inversion value */ + dif_misc_ctrl_value &= FLD_DIF_SPEC_INV; + dif_misc_ctrl_value |= 0x3a023F11; + + } else { /* V4L2_STD_NTSC_M (75 IRE Setup) Or V4L2_STD_NTSC_M_JP (Japan, 0 IRE Setup) */ + + /* For NTSC the centre frequency of video coming out of sidewinder is + around 7.1MHz or 3.6MHz depending on the spectral inversion. + so for a non spectrally inverted channel the pll freq word is 0x03420c49 + */ + + status = + cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, + DIF_PLL_CTRL, 2, 0x6503BC0C, 4); + status = + cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, + DIF_PLL_CTRL1, 2, 0xBD038C85, 4); + status = + cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, + DIF_PLL_CTRL2, 2, 0x1DB4640A, 4); + status = + cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, + DIF_PLL_CTRL3, 2, 0x00008800, 4); + status = + cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, + DIF_AGC_IF_REF, 2, 0x444C0380, 4); + status = + cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, + DIF_AGC_IF_INT_CURRENT, 2, + 0x26001700, 4); + status = + cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, + DIF_AGC_RF_CURRENT, 2, 0x00002660, + 4); + status = + cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, + DIF_VIDEO_AGC_CTRL, 2, 0x04000800, + 4); + status = + cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, + DIF_VID_AUD_OVERRIDE, 2, 0x27000100, + 4); + status = + cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, + DIF_AV_SEP_CTRL, 2, 0x01296e1f, 4); + + status = + cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, + DIF_COMP_FLT_CTRL, 2, 0x009f50c1, 4); + status = + cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, + DIF_SRC_PHASE_INC, 2, 0x1befbf06, 4); + status = + cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, + DIF_SRC_GAIN_CONTROL, 2, 0x000035e8, + 4); + + status = + cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, + DIF_AGC_CTRL_IF, 2, 0xC2262600, 4); + status = + cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, + DIF_AGC_CTRL_INT, 2, 0xC2262600, 4); + status = + cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, + DIF_AGC_CTRL_RF, 2, 0xC2262600, 4); + + /* Save the Spec Inversion value */ + dif_misc_ctrl_value &= FLD_DIF_SPEC_INV; + dif_misc_ctrl_value |= 0x3a003F10; + + } + + /* The AGC values should be the same for all standards, + AUD_SRC_SEL[19] should always be disabled */ + dif_misc_ctrl_value &= ~FLD_DIF_AUD_SRC_SEL; + + /* It is still possible to get Set Standard calls even when we are in FM mode + This is done to override the value for FM. */ + if (dev->active_mode == V4L2_TUNER_RADIO) + dif_misc_ctrl_value = 0x7a080000; + + /* Write the calculated value for misc ontrol register */ + status = + cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, DIF_MISC_CTRL, + 2, dif_misc_ctrl_value, 4); + + return status; } int cx231xx_tuner_pre_channel_change(struct cx231xx *dev) @@ -1325,540 +2036,571 @@ int cx231xx_tuner_pre_channel_change(struct cx231xx *dev) u32 dwval; /* Set the RF and IF k_agc values to 3 */ - status = cx231xx_read_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, - DIF_AGC_IF_REF, 2, &dwval, 4); - dwval &= ~(FLD_DIF_K_AGC_RF | FLD_DIF_K_AGC_IF); - dwval |= 0x33000000; + status = cx231xx_read_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, + DIF_AGC_IF_REF, 2, &dwval, 4); + dwval &= ~(FLD_DIF_K_AGC_RF | FLD_DIF_K_AGC_IF); + dwval |= 0x33000000; - status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, - DIF_AGC_IF_REF, 2, dwval, 4); + status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, + DIF_AGC_IF_REF, 2, dwval, 4); - return status; + return status; } int cx231xx_tuner_post_channel_change(struct cx231xx *dev) -{ - int status = 0; +{ + int status = 0; u32 dwval; - /* Set the RF and IF k_agc values to 4 for PAL/NTSC and 8 for SECAM */ - status = cx231xx_read_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, - DIF_AGC_IF_REF, 2, &dwval, 4); - dwval &= ~(FLD_DIF_K_AGC_RF | FLD_DIF_K_AGC_IF); + /* Set the RF and IF k_agc values to 4 for PAL/NTSC and 8 for SECAM */ + status = cx231xx_read_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, + DIF_AGC_IF_REF, 2, &dwval, 4); + dwval &= ~(FLD_DIF_K_AGC_RF | FLD_DIF_K_AGC_IF); - if(dev->norm & ( V4L2_STD_SECAM_L | V4L2_STD_SECAM_B | V4L2_STD_SECAM_D) ) { - dwval |= 0x88000000; - } else { - dwval |= 0x44000000; - } + if (dev-> + norm & (V4L2_STD_SECAM_L | V4L2_STD_SECAM_B | V4L2_STD_SECAM_D)) { + dwval |= 0x88000000; + } else { + dwval |= 0x44000000; + } - status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, - DIF_AGC_IF_REF, 2, dwval, 4); + status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, + DIF_AGC_IF_REF, 2, dwval, 4); - return status; + return status; } - - /************************************************************************************* * F L A T I R O N - B L O C K C O N T R O L functions * *************************************************************************************/ int cx231xx_flatiron_initialize(struct cx231xx *dev) { - int status = 0; - u32 value; - - status = cx231xx_read_i2c_data(dev, Flatrion_DEVICE_ADDRESS, CH_PWR_CTRL1, 1, &value, 1); - /* enables clock to delta-sigma and decimation filter */ - value |= 0x80; - status = cx231xx_write_i2c_data(dev, Flatrion_DEVICE_ADDRESS, - CH_PWR_CTRL1, 1, value, 1); - /* power up all channel */ - status = cx231xx_write_i2c_data(dev, Flatrion_DEVICE_ADDRESS, - CH_PWR_CTRL2, 1, 0x00, 1); - - return status; + int status = 0; + u32 value; + + status = + cx231xx_read_i2c_data(dev, Flatrion_DEVICE_ADDRESS, CH_PWR_CTRL1, 1, + &value, 1); + /* enables clock to delta-sigma and decimation filter */ + value |= 0x80; + status = cx231xx_write_i2c_data(dev, Flatrion_DEVICE_ADDRESS, + CH_PWR_CTRL1, 1, value, 1); + /* power up all channel */ + status = cx231xx_write_i2c_data(dev, Flatrion_DEVICE_ADDRESS, + CH_PWR_CTRL2, 1, 0x00, 1); + + return status; } int cx231xx_flatiron_update_power_control(struct cx231xx *dev, AV_MODE avmode) { - int status = 0; - u32 value=0; - - if(avmode!=POLARIS_AVMODE_ENXTERNAL_AV) { - status = cx231xx_read_i2c_data(dev, Flatrion_DEVICE_ADDRESS, CH_PWR_CTRL2, 1, &value, 1); - value |= 0xfe; - status = cx231xx_write_i2c_data(dev, Flatrion_DEVICE_ADDRESS, - CH_PWR_CTRL2, 1, value, 1); - } - else { - status = cx231xx_write_i2c_data(dev, Flatrion_DEVICE_ADDRESS, - CH_PWR_CTRL2, 1, 0x00, 1); - } - - return status; + int status = 0; + u32 value = 0; + + if (avmode != POLARIS_AVMODE_ENXTERNAL_AV) { + status = + cx231xx_read_i2c_data(dev, Flatrion_DEVICE_ADDRESS, + CH_PWR_CTRL2, 1, &value, 1); + value |= 0xfe; + status = cx231xx_write_i2c_data(dev, Flatrion_DEVICE_ADDRESS, + CH_PWR_CTRL2, 1, value, 1); + } else { + status = cx231xx_write_i2c_data(dev, Flatrion_DEVICE_ADDRESS, + CH_PWR_CTRL2, 1, 0x00, 1); + } + + return status; } /* set flatiron for audio input types */ int cx231xx_flatiron_set_audio_input(struct cx231xx *dev, u8 audio_input) -{ - int status = 0; - - switch(audio_input) { - case CX231XX_AMUX_LINE_IN: +{ + int status = 0; - status = cx231xx_write_i2c_data(dev, Flatrion_DEVICE_ADDRESS, - CH_PWR_CTRL2, 1, 0x00, 1); - status = cx231xx_write_i2c_data(dev, Flatrion_DEVICE_ADDRESS, - CH_PWR_CTRL1, 1, 0x80, 1); - break; - case CX231XX_AMUX_VIDEO: - default: - break; - } + switch (audio_input) { + case CX231XX_AMUX_LINE_IN: + + status = cx231xx_write_i2c_data(dev, Flatrion_DEVICE_ADDRESS, + CH_PWR_CTRL2, 1, 0x00, 1); + status = cx231xx_write_i2c_data(dev, Flatrion_DEVICE_ADDRESS, + CH_PWR_CTRL1, 1, 0x80, 1); + break; + case CX231XX_AMUX_VIDEO: + default: + break; + } - dev->ctl_ainput = audio_input; + dev->ctl_ainput = audio_input; - return status; + return status; } /************************************************************************************* * P O W E R C O N T R O L functions * *************************************************************************************/ int cx231xx_set_power_mode(struct cx231xx *dev, AV_MODE mode) -{ - u8 value[4] ={0,0,0,0}; - u32 tmp = 0; - int status = 0; - - if(dev->power_mode != mode) - dev->power_mode = mode; - else { - cx231xx_info(" setPowerMode::mode = %d, No Change req.\n",mode); - return 0; - } - - cx231xx_info(" setPowerMode::mode = %d\n",mode); - - status = cx231xx_read_ctrl_reg(dev,VRT_GET_REGISTER, PWR_CTL_EN, value, 4); - if(status < 0) - return status; - - tmp = *((u32 *)value); - - switch(mode) { - case POLARIS_AVMODE_ENXTERNAL_AV: - - tmp &= (~PWR_MODE_MASK); - - tmp |= PWR_AV_EN; - value[0]=(u8)tmp; - value[1]=(u8)(tmp>>8); - value[2]=(u8)(tmp>>16); - value[3]=(u8)(tmp>>24); - status = cx231xx_write_ctrl_reg(dev,VRT_SET_REGISTER, PWR_CTL_EN,value,4); - msleep(PWR_SLEEP_INTERVAL); - - tmp |= PWR_ISO_EN; - value[0]=(u8)tmp; - value[1]=(u8)(tmp>>8); - value[2]=(u8)(tmp>>16); - value[3]=(u8)(tmp>>24); - status = cx231xx_write_ctrl_reg(dev,VRT_SET_REGISTER, PWR_CTL_EN,value,4); - msleep(PWR_SLEEP_INTERVAL); - - tmp |=POLARIS_AVMODE_ENXTERNAL_AV; - value[0]=(u8)tmp; - value[1]=(u8)(tmp>>8); - value[2]=(u8)(tmp>>16); - value[3]=(u8)(tmp>>24); - status = cx231xx_write_ctrl_reg(dev,VRT_SET_REGISTER, PWR_CTL_EN,value,4); - - dev->xc_fw_load_done = 0; /* reset state of xceive tuner */ - break; - - case POLARIS_AVMODE_ANALOGT_TV: - - tmp &= (~PWR_DEMOD_EN); - tmp |= (I2C_DEMOD_EN); - value[0]=(u8)tmp; - value[1]=(u8)(tmp>>8); - value[2]=(u8)(tmp>>16); - value[3]=(u8)(tmp>>24); - status = cx231xx_write_ctrl_reg(dev,VRT_SET_REGISTER, PWR_CTL_EN,value,4); - msleep(PWR_SLEEP_INTERVAL); - - if(!(tmp & PWR_TUNER_EN)) { - tmp |= (PWR_TUNER_EN); - value[0]=(u8)tmp; - value[1]=(u8)(tmp>>8); - value[2]=(u8)(tmp>>16); - value[3]=(u8)(tmp>>24); - status = cx231xx_write_ctrl_reg(dev,VRT_SET_REGISTER, PWR_CTL_EN,value,4); - msleep(PWR_SLEEP_INTERVAL); - } - - if(!(tmp & PWR_AV_EN)) { - tmp |= PWR_AV_EN; - value[0]=(u8)tmp; - value[1]=(u8)(tmp>>8); - value[2]=(u8)(tmp>>16); - value[3]=(u8)(tmp>>24); - status = cx231xx_write_ctrl_reg(dev,VRT_SET_REGISTER, PWR_CTL_EN,value,4); - msleep(PWR_SLEEP_INTERVAL); - } - if(!(tmp & PWR_ISO_EN )) { - tmp |= PWR_ISO_EN; - value[0]=(u8)tmp; - value[1]=(u8)(tmp>>8); - value[2]=(u8)(tmp>>16); - value[3]=(u8)(tmp>>24); - status = cx231xx_write_ctrl_reg(dev,VRT_SET_REGISTER, PWR_CTL_EN,value,4); - msleep(PWR_SLEEP_INTERVAL); - } - - if(!(tmp & POLARIS_AVMODE_ANALOGT_TV )) { - tmp |= POLARIS_AVMODE_ANALOGT_TV; - value[0]=(u8)tmp; - value[1]=(u8)(tmp>>8); - value[2]=(u8)(tmp>>16); - value[3]=(u8)(tmp>>24); - status = cx231xx_write_ctrl_reg(dev,VRT_SET_REGISTER, PWR_CTL_EN,value,4); - msleep(PWR_SLEEP_INTERVAL); - } - - if( (dev->model == CX231XX_BOARD_CNXT_RDE_250) || - (dev->model == CX231XX_BOARD_CNXT_RDU_250)) { - - /* tuner path to channel 1 from port 3 */ - cx231xx_enable_i2c_for_tuner(dev, I2C_3); - - if(dev->cx231xx_reset_analog_tuner) - dev->cx231xx_reset_analog_tuner(dev); - } - break; - - case POLARIS_AVMODE_DIGITAL: - - if(!(tmp & PWR_TUNER_EN)) { - tmp |= (PWR_TUNER_EN); - value[0]=(u8)tmp; - value[1]=(u8)(tmp>>8); - value[2]=(u8)(tmp>>16); - value[3]=(u8)(tmp>>24); - status = cx231xx_write_ctrl_reg(dev,VRT_SET_REGISTER, PWR_CTL_EN,value,4); - msleep(PWR_SLEEP_INTERVAL); - } - if(!(tmp & PWR_AV_EN)) { - tmp |= PWR_AV_EN; - value[0]=(u8)tmp; - value[1]=(u8)(tmp>>8); - value[2]=(u8)(tmp>>16); - value[3]=(u8)(tmp>>24); - status = cx231xx_write_ctrl_reg(dev,VRT_SET_REGISTER, PWR_CTL_EN,value,4); - msleep(PWR_SLEEP_INTERVAL); - } - if(!(tmp & PWR_ISO_EN)) { - tmp |= PWR_ISO_EN; - value[0]=(u8)tmp; - value[1]=(u8)(tmp>>8); - value[2]=(u8)(tmp>>16); - value[3]=(u8)(tmp>>24); - status = cx231xx_write_ctrl_reg(dev,VRT_SET_REGISTER, PWR_CTL_EN,value,4); - msleep(PWR_SLEEP_INTERVAL); - } - - tmp |= POLARIS_AVMODE_DIGITAL|I2C_DEMOD_EN; - value[0]=(u8)tmp; - value[1]=(u8)(tmp>>8); - value[2]=(u8)(tmp>>16); - value[3]=(u8)(tmp>>24); - status = cx231xx_write_ctrl_reg(dev,VRT_SET_REGISTER, PWR_CTL_EN,value,4); - msleep(PWR_SLEEP_INTERVAL); - - if(!(tmp & PWR_DEMOD_EN)) { - tmp |= PWR_DEMOD_EN; - value[0]=(u8)tmp; - value[1]=(u8)(tmp>>8); - value[2]=(u8)(tmp>>16); - value[3]=(u8)(tmp>>24); - status = cx231xx_write_ctrl_reg(dev,VRT_SET_REGISTER, PWR_CTL_EN,value,4); - msleep(PWR_SLEEP_INTERVAL); - } - - if( (dev->model == CX231XX_BOARD_CNXT_RDE_250) || - (dev->model == CX231XX_BOARD_CNXT_RDU_250)) { - - /* tuner path to channel 1 from port 3 */ - cx231xx_enable_i2c_for_tuner(dev, I2C_3); - - if(dev->cx231xx_reset_analog_tuner) - dev->cx231xx_reset_analog_tuner(dev); - } - break; - - default: - break; - } - - msleep(PWR_SLEEP_INTERVAL); - - /* For power saving, only enable Pwr_resetout_n when digital TV is selected. */ - if(mode == POLARIS_AVMODE_DIGITAL) { - tmp |= PWR_RESETOUT_EN; - value[0]=(u8)tmp; - value[1]=(u8)(tmp>>8); - value[2]=(u8)(tmp>>16); - value[3]=(u8)(tmp>>24); - status = cx231xx_write_ctrl_reg(dev,VRT_SET_REGISTER, PWR_CTL_EN,value,4); - msleep(PWR_SLEEP_INTERVAL); - } - - /* update power control for colibri */ - status = cx231xx_colibri_update_power_control(dev, mode); - - /* update power control for flatiron */ - status = cx231xx_flatiron_update_power_control(dev, mode); - - status = cx231xx_read_ctrl_reg(dev,VRT_GET_REGISTER, PWR_CTL_EN, value, 4); - cx231xx_info(" The data of PWR_CTL_EN register 0x74=0x%0x,0x%0x,0x%0x,0x%0x\n",value[0],value[1],value[2],value[3]); - - return status; +{ + u8 value[4] = { 0, 0, 0, 0 }; + u32 tmp = 0; + int status = 0; + + if (dev->power_mode != mode) + dev->power_mode = mode; + else { + cx231xx_info(" setPowerMode::mode = %d, No Change req.\n", + mode); + return 0; + } + + cx231xx_info(" setPowerMode::mode = %d\n", mode); + + status = + cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, PWR_CTL_EN, value, 4); + if (status < 0) + return status; + + tmp = *((u32 *) value); + + switch (mode) { + case POLARIS_AVMODE_ENXTERNAL_AV: + + tmp &= (~PWR_MODE_MASK); + + tmp |= PWR_AV_EN; + value[0] = (u8) tmp; + value[1] = (u8) (tmp >> 8); + value[2] = (u8) (tmp >> 16); + value[3] = (u8) (tmp >> 24); + status = + cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, PWR_CTL_EN, + value, 4); + msleep(PWR_SLEEP_INTERVAL); + + tmp |= PWR_ISO_EN; + value[0] = (u8) tmp; + value[1] = (u8) (tmp >> 8); + value[2] = (u8) (tmp >> 16); + value[3] = (u8) (tmp >> 24); + status = + cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, PWR_CTL_EN, + value, 4); + msleep(PWR_SLEEP_INTERVAL); + + tmp |= POLARIS_AVMODE_ENXTERNAL_AV; + value[0] = (u8) tmp; + value[1] = (u8) (tmp >> 8); + value[2] = (u8) (tmp >> 16); + value[3] = (u8) (tmp >> 24); + status = + cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, PWR_CTL_EN, + value, 4); + + dev->xc_fw_load_done = 0; /* reset state of xceive tuner */ + break; + + case POLARIS_AVMODE_ANALOGT_TV: + + tmp &= (~PWR_DEMOD_EN); + tmp |= (I2C_DEMOD_EN); + value[0] = (u8) tmp; + value[1] = (u8) (tmp >> 8); + value[2] = (u8) (tmp >> 16); + value[3] = (u8) (tmp >> 24); + status = + cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, PWR_CTL_EN, + value, 4); + msleep(PWR_SLEEP_INTERVAL); + + if (!(tmp & PWR_TUNER_EN)) { + tmp |= (PWR_TUNER_EN); + value[0] = (u8) tmp; + value[1] = (u8) (tmp >> 8); + value[2] = (u8) (tmp >> 16); + value[3] = (u8) (tmp >> 24); + status = + cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, + PWR_CTL_EN, value, 4); + msleep(PWR_SLEEP_INTERVAL); + } + + if (!(tmp & PWR_AV_EN)) { + tmp |= PWR_AV_EN; + value[0] = (u8) tmp; + value[1] = (u8) (tmp >> 8); + value[2] = (u8) (tmp >> 16); + value[3] = (u8) (tmp >> 24); + status = + cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, + PWR_CTL_EN, value, 4); + msleep(PWR_SLEEP_INTERVAL); + } + if (!(tmp & PWR_ISO_EN)) { + tmp |= PWR_ISO_EN; + value[0] = (u8) tmp; + value[1] = (u8) (tmp >> 8); + value[2] = (u8) (tmp >> 16); + value[3] = (u8) (tmp >> 24); + status = + cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, + PWR_CTL_EN, value, 4); + msleep(PWR_SLEEP_INTERVAL); + } + + if (!(tmp & POLARIS_AVMODE_ANALOGT_TV)) { + tmp |= POLARIS_AVMODE_ANALOGT_TV; + value[0] = (u8) tmp; + value[1] = (u8) (tmp >> 8); + value[2] = (u8) (tmp >> 16); + value[3] = (u8) (tmp >> 24); + status = + cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, + PWR_CTL_EN, value, 4); + msleep(PWR_SLEEP_INTERVAL); + } + + if ((dev->model == CX231XX_BOARD_CNXT_RDE_250) || + (dev->model == CX231XX_BOARD_CNXT_RDU_250)) { + + /* tuner path to channel 1 from port 3 */ + cx231xx_enable_i2c_for_tuner(dev, I2C_3); + + if (dev->cx231xx_reset_analog_tuner) + dev->cx231xx_reset_analog_tuner(dev); + } + break; + + case POLARIS_AVMODE_DIGITAL: + + if (!(tmp & PWR_TUNER_EN)) { + tmp |= (PWR_TUNER_EN); + value[0] = (u8) tmp; + value[1] = (u8) (tmp >> 8); + value[2] = (u8) (tmp >> 16); + value[3] = (u8) (tmp >> 24); + status = + cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, + PWR_CTL_EN, value, 4); + msleep(PWR_SLEEP_INTERVAL); + } + if (!(tmp & PWR_AV_EN)) { + tmp |= PWR_AV_EN; + value[0] = (u8) tmp; + value[1] = (u8) (tmp >> 8); + value[2] = (u8) (tmp >> 16); + value[3] = (u8) (tmp >> 24); + status = + cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, + PWR_CTL_EN, value, 4); + msleep(PWR_SLEEP_INTERVAL); + } + if (!(tmp & PWR_ISO_EN)) { + tmp |= PWR_ISO_EN; + value[0] = (u8) tmp; + value[1] = (u8) (tmp >> 8); + value[2] = (u8) (tmp >> 16); + value[3] = (u8) (tmp >> 24); + status = + cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, + PWR_CTL_EN, value, 4); + msleep(PWR_SLEEP_INTERVAL); + } + + tmp |= POLARIS_AVMODE_DIGITAL | I2C_DEMOD_EN; + value[0] = (u8) tmp; + value[1] = (u8) (tmp >> 8); + value[2] = (u8) (tmp >> 16); + value[3] = (u8) (tmp >> 24); + status = + cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, PWR_CTL_EN, + value, 4); + msleep(PWR_SLEEP_INTERVAL); + + if (!(tmp & PWR_DEMOD_EN)) { + tmp |= PWR_DEMOD_EN; + value[0] = (u8) tmp; + value[1] = (u8) (tmp >> 8); + value[2] = (u8) (tmp >> 16); + value[3] = (u8) (tmp >> 24); + status = + cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, + PWR_CTL_EN, value, 4); + msleep(PWR_SLEEP_INTERVAL); + } + + if ((dev->model == CX231XX_BOARD_CNXT_RDE_250) || + (dev->model == CX231XX_BOARD_CNXT_RDU_250)) { + + /* tuner path to channel 1 from port 3 */ + cx231xx_enable_i2c_for_tuner(dev, I2C_3); + + if (dev->cx231xx_reset_analog_tuner) + dev->cx231xx_reset_analog_tuner(dev); + } + break; + + default: + break; + } + + msleep(PWR_SLEEP_INTERVAL); + + /* For power saving, only enable Pwr_resetout_n when digital TV is selected. */ + if (mode == POLARIS_AVMODE_DIGITAL) { + tmp |= PWR_RESETOUT_EN; + value[0] = (u8) tmp; + value[1] = (u8) (tmp >> 8); + value[2] = (u8) (tmp >> 16); + value[3] = (u8) (tmp >> 24); + status = + cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, PWR_CTL_EN, + value, 4); + msleep(PWR_SLEEP_INTERVAL); + } + + /* update power control for colibri */ + status = cx231xx_colibri_update_power_control(dev, mode); + + /* update power control for flatiron */ + status = cx231xx_flatiron_update_power_control(dev, mode); + + status = + cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, PWR_CTL_EN, value, 4); + cx231xx_info + (" The data of PWR_CTL_EN register 0x74=0x%0x,0x%0x,0x%0x,0x%0x\n", + value[0], value[1], value[2], value[3]); + + return status; } int cx231xx_power_suspend(struct cx231xx *dev) { - u8 value[4] ={0,0,0,0}; - u32 tmp = 0; - int status = 0; - - status = cx231xx_read_ctrl_reg(dev,VRT_GET_REGISTER, PWR_CTL_EN, value, 4); - if(status > 0) - return status; - - tmp = *((u32 *)value); - tmp &= (~PWR_MODE_MASK); - - value[0]=(u8)tmp; - value[1]=(u8)(tmp>>8); - value[2]=(u8)(tmp>>16); - value[3]=(u8)(tmp>>24); - status = cx231xx_write_ctrl_reg(dev,VRT_SET_REGISTER, PWR_CTL_EN,value,4); - - return status; -} + u8 value[4] = { 0, 0, 0, 0 }; + u32 tmp = 0; + int status = 0; + + status = + cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, PWR_CTL_EN, value, 4); + if (status > 0) + return status; + tmp = *((u32 *) value); + tmp &= (~PWR_MODE_MASK); + + value[0] = (u8) tmp; + value[1] = (u8) (tmp >> 8); + value[2] = (u8) (tmp >> 16); + value[3] = (u8) (tmp >> 24); + status = + cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, PWR_CTL_EN, value, 4); + + return status; +} /************************************************************************************* * S T R E A M C O N T R O L functions * *************************************************************************************/ int cx231xx_start_stream(struct cx231xx *dev, u32 ep_mask) { - u8 value[4] = {0x0, 0x0, 0x0, 0x0}; - u32 tmp =0; - int status = 0; - - cx231xx_info("cx231xx_start_stream():: ep_mask = %x\n", ep_mask); - status = cx231xx_read_ctrl_reg(dev,VRT_GET_REGISTER, EP_MODE_SET,value,4); - if(status < 0) - return status; - - tmp = *((u32 *)value); - tmp |= ep_mask; - value[0]=(u8) tmp; - value[1]=(u8)(tmp>>8); - value[2]=(u8)(tmp>>16); - value[3]=(u8)(tmp>>24); - - status = cx231xx_write_ctrl_reg(dev,VRT_SET_REGISTER, EP_MODE_SET,value,4); - - return status; + u8 value[4] = { 0x0, 0x0, 0x0, 0x0 }; + u32 tmp = 0; + int status = 0; + + cx231xx_info("cx231xx_start_stream():: ep_mask = %x\n", ep_mask); + status = + cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, EP_MODE_SET, value, 4); + if (status < 0) + return status; + + tmp = *((u32 *) value); + tmp |= ep_mask; + value[0] = (u8) tmp; + value[1] = (u8) (tmp >> 8); + value[2] = (u8) (tmp >> 16); + value[3] = (u8) (tmp >> 24); + + status = + cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, EP_MODE_SET, value, + 4); + + return status; } int cx231xx_stop_stream(struct cx231xx *dev, u32 ep_mask) -{ - u8 value[4] = {0x0, 0x0, 0x0, 0x0}; - u32 tmp =0; - int status = 0; - - cx231xx_info("cx231xx_stop_stream():: ep_mask = %x\n", ep_mask); - status = cx231xx_read_ctrl_reg(dev,VRT_GET_REGISTER, EP_MODE_SET,value,4); - if(status < 0) - return status; - - tmp = *((u32 *)value); - tmp&= (~ep_mask); - value[0]=(u8) tmp; - value[1]=(u8)(tmp>>8); - value[2]=(u8)(tmp>>16); - value[3]=(u8)(tmp>>24); - - status = cx231xx_write_ctrl_reg(dev,VRT_SET_REGISTER, EP_MODE_SET,value,4); - - return status; +{ + u8 value[4] = { 0x0, 0x0, 0x0, 0x0 }; + u32 tmp = 0; + int status = 0; + + cx231xx_info("cx231xx_stop_stream():: ep_mask = %x\n", ep_mask); + status = + cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, EP_MODE_SET, value, 4); + if (status < 0) + return status; + + tmp = *((u32 *) value); + tmp &= (~ep_mask); + value[0] = (u8) tmp; + value[1] = (u8) (tmp >> 8); + value[2] = (u8) (tmp >> 16); + value[3] = (u8) (tmp >> 24); + + status = + cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, EP_MODE_SET, value, + 4); + + return status; } int cx231xx_initialize_stream_xfer(struct cx231xx *dev, u32 media_type) { - int status = 0; - - if(dev->udev->speed == USB_SPEED_HIGH) - { - switch(media_type) - { - case 81: /* audio */ - cx231xx_info("%s: Audio enter HANC\n",__func__); - status = cx231xx_mode_register(dev, TS_MODE_REG, 0x9300); - break; - - case 2: /* vbi */ - cx231xx_info("%s: set vanc registers\n",__func__); - status = cx231xx_mode_register(dev, TS_MODE_REG, 0x300); - break; - - case 3: /* sliced cc */ - cx231xx_info("%s: set hanc registers\n",__func__); - status = cx231xx_mode_register(dev, TS_MODE_REG, 0x1300); - break; - - case 0: /* video */ - cx231xx_info("%s: set video registers\n",__func__); - status = cx231xx_mode_register(dev, TS_MODE_REG, 0x100); - break; - - case 4: /* ts1 */ - cx231xx_info("%s: set ts1 registers\n",__func__); - status = cx231xx_mode_register(dev, TS_MODE_REG, 0x101); - status = cx231xx_mode_register(dev, TS1_CFG_REG, 0x400); - break; - case 6: /* ts1 parallel mode */ - cx231xx_info("%s: set ts1 parrallel mode registers\n",__func__); - status = cx231xx_mode_register(dev, TS_MODE_REG, 0x100); - status = cx231xx_mode_register(dev, TS1_CFG_REG, 0x400); - break; - } - } - else - { - status = cx231xx_mode_register(dev, TS_MODE_REG, 0x101); - } - - return status; -} - + int status = 0; + if (dev->udev->speed == USB_SPEED_HIGH) { + switch (media_type) { + case 81: /* audio */ + cx231xx_info("%s: Audio enter HANC\n", __func__); + status = + cx231xx_mode_register(dev, TS_MODE_REG, 0x9300); + break; + + case 2: /* vbi */ + cx231xx_info("%s: set vanc registers\n", __func__); + status = cx231xx_mode_register(dev, TS_MODE_REG, 0x300); + break; + + case 3: /* sliced cc */ + cx231xx_info("%s: set hanc registers\n", __func__); + status = + cx231xx_mode_register(dev, TS_MODE_REG, 0x1300); + break; + + case 0: /* video */ + cx231xx_info("%s: set video registers\n", __func__); + status = cx231xx_mode_register(dev, TS_MODE_REG, 0x100); + break; + + case 4: /* ts1 */ + cx231xx_info("%s: set ts1 registers\n", __func__); + status = cx231xx_mode_register(dev, TS_MODE_REG, 0x101); + status = cx231xx_mode_register(dev, TS1_CFG_REG, 0x400); + break; + case 6: /* ts1 parallel mode */ + cx231xx_info("%s: set ts1 parrallel mode registers\n", + __func__); + status = cx231xx_mode_register(dev, TS_MODE_REG, 0x100); + status = cx231xx_mode_register(dev, TS1_CFG_REG, 0x400); + break; + } + } else { + status = cx231xx_mode_register(dev, TS_MODE_REG, 0x101); + } + return status; +} int cx231xx_capture_start(struct cx231xx *dev, int start, u8 media_type) { int rc; - u32 ep_mask = -1; - PPCB_CONFIG pcb_config; - - /* get EP for media type */ - pcb_config = &dev->current_pcb_config; - - if(pcb_config->config_num==1) - { - switch (media_type) - { - case 0: /* Video */ - ep_mask =ENABLE_EP4; /* ep4 [00:1000] */ - break; - case 1: /* Audio */ - ep_mask =ENABLE_EP3; /* ep3 [00:0100] */ - break; - case 2: /* Vbi */ - ep_mask = ENABLE_EP5; /* ep5 [01:0000] */ - break; - case 3: /* Sliced_cc */ - ep_mask = ENABLE_EP6; /* ep6 [10:0000] */ - break; - case 4: /* ts1 */ - case 6: /* ts1 parallel mode */ - ep_mask = ENABLE_EP1; /* ep1 [00:0001] */ - break; - case 5: /* ts2 */ - ep_mask = ENABLE_EP2; /* ep2 [00:0010] */ - break; - } - - } - else if(pcb_config->config_num>1) - { - switch (media_type) - { - case 0: /* Video */ - ep_mask = ENABLE_EP4; /* ep4 [00:1000] */ - break; - case 1: /* Audio */ - ep_mask = ENABLE_EP3; /* ep3 [00:0100] */ - break; - case 2: /* Vbi */ - ep_mask = ENABLE_EP5; /* ep5 [01:0000] */ - break; - case 3: /* Sliced_cc */ - ep_mask = ENABLE_EP6; /* ep6 [10:0000] */ - break; - case 4: /* ts1 */ - case 6: /* ts1 parallel mode */ - ep_mask = ENABLE_EP1; /* ep1 [00:0001] */ - break; - case 5: /* ts2 */ - ep_mask = ENABLE_EP2; /* ep2 [00:0010] */ - break; - } - - } - - if(start) { - rc = cx231xx_initialize_stream_xfer(dev, media_type); - - if(rc < 0) { - return rc; - } - - /* enable video capture */ - if(ep_mask > 0 ) - rc = cx231xx_start_stream(dev, ep_mask); - } - else { - /* disable video capture */ - if(ep_mask > 0 ) - rc = cx231xx_stop_stream(dev, ep_mask); - } - - if (dev->mode == CX231XX_ANALOG_MODE){ - /* do any in Analog mode */ - } - else { - /* do any in digital mode */ - } + u32 ep_mask = -1; + PPCB_CONFIG pcb_config; + + /* get EP for media type */ + pcb_config = &dev->current_pcb_config; + + if (pcb_config->config_num == 1) { + switch (media_type) { + case 0: /* Video */ + ep_mask = ENABLE_EP4; /* ep4 [00:1000] */ + break; + case 1: /* Audio */ + ep_mask = ENABLE_EP3; /* ep3 [00:0100] */ + break; + case 2: /* Vbi */ + ep_mask = ENABLE_EP5; /* ep5 [01:0000] */ + break; + case 3: /* Sliced_cc */ + ep_mask = ENABLE_EP6; /* ep6 [10:0000] */ + break; + case 4: /* ts1 */ + case 6: /* ts1 parallel mode */ + ep_mask = ENABLE_EP1; /* ep1 [00:0001] */ + break; + case 5: /* ts2 */ + ep_mask = ENABLE_EP2; /* ep2 [00:0010] */ + break; + } + + } else if (pcb_config->config_num > 1) { + switch (media_type) { + case 0: /* Video */ + ep_mask = ENABLE_EP4; /* ep4 [00:1000] */ + break; + case 1: /* Audio */ + ep_mask = ENABLE_EP3; /* ep3 [00:0100] */ + break; + case 2: /* Vbi */ + ep_mask = ENABLE_EP5; /* ep5 [01:0000] */ + break; + case 3: /* Sliced_cc */ + ep_mask = ENABLE_EP6; /* ep6 [10:0000] */ + break; + case 4: /* ts1 */ + case 6: /* ts1 parallel mode */ + ep_mask = ENABLE_EP1; /* ep1 [00:0001] */ + break; + case 5: /* ts2 */ + ep_mask = ENABLE_EP2; /* ep2 [00:0010] */ + break; + } + + } + + if (start) { + rc = cx231xx_initialize_stream_xfer(dev, media_type); + + if (rc < 0) { + return rc; + } + + /* enable video capture */ + if (ep_mask > 0) + rc = cx231xx_start_stream(dev, ep_mask); + } else { + /* disable video capture */ + if (ep_mask > 0) + rc = cx231xx_stop_stream(dev, ep_mask); + } + + if (dev->mode == CX231XX_ANALOG_MODE) { + /* do any in Analog mode */ + } else { + /* do any in digital mode */ + } return rc; } -EXPORT_SYMBOL_GPL(cx231xx_capture_start); +EXPORT_SYMBOL_GPL(cx231xx_capture_start); /************************************************************************************ * G P I O B I T control functions * *************************************************************************************/ -int cx231xx_set_gpio_bit(struct cx231xx *dev, u32 gpio_bit, u8* gpio_val) +int cx231xx_set_gpio_bit(struct cx231xx *dev, u32 gpio_bit, u8 * gpio_val) { - int status = 0; + int status = 0; - status = cx231xx_send_gpio_cmd(dev, gpio_bit, gpio_val, 4, 0, 0); + status = cx231xx_send_gpio_cmd(dev, gpio_bit, gpio_val, 4, 0, 0); - return status; + return status; } -int cx231xx_get_gpio_bit(struct cx231xx *dev, u32 gpio_bit, u8* gpio_val) +int cx231xx_get_gpio_bit(struct cx231xx *dev, u32 gpio_bit, u8 * gpio_val) { - int status = 0; + int status = 0; - status = cx231xx_send_gpio_cmd(dev, gpio_bit, gpio_val, 4, 0, 1); + status = cx231xx_send_gpio_cmd(dev, gpio_bit, gpio_val, 4, 0, 1); - return status; + return status; } /* @@ -1873,32 +2615,30 @@ int cx231xx_get_gpio_bit(struct cx231xx *dev, u32 gpio_bit, u8* gpio_val) * 1 = Output direction */ int cx231xx_set_gpio_direction(struct cx231xx *dev, - int pin_number, - int pin_value) + int pin_number, int pin_value) { int status = 0; - u32 value = 0; + u32 value = 0; - /* Check for valid pin_number - if 32 , bail out */ - if (pin_number >= 32) { - return -EINVAL; - } + /* Check for valid pin_number - if 32 , bail out */ + if (pin_number >= 32) { + return -EINVAL; + } - if (pin_value == 0) { /* input */ - value = dev->gpio_dir &(~(1<gpio_dir | (1<gpio_dir & (~(1 << pin_number)); /* clear */ + } else { + value = dev->gpio_dir | (1 << pin_number); + } - status = cx231xx_set_gpio_bit(dev, value, (u8*) & dev->gpio_val); + status = cx231xx_set_gpio_bit(dev, value, (u8 *) & dev->gpio_val); - /* cache the value for future */ + /* cache the value for future */ dev->gpio_dir = value; - return status; + return status; } - /* * SetGpioPinLogicValue * Sets the value of the GPIO pin to Logic high or low. The Pin under @@ -1910,42 +2650,41 @@ int cx231xx_set_gpio_direction(struct cx231xx *dev, * 0 = set it to 0 * 1 = set it to 1 */ -int cx231xx_set_gpio_value(struct cx231xx *dev, - int pin_number, - int pin_value) +int cx231xx_set_gpio_value(struct cx231xx *dev, int pin_number, int pin_value) { - int status = 0; - u32 value = 0; - - /* Check for valid pin_number - if 0xFF , bail out */ - if (pin_number >= 32) - return -EINVAL; - - /* first do a sanity check - if the Pin is not output, make it output */ - if ((dev->gpio_dir & (1<gpio_dir | (1<gpio_dir = value; - status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8*) &dev->gpio_val); - value = 0; - } - - if (pin_value == 0) { - value = dev->gpio_val & (~(1<gpio_val | (1<gpio_val=value; - - /* toggle bit0 of GP_IO */ - status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8*) &dev->gpio_val); - - return status; -} + int status = 0; + u32 value = 0; + + /* Check for valid pin_number - if 0xFF , bail out */ + if (pin_number >= 32) + return -EINVAL; + + /* first do a sanity check - if the Pin is not output, make it output */ + if ((dev->gpio_dir & (1 << pin_number)) == 0x00) { + /* It was in input mode */ + value = dev->gpio_dir | (1 << pin_number); + dev->gpio_dir = value; + status = + cx231xx_set_gpio_bit(dev, dev->gpio_dir, + (u8 *) & dev->gpio_val); + value = 0; + } + if (pin_value == 0) { + value = dev->gpio_val & (~(1 << pin_number)); + } else { + value = dev->gpio_val | (1 << pin_number); + } + + /* store the value */ + dev->gpio_val = value; + + /* toggle bit0 of GP_IO */ + status = + cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *) & dev->gpio_val); + + return status; +} /************************************************************************************ * G P I O I2C related functions * @@ -1955,288 +2694,324 @@ int cx231xx_gpio_i2c_start(struct cx231xx *dev) int status = 0; /* set SCL to output 1 ; set SDA to output 1 */ - dev->gpio_dir |= 1<< dev->board.tuner_scl_gpio; - dev->gpio_dir |= 1<board.tuner_sda_gpio; - dev->gpio_val |= 1<board.tuner_scl_gpio; - dev->gpio_val |= 1<board.tuner_sda_gpio; - - status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8*) &dev->gpio_val); - if(status < 0){ + dev->gpio_dir |= 1 << dev->board.tuner_scl_gpio; + dev->gpio_dir |= 1 << dev->board.tuner_sda_gpio; + dev->gpio_val |= 1 << dev->board.tuner_scl_gpio; + dev->gpio_val |= 1 << dev->board.tuner_sda_gpio; + + status = + cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *) & dev->gpio_val); + if (status < 0) { return -EINVAL; } /* set SCL to output 1; set SDA to output 0 */ - dev->gpio_val |= 1<board.tuner_scl_gpio; - dev->gpio_val &= ~(1<board.tuner_sda_gpio); - - status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8*) &dev->gpio_val); - if(status < 0){ + dev->gpio_val |= 1 << dev->board.tuner_scl_gpio; + dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio); + + status = + cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *) & dev->gpio_val); + if (status < 0) { return -EINVAL; } - /* set SCL to output 0; set SDA to output 0 */ - dev->gpio_val &= ~(1<board.tuner_scl_gpio); - dev->gpio_val &= ~(1<board.tuner_sda_gpio); - - status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8*) &dev->gpio_val); - if(status < 0){ + /* set SCL to output 0; set SDA to output 0 */ + dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio); + dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio); + + status = + cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *) & dev->gpio_val); + if (status < 0) { return -EINVAL; } - + return status; } - int cx231xx_gpio_i2c_end(struct cx231xx *dev) { - int status = 0; - - /* set SCL to output 0; set SDA to output 0 */ - dev->gpio_dir |= 1<board.tuner_scl_gpio; - dev->gpio_dir |= 1<board.tuner_sda_gpio; - - dev->gpio_val &= ~(1<board.tuner_scl_gpio); - dev->gpio_val &= ~(1<board.tuner_sda_gpio); - - status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8*) &dev->gpio_val); - if(status < 0){ + int status = 0; + + /* set SCL to output 0; set SDA to output 0 */ + dev->gpio_dir |= 1 << dev->board.tuner_scl_gpio; + dev->gpio_dir |= 1 << dev->board.tuner_sda_gpio; + + dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio); + dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio); + + status = + cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *) & dev->gpio_val); + if (status < 0) { return -EINVAL; } - /* set SCL to output 1; set SDA to output 0 */ - dev->gpio_val |= 1<board.tuner_scl_gpio; - dev->gpio_val &= ~(1<board.tuner_sda_gpio); - - status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8*) &dev->gpio_val); - if(status < 0){ + /* set SCL to output 1; set SDA to output 0 */ + dev->gpio_val |= 1 << dev->board.tuner_scl_gpio; + dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio); + + status = + cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *) & dev->gpio_val); + if (status < 0) { return -EINVAL; } - - /* set SCL to input ,release SCL cable control + + /* set SCL to input ,release SCL cable control set SDA to input ,release SDA cable control */ - dev->gpio_dir &= ~(1<board.tuner_scl_gpio); - dev->gpio_dir &= ~(1<board.tuner_sda_gpio); - - status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8*) &dev->gpio_val); - if(status < 0){ + dev->gpio_dir &= ~(1 << dev->board.tuner_scl_gpio); + dev->gpio_dir &= ~(1 << dev->board.tuner_sda_gpio); + + status = + cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *) & dev->gpio_val); + if (status < 0) { return -EINVAL; } - return status; + return status; } - int cx231xx_gpio_i2c_write_byte(struct cx231xx *dev, u8 data) { - int status = 0; - u8 i; + int status = 0; + u8 i; /* set SCL to output ; set SDA to output */ - dev->gpio_dir |= 1<board.tuner_scl_gpio; - dev->gpio_dir |= 1<board.tuner_sda_gpio; - - for(i = 0;i<8;i++) { - if(((data<gpio_val &= ~(1<board.tuner_scl_gpio); - dev->gpio_val &= ~(1<board.tuner_sda_gpio); - status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8*) &dev->gpio_val); - - /* set SCL to output 1; set SDA to output 0 */ - dev->gpio_val |= 1<board.tuner_scl_gpio; - status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8*) &dev->gpio_val); - - /* set SCL to output 0; set SDA to output 0 */ - dev->gpio_val &= ~(1<board.tuner_scl_gpio); - status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8*) &dev->gpio_val); + dev->gpio_dir |= 1 << dev->board.tuner_scl_gpio; + dev->gpio_dir |= 1 << dev->board.tuner_sda_gpio; + + for (i = 0; i < 8; i++) { + if (((data << i) & 0x80) == 0) { + /* set SCL to output 0; set SDA to output 0 */ + dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio); + dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio); + status = + cx231xx_set_gpio_bit(dev, dev->gpio_dir, + (u8 *) & dev->gpio_val); + + /* set SCL to output 1; set SDA to output 0 */ + dev->gpio_val |= 1 << dev->board.tuner_scl_gpio; + status = + cx231xx_set_gpio_bit(dev, dev->gpio_dir, + (u8 *) & dev->gpio_val); + + /* set SCL to output 0; set SDA to output 0 */ + dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio); + status = + cx231xx_set_gpio_bit(dev, dev->gpio_dir, + (u8 *) & dev->gpio_val); } else { - /* set SCL to output 0; set SDA to output 1 */ - dev->gpio_val &= ~(1<board.tuner_scl_gpio); - dev->gpio_val |= 1<board.tuner_sda_gpio; - status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8*) &dev->gpio_val); - - /* set SCL to output 1; set SDA to output 1 */ - dev->gpio_val |= 1<board.tuner_scl_gpio; - status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8*) &dev->gpio_val); - - /* set SCL to output 0; set SDA to output 1 */ - dev->gpio_val &= ~(1<board.tuner_scl_gpio); - status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8*) &dev->gpio_val); - } + /* set SCL to output 0; set SDA to output 1 */ + dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio); + dev->gpio_val |= 1 << dev->board.tuner_sda_gpio; + status = + cx231xx_set_gpio_bit(dev, dev->gpio_dir, + (u8 *) & dev->gpio_val); + + /* set SCL to output 1; set SDA to output 1 */ + dev->gpio_val |= 1 << dev->board.tuner_scl_gpio; + status = + cx231xx_set_gpio_bit(dev, dev->gpio_dir, + (u8 *) & dev->gpio_val); + + /* set SCL to output 0; set SDA to output 1 */ + dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio); + status = + cx231xx_set_gpio_bit(dev, dev->gpio_dir, + (u8 *) & dev->gpio_val); + } } return status; } -int cx231xx_gpio_i2c_read_byte(struct cx231xx *dev, u8 *buf) +int cx231xx_gpio_i2c_read_byte(struct cx231xx *dev, u8 * buf) { u8 value = 0; - int status = 0; - u32 gpio_logic_value =0; - u8 i; + int status = 0; + u32 gpio_logic_value = 0; + u8 i; /* read byte */ - for(i=0;i<8;i++) { /* send write I2c addr */ + for (i = 0; i < 8; i++) { /* send write I2c addr */ /* set SCL to output 0; set SDA to input */ - dev->gpio_val &= ~(1<board.tuner_scl_gpio); - status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8*) &dev->gpio_val); - + dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio); + status = + cx231xx_set_gpio_bit(dev, dev->gpio_dir, + (u8 *) & dev->gpio_val); + /* set SCL to output 1; set SDA to input */ - dev->gpio_val |= 1<board.tuner_scl_gpio; - status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8*) &dev->gpio_val); - + dev->gpio_val |= 1 << dev->board.tuner_scl_gpio; + status = + cx231xx_set_gpio_bit(dev, dev->gpio_dir, + (u8 *) & dev->gpio_val); + /* get SDA data bit */ gpio_logic_value = dev->gpio_val; - status = cx231xx_get_gpio_bit(dev, dev->gpio_dir, (u8*) &dev->gpio_val); - if((dev->gpio_val & (1<board.tuner_sda_gpio)) != 0) { - value |= (1<<(8-i-1)); + status = + cx231xx_get_gpio_bit(dev, dev->gpio_dir, + (u8 *) & dev->gpio_val); + if ((dev->gpio_val & (1 << dev->board.tuner_sda_gpio)) != 0) { + value |= (1 << (8 - i - 1)); } - - dev->gpio_val = gpio_logic_value; + + dev->gpio_val = gpio_logic_value; } /* set SCL to output 0,finish the read latest SCL signal. !!!set SDA to input,never to modify SDA direction at the same times */ - dev->gpio_val &= ~(1<board.tuner_scl_gpio); - status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8*) &dev->gpio_val); - - /* store the value */ - *buf = value & 0xff; - + dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio); + status = + cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *) & dev->gpio_val); + + /* store the value */ + *buf = value & 0xff; + return status; } int cx231xx_gpio_i2c_read_ack(struct cx231xx *dev) { - int status = 0; + int status = 0; u32 gpio_logic_value = 0; - int nCnt=10; - int nInit=nCnt; + int nCnt = 10; + int nInit = nCnt; /* clock stretch; set SCL to input; set SDA to input; get SCL value till SCL = 1 */ - dev->gpio_dir &= ~(1<board.tuner_sda_gpio); - dev->gpio_dir &= ~(1<board.tuner_scl_gpio); + dev->gpio_dir &= ~(1 << dev->board.tuner_sda_gpio); + dev->gpio_dir &= ~(1 << dev->board.tuner_scl_gpio); gpio_logic_value = dev->gpio_val; - status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8*) &dev->gpio_val); - - do{ + status = + cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *) & dev->gpio_val); + + do { msleep(2); - status = cx231xx_get_gpio_bit(dev, dev->gpio_dir, (u8*) &dev->gpio_val); - nCnt--; - }while(((dev->gpio_val & (1<board.tuner_scl_gpio)) == 0) && (nCnt>0)); - - if(nCnt==0) { - cx231xx_info("No ACK after %d msec for clock stretch. GPIO I2C operation failed!",nInit*10); - } - + status = + cx231xx_get_gpio_bit(dev, dev->gpio_dir, + (u8 *) & dev->gpio_val); + nCnt--; + } while (((dev->gpio_val & (1 << dev->board.tuner_scl_gpio)) == 0) + && (nCnt > 0)); + + if (nCnt == 0) { + cx231xx_info + ("No ACK after %d msec for clock stretch. GPIO I2C operation failed!", + nInit * 10); + } + /* readAck throuth clock stretch ,slave has given a SCL signal,so the SDA data can be directly read. */ - status = cx231xx_get_gpio_bit(dev, dev->gpio_dir, (u8*) &dev->gpio_val); - - if((dev->gpio_val & 1<< dev->board.tuner_sda_gpio) == 0){ + status = + cx231xx_get_gpio_bit(dev, dev->gpio_dir, (u8 *) & dev->gpio_val); + + if ((dev->gpio_val & 1 << dev->board.tuner_sda_gpio) == 0) { dev->gpio_val = gpio_logic_value; - dev->gpio_val &= ~(1<< dev->board.tuner_sda_gpio); + dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio); status = 0; } else { dev->gpio_val = gpio_logic_value; - dev->gpio_val |= (1<< dev->board.tuner_sda_gpio); + dev->gpio_val |= (1 << dev->board.tuner_sda_gpio); } /* read SDA end, set the SCL to output 0, after this operation, SDA direction can be changed. */ dev->gpio_val = gpio_logic_value; - dev->gpio_dir |= (1<board.tuner_scl_gpio); - dev->gpio_val &= ~(1<board.tuner_scl_gpio); - status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8*) &dev->gpio_val); - + dev->gpio_dir |= (1 << dev->board.tuner_scl_gpio); + dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio); + status = + cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *) & dev->gpio_val); + return status; } - int cx231xx_gpio_i2c_write_ack(struct cx231xx *dev) { - int status = 0; - + int status = 0; + /* set SDA to ouput */ - dev->gpio_dir |= 1<board.tuner_sda_gpio; - status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8*) &dev->gpio_val); - + dev->gpio_dir |= 1 << dev->board.tuner_sda_gpio; + status = + cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *) & dev->gpio_val); + /* set SCL = 0 (output); set SDA = 0 (output) */ - dev->gpio_val &= ~(1<board.tuner_sda_gpio); - dev->gpio_val &= ~(1<board.tuner_scl_gpio); - status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8*) &dev->gpio_val); - + dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio); + dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio); + status = + cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *) & dev->gpio_val); + /* set SCL = 1 (output); set SDA = 0 (output) */ - dev->gpio_val |= 1<board.tuner_scl_gpio; - status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8*) &dev->gpio_val); - + dev->gpio_val |= 1 << dev->board.tuner_scl_gpio; + status = + cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *) & dev->gpio_val); + /* set SCL = 0 (output); set SDA = 0 (output) */ - dev->gpio_val &= ~(1<board.tuner_scl_gpio); - status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8*) &dev->gpio_val); - + dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio); + status = + cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *) & dev->gpio_val); + /* set SDA to input,and then the slave will read data from SDA. */ - dev->gpio_dir &= ~(1<board.tuner_sda_gpio); - status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8*) &dev->gpio_val); - - return status; + dev->gpio_dir &= ~(1 << dev->board.tuner_sda_gpio); + status = + cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *) & dev->gpio_val); + + return status; } int cx231xx_gpio_i2c_write_nak(struct cx231xx *dev) { - int status = 0; - + int status = 0; + /* set scl to output ; set sda to input */ - dev->gpio_dir |= 1<board.tuner_scl_gpio; - dev->gpio_dir &= ~(1<board.tuner_sda_gpio); - status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8*) &dev->gpio_val); - + dev->gpio_dir |= 1 << dev->board.tuner_scl_gpio; + dev->gpio_dir &= ~(1 << dev->board.tuner_sda_gpio); + status = + cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *) & dev->gpio_val); + /* set scl to output 0; set sda to input */ - dev->gpio_val &= ~(1<board.tuner_scl_gpio); - status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8*) &dev->gpio_val); - + dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio); + status = + cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *) & dev->gpio_val); + /* set scl to output 1; set sda to input */ - dev->gpio_val |= 1<board.tuner_scl_gpio; - status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8*) &dev->gpio_val); + dev->gpio_val |= 1 << dev->board.tuner_scl_gpio; + status = + cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *) & dev->gpio_val); - return status; + return status; } - - /************************************************************************************ * G P I O I2C related functions * *************************************************************************************/ /* cx231xx_gpio_i2c_read - * Function to read data from gpio based I2C interface + * Function to read data from gpio based I2C interface */ -int cx231xx_gpio_i2c_read(struct cx231xx *dev, u8 dev_addr, u8 *buf ,u8 len) +int cx231xx_gpio_i2c_read(struct cx231xx *dev, u8 dev_addr, u8 * buf, u8 len) { - int status = 0; - int i = 0; + int status = 0; + int i = 0; - /* get the lock */ + /* get the lock */ mutex_lock(&dev->gpio_i2c_lock); - + /* start */ status = cx231xx_gpio_i2c_start(dev); - + /* write dev_addr */ - status = cx231xx_gpio_i2c_write_byte(dev, (dev_addr << 1) +1); - + status = cx231xx_gpio_i2c_write_byte(dev, (dev_addr << 1) + 1); + /* readAck */ status = cx231xx_gpio_i2c_read_ack(dev); - /* read data */ - for(i = 0; i < len; i++ ) { - /* read data */ - buf[i] = 0; - status = cx231xx_gpio_i2c_read_byte(dev, & buf[i]); - - if( (i+1) != len) { - /* only do write ack if we more length */ - status = cx231xx_gpio_i2c_write_ack(dev); - } - } - + /* read data */ + for (i = 0; i < len; i++) { + /* read data */ + buf[i] = 0; + status = cx231xx_gpio_i2c_read_byte(dev, &buf[i]); + + if ((i + 1) != len) { + /* only do write ack if we more length */ + status = cx231xx_gpio_i2c_write_ack(dev); + } + } + /* write NAK - inform reads are complete */ status = cx231xx_gpio_i2c_write_nak(dev); @@ -2245,45 +3020,43 @@ int cx231xx_gpio_i2c_read(struct cx231xx *dev, u8 dev_addr, u8 *buf ,u8 len) /* release the lock */ mutex_unlock(&dev->gpio_i2c_lock); - + return status; } - /* cx231xx_gpio_i2c_write - * Function to write data to gpio based I2C interface + * Function to write data to gpio based I2C interface */ -int cx231xx_gpio_i2c_write(struct cx231xx *dev, u8 dev_addr, u8 *buf ,u8 len) +int cx231xx_gpio_i2c_write(struct cx231xx *dev, u8 dev_addr, u8 * buf, u8 len) { - int status = 0; - int i=0; - + int status = 0; + int i = 0; + /* get the lock */ mutex_lock(&dev->gpio_i2c_lock); /* start */ status = cx231xx_gpio_i2c_start(dev); - + /* write dev_addr */ status = cx231xx_gpio_i2c_write_byte(dev, dev_addr << 1); - + /* read Ack */ - status = cx231xx_gpio_i2c_read_ack(dev); + status = cx231xx_gpio_i2c_read_ack(dev); - for(i = 0; i < len; i++ ) { - /* Write data */ - status = cx231xx_gpio_i2c_write_byte(dev, buf[i]); + for (i = 0; i < len; i++) { + /* Write data */ + status = cx231xx_gpio_i2c_write_byte(dev, buf[i]); - /* read Ack */ - status = cx231xx_gpio_i2c_read_ack(dev); - } + /* read Ack */ + status = cx231xx_gpio_i2c_read_ack(dev); + } - /* write End */ + /* write End */ status = cx231xx_gpio_i2c_end(dev); /* release the lock */ mutex_unlock(&dev->gpio_i2c_lock); - + return 0; } - -- cgit v1.2.3 From 1e59b30169044ec05336c5df466b489b4f98c587 Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Tue, 3 Mar 2009 13:31:36 -0300 Subject: cx231xx: First series of manual CodingStyle fixes From: Mauro Carvalho Chehab This patch cleans up CodingStyle on the following source files: There are still much more to be fixed on later patches Signed-off-by: Mauro Carvalho Chehab --- linux/drivers/media/video/cx231xx/cx231xx-avcore.c | 2104 +++++++++----------- 1 file changed, 888 insertions(+), 1216 deletions(-) (limited to 'linux/drivers/media/video/cx231xx/cx231xx-avcore.c') diff --git a/linux/drivers/media/video/cx231xx/cx231xx-avcore.c b/linux/drivers/media/video/cx231xx/cx231xx-avcore.c index 3c09b9473..6eb63d078 100644 --- a/linux/drivers/media/video/cx231xx/cx231xx-avcore.c +++ b/linux/drivers/media/video/cx231xx/cx231xx-avcore.c @@ -1,5 +1,6 @@ /* - cx231xx_avcore.c - driver for Conexant Cx23100/101/102 USB video capture devices + cx231xx_avcore.c - driver for Conexant Cx23100/101/102 + USB video capture devices Copyright (C) 2008 @@ -38,9 +39,9 @@ #include "cx231xx.h" -/************************************************************************************* - * C O L I B R I - B L O C K C O N T R O L functions * - *************************************************************************************/ +/****************************************************************************** + * C O L I B R I - B L O C K C O N T R O L functions * + ********************************************************************* ********/ int cx231xx_colibri_init_super_block(struct cx231xx *dev, u32 ref_count) { int status = 0; @@ -50,42 +51,35 @@ int cx231xx_colibri_init_super_block(struct cx231xx *dev, u32 ref_count) /* super block initialize */ temp = (u8) (ref_count & 0xff); - status = - cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, SUP_BLK_TUNE2, - 2, temp, 1); + status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, + SUP_BLK_TUNE2, 2, temp, 1); - status = - cx231xx_read_i2c_data(dev, Colibri_DEVICE_ADDRESS, SUP_BLK_TUNE2, 2, - &colibri_power_status, 1); + status = cx231xx_read_i2c_data(dev, Colibri_DEVICE_ADDRESS, + SUP_BLK_TUNE2, 2, + &colibri_power_status, 1); temp = (u8) ((ref_count & 0x300) >> 8); temp |= 0x40; - status = - cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, SUP_BLK_TUNE1, - 2, temp, 1); - status = - cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, SUP_BLK_PLL2, 2, - 0x0f, 1); + status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, + SUP_BLK_TUNE1, 2, temp, 1); + status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, + SUP_BLK_PLL2, 2, 0x0f, 1); /* enable pll */ while (colibri_power_status != 0x18) { - status = - cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, - SUP_BLK_PWRDN, 2, 0x18, 1); - status = - cx231xx_read_i2c_data(dev, Colibri_DEVICE_ADDRESS, - SUP_BLK_PWRDN, 2, - &colibri_power_status, 1); + status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, + SUP_BLK_PWRDN, 2, 0x18, 1); + status = cx231xx_read_i2c_data(dev, Colibri_DEVICE_ADDRESS, + SUP_BLK_PWRDN, 2, + &colibri_power_status, 1); colibri_power_status &= 0xff; if (status < 0) { - cx231xx_info - (": Init Super Block failed in sending/receiving cmds\n"); + cx231xx_info(": Init Super Block failed in sending/receiving cmds\n"); break; } i++; if (i == 10) { - cx231xx_info - (": Init Super Block force break in loop !!!!\n"); + cx231xx_info(": Init Super Block force break in loop !!!!\n"); status = -1; break; } @@ -95,9 +89,8 @@ int cx231xx_colibri_init_super_block(struct cx231xx *dev, u32 ref_count) return status; /* start tuning filter */ - status = - cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, SUP_BLK_TUNE3, - 2, 0x40, 1); + status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, + SUP_BLK_TUNE3, 2, 0x40, 1); msleep(5); /* exit tuning */ @@ -113,86 +106,64 @@ int cx231xx_colibri_init_channels(struct cx231xx *dev) int status = 0; /* power up all 3 channels, clear pd_buffer */ - status = - cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, + status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, ADC_PWRDN_CLAMP_CH1, 2, 0x00, 1); - status = - cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, + status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, ADC_PWRDN_CLAMP_CH2, 2, 0x00, 1); - status = - cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, + status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, ADC_PWRDN_CLAMP_CH3, 2, 0x00, 1); /* Enable quantizer calibration */ - status = - cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, ADC_COM_QUANT, - 2, 0x02, 1); + status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, + ADC_COM_QUANT, 2, 0x02, 1); /* channel initialize, force modulator (fb) reset */ - status = - cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, + status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, ADC_FB_FRCRST_CH1, 2, 0x17, 1); - status = - cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, + status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, ADC_FB_FRCRST_CH2, 2, 0x17, 1); - status = - cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, + status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, ADC_FB_FRCRST_CH3, 2, 0x17, 1); /* start quantilizer calibration */ - status = - cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, + status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, ADC_CAL_ATEST_CH1, 2, 0x10, 1); - status = - cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, + status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, ADC_CAL_ATEST_CH2, 2, 0x10, 1); - status = - cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, + status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, ADC_CAL_ATEST_CH3, 2, 0x10, 1); msleep(5); /* exit modulator (fb) reset */ - status = - cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, + status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, ADC_FB_FRCRST_CH1, 2, 0x07, 1); - status = - cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, + status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, ADC_FB_FRCRST_CH2, 2, 0x07, 1); - status = - cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, + status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, ADC_FB_FRCRST_CH3, 2, 0x07, 1); /* enable the pre_clamp in each channel for single-ended input */ - status = - cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, + status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, ADC_NTF_PRECLMP_EN_CH1, 2, 0xf0, 1); - status = - cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, + status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, ADC_NTF_PRECLMP_EN_CH2, 2, 0xf0, 1); - status = - cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, + status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, ADC_NTF_PRECLMP_EN_CH3, 2, 0xf0, 1); /* use diode instead of resistor, so set term_en to 0, res_en to 0 */ - status = - cx231xx_reg_mask_write(dev, Colibri_DEVICE_ADDRESS, 8, + status = cx231xx_reg_mask_write(dev, Colibri_DEVICE_ADDRESS, 8, ADC_QGAIN_RES_TRM_CH1, 3, 7, 0x00); - status = - cx231xx_reg_mask_write(dev, Colibri_DEVICE_ADDRESS, 8, + status = cx231xx_reg_mask_write(dev, Colibri_DEVICE_ADDRESS, 8, ADC_QGAIN_RES_TRM_CH2, 3, 7, 0x00); - status = - cx231xx_reg_mask_write(dev, Colibri_DEVICE_ADDRESS, 8, + status = cx231xx_reg_mask_write(dev, Colibri_DEVICE_ADDRESS, 8, ADC_QGAIN_RES_TRM_CH3, 3, 7, 0x00); /* dynamic element matching off */ - status = - cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, + status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, ADC_DCSERVO_DEM_CH1, 2, 0x03, 1); - status = - cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, + status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, ADC_DCSERVO_DEM_CH2, 2, 0x03, 1); - status = - cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, + status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, ADC_DCSERVO_DEM_CH3, 2, 0x03, 1); return status; @@ -235,8 +206,7 @@ int cx231xx_colibri_set_input_mux(struct cx231xx *dev, u32 input_mux) value &= (!INPUT_SEL_MASK); value |= (ch1_setting - 1) << 4; value &= 0xff; - status = - cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, + status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, ADC_INPUT_CH1, 2, value, 1); } @@ -247,21 +217,19 @@ int cx231xx_colibri_set_input_mux(struct cx231xx *dev, u32 input_mux) value &= (!INPUT_SEL_MASK); value |= (ch2_setting - 1) << 4; value &= 0xff; - status = - cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, + status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, ADC_INPUT_CH2, 2, value, 1); } - /* For ch3_setting, the value to put in the register is 7 less than the input number */ + /* For ch3_setting, the value to put in the register is + 7 less than the input number */ if (ch3_setting != 0) { - status = - cx231xx_read_i2c_data(dev, Colibri_DEVICE_ADDRESS, + status = cx231xx_read_i2c_data(dev, Colibri_DEVICE_ADDRESS, ADC_INPUT_CH3, 2, &value, 1); value &= (!INPUT_SEL_MASK); value |= (ch3_setting - 1) << 4; value &= 0xff; - status = - cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, + status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, ADC_INPUT_CH3, 2, value, 1); } @@ -290,12 +258,9 @@ int cx231xx_colibri_set_mode(struct cx231xx *dev, enum AFE_MODE mode) break; } - if ((mode != dev->colibri_mode) - && (dev->video_input == CX231XX_VMUX_TELEVISION)) { - status = - cx231xx_colibri_adjust_ref_count(dev, + if ((mode != dev->colibri_mode) && (dev->video_input == CX231XX_VMUX_TELEVISION)) + status = cx231xx_colibri_adjust_ref_count(dev, CX231XX_VMUX_TELEVISION); - } dev->colibri_mode = mode; @@ -314,84 +279,80 @@ int cx231xx_colibri_update_power_control(struct cx231xx *dev, AV_MODE avmode) if (avmode == POLARIS_AVMODE_ANALOGT_TV) { while (colibri_power_status != 0x18) { - status = - cx231xx_write_i2c_data(dev, - Colibri_DEVICE_ADDRESS, - SUP_BLK_PWRDN, 2, - 0x18, 1); - status = - cx231xx_read_i2c_data(dev, - Colibri_DEVICE_ADDRESS, - SUP_BLK_PWRDN, 2, - &colibri_power_status, - 1); + status = cx231xx_write_i2c_data(dev, + Colibri_DEVICE_ADDRESS, + SUP_BLK_PWRDN, 2, + 0x18, 1); + status = cx231xx_read_i2c_data(dev, + Colibri_DEVICE_ADDRESS, + SUP_BLK_PWRDN, 2, + &colibri_power_status, + 1); if (status < 0) break; } - status = - cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, + status = cx231xx_write_i2c_data(dev, + Colibri_DEVICE_ADDRESS, ADC_PWRDN_CLAMP_CH1, 2, 0x00, 1); - status = - cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, + status = cx231xx_write_i2c_data(dev, + Colibri_DEVICE_ADDRESS, ADC_PWRDN_CLAMP_CH2, 2, 0x00, 1); - status = - cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, + status = cx231xx_write_i2c_data(dev, + Colibri_DEVICE_ADDRESS, ADC_PWRDN_CLAMP_CH3, 2, 0x00, 1); } else if (avmode == POLARIS_AVMODE_DIGITAL) { - status = - cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, + status = cx231xx_write_i2c_data(dev, + Colibri_DEVICE_ADDRESS, ADC_PWRDN_CLAMP_CH1, 2, 0x70, 1); - status = - cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, + status = cx231xx_write_i2c_data(dev, + Colibri_DEVICE_ADDRESS, ADC_PWRDN_CLAMP_CH2, 2, 0x70, 1); - status = - cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, + status = cx231xx_write_i2c_data(dev, + Colibri_DEVICE_ADDRESS, ADC_PWRDN_CLAMP_CH3, 2, 0x70, 1); - status = - cx231xx_read_i2c_data(dev, Colibri_DEVICE_ADDRESS, + status = cx231xx_read_i2c_data(dev, + Colibri_DEVICE_ADDRESS, SUP_BLK_PWRDN, 2, &colibri_power_status, 1); colibri_power_status |= 0x07; - status = - cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, + status = cx231xx_write_i2c_data(dev, + Colibri_DEVICE_ADDRESS, SUP_BLK_PWRDN, 2, colibri_power_status, 1); } else if (avmode == POLARIS_AVMODE_ENXTERNAL_AV) { while (colibri_power_status != 0x18) { - status = - cx231xx_write_i2c_data(dev, - Colibri_DEVICE_ADDRESS, - SUP_BLK_PWRDN, 2, - 0x18, 1); - status = - cx231xx_read_i2c_data(dev, - Colibri_DEVICE_ADDRESS, - SUP_BLK_PWRDN, 2, - &colibri_power_status, - 1); + status = cx231xx_write_i2c_data(dev, + Colibri_DEVICE_ADDRESS, + SUP_BLK_PWRDN, 2, + 0x18, 1); + status = cx231xx_read_i2c_data(dev, + Colibri_DEVICE_ADDRESS, + SUP_BLK_PWRDN, 2, + &colibri_power_status, + 1); if (status < 0) break; } - status = - cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, + status = cx231xx_write_i2c_data(dev, + Colibri_DEVICE_ADDRESS, ADC_PWRDN_CLAMP_CH1, 2, 0x00, 1); - status = - cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, + status = cx231xx_write_i2c_data(dev, + Colibri_DEVICE_ADDRESS, ADC_PWRDN_CLAMP_CH2, 2, 0x00, 1); - status = - cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, + status = cx231xx_write_i2c_data(dev, + Colibri_DEVICE_ADDRESS, ADC_PWRDN_CLAMP_CH3, 2, 0x00, 1); } else { @@ -402,85 +363,83 @@ int cx231xx_colibri_update_power_control(struct cx231xx *dev, AV_MODE avmode) default: if (avmode == POLARIS_AVMODE_ANALOGT_TV) { while (colibri_power_status != 0x18) { - status = - cx231xx_write_i2c_data(dev, - Colibri_DEVICE_ADDRESS, - SUP_BLK_PWRDN, 2, - 0x18, 1); - status = - cx231xx_read_i2c_data(dev, - Colibri_DEVICE_ADDRESS, - SUP_BLK_PWRDN, 2, - &colibri_power_status, - 1); + status = cx231xx_write_i2c_data(dev, + Colibri_DEVICE_ADDRESS, + SUP_BLK_PWRDN, 2, + 0x18, 1); + status = cx231xx_read_i2c_data(dev, + Colibri_DEVICE_ADDRESS, + SUP_BLK_PWRDN, 2, + &colibri_power_status, + 1); if (status < 0) break; } - status = - cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, - ADC_PWRDN_CLAMP_CH1, 2, 0x40, - 1); - status = - cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, - ADC_PWRDN_CLAMP_CH2, 2, 0x40, - 1); - status = - cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, - ADC_PWRDN_CLAMP_CH3, 2, 0x00, - 1); + status = cx231xx_write_i2c_data(dev, + Colibri_DEVICE_ADDRESS, + ADC_PWRDN_CLAMP_CH1, 2, + 0x40, 1); + status = cx231xx_write_i2c_data(dev, + Colibri_DEVICE_ADDRESS, + ADC_PWRDN_CLAMP_CH2, 2, + 0x40, 1); + status = cx231xx_write_i2c_data(dev, + Colibri_DEVICE_ADDRESS, + ADC_PWRDN_CLAMP_CH3, 2, + 0x00, 1); } else if (avmode == POLARIS_AVMODE_DIGITAL) { - status = - cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, - ADC_PWRDN_CLAMP_CH1, 2, 0x70, - 1); - status = - cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, - ADC_PWRDN_CLAMP_CH2, 2, 0x70, - 1); - status = - cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, - ADC_PWRDN_CLAMP_CH3, 2, 0x70, - 1); - - status = - cx231xx_read_i2c_data(dev, Colibri_DEVICE_ADDRESS, - SUP_BLK_PWRDN, 2, - &colibri_power_status, 1); + status = cx231xx_write_i2c_data(dev, + Colibri_DEVICE_ADDRESS, + ADC_PWRDN_CLAMP_CH1, 2, + 0x70, 1); + status = cx231xx_write_i2c_data(dev, + Colibri_DEVICE_ADDRESS, + ADC_PWRDN_CLAMP_CH2, 2, + 0x70, 1); + status = cx231xx_write_i2c_data(dev, + Colibri_DEVICE_ADDRESS, + ADC_PWRDN_CLAMP_CH3, 2, + 0x70, 1); + + status = cx231xx_read_i2c_data(dev, + Colibri_DEVICE_ADDRESS, + SUP_BLK_PWRDN, 2, + &colibri_power_status, + 1); colibri_power_status |= 0x07; - status = - cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, - SUP_BLK_PWRDN, 2, - colibri_power_status, 1); + status = cx231xx_write_i2c_data(dev, + Colibri_DEVICE_ADDRESS, + SUP_BLK_PWRDN, 2, + colibri_power_status, + 1); } else if (avmode == POLARIS_AVMODE_ENXTERNAL_AV) { while (colibri_power_status != 0x18) { - status = - cx231xx_write_i2c_data(dev, - Colibri_DEVICE_ADDRESS, - SUP_BLK_PWRDN, 2, - 0x18, 1); - status = - cx231xx_read_i2c_data(dev, - Colibri_DEVICE_ADDRESS, - SUP_BLK_PWRDN, 2, - &colibri_power_status, - 1); + status = cx231xx_write_i2c_data(dev, + Colibri_DEVICE_ADDRESS, + SUP_BLK_PWRDN, 2, + 0x18, 1); + status = cx231xx_read_i2c_data(dev, + Colibri_DEVICE_ADDRESS, + SUP_BLK_PWRDN, 2, + &colibri_power_status, + 1); if (status < 0) break; } - status = - cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, - ADC_PWRDN_CLAMP_CH1, 2, 0x00, - 1); - status = - cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, - ADC_PWRDN_CLAMP_CH2, 2, 0x00, - 1); - status = - cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, - ADC_PWRDN_CLAMP_CH3, 2, 0x40, - 1); + status = cx231xx_write_i2c_data(dev, + Colibri_DEVICE_ADDRESS, + ADC_PWRDN_CLAMP_CH1, 2, + 0x00, 1); + status = cx231xx_write_i2c_data(dev, + Colibri_DEVICE_ADDRESS, + ADC_PWRDN_CLAMP_CH2, 2, + 0x00, 1); + status = cx231xx_write_i2c_data(dev, + Colibri_DEVICE_ADDRESS, + ADC_PWRDN_CLAMP_CH3, 2, + 0x40, 1); } else { cx231xx_info("Invalid AV mode input\n"); status = -1; @@ -499,19 +458,15 @@ int cx231xx_colibri_adjust_ref_count(struct cx231xx *dev, u32 video_input) dev->video_input = video_input; if (video_input == CX231XX_VMUX_TELEVISION) { - status = - cx231xx_read_i2c_data(dev, Colibri_DEVICE_ADDRESS, + status = cx231xx_read_i2c_data(dev, Colibri_DEVICE_ADDRESS, ADC_INPUT_CH3, 2, &input_mode, 1); - status = - cx231xx_read_i2c_data(dev, Colibri_DEVICE_ADDRESS, + status = cx231xx_read_i2c_data(dev, Colibri_DEVICE_ADDRESS, ADC_NTF_PRECLMP_EN_CH3, 2, &ntf_mode, 1); } else { - status = - cx231xx_read_i2c_data(dev, Colibri_DEVICE_ADDRESS, + status = cx231xx_read_i2c_data(dev, Colibri_DEVICE_ADDRESS, ADC_INPUT_CH1, 2, &input_mode, 1); - status = - cx231xx_read_i2c_data(dev, Colibri_DEVICE_ADDRESS, + status = cx231xx_read_i2c_data(dev, Colibri_DEVICE_ADDRESS, ADC_NTF_PRECLMP_EN_CH1, 2, &ntf_mode, 1); } @@ -540,9 +495,9 @@ int cx231xx_colibri_adjust_ref_count(struct cx231xx *dev, u32 video_input) return status; } -/************************************************************************************* - * V I D E O / A U D I O D E C O D E R C O N T R O L functions * - *************************************************************************************/ +/****************************************************************************** + * V I D E O / A U D I O D E C O D E R C O N T R O L functions * + ******************************************++**********************************/ int cx231xx_set_video_input_mux(struct cx231xx *dev, u8 input) { int status = 0; @@ -552,38 +507,38 @@ int cx231xx_set_video_input_mux(struct cx231xx *dev, u8 input) case CX231XX_VMUX_SVIDEO: if ((dev->current_pcb_config.type == USB_BUS_POWER) && (dev->power_mode != POLARIS_AVMODE_ENXTERNAL_AV)) { - status = cx231xx_set_power_mode(dev, POLARIS_AVMODE_ENXTERNAL_AV); /* External AV */ + /* External AV */ + status = cx231xx_set_power_mode(dev, + POLARIS_AVMODE_ENXTERNAL_AV); if (status < 0) { - cx231xx_errdev - ("%s: cx231xx_set_power_mode : Failed to set Power - errCode [%d]!\n", + cx231xx_errdev("%s: cx231xx_set_power_mode : Failed to set Power - errCode [%d]!\n", __func__, status); return status; } } - status = - cx231xx_set_decoder_video_input(dev, INPUT(input)->type, - INPUT(input)->vmux); + status = cx231xx_set_decoder_video_input(dev, + INPUT(input)->type, + INPUT(input)->vmux); break; case CX231XX_VMUX_TELEVISION: case CX231XX_VMUX_CABLE: if ((dev->current_pcb_config.type == USB_BUS_POWER) && (dev->power_mode != POLARIS_AVMODE_ANALOGT_TV)) { - status = cx231xx_set_power_mode(dev, POLARIS_AVMODE_ANALOGT_TV); /* Tuner */ + /* Tuner */ + status = cx231xx_set_power_mode(dev, + POLARIS_AVMODE_ANALOGT_TV); if (status < 0) { - cx231xx_errdev - ("%s: cx231xx_set_power_mode : Failed to set Power - errCode [%d]!\n", + cx231xx_errdev("%s: cx231xx_set_power_mode : Failed to set Power - errCode [%d]!\n", __func__, status); return status; } } - status = - cx231xx_set_decoder_video_input(dev, - CX231XX_VMUX_COMPOSITE1, - INPUT(input)->vmux); + status = cx231xx_set_decoder_video_input(dev, + CX231XX_VMUX_COMPOSITE1, + INPUT(input)->vmux); break; default: - cx231xx_errdev - ("%s: cx231xx_set_power_mode : Unknown Input %d !\n", + cx231xx_errdev("%s: cx231xx_set_power_mode : Unknown Input %d !\n", __func__, INPUT(input)->type); break; } @@ -602,8 +557,7 @@ int cx231xx_set_decoder_video_input(struct cx231xx *dev, u8 pin_type, u8 input) if (pin_type != dev->video_input) { status = cx231xx_colibri_adjust_ref_count(dev, pin_type); if (status < 0) { - cx231xx_errdev - ("%s: cx231xx_colibri_adjust_ref_count :Failed to set Colibri input mux - errCode [%d]!\n", + cx231xx_errdev("%s: cx231xx_colibri_adjust_ref_count :Failed to set Colibri input mux - errCode [%d]!\n", __func__, status); return status; } @@ -612,57 +566,190 @@ int cx231xx_set_decoder_video_input(struct cx231xx *dev, u8 pin_type, u8 input) /* call colibri block to set video inputs */ status = cx231xx_colibri_set_input_mux(dev, input); if (status < 0) { - cx231xx_errdev - ("%s: cx231xx_colibri_set_input_mux :Failed to set Colibri input mux - errCode [%d]!\n", + cx231xx_errdev("%s: cx231xx_colibri_set_input_mux :Failed to set Colibri input mux - errCode [%d]!\n", __func__, status); return status; } switch (pin_type) { case CX231XX_VMUX_COMPOSITE1: - { - status = - cx231xx_read_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, - AFE_CTRL, 2, &value, 4); + status = cx231xx_read_i2c_data(dev, + HAMMERHEAD_I2C_ADDRESS, + AFE_CTRL, 2, &value, 4); + value |= (0 << 13) | (1 << 4); + value &= ~(1 << 5); + + value &= (~(0x1ff8000)); /* set [24:23] [22:15] to 0 */ + value |= 0x1000000; /* set FUNC_MODE[24:23] = 2 IF_MOD[22:15] = 0 */ + status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, + AFE_CTRL, 2, value, 4); + + status = cx231xx_read_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, + OUT_CTRL1, 2, &value, 4); + value |= (1 << 7); + status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, + OUT_CTRL1, 2, value, 4); + + /* Set vip 1.1 output mode */ + status = cx231xx_read_modify_write_i2c_dword(dev, + HAMMERHEAD_I2C_ADDRESS, + OUT_CTRL1, + FLD_OUT_MODE, + OUT_MODE_VIP11); + + /* Tell DIF object to go to baseband mode */ + status = cx231xx_dif_set_standard(dev, DIF_USE_BASEBAND); + if (status < 0) { + cx231xx_errdev("%s: cx231xx_dif set to By pass mode - errCode [%d]!\n", + __func__, status); + return status; + } + + /* Read the DFE_CTRL1 register */ + status = cx231xx_read_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, + DFE_CTRL1, 2, &value, 4); + + /* enable the VBI_GATE_EN */ + value |= FLD_VBI_GATE_EN; + + /* Enable the auto-VGA enable */ + value |= FLD_VGA_AUTO_EN; + + /* Write it back */ + status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, + DFE_CTRL1, 2, value, 4); + + /* Disable auto config of registers */ + status = cx231xx_read_modify_write_i2c_dword(dev, + HAMMERHEAD_I2C_ADDRESS, + MODE_CTRL, FLD_ACFG_DIS, + cx231xx_set_field(FLD_ACFG_DIS, 1)); + + /* Set CVBS input mode */ + status = cx231xx_read_modify_write_i2c_dword(dev, + HAMMERHEAD_I2C_ADDRESS, + MODE_CTRL, FLD_INPUT_MODE, + cx231xx_set_field(FLD_INPUT_MODE, INPUT_MODE_CVBS_0)); + break; + case CX231XX_VMUX_SVIDEO: + /* Disable the use of DIF */ + + status = cx231xx_read_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, + AFE_CTRL, 2, &value, 4); + + value &= (~(0x1ff8000)); /* set [24:23] [22:15] to 0 */ + value |= 0x1000010; /* set FUNC_MODE[24:23] = 2 + IF_MOD[22:15] = 0 DCR_BYP_CH2[4:4] = 1; */ + status = cx231xx_write_i2c_data(dev, + HAMMERHEAD_I2C_ADDRESS, + AFE_CTRL, 2, value, 4); + + /* Tell DIF object to go to baseband mode */ + status = cx231xx_dif_set_standard(dev, DIF_USE_BASEBAND); + if (status < 0) { + cx231xx_errdev("%s: cx231xx_dif set to By pass mode - errCode [%d]!\n", + __func__, status); + return status; + } + + /* Read the DFE_CTRL1 register */ + status = cx231xx_read_i2c_data(dev, + HAMMERHEAD_I2C_ADDRESS, + DFE_CTRL1, 2, &value, 4); + + /* enable the VBI_GATE_EN */ + value |= FLD_VBI_GATE_EN; + + /* Enable the auto-VGA enable */ + value |= FLD_VGA_AUTO_EN; + + /* Write it back */ + status = cx231xx_write_i2c_data(dev, + HAMMERHEAD_I2C_ADDRESS, + DFE_CTRL1, 2, value, 4); + + /* Disable auto config of registers */ + status = cx231xx_read_modify_write_i2c_dword(dev, + HAMMERHEAD_I2C_ADDRESS, + MODE_CTRL, FLD_ACFG_DIS, + cx231xx_set_field(FLD_ACFG_DIS, 1)); + + /* Set YC input mode */ + status = cx231xx_read_modify_write_i2c_dword(dev, + HAMMERHEAD_I2C_ADDRESS, + MODE_CTRL, + FLD_INPUT_MODE, + cx231xx_set_field(FLD_INPUT_MODE, INPUT_MODE_YC_1)); + + /* Chroma to ADC2 */ + status = cx231xx_read_i2c_data(dev, + HAMMERHEAD_I2C_ADDRESS, + AFE_CTRL, 2, &value, 4); + value |= FLD_CHROMA_IN_SEL; /* set the chroma in select */ + + /* Clear VGA_SEL_CH2 and VGA_SEL_CH3 (bits 7 and 8) + This sets them to use video + rather than audio. Only one of the two will be in use. */ + value &= ~(FLD_VGA_SEL_CH2 | FLD_VGA_SEL_CH3); + + status = cx231xx_write_i2c_data(dev, + HAMMERHEAD_I2C_ADDRESS, + AFE_CTRL, 2, value, 4); + + status = cx231xx_colibri_set_mode(dev, AFE_MODE_BASEBAND); + break; + case CX231XX_VMUX_TELEVISION: + case CX231XX_VMUX_CABLE: + default: + switch (dev->model) { + case CX231XX_BOARD_CNXT_RDE_250: + case CX231XX_BOARD_CNXT_RDU_250: + /* Disable the use of DIF */ + + status = cx231xx_read_i2c_data(dev, + HAMMERHEAD_I2C_ADDRESS, + AFE_CTRL, 2, + &value, 4); value |= (0 << 13) | (1 << 4); value &= ~(1 << 5); - value &= (~(0x1FF8000)); /* set [24:23] [22:15] to 0 */ - value |= 0x1000000; /* set FUNC_MODE[24:23] = 2 IF_MOD[22:15] = 0 */ - status = - cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, - AFE_CTRL, 2, value, 4); + value &= (~(0x1FF8000)); /* set [24:23] [22:15] to 0 */ + value |= 0x1000000; /* set FUNC_MODE[24:23] = 2 IF_MOD[22:15] = 0 */ + status = cx231xx_write_i2c_data(dev, + HAMMERHEAD_I2C_ADDRESS, + AFE_CTRL, 2, + value, 4); - status = - cx231xx_read_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, - OUT_CTRL1, 2, &value, 4); + status = cx231xx_read_i2c_data(dev, + HAMMERHEAD_I2C_ADDRESS, + OUT_CTRL1, 2, + &value, 4); value |= (1 << 7); - status = - cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, - OUT_CTRL1, 2, value, 4); + status = cx231xx_write_i2c_data(dev, + HAMMERHEAD_I2C_ADDRESS, + OUT_CTRL1, 2, + value, 4); /* Set vip 1.1 output mode */ - status = - cx231xx_read_modify_write_i2c_dword(dev, - HAMMERHEAD_I2C_ADDRESS, - OUT_CTRL1, - FLD_OUT_MODE, - OUT_MODE_VIP11); + status = cx231xx_read_modify_write_i2c_dword(dev, + HAMMERHEAD_I2C_ADDRESS, + OUT_CTRL1, FLD_OUT_MODE, + OUT_MODE_VIP11); - /* Tell DIF object to go to baseband mode */ - status = - cx231xx_dif_set_standard(dev, DIF_USE_BASEBAND); + /* Tell DIF object to go to baseband mode */ + status = cx231xx_dif_set_standard(dev, + DIF_USE_BASEBAND); if (status < 0) { - cx231xx_errdev - ("%s: cx231xx_dif set to By pass mode - errCode [%d]!\n", - __func__, status); + cx231xx_errdev("%s: cx231xx_dif set to By pass mode - errCode [%d]!\n", + __func__, status); return status; } /* Read the DFE_CTRL1 register */ - status = - cx231xx_read_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, - DFE_CTRL1, 2, &value, 4); + status = cx231xx_read_i2c_data(dev, + HAMMERHEAD_I2C_ADDRESS, + DFE_CTRL1, 2, + &value, 4); /* enable the VBI_GATE_EN */ value |= FLD_VBI_GATE_EN; @@ -671,349 +758,144 @@ int cx231xx_set_decoder_video_input(struct cx231xx *dev, u8 pin_type, u8 input) value |= FLD_VGA_AUTO_EN; /* Write it back */ - status = - cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, - DFE_CTRL1, 2, value, 4); + status = cx231xx_write_i2c_data(dev, + HAMMERHEAD_I2C_ADDRESS, + DFE_CTRL1, 2, + value, 4); /* Disable auto config of registers */ - status = - cx231xx_read_modify_write_i2c_dword(dev, - HAMMERHEAD_I2C_ADDRESS, - MODE_CTRL, - FLD_ACFG_DIS, - cx231xx_set_field - (FLD_ACFG_DIS, - 1)); + status = cx231xx_read_modify_write_i2c_dword(dev, + HAMMERHEAD_I2C_ADDRESS, + MODE_CTRL, FLD_ACFG_DIS, + cx231xx_set_field(FLD_ACFG_DIS, 1)); /* Set CVBS input mode */ - status = - cx231xx_read_modify_write_i2c_dword(dev, - HAMMERHEAD_I2C_ADDRESS, - MODE_CTRL, - FLD_INPUT_MODE, - cx231xx_set_field - (FLD_INPUT_MODE, - INPUT_MODE_CVBS_0)); - } - break; - case CX231XX_VMUX_SVIDEO: - { - /* Disable the use of DIF */ - - status = - cx231xx_read_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, - AFE_CTRL, 2, &value, 4); - - value &= (~(0x1FF8000)); /* set [24:23] [22:15] to 0 */ - value |= 0x1000010; /* set FUNC_MODE[24:23] = 2 - IF_MOD[22:15] = 0 DCR_BYP_CH2[4:4] = 1; */ - status = - cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, - AFE_CTRL, 2, value, 4); + status = cx231xx_read_modify_write_i2c_dword(dev, + HAMMERHEAD_I2C_ADDRESS, + MODE_CTRL, FLD_INPUT_MODE, + cx231xx_set_field(FLD_INPUT_MODE, INPUT_MODE_CVBS_0)); + break; + default: + /* Enable the DIF for the tuner */ - /* Tell DIF object to go to baseband mode */ - status = - cx231xx_dif_set_standard(dev, DIF_USE_BASEBAND); + /* Reinitialize the DIF */ + status = cx231xx_dif_set_standard(dev, dev->norm); if (status < 0) { - cx231xx_errdev - ("%s: cx231xx_dif set to By pass mode - errCode [%d]!\n", - __func__, status); + cx231xx_errdev("%s: cx231xx_dif set to By pass mode - errCode [%d]!\n", + __func__, status); return status; } + /* Make sure bypass is cleared */ + status = cx231xx_read_i2c_data(dev, + HAMMERHEAD_I2C_ADDRESS, + DIF_MISC_CTRL, + 2, &value, 4); + + /* Clear the bypass bit */ + value &= ~FLD_DIF_DIF_BYPASS; + + /* Enable the use of the DIF block */ + status = cx231xx_write_i2c_data(dev, + HAMMERHEAD_I2C_ADDRESS, + DIF_MISC_CTRL, + 2, value, 4); + /* Read the DFE_CTRL1 register */ - status = - cx231xx_read_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, - DFE_CTRL1, 2, &value, 4); + status = cx231xx_read_i2c_data(dev, + HAMMERHEAD_I2C_ADDRESS, + DFE_CTRL1, 2, + &value, 4); - /* enable the VBI_GATE_EN */ - value |= FLD_VBI_GATE_EN; + /* Disable the VBI_GATE_EN */ + value &= ~FLD_VBI_GATE_EN; - /* Enable the auto-VGA enable */ - value |= FLD_VGA_AUTO_EN; + /* Enable the auto-VGA enable, AGC, and + set the skip count to 2 */ + value |= FLD_VGA_AUTO_EN | FLD_AGC_AUTO_EN | 0x00200000; /* Write it back */ - status = - cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, - DFE_CTRL1, 2, value, 4); + status = cx231xx_write_i2c_data(dev, + HAMMERHEAD_I2C_ADDRESS, + DFE_CTRL1, 2, + value, 4); - /* Disable auto config of registers */ - status = - cx231xx_read_modify_write_i2c_dword(dev, - HAMMERHEAD_I2C_ADDRESS, - MODE_CTRL, - FLD_ACFG_DIS, - cx231xx_set_field - (FLD_ACFG_DIS, - 1)); - - /* Set YC input mode */ - status = - cx231xx_read_modify_write_i2c_dword(dev, - HAMMERHEAD_I2C_ADDRESS, - MODE_CTRL, - FLD_INPUT_MODE, - cx231xx_set_field - (FLD_INPUT_MODE, - INPUT_MODE_YC_1)); - - /* Chroma to ADC2 */ - status = - cx231xx_read_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, - AFE_CTRL, 2, &value, 4); - value |= FLD_CHROMA_IN_SEL; /* set the chroma in select */ + /* Wait 15 ms */ + msleep(1); - /* Clear VGA_SEL_CH2 and VGA_SEL_CH3 (bits 7 and 8) This sets them to use video - rather than audio. Only one of the two will be in use. */ - value &= ~(FLD_VGA_SEL_CH2 | FLD_VGA_SEL_CH3); + /* Disable the auto-VGA enable AGC */ + value &= ~(FLD_VGA_AUTO_EN); - status = - cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, - AFE_CTRL, 2, value, 4); + /* Write it back */ + status = cx231xx_write_i2c_data(dev, + HAMMERHEAD_I2C_ADDRESS, + DFE_CTRL1, 2, + value, 4); - status = - cx231xx_colibri_set_mode(dev, AFE_MODE_BASEBAND); - } - break; - case CX231XX_VMUX_TELEVISION: - case CX231XX_VMUX_CABLE: - default: - { - switch (dev->model) { - case CX231XX_BOARD_CNXT_RDE_250: - case CX231XX_BOARD_CNXT_RDU_250: - { - /* Disable the use of DIF */ - - status = - cx231xx_read_i2c_data(dev, - HAMMERHEAD_I2C_ADDRESS, - AFE_CTRL, 2, - &value, 4); - value |= (0 << 13) | (1 << 4); - value &= ~(1 << 5); - - value &= (~(0x1FF8000)); /* set [24:23] [22:15] to 0 */ - value |= 0x1000000; /* set FUNC_MODE[24:23] = 2 IF_MOD[22:15] = 0 */ - status = - cx231xx_write_i2c_data(dev, - HAMMERHEAD_I2C_ADDRESS, - AFE_CTRL, 2, - value, 4); - - status = - cx231xx_read_i2c_data(dev, - HAMMERHEAD_I2C_ADDRESS, - OUT_CTRL1, 2, - &value, 4); - value |= (1 << 7); - status = - cx231xx_write_i2c_data(dev, - HAMMERHEAD_I2C_ADDRESS, - OUT_CTRL1, 2, - value, 4); - - /* Set vip 1.1 output mode */ - status = - cx231xx_read_modify_write_i2c_dword - (dev, HAMMERHEAD_I2C_ADDRESS, - OUT_CTRL1, FLD_OUT_MODE, - OUT_MODE_VIP11); - - /* Tell DIF object to go to baseband mode */ - status = - cx231xx_dif_set_standard(dev, - DIF_USE_BASEBAND); - if (status < 0) { - cx231xx_errdev - ("%s: cx231xx_dif set to By pass mode - errCode [%d]!\n", - __func__, status); - return status; - } - - /* Read the DFE_CTRL1 register */ - status = - cx231xx_read_i2c_data(dev, - HAMMERHEAD_I2C_ADDRESS, - DFE_CTRL1, 2, - &value, 4); - - /* enable the VBI_GATE_EN */ - value |= FLD_VBI_GATE_EN; - - /* Enable the auto-VGA enable */ - value |= FLD_VGA_AUTO_EN; - - /* Write it back */ - status = - cx231xx_write_i2c_data(dev, - HAMMERHEAD_I2C_ADDRESS, - DFE_CTRL1, 2, - value, 4); - - /* Disable auto config of registers */ - status = - cx231xx_read_modify_write_i2c_dword - (dev, HAMMERHEAD_I2C_ADDRESS, - MODE_CTRL, FLD_ACFG_DIS, - cx231xx_set_field(FLD_ACFG_DIS, - 1)); - - /* Set CVBS input mode */ - status = - cx231xx_read_modify_write_i2c_dword - (dev, HAMMERHEAD_I2C_ADDRESS, - MODE_CTRL, FLD_INPUT_MODE, - cx231xx_set_field(FLD_INPUT_MODE, - INPUT_MODE_CVBS_0)); - } - break; - default: - { - /* Enable the DIF for the tuner */ - - /* Reinitialize the DIF */ - status = - cx231xx_dif_set_standard(dev, - dev->norm); - if (status < 0) { - cx231xx_errdev - ("%s: cx231xx_dif set to By pass mode - errCode [%d]!\n", - __func__, status); - return status; - } - - /* Make sure bypass is cleared */ - status = - cx231xx_read_i2c_data(dev, - HAMMERHEAD_I2C_ADDRESS, - DIF_MISC_CTRL, - 2, &value, 4); - - /* Clear the bypass bit */ - value &= ~FLD_DIF_DIF_BYPASS; - - /* Enable the use of the DIF block */ - status = - cx231xx_write_i2c_data(dev, - HAMMERHEAD_I2C_ADDRESS, - DIF_MISC_CTRL, - 2, value, 4); - - /* Read the DFE_CTRL1 register */ - status = - cx231xx_read_i2c_data(dev, - HAMMERHEAD_I2C_ADDRESS, - DFE_CTRL1, 2, - &value, 4); - - /* Disable the VBI_GATE_EN */ - value &= ~FLD_VBI_GATE_EN; - - /* Enable the auto-VGA enable, AGC, and set the skip count to 2 */ - value |= - FLD_VGA_AUTO_EN | FLD_AGC_AUTO_EN | - 0x00200000; - - /* Write it back */ - status = - cx231xx_write_i2c_data(dev, - HAMMERHEAD_I2C_ADDRESS, - DFE_CTRL1, 2, - value, 4); - - /* Wait 15 ms */ - msleep(1); - - /* Disable the auto-VGA enable AGC */ - value &= ~(FLD_VGA_AUTO_EN); - - /* Write it back */ - status = - cx231xx_write_i2c_data(dev, - HAMMERHEAD_I2C_ADDRESS, - DFE_CTRL1, 2, - value, 4); - - /* Enable Polaris B0 AGC output */ - status = - cx231xx_read_i2c_data(dev, - HAMMERHEAD_I2C_ADDRESS, - PIN_CTRL, 2, - &value, 4); - value |= - (FLD_OEF_AGC_RF) | - (FLD_OEF_AGC_IFVGA) | - (FLD_OEF_AGC_IF); - status = - cx231xx_write_i2c_data(dev, - HAMMERHEAD_I2C_ADDRESS, - PIN_CTRL, 2, - value, 4); - - /* Set vip 1.1 output mode */ - status = - cx231xx_read_modify_write_i2c_dword - (dev, HAMMERHEAD_I2C_ADDRESS, - OUT_CTRL1, FLD_OUT_MODE, - OUT_MODE_VIP11); - - /* Disable auto config of registers */ - status = - cx231xx_read_modify_write_i2c_dword - (dev, HAMMERHEAD_I2C_ADDRESS, - MODE_CTRL, FLD_ACFG_DIS, - cx231xx_set_field(FLD_ACFG_DIS, - 1)); - - /* Set CVBS input mode */ - status = - cx231xx_read_modify_write_i2c_dword - (dev, HAMMERHEAD_I2C_ADDRESS, - MODE_CTRL, FLD_INPUT_MODE, - cx231xx_set_field(FLD_INPUT_MODE, - INPUT_MODE_CVBS_0)); - - /* Set some bits in AFE_CTRL so that channel 2 or 3 is ready to receive audio */ - /* Clear clamp for channels 2 and 3 (bit 16-17) */ - /* Clear droop comp (bit 19-20) */ - /* Set VGA_SEL (for audio control) (bit 7-8) */ - status = - cx231xx_read_i2c_data(dev, - HAMMERHEAD_I2C_ADDRESS, - AFE_CTRL, 2, - &value, 4); - - value |= - FLD_VGA_SEL_CH3 | FLD_VGA_SEL_CH2; - - status = - cx231xx_write_i2c_data(dev, - HAMMERHEAD_I2C_ADDRESS, - AFE_CTRL, 2, - value, 4); - } - break; + /* Enable Polaris B0 AGC output */ + status = cx231xx_read_i2c_data(dev, + HAMMERHEAD_I2C_ADDRESS, + PIN_CTRL, 2, + &value, 4); + value |= (FLD_OEF_AGC_RF) | + (FLD_OEF_AGC_IFVGA) | + (FLD_OEF_AGC_IF); + status = cx231xx_write_i2c_data(dev, + HAMMERHEAD_I2C_ADDRESS, + PIN_CTRL, 2, + value, 4); + + /* Set vip 1.1 output mode */ + status = cx231xx_read_modify_write_i2c_dword(dev, + HAMMERHEAD_I2C_ADDRESS, + OUT_CTRL1, FLD_OUT_MODE, + OUT_MODE_VIP11); + + /* Disable auto config of registers */ + status = cx231xx_read_modify_write_i2c_dword(dev, + HAMMERHEAD_I2C_ADDRESS, + MODE_CTRL, FLD_ACFG_DIS, + cx231xx_set_field(FLD_ACFG_DIS, 1)); + + /* Set CVBS input mode */ + status = cx231xx_read_modify_write_i2c_dword(dev, + HAMMERHEAD_I2C_ADDRESS, + MODE_CTRL, FLD_INPUT_MODE, + cx231xx_set_field(FLD_INPUT_MODE, INPUT_MODE_CVBS_0)); + + /* Set some bits in AFE_CTRL so that channel 2 or 3 is ready to receive audio */ + /* Clear clamp for channels 2 and 3 (bit 16-17) */ + /* Clear droop comp (bit 19-20) */ + /* Set VGA_SEL (for audio control) (bit 7-8) */ + status = cx231xx_read_i2c_data(dev, + HAMMERHEAD_I2C_ADDRESS, + AFE_CTRL, 2, + &value, 4); + + value |= FLD_VGA_SEL_CH3 | FLD_VGA_SEL_CH2; + + status = cx231xx_write_i2c_data(dev, + HAMMERHEAD_I2C_ADDRESS, + AFE_CTRL, 2, + value, 4); + break; - } } break; } /* Set raw VBI mode */ - status = - cx231xx_read_modify_write_i2c_dword(dev, HAMMERHEAD_I2C_ADDRESS, - OUT_CTRL1, FLD_VBIHACTRAW_EN, - cx231xx_set_field - (FLD_VBIHACTRAW_EN, 1)); + status = cx231xx_read_modify_write_i2c_dword(dev, + HAMMERHEAD_I2C_ADDRESS, + OUT_CTRL1, FLD_VBIHACTRAW_EN, + cx231xx_set_field(FLD_VBIHACTRAW_EN, 1)); - status = - cx231xx_read_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, OUT_CTRL1, 2, - &value, 4); + status = cx231xx_read_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, + OUT_CTRL1, 2, + &value, 4); if (value & 0x02) { value |= (1 << 19); - status = - cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, + status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, OUT_CTRL1, 2, value, 4); } @@ -1032,70 +914,62 @@ int cx231xx_do_mode_ctrl_overrides(struct cx231xx *dev) (unsigned int)dev->norm); /* Change the DFE_CTRL3 bp_percent to fix flagging */ - status = - cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, DFE_CTRL3, 2, - 0xCD3F0280, 4); + status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, + DFE_CTRL3, 2, + 0xCD3F0280, 4); if (dev->norm & (V4L2_STD_NTSC_M | V4L2_STD_NTSC_M_JP | V4L2_STD_PAL_M)) { cx231xx_info("do_mode_ctrl_overrides NTSC\n"); - /* Move the close caption lines out of active video, adjust the active video start point */ - status = - cx231xx_read_modify_write_i2c_dword(dev, + /* Move the close caption lines out of active video, + adjust the active video start point */ + status = cx231xx_read_modify_write_i2c_dword(dev, HAMMERHEAD_I2C_ADDRESS, VERT_TIM_CTRL, FLD_VBLANK_CNT, 0x18); - status = - cx231xx_read_modify_write_i2c_dword(dev, + status = cx231xx_read_modify_write_i2c_dword(dev, HAMMERHEAD_I2C_ADDRESS, VERT_TIM_CTRL, FLD_VACTIVE_CNT, 0x1E6000); - status = - cx231xx_read_modify_write_i2c_dword(dev, + status = cx231xx_read_modify_write_i2c_dword(dev, HAMMERHEAD_I2C_ADDRESS, VERT_TIM_CTRL, FLD_V656BLANK_CNT, 0x1E000000); - status = - cx231xx_read_modify_write_i2c_dword(dev, + status = cx231xx_read_modify_write_i2c_dword(dev, HAMMERHEAD_I2C_ADDRESS, HORIZ_TIM_CTRL, FLD_HBLANK_CNT, cx231xx_set_field (FLD_HBLANK_CNT, 0x79)); - } else if (dev-> - norm & (V4L2_STD_PAL_B | V4L2_STD_PAL_G | V4L2_STD_PAL_D | - V4L2_STD_PAL_I | V4L2_STD_PAL_N | V4L2_STD_PAL_Nc)) { + } else if (dev->norm & (V4L2_STD_PAL_B | V4L2_STD_PAL_G | + V4L2_STD_PAL_D | V4L2_STD_PAL_I | + V4L2_STD_PAL_N | V4L2_STD_PAL_Nc)) { cx231xx_info("do_mode_ctrl_overrides PAL\n"); - status = - cx231xx_read_modify_write_i2c_dword(dev, + status = cx231xx_read_modify_write_i2c_dword(dev, HAMMERHEAD_I2C_ADDRESS, VERT_TIM_CTRL, FLD_VBLANK_CNT, 0x24); /* Adjust the active video horizontal start point */ - status = - cx231xx_read_modify_write_i2c_dword(dev, + status = cx231xx_read_modify_write_i2c_dword(dev, HAMMERHEAD_I2C_ADDRESS, HORIZ_TIM_CTRL, FLD_HBLANK_CNT, cx231xx_set_field (FLD_HBLANK_CNT, 0x85)); - } else if (dev-> - norm & (V4L2_STD_SECAM_B | V4L2_STD_SECAM_D | - V4L2_STD_SECAM_G | V4L2_STD_SECAM_K | - V4L2_STD_SECAM_K1 | V4L2_STD_SECAM_L | - V4L2_STD_SECAM_LC)) { + } else if (dev->norm & (V4L2_STD_SECAM_B | V4L2_STD_SECAM_D | + V4L2_STD_SECAM_G | V4L2_STD_SECAM_K | + V4L2_STD_SECAM_K1 | V4L2_STD_SECAM_L | + V4L2_STD_SECAM_LC)) { cx231xx_info("do_mode_ctrl_overrides SECAM\n"); - status = - cx231xx_read_modify_write_i2c_dword(dev, + status = cx231xx_read_modify_write_i2c_dword(dev, HAMMERHEAD_I2C_ADDRESS, VERT_TIM_CTRL, FLD_VBLANK_CNT, 0x24); /* Adjust the active video horizontal start point */ - status = - cx231xx_read_modify_write_i2c_dword(dev, + status = cx231xx_read_modify_write_i2c_dword(dev, HAMMERHEAD_I2C_ADDRESS, HORIZ_TIM_CTRL, FLD_HBLANK_CNT, @@ -1137,69 +1011,57 @@ int cx231xx_set_audio_decoder_input(struct cx231xx *dev, u32 value = 0; /* Put it in soft reset */ - status = - cx231xx_read_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, GENERAL_CTL, 2, - &gen_ctrl, 1); + status = cx231xx_read_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, + GENERAL_CTL, 2, &gen_ctrl, 1); gen_ctrl |= 1; - status = - cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, GENERAL_CTL, 2, - gen_ctrl, 1); + status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, + GENERAL_CTL, 2, gen_ctrl, 1); switch (audio_input) { case AUDIO_INPUT_LINE: - /* setup AUD_IO control from Merlin paralle output */ - value = - cx231xx_set_field(FLD_AUD_CHAN1_SRC, AUD_CHAN_SRC_PARALLEL); - status = - cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, - AUD_IO_CTRL, 2, value, 4); + value = cx231xx_set_field(FLD_AUD_CHAN1_SRC, + AUD_CHAN_SRC_PARALLEL); + status = cx231xx_write_i2c_data(dev, + HAMMERHEAD_I2C_ADDRESS, + AUD_IO_CTRL, 2, value, 4); /* setup input to Merlin, SRC2 connect to AC97 bypass upsample-by-2, slave mode, sony mode, left justify adr 091c, dat 01000000 */ - status = - cx231xx_read_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, AC97_CTL, + status = cx231xx_read_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, + AC97_CTL, 2, &dwval, 4); - status = - cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, + status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, AC97_CTL, 2, (dwval | FLD_AC97_UP2X_BYPASS), 4); /* select the parallel1 and SRC3 */ - status = - cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, - BAND_OUT_SEL, 2, - cx231xx_set_field(FLD_SRC3_IN_SEL, - 0x0) | - cx231xx_set_field(FLD_SRC3_CLK_SEL, - 0x0) | - cx231xx_set_field - (FLD_PARALLEL1_SRC_SEL, 0x0), 4); + status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, + BAND_OUT_SEL, 2, + cx231xx_set_field(FLD_SRC3_IN_SEL, 0x0) | + cx231xx_set_field(FLD_SRC3_CLK_SEL, 0x0) | + cx231xx_set_field(FLD_PARALLEL1_SRC_SEL, 0x0), + 4); /* unmute all, AC97 in, independence mode adr 08d0, data 0x00063073 */ - status = - cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, + status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, PATH1_CTL1, 2, 0x00063073, 4); /* set AVC maximum threshold, adr 08d4, dat ffff0024 */ - status = - cx231xx_read_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, + status = cx231xx_read_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, PATH1_VOL_CTL, 2, &dwval, 4); - status = - cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, + status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, PATH1_VOL_CTL, 2, (dwval | FLD_PATH1_AVC_THRESHOLD), 4); /* set SC maximum threshold, adr 08ec, dat ffffb3a3 */ - status = - cx231xx_read_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, + status = cx231xx_read_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, PATH1_SC_CTL, 2, &dwval, 4); - status = - cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, + status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, PATH1_SC_CTL, 2, (dwval | FLD_PATH1_SC_THRESHOLD), 4); break; @@ -1208,73 +1070,46 @@ int cx231xx_set_audio_decoder_input(struct cx231xx *dev, default: /* Setup SRC sources and clocks */ - status = - cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, - BAND_OUT_SEL, 2, - cx231xx_set_field(FLD_SRC6_IN_SEL, - 0x00) | - cx231xx_set_field(FLD_SRC6_CLK_SEL, - 0x01) | - cx231xx_set_field(FLD_SRC5_IN_SEL, - 0x00) | - cx231xx_set_field(FLD_SRC5_CLK_SEL, - 0x02) | - cx231xx_set_field(FLD_SRC4_IN_SEL, - 0x02) | - cx231xx_set_field(FLD_SRC4_CLK_SEL, - 0x03) | - cx231xx_set_field(FLD_SRC3_IN_SEL, - 0x00) | - cx231xx_set_field(FLD_SRC3_CLK_SEL, - 0x00) | - cx231xx_set_field - (FLD_BASEBAND_BYPASS_CTL, - 0x00) | - cx231xx_set_field(FLD_AC97_SRC_SEL, - 0x03) | - cx231xx_set_field(FLD_I2S_SRC_SEL, - 0x00) | - cx231xx_set_field - (FLD_PARALLEL2_SRC_SEL, - 0x02) | - cx231xx_set_field - (FLD_PARALLEL1_SRC_SEL, 0x01), 4); + status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, + BAND_OUT_SEL, 2, + cx231xx_set_field(FLD_SRC6_IN_SEL, 0x00) | + cx231xx_set_field(FLD_SRC6_CLK_SEL, 0x01) | + cx231xx_set_field(FLD_SRC5_IN_SEL, 0x00) | + cx231xx_set_field(FLD_SRC5_CLK_SEL, 0x02) | + cx231xx_set_field(FLD_SRC4_IN_SEL, 0x02) | + cx231xx_set_field(FLD_SRC4_CLK_SEL, 0x03) | + cx231xx_set_field(FLD_SRC3_IN_SEL, 0x00) | + cx231xx_set_field(FLD_SRC3_CLK_SEL, 0x00) | + cx231xx_set_field(FLD_BASEBAND_BYPASS_CTL, 0x00) | + cx231xx_set_field(FLD_AC97_SRC_SEL, 0x03) | + cx231xx_set_field(FLD_I2S_SRC_SEL, 0x00) | + cx231xx_set_field(FLD_PARALLEL2_SRC_SEL, 0x02) | + cx231xx_set_field(FLD_PARALLEL1_SRC_SEL, 0x01), 4); /* Setup the AUD_IO control */ - status = - cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, - AUD_IO_CTRL, 2, - cx231xx_set_field(FLD_I2S_PORT_DIR, - 0x00) | - cx231xx_set_field(FLD_I2S_OUT_SRC, - 0x00) | - cx231xx_set_field(FLD_AUD_CHAN3_SRC, - 0x00) | - cx231xx_set_field(FLD_AUD_CHAN2_SRC, - 0x00) | - cx231xx_set_field(FLD_AUD_CHAN1_SRC, - 0x03), 4); + status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, + AUD_IO_CTRL, 2, + cx231xx_set_field(FLD_I2S_PORT_DIR, 0x00) | + cx231xx_set_field(FLD_I2S_OUT_SRC, 0x00) | + cx231xx_set_field(FLD_AUD_CHAN3_SRC, 0x00) | + cx231xx_set_field(FLD_AUD_CHAN2_SRC, 0x00) | + cx231xx_set_field(FLD_AUD_CHAN1_SRC, 0x03), 4); - status = - cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, + status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, PATH1_CTL1, 2, 0x1F063870, 4); /* setAudioStandard(_audio_standard); */ - status = - cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, + status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, PATH1_CTL1, 2, 0x00063870, 4); switch (dev->model) { case CX231XX_BOARD_CNXT_RDE_250: case CX231XX_BOARD_CNXT_RDU_250: - status = - cx231xx_read_modify_write_i2c_dword(dev, - HAMMERHEAD_I2C_ADDRESS, - CHIP_CTRL, - FLD_SIF_EN, - cx231xx_set_field - (FLD_SIF_EN, - 1)); + status = cx231xx_read_modify_write_i2c_dword(dev, + HAMMERHEAD_I2C_ADDRESS, + CHIP_CTRL, + FLD_SIF_EN, + cx231xx_set_field(FLD_SIF_EN, 1)); break; default: break; @@ -1289,20 +1124,17 @@ int cx231xx_set_audio_decoder_input(struct cx231xx *dev, break; case AUDIO_INPUT_MUTE: - status = - cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, + status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, PATH1_CTL1, 2, 0x1F011012, 4); break; } /* Take it out of soft reset */ - status = - cx231xx_read_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, GENERAL_CTL, 2, - &gen_ctrl, 1); + status = cx231xx_read_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, + GENERAL_CTL, 2, &gen_ctrl, 1); gen_ctrl &= ~1; - status = - cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, GENERAL_CTL, 2, - gen_ctrl, 1); + status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, + GENERAL_CTL, 2, gen_ctrl, 1); return status; } @@ -1320,33 +1152,29 @@ int cx231xx_resolution_set(struct cx231xx *dev) get_scale(dev, width, height, &hscale, &vscale); /* set horzontal scale */ - status = - cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, HSCALE_CTRL, 2, - hscale, 4); + status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, + HSCALE_CTRL, 2, hscale, 4); /* set vertical scale */ - status = - cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, VSCALE_CTRL, 2, - vscale, 4); + status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, + VSCALE_CTRL, 2, vscale, 4); return status; } -/************************************************************************************* - * C H I P Specific C O N T R O L functions * - *************************************************************************************/ +/****************************************************************************** + * C H I P Specific C O N T R O L functions * + ******************************************************************************/ int cx231xx_init_ctrl_pin_status(struct cx231xx *dev) { u32 value; int status = 0; - status = - cx231xx_read_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, PIN_CTRL, 2, - &value, 4); + status = cx231xx_read_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, PIN_CTRL, + 2, &value, 4); value |= (~dev->board.ctl_pin_status_mask); - status = - cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, PIN_CTRL, 2, - value, 4); + status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, PIN_CTRL, + 2, value, 4); return status; } @@ -1357,14 +1185,12 @@ int cx231xx_set_agc_analog_digital_mux_select(struct cx231xx *dev, int status = 0; /* first set the direction to output */ - status = - cx231xx_set_gpio_direction(dev, - dev->board. - agc_analog_digital_select_gpio, 1); + status = cx231xx_set_gpio_direction(dev, + dev->board. + agc_analog_digital_select_gpio, 1); /* 0 - demod ; 1 - Analog mode */ - status = - cx231xx_set_gpio_value(dev, + status = cx231xx_set_gpio_value(dev, dev->board.agc_analog_digital_select_gpio, analog_or_digital); @@ -1378,23 +1204,21 @@ int cx231xx_enable_i2c_for_tuner(struct cx231xx *dev, u8 I2CIndex) cx231xx_info("Changing the i2c port for tuner to %d\n", I2CIndex); - status = - cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, PWR_CTL_EN, value, 4); + status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, + PWR_CTL_EN, value, 4); if (status < 0) return status; if (I2CIndex == I2C_1) { if (value[0] & I2C_DEMOD_EN) { value[0] &= ~I2C_DEMOD_EN; - status = - cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, + status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, PWR_CTL_EN, value, 4); } } else { if (!(value[0] & I2C_DEMOD_EN)) { value[0] |= I2C_DEMOD_EN; - status = - cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, + status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, PWR_CTL_EN, value, 4); } } @@ -1403,9 +1227,9 @@ int cx231xx_enable_i2c_for_tuner(struct cx231xx *dev, u8 I2CIndex) } -/************************************************************************************* - * D I F - B L O C K C O N T R O L functions * - *************************************************************************************/ +/****************************************************************************** + * D I F - B L O C K C O N T R O L functions * + ******************************************************************************/ int cx231xx_dif_configure_C2HH_for_low_IF(struct cx231xx *dev, u32 mode, u32 function_mode, u32 standard) { @@ -1413,10 +1237,14 @@ int cx231xx_dif_configure_C2HH_for_low_IF(struct cx231xx *dev, u32 mode, if (mode == V4L2_TUNER_RADIO) { /* C2HH */ - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, AFE_CTRL_C2HH_SRC_CTRL, 30, 31, 0x1); /* lo if big signal */ - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, AFE_CTRL_C2HH_SRC_CTRL, 23, 24, function_mode); /* FUNC_MODE = DIF */ - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, AFE_CTRL_C2HH_SRC_CTRL, 15, 22, 0xFF); /* IF_MODE */ - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, AFE_CTRL_C2HH_SRC_CTRL, 9, 9, 0x1); /* no inv */ + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + AFE_CTRL_C2HH_SRC_CTRL, 30, 31, 0x1); /* lo if big signal */ + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + AFE_CTRL_C2HH_SRC_CTRL, 23, 24, function_mode); /* FUNC_MODE = DIF */ + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + AFE_CTRL_C2HH_SRC_CTRL, 15, 22, 0xFF); /* IF_MODE */ + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + AFE_CTRL_C2HH_SRC_CTRL, 9, 9, 0x1); /* no inv */ } else { switch (standard) { case V4L2_STD_NTSC_M: /* 75 IRE Setup */ @@ -1424,20 +1252,40 @@ int cx231xx_dif_configure_C2HH_for_low_IF(struct cx231xx *dev, u32 mode, case V4L2_STD_PAL_M: case V4L2_STD_PAL_N: case V4L2_STD_PAL_Nc: - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, AFE_CTRL_C2HH_SRC_CTRL, 30, 31, 0x1); /* lo if big signal */ - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, AFE_CTRL_C2HH_SRC_CTRL, 23, 24, function_mode); /* FUNC_MODE = DIF */ - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, AFE_CTRL_C2HH_SRC_CTRL, 15, 22, 0xb); /* IF_MODE */ - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, AFE_CTRL_C2HH_SRC_CTRL, 9, 9, 0x1); /* no inv */ - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, AUD_IO_CTRL, 0, 31, 0x00000003); /* 0x124, AUD_CHAN1_SRC = 0x3 */ + status = cx231xx_reg_mask_write(dev, + HAMMERHEAD_I2C_ADDRESS, 32, + AFE_CTRL_C2HH_SRC_CTRL, 30, 31, 0x1); /* lo if big signal */ + status = cx231xx_reg_mask_write(dev, + HAMMERHEAD_I2C_ADDRESS, 32, + AFE_CTRL_C2HH_SRC_CTRL, 23, 24, + function_mode); /* FUNC_MODE = DIF */ + status = cx231xx_reg_mask_write(dev, + HAMMERHEAD_I2C_ADDRESS, 32, + AFE_CTRL_C2HH_SRC_CTRL, 15, 22, 0xb); /* IF_MODE */ + status = cx231xx_reg_mask_write(dev, + HAMMERHEAD_I2C_ADDRESS, 32, + AFE_CTRL_C2HH_SRC_CTRL, 9, 9, 0x1); /* no inv */ + status = cx231xx_reg_mask_write(dev, + HAMMERHEAD_I2C_ADDRESS, 32, + AUD_IO_CTRL, 0, 31, 0x00000003); /* 0x124, AUD_CHAN1_SRC = 0x3 */ break; case V4L2_STD_PAL_B: case V4L2_STD_PAL_G: /* C2HH setup */ - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, AFE_CTRL_C2HH_SRC_CTRL, 30, 31, 0x1); /* lo if big signal */ - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, AFE_CTRL_C2HH_SRC_CTRL, 23, 24, function_mode); /* FUNC_MODE = DIF */ - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, AFE_CTRL_C2HH_SRC_CTRL, 15, 22, 0xE); /* IF_MODE */ - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, AFE_CTRL_C2HH_SRC_CTRL, 9, 9, 0x1); /* no inv */ + status = cx231xx_reg_mask_write(dev, + HAMMERHEAD_I2C_ADDRESS, 32, + AFE_CTRL_C2HH_SRC_CTRL, 30, 31, 0x1); /* lo if big signal */ + status = cx231xx_reg_mask_write(dev, + HAMMERHEAD_I2C_ADDRESS, 32, + AFE_CTRL_C2HH_SRC_CTRL, 23, 24, + function_mode); /* FUNC_MODE = DIF */ + status = cx231xx_reg_mask_write(dev, + HAMMERHEAD_I2C_ADDRESS, 32, + AFE_CTRL_C2HH_SRC_CTRL, 15, 22, 0xE); /* IF_MODE */ + status = cx231xx_reg_mask_write(dev, + HAMMERHEAD_I2C_ADDRESS, 32, + AFE_CTRL_C2HH_SRC_CTRL, 9, 9, 0x1); /* no inv */ break; case V4L2_STD_PAL_D: @@ -1450,10 +1298,19 @@ int cx231xx_dif_configure_C2HH_for_low_IF(struct cx231xx *dev, u32 mode, case V4L2_STD_SECAM_K: case V4L2_STD_SECAM_K1: /* C2HH setup */ - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, AFE_CTRL_C2HH_SRC_CTRL, 30, 31, 0x1); /* lo if big signal */ - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, AFE_CTRL_C2HH_SRC_CTRL, 23, 24, function_mode); /* FUNC_MODE = DIF */ - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, AFE_CTRL_C2HH_SRC_CTRL, 15, 22, 0xF); /* IF_MODE */ - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, AFE_CTRL_C2HH_SRC_CTRL, 9, 9, 0x1); /* no inv */ + status = cx231xx_reg_mask_write(dev, + HAMMERHEAD_I2C_ADDRESS, 32, + AFE_CTRL_C2HH_SRC_CTRL, 30, 31, 0x1); /* lo if big signal */ + status = cx231xx_reg_mask_write(dev, + HAMMERHEAD_I2C_ADDRESS, 32, + AFE_CTRL_C2HH_SRC_CTRL, 23, 24, + function_mode); /* FUNC_MODE = DIF */ + status = cx231xx_reg_mask_write(dev, + HAMMERHEAD_I2C_ADDRESS, 32, + AFE_CTRL_C2HH_SRC_CTRL, 15, 22, 0xF); /* IF_MODE */ + status = cx231xx_reg_mask_write(dev, + HAMMERHEAD_I2C_ADDRESS, 32, + AFE_CTRL_C2HH_SRC_CTRL, 9, 9, 0x1); /* no inv */ break; case DIF_USE_BASEBAND: @@ -1489,20 +1346,18 @@ int cx231xx_dif_set_standard(struct cx231xx *dev, u32 standard) func_mode = 0x01; } - status = - cx231xx_dif_configure_C2HH_for_low_IF(dev, dev->active_mode, + status = cx231xx_dif_configure_C2HH_for_low_IF(dev, dev->active_mode, func_mode, standard); if (standard == DIF_USE_BASEBAND) { /* base band */ - - /* There is a different SRC_PHASE_INC value for baseband vs. DIF */ + /* There is a different SRC_PHASE_INC value + for baseband vs. DIF */ status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, DIF_SRC_PHASE_INC, 2, 0xDF7DF83, 4); - status = - cx231xx_read_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, - DIF_MISC_CTRL, 2, - &dif_misc_ctrl_value, 4); + status = cx231xx_read_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, + DIF_MISC_CTRL, 2, + &dif_misc_ctrl_value, 4); dif_misc_ctrl_value |= FLD_DIF_DIF_BYPASS; status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, DIF_MISC_CTRL, 2, @@ -1510,127 +1365,92 @@ int cx231xx_dif_set_standard(struct cx231xx *dev, u32 standard) } else if (standard & (V4L2_STD_PAL_B | V4L2_STD_PAL_G)) { - status = - cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_PLL_CTRL, 0, 31, 0x6503bc0c); - status = - cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_PLL_CTRL1, 0, 31, 0xbd038c85); - status = - cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_PLL_CTRL2, 0, 31, 0x1db4640a); - status = - cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_PLL_CTRL3, 0, 31, 0x00008800); - status = - cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_AGC_IF_REF, 0, 31, 0x444C1380); - status = - cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_AGC_CTRL_IF, 0, 31, 0xDA302600); - status = - cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_AGC_CTRL_INT, 0, 31, 0xDA261700); - status = - cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_AGC_CTRL_RF, 0, 31, 0xDA262600); - status = - cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_AGC_IF_INT_CURRENT, 0, 31, 0x26001700); - status = - cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_AGC_RF_CURRENT, 0, 31, 0x00002660); - status = - cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_VIDEO_AGC_CTRL, 0, 31, 0x72500800); - status = - cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_VID_AUD_OVERRIDE, 0, 31, 0x27000100); - status = - cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_AV_SEP_CTRL, 0, 31, 0x3F3530EC); - status = - cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_COMP_FLT_CTRL, 0, 31, 0x00A653A8); - status = - cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_SRC_PHASE_INC, 0, 31, 0x1befbf06); - status = - cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_SRC_GAIN_CONTROL, 0, 31, 0x000035e8); - status = - cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_RPT_VARIANCE, 0, 31, 0x00000000); /* Save the Spec Inversion value */ dif_misc_ctrl_value &= FLD_DIF_SPEC_INV; dif_misc_ctrl_value |= 0x3a013F11; } else if (standard & V4L2_STD_PAL_D) { - - status = - cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_PLL_CTRL, 0, 31, 0x6503bc0c); - status = - cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_PLL_CTRL1, 0, 31, 0xbd038c85); - status = - cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_PLL_CTRL2, 0, 31, 0x1db4640a); - status = - cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_PLL_CTRL3, 0, 31, 0x00008800); - status = - cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_AGC_IF_REF, 0, 31, 0x444C1380); - status = - cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_AGC_CTRL_IF, 0, 31, 0xDA302600); - status = - cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_AGC_CTRL_INT, 0, 31, 0xDA261700); - status = - cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_AGC_CTRL_RF, 0, 31, 0xDA262600); - status = - cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_AGC_IF_INT_CURRENT, 0, 31, 0x26001700); - status = - cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_AGC_RF_CURRENT, 0, 31, 0x00002660); - status = - cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_VIDEO_AGC_CTRL, 0, 31, 0x72500800); - status = - cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_VID_AUD_OVERRIDE, 0, 31, 0x27000100); - status = - cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_AV_SEP_CTRL, 0, 31, 0x3F3934EA); - status = - cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_COMP_FLT_CTRL, 0, 31, 0x00000000); - status = - cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_SRC_PHASE_INC, 0, 31, 0x1befbf06); - status = - cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_SRC_GAIN_CONTROL, 0, 31, 0x000035e8); - status = - cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_RPT_VARIANCE, 0, 31, 0x00000000); /* Save the Spec Inversion value */ dif_misc_ctrl_value &= FLD_DIF_SPEC_INV; @@ -1638,116 +1458,86 @@ int cx231xx_dif_set_standard(struct cx231xx *dev, u32 standard) } else if (standard & V4L2_STD_PAL_I) { - status = - cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_PLL_CTRL, 0, 31, 0x6503bc0c); - status = - cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_PLL_CTRL1, 0, 31, 0xbd038c85); - status = - cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_PLL_CTRL2, 0, 31, 0x1db4640a); - status = - cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_PLL_CTRL3, 0, 31, 0x00008800); - status = - cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_AGC_IF_REF, 0, 31, 0x444C1380); - status = - cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_AGC_CTRL_IF, 0, 31, 0xDA302600); - status = - cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_AGC_CTRL_INT, 0, 31, 0xDA261700); - status = - cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_AGC_CTRL_RF, 0, 31, 0xDA262600); - status = - cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_AGC_IF_INT_CURRENT, 0, 31, 0x26001700); - status = - cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_AGC_RF_CURRENT, 0, 31, 0x00002660); - status = - cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_VIDEO_AGC_CTRL, 0, 31, 0x72500800); - status = - cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_VID_AUD_OVERRIDE, 0, 31, 0x27000100); - status = - cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_AV_SEP_CTRL, 0, 31, 0x5F39A934); - status = - cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_COMP_FLT_CTRL, 0, 31, 0x00000000); - status = - cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_SRC_PHASE_INC, 0, 31, 0x1befbf06); - status = - cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_SRC_GAIN_CONTROL, 0, 31, 0x000035e8); - status = - cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_RPT_VARIANCE, 0, 31, 0x00000000); /* Save the Spec Inversion value */ dif_misc_ctrl_value &= FLD_DIF_SPEC_INV; dif_misc_ctrl_value |= 0x3a033F11; } else if (standard & V4L2_STD_PAL_M) { - /* improved Low Frequency Phase Noise */ status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, DIF_PLL_CTRL, 2, 0xFF01FF0C, 4); status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, DIF_PLL_CTRL1, 2, 0xbd038c85, 4); - status = - cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, + status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, DIF_PLL_CTRL2, 2, 0x1db4640a, 4); - status = - cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, + status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, DIF_PLL_CTRL3, 2, 0x00008800, 4); - status = - cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, + status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, DIF_AGC_IF_REF, 2, 0x444C1380, 4); - status = - cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, + status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, DIF_AGC_IF_INT_CURRENT, 2, 0x26001700, 4); - status = - cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, + status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, DIF_AGC_RF_CURRENT, 2, 0x00002660, 4); - status = - cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, + status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, DIF_VIDEO_AGC_CTRL, 2, 0x72500800, 4); - status = - cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, + status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, DIF_VID_AUD_OVERRIDE, 2, 0x27000100, 4); - status = - cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, + status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, DIF_AV_SEP_CTRL, 2, 0x012c405d, 4); - status = - cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, + status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, DIF_COMP_FLT_CTRL, 2, 0x009f50c1, 4); - status = - cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, + status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, DIF_SRC_PHASE_INC, 2, 0x1befbf06, 4); - status = - cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, + status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, DIF_SRC_GAIN_CONTROL, 2, 0x000035e8, 4); - status = - cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, + status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, DIF_SOFT_RST_CTRL_REVB, 2, 0x00000000, 4); @@ -1758,52 +1548,38 @@ int cx231xx_dif_set_standard(struct cx231xx *dev, u32 standard) } else if (standard & (V4L2_STD_PAL_N | V4L2_STD_PAL_Nc)) { /* improved Low Frequency Phase Noise */ - status = - cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, + status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, DIF_PLL_CTRL, 2, 0xFF01FF0C, 4); - status = - cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, + status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, DIF_PLL_CTRL1, 2, 0xbd038c85, 4); - status = - cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, + status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, DIF_PLL_CTRL2, 2, 0x1db4640a, 4); - status = - cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, + status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, DIF_PLL_CTRL3, 2, 0x00008800, 4); - status = - cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, + status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, DIF_AGC_IF_REF, 2, 0x444C1380, 4); - status = - cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, + status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, DIF_AGC_IF_INT_CURRENT, 2, 0x26001700, 4); - status = - cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, + status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, DIF_AGC_RF_CURRENT, 2, 0x00002660, 4); - status = - cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, + status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, DIF_VIDEO_AGC_CTRL, 2, 0x72500800, 4); - status = - cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, + status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, DIF_VID_AUD_OVERRIDE, 2, 0x27000100, 4); - status = - cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, + status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, DIF_AV_SEP_CTRL, 2, 0x012c405d, 4); - status = - cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, + status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, DIF_COMP_FLT_CTRL, 2, 0x009f50c1, 4); - status = - cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, + status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, DIF_SRC_PHASE_INC, 2, 0x1befbf06, 4); - status = - cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, + status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, DIF_SRC_GAIN_CONTROL, 2, 0x000035e8, 4); - status = - cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, + status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, DIF_SOFT_RST_CTRL_REVB, 2, 0x00000000, 4); @@ -1815,62 +1591,45 @@ int cx231xx_dif_set_standard(struct cx231xx *dev, u32 standard) (V4L2_STD_SECAM_B | V4L2_STD_SECAM_D | V4L2_STD_SECAM_G | V4L2_STD_SECAM_K | V4L2_STD_SECAM_K1)) { - status = - cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_PLL_CTRL, 0, 31, 0x6503bc0c); - status = - cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_PLL_CTRL1, 0, 31, 0xbd038c85); - status = - cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_PLL_CTRL2, 0, 31, 0x1db4640a); - status = - cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_PLL_CTRL3, 0, 31, 0x00008800); - status = - cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_AGC_IF_REF, 0, 31, 0x888C0380); - status = - cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_AGC_CTRL_IF, 0, 31, 0xe0262600); - status = - cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_AGC_CTRL_INT, 0, 31, 0xc2171700); - status = - cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_AGC_CTRL_RF, 0, 31, 0xc2262600); - status = - cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_AGC_IF_INT_CURRENT, 0, 31, 0x26001700); - status = - cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_AGC_RF_CURRENT, 0, 31, 0x00002660); - status = - cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_VID_AUD_OVERRIDE, 0, 31, 0x27000100); - status = - cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_AV_SEP_CTRL, 0, 31, 0x3F3530ec); - status = - cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_COMP_FLT_CTRL, 0, 31, 0x00000000); - status = - cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_SRC_PHASE_INC, 0, 31, 0x1befbf06); - status = - cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_SRC_GAIN_CONTROL, 0, 31, 0x000035e8); - status = - cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_RPT_VARIANCE, 0, 31, 0x00000000); - status = - cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_VIDEO_AGC_CTRL, 0, 31, 0xf4000000); @@ -1881,62 +1640,45 @@ int cx231xx_dif_set_standard(struct cx231xx *dev, u32 standard) } else if (standard & (V4L2_STD_SECAM_L | V4L2_STD_SECAM_LC)) { /* Is it SECAM_L1? */ - status = - cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_PLL_CTRL, 0, 31, 0x6503bc0c); - status = - cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_PLL_CTRL1, 0, 31, 0xbd038c85); - status = - cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_PLL_CTRL2, 0, 31, 0x1db4640a); - status = - cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_PLL_CTRL3, 0, 31, 0x00008800); - status = - cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_AGC_IF_REF, 0, 31, 0x888C0380); - status = - cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_AGC_CTRL_IF, 0, 31, 0xe0262600); - status = - cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_AGC_CTRL_INT, 0, 31, 0xc2171700); - status = - cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_AGC_CTRL_RF, 0, 31, 0xc2262600); - status = - cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_AGC_IF_INT_CURRENT, 0, 31, 0x26001700); - status = - cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_AGC_RF_CURRENT, 0, 31, 0x00002660); - status = - cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_VID_AUD_OVERRIDE, 0, 31, 0x27000100); - status = - cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_AV_SEP_CTRL, 0, 31, 0x3F3530ec); - status = - cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_COMP_FLT_CTRL, 0, 31, 0x00000000); - status = - cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_SRC_PHASE_INC, 0, 31, 0x1befbf06); - status = - cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_SRC_GAIN_CONTROL, 0, 31, 0x000035e8); - status = - cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_RPT_VARIANCE, 0, 31, 0x00000000); - status = - cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_VIDEO_AGC_CTRL, 0, 31, 0xf2560000); @@ -1944,67 +1686,54 @@ int cx231xx_dif_set_standard(struct cx231xx *dev, u32 standard) dif_misc_ctrl_value &= FLD_DIF_SPEC_INV; dif_misc_ctrl_value |= 0x3a023F11; - } else { /* V4L2_STD_NTSC_M (75 IRE Setup) Or V4L2_STD_NTSC_M_JP (Japan, 0 IRE Setup) */ + } else { + /* V4L2_STD_NTSC_M (75 IRE Setup) Or + V4L2_STD_NTSC_M_JP (Japan, 0 IRE Setup) */ - /* For NTSC the centre frequency of video coming out of sidewinder is - around 7.1MHz or 3.6MHz depending on the spectral inversion. - so for a non spectrally inverted channel the pll freq word is 0x03420c49 + /* For NTSC the centre frequency of video coming out of + sidewinder is around 7.1MHz or 3.6MHz depending on the + spectral inversion. so for a non spectrally inverted channel + the pll freq word is 0x03420c49 */ - status = - cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, + status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, DIF_PLL_CTRL, 2, 0x6503BC0C, 4); - status = - cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, + status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, DIF_PLL_CTRL1, 2, 0xBD038C85, 4); - status = - cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, + status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, DIF_PLL_CTRL2, 2, 0x1DB4640A, 4); - status = - cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, + status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, DIF_PLL_CTRL3, 2, 0x00008800, 4); - status = - cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, + status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, DIF_AGC_IF_REF, 2, 0x444C0380, 4); - status = - cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, + status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, DIF_AGC_IF_INT_CURRENT, 2, 0x26001700, 4); - status = - cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, + status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, DIF_AGC_RF_CURRENT, 2, 0x00002660, 4); - status = - cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, + status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, DIF_VIDEO_AGC_CTRL, 2, 0x04000800, 4); - status = - cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, + status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, DIF_VID_AUD_OVERRIDE, 2, 0x27000100, 4); - status = - cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, + status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, DIF_AV_SEP_CTRL, 2, 0x01296e1f, 4); - status = - cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, + status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, DIF_COMP_FLT_CTRL, 2, 0x009f50c1, 4); - status = - cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, + status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, DIF_SRC_PHASE_INC, 2, 0x1befbf06, 4); - status = - cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, + status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, DIF_SRC_GAIN_CONTROL, 2, 0x000035e8, 4); - status = - cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, + status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, DIF_AGC_CTRL_IF, 2, 0xC2262600, 4); - status = - cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, + status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, DIF_AGC_CTRL_INT, 2, 0xC2262600, 4); - status = - cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, + status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, DIF_AGC_CTRL_RF, 2, 0xC2262600, 4); /* Save the Spec Inversion value */ @@ -2017,7 +1746,8 @@ int cx231xx_dif_set_standard(struct cx231xx *dev, u32 standard) AUD_SRC_SEL[19] should always be disabled */ dif_misc_ctrl_value &= ~FLD_DIF_AUD_SRC_SEL; - /* It is still possible to get Set Standard calls even when we are in FM mode + /* It is still possible to get Set Standard calls even when we + are in FM mode. This is done to override the value for FM. */ if (dev->active_mode == V4L2_TUNER_RADIO) dif_misc_ctrl_value = 0x7a080000; @@ -2057,12 +1787,11 @@ int cx231xx_tuner_post_channel_change(struct cx231xx *dev) DIF_AGC_IF_REF, 2, &dwval, 4); dwval &= ~(FLD_DIF_K_AGC_RF | FLD_DIF_K_AGC_IF); - if (dev-> - norm & (V4L2_STD_SECAM_L | V4L2_STD_SECAM_B | V4L2_STD_SECAM_D)) { + if (dev->norm & (V4L2_STD_SECAM_L | V4L2_STD_SECAM_B | + V4L2_STD_SECAM_D)) dwval |= 0x88000000; - } else { + else dwval |= 0x44000000; - } status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, DIF_AGC_IF_REF, 2, dwval, 4); @@ -2070,17 +1799,16 @@ int cx231xx_tuner_post_channel_change(struct cx231xx *dev) return status; } -/************************************************************************************* - * F L A T I R O N - B L O C K C O N T R O L functions * - *************************************************************************************/ +/****************************************************************************** + * F L A T I R O N - B L O C K C O N T R O L functions * + ******************************************************************************/ int cx231xx_flatiron_initialize(struct cx231xx *dev) { int status = 0; u32 value; - status = - cx231xx_read_i2c_data(dev, Flatrion_DEVICE_ADDRESS, CH_PWR_CTRL1, 1, - &value, 1); + status = cx231xx_read_i2c_data(dev, Flatrion_DEVICE_ADDRESS, + CH_PWR_CTRL1, 1, &value, 1); /* enables clock to delta-sigma and decimation filter */ value |= 0x80; status = cx231xx_write_i2c_data(dev, Flatrion_DEVICE_ADDRESS, @@ -2098,8 +1826,7 @@ int cx231xx_flatiron_update_power_control(struct cx231xx *dev, AV_MODE avmode) u32 value = 0; if (avmode != POLARIS_AVMODE_ENXTERNAL_AV) { - status = - cx231xx_read_i2c_data(dev, Flatrion_DEVICE_ADDRESS, + status = cx231xx_read_i2c_data(dev, Flatrion_DEVICE_ADDRESS, CH_PWR_CTRL2, 1, &value, 1); value |= 0xfe; status = cx231xx_write_i2c_data(dev, Flatrion_DEVICE_ADDRESS, @@ -2119,7 +1846,6 @@ int cx231xx_flatiron_set_audio_input(struct cx231xx *dev, u8 audio_input) switch (audio_input) { case CX231XX_AMUX_LINE_IN: - status = cx231xx_write_i2c_data(dev, Flatrion_DEVICE_ADDRESS, CH_PWR_CTRL2, 1, 0x00, 1); status = cx231xx_write_i2c_data(dev, Flatrion_DEVICE_ADDRESS, @@ -2135,9 +1861,9 @@ int cx231xx_flatiron_set_audio_input(struct cx231xx *dev, u8 audio_input) return status; } -/************************************************************************************* - * P O W E R C O N T R O L functions * - *************************************************************************************/ +/****************************************************************************** + * P O W E R C O N T R O L functions * + ******************************************************************************/ int cx231xx_set_power_mode(struct cx231xx *dev, AV_MODE mode) { u8 value[4] = { 0, 0, 0, 0 }; @@ -2154,8 +1880,8 @@ int cx231xx_set_power_mode(struct cx231xx *dev, AV_MODE mode) cx231xx_info(" setPowerMode::mode = %d\n", mode); - status = - cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, PWR_CTL_EN, value, 4); + status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, PWR_CTL_EN, value, + 4); if (status < 0) return status; @@ -2171,9 +1897,8 @@ int cx231xx_set_power_mode(struct cx231xx *dev, AV_MODE mode) value[1] = (u8) (tmp >> 8); value[2] = (u8) (tmp >> 16); value[3] = (u8) (tmp >> 24); - status = - cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, PWR_CTL_EN, - value, 4); + status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, + PWR_CTL_EN, value, 4); msleep(PWR_SLEEP_INTERVAL); tmp |= PWR_ISO_EN; @@ -2191,9 +1916,8 @@ int cx231xx_set_power_mode(struct cx231xx *dev, AV_MODE mode) value[1] = (u8) (tmp >> 8); value[2] = (u8) (tmp >> 16); value[3] = (u8) (tmp >> 24); - status = - cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, PWR_CTL_EN, - value, 4); + status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, + PWR_CTL_EN, value, 4); dev->xc_fw_load_done = 0; /* reset state of xceive tuner */ break; @@ -2206,9 +1930,8 @@ int cx231xx_set_power_mode(struct cx231xx *dev, AV_MODE mode) value[1] = (u8) (tmp >> 8); value[2] = (u8) (tmp >> 16); value[3] = (u8) (tmp >> 24); - status = - cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, PWR_CTL_EN, - value, 4); + status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, + PWR_CTL_EN, value, 4); msleep(PWR_SLEEP_INTERVAL); if (!(tmp & PWR_TUNER_EN)) { @@ -2217,9 +1940,8 @@ int cx231xx_set_power_mode(struct cx231xx *dev, AV_MODE mode) value[1] = (u8) (tmp >> 8); value[2] = (u8) (tmp >> 16); value[3] = (u8) (tmp >> 24); - status = - cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, - PWR_CTL_EN, value, 4); + status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, + PWR_CTL_EN, value, 4); msleep(PWR_SLEEP_INTERVAL); } @@ -2229,9 +1951,8 @@ int cx231xx_set_power_mode(struct cx231xx *dev, AV_MODE mode) value[1] = (u8) (tmp >> 8); value[2] = (u8) (tmp >> 16); value[3] = (u8) (tmp >> 24); - status = - cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, - PWR_CTL_EN, value, 4); + status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, + PWR_CTL_EN, value, 4); msleep(PWR_SLEEP_INTERVAL); } if (!(tmp & PWR_ISO_EN)) { @@ -2240,9 +1961,8 @@ int cx231xx_set_power_mode(struct cx231xx *dev, AV_MODE mode) value[1] = (u8) (tmp >> 8); value[2] = (u8) (tmp >> 16); value[3] = (u8) (tmp >> 24); - status = - cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, - PWR_CTL_EN, value, 4); + status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, + PWR_CTL_EN, value, 4); msleep(PWR_SLEEP_INTERVAL); } @@ -2252,15 +1972,13 @@ int cx231xx_set_power_mode(struct cx231xx *dev, AV_MODE mode) value[1] = (u8) (tmp >> 8); value[2] = (u8) (tmp >> 16); value[3] = (u8) (tmp >> 24); - status = - cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, - PWR_CTL_EN, value, 4); + status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, + PWR_CTL_EN, value, 4); msleep(PWR_SLEEP_INTERVAL); } if ((dev->model == CX231XX_BOARD_CNXT_RDE_250) || (dev->model == CX231XX_BOARD_CNXT_RDU_250)) { - /* tuner path to channel 1 from port 3 */ cx231xx_enable_i2c_for_tuner(dev, I2C_3); @@ -2270,16 +1988,14 @@ int cx231xx_set_power_mode(struct cx231xx *dev, AV_MODE mode) break; case POLARIS_AVMODE_DIGITAL: - if (!(tmp & PWR_TUNER_EN)) { tmp |= (PWR_TUNER_EN); value[0] = (u8) tmp; value[1] = (u8) (tmp >> 8); value[2] = (u8) (tmp >> 16); value[3] = (u8) (tmp >> 24); - status = - cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, - PWR_CTL_EN, value, 4); + status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, + PWR_CTL_EN, value, 4); msleep(PWR_SLEEP_INTERVAL); } if (!(tmp & PWR_AV_EN)) { @@ -2288,9 +2004,8 @@ int cx231xx_set_power_mode(struct cx231xx *dev, AV_MODE mode) value[1] = (u8) (tmp >> 8); value[2] = (u8) (tmp >> 16); value[3] = (u8) (tmp >> 24); - status = - cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, - PWR_CTL_EN, value, 4); + status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, + PWR_CTL_EN, value, 4); msleep(PWR_SLEEP_INTERVAL); } if (!(tmp & PWR_ISO_EN)) { @@ -2299,9 +2014,8 @@ int cx231xx_set_power_mode(struct cx231xx *dev, AV_MODE mode) value[1] = (u8) (tmp >> 8); value[2] = (u8) (tmp >> 16); value[3] = (u8) (tmp >> 24); - status = - cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, - PWR_CTL_EN, value, 4); + status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, + PWR_CTL_EN, value, 4); msleep(PWR_SLEEP_INTERVAL); } @@ -2310,9 +2024,8 @@ int cx231xx_set_power_mode(struct cx231xx *dev, AV_MODE mode) value[1] = (u8) (tmp >> 8); value[2] = (u8) (tmp >> 16); value[3] = (u8) (tmp >> 24); - status = - cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, PWR_CTL_EN, - value, 4); + status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, + PWR_CTL_EN, value, 4); msleep(PWR_SLEEP_INTERVAL); if (!(tmp & PWR_DEMOD_EN)) { @@ -2321,15 +2034,13 @@ int cx231xx_set_power_mode(struct cx231xx *dev, AV_MODE mode) value[1] = (u8) (tmp >> 8); value[2] = (u8) (tmp >> 16); value[3] = (u8) (tmp >> 24); - status = - cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, - PWR_CTL_EN, value, 4); + status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, + PWR_CTL_EN, value, 4); msleep(PWR_SLEEP_INTERVAL); } if ((dev->model == CX231XX_BOARD_CNXT_RDE_250) || (dev->model == CX231XX_BOARD_CNXT_RDU_250)) { - /* tuner path to channel 1 from port 3 */ cx231xx_enable_i2c_for_tuner(dev, I2C_3); @@ -2344,16 +2055,16 @@ int cx231xx_set_power_mode(struct cx231xx *dev, AV_MODE mode) msleep(PWR_SLEEP_INTERVAL); - /* For power saving, only enable Pwr_resetout_n when digital TV is selected. */ + /* For power saving, only enable Pwr_resetout_n + when digital TV is selected. */ if (mode == POLARIS_AVMODE_DIGITAL) { tmp |= PWR_RESETOUT_EN; value[0] = (u8) tmp; value[1] = (u8) (tmp >> 8); value[2] = (u8) (tmp >> 16); value[3] = (u8) (tmp >> 24); - status = - cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, PWR_CTL_EN, - value, 4); + status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, + PWR_CTL_EN, value, 4); msleep(PWR_SLEEP_INTERVAL); } @@ -2363,11 +2074,10 @@ int cx231xx_set_power_mode(struct cx231xx *dev, AV_MODE mode) /* update power control for flatiron */ status = cx231xx_flatiron_update_power_control(dev, mode); - status = - cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, PWR_CTL_EN, value, 4); - cx231xx_info - (" The data of PWR_CTL_EN register 0x74=0x%0x,0x%0x,0x%0x,0x%0x\n", - value[0], value[1], value[2], value[3]); + status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, PWR_CTL_EN, value, + 4); + cx231xx_info(" The data of PWR_CTL_EN register 0x74=0x%0x,0x%0x,0x%0x,0x%0x\n", + value[0], value[1], value[2], value[3]); return status; } @@ -2378,8 +2088,8 @@ int cx231xx_power_suspend(struct cx231xx *dev) u32 tmp = 0; int status = 0; - status = - cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, PWR_CTL_EN, value, 4); + status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, PWR_CTL_EN, + value, 4); if (status > 0) return status; @@ -2390,15 +2100,15 @@ int cx231xx_power_suspend(struct cx231xx *dev) value[1] = (u8) (tmp >> 8); value[2] = (u8) (tmp >> 16); value[3] = (u8) (tmp >> 24); - status = - cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, PWR_CTL_EN, value, 4); + status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, PWR_CTL_EN, + value, 4); return status; } -/************************************************************************************* - * S T R E A M C O N T R O L functions * - *************************************************************************************/ +/****************************************************************************** + * S T R E A M C O N T R O L functions * + ******************************************************************************/ int cx231xx_start_stream(struct cx231xx *dev, u32 ep_mask) { u8 value[4] = { 0x0, 0x0, 0x0, 0x0 }; @@ -2406,8 +2116,8 @@ int cx231xx_start_stream(struct cx231xx *dev, u32 ep_mask) int status = 0; cx231xx_info("cx231xx_start_stream():: ep_mask = %x\n", ep_mask); - status = - cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, EP_MODE_SET, value, 4); + status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, EP_MODE_SET, + value, 4); if (status < 0) return status; @@ -2418,9 +2128,8 @@ int cx231xx_start_stream(struct cx231xx *dev, u32 ep_mask) value[2] = (u8) (tmp >> 16); value[3] = (u8) (tmp >> 24); - status = - cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, EP_MODE_SET, value, - 4); + status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, EP_MODE_SET, + value, 4); return status; } @@ -2444,9 +2153,8 @@ int cx231xx_stop_stream(struct cx231xx *dev, u32 ep_mask) value[2] = (u8) (tmp >> 16); value[3] = (u8) (tmp >> 24); - status = - cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, EP_MODE_SET, value, - 4); + status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, EP_MODE_SET, + value, 4); return status; } @@ -2558,9 +2266,8 @@ int cx231xx_capture_start(struct cx231xx *dev, int start, u8 media_type) if (start) { rc = cx231xx_initialize_stream_xfer(dev, media_type); - if (rc < 0) { + if (rc < 0) return rc; - } /* enable video capture */ if (ep_mask > 0) @@ -2571,20 +2278,21 @@ int cx231xx_capture_start(struct cx231xx *dev, int start, u8 media_type) rc = cx231xx_stop_stream(dev, ep_mask); } +#if 0 if (dev->mode == CX231XX_ANALOG_MODE) { /* do any in Analog mode */ } else { /* do any in digital mode */ } +#endif return rc; } - EXPORT_SYMBOL_GPL(cx231xx_capture_start); -/************************************************************************************ -* G P I O B I T control functions * -*************************************************************************************/ +/***************************************************************************** +* G P I O B I T control functions * +******************************************************************************/ int cx231xx_set_gpio_bit(struct cx231xx *dev, u32 gpio_bit, u8 * gpio_val) { int status = 0; @@ -2621,17 +2329,16 @@ int cx231xx_set_gpio_direction(struct cx231xx *dev, u32 value = 0; /* Check for valid pin_number - if 32 , bail out */ - if (pin_number >= 32) { + if (pin_number >= 32) return -EINVAL; - } - if (pin_value == 0) { /* input */ + /* input */ + if (pin_value == 0) value = dev->gpio_dir & (~(1 << pin_number)); /* clear */ - } else { + else value = dev->gpio_dir | (1 << pin_number); - } - status = cx231xx_set_gpio_bit(dev, value, (u8 *) & dev->gpio_val); + status = cx231xx_set_gpio_bit(dev, value, (u8 *) &dev->gpio_val); /* cache the value for future */ dev->gpio_dir = value; @@ -2664,31 +2371,28 @@ int cx231xx_set_gpio_value(struct cx231xx *dev, int pin_number, int pin_value) /* It was in input mode */ value = dev->gpio_dir | (1 << pin_number); dev->gpio_dir = value; - status = - cx231xx_set_gpio_bit(dev, dev->gpio_dir, - (u8 *) & dev->gpio_val); + status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, + (u8 *) &dev->gpio_val); value = 0; } - if (pin_value == 0) { + if (pin_value == 0) value = dev->gpio_val & (~(1 << pin_number)); - } else { + else value = dev->gpio_val | (1 << pin_number); - } /* store the value */ dev->gpio_val = value; /* toggle bit0 of GP_IO */ - status = - cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *) & dev->gpio_val); + status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val); return status; } -/************************************************************************************ -* G P I O I2C related functions * -*************************************************************************************/ +/***************************************************************************** +* G P I O I2C related functions * +******************************************************************************/ int cx231xx_gpio_i2c_start(struct cx231xx *dev) { int status = 0; @@ -2699,31 +2403,25 @@ int cx231xx_gpio_i2c_start(struct cx231xx *dev) dev->gpio_val |= 1 << dev->board.tuner_scl_gpio; dev->gpio_val |= 1 << dev->board.tuner_sda_gpio; - status = - cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *) & dev->gpio_val); - if (status < 0) { + status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val); + if (status < 0) return -EINVAL; - } /* set SCL to output 1; set SDA to output 0 */ dev->gpio_val |= 1 << dev->board.tuner_scl_gpio; dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio); - status = - cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *) & dev->gpio_val); - if (status < 0) { + status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val); + if (status < 0) return -EINVAL; - } /* set SCL to output 0; set SDA to output 0 */ dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio); dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio); - status = - cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *) & dev->gpio_val); - if (status < 0) { + status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val); + if (status < 0) return -EINVAL; - } return status; } @@ -2739,21 +2437,17 @@ int cx231xx_gpio_i2c_end(struct cx231xx *dev) dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio); dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio); - status = - cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *) & dev->gpio_val); - if (status < 0) { + status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val); + if (status < 0) return -EINVAL; - } /* set SCL to output 1; set SDA to output 0 */ dev->gpio_val |= 1 << dev->board.tuner_scl_gpio; dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio); - status = - cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *) & dev->gpio_val); - if (status < 0) { + status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val); + if (status < 0) return -EINVAL; - } /* set SCL to input ,release SCL cable control set SDA to input ,release SDA cable control */ @@ -2761,10 +2455,10 @@ int cx231xx_gpio_i2c_end(struct cx231xx *dev) dev->gpio_dir &= ~(1 << dev->board.tuner_sda_gpio); status = - cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *) & dev->gpio_val); - if (status < 0) { + cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val); + if (status < 0) return -EINVAL; - } + return status; } @@ -2782,40 +2476,34 @@ int cx231xx_gpio_i2c_write_byte(struct cx231xx *dev, u8 data) /* set SCL to output 0; set SDA to output 0 */ dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio); dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio); - status = - cx231xx_set_gpio_bit(dev, dev->gpio_dir, - (u8 *) & dev->gpio_val); + status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, + (u8 *)&dev->gpio_val); /* set SCL to output 1; set SDA to output 0 */ dev->gpio_val |= 1 << dev->board.tuner_scl_gpio; - status = - cx231xx_set_gpio_bit(dev, dev->gpio_dir, - (u8 *) & dev->gpio_val); + status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, + (u8 *)&dev->gpio_val); /* set SCL to output 0; set SDA to output 0 */ dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio); - status = - cx231xx_set_gpio_bit(dev, dev->gpio_dir, - (u8 *) & dev->gpio_val); + status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, + (u8 *)&dev->gpio_val); } else { /* set SCL to output 0; set SDA to output 1 */ dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio); dev->gpio_val |= 1 << dev->board.tuner_sda_gpio; - status = - cx231xx_set_gpio_bit(dev, dev->gpio_dir, - (u8 *) & dev->gpio_val); + status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, + (u8 *)&dev->gpio_val); /* set SCL to output 1; set SDA to output 1 */ dev->gpio_val |= 1 << dev->board.tuner_scl_gpio; - status = - cx231xx_set_gpio_bit(dev, dev->gpio_dir, - (u8 *) & dev->gpio_val); + status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, + (u8 *)&dev->gpio_val); /* set SCL to output 0; set SDA to output 1 */ dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio); - status = - cx231xx_set_gpio_bit(dev, dev->gpio_dir, - (u8 *) & dev->gpio_val); + status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, + (u8 *)&dev->gpio_val); } } return status; @@ -2833,33 +2521,29 @@ int cx231xx_gpio_i2c_read_byte(struct cx231xx *dev, u8 * buf) /* set SCL to output 0; set SDA to input */ dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio); - status = - cx231xx_set_gpio_bit(dev, dev->gpio_dir, - (u8 *) & dev->gpio_val); + status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, + (u8 *)&dev->gpio_val); /* set SCL to output 1; set SDA to input */ dev->gpio_val |= 1 << dev->board.tuner_scl_gpio; - status = - cx231xx_set_gpio_bit(dev, dev->gpio_dir, - (u8 *) & dev->gpio_val); + status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, + (u8 *)&dev->gpio_val); /* get SDA data bit */ gpio_logic_value = dev->gpio_val; - status = - cx231xx_get_gpio_bit(dev, dev->gpio_dir, - (u8 *) & dev->gpio_val); - if ((dev->gpio_val & (1 << dev->board.tuner_sda_gpio)) != 0) { + status = cx231xx_get_gpio_bit(dev, dev->gpio_dir, + (u8 *)&dev->gpio_val); + if ((dev->gpio_val & (1 << dev->board.tuner_sda_gpio)) != 0) value |= (1 << (8 - i - 1)); - } dev->gpio_val = gpio_logic_value; } /* set SCL to output 0,finish the read latest SCL signal. - !!!set SDA to input,never to modify SDA direction at the same times */ + !!!set SDA to input, never to modify SDA direction at + the same times */ dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio); - status = - cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *) & dev->gpio_val); + status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val); /* store the value */ *buf = value & 0xff; @@ -2874,33 +2558,29 @@ int cx231xx_gpio_i2c_read_ack(struct cx231xx *dev) int nCnt = 10; int nInit = nCnt; - /* clock stretch; set SCL to input; set SDA to input; get SCL value till SCL = 1 */ + /* clock stretch; set SCL to input; set SDA to input; + get SCL value till SCL = 1 */ dev->gpio_dir &= ~(1 << dev->board.tuner_sda_gpio); dev->gpio_dir &= ~(1 << dev->board.tuner_scl_gpio); gpio_logic_value = dev->gpio_val; - status = - cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *) & dev->gpio_val); + status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val); do { msleep(2); - status = - cx231xx_get_gpio_bit(dev, dev->gpio_dir, - (u8 *) & dev->gpio_val); + status = cx231xx_get_gpio_bit(dev, dev->gpio_dir, + (u8 *)&dev->gpio_val); nCnt--; - } while (((dev->gpio_val & (1 << dev->board.tuner_scl_gpio)) == 0) - && (nCnt > 0)); + } while (((dev->gpio_val & (1 << dev->board.tuner_scl_gpio)) == 0) && (nCnt > 0)); - if (nCnt == 0) { - cx231xx_info - ("No ACK after %d msec for clock stretch. GPIO I2C operation failed!", - nInit * 10); - } + if (nCnt == 0) + cx231xx_info("No ACK after %d msec for clock stretch. GPIO I2C operation failed!", + nInit * 10); /* readAck - throuth clock stretch ,slave has given a SCL signal,so the SDA data can be directly read. */ - status = - cx231xx_get_gpio_bit(dev, dev->gpio_dir, (u8 *) & dev->gpio_val); + throuth clock stretch ,slave has given a SCL signal, + so the SDA data can be directly read. */ + status = cx231xx_get_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val); if ((dev->gpio_val & 1 << dev->board.tuner_sda_gpio) == 0) { dev->gpio_val = gpio_logic_value; @@ -2911,12 +2591,12 @@ int cx231xx_gpio_i2c_read_ack(struct cx231xx *dev) dev->gpio_val |= (1 << dev->board.tuner_sda_gpio); } - /* read SDA end, set the SCL to output 0, after this operation, SDA direction can be changed. */ + /* read SDA end, set the SCL to output 0, after this operation, + SDA direction can be changed. */ dev->gpio_val = gpio_logic_value; dev->gpio_dir |= (1 << dev->board.tuner_scl_gpio); dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio); - status = - cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *) & dev->gpio_val); + status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val); return status; } @@ -2927,29 +2607,24 @@ int cx231xx_gpio_i2c_write_ack(struct cx231xx *dev) /* set SDA to ouput */ dev->gpio_dir |= 1 << dev->board.tuner_sda_gpio; - status = - cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *) & dev->gpio_val); + status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val); /* set SCL = 0 (output); set SDA = 0 (output) */ dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio); dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio); - status = - cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *) & dev->gpio_val); + status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val); /* set SCL = 1 (output); set SDA = 0 (output) */ dev->gpio_val |= 1 << dev->board.tuner_scl_gpio; - status = - cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *) & dev->gpio_val); + status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val); /* set SCL = 0 (output); set SDA = 0 (output) */ dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio); - status = - cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *) & dev->gpio_val); + status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val); /* set SDA to input,and then the slave will read data from SDA. */ dev->gpio_dir &= ~(1 << dev->board.tuner_sda_gpio); - status = - cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *) & dev->gpio_val); + status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val); return status; } @@ -2961,25 +2636,22 @@ int cx231xx_gpio_i2c_write_nak(struct cx231xx *dev) /* set scl to output ; set sda to input */ dev->gpio_dir |= 1 << dev->board.tuner_scl_gpio; dev->gpio_dir &= ~(1 << dev->board.tuner_sda_gpio); - status = - cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *) & dev->gpio_val); + status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val); /* set scl to output 0; set sda to input */ dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio); - status = - cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *) & dev->gpio_val); + status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val); /* set scl to output 1; set sda to input */ dev->gpio_val |= 1 << dev->board.tuner_scl_gpio; - status = - cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *) & dev->gpio_val); + status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val); return status; } -/************************************************************************************ -* G P I O I2C related functions * -*************************************************************************************/ +/***************************************************************************** +* G P I O I2C related functions * +******************************************************************************/ /* cx231xx_gpio_i2c_read * Function to read data from gpio based I2C interface */ -- cgit v1.2.3 From 688b148d5028295349c3cd5c14cf539fd46a58a5 Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Wed, 4 Mar 2009 17:49:01 -0300 Subject: cx231xx: Fix CodingStyle From: Sri Deevi Fixes several CodingStyle issues on the driver. Signed-off-by: Srinivasa Deevi Signed-off-by: Mauro Carvalho Chehab --- linux/drivers/media/video/cx231xx/cx231xx-avcore.c | 179 +++++++++++++-------- 1 file changed, 112 insertions(+), 67 deletions(-) (limited to 'linux/drivers/media/video/cx231xx/cx231xx-avcore.c') diff --git a/linux/drivers/media/video/cx231xx/cx231xx-avcore.c b/linux/drivers/media/video/cx231xx/cx231xx-avcore.c index 6eb63d078..8bbe518f4 100644 --- a/linux/drivers/media/video/cx231xx/cx231xx-avcore.c +++ b/linux/drivers/media/video/cx231xx/cx231xx-avcore.c @@ -74,12 +74,14 @@ int cx231xx_colibri_init_super_block(struct cx231xx *dev, u32 ref_count) &colibri_power_status, 1); colibri_power_status &= 0xff; if (status < 0) { - cx231xx_info(": Init Super Block failed in sending/receiving cmds\n"); + cx231xx_info( + ": Init Super Block failed in send/receive cmds\n"); break; } i++; if (i == 10) { - cx231xx_info(": Init Super Block force break in loop !!!!\n"); + cx231xx_info( + ": Init Super Block force break in loop !!!!\n"); status = -1; break; } @@ -258,7 +260,8 @@ int cx231xx_colibri_set_mode(struct cx231xx *dev, enum AFE_MODE mode) break; } - if ((mode != dev->colibri_mode) && (dev->video_input == CX231XX_VMUX_TELEVISION)) + if ((mode != dev->colibri_mode) && + (dev->video_input == CX231XX_VMUX_TELEVISION)) status = cx231xx_colibri_adjust_ref_count(dev, CX231XX_VMUX_TELEVISION); @@ -511,8 +514,9 @@ int cx231xx_set_video_input_mux(struct cx231xx *dev, u8 input) status = cx231xx_set_power_mode(dev, POLARIS_AVMODE_ENXTERNAL_AV); if (status < 0) { - cx231xx_errdev("%s: cx231xx_set_power_mode : Failed to set Power - errCode [%d]!\n", - __func__, status); + cx231xx_errdev("%s: set_power_mode : Failed to" + " set Power - errCode [%d]!\n", + __func__, status); return status; } } @@ -528,8 +532,9 @@ int cx231xx_set_video_input_mux(struct cx231xx *dev, u8 input) status = cx231xx_set_power_mode(dev, POLARIS_AVMODE_ANALOGT_TV); if (status < 0) { - cx231xx_errdev("%s: cx231xx_set_power_mode : Failed to set Power - errCode [%d]!\n", - __func__, status); + cx231xx_errdev("%s: set_power_mode:Failed" + " to set Power - errCode [%d]!\n", + __func__, status); return status; } } @@ -538,7 +543,7 @@ int cx231xx_set_video_input_mux(struct cx231xx *dev, u8 input) INPUT(input)->vmux); break; default: - cx231xx_errdev("%s: cx231xx_set_power_mode : Unknown Input %d !\n", + cx231xx_errdev("%s: set_power_mode : Unknown Input %d !\n", __func__, INPUT(input)->type); break; } @@ -549,7 +554,8 @@ int cx231xx_set_video_input_mux(struct cx231xx *dev, u8 input) return status; } -int cx231xx_set_decoder_video_input(struct cx231xx *dev, u8 pin_type, u8 input) +int cx231xx_set_decoder_video_input(struct cx231xx *dev, + u8 pin_type, u8 input) { int status = 0; u32 value = 0; @@ -557,8 +563,9 @@ int cx231xx_set_decoder_video_input(struct cx231xx *dev, u8 pin_type, u8 input) if (pin_type != dev->video_input) { status = cx231xx_colibri_adjust_ref_count(dev, pin_type); if (status < 0) { - cx231xx_errdev("%s: cx231xx_colibri_adjust_ref_count :Failed to set Colibri input mux - errCode [%d]!\n", - __func__, status); + cx231xx_errdev("%s: adjust_ref_count :Failed to set" + "Colibri input mux - errCode [%d]!\n", + __func__, status); return status; } } @@ -566,8 +573,9 @@ int cx231xx_set_decoder_video_input(struct cx231xx *dev, u8 pin_type, u8 input) /* call colibri block to set video inputs */ status = cx231xx_colibri_set_input_mux(dev, input); if (status < 0) { - cx231xx_errdev("%s: cx231xx_colibri_set_input_mux :Failed to set Colibri input mux - errCode [%d]!\n", - __func__, status); + cx231xx_errdev("%s: set_input_mux :Failed to set" + " Colibri input mux - errCode [%d]!\n", + __func__, status); return status; } @@ -579,8 +587,10 @@ int cx231xx_set_decoder_video_input(struct cx231xx *dev, u8 pin_type, u8 input) value |= (0 << 13) | (1 << 4); value &= ~(1 << 5); - value &= (~(0x1ff8000)); /* set [24:23] [22:15] to 0 */ - value |= 0x1000000; /* set FUNC_MODE[24:23] = 2 IF_MOD[22:15] = 0 */ + /* set [24:23] [22:15] to 0 */ + value &= (~(0x1ff8000)); + /* set FUNC_MODE[24:23] = 2 IF_MOD[22:15] = 0 */ + value |= 0x1000000; status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, AFE_CTRL, 2, value, 4); @@ -600,7 +610,8 @@ int cx231xx_set_decoder_video_input(struct cx231xx *dev, u8 pin_type, u8 input) /* Tell DIF object to go to baseband mode */ status = cx231xx_dif_set_standard(dev, DIF_USE_BASEBAND); if (status < 0) { - cx231xx_errdev("%s: cx231xx_dif set to By pass mode - errCode [%d]!\n", + cx231xx_errdev("%s: cx231xx_dif set to By pass" + " mode- errCode [%d]!\n", __func__, status); return status; } @@ -637,9 +648,11 @@ int cx231xx_set_decoder_video_input(struct cx231xx *dev, u8 pin_type, u8 input) status = cx231xx_read_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, AFE_CTRL, 2, &value, 4); - value &= (~(0x1ff8000)); /* set [24:23] [22:15] to 0 */ - value |= 0x1000010; /* set FUNC_MODE[24:23] = 2 - IF_MOD[22:15] = 0 DCR_BYP_CH2[4:4] = 1; */ + /* set [24:23] [22:15] to 0 */ + value &= (~(0x1ff8000)); + /* set FUNC_MODE[24:23] = 2 + IF_MOD[22:15] = 0 DCR_BYP_CH2[4:4] = 1; */ + value |= 0x1000010; status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, AFE_CTRL, 2, value, 4); @@ -647,7 +660,8 @@ int cx231xx_set_decoder_video_input(struct cx231xx *dev, u8 pin_type, u8 input) /* Tell DIF object to go to baseband mode */ status = cx231xx_dif_set_standard(dev, DIF_USE_BASEBAND); if (status < 0) { - cx231xx_errdev("%s: cx231xx_dif set to By pass mode - errCode [%d]!\n", + cx231xx_errdev("%s: cx231xx_dif set to By pass" + " mode- errCode [%d]!\n", __func__, status); return status; } @@ -713,8 +727,10 @@ int cx231xx_set_decoder_video_input(struct cx231xx *dev, u8 pin_type, u8 input) value |= (0 << 13) | (1 << 4); value &= ~(1 << 5); - value &= (~(0x1FF8000)); /* set [24:23] [22:15] to 0 */ - value |= 0x1000000; /* set FUNC_MODE[24:23] = 2 IF_MOD[22:15] = 0 */ + /* set [24:23] [22:15] to 0 */ + value &= (~(0x1FF8000)); + /* set FUNC_MODE[24:23] = 2 IF_MOD[22:15] = 0 */ + value |= 0x1000000; status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, AFE_CTRL, 2, @@ -740,8 +756,9 @@ int cx231xx_set_decoder_video_input(struct cx231xx *dev, u8 pin_type, u8 input) status = cx231xx_dif_set_standard(dev, DIF_USE_BASEBAND); if (status < 0) { - cx231xx_errdev("%s: cx231xx_dif set to By pass mode - errCode [%d]!\n", - __func__, status); + cx231xx_errdev("%s: cx231xx_dif set to By pass" + " mode- errCode [%d]!\n", + __func__, status); return status; } @@ -773,7 +790,8 @@ int cx231xx_set_decoder_video_input(struct cx231xx *dev, u8 pin_type, u8 input) status = cx231xx_read_modify_write_i2c_dword(dev, HAMMERHEAD_I2C_ADDRESS, MODE_CTRL, FLD_INPUT_MODE, - cx231xx_set_field(FLD_INPUT_MODE, INPUT_MODE_CVBS_0)); + cx231xx_set_field(FLD_INPUT_MODE, + INPUT_MODE_CVBS_0)); break; default: /* Enable the DIF for the tuner */ @@ -781,8 +799,9 @@ int cx231xx_set_decoder_video_input(struct cx231xx *dev, u8 pin_type, u8 input) /* Reinitialize the DIF */ status = cx231xx_dif_set_standard(dev, dev->norm); if (status < 0) { - cx231xx_errdev("%s: cx231xx_dif set to By pass mode - errCode [%d]!\n", - __func__, status); + cx231xx_errdev("%s: cx231xx_dif set to By pass" + " mode- errCode [%d]!\n", + __func__, status); return status; } @@ -861,9 +880,11 @@ int cx231xx_set_decoder_video_input(struct cx231xx *dev, u8 pin_type, u8 input) status = cx231xx_read_modify_write_i2c_dword(dev, HAMMERHEAD_I2C_ADDRESS, MODE_CTRL, FLD_INPUT_MODE, - cx231xx_set_field(FLD_INPUT_MODE, INPUT_MODE_CVBS_0)); + cx231xx_set_field(FLD_INPUT_MODE, + INPUT_MODE_CVBS_0)); - /* Set some bits in AFE_CTRL so that channel 2 or 3 is ready to receive audio */ + /* Set some bits in AFE_CTRL so that channel 2 or 3 + * is ready to receive audio */ /* Clear clamp for channels 2 and 3 (bit 16-17) */ /* Clear droop comp (bit 19-20) */ /* Set VGA_SEL (for audio control) (bit 7-8) */ @@ -903,8 +924,9 @@ int cx231xx_set_decoder_video_input(struct cx231xx *dev, u8 pin_type, u8 input) } /* - * Handle any video-mode specific overrides that are different on a per video standards - * basis after touching the MODE_CTRL register which resets many values for autodetect + * Handle any video-mode specific overrides that are different + * on a per video standards basis after touching the MODE_CTRL + * register which resets many values for autodetect */ int cx231xx_do_mode_ctrl_overrides(struct cx231xx *dev) { @@ -918,7 +940,8 @@ int cx231xx_do_mode_ctrl_overrides(struct cx231xx *dev) DFE_CTRL3, 2, 0xCD3F0280, 4); - if (dev->norm & (V4L2_STD_NTSC_M | V4L2_STD_NTSC_M_JP | V4L2_STD_PAL_M)) { + if (dev->norm & (V4L2_STD_NTSC_M | V4L2_STD_NTSC_M_JP | + V4L2_STD_PAL_M)) { cx231xx_info("do_mode_ctrl_overrides NTSC\n"); /* Move the close caption lines out of active video, @@ -1237,55 +1260,72 @@ int cx231xx_dif_configure_C2HH_for_low_IF(struct cx231xx *dev, u32 mode, if (mode == V4L2_TUNER_RADIO) { /* C2HH */ - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, - AFE_CTRL_C2HH_SRC_CTRL, 30, 31, 0x1); /* lo if big signal */ - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, - AFE_CTRL_C2HH_SRC_CTRL, 23, 24, function_mode); /* FUNC_MODE = DIF */ - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, - AFE_CTRL_C2HH_SRC_CTRL, 15, 22, 0xFF); /* IF_MODE */ - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, - AFE_CTRL_C2HH_SRC_CTRL, 9, 9, 0x1); /* no inv */ + /* lo if big signal */ + status = cx231xx_reg_mask_write(dev, + HAMMERHEAD_I2C_ADDRESS, 32, + AFE_CTRL_C2HH_SRC_CTRL, 30, 31, 0x1); + /* FUNC_MODE = DIF */ + status = cx231xx_reg_mask_write(dev, + HAMMERHEAD_I2C_ADDRESS, 32, + AFE_CTRL_C2HH_SRC_CTRL, 23, 24, function_mode); + /* IF_MODE */ + status = cx231xx_reg_mask_write(dev, + HAMMERHEAD_I2C_ADDRESS, 32, + AFE_CTRL_C2HH_SRC_CTRL, 15, 22, 0xFF); + /* no inv */ + status = cx231xx_reg_mask_write(dev, + HAMMERHEAD_I2C_ADDRESS, 32, + AFE_CTRL_C2HH_SRC_CTRL, 9, 9, 0x1); } else { switch (standard) { case V4L2_STD_NTSC_M: /* 75 IRE Setup */ - case V4L2_STD_NTSC_M_JP: /* Japan, 0 IRE Setup */ + case V4L2_STD_NTSC_M_JP:/* Japan, 0 IRE Setup */ case V4L2_STD_PAL_M: case V4L2_STD_PAL_N: case V4L2_STD_PAL_Nc: + /* lo if big signal */ status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, - AFE_CTRL_C2HH_SRC_CTRL, 30, 31, 0x1); /* lo if big signal */ + AFE_CTRL_C2HH_SRC_CTRL, 30, 31, 0x1); + /* FUNC_MODE = DIF */ status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, AFE_CTRL_C2HH_SRC_CTRL, 23, 24, - function_mode); /* FUNC_MODE = DIF */ + function_mode); + /* IF_MODE */ status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, - AFE_CTRL_C2HH_SRC_CTRL, 15, 22, 0xb); /* IF_MODE */ + AFE_CTRL_C2HH_SRC_CTRL, 15, 22, 0xb); + /* no inv */ status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, - AFE_CTRL_C2HH_SRC_CTRL, 9, 9, 0x1); /* no inv */ + AFE_CTRL_C2HH_SRC_CTRL, 9, 9, 0x1); + /* 0x124, AUD_CHAN1_SRC = 0x3 */ status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, - AUD_IO_CTRL, 0, 31, 0x00000003); /* 0x124, AUD_CHAN1_SRC = 0x3 */ + AUD_IO_CTRL, 0, 31, 0x00000003); break; case V4L2_STD_PAL_B: case V4L2_STD_PAL_G: /* C2HH setup */ + /* lo if big signal */ status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, - AFE_CTRL_C2HH_SRC_CTRL, 30, 31, 0x1); /* lo if big signal */ + AFE_CTRL_C2HH_SRC_CTRL, 30, 31, 0x1); + /* FUNC_MODE = DIF */ status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, AFE_CTRL_C2HH_SRC_CTRL, 23, 24, - function_mode); /* FUNC_MODE = DIF */ + function_mode); + /* IF_MODE */ status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, - AFE_CTRL_C2HH_SRC_CTRL, 15, 22, 0xE); /* IF_MODE */ + AFE_CTRL_C2HH_SRC_CTRL, 15, 22, 0xE); + /* no inv */ status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, - AFE_CTRL_C2HH_SRC_CTRL, 9, 9, 0x1); /* no inv */ + AFE_CTRL_C2HH_SRC_CTRL, 9, 9, 0x1); break; case V4L2_STD_PAL_D: @@ -1298,19 +1338,23 @@ int cx231xx_dif_configure_C2HH_for_low_IF(struct cx231xx *dev, u32 mode, case V4L2_STD_SECAM_K: case V4L2_STD_SECAM_K1: /* C2HH setup */ + /* lo if big signal */ status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, - AFE_CTRL_C2HH_SRC_CTRL, 30, 31, 0x1); /* lo if big signal */ + AFE_CTRL_C2HH_SRC_CTRL, 30, 31, 0x1); + /* FUNC_MODE = DIF */ status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, AFE_CTRL_C2HH_SRC_CTRL, 23, 24, - function_mode); /* FUNC_MODE = DIF */ + function_mode); + /* IF_MODE */ status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, - AFE_CTRL_C2HH_SRC_CTRL, 15, 22, 0xF); /* IF_MODE */ + AFE_CTRL_C2HH_SRC_CTRL, 15, 22, 0xF); + /* no inv */ status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, - AFE_CTRL_C2HH_SRC_CTRL, 9, 9, 0x1); /* no inv */ + AFE_CTRL_C2HH_SRC_CTRL, 9, 9, 0x1); break; case DIF_USE_BASEBAND: @@ -1919,7 +1963,8 @@ int cx231xx_set_power_mode(struct cx231xx *dev, AV_MODE mode) status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, PWR_CTL_EN, value, 4); - dev->xc_fw_load_done = 0; /* reset state of xceive tuner */ + /* reset state of xceive tuner */ + dev->xc_fw_load_done = 0; break; case POLARIS_AVMODE_ANALOGT_TV: @@ -2076,7 +2121,8 @@ int cx231xx_set_power_mode(struct cx231xx *dev, AV_MODE mode) status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, PWR_CTL_EN, value, 4); - cx231xx_info(" The data of PWR_CTL_EN register 0x74=0x%0x,0x%0x,0x%0x,0x%0x\n", + cx231xx_info(" The data of PWR_CTL_EN register 0x74" + "=0x%0x,0x%0x,0x%0x,0x%0x\n", value[0], value[1], value[2], value[3]); return status; @@ -2210,10 +2256,10 @@ int cx231xx_capture_start(struct cx231xx *dev, int start, u8 media_type) { int rc; u32 ep_mask = -1; - PPCB_CONFIG pcb_config; + struct pcb_config *pcb_config; /* get EP for media type */ - pcb_config = &dev->current_pcb_config; + pcb_config = (struct pcb_config *)&dev->current_pcb_config; if (pcb_config->config_num == 1) { switch (media_type) { @@ -2278,13 +2324,10 @@ int cx231xx_capture_start(struct cx231xx *dev, int start, u8 media_type) rc = cx231xx_stop_stream(dev, ep_mask); } -#if 0 - if (dev->mode == CX231XX_ANALOG_MODE) { - /* do any in Analog mode */ - } else { - /* do any in digital mode */ - } -#endif + if (dev->mode == CX231XX_ANALOG_MODE) + ;/* do any in Analog mode */ + else + ;/* do any in digital mode */ return rc; } @@ -2571,10 +2614,12 @@ int cx231xx_gpio_i2c_read_ack(struct cx231xx *dev) status = cx231xx_get_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val); nCnt--; - } while (((dev->gpio_val & (1 << dev->board.tuner_scl_gpio)) == 0) && (nCnt > 0)); + } while (((dev->gpio_val & + (1 << dev->board.tuner_scl_gpio)) == 0) && + (nCnt > 0)); if (nCnt == 0) - cx231xx_info("No ACK after %d msec for clock stretch. GPIO I2C operation failed!", + cx231xx_info("No ACK after %d msec -GPIO I2C failed!", nInit * 10); /* readAck -- cgit v1.2.3 From 24633f3642291c4afb7f6839f0d7e2c1ea7c2be1 Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Tue, 10 Mar 2009 21:16:26 -0300 Subject: Some additional CodingStyle and minor fixes From: Srinivasa Deevi > changed the pcb-config.c/h to pcb-cfg.c/h for short names. Signed-off-by: Srinivasa Deevi > Signed-off-by: Mauro Carvalho Chehab --- linux/drivers/media/video/cx231xx/cx231xx-avcore.c | 305 +++++++++++---------- 1 file changed, 153 insertions(+), 152 deletions(-) (limited to 'linux/drivers/media/video/cx231xx/cx231xx-avcore.c') diff --git a/linux/drivers/media/video/cx231xx/cx231xx-avcore.c b/linux/drivers/media/video/cx231xx/cx231xx-avcore.c index 8bbe518f4..226299d62 100644 --- a/linux/drivers/media/video/cx231xx/cx231xx-avcore.c +++ b/linux/drivers/media/video/cx231xx/cx231xx-avcore.c @@ -41,7 +41,7 @@ /****************************************************************************** * C O L I B R I - B L O C K C O N T R O L functions * - ********************************************************************* ********/ + ******************************************************************************/ int cx231xx_colibri_init_super_block(struct cx231xx *dev, u32 ref_count) { int status = 0; @@ -53,29 +53,44 @@ int cx231xx_colibri_init_super_block(struct cx231xx *dev, u32 ref_count) temp = (u8) (ref_count & 0xff); status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, SUP_BLK_TUNE2, 2, temp, 1); + if (status < 0) + return status; status = cx231xx_read_i2c_data(dev, Colibri_DEVICE_ADDRESS, SUP_BLK_TUNE2, 2, &colibri_power_status, 1); + if (status < 0) + return status; temp = (u8) ((ref_count & 0x300) >> 8); temp |= 0x40; status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, SUP_BLK_TUNE1, 2, temp, 1); + if (status < 0) + return status; + status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, SUP_BLK_PLL2, 2, 0x0f, 1); + if (status < 0) + return status; /* enable pll */ while (colibri_power_status != 0x18) { status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, SUP_BLK_PWRDN, 2, 0x18, 1); + if (status < 0) { + cx231xx_info( + ": Init Super Block failed in send cmd\n"); + break; + } + status = cx231xx_read_i2c_data(dev, Colibri_DEVICE_ADDRESS, SUP_BLK_PWRDN, 2, &colibri_power_status, 1); colibri_power_status &= 0xff; if (status < 0) { cx231xx_info( - ": Init Super Block failed in send/receive cmds\n"); + ": Init Super Block failed in receive cmd\n"); break; } i++; @@ -93,6 +108,9 @@ int cx231xx_colibri_init_super_block(struct cx231xx *dev, u32 ref_count) /* start tuning filter */ status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, SUP_BLK_TUNE3, 2, 0x40, 1); + if (status < 0) + return status; + msleep(5); /* exit tuning */ @@ -188,7 +206,10 @@ int cx231xx_colibri_setup_AFE_for_baseband(struct cx231xx *dev) } /* - we have 3 channel + The Analog Front End in Cx231xx has 3 channels. These + channels are used to share between different inputs + like tuner, s-video and composite inputs. + channel 1 ----- pin 1 to pin4(in reg is 1-4) channel 2 ----- pin 5 to pin8(in reg is 5-8) channel 3 ----- pin 9 to pin 12(in reg is 9-11) @@ -242,6 +263,11 @@ int cx231xx_colibri_set_mode(struct cx231xx *dev, enum AFE_MODE mode) { int status = 0; + /* + * FIXME: We need to implement the AFE code for LOW IF and for HI IF. + * Currently, only baseband works. + */ + switch (mode) { case AFE_MODE_LOW_IF: /* SetupAFEforLowIF(); */ @@ -270,8 +296,8 @@ int cx231xx_colibri_set_mode(struct cx231xx *dev, enum AFE_MODE mode) return status; } -/* For power saving in the EVK */ -int cx231xx_colibri_update_power_control(struct cx231xx *dev, AV_MODE avmode) +int cx231xx_colibri_update_power_control(struct cx231xx *dev, + enum AV_MODE avmode) { u32 colibri_power_status = 0; int status = 0; @@ -279,14 +305,16 @@ int cx231xx_colibri_update_power_control(struct cx231xx *dev, AV_MODE avmode) switch (dev->model) { case CX231XX_BOARD_CNXT_RDE_250: case CX231XX_BOARD_CNXT_RDU_250: - if (avmode == POLARIS_AVMODE_ANALOGT_TV) { - while (colibri_power_status != 0x18) { + while (colibri_power_status != (FLD_PWRDN_TUNING_BIAS | + FLD_PWRDN_ENABLE_PLL)) { status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, SUP_BLK_PWRDN, 2, - 0x18, 1); - status = cx231xx_read_i2c_data(dev, + FLD_PWRDN_TUNING_BIAS | + FLD_PWRDN_ENABLE_PLL, + 1); + status |= cx231xx_read_i2c_data(dev, Colibri_DEVICE_ADDRESS, SUP_BLK_PWRDN, 2, &colibri_power_status, @@ -299,11 +327,11 @@ int cx231xx_colibri_update_power_control(struct cx231xx *dev, AV_MODE avmode) Colibri_DEVICE_ADDRESS, ADC_PWRDN_CLAMP_CH1, 2, 0x00, 1); - status = cx231xx_write_i2c_data(dev, + status |= cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, ADC_PWRDN_CLAMP_CH2, 2, 0x00, 1); - status = cx231xx_write_i2c_data(dev, + status |= cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, ADC_PWRDN_CLAMP_CH3, 2, 0x00, 1); @@ -312,32 +340,36 @@ int cx231xx_colibri_update_power_control(struct cx231xx *dev, AV_MODE avmode) Colibri_DEVICE_ADDRESS, ADC_PWRDN_CLAMP_CH1, 2, 0x70, 1); - status = cx231xx_write_i2c_data(dev, + status |= cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, ADC_PWRDN_CLAMP_CH2, 2, 0x70, 1); - status = cx231xx_write_i2c_data(dev, + status |= cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, ADC_PWRDN_CLAMP_CH3, 2, 0x70, 1); - status = cx231xx_read_i2c_data(dev, + status |= cx231xx_read_i2c_data(dev, Colibri_DEVICE_ADDRESS, SUP_BLK_PWRDN, 2, &colibri_power_status, 1); - colibri_power_status |= 0x07; - status = cx231xx_write_i2c_data(dev, + colibri_power_status |= FLD_PWRDN_PD_BANDGAP | + FLD_PWRDN_PD_BIAS | + FLD_PWRDN_PD_TUNECK; + status |= cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, SUP_BLK_PWRDN, 2, colibri_power_status, 1); } else if (avmode == POLARIS_AVMODE_ENXTERNAL_AV) { - - while (colibri_power_status != 0x18) { + while (colibri_power_status != (FLD_PWRDN_TUNING_BIAS | + FLD_PWRDN_ENABLE_PLL)) { status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, SUP_BLK_PWRDN, 2, - 0x18, 1); - status = cx231xx_read_i2c_data(dev, + FLD_PWRDN_TUNING_BIAS | + FLD_PWRDN_ENABLE_PLL, + 1); + status |= cx231xx_read_i2c_data(dev, Colibri_DEVICE_ADDRESS, SUP_BLK_PWRDN, 2, &colibri_power_status, @@ -346,15 +378,15 @@ int cx231xx_colibri_update_power_control(struct cx231xx *dev, AV_MODE avmode) break; } - status = cx231xx_write_i2c_data(dev, + status |= cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, ADC_PWRDN_CLAMP_CH1, 2, 0x00, 1); - status = cx231xx_write_i2c_data(dev, + status |= cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, ADC_PWRDN_CLAMP_CH2, 2, 0x00, 1); - status = cx231xx_write_i2c_data(dev, + status |= cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, ADC_PWRDN_CLAMP_CH3, 2, 0x00, 1); @@ -365,12 +397,15 @@ int cx231xx_colibri_update_power_control(struct cx231xx *dev, AV_MODE avmode) break; default: if (avmode == POLARIS_AVMODE_ANALOGT_TV) { - while (colibri_power_status != 0x18) { + while (colibri_power_status != (FLD_PWRDN_TUNING_BIAS | + FLD_PWRDN_ENABLE_PLL)) { status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, SUP_BLK_PWRDN, 2, - 0x18, 1); - status = cx231xx_read_i2c_data(dev, + FLD_PWRDN_TUNING_BIAS | + FLD_PWRDN_ENABLE_PLL, + 1); + status |= cx231xx_read_i2c_data(dev, Colibri_DEVICE_ADDRESS, SUP_BLK_PWRDN, 2, &colibri_power_status, @@ -379,15 +414,15 @@ int cx231xx_colibri_update_power_control(struct cx231xx *dev, AV_MODE avmode) break; } - status = cx231xx_write_i2c_data(dev, + status |= cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, ADC_PWRDN_CLAMP_CH1, 2, 0x40, 1); - status = cx231xx_write_i2c_data(dev, + status |= cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, ADC_PWRDN_CLAMP_CH2, 2, 0x40, 1); - status = cx231xx_write_i2c_data(dev, + status |= cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, ADC_PWRDN_CLAMP_CH3, 2, 0x00, 1); @@ -396,33 +431,38 @@ int cx231xx_colibri_update_power_control(struct cx231xx *dev, AV_MODE avmode) Colibri_DEVICE_ADDRESS, ADC_PWRDN_CLAMP_CH1, 2, 0x70, 1); - status = cx231xx_write_i2c_data(dev, + status |= cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, ADC_PWRDN_CLAMP_CH2, 2, 0x70, 1); - status = cx231xx_write_i2c_data(dev, + status |= cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, ADC_PWRDN_CLAMP_CH3, 2, 0x70, 1); - status = cx231xx_read_i2c_data(dev, + status |= cx231xx_read_i2c_data(dev, Colibri_DEVICE_ADDRESS, SUP_BLK_PWRDN, 2, &colibri_power_status, 1); - colibri_power_status |= 0x07; - status = cx231xx_write_i2c_data(dev, + colibri_power_status |= FLD_PWRDN_PD_BANDGAP | + FLD_PWRDN_PD_BIAS | + FLD_PWRDN_PD_TUNECK; + status |= cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, SUP_BLK_PWRDN, 2, colibri_power_status, 1); } else if (avmode == POLARIS_AVMODE_ENXTERNAL_AV) { - while (colibri_power_status != 0x18) { + while (colibri_power_status != (FLD_PWRDN_TUNING_BIAS | + FLD_PWRDN_ENABLE_PLL)) { status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, SUP_BLK_PWRDN, 2, - 0x18, 1); - status = cx231xx_read_i2c_data(dev, + FLD_PWRDN_TUNING_BIAS | + FLD_PWRDN_ENABLE_PLL, + 1); + status |= cx231xx_read_i2c_data(dev, Colibri_DEVICE_ADDRESS, SUP_BLK_PWRDN, 2, &colibri_power_status, @@ -431,15 +471,15 @@ int cx231xx_colibri_update_power_control(struct cx231xx *dev, AV_MODE avmode) break; } - status = cx231xx_write_i2c_data(dev, + status |= cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, ADC_PWRDN_CLAMP_CH1, 2, 0x00, 1); - status = cx231xx_write_i2c_data(dev, + status |= cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, ADC_PWRDN_CLAMP_CH2, 2, 0x00, 1); - status = cx231xx_write_i2c_data(dev, + status |= cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, ADC_PWRDN_CLAMP_CH3, 2, 0x40, 1); @@ -500,7 +540,7 @@ int cx231xx_colibri_adjust_ref_count(struct cx231xx *dev, u32 video_input) /****************************************************************************** * V I D E O / A U D I O D E C O D E R C O N T R O L functions * - ******************************************++**********************************/ + ******************************************************************************/ int cx231xx_set_video_input_mux(struct cx231xx *dev, u8 input) { int status = 0; @@ -839,7 +879,7 @@ int cx231xx_set_decoder_video_input(struct cx231xx *dev, DFE_CTRL1, 2, value, 4); - /* Wait 15 ms */ + /* Wait until AGC locks up */ msleep(1); /* Disable the auto-VGA enable AGC */ @@ -940,8 +980,7 @@ int cx231xx_do_mode_ctrl_overrides(struct cx231xx *dev) DFE_CTRL3, 2, 0xCD3F0280, 4); - if (dev->norm & (V4L2_STD_NTSC_M | V4L2_STD_NTSC_M_JP | - V4L2_STD_PAL_M)) { + if (dev->norm & (V4L2_STD_NTSC | V4L2_STD_PAL_M)) { cx231xx_info("do_mode_ctrl_overrides NTSC\n"); /* Move the close caption lines out of active video, @@ -967,11 +1006,9 @@ int cx231xx_do_mode_ctrl_overrides(struct cx231xx *dev) FLD_HBLANK_CNT, cx231xx_set_field (FLD_HBLANK_CNT, 0x79)); - } else if (dev->norm & (V4L2_STD_PAL_B | V4L2_STD_PAL_G | - V4L2_STD_PAL_D | V4L2_STD_PAL_I | - V4L2_STD_PAL_N | V4L2_STD_PAL_Nc)) { - cx231xx_info("do_mode_ctrl_overrides PAL\n"); - status = cx231xx_read_modify_write_i2c_dword(dev, + } else if (dev->norm & V4L2_STD_SECAM) { + cx231xx_info("do_mode_ctrl_overrides SECAM\n"); + status = cx231xx_read_modify_write_i2c_dword(dev, HAMMERHEAD_I2C_ADDRESS, VERT_TIM_CTRL, FLD_VBLANK_CNT, 0x24); @@ -982,12 +1019,9 @@ int cx231xx_do_mode_ctrl_overrides(struct cx231xx *dev) FLD_HBLANK_CNT, cx231xx_set_field (FLD_HBLANK_CNT, 0x85)); - } else if (dev->norm & (V4L2_STD_SECAM_B | V4L2_STD_SECAM_D | - V4L2_STD_SECAM_G | V4L2_STD_SECAM_K | - V4L2_STD_SECAM_K1 | V4L2_STD_SECAM_L | - V4L2_STD_SECAM_LC)) { - cx231xx_info("do_mode_ctrl_overrides SECAM\n"); - status = cx231xx_read_modify_write_i2c_dword(dev, + } else { + cx231xx_info("do_mode_ctrl_overrides PAL\n"); + status = cx231xx_read_modify_write_i2c_dword(dev, HAMMERHEAD_I2C_ADDRESS, VERT_TIM_CTRL, FLD_VBLANK_CNT, 0x24); @@ -1276,13 +1310,8 @@ int cx231xx_dif_configure_C2HH_for_low_IF(struct cx231xx *dev, u32 mode, status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, AFE_CTRL_C2HH_SRC_CTRL, 9, 9, 0x1); - } else { - switch (standard) { - case V4L2_STD_NTSC_M: /* 75 IRE Setup */ - case V4L2_STD_NTSC_M_JP:/* Japan, 0 IRE Setup */ - case V4L2_STD_PAL_M: - case V4L2_STD_PAL_N: - case V4L2_STD_PAL_Nc: + } else if (standard != DIF_USE_BASEBAND) { + if (standard & V4L2_STD_MN) { /* lo if big signal */ status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, @@ -1304,10 +1333,8 @@ int cx231xx_dif_configure_C2HH_for_low_IF(struct cx231xx *dev, u32 mode, status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, AUD_IO_CTRL, 0, 31, 0x00000003); - break; - - case V4L2_STD_PAL_B: - case V4L2_STD_PAL_G: + } else if ((standard == V4L2_STD_PAL_I) | + (standard & V4L2_STD_SECAM)) { /* C2HH setup */ /* lo if big signal */ status = cx231xx_reg_mask_write(dev, @@ -1321,22 +1348,13 @@ int cx231xx_dif_configure_C2HH_for_low_IF(struct cx231xx *dev, u32 mode, /* IF_MODE */ status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, - AFE_CTRL_C2HH_SRC_CTRL, 15, 22, 0xE); + AFE_CTRL_C2HH_SRC_CTRL, 15, 22, 0xF); /* no inv */ status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, AFE_CTRL_C2HH_SRC_CTRL, 9, 9, 0x1); - break; - - case V4L2_STD_PAL_D: - case V4L2_STD_PAL_I: - case V4L2_STD_SECAM_L: - case V4L2_STD_SECAM_LC: - case V4L2_STD_SECAM_B: - case V4L2_STD_SECAM_D: - case V4L2_STD_SECAM_G: - case V4L2_STD_SECAM_K: - case V4L2_STD_SECAM_K1: + } else { + /* default PAL BG */ /* C2HH setup */ /* lo if big signal */ status = cx231xx_reg_mask_write(dev, @@ -1350,17 +1368,11 @@ int cx231xx_dif_configure_C2HH_for_low_IF(struct cx231xx *dev, u32 mode, /* IF_MODE */ status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, - AFE_CTRL_C2HH_SRC_CTRL, 15, 22, 0xF); + AFE_CTRL_C2HH_SRC_CTRL, 15, 22, 0xE); /* no inv */ status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, AFE_CTRL_C2HH_SRC_CTRL, 9, 9, 0x1); - break; - - case DIF_USE_BASEBAND: - default: - /* do nothing to config C2HH for baseband */ - break; } } @@ -1406,54 +1418,6 @@ int cx231xx_dif_set_standard(struct cx231xx *dev, u32 standard) status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, DIF_MISC_CTRL, 2, dif_misc_ctrl_value, 4); - - } else if (standard & (V4L2_STD_PAL_B | V4L2_STD_PAL_G)) { - - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, - DIF_PLL_CTRL, 0, 31, 0x6503bc0c); - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, - DIF_PLL_CTRL1, 0, 31, 0xbd038c85); - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, - DIF_PLL_CTRL2, 0, 31, 0x1db4640a); - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, - DIF_PLL_CTRL3, 0, 31, 0x00008800); - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, - DIF_AGC_IF_REF, 0, 31, 0x444C1380); - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, - DIF_AGC_CTRL_IF, 0, 31, 0xDA302600); - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, - DIF_AGC_CTRL_INT, 0, 31, 0xDA261700); - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, - DIF_AGC_CTRL_RF, 0, 31, 0xDA262600); - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, - DIF_AGC_IF_INT_CURRENT, 0, 31, - 0x26001700); - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, - DIF_AGC_RF_CURRENT, 0, 31, - 0x00002660); - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, - DIF_VIDEO_AGC_CTRL, 0, 31, - 0x72500800); - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, - DIF_VID_AUD_OVERRIDE, 0, 31, - 0x27000100); - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, - DIF_AV_SEP_CTRL, 0, 31, 0x3F3530EC); - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, - DIF_COMP_FLT_CTRL, 0, 31, - 0x00A653A8); - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, - DIF_SRC_PHASE_INC, 0, 31, - 0x1befbf06); - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, - DIF_SRC_GAIN_CONTROL, 0, 31, - 0x000035e8); - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, - DIF_RPT_VARIANCE, 0, 31, 0x00000000); - /* Save the Spec Inversion value */ - dif_misc_ctrl_value &= FLD_DIF_SPEC_INV; - dif_misc_ctrl_value |= 0x3a013F11; - } else if (standard & V4L2_STD_PAL_D) { status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_PLL_CTRL, 0, 31, 0x6503bc0c); @@ -1499,9 +1463,7 @@ int cx231xx_dif_set_standard(struct cx231xx *dev, u32 standard) /* Save the Spec Inversion value */ dif_misc_ctrl_value &= FLD_DIF_SPEC_INV; dif_misc_ctrl_value |= 0x3a023F11; - } else if (standard & V4L2_STD_PAL_I) { - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_PLL_CTRL, 0, 31, 0x6503bc0c); status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, @@ -1546,7 +1508,6 @@ int cx231xx_dif_set_standard(struct cx231xx *dev, u32 standard) /* Save the Spec Inversion value */ dif_misc_ctrl_value &= FLD_DIF_SPEC_INV; dif_misc_ctrl_value |= 0x3a033F11; - } else if (standard & V4L2_STD_PAL_M) { /* improved Low Frequency Phase Noise */ status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, @@ -1584,13 +1545,10 @@ int cx231xx_dif_set_standard(struct cx231xx *dev, u32 standard) status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, DIF_SOFT_RST_CTRL_REVB, 2, 0x00000000, 4); - /* Save the Spec Inversion value */ dif_misc_ctrl_value &= FLD_DIF_SPEC_INV; dif_misc_ctrl_value |= 0x3A0A3F10; - } else if (standard & (V4L2_STD_PAL_N | V4L2_STD_PAL_Nc)) { - /* improved Low Frequency Phase Noise */ status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, DIF_PLL_CTRL, 2, 0xFF01FF0C, 4); @@ -1626,14 +1584,12 @@ int cx231xx_dif_set_standard(struct cx231xx *dev, u32 standard) status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, DIF_SOFT_RST_CTRL_REVB, 2, 0x00000000, 4); - /* Save the Spec Inversion value */ dif_misc_ctrl_value &= FLD_DIF_SPEC_INV; dif_misc_ctrl_value = 0x3A093F10; - } else if (standard & - (V4L2_STD_SECAM_B | V4L2_STD_SECAM_D | V4L2_STD_SECAM_G | - V4L2_STD_SECAM_K | V4L2_STD_SECAM_K1)) { + (V4L2_STD_SECAM_B | V4L2_STD_SECAM_D | V4L2_STD_SECAM_G | + V4L2_STD_SECAM_K | V4L2_STD_SECAM_K1)) { status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_PLL_CTRL, 0, 31, 0x6503bc0c); @@ -1680,9 +1636,7 @@ int cx231xx_dif_set_standard(struct cx231xx *dev, u32 standard) /* Save the Spec Inversion value */ dif_misc_ctrl_value &= FLD_DIF_SPEC_INV; dif_misc_ctrl_value |= 0x3a023F11; - } else if (standard & (V4L2_STD_SECAM_L | V4L2_STD_SECAM_LC)) { - /* Is it SECAM_L1? */ status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, DIF_PLL_CTRL, 0, 31, 0x6503bc0c); @@ -1730,7 +1684,7 @@ int cx231xx_dif_set_standard(struct cx231xx *dev, u32 standard) dif_misc_ctrl_value &= FLD_DIF_SPEC_INV; dif_misc_ctrl_value |= 0x3a023F11; - } else { + } else if (standard & V4L2_STD_NTSC_M) { /* V4L2_STD_NTSC_M (75 IRE Setup) Or V4L2_STD_NTSC_M_JP (Japan, 0 IRE Setup) */ @@ -1783,7 +1737,52 @@ int cx231xx_dif_set_standard(struct cx231xx *dev, u32 standard) /* Save the Spec Inversion value */ dif_misc_ctrl_value &= FLD_DIF_SPEC_INV; dif_misc_ctrl_value |= 0x3a003F10; - + } else { + /* default PAL BG */ + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + DIF_PLL_CTRL, 0, 31, 0x6503bc0c); + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + DIF_PLL_CTRL1, 0, 31, 0xbd038c85); + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + DIF_PLL_CTRL2, 0, 31, 0x1db4640a); + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + DIF_PLL_CTRL3, 0, 31, 0x00008800); + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + DIF_AGC_IF_REF, 0, 31, 0x444C1380); + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + DIF_AGC_CTRL_IF, 0, 31, 0xDA302600); + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + DIF_AGC_CTRL_INT, 0, 31, 0xDA261700); + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + DIF_AGC_CTRL_RF, 0, 31, 0xDA262600); + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + DIF_AGC_IF_INT_CURRENT, 0, 31, + 0x26001700); + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + DIF_AGC_RF_CURRENT, 0, 31, + 0x00002660); + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + DIF_VIDEO_AGC_CTRL, 0, 31, + 0x72500800); + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + DIF_VID_AUD_OVERRIDE, 0, 31, + 0x27000100); + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + DIF_AV_SEP_CTRL, 0, 31, 0x3F3530EC); + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + DIF_COMP_FLT_CTRL, 0, 31, + 0x00A653A8); + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + DIF_SRC_PHASE_INC, 0, 31, + 0x1befbf06); + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + DIF_SRC_GAIN_CONTROL, 0, 31, + 0x000035e8); + status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + DIF_RPT_VARIANCE, 0, 31, 0x00000000); + /* Save the Spec Inversion value */ + dif_misc_ctrl_value &= FLD_DIF_SPEC_INV; + dif_misc_ctrl_value |= 0x3a013F11; } /* The AGC values should be the same for all standards, @@ -1826,7 +1825,8 @@ int cx231xx_tuner_post_channel_change(struct cx231xx *dev) int status = 0; u32 dwval; - /* Set the RF and IF k_agc values to 4 for PAL/NTSC and 8 for SECAM */ + /* Set the RF and IF k_agc values to 4 for PAL/NTSC and 8 for + * SECAM L/B/D standards */ status = cx231xx_read_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, DIF_AGC_IF_REF, 2, &dwval, 4); dwval &= ~(FLD_DIF_K_AGC_RF | FLD_DIF_K_AGC_IF); @@ -1864,7 +1864,8 @@ int cx231xx_flatiron_initialize(struct cx231xx *dev) return status; } -int cx231xx_flatiron_update_power_control(struct cx231xx *dev, AV_MODE avmode) +int cx231xx_flatiron_update_power_control(struct cx231xx *dev, + enum AV_MODE avmode) { int status = 0; u32 value = 0; @@ -1908,7 +1909,7 @@ int cx231xx_flatiron_set_audio_input(struct cx231xx *dev, u8 audio_input) /****************************************************************************** * P O W E R C O N T R O L functions * ******************************************************************************/ -int cx231xx_set_power_mode(struct cx231xx *dev, AV_MODE mode) +int cx231xx_set_power_mode(struct cx231xx *dev, enum AV_MODE mode) { u8 value[4] = { 0, 0, 0, 0 }; u32 tmp = 0; @@ -2211,7 +2212,7 @@ int cx231xx_initialize_stream_xfer(struct cx231xx *dev, u32 media_type) if (dev->udev->speed == USB_SPEED_HIGH) { switch (media_type) { - case 81: /* audio */ + case 81: /* audio */ cx231xx_info("%s: Audio enter HANC\n", __func__); status = cx231xx_mode_register(dev, TS_MODE_REG, 0x9300); @@ -2390,7 +2391,7 @@ int cx231xx_set_gpio_direction(struct cx231xx *dev, } /* -* SetGpioPinLogicValue +* cx231xx_set_gpio_value * Sets the value of the GPIO pin to Logic high or low. The Pin under * reference should ALREADY BE SET IN OUTPUT MODE !!!!!!!!! * -- cgit v1.2.3 From abd67a8824bedd0562212ae4c205722d08ace135 Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Sat, 21 Mar 2009 22:00:20 -0300 Subject: cx231xx: Use generic names for each device block From: Sri Deevi Priority: normal Signed-off-by: Srinivasa Deevi Reviewed-by: Hans Verkuil Signed-off-by: Mauro Carvalho Chehab --- linux/drivers/media/video/cx231xx/cx231xx-avcore.c | 1171 ++++++++------------ 1 file changed, 486 insertions(+), 685 deletions(-) (limited to 'linux/drivers/media/video/cx231xx/cx231xx-avcore.c') diff --git a/linux/drivers/media/video/cx231xx/cx231xx-avcore.c b/linux/drivers/media/video/cx231xx/cx231xx-avcore.c index 226299d62..1be3881be 100644 --- a/linux/drivers/media/video/cx231xx/cx231xx-avcore.c +++ b/linux/drivers/media/video/cx231xx/cx231xx-avcore.c @@ -40,54 +40,77 @@ #include "cx231xx.h" /****************************************************************************** - * C O L I B R I - B L O C K C O N T R O L functions * + -: BLOCK ARRANGEMENT :- + I2S block ----------------------| + [I2S audio] | + | + Analog Front End --> Direct IF -|-> Cx25840 --> Audio + [video & audio] | [Audio] + | + |-> Cx25840 --> Video + [Video] + +*******************************************************************************/ + +/****************************************************************************** + * A F E - B L O C K C O N T R O L functions * + * [ANALOG FRONT END] * ******************************************************************************/ -int cx231xx_colibri_init_super_block(struct cx231xx *dev, u32 ref_count) +static int afe_write_byte(struct cx231xx *dev, u16 saddr, u8 data) +{ + return cx231xx_write_i2c_data(dev, AFE_DEVICE_ADDRESS, + saddr, 2, data, 1); +} + +static int afe_read_byte(struct cx231xx *dev, u16 saddr, u8 *data) +{ + int status; + u32 temp = 0; + + status = cx231xx_read_i2c_data(dev, AFE_DEVICE_ADDRESS, + saddr, 2, &temp, 1); + *data = (u8) temp; + return status; +} + +int cx231xx_afe_init_super_block(struct cx231xx *dev, u32 ref_count) { int status = 0; u8 temp = 0; - u32 colibri_power_status = 0; + u8 afe_power_status = 0; int i = 0; /* super block initialize */ temp = (u8) (ref_count & 0xff); - status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, - SUP_BLK_TUNE2, 2, temp, 1); + status = afe_write_byte(dev, SUP_BLK_TUNE2, temp); if (status < 0) return status; - status = cx231xx_read_i2c_data(dev, Colibri_DEVICE_ADDRESS, - SUP_BLK_TUNE2, 2, - &colibri_power_status, 1); + status = afe_read_byte(dev, SUP_BLK_TUNE2, &afe_power_status); if (status < 0) return status; temp = (u8) ((ref_count & 0x300) >> 8); temp |= 0x40; - status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, - SUP_BLK_TUNE1, 2, temp, 1); + status = afe_write_byte(dev, SUP_BLK_TUNE1, temp); if (status < 0) return status; - status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, - SUP_BLK_PLL2, 2, 0x0f, 1); + status = afe_write_byte(dev, SUP_BLK_PLL2, 0x0f); if (status < 0) return status; /* enable pll */ - while (colibri_power_status != 0x18) { - status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, - SUP_BLK_PWRDN, 2, 0x18, 1); + while (afe_power_status != 0x18) { + status = afe_write_byte(dev, SUP_BLK_PWRDN, 0x18); if (status < 0) { cx231xx_info( ": Init Super Block failed in send cmd\n"); break; } - status = cx231xx_read_i2c_data(dev, Colibri_DEVICE_ADDRESS, - SUP_BLK_PWRDN, 2, - &colibri_power_status, 1); - colibri_power_status &= 0xff; + status = afe_read_byte(dev, SUP_BLK_PWRDN, &afe_power_status); + afe_power_status &= 0xff; if (status < 0) { cx231xx_info( ": Init Super Block failed in receive cmd\n"); @@ -106,101 +129,75 @@ int cx231xx_colibri_init_super_block(struct cx231xx *dev, u32 ref_count) return status; /* start tuning filter */ - status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, - SUP_BLK_TUNE3, 2, 0x40, 1); + status = afe_write_byte(dev, SUP_BLK_TUNE3, 0x40); if (status < 0) return status; msleep(5); /* exit tuning */ - status = - cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, SUP_BLK_TUNE3, - 2, 0x00, 1); + status = afe_write_byte(dev, SUP_BLK_TUNE3, 0x00); return status; } -int cx231xx_colibri_init_channels(struct cx231xx *dev) +int cx231xx_afe_init_channels(struct cx231xx *dev) { int status = 0; /* power up all 3 channels, clear pd_buffer */ - status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, - ADC_PWRDN_CLAMP_CH1, 2, 0x00, 1); - status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, - ADC_PWRDN_CLAMP_CH2, 2, 0x00, 1); - status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, - ADC_PWRDN_CLAMP_CH3, 2, 0x00, 1); + status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1, 0x00); + status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2, 0x00); + status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3, 0x00); /* Enable quantizer calibration */ - status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, - ADC_COM_QUANT, 2, 0x02, 1); + status = afe_write_byte(dev, ADC_COM_QUANT, 0x02); /* channel initialize, force modulator (fb) reset */ - status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, - ADC_FB_FRCRST_CH1, 2, 0x17, 1); - status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, - ADC_FB_FRCRST_CH2, 2, 0x17, 1); - status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, - ADC_FB_FRCRST_CH3, 2, 0x17, 1); + status = afe_write_byte(dev, ADC_FB_FRCRST_CH1, 0x17); + status = afe_write_byte(dev, ADC_FB_FRCRST_CH2, 0x17); + status = afe_write_byte(dev, ADC_FB_FRCRST_CH3, 0x17); /* start quantilizer calibration */ - status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, - ADC_CAL_ATEST_CH1, 2, 0x10, 1); - status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, - ADC_CAL_ATEST_CH2, 2, 0x10, 1); - status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, - ADC_CAL_ATEST_CH3, 2, 0x10, 1); + status = afe_write_byte(dev, ADC_CAL_ATEST_CH1, 0x10); + status = afe_write_byte(dev, ADC_CAL_ATEST_CH2, 0x10); + status = afe_write_byte(dev, ADC_CAL_ATEST_CH3, 0x10); msleep(5); /* exit modulator (fb) reset */ - status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, - ADC_FB_FRCRST_CH1, 2, 0x07, 1); - status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, - ADC_FB_FRCRST_CH2, 2, 0x07, 1); - status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, - ADC_FB_FRCRST_CH3, 2, 0x07, 1); + status = afe_write_byte(dev, ADC_FB_FRCRST_CH1, 0x07); + status = afe_write_byte(dev, ADC_FB_FRCRST_CH2, 0x07); + status = afe_write_byte(dev, ADC_FB_FRCRST_CH3, 0x07); /* enable the pre_clamp in each channel for single-ended input */ - status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, - ADC_NTF_PRECLMP_EN_CH1, 2, 0xf0, 1); - status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, - ADC_NTF_PRECLMP_EN_CH2, 2, 0xf0, 1); - status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, - ADC_NTF_PRECLMP_EN_CH3, 2, 0xf0, 1); + status = afe_write_byte(dev, ADC_NTF_PRECLMP_EN_CH1, 0xf0); + status = afe_write_byte(dev, ADC_NTF_PRECLMP_EN_CH2, 0xf0); + status = afe_write_byte(dev, ADC_NTF_PRECLMP_EN_CH3, 0xf0); /* use diode instead of resistor, so set term_en to 0, res_en to 0 */ - status = cx231xx_reg_mask_write(dev, Colibri_DEVICE_ADDRESS, 8, + status = cx231xx_reg_mask_write(dev, AFE_DEVICE_ADDRESS, 8, ADC_QGAIN_RES_TRM_CH1, 3, 7, 0x00); - status = cx231xx_reg_mask_write(dev, Colibri_DEVICE_ADDRESS, 8, + status = cx231xx_reg_mask_write(dev, AFE_DEVICE_ADDRESS, 8, ADC_QGAIN_RES_TRM_CH2, 3, 7, 0x00); - status = cx231xx_reg_mask_write(dev, Colibri_DEVICE_ADDRESS, 8, + status = cx231xx_reg_mask_write(dev, AFE_DEVICE_ADDRESS, 8, ADC_QGAIN_RES_TRM_CH3, 3, 7, 0x00); /* dynamic element matching off */ - status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, - ADC_DCSERVO_DEM_CH1, 2, 0x03, 1); - status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, - ADC_DCSERVO_DEM_CH2, 2, 0x03, 1); - status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, - ADC_DCSERVO_DEM_CH3, 2, 0x03, 1); + status = afe_write_byte(dev, ADC_DCSERVO_DEM_CH1, 0x03); + status = afe_write_byte(dev, ADC_DCSERVO_DEM_CH2, 0x03); + status = afe_write_byte(dev, ADC_DCSERVO_DEM_CH3, 0x03); return status; } -int cx231xx_colibri_setup_AFE_for_baseband(struct cx231xx *dev) +int cx231xx_afe_setup_AFE_for_baseband(struct cx231xx *dev) { - u32 c_value = 0; + u8 c_value = 0; int status = 0; - status = - cx231xx_read_i2c_data(dev, Colibri_DEVICE_ADDRESS, - ADC_PWRDN_CLAMP_CH2, 2, &c_value, 1); + status = afe_read_byte(dev, ADC_PWRDN_CLAMP_CH2, &c_value); c_value &= (~(0x50)); - status = - cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, - ADC_PWRDN_CLAMP_CH2, 2, c_value, 1); + status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2, c_value); return status; } @@ -214,52 +211,44 @@ int cx231xx_colibri_setup_AFE_for_baseband(struct cx231xx *dev) channel 2 ----- pin 5 to pin8(in reg is 5-8) channel 3 ----- pin 9 to pin 12(in reg is 9-11) */ -int cx231xx_colibri_set_input_mux(struct cx231xx *dev, u32 input_mux) +int cx231xx_afe_set_input_mux(struct cx231xx *dev, u32 input_mux) { u8 ch1_setting = (u8) input_mux; u8 ch2_setting = (u8) (input_mux >> 8); u8 ch3_setting = (u8) (input_mux >> 16); int status = 0; - u32 value = 0; + u8 value = 0; if (ch1_setting != 0) { - status = - cx231xx_read_i2c_data(dev, Colibri_DEVICE_ADDRESS, - ADC_INPUT_CH1, 2, &value, 1); + status = afe_read_byte(dev, ADC_INPUT_CH1, &value); value &= (!INPUT_SEL_MASK); value |= (ch1_setting - 1) << 4; value &= 0xff; - status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, - ADC_INPUT_CH1, 2, value, 1); + status = afe_write_byte(dev, ADC_INPUT_CH1, value); } if (ch2_setting != 0) { - status = - cx231xx_read_i2c_data(dev, Colibri_DEVICE_ADDRESS, - ADC_INPUT_CH2, 2, &value, 1); + status = afe_read_byte(dev, ADC_INPUT_CH2, &value); value &= (!INPUT_SEL_MASK); value |= (ch2_setting - 1) << 4; value &= 0xff; - status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, - ADC_INPUT_CH2, 2, value, 1); + status = afe_write_byte(dev, ADC_INPUT_CH2, value); } /* For ch3_setting, the value to put in the register is 7 less than the input number */ if (ch3_setting != 0) { - status = cx231xx_read_i2c_data(dev, Colibri_DEVICE_ADDRESS, - ADC_INPUT_CH3, 2, &value, 1); + status = afe_read_byte(dev, ADC_INPUT_CH3, &value); value &= (!INPUT_SEL_MASK); value |= (ch3_setting - 1) << 4; value &= 0xff; - status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, - ADC_INPUT_CH3, 2, value, 1); + status = afe_write_byte(dev, ADC_INPUT_CH3, value); } return status; } -int cx231xx_colibri_set_mode(struct cx231xx *dev, enum AFE_MODE mode) +int cx231xx_afe_set_mode(struct cx231xx *dev, enum AFE_MODE mode) { int status = 0; @@ -273,7 +262,7 @@ int cx231xx_colibri_set_mode(struct cx231xx *dev, enum AFE_MODE mode) /* SetupAFEforLowIF(); */ break; case AFE_MODE_BASEBAND: - status = cx231xx_colibri_setup_AFE_for_baseband(dev); + status = cx231xx_afe_setup_AFE_for_baseband(dev); break; case AFE_MODE_EU_HI_IF: /* SetupAFEforEuHiIF(); */ @@ -286,110 +275,76 @@ int cx231xx_colibri_set_mode(struct cx231xx *dev, enum AFE_MODE mode) break; } - if ((mode != dev->colibri_mode) && + if ((mode != dev->afe_mode) && (dev->video_input == CX231XX_VMUX_TELEVISION)) - status = cx231xx_colibri_adjust_ref_count(dev, + status = cx231xx_afe_adjust_ref_count(dev, CX231XX_VMUX_TELEVISION); - dev->colibri_mode = mode; + dev->afe_mode = mode; return status; } -int cx231xx_colibri_update_power_control(struct cx231xx *dev, +int cx231xx_afe_update_power_control(struct cx231xx *dev, enum AV_MODE avmode) { - u32 colibri_power_status = 0; + u8 afe_power_status = 0; int status = 0; switch (dev->model) { case CX231XX_BOARD_CNXT_RDE_250: case CX231XX_BOARD_CNXT_RDU_250: if (avmode == POLARIS_AVMODE_ANALOGT_TV) { - while (colibri_power_status != (FLD_PWRDN_TUNING_BIAS | + while (afe_power_status != (FLD_PWRDN_TUNING_BIAS | FLD_PWRDN_ENABLE_PLL)) { - status = cx231xx_write_i2c_data(dev, - Colibri_DEVICE_ADDRESS, - SUP_BLK_PWRDN, 2, + status = afe_write_byte(dev, SUP_BLK_PWRDN, FLD_PWRDN_TUNING_BIAS | - FLD_PWRDN_ENABLE_PLL, - 1); - status |= cx231xx_read_i2c_data(dev, - Colibri_DEVICE_ADDRESS, - SUP_BLK_PWRDN, 2, - &colibri_power_status, - 1); + FLD_PWRDN_ENABLE_PLL); + status |= afe_read_byte(dev, SUP_BLK_PWRDN, + &afe_power_status); if (status < 0) break; } - status = cx231xx_write_i2c_data(dev, - Colibri_DEVICE_ADDRESS, - ADC_PWRDN_CLAMP_CH1, 2, 0x00, - 1); - status |= cx231xx_write_i2c_data(dev, - Colibri_DEVICE_ADDRESS, - ADC_PWRDN_CLAMP_CH2, 2, 0x00, - 1); - status |= cx231xx_write_i2c_data(dev, - Colibri_DEVICE_ADDRESS, - ADC_PWRDN_CLAMP_CH3, 2, 0x00, - 1); + status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1, + 0x00); + status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2, + 0x00); + status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3, + 0x00); } else if (avmode == POLARIS_AVMODE_DIGITAL) { - status = cx231xx_write_i2c_data(dev, - Colibri_DEVICE_ADDRESS, - ADC_PWRDN_CLAMP_CH1, 2, 0x70, - 1); - status |= cx231xx_write_i2c_data(dev, - Colibri_DEVICE_ADDRESS, - ADC_PWRDN_CLAMP_CH2, 2, 0x70, - 1); - status |= cx231xx_write_i2c_data(dev, - Colibri_DEVICE_ADDRESS, - ADC_PWRDN_CLAMP_CH3, 2, 0x70, - 1); - - status |= cx231xx_read_i2c_data(dev, - Colibri_DEVICE_ADDRESS, - SUP_BLK_PWRDN, 2, - &colibri_power_status, 1); - colibri_power_status |= FLD_PWRDN_PD_BANDGAP | + status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1, + 0x70); + status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2, + 0x70); + status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3, + 0x70); + + status |= afe_read_byte(dev, SUP_BLK_PWRDN, + &afe_power_status); + afe_power_status |= FLD_PWRDN_PD_BANDGAP | FLD_PWRDN_PD_BIAS | FLD_PWRDN_PD_TUNECK; - status |= cx231xx_write_i2c_data(dev, - Colibri_DEVICE_ADDRESS, - SUP_BLK_PWRDN, 2, - colibri_power_status, 1); + status |= afe_write_byte(dev, SUP_BLK_PWRDN, + afe_power_status); } else if (avmode == POLARIS_AVMODE_ENXTERNAL_AV) { - while (colibri_power_status != (FLD_PWRDN_TUNING_BIAS | + while (afe_power_status != (FLD_PWRDN_TUNING_BIAS | FLD_PWRDN_ENABLE_PLL)) { - status = cx231xx_write_i2c_data(dev, - Colibri_DEVICE_ADDRESS, - SUP_BLK_PWRDN, 2, + status = afe_write_byte(dev, SUP_BLK_PWRDN, FLD_PWRDN_TUNING_BIAS | - FLD_PWRDN_ENABLE_PLL, - 1); - status |= cx231xx_read_i2c_data(dev, - Colibri_DEVICE_ADDRESS, - SUP_BLK_PWRDN, 2, - &colibri_power_status, - 1); + FLD_PWRDN_ENABLE_PLL); + status |= afe_read_byte(dev, SUP_BLK_PWRDN, + &afe_power_status); if (status < 0) break; } - status |= cx231xx_write_i2c_data(dev, - Colibri_DEVICE_ADDRESS, - ADC_PWRDN_CLAMP_CH1, 2, 0x00, - 1); - status |= cx231xx_write_i2c_data(dev, - Colibri_DEVICE_ADDRESS, - ADC_PWRDN_CLAMP_CH2, 2, 0x00, - 1); - status |= cx231xx_write_i2c_data(dev, - Colibri_DEVICE_ADDRESS, - ADC_PWRDN_CLAMP_CH3, 2, 0x00, - 1); + status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1, + 0x00); + status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2, + 0x00); + status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3, + 0x00); } else { cx231xx_info("Invalid AV mode input\n"); status = -1; @@ -397,92 +352,56 @@ int cx231xx_colibri_update_power_control(struct cx231xx *dev, break; default: if (avmode == POLARIS_AVMODE_ANALOGT_TV) { - while (colibri_power_status != (FLD_PWRDN_TUNING_BIAS | + while (afe_power_status != (FLD_PWRDN_TUNING_BIAS | FLD_PWRDN_ENABLE_PLL)) { - status = cx231xx_write_i2c_data(dev, - Colibri_DEVICE_ADDRESS, - SUP_BLK_PWRDN, 2, + status = afe_write_byte(dev, SUP_BLK_PWRDN, FLD_PWRDN_TUNING_BIAS | - FLD_PWRDN_ENABLE_PLL, - 1); - status |= cx231xx_read_i2c_data(dev, - Colibri_DEVICE_ADDRESS, - SUP_BLK_PWRDN, 2, - &colibri_power_status, - 1); + FLD_PWRDN_ENABLE_PLL); + status |= afe_read_byte(dev, SUP_BLK_PWRDN, + &afe_power_status); if (status < 0) break; } - status |= cx231xx_write_i2c_data(dev, - Colibri_DEVICE_ADDRESS, - ADC_PWRDN_CLAMP_CH1, 2, - 0x40, 1); - status |= cx231xx_write_i2c_data(dev, - Colibri_DEVICE_ADDRESS, - ADC_PWRDN_CLAMP_CH2, 2, - 0x40, 1); - status |= cx231xx_write_i2c_data(dev, - Colibri_DEVICE_ADDRESS, - ADC_PWRDN_CLAMP_CH3, 2, - 0x00, 1); + status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1, + 0x40); + status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2, + 0x40); + status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3, + 0x00); } else if (avmode == POLARIS_AVMODE_DIGITAL) { - status = cx231xx_write_i2c_data(dev, - Colibri_DEVICE_ADDRESS, - ADC_PWRDN_CLAMP_CH1, 2, - 0x70, 1); - status |= cx231xx_write_i2c_data(dev, - Colibri_DEVICE_ADDRESS, - ADC_PWRDN_CLAMP_CH2, 2, - 0x70, 1); - status |= cx231xx_write_i2c_data(dev, - Colibri_DEVICE_ADDRESS, - ADC_PWRDN_CLAMP_CH3, 2, - 0x70, 1); - - status |= cx231xx_read_i2c_data(dev, - Colibri_DEVICE_ADDRESS, - SUP_BLK_PWRDN, 2, - &colibri_power_status, - 1); - colibri_power_status |= FLD_PWRDN_PD_BANDGAP | + status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1, + 0x70); + status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2, + 0x70); + status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3, + 0x70); + + status |= afe_read_byte(dev, SUP_BLK_PWRDN, + &afe_power_status); + afe_power_status |= FLD_PWRDN_PD_BANDGAP | FLD_PWRDN_PD_BIAS | FLD_PWRDN_PD_TUNECK; - status |= cx231xx_write_i2c_data(dev, - Colibri_DEVICE_ADDRESS, - SUP_BLK_PWRDN, 2, - colibri_power_status, - 1); + status |= afe_write_byte(dev, SUP_BLK_PWRDN, + afe_power_status); } else if (avmode == POLARIS_AVMODE_ENXTERNAL_AV) { - while (colibri_power_status != (FLD_PWRDN_TUNING_BIAS | + while (afe_power_status != (FLD_PWRDN_TUNING_BIAS | FLD_PWRDN_ENABLE_PLL)) { - status = cx231xx_write_i2c_data(dev, - Colibri_DEVICE_ADDRESS, - SUP_BLK_PWRDN, 2, + status = afe_write_byte(dev, SUP_BLK_PWRDN, FLD_PWRDN_TUNING_BIAS | - FLD_PWRDN_ENABLE_PLL, - 1); - status |= cx231xx_read_i2c_data(dev, - Colibri_DEVICE_ADDRESS, - SUP_BLK_PWRDN, 2, - &colibri_power_status, - 1); + FLD_PWRDN_ENABLE_PLL); + status |= afe_read_byte(dev, SUP_BLK_PWRDN, + &afe_power_status); if (status < 0) break; } - status |= cx231xx_write_i2c_data(dev, - Colibri_DEVICE_ADDRESS, - ADC_PWRDN_CLAMP_CH1, 2, - 0x00, 1); - status |= cx231xx_write_i2c_data(dev, - Colibri_DEVICE_ADDRESS, - ADC_PWRDN_CLAMP_CH2, 2, - 0x00, 1); - status |= cx231xx_write_i2c_data(dev, - Colibri_DEVICE_ADDRESS, - ADC_PWRDN_CLAMP_CH3, 2, - 0x40, 1); + status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1, + 0x00); + status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2, + 0x00); + status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3, + 0x40); } else { cx231xx_info("Invalid AV mode input\n"); status = -1; @@ -492,48 +411,44 @@ int cx231xx_colibri_update_power_control(struct cx231xx *dev, return status; } -int cx231xx_colibri_adjust_ref_count(struct cx231xx *dev, u32 video_input) +int cx231xx_afe_adjust_ref_count(struct cx231xx *dev, u32 video_input) { - u32 input_mode = 0; - u32 ntf_mode = 0; + u8 input_mode = 0; + u8 ntf_mode = 0; int status = 0; dev->video_input = video_input; if (video_input == CX231XX_VMUX_TELEVISION) { - status = cx231xx_read_i2c_data(dev, Colibri_DEVICE_ADDRESS, - ADC_INPUT_CH3, 2, &input_mode, 1); - status = cx231xx_read_i2c_data(dev, Colibri_DEVICE_ADDRESS, - ADC_NTF_PRECLMP_EN_CH3, 2, &ntf_mode, - 1); + status = afe_read_byte(dev, ADC_INPUT_CH3, &input_mode); + status = afe_read_byte(dev, ADC_NTF_PRECLMP_EN_CH3, + &ntf_mode); } else { - status = cx231xx_read_i2c_data(dev, Colibri_DEVICE_ADDRESS, - ADC_INPUT_CH1, 2, &input_mode, 1); - status = cx231xx_read_i2c_data(dev, Colibri_DEVICE_ADDRESS, - ADC_NTF_PRECLMP_EN_CH1, 2, &ntf_mode, - 1); + status = afe_read_byte(dev, ADC_INPUT_CH1, &input_mode); + status = afe_read_byte(dev, ADC_NTF_PRECLMP_EN_CH1, + &ntf_mode); } input_mode = (ntf_mode & 0x3) | ((input_mode & 0x6) << 1); switch (input_mode) { case SINGLE_ENDED: - dev->colibri_ref_count = 0x23C; + dev->afe_ref_count = 0x23C; break; case LOW_IF: - dev->colibri_ref_count = 0x24C; + dev->afe_ref_count = 0x24C; break; case EU_IF: - dev->colibri_ref_count = 0x258; + dev->afe_ref_count = 0x258; break; case US_IF: - dev->colibri_ref_count = 0x260; + dev->afe_ref_count = 0x260; break; default: break; } - status = cx231xx_colibri_init_super_block(dev, dev->colibri_ref_count); + status = cx231xx_afe_init_super_block(dev, dev->afe_ref_count); return status; } @@ -541,6 +456,35 @@ int cx231xx_colibri_adjust_ref_count(struct cx231xx *dev, u32 video_input) /****************************************************************************** * V I D E O / A U D I O D E C O D E R C O N T R O L functions * ******************************************************************************/ +static int vid_blk_write_byte(struct cx231xx *dev, u16 saddr, u8 data) +{ + return cx231xx_write_i2c_data(dev, VID_BLK_I2C_ADDRESS, + saddr, 2, data, 1); +} + +static int vid_blk_read_byte(struct cx231xx *dev, u16 saddr, u8 *data) +{ + int status; + u32 temp = 0; + + status = cx231xx_read_i2c_data(dev, VID_BLK_I2C_ADDRESS, + saddr, 2, &temp, 1); + *data = (u8) temp; + return status; +} + +static int vid_blk_write_word(struct cx231xx *dev, u16 saddr, u32 data) +{ + return cx231xx_write_i2c_data(dev, VID_BLK_I2C_ADDRESS, + saddr, 2, data, 4); +} + +static int vid_blk_read_word(struct cx231xx *dev, u16 saddr, u32 *data) +{ + return cx231xx_read_i2c_data(dev, VID_BLK_I2C_ADDRESS, + saddr, 2, data, 4); +} + int cx231xx_set_video_input_mux(struct cx231xx *dev, u8 input) { int status = 0; @@ -601,29 +545,27 @@ int cx231xx_set_decoder_video_input(struct cx231xx *dev, u32 value = 0; if (pin_type != dev->video_input) { - status = cx231xx_colibri_adjust_ref_count(dev, pin_type); + status = cx231xx_afe_adjust_ref_count(dev, pin_type); if (status < 0) { cx231xx_errdev("%s: adjust_ref_count :Failed to set" - "Colibri input mux - errCode [%d]!\n", + "AFE input mux - errCode [%d]!\n", __func__, status); return status; } } - /* call colibri block to set video inputs */ - status = cx231xx_colibri_set_input_mux(dev, input); + /* call afe block to set video inputs */ + status = cx231xx_afe_set_input_mux(dev, input); if (status < 0) { cx231xx_errdev("%s: set_input_mux :Failed to set" - " Colibri input mux - errCode [%d]!\n", + " AFE input mux - errCode [%d]!\n", __func__, status); return status; } switch (pin_type) { case CX231XX_VMUX_COMPOSITE1: - status = cx231xx_read_i2c_data(dev, - HAMMERHEAD_I2C_ADDRESS, - AFE_CTRL, 2, &value, 4); + status = vid_blk_read_word(dev, AFE_CTRL, &value); value |= (0 << 13) | (1 << 4); value &= ~(1 << 5); @@ -631,18 +573,15 @@ int cx231xx_set_decoder_video_input(struct cx231xx *dev, value &= (~(0x1ff8000)); /* set FUNC_MODE[24:23] = 2 IF_MOD[22:15] = 0 */ value |= 0x1000000; - status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, - AFE_CTRL, 2, value, 4); + status = vid_blk_write_word(dev, AFE_CTRL, value); - status = cx231xx_read_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, - OUT_CTRL1, 2, &value, 4); + status = vid_blk_read_word(dev, OUT_CTRL1, &value); value |= (1 << 7); - status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, - OUT_CTRL1, 2, value, 4); + status = vid_blk_write_word(dev, OUT_CTRL1, value); /* Set vip 1.1 output mode */ status = cx231xx_read_modify_write_i2c_dword(dev, - HAMMERHEAD_I2C_ADDRESS, + VID_BLK_I2C_ADDRESS, OUT_CTRL1, FLD_OUT_MODE, OUT_MODE_VIP11); @@ -657,8 +596,7 @@ int cx231xx_set_decoder_video_input(struct cx231xx *dev, } /* Read the DFE_CTRL1 register */ - status = cx231xx_read_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, - DFE_CTRL1, 2, &value, 4); + status = vid_blk_read_word(dev, DFE_CTRL1, &value); /* enable the VBI_GATE_EN */ value |= FLD_VBI_GATE_EN; @@ -667,35 +605,31 @@ int cx231xx_set_decoder_video_input(struct cx231xx *dev, value |= FLD_VGA_AUTO_EN; /* Write it back */ - status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, - DFE_CTRL1, 2, value, 4); + status = vid_blk_write_word(dev, DFE_CTRL1, value); /* Disable auto config of registers */ status = cx231xx_read_modify_write_i2c_dword(dev, - HAMMERHEAD_I2C_ADDRESS, + VID_BLK_I2C_ADDRESS, MODE_CTRL, FLD_ACFG_DIS, cx231xx_set_field(FLD_ACFG_DIS, 1)); /* Set CVBS input mode */ status = cx231xx_read_modify_write_i2c_dword(dev, - HAMMERHEAD_I2C_ADDRESS, + VID_BLK_I2C_ADDRESS, MODE_CTRL, FLD_INPUT_MODE, cx231xx_set_field(FLD_INPUT_MODE, INPUT_MODE_CVBS_0)); break; case CX231XX_VMUX_SVIDEO: /* Disable the use of DIF */ - status = cx231xx_read_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, - AFE_CTRL, 2, &value, 4); + status = vid_blk_read_word(dev, AFE_CTRL, &value); /* set [24:23] [22:15] to 0 */ value &= (~(0x1ff8000)); /* set FUNC_MODE[24:23] = 2 IF_MOD[22:15] = 0 DCR_BYP_CH2[4:4] = 1; */ value |= 0x1000010; - status = cx231xx_write_i2c_data(dev, - HAMMERHEAD_I2C_ADDRESS, - AFE_CTRL, 2, value, 4); + status = vid_blk_write_word(dev, AFE_CTRL, value); /* Tell DIF object to go to baseband mode */ status = cx231xx_dif_set_standard(dev, DIF_USE_BASEBAND); @@ -707,9 +641,7 @@ int cx231xx_set_decoder_video_input(struct cx231xx *dev, } /* Read the DFE_CTRL1 register */ - status = cx231xx_read_i2c_data(dev, - HAMMERHEAD_I2C_ADDRESS, - DFE_CTRL1, 2, &value, 4); + status = vid_blk_read_word(dev, DFE_CTRL1, &value); /* enable the VBI_GATE_EN */ value |= FLD_VBI_GATE_EN; @@ -718,27 +650,23 @@ int cx231xx_set_decoder_video_input(struct cx231xx *dev, value |= FLD_VGA_AUTO_EN; /* Write it back */ - status = cx231xx_write_i2c_data(dev, - HAMMERHEAD_I2C_ADDRESS, - DFE_CTRL1, 2, value, 4); + status = vid_blk_write_word(dev, DFE_CTRL1, value); /* Disable auto config of registers */ status = cx231xx_read_modify_write_i2c_dword(dev, - HAMMERHEAD_I2C_ADDRESS, + VID_BLK_I2C_ADDRESS, MODE_CTRL, FLD_ACFG_DIS, cx231xx_set_field(FLD_ACFG_DIS, 1)); /* Set YC input mode */ status = cx231xx_read_modify_write_i2c_dword(dev, - HAMMERHEAD_I2C_ADDRESS, + VID_BLK_I2C_ADDRESS, MODE_CTRL, FLD_INPUT_MODE, cx231xx_set_field(FLD_INPUT_MODE, INPUT_MODE_YC_1)); /* Chroma to ADC2 */ - status = cx231xx_read_i2c_data(dev, - HAMMERHEAD_I2C_ADDRESS, - AFE_CTRL, 2, &value, 4); + status = vid_blk_read_word(dev, AFE_CTRL, &value); value |= FLD_CHROMA_IN_SEL; /* set the chroma in select */ /* Clear VGA_SEL_CH2 and VGA_SEL_CH3 (bits 7 and 8) @@ -746,11 +674,9 @@ int cx231xx_set_decoder_video_input(struct cx231xx *dev, rather than audio. Only one of the two will be in use. */ value &= ~(FLD_VGA_SEL_CH2 | FLD_VGA_SEL_CH3); - status = cx231xx_write_i2c_data(dev, - HAMMERHEAD_I2C_ADDRESS, - AFE_CTRL, 2, value, 4); + status = vid_blk_write_word(dev, AFE_CTRL, value); - status = cx231xx_colibri_set_mode(dev, AFE_MODE_BASEBAND); + status = cx231xx_afe_set_mode(dev, AFE_MODE_BASEBAND); break; case CX231XX_VMUX_TELEVISION: case CX231XX_VMUX_CABLE: @@ -760,10 +686,7 @@ int cx231xx_set_decoder_video_input(struct cx231xx *dev, case CX231XX_BOARD_CNXT_RDU_250: /* Disable the use of DIF */ - status = cx231xx_read_i2c_data(dev, - HAMMERHEAD_I2C_ADDRESS, - AFE_CTRL, 2, - &value, 4); + status = vid_blk_read_word(dev, AFE_CTRL, &value); value |= (0 << 13) | (1 << 4); value &= ~(1 << 5); @@ -771,24 +694,15 @@ int cx231xx_set_decoder_video_input(struct cx231xx *dev, value &= (~(0x1FF8000)); /* set FUNC_MODE[24:23] = 2 IF_MOD[22:15] = 0 */ value |= 0x1000000; - status = cx231xx_write_i2c_data(dev, - HAMMERHEAD_I2C_ADDRESS, - AFE_CTRL, 2, - value, 4); - - status = cx231xx_read_i2c_data(dev, - HAMMERHEAD_I2C_ADDRESS, - OUT_CTRL1, 2, - &value, 4); + status = vid_blk_write_word(dev, AFE_CTRL, value); + + status = vid_blk_read_word(dev, OUT_CTRL1, &value); value |= (1 << 7); - status = cx231xx_write_i2c_data(dev, - HAMMERHEAD_I2C_ADDRESS, - OUT_CTRL1, 2, - value, 4); + status = vid_blk_write_word(dev, OUT_CTRL1, value); /* Set vip 1.1 output mode */ status = cx231xx_read_modify_write_i2c_dword(dev, - HAMMERHEAD_I2C_ADDRESS, + VID_BLK_I2C_ADDRESS, OUT_CTRL1, FLD_OUT_MODE, OUT_MODE_VIP11); @@ -803,10 +717,7 @@ int cx231xx_set_decoder_video_input(struct cx231xx *dev, } /* Read the DFE_CTRL1 register */ - status = cx231xx_read_i2c_data(dev, - HAMMERHEAD_I2C_ADDRESS, - DFE_CTRL1, 2, - &value, 4); + status = vid_blk_read_word(dev, DFE_CTRL1, &value); /* enable the VBI_GATE_EN */ value |= FLD_VBI_GATE_EN; @@ -815,20 +726,17 @@ int cx231xx_set_decoder_video_input(struct cx231xx *dev, value |= FLD_VGA_AUTO_EN; /* Write it back */ - status = cx231xx_write_i2c_data(dev, - HAMMERHEAD_I2C_ADDRESS, - DFE_CTRL1, 2, - value, 4); + status = vid_blk_write_word(dev, DFE_CTRL1, value); /* Disable auto config of registers */ status = cx231xx_read_modify_write_i2c_dword(dev, - HAMMERHEAD_I2C_ADDRESS, + VID_BLK_I2C_ADDRESS, MODE_CTRL, FLD_ACFG_DIS, cx231xx_set_field(FLD_ACFG_DIS, 1)); /* Set CVBS input mode */ status = cx231xx_read_modify_write_i2c_dword(dev, - HAMMERHEAD_I2C_ADDRESS, + VID_BLK_I2C_ADDRESS, MODE_CTRL, FLD_INPUT_MODE, cx231xx_set_field(FLD_INPUT_MODE, INPUT_MODE_CVBS_0)); @@ -846,25 +754,16 @@ int cx231xx_set_decoder_video_input(struct cx231xx *dev, } /* Make sure bypass is cleared */ - status = cx231xx_read_i2c_data(dev, - HAMMERHEAD_I2C_ADDRESS, - DIF_MISC_CTRL, - 2, &value, 4); + status = vid_blk_read_word(dev, DIF_MISC_CTRL, &value); /* Clear the bypass bit */ value &= ~FLD_DIF_DIF_BYPASS; /* Enable the use of the DIF block */ - status = cx231xx_write_i2c_data(dev, - HAMMERHEAD_I2C_ADDRESS, - DIF_MISC_CTRL, - 2, value, 4); + status = vid_blk_write_word(dev, DIF_MISC_CTRL, value); /* Read the DFE_CTRL1 register */ - status = cx231xx_read_i2c_data(dev, - HAMMERHEAD_I2C_ADDRESS, - DFE_CTRL1, 2, - &value, 4); + status = vid_blk_read_word(dev, DFE_CTRL1, &value); /* Disable the VBI_GATE_EN */ value &= ~FLD_VBI_GATE_EN; @@ -874,10 +773,7 @@ int cx231xx_set_decoder_video_input(struct cx231xx *dev, value |= FLD_VGA_AUTO_EN | FLD_AGC_AUTO_EN | 0x00200000; /* Write it back */ - status = cx231xx_write_i2c_data(dev, - HAMMERHEAD_I2C_ADDRESS, - DFE_CTRL1, 2, - value, 4); + status = vid_blk_write_word(dev, DFE_CTRL1, value); /* Wait until AGC locks up */ msleep(1); @@ -886,39 +782,30 @@ int cx231xx_set_decoder_video_input(struct cx231xx *dev, value &= ~(FLD_VGA_AUTO_EN); /* Write it back */ - status = cx231xx_write_i2c_data(dev, - HAMMERHEAD_I2C_ADDRESS, - DFE_CTRL1, 2, - value, 4); + status = vid_blk_write_word(dev, DFE_CTRL1, value); /* Enable Polaris B0 AGC output */ - status = cx231xx_read_i2c_data(dev, - HAMMERHEAD_I2C_ADDRESS, - PIN_CTRL, 2, - &value, 4); + status = vid_blk_read_word(dev, PIN_CTRL, &value); value |= (FLD_OEF_AGC_RF) | (FLD_OEF_AGC_IFVGA) | (FLD_OEF_AGC_IF); - status = cx231xx_write_i2c_data(dev, - HAMMERHEAD_I2C_ADDRESS, - PIN_CTRL, 2, - value, 4); + status = vid_blk_write_word(dev, PIN_CTRL, value); /* Set vip 1.1 output mode */ status = cx231xx_read_modify_write_i2c_dword(dev, - HAMMERHEAD_I2C_ADDRESS, + VID_BLK_I2C_ADDRESS, OUT_CTRL1, FLD_OUT_MODE, OUT_MODE_VIP11); /* Disable auto config of registers */ status = cx231xx_read_modify_write_i2c_dword(dev, - HAMMERHEAD_I2C_ADDRESS, + VID_BLK_I2C_ADDRESS, MODE_CTRL, FLD_ACFG_DIS, cx231xx_set_field(FLD_ACFG_DIS, 1)); /* Set CVBS input mode */ status = cx231xx_read_modify_write_i2c_dword(dev, - HAMMERHEAD_I2C_ADDRESS, + VID_BLK_I2C_ADDRESS, MODE_CTRL, FLD_INPUT_MODE, cx231xx_set_field(FLD_INPUT_MODE, INPUT_MODE_CVBS_0)); @@ -928,17 +815,11 @@ int cx231xx_set_decoder_video_input(struct cx231xx *dev, /* Clear clamp for channels 2 and 3 (bit 16-17) */ /* Clear droop comp (bit 19-20) */ /* Set VGA_SEL (for audio control) (bit 7-8) */ - status = cx231xx_read_i2c_data(dev, - HAMMERHEAD_I2C_ADDRESS, - AFE_CTRL, 2, - &value, 4); + status = vid_blk_read_word(dev, AFE_CTRL, &value); value |= FLD_VGA_SEL_CH3 | FLD_VGA_SEL_CH2; - status = cx231xx_write_i2c_data(dev, - HAMMERHEAD_I2C_ADDRESS, - AFE_CTRL, 2, - value, 4); + status = vid_blk_write_word(dev, AFE_CTRL, value); break; } @@ -947,17 +828,14 @@ int cx231xx_set_decoder_video_input(struct cx231xx *dev, /* Set raw VBI mode */ status = cx231xx_read_modify_write_i2c_dword(dev, - HAMMERHEAD_I2C_ADDRESS, + VID_BLK_I2C_ADDRESS, OUT_CTRL1, FLD_VBIHACTRAW_EN, cx231xx_set_field(FLD_VBIHACTRAW_EN, 1)); - status = cx231xx_read_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, - OUT_CTRL1, 2, - &value, 4); + status = vid_blk_read_word(dev, OUT_CTRL1, &value); if (value & 0x02) { value |= (1 << 19); - status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, - OUT_CTRL1, 2, value, 4); + status = vid_blk_write_word(dev, OUT_CTRL1, value); } return status; @@ -976,9 +854,7 @@ int cx231xx_do_mode_ctrl_overrides(struct cx231xx *dev) (unsigned int)dev->norm); /* Change the DFE_CTRL3 bp_percent to fix flagging */ - status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, - DFE_CTRL3, 2, - 0xCD3F0280, 4); + status = vid_blk_write_word(dev, DFE_CTRL3, 0xCD3F0280); if (dev->norm & (V4L2_STD_NTSC | V4L2_STD_PAL_M)) { cx231xx_info("do_mode_ctrl_overrides NTSC\n"); @@ -986,22 +862,22 @@ int cx231xx_do_mode_ctrl_overrides(struct cx231xx *dev) /* Move the close caption lines out of active video, adjust the active video start point */ status = cx231xx_read_modify_write_i2c_dword(dev, - HAMMERHEAD_I2C_ADDRESS, + VID_BLK_I2C_ADDRESS, VERT_TIM_CTRL, FLD_VBLANK_CNT, 0x18); status = cx231xx_read_modify_write_i2c_dword(dev, - HAMMERHEAD_I2C_ADDRESS, + VID_BLK_I2C_ADDRESS, VERT_TIM_CTRL, FLD_VACTIVE_CNT, 0x1E6000); status = cx231xx_read_modify_write_i2c_dword(dev, - HAMMERHEAD_I2C_ADDRESS, + VID_BLK_I2C_ADDRESS, VERT_TIM_CTRL, FLD_V656BLANK_CNT, 0x1E000000); status = cx231xx_read_modify_write_i2c_dword(dev, - HAMMERHEAD_I2C_ADDRESS, + VID_BLK_I2C_ADDRESS, HORIZ_TIM_CTRL, FLD_HBLANK_CNT, cx231xx_set_field @@ -1009,12 +885,12 @@ int cx231xx_do_mode_ctrl_overrides(struct cx231xx *dev) } else if (dev->norm & V4L2_STD_SECAM) { cx231xx_info("do_mode_ctrl_overrides SECAM\n"); status = cx231xx_read_modify_write_i2c_dword(dev, - HAMMERHEAD_I2C_ADDRESS, + VID_BLK_I2C_ADDRESS, VERT_TIM_CTRL, FLD_VBLANK_CNT, 0x24); /* Adjust the active video horizontal start point */ status = cx231xx_read_modify_write_i2c_dword(dev, - HAMMERHEAD_I2C_ADDRESS, + VID_BLK_I2C_ADDRESS, HORIZ_TIM_CTRL, FLD_HBLANK_CNT, cx231xx_set_field @@ -1022,12 +898,12 @@ int cx231xx_do_mode_ctrl_overrides(struct cx231xx *dev) } else { cx231xx_info("do_mode_ctrl_overrides PAL\n"); status = cx231xx_read_modify_write_i2c_dword(dev, - HAMMERHEAD_I2C_ADDRESS, + VID_BLK_I2C_ADDRESS, VERT_TIM_CTRL, FLD_VBLANK_CNT, 0x24); /* Adjust the active video horizontal start point */ status = cx231xx_read_modify_write_i2c_dword(dev, - HAMMERHEAD_I2C_ADDRESS, + VID_BLK_I2C_ADDRESS, HORIZ_TIM_CTRL, FLD_HBLANK_CNT, cx231xx_set_field @@ -1047,7 +923,7 @@ int cx231xx_set_audio_input(struct cx231xx *dev, u8 input) ainput = AUDIO_INPUT_TUNER_TV; break; case CX231XX_AMUX_LINE_IN: - status = cx231xx_flatiron_set_audio_input(dev, input); + status = cx231xx_i2s_blk_set_audio_input(dev, input); ainput = AUDIO_INPUT_LINE; break; default: @@ -1064,71 +940,55 @@ int cx231xx_set_audio_decoder_input(struct cx231xx *dev, { u32 dwval; int status; - u32 gen_ctrl; + u8 gen_ctrl; u32 value = 0; /* Put it in soft reset */ - status = cx231xx_read_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, - GENERAL_CTL, 2, &gen_ctrl, 1); + status = vid_blk_read_byte(dev, GENERAL_CTL, &gen_ctrl); gen_ctrl |= 1; - status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, - GENERAL_CTL, 2, gen_ctrl, 1); + status = vid_blk_write_byte(dev, GENERAL_CTL, gen_ctrl); switch (audio_input) { case AUDIO_INPUT_LINE: /* setup AUD_IO control from Merlin paralle output */ value = cx231xx_set_field(FLD_AUD_CHAN1_SRC, AUD_CHAN_SRC_PARALLEL); - status = cx231xx_write_i2c_data(dev, - HAMMERHEAD_I2C_ADDRESS, - AUD_IO_CTRL, 2, value, 4); + status = vid_blk_write_word(dev, AUD_IO_CTRL, value); /* setup input to Merlin, SRC2 connect to AC97 bypass upsample-by-2, slave mode, sony mode, left justify adr 091c, dat 01000000 */ - status = cx231xx_read_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, - AC97_CTL, - 2, &dwval, 4); + status = vid_blk_read_word(dev, AC97_CTL, &dwval); - status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, - AC97_CTL, 2, - (dwval | FLD_AC97_UP2X_BYPASS), 4); + status = vid_blk_write_word(dev, AC97_CTL, + (dwval | FLD_AC97_UP2X_BYPASS)); /* select the parallel1 and SRC3 */ - status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, - BAND_OUT_SEL, 2, + status = vid_blk_write_word(dev, BAND_OUT_SEL, cx231xx_set_field(FLD_SRC3_IN_SEL, 0x0) | cx231xx_set_field(FLD_SRC3_CLK_SEL, 0x0) | - cx231xx_set_field(FLD_PARALLEL1_SRC_SEL, 0x0), - 4); + cx231xx_set_field(FLD_PARALLEL1_SRC_SEL, 0x0)); /* unmute all, AC97 in, independence mode adr 08d0, data 0x00063073 */ - status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, - PATH1_CTL1, 2, 0x00063073, 4); + status = vid_blk_write_word(dev, PATH1_CTL1, 0x00063073); /* set AVC maximum threshold, adr 08d4, dat ffff0024 */ - status = cx231xx_read_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, - PATH1_VOL_CTL, 2, &dwval, 4); - status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, - PATH1_VOL_CTL, 2, - (dwval | FLD_PATH1_AVC_THRESHOLD), - 4); + status = vid_blk_read_word(dev, PATH1_VOL_CTL, &dwval); + status = vid_blk_write_word(dev, PATH1_VOL_CTL, + (dwval | FLD_PATH1_AVC_THRESHOLD)); /* set SC maximum threshold, adr 08ec, dat ffffb3a3 */ - status = cx231xx_read_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, - PATH1_SC_CTL, 2, &dwval, 4); - status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, - PATH1_SC_CTL, 2, - (dwval | FLD_PATH1_SC_THRESHOLD), 4); + status = vid_blk_read_word(dev, PATH1_SC_CTL, &dwval); + status = vid_blk_write_word(dev, PATH1_SC_CTL, + (dwval | FLD_PATH1_SC_THRESHOLD)); break; case AUDIO_INPUT_TUNER_TV: default: /* Setup SRC sources and clocks */ - status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, - BAND_OUT_SEL, 2, + status = vid_blk_write_word(dev, BAND_OUT_SEL, cx231xx_set_field(FLD_SRC6_IN_SEL, 0x00) | cx231xx_set_field(FLD_SRC6_CLK_SEL, 0x01) | cx231xx_set_field(FLD_SRC5_IN_SEL, 0x00) | @@ -1141,29 +1001,26 @@ int cx231xx_set_audio_decoder_input(struct cx231xx *dev, cx231xx_set_field(FLD_AC97_SRC_SEL, 0x03) | cx231xx_set_field(FLD_I2S_SRC_SEL, 0x00) | cx231xx_set_field(FLD_PARALLEL2_SRC_SEL, 0x02) | - cx231xx_set_field(FLD_PARALLEL1_SRC_SEL, 0x01), 4); + cx231xx_set_field(FLD_PARALLEL1_SRC_SEL, 0x01)); /* Setup the AUD_IO control */ - status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, - AUD_IO_CTRL, 2, + status = vid_blk_write_word(dev, AUD_IO_CTRL, cx231xx_set_field(FLD_I2S_PORT_DIR, 0x00) | cx231xx_set_field(FLD_I2S_OUT_SRC, 0x00) | cx231xx_set_field(FLD_AUD_CHAN3_SRC, 0x00) | cx231xx_set_field(FLD_AUD_CHAN2_SRC, 0x00) | - cx231xx_set_field(FLD_AUD_CHAN1_SRC, 0x03), 4); + cx231xx_set_field(FLD_AUD_CHAN1_SRC, 0x03)); - status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, - PATH1_CTL1, 2, 0x1F063870, 4); + status = vid_blk_write_word(dev, PATH1_CTL1, 0x1F063870); /* setAudioStandard(_audio_standard); */ - status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, - PATH1_CTL1, 2, 0x00063870, 4); + status = vid_blk_write_word(dev, PATH1_CTL1, 0x00063870); switch (dev->model) { case CX231XX_BOARD_CNXT_RDE_250: case CX231XX_BOARD_CNXT_RDU_250: status = cx231xx_read_modify_write_i2c_dword(dev, - HAMMERHEAD_I2C_ADDRESS, + VID_BLK_I2C_ADDRESS, CHIP_CTRL, FLD_SIF_EN, cx231xx_set_field(FLD_SIF_EN, 1)); @@ -1181,17 +1038,14 @@ int cx231xx_set_audio_decoder_input(struct cx231xx *dev, break; case AUDIO_INPUT_MUTE: - status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, - PATH1_CTL1, 2, 0x1F011012, 4); + status = vid_blk_write_word(dev, PATH1_CTL1, 0x1F011012); break; } /* Take it out of soft reset */ - status = cx231xx_read_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, - GENERAL_CTL, 2, &gen_ctrl, 1); + status = vid_blk_read_byte(dev, GENERAL_CTL, &gen_ctrl); gen_ctrl &= ~1; - status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, - GENERAL_CTL, 2, gen_ctrl, 1); + status = vid_blk_write_byte(dev, GENERAL_CTL, gen_ctrl); return status; } @@ -1209,12 +1063,10 @@ int cx231xx_resolution_set(struct cx231xx *dev) get_scale(dev, width, height, &hscale, &vscale); /* set horzontal scale */ - status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, - HSCALE_CTRL, 2, hscale, 4); + status = vid_blk_write_word(dev, HSCALE_CTRL, hscale); /* set vertical scale */ - status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, - VSCALE_CTRL, 2, vscale, 4); + status = vid_blk_write_word(dev, VSCALE_CTRL, vscale); return status; } @@ -1227,11 +1079,9 @@ int cx231xx_init_ctrl_pin_status(struct cx231xx *dev) u32 value; int status = 0; - status = cx231xx_read_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, PIN_CTRL, - 2, &value, 4); + status = vid_blk_read_word(dev, PIN_CTRL, &value); value |= (~dev->board.ctl_pin_status_mask); - status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, PIN_CTRL, - 2, value, 4); + status = vid_blk_write_word(dev, PIN_CTRL, value); return status; } @@ -1296,82 +1146,82 @@ int cx231xx_dif_configure_C2HH_for_low_IF(struct cx231xx *dev, u32 mode, /* C2HH */ /* lo if big signal */ status = cx231xx_reg_mask_write(dev, - HAMMERHEAD_I2C_ADDRESS, 32, + VID_BLK_I2C_ADDRESS, 32, AFE_CTRL_C2HH_SRC_CTRL, 30, 31, 0x1); /* FUNC_MODE = DIF */ status = cx231xx_reg_mask_write(dev, - HAMMERHEAD_I2C_ADDRESS, 32, + VID_BLK_I2C_ADDRESS, 32, AFE_CTRL_C2HH_SRC_CTRL, 23, 24, function_mode); /* IF_MODE */ status = cx231xx_reg_mask_write(dev, - HAMMERHEAD_I2C_ADDRESS, 32, + VID_BLK_I2C_ADDRESS, 32, AFE_CTRL_C2HH_SRC_CTRL, 15, 22, 0xFF); /* no inv */ status = cx231xx_reg_mask_write(dev, - HAMMERHEAD_I2C_ADDRESS, 32, + VID_BLK_I2C_ADDRESS, 32, AFE_CTRL_C2HH_SRC_CTRL, 9, 9, 0x1); } else if (standard != DIF_USE_BASEBAND) { if (standard & V4L2_STD_MN) { /* lo if big signal */ status = cx231xx_reg_mask_write(dev, - HAMMERHEAD_I2C_ADDRESS, 32, + VID_BLK_I2C_ADDRESS, 32, AFE_CTRL_C2HH_SRC_CTRL, 30, 31, 0x1); /* FUNC_MODE = DIF */ status = cx231xx_reg_mask_write(dev, - HAMMERHEAD_I2C_ADDRESS, 32, + VID_BLK_I2C_ADDRESS, 32, AFE_CTRL_C2HH_SRC_CTRL, 23, 24, function_mode); /* IF_MODE */ status = cx231xx_reg_mask_write(dev, - HAMMERHEAD_I2C_ADDRESS, 32, + VID_BLK_I2C_ADDRESS, 32, AFE_CTRL_C2HH_SRC_CTRL, 15, 22, 0xb); /* no inv */ status = cx231xx_reg_mask_write(dev, - HAMMERHEAD_I2C_ADDRESS, 32, + VID_BLK_I2C_ADDRESS, 32, AFE_CTRL_C2HH_SRC_CTRL, 9, 9, 0x1); /* 0x124, AUD_CHAN1_SRC = 0x3 */ status = cx231xx_reg_mask_write(dev, - HAMMERHEAD_I2C_ADDRESS, 32, + VID_BLK_I2C_ADDRESS, 32, AUD_IO_CTRL, 0, 31, 0x00000003); } else if ((standard == V4L2_STD_PAL_I) | (standard & V4L2_STD_SECAM)) { /* C2HH setup */ /* lo if big signal */ status = cx231xx_reg_mask_write(dev, - HAMMERHEAD_I2C_ADDRESS, 32, + VID_BLK_I2C_ADDRESS, 32, AFE_CTRL_C2HH_SRC_CTRL, 30, 31, 0x1); /* FUNC_MODE = DIF */ status = cx231xx_reg_mask_write(dev, - HAMMERHEAD_I2C_ADDRESS, 32, + VID_BLK_I2C_ADDRESS, 32, AFE_CTRL_C2HH_SRC_CTRL, 23, 24, function_mode); /* IF_MODE */ status = cx231xx_reg_mask_write(dev, - HAMMERHEAD_I2C_ADDRESS, 32, + VID_BLK_I2C_ADDRESS, 32, AFE_CTRL_C2HH_SRC_CTRL, 15, 22, 0xF); /* no inv */ status = cx231xx_reg_mask_write(dev, - HAMMERHEAD_I2C_ADDRESS, 32, + VID_BLK_I2C_ADDRESS, 32, AFE_CTRL_C2HH_SRC_CTRL, 9, 9, 0x1); } else { /* default PAL BG */ /* C2HH setup */ /* lo if big signal */ status = cx231xx_reg_mask_write(dev, - HAMMERHEAD_I2C_ADDRESS, 32, + VID_BLK_I2C_ADDRESS, 32, AFE_CTRL_C2HH_SRC_CTRL, 30, 31, 0x1); /* FUNC_MODE = DIF */ status = cx231xx_reg_mask_write(dev, - HAMMERHEAD_I2C_ADDRESS, 32, + VID_BLK_I2C_ADDRESS, 32, AFE_CTRL_C2HH_SRC_CTRL, 23, 24, function_mode); /* IF_MODE */ status = cx231xx_reg_mask_write(dev, - HAMMERHEAD_I2C_ADDRESS, 32, + VID_BLK_I2C_ADDRESS, 32, AFE_CTRL_C2HH_SRC_CTRL, 15, 22, 0xE); /* no inv */ status = cx231xx_reg_mask_write(dev, - HAMMERHEAD_I2C_ADDRESS, 32, + VID_BLK_I2C_ADDRESS, 32, AFE_CTRL_C2HH_SRC_CTRL, 9, 9, 0x1); } } @@ -1387,9 +1237,7 @@ int cx231xx_dif_set_standard(struct cx231xx *dev, u32 standard) cx231xx_info("%s: setStandard to %x\n", __func__, standard); - status = cx231xx_read_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, - DIF_MISC_CTRL, 2, &dif_misc_ctrl_value, - 4); + status = vid_blk_read_word(dev, DIF_MISC_CTRL, &dif_misc_ctrl_value); if (standard != DIF_USE_BASEBAND) dev->norm = standard; @@ -1408,182 +1256,154 @@ int cx231xx_dif_set_standard(struct cx231xx *dev, u32 standard) if (standard == DIF_USE_BASEBAND) { /* base band */ /* There is a different SRC_PHASE_INC value for baseband vs. DIF */ - status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, - DIF_SRC_PHASE_INC, 2, 0xDF7DF83, - 4); - status = cx231xx_read_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, - DIF_MISC_CTRL, 2, - &dif_misc_ctrl_value, 4); + status = vid_blk_write_word(dev, DIF_SRC_PHASE_INC, 0xDF7DF83); + status = vid_blk_read_word(dev, DIF_MISC_CTRL, + &dif_misc_ctrl_value); dif_misc_ctrl_value |= FLD_DIF_DIF_BYPASS; - status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, - DIF_MISC_CTRL, 2, - dif_misc_ctrl_value, 4); + status = vid_blk_write_word(dev, DIF_MISC_CTRL, + dif_misc_ctrl_value); } else if (standard & V4L2_STD_PAL_D) { - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, DIF_PLL_CTRL, 0, 31, 0x6503bc0c); - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, DIF_PLL_CTRL1, 0, 31, 0xbd038c85); - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, DIF_PLL_CTRL2, 0, 31, 0x1db4640a); - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, DIF_PLL_CTRL3, 0, 31, 0x00008800); - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, DIF_AGC_IF_REF, 0, 31, 0x444C1380); - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, DIF_AGC_CTRL_IF, 0, 31, 0xDA302600); - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, DIF_AGC_CTRL_INT, 0, 31, 0xDA261700); - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, DIF_AGC_CTRL_RF, 0, 31, 0xDA262600); - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, DIF_AGC_IF_INT_CURRENT, 0, 31, 0x26001700); - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, DIF_AGC_RF_CURRENT, 0, 31, 0x00002660); - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, DIF_VIDEO_AGC_CTRL, 0, 31, 0x72500800); - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, DIF_VID_AUD_OVERRIDE, 0, 31, 0x27000100); - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, DIF_AV_SEP_CTRL, 0, 31, 0x3F3934EA); - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, DIF_COMP_FLT_CTRL, 0, 31, 0x00000000); - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, DIF_SRC_PHASE_INC, 0, 31, 0x1befbf06); - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, DIF_SRC_GAIN_CONTROL, 0, 31, 0x000035e8); - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, DIF_RPT_VARIANCE, 0, 31, 0x00000000); /* Save the Spec Inversion value */ dif_misc_ctrl_value &= FLD_DIF_SPEC_INV; dif_misc_ctrl_value |= 0x3a023F11; } else if (standard & V4L2_STD_PAL_I) { - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, DIF_PLL_CTRL, 0, 31, 0x6503bc0c); - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, DIF_PLL_CTRL1, 0, 31, 0xbd038c85); - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, DIF_PLL_CTRL2, 0, 31, 0x1db4640a); - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, DIF_PLL_CTRL3, 0, 31, 0x00008800); - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, DIF_AGC_IF_REF, 0, 31, 0x444C1380); - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, DIF_AGC_CTRL_IF, 0, 31, 0xDA302600); - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, DIF_AGC_CTRL_INT, 0, 31, 0xDA261700); - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, DIF_AGC_CTRL_RF, 0, 31, 0xDA262600); - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, DIF_AGC_IF_INT_CURRENT, 0, 31, 0x26001700); - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, DIF_AGC_RF_CURRENT, 0, 31, 0x00002660); - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, DIF_VIDEO_AGC_CTRL, 0, 31, 0x72500800); - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, DIF_VID_AUD_OVERRIDE, 0, 31, 0x27000100); - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, DIF_AV_SEP_CTRL, 0, 31, 0x5F39A934); - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, DIF_COMP_FLT_CTRL, 0, 31, 0x00000000); - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, DIF_SRC_PHASE_INC, 0, 31, 0x1befbf06); - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, DIF_SRC_GAIN_CONTROL, 0, 31, 0x000035e8); - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, DIF_RPT_VARIANCE, 0, 31, 0x00000000); /* Save the Spec Inversion value */ dif_misc_ctrl_value &= FLD_DIF_SPEC_INV; dif_misc_ctrl_value |= 0x3a033F11; } else if (standard & V4L2_STD_PAL_M) { /* improved Low Frequency Phase Noise */ - status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, - DIF_PLL_CTRL, 2, 0xFF01FF0C, 4); - status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, - DIF_PLL_CTRL1, 2, 0xbd038c85, - 4); - status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, - DIF_PLL_CTRL2, 2, 0x1db4640a, 4); - status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, - DIF_PLL_CTRL3, 2, 0x00008800, 4); - status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, - DIF_AGC_IF_REF, 2, 0x444C1380, 4); - status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, - DIF_AGC_IF_INT_CURRENT, 2, - 0x26001700, 4); - status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, - DIF_AGC_RF_CURRENT, 2, 0x00002660, - 4); - status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, - DIF_VIDEO_AGC_CTRL, 2, 0x72500800, - 4); - status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, - DIF_VID_AUD_OVERRIDE, 2, 0x27000100, - 4); - status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, - DIF_AV_SEP_CTRL, 2, 0x012c405d, 4); - status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, - DIF_COMP_FLT_CTRL, 2, 0x009f50c1, 4); - status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, - DIF_SRC_PHASE_INC, 2, 0x1befbf06, 4); - status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, - DIF_SRC_GAIN_CONTROL, 2, 0x000035e8, - 4); - status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, - DIF_SOFT_RST_CTRL_REVB, 2, - 0x00000000, 4); + status = vid_blk_write_word(dev, DIF_PLL_CTRL, 0xFF01FF0C); + status = vid_blk_write_word(dev, DIF_PLL_CTRL1, 0xbd038c85); + status = vid_blk_write_word(dev, DIF_PLL_CTRL2, 0x1db4640a); + status = vid_blk_write_word(dev, DIF_PLL_CTRL3, 0x00008800); + status = vid_blk_write_word(dev, DIF_AGC_IF_REF, 0x444C1380); + status = vid_blk_write_word(dev, DIF_AGC_IF_INT_CURRENT, + 0x26001700); + status = vid_blk_write_word(dev, DIF_AGC_RF_CURRENT, + 0x00002660); + status = vid_blk_write_word(dev, DIF_VIDEO_AGC_CTRL, + 0x72500800); + status = vid_blk_write_word(dev, DIF_VID_AUD_OVERRIDE, + 0x27000100); + status = vid_blk_write_word(dev, DIF_AV_SEP_CTRL, 0x012c405d); + status = vid_blk_write_word(dev, DIF_COMP_FLT_CTRL, + 0x009f50c1); + status = vid_blk_write_word(dev, DIF_SRC_PHASE_INC, + 0x1befbf06); + status = vid_blk_write_word(dev, DIF_SRC_GAIN_CONTROL, + 0x000035e8); + status = vid_blk_write_word(dev, DIF_SOFT_RST_CTRL_REVB, + 0x00000000); /* Save the Spec Inversion value */ dif_misc_ctrl_value &= FLD_DIF_SPEC_INV; dif_misc_ctrl_value |= 0x3A0A3F10; } else if (standard & (V4L2_STD_PAL_N | V4L2_STD_PAL_Nc)) { /* improved Low Frequency Phase Noise */ - status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, - DIF_PLL_CTRL, 2, 0xFF01FF0C, 4); - status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, - DIF_PLL_CTRL1, 2, 0xbd038c85, 4); - status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, - DIF_PLL_CTRL2, 2, 0x1db4640a, 4); - status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, - DIF_PLL_CTRL3, 2, 0x00008800, 4); - status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, - DIF_AGC_IF_REF, 2, 0x444C1380, 4); - status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, - DIF_AGC_IF_INT_CURRENT, 2, - 0x26001700, 4); - status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, - DIF_AGC_RF_CURRENT, 2, 0x00002660, - 4); - status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, - DIF_VIDEO_AGC_CTRL, 2, 0x72500800, - 4); - status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, - DIF_VID_AUD_OVERRIDE, 2, 0x27000100, - 4); - status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, - DIF_AV_SEP_CTRL, 2, 0x012c405d, 4); - status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, - DIF_COMP_FLT_CTRL, 2, 0x009f50c1, 4); - status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, - DIF_SRC_PHASE_INC, 2, 0x1befbf06, 4); - status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, - DIF_SRC_GAIN_CONTROL, 2, 0x000035e8, - 4); - status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, - DIF_SOFT_RST_CTRL_REVB, 2, - 0x00000000, 4); + status = vid_blk_write_word(dev, DIF_PLL_CTRL, 0xFF01FF0C); + status = vid_blk_write_word(dev, DIF_PLL_CTRL1, 0xbd038c85); + status = vid_blk_write_word(dev, DIF_PLL_CTRL2, 0x1db4640a); + status = vid_blk_write_word(dev, DIF_PLL_CTRL3, 0x00008800); + status = vid_blk_write_word(dev, DIF_AGC_IF_REF, 0x444C1380); + status = vid_blk_write_word(dev, DIF_AGC_IF_INT_CURRENT, + 0x26001700); + status = vid_blk_write_word(dev, DIF_AGC_RF_CURRENT, + 0x00002660); + status = vid_blk_write_word(dev, DIF_VIDEO_AGC_CTRL, + 0x72500800); + status = vid_blk_write_word(dev, DIF_VID_AUD_OVERRIDE, + 0x27000100); + status = vid_blk_write_word(dev, DIF_AV_SEP_CTRL, + 0x012c405d); + status = vid_blk_write_word(dev, DIF_COMP_FLT_CTRL, + 0x009f50c1); + status = vid_blk_write_word(dev, DIF_SRC_PHASE_INC, + 0x1befbf06); + status = vid_blk_write_word(dev, DIF_SRC_GAIN_CONTROL, + 0x000035e8); + status = vid_blk_write_word(dev, DIF_SOFT_RST_CTRL_REVB, + 0x00000000); /* Save the Spec Inversion value */ dif_misc_ctrl_value &= FLD_DIF_SPEC_INV; dif_misc_ctrl_value = 0x3A093F10; @@ -1591,45 +1411,45 @@ int cx231xx_dif_set_standard(struct cx231xx *dev, u32 standard) (V4L2_STD_SECAM_B | V4L2_STD_SECAM_D | V4L2_STD_SECAM_G | V4L2_STD_SECAM_K | V4L2_STD_SECAM_K1)) { - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, DIF_PLL_CTRL, 0, 31, 0x6503bc0c); - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, DIF_PLL_CTRL1, 0, 31, 0xbd038c85); - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, DIF_PLL_CTRL2, 0, 31, 0x1db4640a); - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, DIF_PLL_CTRL3, 0, 31, 0x00008800); - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, DIF_AGC_IF_REF, 0, 31, 0x888C0380); - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, DIF_AGC_CTRL_IF, 0, 31, 0xe0262600); - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, DIF_AGC_CTRL_INT, 0, 31, 0xc2171700); - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, DIF_AGC_CTRL_RF, 0, 31, 0xc2262600); - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, DIF_AGC_IF_INT_CURRENT, 0, 31, 0x26001700); - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, DIF_AGC_RF_CURRENT, 0, 31, 0x00002660); - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, DIF_VID_AUD_OVERRIDE, 0, 31, 0x27000100); - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, DIF_AV_SEP_CTRL, 0, 31, 0x3F3530ec); - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, DIF_COMP_FLT_CTRL, 0, 31, 0x00000000); - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, DIF_SRC_PHASE_INC, 0, 31, 0x1befbf06); - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, DIF_SRC_GAIN_CONTROL, 0, 31, 0x000035e8); - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, DIF_RPT_VARIANCE, 0, 31, 0x00000000); - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, DIF_VIDEO_AGC_CTRL, 0, 31, 0xf4000000); @@ -1638,45 +1458,45 @@ int cx231xx_dif_set_standard(struct cx231xx *dev, u32 standard) dif_misc_ctrl_value |= 0x3a023F11; } else if (standard & (V4L2_STD_SECAM_L | V4L2_STD_SECAM_LC)) { /* Is it SECAM_L1? */ - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, DIF_PLL_CTRL, 0, 31, 0x6503bc0c); - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, DIF_PLL_CTRL1, 0, 31, 0xbd038c85); - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, DIF_PLL_CTRL2, 0, 31, 0x1db4640a); - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, DIF_PLL_CTRL3, 0, 31, 0x00008800); - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, DIF_AGC_IF_REF, 0, 31, 0x888C0380); - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, DIF_AGC_CTRL_IF, 0, 31, 0xe0262600); - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, DIF_AGC_CTRL_INT, 0, 31, 0xc2171700); - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, DIF_AGC_CTRL_RF, 0, 31, 0xc2262600); - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, DIF_AGC_IF_INT_CURRENT, 0, 31, 0x26001700); - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, DIF_AGC_RF_CURRENT, 0, 31, 0x00002660); - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, DIF_VID_AUD_OVERRIDE, 0, 31, 0x27000100); - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, DIF_AV_SEP_CTRL, 0, 31, 0x3F3530ec); - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, DIF_COMP_FLT_CTRL, 0, 31, 0x00000000); - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, DIF_SRC_PHASE_INC, 0, 31, 0x1befbf06); - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, DIF_SRC_GAIN_CONTROL, 0, 31, 0x000035e8); - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, DIF_RPT_VARIANCE, 0, 31, 0x00000000); - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, DIF_VIDEO_AGC_CTRL, 0, 31, 0xf2560000); @@ -1694,91 +1514,78 @@ int cx231xx_dif_set_standard(struct cx231xx *dev, u32 standard) the pll freq word is 0x03420c49 */ - status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, - DIF_PLL_CTRL, 2, 0x6503BC0C, 4); - status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, - DIF_PLL_CTRL1, 2, 0xBD038C85, 4); - status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, - DIF_PLL_CTRL2, 2, 0x1DB4640A, 4); - status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, - DIF_PLL_CTRL3, 2, 0x00008800, 4); - status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, - DIF_AGC_IF_REF, 2, 0x444C0380, 4); - status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, - DIF_AGC_IF_INT_CURRENT, 2, - 0x26001700, 4); - status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, - DIF_AGC_RF_CURRENT, 2, 0x00002660, - 4); - status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, - DIF_VIDEO_AGC_CTRL, 2, 0x04000800, - 4); - status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, - DIF_VID_AUD_OVERRIDE, 2, 0x27000100, - 4); - status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, - DIF_AV_SEP_CTRL, 2, 0x01296e1f, 4); - - status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, - DIF_COMP_FLT_CTRL, 2, 0x009f50c1, 4); - status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, - DIF_SRC_PHASE_INC, 2, 0x1befbf06, 4); - status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, - DIF_SRC_GAIN_CONTROL, 2, 0x000035e8, - 4); - - status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, - DIF_AGC_CTRL_IF, 2, 0xC2262600, 4); - status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, - DIF_AGC_CTRL_INT, 2, 0xC2262600, 4); - status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, - DIF_AGC_CTRL_RF, 2, 0xC2262600, 4); + status = vid_blk_write_word(dev, DIF_PLL_CTRL, 0x6503BC0C); + status = vid_blk_write_word(dev, DIF_PLL_CTRL1, 0xBD038C85); + status = vid_blk_write_word(dev, DIF_PLL_CTRL2, 0x1DB4640A); + status = vid_blk_write_word(dev, DIF_PLL_CTRL3, 0x00008800); + status = vid_blk_write_word(dev, DIF_AGC_IF_REF, 0x444C0380); + status = vid_blk_write_word(dev, DIF_AGC_IF_INT_CURRENT, + 0x26001700); + status = vid_blk_write_word(dev, DIF_AGC_RF_CURRENT, + 0x00002660); + status = vid_blk_write_word(dev, DIF_VIDEO_AGC_CTRL, + 0x04000800); + status = vid_blk_write_word(dev, DIF_VID_AUD_OVERRIDE, + 0x27000100); + status = vid_blk_write_word(dev, DIF_AV_SEP_CTRL, 0x01296e1f); + + status = vid_blk_write_word(dev, DIF_COMP_FLT_CTRL, + 0x009f50c1); + status = vid_blk_write_word(dev, DIF_SRC_PHASE_INC, + 0x1befbf06); + status = vid_blk_write_word(dev, DIF_SRC_GAIN_CONTROL, + 0x000035e8); + + status = vid_blk_write_word(dev, DIF_AGC_CTRL_IF, 0xC2262600); + status = vid_blk_write_word(dev, DIF_AGC_CTRL_INT, + 0xC2262600); + status = vid_blk_write_word(dev, DIF_AGC_CTRL_RF, 0xC2262600); /* Save the Spec Inversion value */ dif_misc_ctrl_value &= FLD_DIF_SPEC_INV; dif_misc_ctrl_value |= 0x3a003F10; } else { /* default PAL BG */ - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, DIF_PLL_CTRL, 0, 31, 0x6503bc0c); - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, DIF_PLL_CTRL1, 0, 31, 0xbd038c85); - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, DIF_PLL_CTRL2, 0, 31, 0x1db4640a); - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, DIF_PLL_CTRL3, 0, 31, 0x00008800); - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, DIF_AGC_IF_REF, 0, 31, 0x444C1380); - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, DIF_AGC_CTRL_IF, 0, 31, 0xDA302600); - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, DIF_AGC_CTRL_INT, 0, 31, 0xDA261700); - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, DIF_AGC_CTRL_RF, 0, 31, 0xDA262600); - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, DIF_AGC_IF_INT_CURRENT, 0, 31, 0x26001700); - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, DIF_AGC_RF_CURRENT, 0, 31, 0x00002660); - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, DIF_VIDEO_AGC_CTRL, 0, 31, 0x72500800); - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, DIF_VID_AUD_OVERRIDE, 0, 31, 0x27000100); - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, DIF_AV_SEP_CTRL, 0, 31, 0x3F3530EC); - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, DIF_COMP_FLT_CTRL, 0, 31, 0x00A653A8); - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, DIF_SRC_PHASE_INC, 0, 31, 0x1befbf06); - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, DIF_SRC_GAIN_CONTROL, 0, 31, 0x000035e8); - status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, + status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, DIF_RPT_VARIANCE, 0, 31, 0x00000000); /* Save the Spec Inversion value */ dif_misc_ctrl_value &= FLD_DIF_SPEC_INV; @@ -1796,9 +1603,7 @@ int cx231xx_dif_set_standard(struct cx231xx *dev, u32 standard) dif_misc_ctrl_value = 0x7a080000; /* Write the calculated value for misc ontrol register */ - status = - cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, DIF_MISC_CTRL, - 2, dif_misc_ctrl_value, 4); + status = vid_blk_write_word(dev, DIF_MISC_CTRL, dif_misc_ctrl_value); return status; } @@ -1809,13 +1614,11 @@ int cx231xx_tuner_pre_channel_change(struct cx231xx *dev) u32 dwval; /* Set the RF and IF k_agc values to 3 */ - status = cx231xx_read_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, - DIF_AGC_IF_REF, 2, &dwval, 4); + status = vid_blk_read_word(dev, DIF_AGC_IF_REF, &dwval); dwval &= ~(FLD_DIF_K_AGC_RF | FLD_DIF_K_AGC_IF); dwval |= 0x33000000; - status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, - DIF_AGC_IF_REF, 2, dwval, 4); + status = vid_blk_write_word(dev, DIF_AGC_IF_REF, dwval); return status; } @@ -1827,8 +1630,7 @@ int cx231xx_tuner_post_channel_change(struct cx231xx *dev) /* Set the RF and IF k_agc values to 4 for PAL/NTSC and 8 for * SECAM L/B/D standards */ - status = cx231xx_read_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, - DIF_AGC_IF_REF, 2, &dwval, 4); + status = vid_blk_read_word(dev, DIF_AGC_IF_REF, &dwval); dwval &= ~(FLD_DIF_K_AGC_RF | FLD_DIF_K_AGC_IF); if (dev->norm & (V4L2_STD_SECAM_L | V4L2_STD_SECAM_B | @@ -1837,63 +1639,62 @@ int cx231xx_tuner_post_channel_change(struct cx231xx *dev) else dwval |= 0x44000000; - status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, - DIF_AGC_IF_REF, 2, dwval, 4); + status = vid_blk_write_word(dev, DIF_AGC_IF_REF, dwval); return status; } /****************************************************************************** - * F L A T I R O N - B L O C K C O N T R O L functions * + * I 2 S - B L O C K C O N T R O L functions * ******************************************************************************/ -int cx231xx_flatiron_initialize(struct cx231xx *dev) +int cx231xx_i2s_blk_initialize(struct cx231xx *dev) { int status = 0; u32 value; - status = cx231xx_read_i2c_data(dev, Flatrion_DEVICE_ADDRESS, + status = cx231xx_read_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS, CH_PWR_CTRL1, 1, &value, 1); /* enables clock to delta-sigma and decimation filter */ value |= 0x80; - status = cx231xx_write_i2c_data(dev, Flatrion_DEVICE_ADDRESS, + status = cx231xx_write_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS, CH_PWR_CTRL1, 1, value, 1); /* power up all channel */ - status = cx231xx_write_i2c_data(dev, Flatrion_DEVICE_ADDRESS, + status = cx231xx_write_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS, CH_PWR_CTRL2, 1, 0x00, 1); return status; } -int cx231xx_flatiron_update_power_control(struct cx231xx *dev, +int cx231xx_i2s_blk_update_power_control(struct cx231xx *dev, enum AV_MODE avmode) { int status = 0; u32 value = 0; if (avmode != POLARIS_AVMODE_ENXTERNAL_AV) { - status = cx231xx_read_i2c_data(dev, Flatrion_DEVICE_ADDRESS, + status = cx231xx_read_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS, CH_PWR_CTRL2, 1, &value, 1); value |= 0xfe; - status = cx231xx_write_i2c_data(dev, Flatrion_DEVICE_ADDRESS, + status = cx231xx_write_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS, CH_PWR_CTRL2, 1, value, 1); } else { - status = cx231xx_write_i2c_data(dev, Flatrion_DEVICE_ADDRESS, + status = cx231xx_write_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS, CH_PWR_CTRL2, 1, 0x00, 1); } return status; } -/* set flatiron for audio input types */ -int cx231xx_flatiron_set_audio_input(struct cx231xx *dev, u8 audio_input) +/* set i2s_blk for audio input types */ +int cx231xx_i2s_blk_set_audio_input(struct cx231xx *dev, u8 audio_input) { int status = 0; switch (audio_input) { case CX231XX_AMUX_LINE_IN: - status = cx231xx_write_i2c_data(dev, Flatrion_DEVICE_ADDRESS, + status = cx231xx_write_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS, CH_PWR_CTRL2, 1, 0x00, 1); - status = cx231xx_write_i2c_data(dev, Flatrion_DEVICE_ADDRESS, + status = cx231xx_write_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS, CH_PWR_CTRL1, 1, 0x80, 1); break; case CX231XX_AMUX_VIDEO: @@ -2114,11 +1915,11 @@ int cx231xx_set_power_mode(struct cx231xx *dev, enum AV_MODE mode) msleep(PWR_SLEEP_INTERVAL); } - /* update power control for colibri */ - status = cx231xx_colibri_update_power_control(dev, mode); + /* update power control for afe */ + status = cx231xx_afe_update_power_control(dev, mode); - /* update power control for flatiron */ - status = cx231xx_flatiron_update_power_control(dev, mode); + /* update power control for i2s_blk */ + status = cx231xx_i2s_blk_update_power_control(dev, mode); status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, PWR_CTL_EN, value, 4); -- cgit v1.2.3 From a3ec55c8056a094d349074f26b9f855010a94ef3 Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Tue, 7 Apr 2009 22:49:46 +0000 Subject: V4L/DVB: cx231xx: remove unused #include 's From: Huang Weiyi Remove unused #include 's in drivers/media/video/cx231xx/cx231xx-avcore.c drivers/media/video/cx231xx/cx231xx-vbi.c Signed-off-by: Huang Weiyi Signed-off-by: Mauro Carvalho Chehab --- linux/drivers/media/video/cx231xx/cx231xx-avcore.c | 1 - 1 file changed, 1 deletion(-) (limited to 'linux/drivers/media/video/cx231xx/cx231xx-avcore.c') diff --git a/linux/drivers/media/video/cx231xx/cx231xx-avcore.c b/linux/drivers/media/video/cx231xx/cx231xx-avcore.c index 1be3881be..6a9464079 100644 --- a/linux/drivers/media/video/cx231xx/cx231xx-avcore.c +++ b/linux/drivers/media/video/cx231xx/cx231xx-avcore.c @@ -29,7 +29,6 @@ #include #include #include -#include #include #include -- cgit v1.2.3 From 0b81474a751308c61db74ee4088c8b557b913c3c Mon Sep 17 00:00:00 2001 From: Trent Piepho Date: Sat, 30 May 2009 17:45:46 -0700 Subject: cx231xx: TRY_FMT should not actually set anything From: Trent Piepho In the TRY_FMT handler the function get_scale() is called to find what the scaler hardware will produce for a requested size. The problem is that get_scale(struct cx231xx *dev, ..., unsigned int *vscale, unsigned int *hscale) saves the calculated scale values into both the pointer arguments and into dev's hscale and vscale fields. TRY_FMT shouldn't actually change anything in the device state. The code to in get_scale() that writes to dev->[hv]scale can just be deleted. In all cases when dev's fields should be modified, get_scale() was called with get_scale(dev, ..., &dev->hscale, &dev->vscale), so dev was getting updated anyway. This didn't actually cause a problem because nothing ever actually made use of the hscale and vscale fields. I changed cx231xx_resolution_set() to use those fields rather than re-calculate them with a call to get_scale(). Updating [hv]scale in cx231xx_resolution_set() isn't necessary because every call of cx231xx_resolution_set() was already preceded by a call to get_scale() or setting the [hv]scale fields, so they will be always be up-to-date w.r.t. width and height. Removing the call to get_scale() from cx231xx_resolution_set() allowed making get_scale() a static function, which is a good thing for something with such a short name. There is already another function with the same name in the em28xx driver, but that one is static. Priority: normal Signed-off-by: Trent Piepho --- linux/drivers/media/video/cx231xx/cx231xx-avcore.c | 17 ++++------------- 1 file changed, 4 insertions(+), 13 deletions(-) (limited to 'linux/drivers/media/video/cx231xx/cx231xx-avcore.c') diff --git a/linux/drivers/media/video/cx231xx/cx231xx-avcore.c b/linux/drivers/media/video/cx231xx/cx231xx-avcore.c index 6a9464079..bbbb3f50e 100644 --- a/linux/drivers/media/video/cx231xx/cx231xx-avcore.c +++ b/linux/drivers/media/video/cx231xx/cx231xx-avcore.c @@ -1052,22 +1052,13 @@ int cx231xx_set_audio_decoder_input(struct cx231xx *dev, /* Set resolution of the video */ int cx231xx_resolution_set(struct cx231xx *dev) { - int width, height; - u32 hscale, vscale; - int status = 0; - - width = dev->width; - height = dev->height; - - get_scale(dev, width, height, &hscale, &vscale); - /* set horzontal scale */ - status = vid_blk_write_word(dev, HSCALE_CTRL, hscale); + int status = vid_blk_write_word(dev, HSCALE_CTRL, dev->hscale); + if (status) + return status; /* set vertical scale */ - status = vid_blk_write_word(dev, VSCALE_CTRL, vscale); - - return status; + return vid_blk_write_word(dev, VSCALE_CTRL, dev->vscale); } /****************************************************************************** -- cgit v1.2.3 From ba1331c45ace13485b9d68ac3f2d574f1e80e229 Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Sat, 20 Jun 2009 14:21:37 +0200 Subject: cx231xx: fix uninitialized variable. From: Hans Verkuil The variable 'rc' could be used uninitialized in the cx231xx_capture_start function. Sri informed me that it should be initialized to -1. Priority: normal Signed-off-by: Hans Verkuil Signed-off-by: Mauro Carvalho Chehab --- linux/drivers/media/video/cx231xx/cx231xx-avcore.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'linux/drivers/media/video/cx231xx/cx231xx-avcore.c') diff --git a/linux/drivers/media/video/cx231xx/cx231xx-avcore.c b/linux/drivers/media/video/cx231xx/cx231xx-avcore.c index bbbb3f50e..28f48f41f 100644 --- a/linux/drivers/media/video/cx231xx/cx231xx-avcore.c +++ b/linux/drivers/media/video/cx231xx/cx231xx-avcore.c @@ -2046,7 +2046,7 @@ int cx231xx_initialize_stream_xfer(struct cx231xx *dev, u32 media_type) int cx231xx_capture_start(struct cx231xx *dev, int start, u8 media_type) { - int rc; + int rc = -1; u32 ep_mask = -1; struct pcb_config *pcb_config; -- cgit v1.2.3