Age | Commit message (Collapse) | Author |
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While here, remove some other register dumping that is better done by
i830DumpRegs().
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Also replaced by not spamming unrelated ADPA register. At least, it had sure
better not be related.
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DPLL register contains clock setup, so it cannot be written
from the output mode_set function or 'bad things' happen.
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Also, fix buffer overflow in i830_debug.c
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This behavior matches what we did before when LVDS worked.
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To avoid requiring RandR 1.2 in the X server, use the
xf86 Crtc and Output structures as the basis for the default configuration
computation (and, eventually, the config-file based configuration as well).
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We should use card_fmt for src/mask picture, and use dest color
buffer format helper. Also fix wrong name for G965 texture formats,
and pict_x1r5g5b5 isn't supported by sampler engine.
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* Replace the cvs source url in the long description with an XS-Vcs-Git
control field and a reference to the xf86-video-intel module.
Added a link to www.X.org.
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* Apply upstream patch 1-overlay_fix_lockup.patch (git commit
e065324661ad08b3b359136f48090232f6138959, upstream bug #5774).
Should remove remaining lockup problems in I830WaitLpRing().
Closes: #272294.
* While we're at it, apply upstream patch 11-xv_lockup.patch (git
commit fbb376bd1a4daad4c86e349df98438989ce173f1, upstream bug
#8594), fixing lockups related to Xv. We'll have no lockup bugs in
etch, dammit! Closes: #397485.
* get these patches into unstable and thence etch.
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Conflicts:
src/i830_display.c
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It compiles. It definitely doesn't run.
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RandR structures must be re-created when the server reinitializes,
but the driver PreInit function is not re-invoked. Recreate them
manually in this case during ScreenInit.
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fix corrupt in some subspans
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High pixel clock modes on pipe A of an 8xx chip require
DOUBLE_WIDE mode. It's supposed to be modes > 180MHz or so,
but the board I have requires DOUBLE_WIDE mode for clocks > 108MHz
or so. The limit is related to the core clock speed of the chip, which
can be found indirectly through PCI config space. None of the possible
values explain why this board needs this mode for these relatively low
clock rates though.
Also, create tables of data for the PLL computation and use them
instead of code. I think it's cleaner looking. It is also untested on
9xx. It'll work. Really.
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Our driver private is stored in the bus that we set up, not the DDC device
that xf86 code does.
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Also, don't bother reading the PP_CONTROL register to try to get LVDS status --
that's what PP_STATUS is for.
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Use new TV output condition (all 9xx except 915g)
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Yes, this means not detecting TV hotplug when two outputs are
already running. An alternative would be to turn off one of the other
outputs temporarily, but that would cause flashing. Something to consider.
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Some output detection requires a crtc for load detection, perform all of the
output detection before allocating any crtcs so that there will be a free
crtc for any load detection. Avoids losing TV detection when two monitors
are connected.
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Correctly interpret mode == NULL as CRTC disable, make sure the CRTC is
disabled in this case.
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While the register is laid out suggesting that you can read a low value while
driving the output high, and the I2C spec seems to indicate that you should be
able to as well, and on some hardware this works successfully, on the i865 and
perhaps some other chips it doesn't. So, if we're not holding the clock or
data pin low during GetBits, tristate the pin so that we can successfully read.
This fixes i865 analog (VGA) DDC so it successfully sees slave acks.
Also, improve the I2C bit-banging debugging.
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Outputs and Crtcs now have a driver-independent representation which should
permit generic code to control RandR 1.2 and startup configuration.
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Attempts to override functions in core server fail, so use
new names instead.
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Change function names, create separate i830_randr.h header file
to contain definitions.
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Conflicts:
man/i810.man
src/Makefile.am
src/i830.h
src/i830_driver.c
src/i830_rotate.c
src/i830_video.c
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