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Front buffer tiling is now disabled with G965 and XAA. Some of the acceleration
that i830_xaa.c does can't be supported on tiled buffers.
Adds a tiling field to struct i830_memory, and uses it instead of separate
variables for each potential tiled buffer.
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TV mode names used to contain the signalling standard along with the pixel
size. The signalling has been moved to the TV_FORMAT property, but the
allocation and initialization of the mode name was left a bit messy as a
result.
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Remove an extra "FBC enabled" message from i830_memory.c (only report errors
if they occur), and don't print the "forcing FBC on" message if tiling was
already enabled, as it's redundant and confusing.
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This should be close to the last set of tiling fixes for 965 chipsets.
Prior to this commit, the 965 composite hook didn't take tiling into
account, nor did 965 textured video, which caused display corruption.
However, there seems to be at least one last bug to squash--on occasion,
a configuration with tiling enabled won't properly display text. This
is likely another tiling related problem with the composite hook.
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until we really implement it, OSD can't work for now.
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systems don't reduce the range of backlight values we can present to the user
(cherry picked from commit 0da4f2b0cd7203377ad10407928a367b8c6d310e)
Conflicts:
src/i830.h
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(cherry picked from commit 322a163cfbda885adc6bb09c1f976d36617ea83b)
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Note that this is a slowdown in text rendering due to the high overhead of our
compositing setup, but appears to be correct according to rendercheck.
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We don't have extra attributes than Xv port.
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Conflicts:
src/i830_exa.c
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The 915 and earlier appear to respect the fence registers, while only the 965
requires the per-operation tiling setting and pitch shifting. This will also
fix issues with rendering on the 965 involving multiple cliprects, where the
pitch would get divided repeatedly.
This removes the offset < 4096 fallback, which essentially resulted in no
acceleration to tiled buffers, hiding the issues.
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be called many times for the same pixmap, and we don't want
to keep dividing the pitch by 4.
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and put wrap function in driver xvmc priv instead of per xv port priv
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Reading the docs too literally can cause you to hide bugs with false fixes...
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PrepareSolid - combine pI830->tiling and frontbuffer checks into new exaPixmapTiled function for readability
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ssh://git.freedesktop.org/git/xorg/driver/xf86-video-intel
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- actually enable tiling in DSP(A|B)CNTR if needed
- add logic to EXA routines for tiled case (still needs work)
- enable/disable fbc on DPMS events (meant moving functions higher in file)
- fix fence register pitch programming (use correct pitch instead of kludged value)
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- add support for 965GM
- make sure legacy enabled systems don't reduce the range of backlight values we can present to the user
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(cherry picked from commit 15f71edba37738f8ba279fa07452fda10cc65298)
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From issue report http://lists.freedesktop.org/archives/xorg/2007-July/026644.html
(cherry picked from commit f403a50afbcef1e54f554481c72037338bd5357c)
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This one trys to use a flag for possible quirks. It adds a quirk
for my Lenovo T61 TV output, and ports some origin LVDS quirks to it.
(cherry picked from commit 34c82ad7ce83394db47588693b578cf91991bf1c)
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A number of other interfaces of ours don't allow buffer offsets to be updated
after screeninit. This attempts to catalog why for each one, so that they
can be fixed one by one.
This happens to restore the EXA offscreen allocator for now, as a fixed-offset
object.
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The return value of GetScreenPixmap before CreateScreenResources is not, in
fact, a pixmap.
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If not available, AIGLX init will fail. While here, simplify DRIINFO tests
since we refuse to init with a version queried less than the version we
compiled against, anyway.
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From issue report http://lists.freedesktop.org/archives/xorg/2007-July/026644.html
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This one trys to use a flag for possible quirks. It adds a quirk
for my Lenovo T61 TV output, and ports some origin LVDS quirks to it.
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The upper bits would have been inappropriately dropped on G33-class hardware,
and on G965-class hardware in a 32-bit environment. The only use of physical
addresses on these should be for FBC, though, and FBC requires addresses
below 4GB. This is unresolved.
(cherry picked from commit 88f8b688e2316ae4a1f7485f0010ce90de54783a)
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Reported by A. Costa" <agcosta@gis.net> in
http://bugs.debian.org/cgi-bin/bugreport.cgi?bug=432061
(cherry picked from commit 0fd3ba0518b3cde9ca0e4e2fc1854c00d8a43d5c)
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which do have new host bridge ids
(cherry picked from commit b1af2c0e01c54ef1d40fd0ca1ede29a1dd7ed97b)
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CRT blanking needn't be adjusted to perform load detection on 9xx chips, and
the 8xx load detection path now adjusts blanking just during load detection.
Adjusting the blanking interval turned out to cause many monitors to fail to
sync.
(cherry picked from commit ff2be3995d33f9e4b7f63b380f166b6168c9b9c6)
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If the pipe or output have been set to DPMSOff, then load detection will not
work correctly. Also, share the load detection configuration code between
crt and tv outputs.
(cherry picked from commit 00f4587025a3879626623135b0a153fcdb906719)
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Instead of always adding blanking to mode lines, use the FORCE_BORDER option
on i9xx hardware where it works, and dynamically add a bit of border if
necessary on i8xx hardware to make load detection work. This may cause
flashing when a usable crtc is not otherwise idle when load detection is
requested.
(cherry picked from commit 6f18300aed1340348c6d395f326061b5315be643)
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