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Bug #14423.
Signed-off-by: Eric Anholt <eric@anholt.net>
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Signed-off-by: Eric Anholt <eric@anholt.net>
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That would be the kernel's job if it chooses to do it.
Signed-off-by: Eric Anholt <eric@anholt.net>
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Signed-off-by: Eric Anholt <eric@anholt.net>
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Signed-off-by: Eric Anholt <eric@anholt.net>
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Signed-off-by: Eric Anholt <eric@anholt.net>
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Signed-off-by: Eric Anholt <eric@anholt.net>
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The groff .IP macro is used to put the option defaults in a new indented
paragraph so they are separated from the explanations.
Signed-off-by: Dan Nicholson <dbn.lists@gmail.com>
[anholt: hand-applied due to conflicts. mistakes are my own]
Signed-off-by: Eric Anholt <eric@anholt.net>
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google shows one instance of this being used a year and a half ago.
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Any time we actually need SW cursors, it gets enabled automatically.
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We rely on having AGPGART present to successfully allocate video memory as
we configure it by default. Admit that fact, and remove support for
non-AGPGART/KMS setups.
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It's been broken for years now, and KMS offers a much better chance of getting
this working sensibly without making a mess of the 2D driver.
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The batch_bo buffer object is reallocated on enter VT, so we need to
unref it on leave vt.
Signed-off-by: Lukas Hejtmanek <xhejtman@ics.muni.cz>
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Add an Xv attribute XV_SYNC_TO_VBLANK which has three values -1(auto), 0(off)
and 1(on) to control whether textured adapter synchronizes the screen
update to the vblank. The default value is -1(auto).
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For SDVO encoder that advertise multiple functions,
we have to get attached display to determine current
output, and update output's name according with
current type.
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This fixes huge memory leak at each VT switch (about 600 BOs + 6MB
of RSS of Xserver).
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This allows multiple X server to use DRI and makes it possible to run
multiple X servers under KMS. This requires a 2.6.29 kernel to work.
On older kernels it will just log a warning and DRI will fail to
initialize for the second X server.
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This is based on Jesse's origin patch for bug #12763.
But export integer range to user instead of hardware float
point format, and fix different real format on 965G and 945G
for contrast and saturation.
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This can let user override non-stable driver TV load detect,
and set connector type manually, e.g for s-video to component
converter, this patch seems must needed to use HD modes.
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This is to fix bug #16566, change TV format will cause BadMatch
error when crtc config apply. Everytime when we change TV format,
we may generate a new list of modelines as TV clock changed. After
randr get info request, new modelines will be probed and randr output's
modes will be renewed too. But crtc's mode failed to be updated,
as it never can find a matching mode now within new modes list.
So get info will return an invalid crtc's mode, later set crtc
config will pass that info, and xserver catches a bad match.
This patch trys to refresh output modes and setup crtc's mode
with new modelines in TV format change. So get info would be
sure to turn valid crtc mode that reference in current new modelines.
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This saves massive quantities of memory on pre-965 since the DRI2 tiling
enable caused the minimum size of any pixmap to be 1MB.
(cherry picked from commit 5bfd73cd31ba197a62f549cdbad1a1270b571027)
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(cherry picked from commit 70e0261208654c6c875ad462da2734c6aa9eeb96)
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855GM laptops seems pretty broken when parsing this block.
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This saves massive quantities of memory on pre-965 since the DRI2 tiling
enable caused the minimum size of any pixmap to be 1MB.
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This is the intel video driver patch for a new chip, which is G33-like
and has some clocking setting related register changes. This patch adds
the pci id and DPLx/FPx register changes.
The gtt tool should just work to me, as the chip hasn't any changes
against G33 on this side.
Signed-off-by: Shaohua Li <shaohua.li@intel.com>
Signed-off-by: Eric Anholt <eric@anholt.net>
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It was just printing whether it was a pixmap (it is), instead of whether the
pixmap was offscreen.
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With UXA on the fake bufmgr, the screen pixmap doesn't have a BO and so
no acceleration was occurring.
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This could fix complaints about binding BOs and resulting failure to render.
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The LVDS config bits in VBT driver feature block is used by vendor
to identify the board implement of integrated LVDS/eDP or SDVO LVDS.
And video bios uses these bits for LVDS enabling or not. So check
these bits for integrated LVDS might eliminate more quirks.
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ALL_LVDS is actually not defined before and include GM45.
Embedded DP bit will be used for newer chips.
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(cherry picked from commit 9d8e5c21a1688b915bf39261d4c3b0bf2906daef)
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(cherry picked from commit a6b31f38ebf470c61de0e10b0ce2af0d7ee1684b)
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This was hit by xv86vm's SwitchMode path, and for that the CRTC offsets
get set at mode setting time anyway.
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This was hit by xv86vm's SwitchMode path, and for that the CRTC offsets
get set at mode setting time anyway.
(cherry picked from commit 53108994616d9751ac3a29fd61eb269cfaeab967)
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(cherry picked from commit 73bc7f113969834d00cd92be8374dbadc62f96a9)
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Otherwise, with a pre-2.6.28 older kernel the disable would be lost at
resume time and cause hangs.
Bug #20214
(cherry picked from commit 81c652e9a666a7459bcc5217c8a5ec518b6e00da)
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The assumption is that we're almost always accelerating our drawing to
new pixmaps (fill, copy, etc.).
(cherry picked from commit 0621ba12a3b694720e67a49b25ca52f0e09b3802)
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