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The return value of GetScreenPixmap before CreateScreenResources is not, in
fact, a pixmap.
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If not available, AIGLX init will fail. While here, simplify DRIINFO tests
since we refuse to init with a version queried less than the version we
compiled against, anyway.
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From issue report http://lists.freedesktop.org/archives/xorg/2007-July/026644.html
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This one trys to use a flag for possible quirks. It adds a quirk
for my Lenovo T61 TV output, and ports some origin LVDS quirks to it.
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To do this, we have to deal with buffer offsets being set at EnterVT time
instead of screen init time. We've wanted to move this direction for a long
time, but there are repercussions. The EXA offscreen memory manager has to
be disabled, because it can't be moved. That will be replaced by BO-backed
pixmaps soon. Also unresolved is whether our moving
front/back/depth/texture buffers will break the classic-mode DRI driver.
This code doesn't actually work yet.
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Reported by A. Costa" <agcosta@gis.net> in
http://bugs.debian.org/cgi-bin/bugreport.cgi?bug=432061
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This is a step towards being able to expose buffer objects through the screen
private to DRI clients, instead of having them have to use the fake buffer
object type.
This fails in two ways. First, the kernel memory manager is not currently
suitable for doing the physical allocations we need, so we still use AGP for
those. Additionally, the DRI lock can't be initialized early enough for us, so
these buffer object allocations fail. This will be fixed by improving the
DRM interface.
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Fence setting is in mapstate actually. This fixes rotation in
tiled fb case, thanks Keith to report this.
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which do have new host bridge ids
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dead lock.
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2. clean code
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2. fix an error in map_state
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2. implement macroblock_ipicture instruction
3. 16bit INTRA block
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I probably need to release a libdrm with this interface in it now..
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CRT blanking needn't be adjusted to perform load detection on 9xx chips, and
the 8xx load detection path now adjusts blanking just during load detection.
Adjusting the blanking interval turned out to cause many monitors to fail to
sync.
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If the pipe or output have been set to DPMSOff, then load detection will not
work correctly. Also, share the load detection configuration code between
crt and tv outputs.
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Instead of always adding blanking to mode lines, use the FORCE_BORDER option
on i9xx hardware where it works, and dynamically add a bit of border if
necessary on i8xx hardware to make load detection work. This may cause
flashing when a usable crtc is not otherwise idle when load detection is
requested.
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Make it to check fence register for dest buffer.
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The upper bits would have been inappropriately dropped on G33-class hardware,
and on G965-class hardware in a 32-bit environment. The only use of physical
addresses on these should be for FBC, though, and FBC requires addresses
below 4GB. This is unresolved.
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- allow FBC and Tiling to be forced off if configured to do so
- only touch FBC registers if pI830->fb_compression is true
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isn't enabled twice on two different pipes.
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- change framebuffer option name to "FramebufferCompression"
- add new "Tiling" option (controls all tiling, not just front buffer)
- add debug message to fb compression enable/disable routines
- update man page with new options
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- properly check several FBC enablement constraints
- don't use alpha discard if FBC is in use
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pitch.
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- move FBC register definitions to i830_reg.h
- add fix from Arjan for 965 depth buffer tiling
- add VT switch and clear-at-server-start code for FBC registers
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