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This is the intel video driver patch for a new chip, which is G33-like
and has some clocking setting related register changes. This patch adds
the pci id and DPLx/FPx register changes.
The gtt tool should just work to me, as the chip hasn't any changes
against G33 on this side.
Signed-off-by: Shaohua Li <shaohua.li@intel.com>
Signed-off-by: Eric Anholt <eric@anholt.net>
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Oops, my bad. Reverted 8d4bc36fae50b09a73ba2cfab920adb32141a358
since my kernel doesn't yet have the new param, committed
the revert by accident.
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Set alignments, tile settings and flags correctly in the 2D driver to support
tiled rendering. UXA's create pixmap function currently assumes the worst
about the alignment constraints; that should probably be fixed. Some of the
1M alignment fixes could probably be done more cleanly as well.
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Conflicts:
src/common.h
src/i830_hwmc.c
src/i830_video.c
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Those are identical that using one define is much clear.
And it can also apply fixes for GM45 too, which is missing with
origin define.
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libpciaccess (and the old X server PCI code as well) provides a function to
get the ROM contents. Code to use that was already present in the driver and
used if the INT10 function failed. Skip the INT10 and just use libpciaccess
as that eliminates several module loads and scary use of vm86.
Signed-off-by: Keith Packard <keithp@keithp.com>
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G41 is another 4 series chipset like G45/43.
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Thanks airlied!
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On new chip, DSPARB is controlled by hardware only.
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As xvmc rendering result has already been in fb, we shouldn't
do extra copy on it. Although special care is required for i915
xvmc surface pitch alignment, which must be at least 1KB aligned.
So video display function should take it into acount instead of
always setting Y pitch to be double of U/V pitch.
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Now, SDVO is only probed if the SDVO detected bit is set. If the SDVO probe
fails, but the detect bit is set, assume that it's an HDMI output.
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I want to hack on i830 for changing it into a compat path for batchbuffer
without having to worry about the i810 stuff getting broken.
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Several uses are actually left, which are determined by the X Server
interfaces we're implementing.
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Based on Maxim Levitsky's patch for the same. Many thanks to Maxim for
discovering that this features still works in recent hardware!
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Also add support on new chipset.
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libpciaccess has a new structure that holds the PCI identifier data; borrow
macros from the mga driver to work with either the old xf86-specific
structure or the new libpciaccess structure.
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which do have new host bridge ids
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Which have to use gfx vm offset fot setup overlay regs.
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These chipsets require that the hardware status page be referenced by an offset
in the GTT rather than a physical memory address, so the X Server allocates it
rather than the DRM.
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Because stolen memory happens to be a contiguous block of high system memory,
we can just read the GTT entries for it to get physical addresses for our
allocations there if needed. This reduces fragmentation of the aperture space,
and will often reclaim up to 7 MB of memory that had been left unused since the
simplified aperture manager was put in place, but without reintroducing the
complexities of the old aperture manager.
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git://proxy.ims.intel.com:9419/git/xorg/driver/xf86-video-intel into crestline
Conflicts:
src/i830_display.c
Change LVDS output and postread like upstream. This might
need to be retested on 965GM LVDS.
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With the new mode setting code, rotation is handled outside of the driver,
so the old usage of the 'shadow' module is no longer needed. Code to
initialize the crtc structures has been moved out of the driver and into the
modes code.
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This reuses the i830_debug.c code, so we can run that from the console or from
the BIOS-based X server to debug some remaining issues.
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Conflicts:
src/i830_display.c
src/i830_tv.c
src/i830_xf86Crtc.c
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git://proxy01.pd.intel.com:9419/git/xorg/driver/xf86-video-intel into crestline
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The cachelines are used for two things: XAA pixmap cache and XV memory.
Only XAA pixmap cache is referred to using an offset pointing at the
beginning of the front buffer in rendering, and XAA only uses the 2d BLT
engine, which actually has a vertical limit of 65536. So, pixmap cache is now
limited to that much vertical.
Additionally, the previous cachelines allocation was too small for our
advertised XV limits, so video at the limits would fail with BadAlloc. Now,
XAA allocates the same approximate amount of offscreen memory as EXA:
3 times the screen size, plus one packed HD video.
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I830EntityIndex is shared between 810 and newer driver.
Move most EXA rendering state into I830 structure.
Declare shared variables in shared header files rather than .c.
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This works for analog, but SDVO output appears to not work yet.
Conflicts:
src/i830_driver.c
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This reverts most of the mergedfb code. This will instead be done in device-
independent RandR code.
Conflicts:
src/Makefile.am
src/i810_driver.c
src/i810_reg.h
src/i830.h
src/i830_cursor.c
src/i830_driver.c
src/i830_modes.c
src/i830_video.c
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Lots of names included BIOS for no apparent reason; as we try to eliminate
BIOS calls from the driver, these only serve to confuse us.
(cherry picked from 8e5d280d94ad3d3ba3c75871c17abec9da62ed34 commit)
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The "Crestline" banner should be replaced with official
name later.
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