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It's been broken for years now, and KMS offers a much better chance of getting
this working sensibly without making a mess of the 2D driver.
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This is the intel video driver patch for a new chip, which is G33-like
and has some clocking setting related register changes. This patch adds
the pci id and DPLx/FPx register changes.
The gtt tool should just work to me, as the chip hasn't any changes
against G33 on this side.
Signed-off-by: Shaohua Li <shaohua.li@intel.com>
Signed-off-by: Eric Anholt <eric@anholt.net>
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In debugging the frame buffer resize code, I needed to see what the server
was doing to the fence registers, so I added this debug code. Seems useful
enough to include it.
Signed-off-by: Keith Packard <keithp@keithp.com>
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This eliminates the cost of EXA migration management while providing full
pixmap allocation control to the driver. The goal is to make something
useful for UMA drivers.
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Conflicts:
src/i830_driver.c
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Conflicts:
configure.ac
src/reg_dumper/Makefile.am
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This makes it easier to read.
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This reverts commit 0c00a638ef57aa9d6a3047176b0bfad733f781f0.
Those FIFO watermark regs are 945-ish, and cause problem
on G35.
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Several uses are actually left, which are determined by the X Server
interfaces we're implementing.
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Fix printf formatting warnings, wrap a couple of long lines, nuke
unused variables, add missing #include <unistd.h>.
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The VGA register dumping code was leaving ARX in data mode rather than index
mode, which could cause problems for later software accessing AR* registers.
Fix it to make sure it's in index mode when we're done.
Fixes #14434.
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MI_ARB_STATE, MI_RDRET_STATE, ECOSKPD
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Use PRIx32 for printing CARD32 types, and PRIx64 for portably printing uint64_t
types. Requires the addition of a new include, inttypes.h, to work. Hope C99
is ok with everybody...
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Also fix debug dump, slightly modified to use macro instead.
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where we put MMIO control reg in, and shared with intel_reg_dump
program.
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Just for completeness.
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Add a VGA AR dumping function so we can debug text mode problems too.
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LVDS mode changes how the PLL works in fairly dramatic ways; the debug code
wasn't properly accounting for those differences resulting in fairly bogus
debug output.
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Be sure to check G33 chip type in:
- sdvo output
- Y-major tile
- crt detect
- and xaa composite
Sorry for that I should have fixed them very earlier...
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When the hardware locks up, dump the pending commands in the ring for
analysis.
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- Use the existing single/dual-channel state when available, as changing it
doesn't appear to work out.
- Set the power state of the CLKB and B0-B3 pairs according to whether
choose to go dual-channel or not.
- Restore the LVDS register at the appropriate point (before DPLLs are
re-programmed.
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This gets correct clocks detected on most harware. The SSC is always assumed
to be 66Mhz, which may not be true, but we'll fix that when we find example
hardware.
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This reuses the i830_debug.c code, so we can run that from the console or from
the BIOS-based X server to debug some remaining issues.
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This should fix a number of issues with i855s, particularly with integrated
LVDS panels.
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This includes not reporting some fields on hardware where those bits are
reserved, correcting one of the hardware error bit numbers, and reducing
the severity of the debugging output warnings.
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Autodetect libdrm version, disable new memory manager on older libraries.
Move new M_T_ defines from i830.h to i830_xf86Crtc.h. Add many system
headers to define functions. Use i830PipeSetBase at end of mode setting
code to set DSP*BASE and flush changes. Don't duplicate PipeSetBase call
from screen init function. Make initial RandR configuration code usable on
older versions of extension so the server doesn't start in a panning mode.
Use xfree instead of free in i830_tv.c.
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