| Age | Commit message (Collapse) | Author |
|---|
|
|
|
- Full functionality of Radeon based original patch now ported
to recent Intel graphics hardware. This includes support
for i945G chipsets as found on EEE PCs and D945GCLF[2] boards.
- Exploits some special features of i945G chipsets like
vertical phase registers and fine tuning of vertical scaling.
This enables us to compensate for interference effects observed
when driving modern digital displays through a SCART interface.
Signed-off-by: Thomas Hilber <sparkie@lowbyte.de>
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
|
In hindsight, this is obvious, since nowhere do we tell the FBC unit how much
memory it has available. We need to make sure the compressed buffer is big
enough to handle the uncompresed buffer, both in terms of vertical size and
total framebuffer size, or the compressor could overwrite the memory
immediately following the compressed buffer.
(cherry picked from commit 7332132a79e5b5c208d43e93dfe0c8b12eb1728d)
(cherry picked from commit 7d1aa118a24195833466a4a4342c71f37db673f8)
|
|
(cherry picked from commit a34a4e3f6420e2b06bbdaa124fe0ccb1bc6a0bd9)
|
|
(cherry picked from commit 9a05662918223477eb1cf6f80ffac08712721c70)
(cherry picked from commit 82300116af8b01fc3c071d9c8625ffea122431fa)
Conflicts:
src/i830_hdmi.c
|
|
(cherry picked from commit bff180e6cac4452ef491c81855eb12bfa03d0bf3)
|
|
(cherry picked from commit 5c9cde37e769287fb7bf4e08c3600a33c2e92dce)
|
|
(cherry picked from commit 152a50703aa5e9ebaa9abbe448518742734a5eb7)
|
|
The Intel driver appears to be coded to only work with displays
expecting 18 bit pixels. However I have an application using a LCD
display that expects pixel data in 24 bit format. The difference is
only 2 bits in a single GPU register. This patch implements that
change, controlled by a new driver option, "LVDS24Bit". The default
value is false, which is the previous behavior. When set to true,
then 24 bit panels should work (at least the one I'm testing here
does).
Fd.o bug #15201
Signed-off-by: Mike Isely <isely@pobox.com>
(cherry picked from commit e031cc02e65acfbafb48136dad414751e04425c5)
|
|
Disable panel fitting on 855GM, and fix dither setting.
(cherry picked from commit 2b720262e1235f1c9da860ba3e9181f0c377aa5e)
|
|
(cherry picked from commit 7dcb6e627449c80cea9812462ce6a3e125bd1240)
|
|
Tired of them filling up my logs.
|
|
Several uses are actually left, which are determined by the X Server
interfaces we're implementing.
|
|
|
|
The following patch fixes the display problem on internal development machines.
The code in commit 3c22ed633be2ac96eea7bc533839e956f1f31b84 (Jesse's force pipe
A enable patch) broke DPLL programming. Moving the DPLL set back up in the
function solves the problem.
Fix for internal bug #309.
|
|
Use the "immediate idle" mode for FBC. Rather than waiting for the current
compression pass to finish before signalling to the CPU that it's idle, this
mode should stop any current compression pass and tell the CPU that the GPU is
idle right away.
Seems to fix #13326.
|
|
My fault to change Hong's origin patch reversely.
|
|
The call to disable FBC should only occur if the FBC feature is actually
present or we may end up hanging on a read from a non-existent register.
|
|
Some chips can't support FBC if multiple pipes are active. So if more than one
pipe is on or we're going from one->two pipes enabled, make sure FBC is
disabled.
Intended to fix 13418, 13326, 13152.
|
|
Just a partial fix for some of the FBC issues people have been seeing. The
other half is to disable FBC if both pipes are running.
|
|
Also fix debug dump, slightly modified to use macro instead.
|
|
|
|
|
|
On some platforms, the firmware may read & write GPU registers on lid close,
suspend/resume time or during various SMM events. If one of the graphics pipes
is disabled at that time, the GPU may hang due to the programming dependencies
of the various registers.
This patch adds a quirk to force the driver to keep pipe A enabled if
necessary, through user configuration in xorg.conf or via a platform specific
quirk. Leaving the pipe enabled comes at a power cost however, so the quirk
should only be enabled when strictly necessary.
Fixes https://bugs.freedesktop.org/show_bug.cgi?id=11432.
|
|
i830_reg.h only contains 3d engine cmds for 8XX chips.
|
|
To be consistent, it should say 'plane' rather than 'pipe'.
|
|
The PLL spreadsheet makes the precise register ranges allowed for each mode
quite clear, and shows a few inaccuracies in the b-spec. In particular, the
N register value may range from 1 to 6 instead of 3 to 8. This should close
the gap we've seen in the reachable frequencies.
|
|
Fix a long standing bug in the framebuffer compression code (thanks to
Pierre Willenbrock!) that prevented FBC from working correctly if the front
buffer was anywhere but fence register 0.
|
|
|
|
|
|
We want to associate plane A with pipe B on pre-965 mobile chips, since that's
the only way to get framebuffer compression on the builtin LVDS on those
platforms. However, if we do this swapping and DRM isn't aware of it, we may
end up requesting vblank events for the wrong pipe, or setting up SAREA buffer
swap state incorrectly.
This mod checks whether DRM supports the new plane->pipe swapping behavior, and
only enables the swapping if so. This should fix the bugs Lukas found and
debugged. Reviewed by Michel Danzer.
|
|
Uncomplicated API transistions for libpciaccess usage:
Legacy xf86 API libpciaccess API
--------------- ----------------
xf86ReadPciBIOS pci_device_read_rom
pciReadWord pci_device_cfg_read_u16
pciWriteByte pci_device_cfg_write_u8
And, more use of the API-independent DEVICE_ID/SUBVENDOR_ID/SUBSYS_ID macros
to pull PCI identification data from the underlying structure.
|
|
This requires EXA 2.2 (server 1.3) for rotated performance with EXA, because
the i830_memory.c allocation may not fall within what EXA considers the
offscreen area, so the PixmapIsOffscreen hook is needed.
|
|
Add a new 'plane' field to the intel_crtc private structure for tracking
planes separate from pipes. This allows pre-965 chips to use plane A
on pipe B, enabling framebuffer compression for builtin LVDS displays.
|
|
When TV does load detect, fb hasn't been setup, so we should check
that in i830_display_tiled(). Caught by Nanhai.
|
|
DSPATILEOFF and DSPBTILEOFF replace DSPASURF and DSPBSURF when the frame
buffer is in tiled mode.
|
|
Front buffer tiling is now disabled with G965 and XAA. Some of the acceleration
that i830_xaa.c does can't be supported on tiled buffers.
Adds a tiling field to struct i830_memory, and uses it instead of separate
variables for each potential tiled buffer.
|
|
This should be close to the last set of tiling fixes for 965 chipsets.
Prior to this commit, the 965 composite hook didn't take tiling into
account, nor did 965 textured video, which caused display corruption.
However, there seems to be at least one last bug to squash--on occasion,
a configuration with tiling enabled won't properly display text. This
is likely another tiling related problem with the composite hook.
|
|
- actually enable tiling in DSP(A|B)CNTR if needed
- add logic to EXA routines for tiled case (still needs work)
- enable/disable fbc on DPMS events (meant moving functions higher in file)
- fix fence register pitch programming (use correct pitch instead of kludged value)
|
|
CRT blanking needn't be adjusted to perform load detection on 9xx chips, and
the 8xx load detection path now adjusts blanking just during load detection.
Adjusting the blanking interval turned out to cause many monitors to fail to
sync.
|
|
If the pipe or output have been set to DPMSOff, then load detection will not
work correctly. Also, share the load detection configuration code between
crt and tv outputs.
|
|
Instead of always adding blanking to mode lines, use the FORCE_BORDER option
on i9xx hardware where it works, and dynamically add a bit of border if
necessary on i8xx hardware to make load detection work. This may cause
flashing when a usable crtc is not otherwise idle when load detection is
requested.
|
|
- allow FBC and Tiling to be forced off if configured to do so
- only touch FBC registers if pI830->fb_compression is true
|
|
|
|
isn't enabled twice on two different pipes.
|
|
- change framebuffer option name to "FramebufferCompression"
- add new "Tiling" option (controls all tiling, not just front buffer)
- add debug message to fb compression enable/disable routines
- update man page with new options
|
|
|
|
|
|
- properly check several FBC enablement constraints
- don't use alpha discard if FBC is in use
|
|
pitch.
|
