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- Full functionality of Radeon based original patch now ported
to recent Intel graphics hardware. This includes support
for i945G chipsets as found on EEE PCs and D945GCLF[2] boards.
- Exploits some special features of i945G chipsets like
vertical phase registers and fine tuning of vertical scaling.
This enables us to compensate for interference effects observed
when driving modern digital displays through a SCART interface.
Signed-off-by: Thomas Hilber <sparkie@lowbyte.de>
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
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construct function to find precise parameters from internal spreadsheet
table on G4X platform.
Signed-off-by: Ma Ling <ling.ma@intel.com>
(cherry picked from commit 7c94227dd4fa2164bebb36234958053bf1d26c12)
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These timings on G4X platform were specified by internal spreadsheet from the chipset group.
Signed-off-by: Ma Ling <ling.ma@intel.com>
(cherry picked from commit 48db5bde9298f1126dfb42f4be8a3d61166abfd8)
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When disabling VGA mode, usually we don't need to touch VGA center mode.
However because of hardware reason, for Cresline, Cantiga & Eaglelake platform,
we have to disable center mode as well. The patch fixed bug- TV Out strobing regression,
reported by Robert Lowery in intel-gfx@lists.freedesktop.org mailing list.
Signed-off-by: Ma Ling <ling.ma@intel.com>
(cherry picked from commit b5b377806422c9538fa9f846819ad253c1a50846)
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Since we added the pipe A force quirk (leaving pipe A on all the time),
DPMS calls to disable it have silently returned, leaving the pipe on.
If another driver (like vesafb) has enabled it, we may end up with a bad
configuration, leading to hangs or blank screens at VT switch time.
Fixes bug #19603.
(cherry picked from commit 6deb26ae7bd796e88a5dd90df5f6c35fbc44e798)
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Bug #14423.
Signed-off-by: Eric Anholt <eric@anholt.net>
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It's been broken for years now, and KMS offers a much better chance of getting
this working sensibly without making a mess of the 2D driver.
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This is the intel video driver patch for a new chip, which is G33-like
and has some clocking setting related register changes. This patch adds
the pci id and DPLx/FPx register changes.
The gtt tool should just work to me, as the chip hasn't any changes
against G33 on this side.
Signed-off-by: Shaohua Li <shaohua.li@intel.com>
Signed-off-by: Eric Anholt <eric@anholt.net>
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Wrong SDVO multiplier setup has been slipped
in SDVO TV patch. Thanks Michael Fu to point this out!
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As SDVO TV uses SDVO_TVClkIn from SDVO encoder for clock reference,
it needs to generate proper PLL for current input clock. This uses
fixed PLL table from vbios for this. And possible sdvo mulitiplier
has to be setup correctly. This makes TV output stable on my 945GCLF2
board with NTSC-M format.
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commit id b9f5915ce812144ffd9d2aa42e8ba856129c35e,
which resolved bug #17235, but generate new regression-bug #19715.
This patch intends to resolve bug #17235, and avoid regression as well.
We have successfully re-tested it for bug #17235 and #19715 respectively.
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This fixes #17235, VGA random hang on recent G45/43 board.
From spec, SR01 bit 5 should be set before VGA plane disable through
control register, otherwise we might get random crash and lockups.
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As the rotation memory and rotation pixmap are allocated separately (to make
rotation at startup work), the allocate dri_bo needs to be set in the pixmap
for acceleration to work. This restores the performance in rotated modes.
Signed-off-by: Keith Packard <keithp@keithp.com>
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Signed-off-by: Keith Packard <keithp@keithp.com>
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This eliminates the separate i830_allocate_memory_tiled function which means
that all memory objects will have tiling parameters set correctly.
Signed-off-by: Keith Packard <keithp@keithp.com>
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Since we don't perform any synchronization with the kernel on these regs, we
could race with the kernel to write stale values and end up not having vblank
interrupts enabled when somebody was waiting on one.
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RandR 1.3 panning support can use the regular mode setting interface, but
that's really slow. Providing set_origin makes it nice and snappy.
Signed-off-by: Keith Packard <keithp@keithp.com>
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Conflicts:
src/i830_dri.c
src/i830_driver.c
src/i830_memory.c
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Those are identical that using one define is much clear.
And it can also apply fixes for GM45 too, which is missing with
origin define.
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Vblank in the kernel is far simpler if it deals with pipes instead of
planes, so we're changing both user and kernel side. This is the user mode
side. This fixes both i830_crtc_dpms and i830PipeSetBase, the two functions
which copy geometry from the crtc to the sarea.
Signed-off-by: Keith Packard <keithp@keithp.com>
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From the Intel 965 Programmer’s Reference Manual, volume 3,
chapter 2.2.2 "Mode Switch Programming Sequence".
The disable sequence should be:
- Disable planes (VGA or hires)
- Disable pipe
- Disable VGA display in 0x71400 bit 31
This patch implements that order plus waits for a vblank at the end.
Fixes bug #17756.
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We need to program DSPARB with only one plane enabled at most, and that's
guaranteed to be the case when we're called during mode set, so just assert
that case but otherwise leave the planes alone to avoid flicker on active
displays during output detection for example.
Fixes bug #17050.
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Last commit introduced a logic buglet, we went from (foo & BLAH) -> (!foo &
BLAH) rather than !(foo & BLAH), so fix it up to make my laptop work again.
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Still turn off the VGA plane, and also handle the DRI path at the end.
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ssh://git.freedesktop.org/git/xorg/driver/xf86-video-intel
Conflicts:
src/i830_display.c
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This avoids the flickering people reported in the 2.4.0 release.
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On new chip, DSPARB is controlled by hardware only.
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Fix regression on my 855GM for VGA output.
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Previously, we were attempting to give both planes equal space in the FIFO
to be fair. However, larger modes require more fifo space, so split it based
on the relative HDisplay of the modes. This should resolve some fifo underrun
issues with differently-sized displays, or single large ones.
Bug #16169.
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Improve the VBIOS feature detection and use it to find whether the platform
supports spread spectrum clocking. Use the specified reference clock, but
disable SSC if multiple heads are active, since it can cause problems in cloned
configurations.
Reviewed by Nanhai Zou.
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In hindsight, this is obvious, since nowhere do we tell the FBC unit how much
memory it has available. We need to make sure the compressed buffer is big
enough to handle the uncompresed buffer, both in terms of vertical size and
total framebuffer size, or the compressor could overwrite the memory
immediately following the compressed buffer.
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Oops.
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The DRM supports disabling of vblank interrupts when not in use, but in order
to function properly it must also be aware of mode setting, which will reset
the frame counter to 0. Add code to call into the DRM before and after mode
setting, so that it can account for any lost vblank events.
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Add some debug code to catch FIFO underruns, which are normally bugs (unless
they occur during mode setting) and remove any plane C FIFO allocations, since
we don't use that plane at all. We may eventually need to be a little smarter
about this on platforms that use plane C for the popup.
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Based on a patch by Will Wiseman.
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The Intel driver appears to be coded to only work with displays
expecting 18 bit pixels. However I have an application using a LCD
display that expects pixel data in 24 bit format. The difference is
only 2 bits in a single GPU register. This patch implements that
change, controlled by a new driver option, "LVDS24Bit". The default
value is false, which is the previous behavior. When set to true,
then 24 bit panels should work (at least the one I'm testing here
does).
Fd.o bug #15201
Signed-off-by: Mike Isely <isely@pobox.com>
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Disable panel fitting on 855GM, and fix dither setting.
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Tired of them filling up my logs.
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Several uses are actually left, which are determined by the X Server
interfaces we're implementing.
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