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2D pitch limit applys to all chips. Pre-965 chip has
8KB pitch limit for 3D. 965 supports max pitch by current
exa (128KB).
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This reverts commit 602613e397bdf0cf701a6a7748f9343875864466.
Pre-965 chipset actually have different pitch limit for 2d and 3d
engine. For 2D blit, it's 32KB max. For 3D, it's 8KB max. Don't
limit it to minimal which fallback 2D operations (noteable copy
slow).
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The homogeneous coordinate computation in the core server cannot be used for
many legal matrices as it overflows. Just use floats in the driver; faster
and avoids troubles.
When compositing with bilinear filter, don't push the dst coordinates around
as that makes the output blurry when pixels are aligned.
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Projective transforms require un-normalized texture coordinates and the use
of the texldp instruction. The coordinates are passed as x/y/z/w (the z is
unused, but there isn't a vertext format for just x/y/w).
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These are needed to deal with projective transforms in the composite
operation.
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It never worked and was never that hot of an idea. Most of the motivation is
gone with glyph pixmaps anyway.
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Several uses are actually left, which are determined by the X Server
interfaces we're implementing.
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i830_reg.h only contains 3d engine cmds for 8XX chips.
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This branch changes i830_memory.c's allocator to use TTM when available to
allocate memory, which also allows TTM to control almost the entire aperture.
As a result, our front/back/depth buffers are created as real buffer objects,
which may be used by the DRI driver instead of the fake buffer type in TTM.
The updated DRM with bo_set_pin ioctl is required, to allow us to pin and
unpin our buffers as needed.
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Conflicts:
src/i830.h
src/i830_driver.c
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Use consistent interface for counting pixmap offset.
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This requires EXA 2.2 (server 1.3) for rotated performance with EXA, because
the i830_memory.c allocation may not fall within what EXA considers the
offscreen area, so the PixmapIsOffscreen hook is needed.
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Conflicts:
src/i830_dri.c
src/i830_memory.c
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Front buffer tiling is now disabled with G965 and XAA. Some of the acceleration
that i830_xaa.c does can't be supported on tiled buffers.
Adds a tiling field to struct i830_memory, and uses it instead of separate
variables for each potential tiled buffer.
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This should be close to the last set of tiling fixes for 965 chipsets.
Prior to this commit, the 965 composite hook didn't take tiling into
account, nor did 965 textured video, which caused display corruption.
However, there seems to be at least one last bug to squash--on occasion,
a configuration with tiling enabled won't properly display text. This
is likely another tiling related problem with the composite hook.
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The 915 and earlier appear to respect the fence registers, while only the 965
requires the per-operation tiling setting and pitch shifting. This will also
fix issues with rendering on the 965 involving multiple cliprects, where the
pitch would get divided repeatedly.
This removes the offset < 4096 fallback, which essentially resulted in no
acceleration to tiled buffers, hiding the issues.
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PrepareSolid - combine pI830->tiling and frontbuffer checks into new exaPixmapTiled function for readability
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- actually enable tiling in DSP(A|B)CNTR if needed
- add logic to EXA routines for tiled case (still needs work)
- enable/disable fbc on DPMS events (meant moving functions higher in file)
- fix fence register pitch programming (use correct pitch instead of kludged value)
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To do this, we have to deal with buffer offsets being set at EnterVT time
instead of screen init time. We've wanted to move this direction for a long
time, but there are repercussions. The EXA offscreen memory manager has to
be disabled, because it can't be moved. That will be replaced by BO-backed
pixmaps soon. Also unresolved is whether our moving
front/back/depth/texture buffers will break the classic-mode DRI driver.
This code doesn't actually work yet.
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DDX will check it for EXA_OFFSCREEN_PIXMAPS flag
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Now, all 3D pipeline consumers in the driver just call
IntelEmitInvariantState(), which handles basic state setup, the caching of that
state setup, and notifying DRI clients. This also removes a mistaken idle
wait in the Render code which was papering over the brokenness in the context
switching.
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These chipsets require that the hardware status page be referenced by an offset
in the GTT rather than a physical memory address, so the X Server allocates it
rather than the DRM.
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That notify mesa rendering is smashing the state, and check last 3d
operation to do sync after we're swapped in or others.
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Reported by JM Ibanez.
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This slipped in as a debugging aid, and never got turned off. The driver
appears to work fine without it on an i915 system, and for the non-default EXA
option, we'd rather see issues found than continue running with debugging aids
and hiding them behind bad performance.
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This allows setting the size to 0 when a pipe gets disabled.
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The previous allocator worked in multiple passes, with (at least) one of
setting up allocations, another to attempt to adjust those for tiling, and
then a pass to set up the offsets and fix them in memory.
The new allocator is simpler, allocating memory immediately if possible,
setting up tiling up front, and choosing offsets immediately. AGP memory
is only allocated to back actual memory used, saving some memory that would
have been allocated for padding previous. It will also allow dynamic freeing
and reallocation of memory, which will be useful for framebuffer resizing.
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This seems like a typo, which causes screen artifacts.
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The now-generic (kind of) EXA code will be cleaned up and moved to generic
files in a later commit.
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Previously, we tried to use 2 points instead of 3 to describe the source
rectangles, which mostly just worked for scaling.
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For EXA, this requires version 2.1 of EXA to do rotation, as the VT switching
issues were too complicated otherwise.
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A side effect is the reduction in vertex dispatch, which is nice.
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This reduces max framebuffer width and increases max framebuffer height on
965, reduces max X/Y on pre-965 EXA (could have caused mis-rendering), and
increases max X/Y on 965 EXA (would have prevented acceleration).
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Several new global functions were not put into the header file leading to
potential mismatches between declaration and definition.
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I830EntityIndex is shared between 810 and newer driver.
Move most EXA rendering state into I830 structure.
Declare shared variables in shared header files rather than .c.
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Not split offscreen mem for exa, but alloc a dedicated one
for G965 states.
Signed-off-by: Keith Packard <keithp@neko.keithp.com>
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