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where we put MMIO control reg in, and shared with intel_reg_dump
program.
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Needed for the new debug code
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- actually enable tiling in DSP(A|B)CNTR if needed
- add logic to EXA routines for tiled case (still needs work)
- enable/disable fbc on DPMS events (meant moving functions higher in file)
- fix fence register pitch programming (use correct pitch instead of kludged value)
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pitch.
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- move FBC register definitions to i830_reg.h
- add fix from Arjan for 965 depth buffer tiling
- add VT switch and clear-at-server-start code for FBC registers
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Use LOAD_IMM_2 helper cmd for tex setup. Enable RepeatNormal
support. Fix A8 format, i830 can support it now.
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865GM and 915G. There is issue in picture 'repeat' support.
And also stop recursive behavior in I830WaitLpRing to allow
server to abort instead of system hang.
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rotation at startup.
This mimicks the 3D drivers setup.
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