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2D pitch limit applys to all chips. Pre-965 chip has
8KB pitch limit for 3D. 965 supports max pitch by current
exa (128KB).
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The homogeneous coordinate computation in the core server cannot be used for
many legal matrices as it overflows. Just use floats in the driver; faster
and avoids troubles.
When compositing with bilinear filter, don't push the dst coordinates around
as that makes the output blurry when pixels are aligned.
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Projective transforms require un-normalized texture coordinates and the use
of the texldp instruction. The coordinates are passed as x/y/z/w (the z is
unused, but there isn't a vertext format for just x/y/w).
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When we have unset channels (color for a8, or alpha for x8*), force them
to the appropriate value in the texture combiner rather than relying on getting
the desired results from teture mapping. Performance is the same on 865, so
multiple paths aren't necessary and we can use the less friendly texture
formats everywhere.
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Several uses are actually left, which are determined by the X Server
interfaces we're implementing.
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Whoa, gcc got a lot smarter about warnings. If iXXX_get_dest_format()
doesn't support the picture format passed in it won't initialize the
uint32_t pointed to by dst_format and return FALSE.
What gcc now can detect is if dst_format is used without checking the
return value, it might be used uninitialized. This patch makes sure
we always check the return value before using dst_format.
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Now, all 3D pipeline consumers in the driver just call
IntelEmitInvariantState(), which handles basic state setup, the caching of that
state setup, and notifying DRI clients. This also removes a mistaken idle
wait in the Render code which was papering over the brokenness in the context
switching.
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That notify mesa rendering is smashing the state, and check last 3d
operation to do sync after we're swapped in or others.
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This was found when debug exa on a 865GV, we should set
pipeline state bits properly, otherwise the engine will hang.
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Fix tex blend pipeline in case that src/mask pict has no
alpha. Unmask color buffer write disable bits. These make
rendercheck run fine on 855GM.
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Fallback in 830/845G when pict format is a8, x8r8g8b8 or
x8b8g8r8. The hw doesn't support them.
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Try to map texture stream when setup texture map, and use
correct order in load_immediate_1 cmd, which fixed crash on
845GV. Also remove some flush cmds.
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i830_get_blend_cntl() has already added S8 offset.
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Pick fix from i915 render, change tex blend pipeline for CA.
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Use LOAD_IMM_2 helper cmd for tex setup. Enable RepeatNormal
support. Fix A8 format, i830 can support it now.
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This is the documented correct ordering, and while the previous ordering
(reversed) worked on some hardware, it failed on others.
Reported by: Wang Zhenyu <zhenyu.z.wang@intel.com>
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This fixes the rendercheck "transformed src/mask coords 2" tests. Previously,
the source pixels chosen would be off by one in some cases.
The particular values were taken from Mesa, which uses .125 offsets (except
apparently broken for y), but the signs are changed. I would be happier if
I had better justification for why this worked.
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