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(cherry picked from commit a34a4e3f6420e2b06bbdaa124fe0ccb1bc6a0bd9)
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(cherry picked from commit 1cfe769c74d1a3a392bf1aaaf5c2dcc8273daf66)
(cherry picked from commit 093f65fd04c38e6c1f19889074f9316749959c7a)
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(cherry picked from commit 90886f9a602d58b754e9a8d0f1a9c40803d34fa2)
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(cherry picked from commit 0836373dc6e2f8612f120074980561f7ac11f6f7)
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Saving registers means we can run more in parallel.
(cherry picked from commit bfd803e085e938866efb45c67a79facef78ec399)
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Clean up register allocation to never overlap
Always write 4 values for each texture vertex.
(cherry picked from commit a6492661ae07310128eb73c3ef037c42ce7ab184)
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(cherry picked from commit 6bb92213374f278387c539bbe05b773e87e11b90)
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Use macros for register names, modularize functions into separate files.
(cherry picked from commit 08500507284f13ad7084eb231b43e117e9728129)
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This involves correctly computing u/v locations based on x/y vectors and
line constants computed in new sf program.
Also, use fewer instructions to make this go a bit faster (2X for 500x500
composite).
(cherry picked from commit 6304b38423f99190a5e54f1a7dcaa75adfad4f2a)
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The homogeneous coordinate computation in the core server cannot be used for
many legal matrices as it overflows. Just use floats in the driver; faster
and avoids troubles.
When compositing with bilinear filter, don't push the dst coordinates around
as that makes the output blurry when pixels are aligned.
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Several uses are actually left, which are determined by the X Server
interfaces we're implementing.
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Whoa, gcc got a lot smarter about warnings. If iXXX_get_dest_format()
doesn't support the picture format passed in it won't initialize the
uint32_t pointed to by dst_format and return FALSE.
What gcc now can detect is if dst_format is used without checking the
return value, it might be used uninitialized. This patch makes sure
we always check the return value before using dst_format.
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This should be close to the last set of tiling fixes for 965 chipsets.
Prior to this commit, the 965 composite hook didn't take tiling into
account, nor did 965 textured video, which caused display corruption.
However, there seems to be at least one last bug to squash--on occasion,
a configuration with tiling enabled won't properly display text. This
is likely another tiling related problem with the composite hook.
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Note that this is a slowdown in text rendering due to the high overhead of our
compositing setup, but appears to be correct according to rendercheck.
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It needs to fix shader programs which hasn't been done yet.
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There were two calls to i830WaitSync, and between them no state was
being changed---just offsets were being computed.
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Now, all 3D pipeline consumers in the driver just call
IntelEmitInvariantState(), which handles basic state setup, the caching of that
state setup, and notifying DRI clients. This also removes a mistaken idle
wait in the Render code which was papering over the brokenness in the context
switching.
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Use scrn's virtual size is not correct in rotation rendering.
This fixes initial rotation problem on i965.
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That notify mesa rendering is smashing the state, and check last 3d
operation to do sync after we're swapped in or others.
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Originally we smashed vertex header to store texture
coordinates, this is working as we only use sf/wm kernel
and disable all other stages on pipeline. But better to
not do this. This also cleans up vertex elements state
and makes vertex buffer order looks "normal".
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The new sf/wm should handle the texture sampling only in
rotated case. Also fix possible hole in VUE slot.
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The previous allocator worked in multiple passes, with (at least) one of
setting up allocations, another to attempt to adjust those for tiling, and
then a pass to set up the offsets and fix them in memory.
The new allocator is simpler, allocating memory immediately if possible,
setting up tiling up front, and choosing offsets immediately. AGP memory
is only allocated to back actual memory used, saving some memory that would
have been allocated for padding previous. It will also allow dynamic freeing
and reallocation of memory, which will be useful for framebuffer resizing.
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(0,0,0,1.0) is actually black...
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we're getting load of multiple sf/wm programs for i965, might
need to be cleanup in future.
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Fix SF kernel with corrent coeffient work, and correct
VUE storage in multi texture case.
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