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The automatic panel scaling appears to choose bad sampling on some GM965
hardware for 1:1 mapping modes, and there's no real sense in having it on
if we just want 1:1.
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"true" in your xorg.conf). Should save ~0.5W during typical 2D usage.
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Make sure there is some border area to use by changing how the pipe is
configured, then pick a scanline in the middle of the border for load
detection. This lets the load detect code use an active pipe instead of
requiring an idle one.
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Just as with i9xx LVDS, the i855 LVDS can operate in dual-channel mode with
a modified P2 divisor value (7 instead of 14). Just using the existing 9xx
code for 855 appears to work fine.
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LVDS mode changes how the PLL works in fairly dramatic ways; the debug code
wasn't properly accounting for those differences resulting in fairly bogus
debug output.
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It needs to fix shader programs which hasn't been done yet.
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DDX will check it for EXA_OFFSCREEN_PIXMAPS flag
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There were two calls to i830WaitSync, and between them no state was
being changed---just offsets were being computed.
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This also results in removal of the setup hook, which was being called
unconditionally and breaking non-ivch dvo drivers.
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The patch for the i855 to stop enabling plane/pipe/pll in mode_set broke the
i830. Revert that just for the i830, leaving it enabled for the i855.
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The x40 LVDS mode has a 49.6Hz vertical refresh. Waiting for only 20ms can
sometimes cause the driver to start programming the hardware before the
vblank has occurred, which will lock up the i855 chipset. Extend this to
30ms (the maximum timeout used by the BIOS) to ensure this doesn't happen.
Detecting actual vblank occurance using the various status registers should
also be possible but isn't yet working.
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The backlight control in the LVDS controller can either operate in 'normal'
mode or 'legacy' mode. In legacy mode, it uses the PCI config space register
0xf4 which can range from 0 to 0xff. In normal mode, it reads the range and
current value from the BLC_PWM_CTL register.
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Be sure to check G33 chip type in:
- sdvo output
- Y-major tile
- crt detect
- and xaa composite
Sorry for that I should have fixed them very earlier...
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On 855, letting crtc_mode_set enable the plane and pipe will occasionally
hang the chip. Instead, wait for crtc_enable to light things up. For 9xx,
leave things alone.
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This lights up my monitor VGA-1 - it doesn't look the best though
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ifndef."
This reverts commit c2b130354aecffbeb2a2d23c7371461feaf5766a.
Sadly, a non-working DRM_IOCTL_I915_FLIP already existed.
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Now, all 3D pipeline consumers in the driver just call
IntelEmitInvariantState(), which handles basic state setup, the caching of that
state setup, and notifying DRI clients. This also removes a mistaken idle
wait in the Render code which was papering over the brokenness in the context
switching.
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This is already fixed in the definition in the 3d driver.
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- The screen dimensions were used for the clipping despite drawing being done
to any pixmap, not necessarily the screen.
- One piece of state setup was not documented anywhere, and isn't used in other
3d hardware paths that also work.
- A 3DSTATE_MODES_1 command (830-class only) was issued even though it no
longer exists.
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The 24-bit frame and pixel counters were not described in detail and
will be useful for DRM.
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Which have to use gfx vm offset fot setup overlay regs.
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These chipsets require that the hardware status page be referenced by an offset
in the GTT rather than a physical memory address, so the X Server allocates it
rather than the DRM.
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Ok, so moving video from pipe A to pipe B still requires that pipe A be
active during the transition. Instead of trying to be fancy, just ensure
that pipe A is running on each transition to pipe B.
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As crtcs are disabled and enabled, make sure the automatic crtc selection
mechanism drives overlay configuration at each request to display an image.
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Use scrn's virtual size is not correct in rotation rendering.
This fixes initial rotation problem on i965.
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Apparently some BIOSes will program a small mode with large blanking instead of
using the pannel fitter.
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I don't understand it, but just like the video overlay, if Pipe A is not
running, Pipe B will not turn the first time it is activated. This
patch restructures the code used for the video overlay to share it
with the crtc commit function.
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By clipping to the crtc ahead of time, xf86XVClipVideoHelper will
correctly clip to the bounds of the crtc, eliminating the need for any
custom crtc clipping.
Also, replace the broken xf86XVFillKeyHelper with a private version that
doesn't end up stuck with the wrong clip list when the root window changes
size.
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The overlay on the i830 appears to be clocked by Pipe A when being enabled.
If pipe A is not running, it will freeze the overlay and blank the screen.
Setting a random mode on the Pipe and turning it on fixes this problem
nicely.
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Create separate CRTC selection function, use ints instead of floats for
coverage measurement. Remove pipe stalls waiting for overlay update.
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