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This should be close to the last set of tiling fixes for 965 chipsets.
Prior to this commit, the 965 composite hook didn't take tiling into
account, nor did 965 textured video, which caused display corruption.
However, there seems to be at least one last bug to squash--on occasion,
a configuration with tiling enabled won't properly display text. This
is likely another tiling related problem with the composite hook.
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until we really implement it, OSD can't work for now.
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Note that this is a slowdown in text rendering due to the high overhead of our
compositing setup, but appears to be correct according to rendercheck.
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We don't have extra attributes than Xv port.
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Conflicts:
src/i830_exa.c
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The 915 and earlier appear to respect the fence registers, while only the 965
requires the per-operation tiling setting and pitch shifting. This will also
fix issues with rendering on the 965 involving multiple cliprects, where the
pitch would get divided repeatedly.
This removes the offset < 4096 fallback, which essentially resulted in no
acceleration to tiled buffers, hiding the issues.
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be called many times for the same pixmap, and we don't want
to keep dividing the pitch by 4.
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and put wrap function in driver xvmc priv instead of per xv port priv
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Reading the docs too literally can cause you to hide bugs with false fixes...
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PrepareSolid - combine pI830->tiling and frontbuffer checks into new exaPixmapTiled function for readability
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ssh://git.freedesktop.org/git/xorg/driver/xf86-video-intel
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- actually enable tiling in DSP(A|B)CNTR if needed
- add logic to EXA routines for tiled case (still needs work)
- enable/disable fbc on DPMS events (meant moving functions higher in file)
- fix fence register pitch programming (use correct pitch instead of kludged value)
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- add support for 965GM
- make sure legacy enabled systems don't reduce the range of backlight values we can present to the user
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A number of other interfaces of ours don't allow buffer offsets to be updated
after screeninit. This attempts to catalog why for each one, so that they
can be fixed one by one.
This happens to restore the EXA offscreen allocator for now, as a fixed-offset
object.
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The return value of GetScreenPixmap before CreateScreenResources is not, in
fact, a pixmap.
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If not available, AIGLX init will fail. While here, simplify DRIINFO tests
since we refuse to init with a version queried less than the version we
compiled against, anyway.
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From issue report http://lists.freedesktop.org/archives/xorg/2007-July/026644.html
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This one trys to use a flag for possible quirks. It adds a quirk
for my Lenovo T61 TV output, and ports some origin LVDS quirks to it.
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To do this, we have to deal with buffer offsets being set at EnterVT time
instead of screen init time. We've wanted to move this direction for a long
time, but there are repercussions. The EXA offscreen memory manager has to
be disabled, because it can't be moved. That will be replaced by BO-backed
pixmaps soon. Also unresolved is whether our moving
front/back/depth/texture buffers will break the classic-mode DRI driver.
This code doesn't actually work yet.
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This is a step towards being able to expose buffer objects through the screen
private to DRI clients, instead of having them have to use the fake buffer
object type.
This fails in two ways. First, the kernel memory manager is not currently
suitable for doing the physical allocations we need, so we still use AGP for
those. Additionally, the DRI lock can't be initialized early enough for us, so
these buffer object allocations fail. This will be fixed by improving the
DRM interface.
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Fence setting is in mapstate actually. This fixes rotation in
tiled fb case, thanks Keith to report this.
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which do have new host bridge ids
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dead lock.
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2. clean code
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2. fix an error in map_state
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2. implement macroblock_ipicture instruction
3. 16bit INTRA block
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