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No need to block for the overlay; just use the idle buffer. This will
always work because the buffer switch occurs at vblank time, so there is
always plenty of time to get the next buffer contents in place before it
starts getting scanned to the screen.
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Yes, I can't stand it anymore. it's a huge patch, but
git-diff -w shows no changes.
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Create separate on/continue/off functions for overlay.
Manage overlayOn boolean within those functions.
Eliminate redundant management code in other routines.
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This makes the overlay work on i830 with the modesetting driver. I don't
know why the pre-modesetting driver worked without this, but it did.
A more 'correct' fix would be welcome, but this does seem to do the trick.
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By default, select crtc based on which one covers more of the video output.
pipe property can be used to override selection when both have partial
coverage.
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Replace pipe indices with crtc indices and store references to the xf86Crtc
objects in the video private structure.
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When the hardware locks up, dump the pending commands in the ring for
analysis.
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That notify mesa rendering is smashing the state, and check last 3d
operation to do sync after we're swapped in or others.
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Use proper unsigned type for timer variables, and try to dump 965G state.
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Move clone/crtc config into each output where it's easier to understand (no
need for a switch statement in I830PrepareOutputs. Also, split DVO into
three sub-types (TMDS, LVDS, TVOUT) as those have different cloning
abilities.
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Using BIOS source code as a guide, set up the panel fitter on the ivch. This
involves setting the pipe to the panel fixed mode, the DVO to the source
size and assigning vertical and horizontal scaling factors in the ivch
itself.
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The DVO module interface reflected most of the xf86Output API to the
underlying functions; finish that work given the changes that have since
occurred in the xf86Output API.
Move the LVDS-specific code into the IVCH module and make that work on the
Thinkpad X30 (an i830-based laptop). Panel scaling does not work yet.
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Add-in modules have per-module data in the BIOS which contains configuration
information which cannot be entirely discovered.
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Chips newer than the i830 can force the border color for the active period
of the screen, allowing the load detection to easily see the right data. In
addition, newer chips appear to have more sensible load detection hardware
which either ignores inactive periods on the screen or performs some
longer-term averaging. The i830 appears to provide unfiltered samples of the
detected load.
For the i830, then, emit a border at the bottom of the screen and, for load
detection, simply turn it purple and wait for the current line to be within
the border. Sample an entire scanline, counting the number of times the load
detection sees a monitor. In my testing, the presence of a monitor will
cause the detection to succeed every time, while the absense will cause it
to fail about 75% of the time. The code here, checks for presence at least
75% of the time, which should be adequate.
Also, as the new mode configuration code has already taken care to enable
the CRT output, eliminate much of the load detection code which is simply
duplicating functionality from the general mode setting code. This should
result in faster load detection as this code will now run in no more than
one frame time. It does burn the CPU the whole time though, polling the
displayed scanline register.
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Reported by: Haihao Xiang <haihao.xiang@intel.com>
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The fixed panel timing will only be available when the LVDS is already on
at X startup.
So far, our only mostly-working LVDS driver is for the i830, and on i830 the
LVDS is always on DVOA, so use that for all LVDS chips. This may need to
change if we support the ch7017 I've seen used on embedded i845, for example.
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This disables all outputs on EnterVT as the SDVO output can confuse
the VGA output if the BIOS has enabled it on the same pipe but X
isn't going to use the SDVO.
Worked out on irc with keithp
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It had been necessary to allow more than a small amount of memory to be
allocated, but now those old small allocations people had configured are
getting in the way.
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Because stolen memory happens to be a contiguous block of high system memory,
we can just read the GTT entries for it to get physical addresses for our
allocations there if needed. This reduces fragmentation of the aperture space,
and will often reclaim up to 7 MB of memory that had been left unused since the
simplified aperture manager was put in place, but without reintroducing the
complexities of the old aperture manager.
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965G needs state mem buffer to setup render pipeline.
Thanks Barry Scrott for report this.
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The ihch DVO uses a modified I2C addressing scheme as described
in section 5.2 of the data sheet. Implement this by over-riding
the I2C read and write word routines.
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The server rotation code is now using the root window in IncludeInferiors
mode rather than using the screen pixmap. Change the XAA Composite code
to check for this case now.
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This was found when debug exa on a 865GV, we should set
pipeline state bits properly, otherwise the engine will hang.
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With the fixes to the 2D frame buffer allocation that allows up to 65536
lines of 2D frame buffer in XAA mode, the old linear allocation hacks are no
longer necessary.
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Convert relative X server source path to absolute. Check for local copies
of needed header files before building, rather than requiring server source.
Remove extra duplicate -I elements in AM_CFLAGS in sub directories.
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A closing brace was left inside #ifdef XF86DRI_MM while the matching
open brace was outside.
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usleep isn't always available, and we have an existing delay mechanism
available to use.
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and remove it from get attached displays call.
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Reported by JM Ibanez
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Reported by JM Ibanez.
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Bob deinterlacing in MythTV, and the zoom options in totem would result in
attempting to source from outside the video instead of scaling appropriately.
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displays. Ensures the command has completed before continuing.
(probably need to check PENDING in other SDVO calls too)
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Fix tex blend pipeline in case that src/mask pict has no
alpha. Unmask color buffer write disable bits. These make
rendercheck run fine on 855GM.
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Fallback in 830/845G when pict format is a8, x8r8g8b8 or
x8b8g8r8. The hw doesn't support them.
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