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Try to map texture stream when setup texture map, and use
correct order in load_immediate_1 cmd, which fixed crash on
845GV. Also remove some flush cmds.
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We should alloc xaa_linear mem in LinearAlloc case, otherwise
we get crash when initializing xf86 fb manager.
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This slipped in as a debugging aid, and never got turned off. The driver
appears to work fine without it on an i915 system, and for the non-default EXA
option, we'd rather see issues found than continue running with debugging aids
and hiding them behind bad performance.
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Thanks to alanc for catching this.
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i830_get_blend_cntl() has already added S8 offset.
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Pick fix from i915 render, change tex blend pipeline for CA.
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Use LOAD_IMM_2 helper cmd for tex setup. Enable RepeatNormal
support. Fix A8 format, i830 can support it now.
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crestline
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It was basing off of the clock rate, but we have an override to use the
existing dual channel state when we can detect it, so the two settings were
conflicting.
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crestline
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This allows the driver to report the set of valid formats in the property
data.
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crestline
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RRPostPendingProperty has been removed in favor of RRPostPendingProperties,
and that call is now managed outside of the driver.
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last_3d set to LAST_3D_OTHER indicates that the 3D hardware has unknown
state.
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AdjustFrame is strictly for legacy compatibility; calling it on EnterVT
wrecks crtc positions.
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crestline
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Several places were using byte lengths instead of unit lengths for
properties.
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Remove TV format from mode name, instead use an explicit output property and
split the input resolution from the tv format. Add properties to set the
blank area on all four sides of the image.
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crestline
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Originally we smashed vertex header to store texture
coordinates, this is working as we only use sf/wm kernel
and disable all other stages on pipeline. But better to
not do this. This also cleans up vertex elements state
and makes vertex buffer order looks "normal".
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The new sf/wm should handle the texture sampling only in
rotated case. Also fix possible hole in VUE slot.
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Conflicts:
src/i810_reg.h
src/i830_display.c
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- Use the existing single/dual-channel state when available, as changing it
doesn't appear to work out.
- Set the power state of the CLKB and B0-B3 pairs according to whether
choose to go dual-channel or not.
- Restore the LVDS register at the appropriate point (before DPLLs are
re-programmed.
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git://proxy.ims.intel.com:9419/git/xorg/driver/xf86-video-intel into crestline
Conflicts:
src/i830_display.c
Change LVDS output and postread like upstream. This might
need to be retested on 965GM LVDS.
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Failure to do so gets you a lot of pretty colors.
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For some reason, certain chips don't correctly enable the SDVO hardware when
this register is written only once. We're following what the BIOS code does
and writing it twice now, but with extra posting reads to boot. Yes, this is
cult-and-paste, but it fixes problems found on deployed hardware.
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Linux cannot allocate a large fixed buffer for the HW cursors as needed for
FreeBSD; instead, allocate four separate buffers. The code now prefers to
allocate one buffer (less overhead) and falls back to separate buffers only
when necessary.
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I830DRIClipNotify is passed to newer versions of DRI; don't include it in
the server when building against older versions.
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While we're just doing a memcpy, it's nice for the two argument types to
match.
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Changing this value slows the entire I2C bus down, making it far more
reliable on older monitors. Note the same change has been made in the core X
server code; this change is included here to ensure that older X servers
work reliably with this driver.
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Misplaced brace broke builds with older DRM libraries.
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Setting the value correctly and then immediately breaking it caused many I2C
transactions to timeout with slow monitors. Oops.
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Even current libpciaccess seems to require this.
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