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Uncomplicated API transistions for libpciaccess usage:
Legacy xf86 API libpciaccess API
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xf86ReadPciBIOS pci_device_read_rom
pciReadWord pci_device_cfg_read_u16
pciWriteByte pci_device_cfg_write_u8
And, more use of the API-independent DEVICE_ID/SUBVENDOR_ID/SUBSYS_ID macros
to pull PCI identification data from the underlying structure.
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The DRI interface requires bus identification for each DRI object; pull that
data from the libpciaccess structures as necessary.
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Using libpciaccess requires a different type for PciInfo (struct pci_device
instead of pciVideoPtr) and it requires knowing which BAR each memory region
needs to be mapped from. Add these definitions to the driver private record
along with the includes necessary to use libpciaccess.
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libpciaccess has a new structure that holds the PCI identifier data; borrow
macros from the mga driver to work with either the old xf86-specific
structure or the new libpciaccess structure.
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Detect whether the target X server uses libpciaccess, using it in the driver
compilation as necessary. This change means that utilities that used to use
libpciaccess will not do so unless the driver itself uses libpciaccess. Yes,
that could be fixed, but it doesn't seem that important.
This patch does not include any code changes necessary to actually have the
driver build against an X server using libpciaccess.
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The code was not consistently using XV_PIPE when the desired crtc contained
any portion of the video output.
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This requires EXA 2.2 (server 1.3) for rotated performance with EXA, because
the i830_memory.c allocation may not fall within what EXA considers the
offscreen area, so the PixmapIsOffscreen hook is needed.
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This should fix issues with XV being allocated into XAA's tiled pixmap
cache and resulting bad rendering. Its also brings us closer to being able
to shrink the size of the pixmap cache on XAA, which is of limited utility.
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ssh://git.freedesktop.org/git/xorg/driver/xf86-video-intel
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Add a new 'plane' field to the intel_crtc private structure for tracking
planes separate from pipes. This allows pre-965 chips to use plane A
on pipe B, enabling framebuffer compression for builtin LVDS displays.
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Conflicts:
src/i830_dri.c
src/i830_memory.c
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When TV does load detect, fb hasn't been setup, so we should check
that in i830_display_tiled(). Caught by Nanhai.
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Now that the driver sets these registers, they must be saved and restored.
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DSPATILEOFF and DSPBTILEOFF replace DSPASURF and DSPBSURF when the frame
buffer is in tiled mode.
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Front buffer tiling is now disabled with G965 and XAA. Some of the acceleration
that i830_xaa.c does can't be supported on tiled buffers.
Adds a tiling field to struct i830_memory, and uses it instead of separate
variables for each potential tiled buffer.
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TV mode names used to contain the signalling standard along with the pixel
size. The signalling has been moved to the TV_FORMAT property, but the
allocation and initialization of the mode name was left a bit messy as a
result.
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Remove an extra "FBC enabled" message from i830_memory.c (only report errors
if they occur), and don't print the "forcing FBC on" message if tiling was
already enabled, as it's redundant and confusing.
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This should be close to the last set of tiling fixes for 965 chipsets.
Prior to this commit, the 965 composite hook didn't take tiling into
account, nor did 965 textured video, which caused display corruption.
However, there seems to be at least one last bug to squash--on occasion,
a configuration with tiling enabled won't properly display text. This
is likely another tiling related problem with the composite hook.
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until we really implement it, OSD can't work for now.
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Note that this is a slowdown in text rendering due to the high overhead of our
compositing setup, but appears to be correct according to rendercheck.
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We don't have extra attributes than Xv port.
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Conflicts:
src/i830_exa.c
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The 915 and earlier appear to respect the fence registers, while only the 965
requires the per-operation tiling setting and pitch shifting. This will also
fix issues with rendering on the 965 involving multiple cliprects, where the
pitch would get divided repeatedly.
This removes the offset < 4096 fallback, which essentially resulted in no
acceleration to tiled buffers, hiding the issues.
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be called many times for the same pixmap, and we don't want
to keep dividing the pitch by 4.
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and put wrap function in driver xvmc priv instead of per xv port priv
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Reading the docs too literally can cause you to hide bugs with false fixes...
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PrepareSolid - combine pI830->tiling and frontbuffer checks into new exaPixmapTiled function for readability
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