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Diffstat (limited to 'src/libffmpeg/libavcodec/ppc/dsputil_ppc.c')
-rw-r--r--src/libffmpeg/libavcodec/ppc/dsputil_ppc.c158
1 files changed, 103 insertions, 55 deletions
diff --git a/src/libffmpeg/libavcodec/ppc/dsputil_ppc.c b/src/libffmpeg/libavcodec/ppc/dsputil_ppc.c
index 374309e37..7af2aa002 100644
--- a/src/libffmpeg/libavcodec/ppc/dsputil_ppc.c
+++ b/src/libffmpeg/libavcodec/ppc/dsputil_ppc.c
@@ -33,7 +33,7 @@ int mm_flags = 0;
int mm_support(void)
{
int result = 0;
-#if HAVE_ALTIVEC
+#ifdef HAVE_ALTIVEC
if (has_altivec()) {
result |= MM_ALTIVEC;
}
@@ -41,8 +41,8 @@ int mm_support(void)
return result;
}
-#ifdef POWERPC_TBL_PERFORMANCE_REPORT
-unsigned long long perfdata[powerpc_perf_total][powerpc_data_total];
+#ifdef POWERPC_PERFORMANCE_REPORT
+unsigned long long perfdata[POWERPC_NUM_PMC_ENABLED][powerpc_perf_total][powerpc_data_total];
/* list below must match enum in dsputil_ppc.h */
static unsigned char* perfname[] = {
"fft_calc_altivec",
@@ -57,46 +57,35 @@ static unsigned char* perfname[] = {
"put_no_rnd_pixels8_xy2_altivec",
"put_pixels16_xy2_altivec",
"put_no_rnd_pixels16_xy2_altivec",
- "clear_blocks_dcbz32_ppc"
+ "clear_blocks_dcbz32_ppc",
+ "clear_blocks_dcbz128_ppc"
};
-#ifdef POWERPC_PERF_USE_PMC
-unsigned long long perfdata_miss[powerpc_perf_total][powerpc_data_total];
-#endif
#include <stdio.h>
#endif
-#ifdef POWERPC_TBL_PERFORMANCE_REPORT
+#ifdef POWERPC_PERFORMANCE_REPORT
void powerpc_display_perf_report(void)
{
- int i;
-#ifndef POWERPC_PERF_USE_PMC
- fprintf(stderr, "PowerPC performance report\n Values are from the Time Base register, and represent 4 bus cycles.\n");
-#else /* POWERPC_PERF_USE_PMC */
+ int i, j;
fprintf(stderr, "PowerPC performance report\n Values are from the PMC registers, and represent whatever the registers are set to record.\n");
-#endif /* POWERPC_PERF_USE_PMC */
for(i = 0 ; i < powerpc_perf_total ; i++)
{
- if (perfdata[i][powerpc_data_num] != (unsigned long long)0)
- fprintf(stderr, " Function \"%s\" (pmc1):\n\tmin: %llu\n\tmax: %llu\n\tavg: %1.2lf (%llu)\n",
- perfname[i],
- perfdata[i][powerpc_data_min],
- perfdata[i][powerpc_data_max],
- (double)perfdata[i][powerpc_data_sum] /
- (double)perfdata[i][powerpc_data_num],
- perfdata[i][powerpc_data_num]);
-#ifdef POWERPC_PERF_USE_PMC
- if (perfdata_miss[i][powerpc_data_num] != (unsigned long long)0)
- fprintf(stderr, " Function \"%s\" (pmc2):\n\tmin: %llu\n\tmax: %llu\n\tavg: %1.2lf (%llu)\n",
- perfname[i],
- perfdata_miss[i][powerpc_data_min],
- perfdata_miss[i][powerpc_data_max],
- (double)perfdata_miss[i][powerpc_data_sum] /
- (double)perfdata_miss[i][powerpc_data_num],
- perfdata_miss[i][powerpc_data_num]);
-#endif
+ for (j = 0; j < POWERPC_NUM_PMC_ENABLED ; j++)
+ {
+ if (perfdata[j][i][powerpc_data_num] != (unsigned long long)0)
+ fprintf(stderr,
+ " Function \"%s\" (pmc%d):\n\tmin: %llu\n\tmax: %llu\n\tavg: %1.2lf (%llu)\n",
+ perfname[i],
+ j+1,
+ perfdata[j][i][powerpc_data_min],
+ perfdata[j][i][powerpc_data_max],
+ (double)perfdata[j][i][powerpc_data_sum] /
+ (double)perfdata[j][i][powerpc_data_num],
+ perfdata[j][i][powerpc_data_num]);
+ }
}
}
-#endif /* POWERPC_TBL_PERFORMANCE_REPORT */
+#endif /* POWERPC_PERFORMANCE_REPORT */
/* ***** WARNING ***** WARNING ***** WARNING ***** */
/*
@@ -110,13 +99,25 @@ void powerpc_display_perf_report(void)
It simply clear to zero a single cache line,
so you need to know the cache line size to use it !
It's absurd, but it's fast...
+
+ update 24/06/2003 : Apple released yesterday the G5,
+ with a PPC970. cache line size : 128 bytes. Oups.
+ The semantic of dcbz was changed, it always clear
+ 32 bytes. so the function below will work, but will
+ be slow. So I fixed check_dcbz_effect to use dcbzl,
+ which is defined to clear a cache line (as dcbz before).
+ So we still can distinguish, and use dcbz (32 bytes)
+ or dcbzl (one cache line) as required.
+
+ see <http://developer.apple.com/technotes/tn/tn2087.html>
+ and <http://developer.apple.com/technotes/tn/tn2086.html>
*/
void clear_blocks_dcbz32_ppc(DCTELEM *blocks)
{
-POWERPC_TBL_DECLARE(powerpc_clear_blocks_dcbz32, 1);
+POWERPC_PERF_DECLARE(powerpc_clear_blocks_dcbz32, 1);
register int misal = ((unsigned long)blocks & 0x00000010);
register int i = 0;
-POWERPC_TBL_START_COUNT(powerpc_clear_blocks_dcbz32, 1);
+POWERPC_PERF_START_COUNT(powerpc_clear_blocks_dcbz32, 1);
#if 1
if (misal) {
((unsigned long*)blocks)[0] = 0L;
@@ -126,7 +127,7 @@ POWERPC_TBL_START_COUNT(powerpc_clear_blocks_dcbz32, 1);
i += 16;
}
for ( ; i < sizeof(DCTELEM)*6*64 ; i += 32) {
- asm volatile("dcbz %0,%1" : : "r" (blocks), "r" (i) : "memory");
+ asm volatile("dcbz %0,%1" : : "b" (blocks), "r" (i) : "memory");
}
if (misal) {
((unsigned long*)blocks)[188] = 0L;
@@ -138,11 +139,48 @@ POWERPC_TBL_START_COUNT(powerpc_clear_blocks_dcbz32, 1);
#else
memset(blocks, 0, sizeof(DCTELEM)*6*64);
#endif
-POWERPC_TBL_STOP_COUNT(powerpc_clear_blocks_dcbz32, 1);
+POWERPC_PERF_STOP_COUNT(powerpc_clear_blocks_dcbz32, 1);
+}
+
+/* same as above, when dcbzl clear a whole 128B cache line
+ i.e. the PPC970 aka G5 */
+#ifndef NO_DCBZL
+void clear_blocks_dcbz128_ppc(DCTELEM *blocks)
+{
+POWERPC_PERF_DECLARE(powerpc_clear_blocks_dcbz128, 1);
+ register int misal = ((unsigned long)blocks & 0x0000007f);
+ register int i = 0;
+POWERPC_PERF_START_COUNT(powerpc_clear_blocks_dcbz128, 1);
+#if 1
+ if (misal) {
+ // we could probably also optimize this case,
+ // but there's not much point as the machines
+ // aren't available yet (2003-06-26)
+ memset(blocks, 0, sizeof(DCTELEM)*6*64);
+ }
+ else
+ for ( ; i < sizeof(DCTELEM)*6*64 ; i += 128) {
+ asm volatile("dcbzl %0,%1" : : "b" (blocks), "r" (i) : "memory");
+ }
+#else
+ memset(blocks, 0, sizeof(DCTELEM)*6*64);
+#endif
+POWERPC_PERF_STOP_COUNT(powerpc_clear_blocks_dcbz128, 1);
+}
+#else
+void clear_blocks_dcbz128_ppc(DCTELEM *blocks)
+{
+ memset(blocks, 0, sizeof(DCTELEM)*6*64);
}
+#endif
+#ifndef NO_DCBZL
/* check dcbz report how many bytes are set to 0 by dcbz */
-long check_dcbz_effect(void)
+/* update 24/06/2003 : replace dcbz by dcbzl to get
+ the intended effect (Apple "fixed" dcbz)
+ unfortunately this cannot be used unless the assembler
+ knows about dcbzl ... */
+long check_dcbzl_effect(void)
{
register char *fakedata = (char*)av_malloc(1024);
register char *fakedata_middle;
@@ -159,7 +197,9 @@ long check_dcbz_effect(void)
memset(fakedata, 0xFF, 1024);
- asm volatile("dcbz %0, %1" : : "r" (fakedata_middle), "r" (zero));
+ /* below the constraint "b" seems to mean "Address base register"
+ in gcc-3.3 / RS/6000 speaks. seems to avoid using r0, so.... */
+ asm volatile("dcbzl %0, %1" : : "b" (fakedata_middle), "r" (zero));
for (i = 0; i < 1024 ; i ++)
{
@@ -171,20 +211,29 @@ long check_dcbz_effect(void)
return count;
}
+#else
+long check_dcbzl_effect(void)
+{
+ return 0;
+}
+#endif
void dsputil_init_ppc(DSPContext* c, AVCodecContext *avctx)
{
- // Common optimisations whether Altivec or not
+ // Common optimizations whether Altivec is available or not
- switch (check_dcbz_effect()) {
+ switch (check_dcbzl_effect()) {
case 32:
c->clear_blocks = clear_blocks_dcbz32_ppc;
break;
+ case 128:
+ c->clear_blocks = clear_blocks_dcbz128_ppc;
+ break;
default:
break;
}
-#if HAVE_ALTIVEC
+#ifdef HAVE_ALTIVEC
if (has_altivec()) {
mm_flags |= MM_ALTIVEC;
@@ -207,6 +256,8 @@ void dsputil_init_ppc(DSPContext* c, AVCodecContext *avctx)
c->add_bytes= add_bytes_altivec;
#endif /* 0 */
c->put_pixels_tab[0][0] = put_pixels16_altivec;
+ /* the tow functions do the same thing, so use the same code */
+ c->put_no_rnd_pixels_tab[0][0] = put_pixels16_altivec;
c->avg_pixels_tab[0][0] = avg_pixels16_altivec;
// next one disabled as it's untested.
#if 0
@@ -231,24 +282,21 @@ void dsputil_init_ppc(DSPContext* c, AVCodecContext *avctx)
#endif /* ALTIVEC_USE_REFERENCE_C_CODE */
}
-#ifdef POWERPC_TBL_PERFORMANCE_REPORT
+#ifdef POWERPC_PERFORMANCE_REPORT
{
- int i;
+ int i, j;
for (i = 0 ; i < powerpc_perf_total ; i++)
{
- perfdata[i][powerpc_data_min] = 0xFFFFFFFFFFFFFFFF;
- perfdata[i][powerpc_data_max] = 0x0000000000000000;
- perfdata[i][powerpc_data_sum] = 0x0000000000000000;
- perfdata[i][powerpc_data_num] = 0x0000000000000000;
-#ifdef POWERPC_PERF_USE_PMC
- perfdata_miss[i][powerpc_data_min] = 0xFFFFFFFFFFFFFFFF;
- perfdata_miss[i][powerpc_data_max] = 0x0000000000000000;
- perfdata_miss[i][powerpc_data_sum] = 0x0000000000000000;
- perfdata_miss[i][powerpc_data_num] = 0x0000000000000000;
-#endif /* POWERPC_PERF_USE_PMC */
- }
+ for (j = 0; j < POWERPC_NUM_PMC_ENABLED ; j++)
+ {
+ perfdata[j][i][powerpc_data_min] = (unsigned long long)0xFFFFFFFFFFFFFFFF;
+ perfdata[j][i][powerpc_data_max] = (unsigned long long)0x0000000000000000;
+ perfdata[j][i][powerpc_data_sum] = (unsigned long long)0x0000000000000000;
+ perfdata[j][i][powerpc_data_num] = (unsigned long long)0x0000000000000000;
+ }
+ }
}
-#endif /* POWERPC_TBL_PERFORMANCE_REPORT */
+#endif /* POWERPC_PERFORMANCE_REPORT */
} else
#endif /* HAVE_ALTIVEC */
{
generated by cgit v1.2.3 (git 2.25.1) at 2025-06-02 18:12:41 +0000