From bb7a31a69bac993ffb9cfb195b84c1e374308e08 Mon Sep 17 00:00:00 2001 From: Daniel Caujolle-Bert Date: Sat, 1 Jun 2002 14:08:36 +0000 Subject: Add vidix/libdha from mplayerxp and Miguel's video ouput vidix. CVS patchset: 1976 CVS date: 2002/06/01 14:08:36 --- src/video_out/Makefile.am | 20 +- src/video_out/libdha/AsmMacros.h | 117 + src/video_out/libdha/Makefile.am | 43 + src/video_out/libdha/README | 12 + src/video_out/libdha/bin/Makefile.am | 12 + src/video_out/libdha/bin/README | 6 + src/video_out/libdha/bin/mapdev.copyright | 70 + src/video_out/libdha/bin/mapdev.vxd | Bin 0 -> 5780 bytes src/video_out/libdha/kernelhelper/Makefile.am | 41 + src/video_out/libdha/kernelhelper/README | 34 + src/video_out/libdha/kernelhelper/dhahelper.c | 416 ++ src/video_out/libdha/kernelhelper/dhahelper.h | 78 + src/video_out/libdha/kernelhelper/test.c | 60 + src/video_out/libdha/libdha.c | 156 + src/video_out/libdha/libdha.h | 96 + src/video_out/libdha/mmi.c | 57 + src/video_out/libdha/mtrr.c | 85 + src/video_out/libdha/oth/Makefile.am | 12 + src/video_out/libdha/oth/pci.db | 6074 +++++++++++++++++++++++ src/video_out/libdha/pci.c | 739 +++ src/video_out/libdha/pci_db2c.awk | 267 + src/video_out/libdha/sysdep/AsmMacros_alpha.h | 26 + src/video_out/libdha/sysdep/AsmMacros_arm32.h | 50 + src/video_out/libdha/sysdep/AsmMacros_ia64.h | 16 + src/video_out/libdha/sysdep/AsmMacros_powerpc.h | 62 + src/video_out/libdha/sysdep/AsmMacros_sparc.h | 53 + src/video_out/libdha/sysdep/AsmMacros_x86.h | 162 + src/video_out/libdha/sysdep/Makefile.am | 18 + src/video_out/libdha/sysdep/libdha_os2.c | 161 + src/video_out/libdha/sysdep/libdha_win32.c | 70 + src/video_out/libdha/sysdep/pci_386bsd.c | 38 + src/video_out/libdha/sysdep/pci_alpha.c | 29 + src/video_out/libdha/sysdep/pci_arm32.c | 60 + src/video_out/libdha/sysdep/pci_bsdi.c | 39 + src/video_out/libdha/sysdep/pci_freebsd.c | 41 + src/video_out/libdha/sysdep/pci_ia64.c | 60 + src/video_out/libdha/sysdep/pci_isc.c | 32 + src/video_out/libdha/sysdep/pci_linux.c | 48 + src/video_out/libdha/sysdep/pci_lynx.c | 93 + src/video_out/libdha/sysdep/pci_mach386.c | 25 + src/video_out/libdha/sysdep/pci_netbsd.c | 44 + src/video_out/libdha/sysdep/pci_openbsd.c | 24 + src/video_out/libdha/sysdep/pci_os2.c | 55 + src/video_out/libdha/sysdep/pci_powerpc.c | 28 + src/video_out/libdha/sysdep/pci_sco.c | 33 + src/video_out/libdha/sysdep/pci_sparc.c | 60 + src/video_out/libdha/sysdep/pci_svr4.c | 42 + src/video_out/libdha/sysdep/pci_win32.c | 18 + src/video_out/libdha/sysdep/pci_x86.c | 60 + src/video_out/libdha/test.c | 27 + src/video_out/video_out_vidix.c | 872 ++++ src/video_out/vidix/Makefile.am | 32 + src/video_out/vidix/README | 7 + src/video_out/vidix/drivers/Makefile.am | 59 + src/video_out/vidix/drivers/genfb_vid.c | 145 + src/video_out/vidix/drivers/mach64.h | 2481 +++++++++ src/video_out/vidix/drivers/mach64_vid.c | 1068 ++++ src/video_out/vidix/drivers/mga_vid.c | 1488 ++++++ src/video_out/vidix/drivers/nvidia.h | 55 + src/video_out/vidix/drivers/nvidia_vid.c | 326 ++ src/video_out/vidix/drivers/pm3_regs.h | 1113 +++++ src/video_out/vidix/drivers/pm3_vid.c | 370 ++ src/video_out/vidix/drivers/radeon.h | 2156 ++++++++ src/video_out/vidix/drivers/radeon_vid.c | 1610 ++++++ src/video_out/vidix/fourcc.h | 66 + src/video_out/vidix/vidix.h | 293 ++ src/video_out/vidix/vidix.txt | 154 + src/video_out/vidix/vidixlib.c | 337 ++ src/video_out/vidix/vidixlib.h | 101 + 69 files changed, 22599 insertions(+), 3 deletions(-) create mode 100644 src/video_out/libdha/AsmMacros.h create mode 100644 src/video_out/libdha/Makefile.am create mode 100644 src/video_out/libdha/README create mode 100644 src/video_out/libdha/bin/Makefile.am create mode 100644 src/video_out/libdha/bin/README create mode 100644 src/video_out/libdha/bin/mapdev.copyright create mode 100644 src/video_out/libdha/bin/mapdev.vxd create mode 100644 src/video_out/libdha/kernelhelper/Makefile.am create mode 100644 src/video_out/libdha/kernelhelper/README create mode 100644 src/video_out/libdha/kernelhelper/dhahelper.c create mode 100644 src/video_out/libdha/kernelhelper/dhahelper.h create mode 100644 src/video_out/libdha/kernelhelper/test.c create mode 100644 src/video_out/libdha/libdha.c create mode 100644 src/video_out/libdha/libdha.h create mode 100644 src/video_out/libdha/mmi.c create mode 100644 src/video_out/libdha/mtrr.c create mode 100644 src/video_out/libdha/oth/Makefile.am create mode 100644 src/video_out/libdha/oth/pci.db create mode 100644 src/video_out/libdha/pci.c create mode 100644 src/video_out/libdha/pci_db2c.awk create mode 100644 src/video_out/libdha/sysdep/AsmMacros_alpha.h create mode 100644 src/video_out/libdha/sysdep/AsmMacros_arm32.h create mode 100644 src/video_out/libdha/sysdep/AsmMacros_ia64.h create mode 100644 src/video_out/libdha/sysdep/AsmMacros_powerpc.h create mode 100644 src/video_out/libdha/sysdep/AsmMacros_sparc.h create mode 100644 src/video_out/libdha/sysdep/AsmMacros_x86.h create mode 100644 src/video_out/libdha/sysdep/Makefile.am create mode 100644 src/video_out/libdha/sysdep/libdha_os2.c create mode 100644 src/video_out/libdha/sysdep/libdha_win32.c create mode 100644 src/video_out/libdha/sysdep/pci_386bsd.c create mode 100644 src/video_out/libdha/sysdep/pci_alpha.c create mode 100644 src/video_out/libdha/sysdep/pci_arm32.c create mode 100644 src/video_out/libdha/sysdep/pci_bsdi.c create mode 100644 src/video_out/libdha/sysdep/pci_freebsd.c create mode 100644 src/video_out/libdha/sysdep/pci_ia64.c create mode 100644 src/video_out/libdha/sysdep/pci_isc.c create mode 100644 src/video_out/libdha/sysdep/pci_linux.c create mode 100644 src/video_out/libdha/sysdep/pci_lynx.c create mode 100644 src/video_out/libdha/sysdep/pci_mach386.c create mode 100644 src/video_out/libdha/sysdep/pci_netbsd.c create mode 100644 src/video_out/libdha/sysdep/pci_openbsd.c create mode 100644 src/video_out/libdha/sysdep/pci_os2.c create mode 100644 src/video_out/libdha/sysdep/pci_powerpc.c create mode 100644 src/video_out/libdha/sysdep/pci_sco.c create mode 100644 src/video_out/libdha/sysdep/pci_sparc.c create mode 100644 src/video_out/libdha/sysdep/pci_svr4.c create mode 100644 src/video_out/libdha/sysdep/pci_win32.c create mode 100644 src/video_out/libdha/sysdep/pci_x86.c create mode 100644 src/video_out/libdha/test.c create mode 100644 src/video_out/video_out_vidix.c create mode 100644 src/video_out/vidix/Makefile.am create mode 100644 src/video_out/vidix/README create mode 100644 src/video_out/vidix/drivers/Makefile.am create mode 100644 src/video_out/vidix/drivers/genfb_vid.c create mode 100644 src/video_out/vidix/drivers/mach64.h create mode 100644 src/video_out/vidix/drivers/mach64_vid.c create mode 100644 src/video_out/vidix/drivers/mga_vid.c create mode 100644 src/video_out/vidix/drivers/nvidia.h create mode 100644 src/video_out/vidix/drivers/nvidia_vid.c create mode 100644 src/video_out/vidix/drivers/pm3_regs.h create mode 100644 src/video_out/vidix/drivers/pm3_vid.c create mode 100644 src/video_out/vidix/drivers/radeon.h create mode 100644 src/video_out/vidix/drivers/radeon_vid.c create mode 100644 src/video_out/vidix/fourcc.h create mode 100644 src/video_out/vidix/vidix.h create mode 100644 src/video_out/vidix/vidix.txt create mode 100644 src/video_out/vidix/vidixlib.c create mode 100644 src/video_out/vidix/vidixlib.h (limited to 'src') diff --git a/src/video_out/Makefile.am b/src/video_out/Makefile.am index 733bab373..a11d64bde 100644 --- a/src/video_out/Makefile.am +++ b/src/video_out/Makefile.am @@ -1,5 +1,9 @@ -CFLAGS = @CFLAGS@ $(X_CFLAGS) $(LIBMPEG2_CFLAGS) -DXINE_COMPILE $(SDL_CFLAGS) -DEBUG_CFLAGS = @DEBUG_CFLAGS@ $(X_CFLAGS) $(LIBMPEG2_CFLAGS) -DXINE_COMPILE $(SDL_CFLAGS) +SUBDIRS = libdha vidix + +VIDIX_CFLAGS = -I$(top_builddir)/src/video_out/vidix -I$(top_srcdir)/src/video_out/vidix + +CFLAGS = @CFLAGS@ $(X_CFLAGS) $(LIBMPEG2_CFLAGS) -DXINE_COMPILE $(SDL_CFLAGS) $(VIDIX_CFLAGS) +DEBUG_CFLAGS = @DEBUG_CFLAGS@ $(X_CFLAGS) $(LIBMPEG2_CFLAGS) -DXINE_COMPILE $(SDL_CFLAGS) $(VIDIX_CFLAGS) LIBTOOL = $(SHELL) $(top_builddir)/libtool-nofpic @@ -8,6 +12,9 @@ libdir = $(XINE_PLUGINDIR) if HAVE_X11 xshm_module = xineplug_vo_out_xshm.la syncfb_module = xineplug_vo_out_syncfb.la +if HAVE_VIDIX +vidix_module = xineplug_vo_out_vidix.la +endif if HAVE_XV xv_module = xineplug_vo_out_xv.la endif @@ -40,7 +47,7 @@ endif # "xineplug_vo_out_*" lib_LTLIBRARIES = $(xshm_module) $(xv_module) $(directfb_module) $(aa_module) \ - $(syncfb_module) $(fb_module) $(opengl_module) $(sdl_module) + $(syncfb_module) $(fb_module) $(opengl_module) $(sdl_module) $(vidix_module) xineplug_vo_out_xv_la_SOURCES = deinterlace.c alphablend.c video_out_xv.c xineplug_vo_out_xv_la_LIBADD = $(XV_LIB) $(X_LIBS) -lXext \ @@ -79,6 +86,10 @@ xineplug_vo_out_sdl_la_SOURCES = alphablend.c video_out_sdl.c xineplug_vo_out_sdl_la_LIBADD = $(SDL_LIBS) xineplug_vo_out_sdl_la_LDFLAGS = -avoid-version -module +xineplug_vo_out_vidix_la_SOURCES = alphablend.c video_out_vidix.c +xineplug_vo_out_vidix_la_LIBADD = $(X_LIBS) $(top_builddir)/src/video_out/vidix/libvidix.la +xineplug_vo_out_vidix_la_LDFLAGS = -avoid-version -module + noinst_HEADERS = yuv2rgb.h video_out_syncfb.h alphablend.h deinterlace.h include_HEADERS = video_out_x11.h @@ -87,6 +98,9 @@ debug: @$(MAKE) CFLAGS="$(DEBUG_CFLAGS) -DXINE_COMPILE" install-debug: debug + @list='$(SUBDIRS)'; for subdir in $$list; do \ + (cd $$subdir && $(MAKE) $@) || exit;\ + done; @$(MAKE) $(AM_MAKEFLAGS) install-exec-am install-data-am ### diff --git a/src/video_out/libdha/AsmMacros.h b/src/video_out/libdha/AsmMacros.h new file mode 100644 index 000000000..5e4e1addc --- /dev/null +++ b/src/video_out/libdha/AsmMacros.h @@ -0,0 +1,117 @@ +/* $XConsortium: AsmMacros.h /main/13 1996/10/25 11:33:12 kaleb $ */ +/* + * (c) Copyright 1993,1994 by David Wexelblat + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * DAVID WEXELBLAT BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF + * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + * + * Except as contained in this notice, the name of David Wexelblat shall not be + * used in advertising or otherwise to promote the sale, use or other dealings + * in this Software without prior written authorization from David Wexelblat. + * + */ +/* + * Copyright 1997 + * Digital Equipment Corporation. All rights reserved. + * This software is furnished under license and may be used and copied only in + * accordance with the following terms and conditions. Subject to these + * conditions, you may download, copy, install, use, modify and distribute + * this software in source and/or binary form. No title or ownership is + * transferred hereby. + * + * 1) Any source code used, modified or distributed must reproduce and retain + * this copyright notice and list of conditions as they appear in the source + * file. + * + * 2) No right is granted to use any trade name, trademark, or logo of Digital + * Equipment Corporation. Neither the "Digital Equipment Corporation" name + * nor any trademark or logo of Digital Equipment Corporation may be used + * to endorse or promote products derived from this software without the + * prior written permission of Digital Equipment Corporation. + * + * 3) This software is provided "AS-IS" and any express or implied warranties, + * including but not limited to, any implied warranties of merchantability, + * fitness for a particular purpose, or non-infringement are disclaimed. In + * no event shall DIGITAL be liable for any damages whatsoever, and in + * particular, DIGITAL shall not be liable for special, indirect, + * consequential, or incidental damages or damages for + * lost profits, loss of revenue or loss of use, whether such damages arise + * in contract, + * negligence, tort, under statute, in equity, at law or otherwise, even if + * advised of the possibility of such damage. + * + */ + +/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/chips/util/AsmMacros.h,v 1.1 2001/11/16 21:13:34 tsi Exp $ */ + +/* + * Modified for readability by Nick Kurshev +*/ + +#if defined(__GNUC__) +#if defined(__alpha__) +#include "sysdep/AsmMacros_alpha.h" +#elif defined(__ia64__) +#include "sysdep/AsmMacros_ia64.h" +#elif defined(__sparc__) +#include "sysdep/AsmMacros_sparc.h" +#elif defined( __arm32__ ) +#include "sysdep/AsmMacros_arm32.h" +#elif defined(__powerpc__) +#include "sysdep/AsmMacros_powerpc.h" +#else +#include "sysdep/AsmMacros_x86.h" +#endif + +#else /* __GNUC__ */ + +#if defined(_MINIX) && defined(_ACK) + +/* inb, outb, inw and outw are defined in the library */ +/* ... but I've no idea if the same is true for inl & outl */ + +u8_t inb(U16_t); +void outb(U16_t, U8_t); +u16_t inw(U16_t); +void outw(U16_t, U16_t); +u32_t inl(U16_t); +void outl(U16_t, U32_t); + +#else /* not _MINIX and _ACK */ + +# if defined(__STDC__) && (__STDC__ == 1) +# ifndef NCR +# define asm __asm +# endif +# endif +# ifdef SVR4 +# include +# ifndef __USLC__ +# define __USLC__ +# endif +# endif +#ifndef SCO325 +# include +#else +# include "../common/scoasm.h" +#endif +#define intr_disable() asm("cli") +#define intr_enable() asm("sti") + +#endif /* _MINIX and _ACK */ +#endif /* __GNUC__ */ diff --git a/src/video_out/libdha/Makefile.am b/src/video_out/libdha/Makefile.am new file mode 100644 index 000000000..b21838533 --- /dev/null +++ b/src/video_out/libdha/Makefile.am @@ -0,0 +1,43 @@ +EXTRA_DIST = README pci_db2c.awk + +SUBDIRS = bin kernelhelper oth sysdep + +CFLAGS = @CFLAGS@ @STATIC@ + +if HAVE_VIDIX +dha_lib = libdha.la +endif + +noinst_LTLIBRARIES = $(dha_lib) + +libdha_la_SOURCES = libdha.c mtrr.c pci.c pci_names.c mmi.c +libdha_la_DEPENDENCIES = pci_names.c + +EXTRA_PROGRAMS = test + +test_SOURCES = test.c +test_LDADD = $(top_builddir)/src/video_out/libdha/libdha.la + +noinst_HEADERS = AsmMacros.h libdha.h + +## for OpenBSD LIBS += -li386 +pci_names.c: + $(AWK) -f pci_db2c.awk oth/pci.db + +debug: + @$(MAKE) CFLAGS="$(DEBUG_CFLAGS) @STATIC@ -DXINE_COMPILE" + +install-debug: debug + @list='$(SUBDIRS)'; for subdir in $$list; do \ + (cd $$subdir && $(MAKE) $@) || exit;\ + done; + @$(MAKE) $(AM_MAKEFLAGS) install-exec-am install-data-am + +mostlyclean-generic: + -rm -f *~ \#* .*~ .\#* test + -rm -f pci_dev_ids.c pci_ids.h pci_names.c pci_names.h pci_vendors.h + +maintainer-clean-generic: + -@echo "This command is intended for maintainers to use;" + -@echo "it deletes files that may require special tools to rebuild." + -rm -f Makefile.in diff --git a/src/video_out/libdha/README b/src/video_out/libdha/README new file mode 100644 index 000000000..a855880cd --- /dev/null +++ b/src/video_out/libdha/README @@ -0,0 +1,12 @@ +libdha - Library of Direct Hardware Access. +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +This library was designed for direct hardware access under different +OS and architectures. It's not linux specific only (like harddrake +and other). + +This library is based on gfxdump utility from GATOS project. +Full list of supported OS'es see in libdha.h + +Note: This library requires ROOT privileges or SUID'ed executable +file (same as XServer). +(Or use newly developed libdha kernel helper. Look at kernelhelper/dhahelper.c) diff --git a/src/video_out/libdha/bin/Makefile.am b/src/video_out/libdha/bin/Makefile.am new file mode 100644 index 000000000..88eac9aca --- /dev/null +++ b/src/video_out/libdha/bin/Makefile.am @@ -0,0 +1,12 @@ +EXTRA_DIST = README mapdev.copyright mapdev.vxd + +debug: +install-debug: + +mostlyclean-generic: + -rm -f *~ \#* .*~ .\#* + +maintainer-clean-generic: + -@echo "This command is intended for maintainers to use;" + -@echo "it deletes files that may require special tools to rebuild." + -rm -f Makefile.in diff --git a/src/video_out/libdha/bin/README b/src/video_out/libdha/bin/README new file mode 100644 index 000000000..fe4bfa6f3 --- /dev/null +++ b/src/video_out/libdha/bin/README @@ -0,0 +1,6 @@ +mapdev.vxd +~~~~~~~~~~ +mapdev.vxd - provides direct hardware access under Win9x. +install: Just copy it into %WINDOWS%\system folder and reboot. +note: This driver won't work under NT-based systems +(like WinNT, Win2000 and even WinME and WinXP due importing NT things). diff --git a/src/video_out/libdha/bin/mapdev.copyright b/src/video_out/libdha/bin/mapdev.copyright new file mode 100644 index 000000000..b22433d29 --- /dev/null +++ b/src/video_out/libdha/bin/mapdev.copyright @@ -0,0 +1,70 @@ +From khazzah@melita.com Mon Jun 23 21:48:19 1997 +Return-Path: +Received: from melita.melita.com by max4.rrze.uni-erlangen.de; Mon, 23 Jun 1997 21:48:16 +0200 +Received: from mailgate.melita.com ([192.68.22.8]) by melita.melita.com (8.6.12/8.6.9) with SMTP id QAA29292 for ; Mon, 23 Jun 1997 16:17:55 -0400 +Received: by mailgate.melita.com with Microsoft Mail + id <33AEFD34@mailgate.melita.com>; Mon, 23 Jun 97 15:48:20 PDT +From: Karen Hazzah +To: "'Stefan.Dirsch@stud.uni-erlangen.de'" +Subject: Your post to vxd newsgroup +Date: Sun, 22 Jun 97 20:51:00 PDT +Message-ID: <33AEFD34@mailgate.melita.com> +Encoding: 22 TEXT +X-Mailer: Microsoft Mail V3.0 + + +I posted an answer to your question in the newsgroup. I also have +additional information for you. + +I can email you the binary for VxD which does exactly what you need: +given a physical address, returns a pointer that can be used by a +Win32 application. I'll also give you source for a Win32 app which +uses the VxD to read an area of physical memory. + +I don't offer this solution to everyone, since in most cases the +proper solution is for them to write a VxD which interacts with their +hardware, rather than simply getting a pointer to the hardware and +interacting with it from an application. + +However, in your case, you're just using a VxD as a tool to get your +Linux driver working...you shouldn't have to write a VxD for this :-) + +Let me know if you're interested. +=============================================================================== +Hello Karen + +A long time ago, you sent me your VXD for reading an area of physical +memory under Win32, so I could make register dumps of the graphic +chip. Did I ever mention, that it works perfectly for me? + +Why I contact you is, that I really would like to offer this solution +to all XFree86 members, so that it will be much easier in the future +for XFree86 to develop drivers for graphic boards. + +Can I count with your agreement? Would you like to add a special +copyright to your software? + +Stefan +=============================================================================== +From KHazzah@melita.com Wed Mar 4 00:00:28 1998 +Return-Path: +Received: from melita.melita.com (melita.com [192.68.22.2]) + by Galois.suse.de (8.8.8/8.8.8) with SMTP id AAA03709 + for ; Wed, 4 Mar 1998 00:00:26 +0100 +Received: from norcross.melita.com (norcross.melita.com [192.68.22.10]) by melita.melita.com (8.6.12/8.6.9) with ESMTP id TAA31217 for ; Tue, 3 Mar 1998 19:48:10 -0500 +Received: by zippy.melita.com with Internet Mail Service (5.5.1960.3) + id ; Tue, 3 Mar 1998 18:00:26 -0500 +Message-ID: +From: "Hazzah, Karen" +To: Stefan Dirsch +Subject: RE: VXD binary for Win32 for reading an area of physical memory +Date: Tue, 3 Mar 1998 18:00:25 -0500 +MIME-Version: 1.0 +X-Mailer: Internet Mail Service (5.5.1960.3) +Content-Type: text/plain +Status: ROr + +OK, you have my permission to make it publicly available, as is. + +If you make it available on the web (ftp, etc.), please give me the +URL so I can refer others to it. diff --git a/src/video_out/libdha/bin/mapdev.vxd b/src/video_out/libdha/bin/mapdev.vxd new file mode 100644 index 000000000..e09194b84 Binary files /dev/null and b/src/video_out/libdha/bin/mapdev.vxd differ diff --git a/src/video_out/libdha/kernelhelper/Makefile.am b/src/video_out/libdha/kernelhelper/Makefile.am new file mode 100644 index 000000000..4d603c0e7 --- /dev/null +++ b/src/video_out/libdha/kernelhelper/Makefile.am @@ -0,0 +1,41 @@ +EXTRA_DIST = README dhahelper.c + +CFLAGS = -O2 -Wall -D__KERNEL__ -DMODULE + +## CLEAN ME +KVERSION = $(shell $(SHELL) -c 'uname -r') +MISC_KDIR = /lib/modules/$(KVERSION)/misc + +KCOMPILE = $(CC) $(CFLAGS) $(INCLUDES) $(LINUX_INCLUDE) + +noinst_HEADERS = dhahelper.h + +EXTRA_PROGRAMS = test +test_SOURCES = test.c + +dhahelper.o: + $(KCOMPILE) -c `test -f $< || echo '$(srcdir)/'`$< + +install-data-local: @HAVE_LINUX_TRUE@ dhahelper.o +@HAVE_LINUX_TRUE@ if test ! -d $(MISC_KDIR); then \ +@HAVE_LINUX_TRUE@ mkdir -p $(MISC_KDIR); \ +@HAVE_LINUX_TRUE@ fi +@HAVE_LINUX_TRUE@ $(INSTALL_DATA) dhahelper.o $(MISC_KDIR)/dhahelper.o +@HAVE_LINUX_TRUE@ $(DEPMOD) -a +@HAVE_LINUX_TRUE@ if test ! -c /dev/dhahelper; then \ +@HAVE_LINUX_TRUE@ $(MKNOD) -m 666 /dev/dhahelper c 180 0; \ +@HAVE_LINUX_TRUE@ fi + +uninstall-local: +@HAVE_LINUX_TRUE@ rm -f $(MISC_KDIR)/dhahelper.o + +debug: +install-debug: install + +mostlyclean-generic: + -rm -f *~ \#* .*~ .\#* test + +maintainer-clean-generic: + -@echo "This command is intended for maintainers to use;" + -@echo "it deletes files that may require special tools to rebuild." + -rm -f Makefile.in diff --git a/src/video_out/libdha/kernelhelper/README b/src/video_out/libdha/kernelhelper/README new file mode 100644 index 000000000..cb5964cb8 --- /dev/null +++ b/src/video_out/libdha/kernelhelper/README @@ -0,0 +1,34 @@ +dhahelper is small driver to provide some kernel function into userspace. +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +Main goal why you need to use that it's busmastering. +(Btw, lacking of possibility to implement convertion of +virtual addresses into physical in userspace caused +implementing of so-called DRM drivers for Linux from +XFree86 side). +Second goal (still is unfinished) - provide possibility +to control port and physical memory access through +groups and access rights of this driver. (Unix way). + +Installation: +~~~~~~~~~~~~~ +just type in this directory: +make all install + +If you have compiled this driver first-time then +type also: +make nodes + +Porting: +~~~~~~~~ +This driver was developed only for Linux. +So if someone will port that on other unicies +then any patches are gladly accepted. + +WARNING: +~~~~~~~~ +This driver violates some kernel's security rules. +To keep this driver from anonymous access I suggest +you create new group for mplayerxp and /dev/dhahelper +only. + +Good luck! diff --git a/src/video_out/libdha/kernelhelper/dhahelper.c b/src/video_out/libdha/kernelhelper/dhahelper.c new file mode 100644 index 000000000..f85b4efd1 --- /dev/null +++ b/src/video_out/libdha/kernelhelper/dhahelper.c @@ -0,0 +1,416 @@ +/* + Direct Hardware Access kernel helper + + (C) 2002 Alex Beregszaszi + + Accessing hardware from userspace as USER (no root needed!) + + Tested on 2.2.x (2.2.19) and 2.4.x (2.4.3,2.4.17). + + License: GPL + + WARNING! THIS MODULE VIOLATES SEVERAL SECURITY LINES! DON'T USE IT + ON PRODUCTION SYSTEMS, ONLY AT HOME, ON A "SINGLE-USER" SYSTEM. + NO WARRANTY! + + Tech: + Communication between userspace and kernelspace goes over character + device using ioctl. + + Usage: + mknod -m 666 /dev/dhahelper c 180 0 + + Also you can change the major number, setting the "dhahelper_major" + module parameter, the default is 180, specified in dhahelper.h. + + Note: do not use other than minor==0, the module forbids it. + + TODO: + * do memory mapping without fops:mmap + * implement unmap memory + * select (request?) a "valid" major number (from Linux project? ;) + * make security + * is pci handling needed? (libdha does this with lowlevel port funcs) + * is mttr handling needed? + * test on older kernels (2.0.x (?)) +*/ + +#ifndef MODULE +#define MODULE +#endif + +#ifndef __KERNEL__ +#define __KERNEL__ +#endif + +#include + +#ifdef CONFIG_MODVERSION +#define MODVERSION +#include +#endif + +#include +#include +#include +#include +#include +#include +#include +#include + +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,4,0) +#include +#else +#include +#endif + +#include +#include +#include + +#include +#include +#include + +#include + +#include +#include + +#include "dhahelper.h" + +MODULE_AUTHOR("Alex Beregszaszi "); +MODULE_DESCRIPTION("Provides userspace access to hardware (security violation!)"); +#ifdef MODULE_LICENSE +MODULE_LICENSE("GPL"); +#endif + +static int dhahelper_major = DEFAULT_MAJOR; +MODULE_PARM(dhahelper_major, "i"); +MODULE_PARM_DESC(dhahelper_major, "Major number of dhahelper characterdevice"); + +/* 0 = silent */ +/* 1 = report errors (default) */ +/* 2 = debug */ +static int dhahelper_verbosity = 1; +MODULE_PARM(dhahelper_verbosity, "i"); +MODULE_PARM_DESC(dhahelper_verbosity, "Level of verbosity (0 = silent, 1 = only errors, 2 = debug)"); + +static dhahelper_memory_t last_mem_request; + + +static int dhahelper_open(struct inode *inode, struct file *file) +{ + if (dhahelper_verbosity > 1) + printk(KERN_DEBUG "dhahelper: device opened\n"); + + if (MINOR(inode->i_rdev) != 0) + return -ENXIO; + + MOD_INC_USE_COUNT; + + return 0; +} + +static int dhahelper_release(struct inode *inode, struct file *file) +{ + if (dhahelper_verbosity > 1) + printk(KERN_DEBUG "dhahelper: device released\n"); + + if (MINOR(inode->i_rdev) != 0) + return -ENXIO; + + MOD_DEC_USE_COUNT; + + return 0; +} + +static int dhahelper_get_version(int * arg) +{ + int version = API_VERSION; + + if (copy_to_user(arg, &version, sizeof(int))) + { + if (dhahelper_verbosity > 0) + printk(KERN_ERR "dhahelper: failed copy to userspace\n"); + return -EFAULT; + } + return 0; +} + +static int dhahelper_port(dhahelper_port_t * arg) +{ + dhahelper_port_t port; + if (copy_from_user(&port, arg, sizeof(dhahelper_port_t))) + { + if (dhahelper_verbosity > 0) + printk(KERN_ERR "dhahelper: failed copy from userspace\n"); + return -EFAULT; + } + switch(port.operation) + { + case PORT_OP_READ: + { + switch(port.size) + { + case 1: + port.value = inb(port.addr); + break; + case 2: + port.value = inw(port.addr); + break; + case 4: + port.value = inl(port.addr); + break; + default: + if (dhahelper_verbosity > 0) + printk(KERN_ERR "dhahelper: invalid port read size (%d)\n", + port.size); + return -EINVAL; + } + break; + } + case PORT_OP_WRITE: + { + switch(port.size) + { + case 1: + outb(port.value, port.addr); + break; + case 2: + outw(port.value, port.addr); + break; + case 4: + outl(port.value, port.addr); + break; + default: + if (dhahelper_verbosity > 0) + printk(KERN_ERR "dhahelper: invalid port write size (%d)\n", + port.size); + return -EINVAL; + } + break; + } + default: + if (dhahelper_verbosity > 0) + printk(KERN_ERR "dhahelper: invalid port operation (%d)\n", + port.operation); + return -EINVAL; + } + /* copy back only if read was performed */ + if (port.operation == PORT_OP_READ) + if (copy_to_user(arg, &port, sizeof(dhahelper_port_t))) + { + if (dhahelper_verbosity > 0) + printk(KERN_ERR "dhahelper: failed copy to userspace\n"); + return -EFAULT; + } + return 0; +} + +static int dhahelper_memory(dhahelper_memory_t * arg) +{ + dhahelper_memory_t mem; + if (copy_from_user(&mem, arg, sizeof(dhahelper_memory_t))) + { + if (dhahelper_verbosity > 0) + printk(KERN_ERR "dhahelper: failed copy from userspace\n"); + return -EFAULT; + } + switch(mem.operation) + { + case MEMORY_OP_MAP: + { +#if 1 + memcpy(&last_mem_request, &mem, sizeof(dhahelper_memory_t)); +#else + mem.ret = do_mmap(file, mem.start, mem.size, PROT_READ|PROT_WRITE, + MAP_SHARED, mem.offset); +#endif + break; + } + case MEMORY_OP_UNMAP: + break; + default: + if (dhahelper_verbosity > 0) + printk(KERN_ERR "dhahelper: invalid memory operation (%d)\n", + mem.operation); + return -EINVAL; + } + if (copy_to_user(arg, &mem, sizeof(dhahelper_memory_t))) + { + if (dhahelper_verbosity > 0) + printk(KERN_ERR "dhahelper: failed copy to userspace\n"); + return -EFAULT; + } + return 0; +} + +static int dhahelper_virt_to_phys(dhahelper_vmi_t *arg) +{ + dhahelper_vmi_t mem; + unsigned long i,nitems; + char *addr; + if (copy_from_user(&mem, arg, sizeof(dhahelper_vmi_t))) + { + if (dhahelper_verbosity > 0) + printk(KERN_ERR "dhahelper: failed copy from userspace\n"); + return -EFAULT; + } + nitems = mem.length / PAGE_SIZE; + if(mem.length % PAGE_SIZE) nitems++; + addr = mem.virtaddr; + for(i=0;i 0) + printk(KERN_ERR "dhahelper: failed copy to userspace\n"); + return -EFAULT; + } + addr += PAGE_SIZE; + } + return 0; +} + +static int dhahelper_virt_to_bus(dhahelper_vmi_t *arg) +{ + dhahelper_vmi_t mem; + unsigned long i,nitems; + char *addr; + if (copy_from_user(&mem, arg, sizeof(dhahelper_vmi_t))) + { + if (dhahelper_verbosity > 0) + printk(KERN_ERR "dhahelper: failed copy from userspace\n"); + return -EFAULT; + } + nitems = mem.length / PAGE_SIZE; + if(mem.length % PAGE_SIZE) nitems++; + addr = mem.virtaddr; + for(i=0;i 0) + printk(KERN_ERR "dhahelper: failed copy to userspace\n"); + return -EFAULT; + } + addr += PAGE_SIZE; + } + return 0; +} + +static int dhahelper_ioctl(struct inode *inode, struct file *file, + unsigned int cmd, unsigned long arg) +{ + if (dhahelper_verbosity > 1) + printk(KERN_DEBUG "dhahelper: ioctl(cmd=%x, arg=%lx)\n", + cmd, arg); + + if (MINOR(inode->i_rdev) != 0) + return -ENXIO; + + switch(cmd) + { + case DHAHELPER_GET_VERSION: return dhahelper_get_version((int *)arg); + case DHAHELPER_PORT: return dhahelper_port((dhahelper_port_t *)arg); + case DHAHELPER_MEMORY: return dhahelper_memory((dhahelper_memory_t *)arg); + case DHAHELPER_VIRT_TO_PHYS:return dhahelper_virt_to_phys((dhahelper_vmi_t *)arg); + case DHAHELPER_VIRT_TO_BUS: return dhahelper_virt_to_bus((dhahelper_vmi_t *)arg); + default: + if (dhahelper_verbosity > 0) + printk(KERN_ERR "dhahelper: invalid ioctl (%x)\n", cmd); + return -EINVAL; + } + return 0; +} + +static int dhahelper_mmap(struct file *file, struct vm_area_struct *vma) +{ + if (last_mem_request.operation != MEMORY_OP_MAP) + { + if (dhahelper_verbosity > 0) + printk(KERN_ERR "dhahelper: mapping not requested before mmap\n"); + return -EFAULT; + } + + if (dhahelper_verbosity > 1) + printk(KERN_INFO "dhahelper: mapping %x (size: %x)\n", + last_mem_request.start+last_mem_request.offset, last_mem_request.size); + + if (remap_page_range(0, last_mem_request.start + last_mem_request.offset, + last_mem_request.size, vma->vm_page_prot)) + { + if (dhahelper_verbosity > 0) + printk(KERN_ERR "dhahelper: error mapping memory\n"); + return -EFAULT; + } + + return 0; +} + +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,4,0) +static struct file_operations dhahelper_fops = +{ + /*llseek*/ NULL, + /*read*/ NULL, + /*write*/ NULL, + /*readdir*/ NULL, + /*poll*/ NULL, + /*ioctl*/ dhahelper_ioctl, + /*mmap*/ dhahelper_mmap, + /*open*/ dhahelper_open, + /*flush*/ NULL, + /*release*/ dhahelper_release, + /* zero out the last 5 entries too ? */ +}; +#else +static struct file_operations dhahelper_fops = +{ + owner: THIS_MODULE, + ioctl: dhahelper_ioctl, + mmap: dhahelper_mmap, + open: dhahelper_open, + release: dhahelper_release +}; +#endif + +#if KERNEL_VERSION < KERNEL_VERSION(2,4,0) +int init_module(void) +#else +static int __init init_dhahelper(void) +#endif +{ + printk(KERN_INFO "Direct Hardware Access kernel helper (C) Alex Beregszaszi\n"); + + if(register_chrdev(dhahelper_major, "dhahelper", &dhahelper_fops)) + { + if (dhahelper_verbosity > 0) + printk(KERN_ERR "dhahelper: unable to register character device (major: %d)\n", + dhahelper_major); + return -EIO; + } + + return 0; +} + +#if KERNEL_VERSION < KERNEL_VERSION(2,4,0) +void cleanup_module(void) +#else +static void __exit exit_dhahelper(void) +#endif +{ + unregister_chrdev(dhahelper_major, "dhahelper"); +} + +EXPORT_NO_SYMBOLS; + +#if KERNEL_VERSION >= KERNEL_VERSION(2,4,0) +module_init(init_dhahelper); +module_exit(exit_dhahelper); +#endif diff --git a/src/video_out/libdha/kernelhelper/dhahelper.h b/src/video_out/libdha/kernelhelper/dhahelper.h new file mode 100644 index 000000000..2cbcb5550 --- /dev/null +++ b/src/video_out/libdha/kernelhelper/dhahelper.h @@ -0,0 +1,78 @@ +/* + Direct Hardware Access kernel helper + + (C) 2002 Alex Beregszaszi +*/ + +#ifndef DHAHELPER_H +#define DHAHELPER_H + +#include + +/* feel free to change */ +#define DEFAULT_MAJOR 180 + +#define API_VERSION 0x2 + +typedef struct dhahelper_port_s +{ +#define PORT_OP_READ 1 +#define PORT_OP_WRITE 2 + int operation; + int size; + int addr; + int value; +} dhahelper_port_t; + +typedef struct dhahelper_memory_s +{ +#define MEMORY_OP_MAP 1 +#define MEMORY_OP_UNMAP 2 + int operation; + int start; + int offset; + int size; + int ret; +#define MEMORY_FLAG_NOCACHE 1 + int flags; +} dhahelper_memory_t; + +typedef struct dhahelper_mtrr_s +{ +#define MTRR_OP_ADD 1 +#define MTRR_OP_DEL 2 + int operation; + int start; + int size; + int type; +} dhahelper_mtrr_t; + +typedef struct dhahelper_pci_s +{ +#define PCI_OP_READ 1 +#define PCI_OP_WRITE 1 + int operation; + int bus; + int dev; + int func; + int cmd; + int size; + int ret; +} dhahelper_pci_t; + +typedef struct dhahelper_vmi_s +{ + void * virtaddr; + unsigned long length; + unsigned long *realaddr; +}dhahelper_vmi_t; + +#define DHAHELPER_GET_VERSION _IOW('D', 0, int) +#define DHAHELPER_PORT _IOWR('D', 1, dhahelper_port_t) +#define DHAHELPER_MEMORY _IOWR('D', 2, dhahelper_memory_t) +#define DHAHELPER_MTRR _IOWR('D', 3, dhahelper_mtrr_t) +#define DHAHELPER_PCI _IOWR('D', 4, dhahelper_pci_t) +#define DHAHELPER_VIRT_TO_PHYS _IOWR('D', 5, dhahelper_vmi_t) +#define DHAHELPER_VIRT_TO_BUS _IOWR('D', 6, dhahelper_vmi_t) + +#endif /* DHAHELPER_H */ diff --git a/src/video_out/libdha/kernelhelper/test.c b/src/video_out/libdha/kernelhelper/test.c new file mode 100644 index 000000000..3dca94c74 --- /dev/null +++ b/src/video_out/libdha/kernelhelper/test.c @@ -0,0 +1,60 @@ +#include +#include +#include +#include +#include +#include +#include + +#include "dhahelper.h" + +int main(int argc, char *argv[]) +{ + int fd; + int ret; + + fd = open("/dev/dhahelper", O_RDWR); + + ioctl(fd, DHAHELPER_GET_VERSION, &ret); + + printf("api version: %d\n", ret); + if (ret != API_VERSION) + printf("incompatible api!\n"); + + { + dhahelper_memory_t mem; + + mem.operation = MEMORY_OP_MAP; + //mem.start = 0xe0000000; + mem.start = 0xe4000008; + mem.offset = 0; + mem.size = 0x4000; + mem.ret = 0; + + ret = ioctl(fd, DHAHELPER_MEMORY, &mem); + + printf("ret: %s\n", strerror(errno)); + + mem.ret = (int)mmap(NULL, (size_t)mem.size, PROT_READ, MAP_SHARED, fd, (off_t)0); + printf("allocated to %x\n", mem.ret); + + if (argc > 1) + if (mem.ret != 0) + { + int i; + + for (i = 0; i < 256; i++) + printf("[%x] ", *(int *)(mem.ret+i)); + printf("\n"); + } + + munmap((void *)mem.ret, mem.size); + + mem.operation = MEMORY_OP_UNMAP; + mem.start = mem.ret; + + ioctl(fd, DHAHELPER_MEMORY, &mem); + } + + return(0); +} diff --git a/src/video_out/libdha/libdha.c b/src/video_out/libdha/libdha.c new file mode 100644 index 000000000..dda6a6abd --- /dev/null +++ b/src/video_out/libdha/libdha.c @@ -0,0 +1,156 @@ +/* + libgha.c - Library for direct hardware access + Copyrights: + 1996/10/27 - Robin Cutshaw (robin@xfree86.org) + XFree86 3.3.3 implementation + 1999 - Øyvind Aabling. + Modified for GATOS/win/gfxdump. + + 2002 - library implementation by Nick Kurshev + - dhahelper and some changes by Alex Beregszaszi + + supported O/S's: SVR4, UnixWare, SCO, Solaris, + FreeBSD, NetBSD, 386BSD, BSDI BSD/386, + Linux, Mach/386, ISC + DOS (WATCOM 9.5 compiler), Win9x (with mapdev.vxd) + Licence: GPL + Original location: www.linuxvideo.org/gatos +*/ +#ifdef HAVE_CONFIG_H +#include "config.h" +#endif + +#include "libdha.h" +#include "AsmMacros.h" +#include +#include +#include +#include +#include +#include +#ifdef ARCH_ALPHA +#include +#endif +#include + +/* instead exit() use libdha_exit, and do the 'mother-application' deinit + only in this code */ +void libdha_exit(const char *message, int level) +{ + printf("libdha: FATAL: %s\n", message); + exit(level); /* FIXME */ +} + +#if defined(_WIN32) +#include "sysdep/libdha_win32.c" +#elif defined (__EMX__) +#include "sysdep/libdha_os2.c" +#else + +#if defined(SVR4) || defined(SCO325) +# if !(defined(sun) && defined (i386) && defined (SVR4)) +# define DEV_MEM "/dev/pmem" +# elif defined(PowerMAX_OS) +# define DEV_MEM "/dev/iomem" +# endif +# ifdef SCO325 +# undef DEV_MEM +# define DEV_MEM "/dev/mem" +# endif +# endif /* SVR4 */ + +/* Generic version */ +#include + +#ifndef DEV_MEM +#define DEV_MEM "/dev/mem" +#endif + +#ifdef CONFIG_DHAHELPER + +#include "kernelhelper/dhahelper.h" + +static int mem=-1; +void *map_phys_mem(unsigned long base, unsigned long size) +{ +#ifdef ARCH_ALPHA +/* TODO: move it into sysdep */ + base += bus_base(); +#endif + if ( (mem = open("/dev/dhahelper",O_RDWR)) < 0) + { + if ( (mem = open(DEV_MEM,O_RDWR)) == -1) { + perror("libdha: open(/dev/mem) failed") ; exit(1) ; + } + } + else + { + dhahelper_memory_t mem_req; + + mem_req.operation = MEMORY_OP_MAP; + mem_req.start = base; + mem_req.offset = 0; + mem_req.size = size; + + if (ioctl(mem, DHAHELPER_MEMORY, &mem_req) < 0) + { + perror("libdha: failed mapping throught kernel helper"); + return NULL; + } + } + return mmap(0,size,PROT_READ|PROT_WRITE,MAP_SHARED,mem,base) ; +} +#else + +static int mem=-1; +void *map_phys_mem(unsigned long base, unsigned long size) +{ +#ifdef ARCH_ALPHA +/* TODO: move it into sysdep */ + base += bus_base(); +#endif + if ( (mem = open(DEV_MEM,O_RDWR)) == -1) { + perror("libdha: open(/dev/mem) failed") ; exit(1) ; + } + return mmap(0,size,PROT_READ|PROT_WRITE,MAP_SHARED,mem,base) ; +} +#endif /* CONFIG_DHAHELPER */ + +void unmap_phys_mem(void *ptr, unsigned long size) +{ + int res=munmap(ptr,size) ; + if (res == -1) { perror("libdha: munmap() failed") ; exit(1) ; } + close(mem); +} +#endif + +unsigned char INPORT8(unsigned idx) +{ + return inb(idx); +} + +unsigned short INPORT16(unsigned idx) +{ + return inw(idx); +} + +unsigned INPORT32(unsigned idx) +{ + return inl(idx); +} + +void OUTPORT8(unsigned idx,unsigned char val) +{ + outb(idx,val); +} + +void OUTPORT16(unsigned idx,unsigned short val) +{ + outw(idx,val); +} + +void OUTPORT32(unsigned idx,unsigned val) +{ + outl(idx,val); +} + diff --git a/src/video_out/libdha/libdha.h b/src/video_out/libdha/libdha.h new file mode 100644 index 000000000..bc319a39f --- /dev/null +++ b/src/video_out/libdha/libdha.h @@ -0,0 +1,96 @@ +/* + libgha.h - Library for direct hardware access + Copyrights: + 1996/10/27 - Robin Cutshaw (robin@xfree86.org) + XFree86 3.3.3 implementation + 1999 - Øyvind Aabling. + Modified for GATOS/win/gfxdump. + 2002 - library implementation by Nick Kurshev + + supported O/S's: SVR4, UnixWare, SCO, Solaris, + FreeBSD, NetBSD, 386BSD, BSDI BSD/386, + Linux, Mach/386, ISC + DOS (WATCOM 9.5 compiler), Win9x (with mapdev.vxd) + Licence: GPL +*/ +#ifndef LIBDHA_H +#define LIBDHA_H + +#ifdef __cplusplus +extern "C" { +#endif + +#define MAX_DEV_PER_VENDOR_CFG1 64 +#define MAX_PCI_DEVICES_PER_BUS 32 +#define MAX_PCI_DEVICES 64 +#define PCI_MULTIFUNC_DEV 0x80 + +typedef struct pciinfo_s +{ + int bus,card,func; /* PCI/AGP bus:card:func */ + unsigned short vendor,device; /* Card vendor+device ID */ + unsigned base0,base1,base2,baserom; /* Memory and I/O base addresses */ +// unsigned base0_limit, base1_limit, base2_limit, baserom_limit; +}pciinfo_t; + +/* needed for mga_vid */ +extern int pci_config_read(unsigned char bus, unsigned char dev, unsigned char func, + unsigned char cmd, int len, unsigned long *val); + /* Fill array pci_list which must have size MAX_PCI_DEVICES + and return 0 if sucessful */ +extern int pci_scan(pciinfo_t *pci_list,unsigned *num_card); + + + /* Enables/disables accessing to IO space from application side. + Should return 0 if o'k or errno on error. */ +extern int enable_app_io( void ); +extern int disable_app_io( void ); + +extern unsigned char INPORT8(unsigned idx); +extern unsigned short INPORT16(unsigned idx); +extern unsigned INPORT32(unsigned idx); +#define INPORT(idx) INPORT32(idx) +extern void OUTPORT8(unsigned idx,unsigned char val); +extern void OUTPORT16(unsigned idx,unsigned short val); +extern void OUTPORT32(unsigned idx,unsigned val); +#define OUTPORT(idx,val) OUTPORT32(idx,val) + +extern void * map_phys_mem(unsigned long base, unsigned long size); +extern void unmap_phys_mem(void *ptr, unsigned long size); + +/* These are the region types */ +#define MTRR_TYPE_UNCACHABLE 0 +#define MTRR_TYPE_WRCOMB 1 +#define MTRR_TYPE_WRTHROUGH 4 +#define MTRR_TYPE_WRPROT 5 +#define MTRR_TYPE_WRBACK 6 +extern int mtrr_set_type(unsigned base,unsigned size,int type); + +/* Busmastering support */ + /* returns 0 if support exists else errno */ +extern int bm_open( void ); +extern void bm_close( void ); + /* Converts virtual memory addresses into physical + returns 0 if OK else - errno + parray should have enough length to accept length/page_size + elements. virt_addr can be located in non-continious memory + block and can be allocated by malloc(). (kmalloc() is not + needed). Note: if you have some very old card which requires + continous memory block then you need to implement bm_kmalloc + bm_kfree functions here. NOTE2: to be sure that every page of + region is present in physical memory (is not swapped out) use + m(un)lock functions. Note3: Probably your card will want to + have page-aligned block for DMA transfer so use + memalign(PAGE_SIZE,mem_size) function to alloc such memory. */ +extern int bm_virt_to_phys( void * virt_addr, unsigned long length, + unsigned long * parray ); + /* Converts virtual memory addresses into bus address + Works in the same way as bm_virt_to_phys. */ +extern int bm_virt_to_bus( void * virt_addr, unsigned long length, + unsigned long * barray ); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/src/video_out/libdha/mmi.c b/src/video_out/libdha/mmi.c new file mode 100644 index 000000000..68d3429f2 --- /dev/null +++ b/src/video_out/libdha/mmi.c @@ -0,0 +1,57 @@ +/* Memory manager interface */ +#include +#include +#include +#include +#include +#include "libdha.h" +#include "kernelhelper/dhahelper.h" + +static int libdha_fd=-1; + +#define ALLOWED_VER 2 +int bm_open( void ) +{ + int retv; + libdha_fd = open("/dev/dhahelper",O_RDWR); + retv = libdha_fd > 0 ? 0 : ENXIO; + if(!retv) + { + int ver; + ioctl(libdha_fd,DHAHELPER_GET_VERSION,&ver); + if(ver < ALLOWED_VER) + { + printf("libdha: You have wrong version (%i) of /dev/dhahelper\n" + "libdha: Please upgrade your driver up to ver=%i\n",ver,ALLOWED_VER); + retv = EINVAL; + close(libdha_fd); + } + } + else printf("libdha: Can't open /dev/dhahelper\n"); + return retv; +} + +void bm_close( void ) +{ + close(libdha_fd); +} + +int bm_virt_to_phys( void * virt_addr, unsigned long length, unsigned long * parray ) +{ + dhahelper_vmi_t vmi; + vmi.virtaddr = virt_addr; + vmi.length = length; + vmi.realaddr = parray; + if(libdha_fd > 0) return ioctl(libdha_fd,DHAHELPER_VIRT_TO_PHYS,&vmi); + return ENXIO; +} + +int bm_virt_to_bus( void * virt_addr, unsigned long length, unsigned long * barray ) +{ + dhahelper_vmi_t vmi; + vmi.virtaddr = virt_addr; + vmi.length = length; + vmi.realaddr = barray; + if(libdha_fd > 0) return ioctl(libdha_fd,DHAHELPER_VIRT_TO_BUS,&vmi); + return ENXIO; +} diff --git a/src/video_out/libdha/mtrr.c b/src/video_out/libdha/mtrr.c new file mode 100644 index 000000000..6ef5c44f5 --- /dev/null +++ b/src/video_out/libdha/mtrr.c @@ -0,0 +1,85 @@ +/* + mtrr.c - Stuff for optimizing memory access + Copyrights: + 2002 - Linux version by Nick Kurshev + Licence: GPL +*/ +#ifdef HAVE_CONFIG_H +#include "config.h" +#endif + +#include +#include +#include "libdha.h" +#include "AsmMacros.h" + +#if defined (__i386__) && defined (__NetBSD__) +#include +#if __NetBSD_Version__ > 105240000 +#include +#include +#include +#include +#endif +#endif + +#if defined( __i386__ ) +int mtrr_set_type(unsigned base,unsigned size,int type) +{ +#ifdef linux + FILE * mtrr_fd; + char * stype; + switch(type) + { + case MTRR_TYPE_UNCACHABLE: stype = "uncachable"; break; + case MTRR_TYPE_WRCOMB: stype = "write-combining"; break; + case MTRR_TYPE_WRTHROUGH: stype = "write-through"; break; + case MTRR_TYPE_WRPROT: stype = "write-protect"; break; + case MTRR_TYPE_WRBACK: stype = "write-back"; break; + default: return EINVAL; + } + mtrr_fd = fopen("/proc/mtrr","wt"); + if(mtrr_fd) + { + char sout[256]; + unsigned wr_len; + sprintf(sout,"base=0x%08X size=0x%08X type=%s\n",base,size,stype); + wr_len = fprintf(mtrr_fd,sout); + /*printf("MTRR: %s\n",sout);*/ + fclose(mtrr_fd); + return wr_len == strlen(sout) ? 0 : EPERM; + } + return ENOSYS; +#elif defined (__NetBSD__) +#if __NetBSD_Version__ > 105240000 + struct mtrr *mtrrp; + int n; + + mtrrp = malloc(sizeof (struct mtrr)); + mtrrp->base = base; + mtrrp->len = size; + mtrrp->type = type; + mtrrp->flags = MTRR_VALID | MTRR_PRIVATE; + n = 1; + + if (i386_set_mtrr(mtrrp, &n) < 0) { + free(mtrrp); + return errno; + } + free(mtrrp); + return 0; +#else + /* NetBSD prior to 1.5Y doesn't have MTRR support */ + return ENOSYS; +#endif +#else +#warning Please port MTRR stuff!!! + return ENOSYS; +#endif +} +#else +int mtrr_set_type(unsigned base,unsigned size,int type) +{ + return ENOSYS; +} +#endif diff --git a/src/video_out/libdha/oth/Makefile.am b/src/video_out/libdha/oth/Makefile.am new file mode 100644 index 000000000..9d9956b41 --- /dev/null +++ b/src/video_out/libdha/oth/Makefile.am @@ -0,0 +1,12 @@ +EXTRA_DIST = pci.db + +debug: +install-debug: + +mostlyclean-generic: + -rm -f *~ \#* .*~ .\#* + +maintainer-clean-generic: + -@echo "This command is intended for maintainers to use;" + -@echo "it deletes files that may require special tools to rebuild." + -rm -f Makefile.in diff --git a/src/video_out/libdha/oth/pci.db b/src/video_out/libdha/oth/pci.db new file mode 100644 index 000000000..bf892c5fb --- /dev/null +++ b/src/video_out/libdha/oth/pci.db @@ -0,0 +1,6074 @@ +v 0000 Gammagraphx, Inc. 0 +v 001a Ascend Communications, Inc. 0 +v 0033 Paradyne corp. 0 +v 003d Lockheed Martin-Marietta Corp 0 +v 0070 Hauppauge computer works Inc. 0 +v 0100 Ncipher Corp Ltd 0 +v 0675 Dynalink 0 +d 06751700 IS64PH ISDN Adapter 0 +d 06751702 IS64PH ISDN Adapter 0 +v 0925 VIA Technologies, Inc. 1 Wrong ID used in subsystem ID of VIA USB controllers. +v 0a89 BREA Technologies Inc 0 +v 0e11 Compaq Computer Corporation 0 +d 0e110001 PCI to EISA Bridge 0 +d 0e110002 PCI to ISA Bridge 0 +d 0e110049 NC7132 Gigabit Upgrade Module 0 +d 0e110049 1 NIC does not have this ven/dev id - it is a subven/devid +d 0e11004a NC6136 Gigabit Server Adapter 0 +d 0e11004a 1 NIC does not have this ven/dev id - it is a subven/devid +d 0e110508 Netelligent 4/16 Token Ring 0 +d 0e111000 Triflex/Pentium Bridge, Model 1000 0 +d 0e112000 Triflex/Pentium Bridge, Model 2000 0 +d 0e113032 QVision 1280/p 0 +d 0e113033 QVision 1280/p 0 +d 0e113034 QVision 1280/p 0 +d 0e114000 4000 [Triflex] 0 +d 0e116010 HotPlug PCI Bridge 6010 0 +d 0e117020 USB Controller 0 +d 0e11a0ec Fibre Channel Host Controller 0 +d 0e11a0f0 Advanced System Management Controller 0 +d 0e11a0f3 Triflex PCI to ISA Bridge 0 +d 0e11a0f7 PCI Hotplug Controller 0 +s 0e11a0f78086002a PCI Hotplug Controller A 0 +s 0e11a0f78086002b PCI Hotplug Controller B 0 +d 0e11a0f8 ZFMicro Chipset OHCI USB 0 +d 0e11a0fc Fibre Channel Host Controller 0 +d 0e11ae10 Smart-2/P RAID Controller 0 +s 0e11ae100e114030 Smart-2/P Array Controller 0 +s 0e11ae100e114031 Smart-2SL Array Controller 0 +s 0e11ae100e114032 Smart Array Controller 0 +s 0e11ae100e114033 Smart 3100ES Array Controller 0 +d 0e11ae29 MIS-L 0 +d 0e11ae2a MPC 0 +d 0e11ae2b MIS-E 0 +d 0e11ae31 System Management Controller 0 +d 0e11ae32 Netelligent 10/100 0 +d 0e11ae33 Triflex Dual EIDE Controller 0 +d 0e11ae34 Netelligent 10 0 +d 0e11ae35 Integrated NetFlex-3/P 0 +d 0e11ae40 Netelligent 10/100 Dual 0 +d 0e11ae43 ProLiant Integrated Netelligent 10/100 0 +d 0e11ae69 CETUS-L 0 +d 0e11ae6c Northstar 0 +d 0e11ae6d NorthStar CPU to PCI Bridge 0 +d 0e11b011 Integrated Netelligent 10/100 0 +d 0e11b012 Netelligent 10 T/2 0 +d 0e11b01e NC3120 Fast Ethernet NIC 0 +d 0e11b01e 1 NIC does not have this ven/dev id - it is a subven/devid +d 0e11b01f NC3122 Fast Ethernet NIC 0 +d 0e11b01f 1 NIC does not have this ven/dev id - it is a subven/devid +d 0e11b02f NC1120 Ethernet NIC 0 +d 0e11b030 Netelligent WS 5100 0 +d 0e11b04a 10/100 TX PCI Intel WOL UTP Controller 0 +d 0e11b04a 1 NIC does not have this ven/dev id - it is a subven/devid +d 0e11b060 Smart Array 5300 Controller 0 +d 0e11b0c6 NC3161 Fast Ethernet NIC 0 +d 0e11b0c6 1 NIC does not have this ven/dev id - it is a subven/devid +d 0e11b0c7 NC3160 Fast Ethernet NIC 0 +d 0e11b0c7 1 NIC does not have this ven/dev id - it is a subven/devid +d 0e11b0d7 NC3121 Fast Ethernet NIC 0 +d 0e11b0d7 1 NIC does not have this ven/dev id - it is a subven/devid +d 0e11b0dd NC3131 Fast Ethernet NIC 0 +d 0e11b0dd 1 NIC does not have this ven/dev id - it is a subven/devid +d 0e11b0de NC3132 Fast Ethernet Module 0 +d 0e11b0de 1 NIC does not have this ven/dev id - it is a subven/devid +d 0e11b0df NC6132 Gigabit Module 0 +d 0e11b0df 1 NIC does not have this ven/dev id - it is a subven/devid +d 0e11b0e0 NC6133 Gigabit Module 0 +d 0e11b0e0 1 NIC does not have this ven/dev id - it is a subven/devid +d 0e11b0e1 NC3133 Fast Ethernet Module 0 +d 0e11b0e1 1 NIC does not have this ven/dev id - it is a subven/devid +d 0e11b123 NC6134 Gigabit NIC 0 +d 0e11b123 1 NIC does not have this ven/dev id - it is a subven/devid +d 0e11b134 NC3163 Fast Ethernet NIC 0 +d 0e11b134 1 NIC does not have this ven/dev id - it is a subven/devid +d 0e11b13c NC3162 Fast Ethernet NIC 0 +d 0e11b13c 1 NIC does not have this ven/dev id - it is a subven/devid +d 0e11b144 NC3123 Fast Ethernet NIC 0 +d 0e11b144 1 NIC does not have this ven/dev id - it is a subven/devid +d 0e11b163 NC3134 Fast Ethernet NIC 0 +d 0e11b163 1 NIC does not have this ven/dev id - it is a subven/devid +d 0e11b164 NC3135 Fast Ethernet Upgrade Module 0 +d 0e11b164 1 NIC does not have this ven/dev id - it is a subven/devid +d 0e11b178 Smart Array 5i/532 0 +d 0e11b1a4 NC7131 Gigabit Server Adapter 0 +d 0e11b1a4 1 NIC does not have this ven/dev id - it is a subven/devid +d 0e11f130 NetFlex-3/P ThunderLAN 1.0 0 +d 0e11f150 NetFlex-3/P ThunderLAN 2.3 0 +v 1000 LSI Logic / Symbios Logic (formerly NCR) 0 +d 10000001 53c810 0 +s 1000000110001000 8100S 0 +d 10000002 53c820 0 +d 10000003 53c825 0 +d 10000004 53c815 0 +d 10000005 53c810AP 0 +d 10000006 53c860 0 +d 1000000a 53c1510 0 +d 1000000b 53c896 0 +d 1000000c 53c895 0 +d 1000000d 53c885 0 +d 1000000f 53c875 0 +s 1000000f0e117004 Embedded Ultra Wide SCSI Controller 0 +s 1000000f10928760 FirePort 40 Dual SCSI Controller 0 +s 1000000f1de13904 DC390F Ultra Wide SCSI Controller 0 +d 10000012 53c895a 0 +d 10000020 53c1010 Ultra3 SCSI Adapter 0 +d 10000021 53c1010 66MHz Ultra3 SCSI Adapter 0 +d 10000030 53c1030 0 +d 10000040 53c1035 0 +d 1000008f 53c875J 0 +s 1000008f10928000 FirePort 40 SCSI Controller 0 +s 1000008f10928760 FirePort 40 Dual SCSI Host Adapter 0 +d 10000621 FC909 0 +d 10000622 FC929 0 +d 10000623 FC929 LAN 0 +d 10000624 FC919 0 +d 10000625 FC919 LAN 0 +d 10000701 83C885 NT50 DigitalScape Fast Ethernet 0 +d 10000702 Yellowfin G-NIC gigabit ethernet 0 +s 1000070213180000 PEI100X 0 +d 10000901 61C102 0 +d 10001000 63C815 0 +v 1001 Initio 0 +d 10010010 PCI 1616 Measurement card with 32 digital I/O lines 0 +d 10010011 OPTO-PCI Opto-Isolated digital I/O board 0 +d 10010012 PCI-AD/DA Analogue I/O board 0 +d 10010013 PCI-OPTO-RELAIS Digital I/O board with relay outputs 0 +d 10010014 PCI-Counter/Timer Counter Timer board 0 +d 10010015 PCI-DAC416 Analogue output board 0 +d 10010016 PCI-MFB Analogue I/O board 0 +d 10010017 PROTO-3 PCI Prototyping board 0 +d 10019100 INI-9100/9100W SCSI Host 0 +v 1002 ATI Technologies Inc 0 +d 10024158 68800AX [Mach32] 0 +d 10024242 Radeon 8500 DV 0 +s 10024242100202aa Radeon 8500 AIW DV Edition 0 +d 10024354 215CT [Mach64 CT] 0 +d 10024358 210888CX [Mach64 CX] 0 +d 10024554 210888ET [Mach64 ET] 0 +d 10024654 Mach64 VT 0 +d 10024742 3D Rage Pro AGP 1X/2X 0 +s 1002474210020040 Rage Pro Turbo AGP 2X 0 +s 1002474210020044 Rage Pro Turbo AGP 2X 0 +s 1002474210020061 Rage Pro AIW AGP 2X 0 +s 1002474210020062 Rage Pro AIW AGP 2X 0 +s 1002474210020063 Rage Pro AIW AGP 2X 0 +s 1002474210020080 Rage Pro Turbo AGP 2X 0 +s 1002474210020084 Rage Pro Turbo AGP 2X 0 +s 1002474210024742 Rage Pro Turbo AGP 2X 0 +s 1002474210028001 Rage Pro Turbo AGP 2X 0 +s 1002474210280082 Rage Pro Turbo AGP 2X 0 +s 1002474210284082 Optiplex GX1 Onboard Display Adapter 0 +s 1002474210288082 Rage Pro Turbo AGP 2X 0 +s 100247421028c082 Rage Pro Turbo AGP 2X 0 +s 1002474280864152 Xpert 98D AGP 2X 0 +s 100247428086464a Rage Pro Turbo AGP 2X 0 +d 10024744 3D Rage Pro AGP 1X 0 +s 1002474410024744 Rage Pro Turbo AGP 0 +d 10024747 3D Rage Pro 0 +d 10024749 3D Rage Pro 0 +s 1002474910020061 Rage Pro AIW 0 +s 1002474910020062 Rage Pro AIW 0 +d 1002474c Rage XC 0 +d 1002474d Rage XL AGP 2X 0 +s 1002474d10020004 Xpert 98 RXL AGP 2X 0 +s 1002474d10020008 Xpert 98 RXL AGP 2X 0 +s 1002474d10020080 Rage XL AGP 2X 0 +s 1002474d10020084 Xpert 98 AGP 2X 0 +s 1002474d1002474d Rage XL AGP 0 +s 1002474d1033806a Rage XL AGP 0 +d 1002474e Rage XC AGP 0 +s 1002474e1002474e Rage XC AGP 0 +d 1002474f Rage XL 0 +s 1002474f10020008 Rage XL 0 +s 1002474f1002474f Rage XL 0 +d 10024750 3D Rage Pro 215GP 0 +s 1002475010020040 Rage Pro Turbo 0 +s 1002475010020044 Rage Pro Turbo 0 +s 1002475010020080 Rage Pro Turbo 0 +s 1002475010020084 Rage Pro Turbo 0 +s 1002475010024750 Rage Pro Turbo 0 +d 10024751 3D Rage Pro 215GQ 0 +d 10024752 Rage XL 0 +s 1002475210020008 Rage XL 0 +s 1002475210024752 Rage XL 0 +d 10024753 Rage XC 0 +s 1002475310024753 Rage XC 0 +d 10024754 3D Rage I/II 215GT [Mach64 GT] 0 +d 10024755 3D Rage II+ 215GTB [Mach64 GTB] 0 +d 10024756 3D Rage IIC 215IIC [Mach64 GT IIC] 0 +s 1002475610024756 Rage IIC 0 +d 10024757 3D Rage IIC AGP 0 +s 1002475710024757 Rage IIC AGP 0 +s 1002475710280089 Rage 3D IIC 0 +s 1002475710284082 Rage 3D IIC 0 +s 1002475710288082 Rage 3D IIC 0 +s 100247571028c082 Rage 3D IIC 0 +d 10024758 210888GX [Mach64 GX] 0 +d 10024759 3D Rage IIC 0 +d 1002475a 3D Rage IIC AGP 0 +s 1002475a10020087 Rage 3D IIC 0 +s 1002475a1002475a Rage IIC AGP 0 +d 10024c42 3D Rage LT Pro AGP-133 0 +s 10024c420e11b0e8 Rage 3D LT Pro 0 +s 10024c420e11b10e 3D Rage LT Pro (Compaq Armada 1750) 0 +s 10024c4210020040 Rage LT Pro AGP 2X 0 +s 10024c4210020044 Rage LT Pro AGP 2X 0 +s 10024c4210024c42 Rage LT Pro AGP 2X 0 +s 10024c4210028001 Rage LT Pro AGP 2X 0 +s 10024c4210280085 Rage 3D LT Pro 0 +d 10024c44 3D Rage LT Pro AGP-66 0 +d 10024c45 Rage Mobility M3 AGP 0 +d 10024c46 Rage Mobility M3 AGP 2x 0 +d 10024c47 3D Rage LT-G 215LG 0 +d 10024c49 3D Rage LT Pro 0 +s 10024c4910020004 Rage LT Pro 0 +s 10024c4910020040 Rage LT Pro 0 +s 10024c4910020044 Rage LT Pro 0 +s 10024c4910024c49 Rage LT Pro 0 +d 10024c4d Rage Mobility P/M AGP 2x 0 +s 10024c4d10020084 Xpert 98 AGP 2X (Mobility) 0 +d 10024c4e Rage Mobility L AGP 2x 0 +d 10024c50 3D Rage LT Pro 0 +s 10024c5010024c50 Rage LT Pro 0 +d 10024c51 3D Rage LT Pro 0 +d 10024c52 Rage Mobility P/M 0 +d 10024c53 Rage Mobility L 0 +d 10024c54 264LT [Mach64 LT] 0 +d 10024c57 Radeon Mobility M6 LW 0 +d 10024c59 Radeon Mobility M6 LY 0 +d 10024c5a Radeon Mobility M6 LZ 0 +d 10024d46 Rage Mobility M4 AGP 0 +d 10024d4c Rage Mobility M4 AGP 0 +d 10025041 Rage 128 PA/PRO 0 +d 10025042 Rage 128 PB/PRO AGP 2x 0 +d 10025043 Rage 128 PC/PRO AGP 4x 0 +d 10025044 Rage 128 PD/PRO TMDS 0 +s 1002504410020028 Rage 128 AIW 0 +s 1002504410020029 Rage 128 AIW 0 +d 10025045 Rage 128 PE/PRO AGP 2x TMDS 0 +d 10025046 Rage 128 PF/PRO AGP 4x TMDS 0 +s 1002504610020004 Rage Fury Pro 0 +s 1002504610020008 Rage Fury Pro/Xpert 2000 Pro 0 +s 1002504610020014 Rage Fury Pro 0 +s 1002504610020018 Rage Fury Pro/Xpert 2000 Pro 0 +s 1002504610020028 Rage 128 Pro AIW AGP 0 +s 100250461002002a Rage 128 Pro AIW AGP 0 +s 1002504610020048 Rage Fury Pro 0 +s 1002504610022000 Rage Fury MAXX AGP 4x (TMDS) (VGA device) 0 +s 1002504610022001 Rage Fury MAXX AGP 4x (TMDS) (Extra device?!) 0 +d 10025047 Rage 128 PG/PRO 0 +d 10025048 Rage 128 PH/PRO AGP 2x 0 +d 10025049 Rage 128 PI/PRO AGP 4x 0 +d 1002504a Rage 128 PJ/PRO TMDS 0 +d 1002504b Rage 128 PK/PRO AGP 2x TMDS 0 +d 1002504c Rage 128 PL/PRO AGP 4x TMDS 0 +d 1002504d Rage 128 PM/PRO 0 +d 1002504e Rage 128 PN/PRO AGP 2x 0 +d 1002504f Rage 128 PO/PRO AGP 4x 0 +d 10025050 Rage 128 PP/PRO TMDS 0 +s 1002505010020008 Xpert 128 0 +d 10025051 Rage 128 PQ/PRO AGP 2x TMDS 0 +d 10025052 Rage 128 PR/PRO AGP 4x TMDS 0 +d 10025053 Rage 128 PS/PRO 0 +d 10025054 Rage 128 PT/PRO AGP 2x 0 +d 10025055 Rage 128 PU/PRO AGP 4x 0 +d 10025056 Rage 128 PV/PRO TMDS 0 +d 10025057 Rage 128 PW/PRO AGP 2x TMDS 0 +d 10025058 Rage 128 PX/PRO AGP 4x TMDS 0 +d 10025144 Radeon QD 0 +s 1002514410020008 Radeon 7000/Radeon VE 0 +s 1002514410020009 Radeon 7000/Radeon 0 +s 100251441002000a Radeon 7000/Radeon 0 +s 100251441002001a Radeon 7000/Radeon 0 +s 1002514410020029 Radeon AIW 0 +s 1002514410020038 Radeon 7000/Radeon 0 +s 1002514410020039 Radeon 7000/Radeon 0 +s 100251441002008a Radeon 7000/Radeon 0 +s 10025144100200ba Radeon 7000/Radeon 0 +s 1002514410020139 Radeon 7000/Radeon 0 +s 100251441002028a Radeon 7000/Radeon 0 +s 10025144100202aa Radeon AIW 0 +s 100251441002053a Radeon 7000/Radeon 0 +d 10025145 Radeon QE 0 +d 10025146 Radeon QF 0 +d 10025147 Radeon QG 0 +d 1002514c Radeon QL 0 +s 1002514c1002013a Radeon 8500 0 +d 10025157 Radeon QW 0 +s 100251571002013a Radeon 7500 0 +d 10025159 Radeon VE QY 0 +s 100251591002000a Radeon 7000/Radeon VE 0 +s 1002515910020038 Radeon 7000/Radeon VE 0 +s 100251591002003a Radeon 7000/Radeon VE 0 +s 10025159100200ba Radeon 7000/Radeon VE 0 +s 100251591002013a Radeon 7000/Radeon VE 0 +d 1002515a Radeon VE QZ 0 +d 10025245 Rage 128 RE/SG 0 +s 1002524510020008 Xpert 128 0 +s 1002524510020028 Rage 128 AIW 0 +s 1002524510020029 Rage 128 AIW 0 +s 1002524510020068 Rage 128 AIW 0 +d 10025246 Rage 128 RF/SG AGP 0 +s 1002524610020004 Magnum/Xpert 128/Xpert 99 0 +s 1002524610020008 Magnum/Xpert128/X99/Xpert2000 0 +s 1002524610020028 Rage 128 AIW AGP 0 +s 1002524610020044 Rage Fury/Xpert 128/Xpert 2000 0 +s 1002524610020068 Rage 128 AIW AGP 0 +s 1002524610020448 Rage Fury 0 +d 10025247 Rage 128 RG 0 +d 1002524b Rage 128 RK/VR 0 +d 1002524c Rage 128 RL/VR AGP 0 +s 1002524c10020008 Xpert 99/Xpert 2000 0 +s 1002524c10020088 Xpert 99 0 +d 10025345 Rage 128 SE/4x 0 +d 10025346 Rage 128 SF/4x AGP 2x 0 +d 10025347 Rage 128 SG/4x AGP 4x 0 +d 10025348 Rage 128 4x 0 +d 1002534b Rage 128 SK/4x 0 +d 1002534c Rage 128 SL/4x AGP 2x 0 +d 1002534d Rage 128 SM/4x AGP 4x 0 +s 1002534d10020008 Xpert 99/Xpert 2000 0 +s 1002534d10020018 Xpert 2000 0 +d 1002534e Rage 128 4x 0 +d 10025354 Mach 64 VT 0 +s 1002535410025654 Mach 64 reference 0 +d 10025446 Rage 128 Pro TF 0 +s 1002544610020004 Rage Fury Pro 0 +s 1002544610020008 Rage Fury Pro/Xpert 2000 Pro 0 +s 1002544610020018 Rage Fury Pro/Xpert 2000 Pro 0 +s 1002544610020028 Rage 128 AIW Pro AGP 0 +s 1002544610020029 Rage 128 AIW 0 +s 100254461002002a Rage 128 AIW Pro AGP 0 +s 100254461002002b Rage 128 AIW 0 +s 1002544610020048 Xpert 2000 Pro 0 +d 1002544c Rage 128 Pro TL 0 +d 10025452 Rage 128 Pro TR 0 +s 100254521002001c Rage 128 Pro 4XL 0 +s 10025452103c1279 Rage 128 Pro 4XL 0 +d 10025654 264VT [Mach64 VT] 0 +s 1002565410025654 Mach64VT Reference 0 +d 10025655 264VT3 [Mach64 VT3] 0 +d 10025656 264VT4 [Mach64 VT4] 0 +v 1003 ULSI Systems 0 +d 10030201 US201 0 +v 1004 VLSI Technology Inc 0 +d 10040005 82C592-FC1 0 +d 10040006 82C593-FC1 0 +d 10040007 82C594-AFC2 0 +d 10040008 82C596/7 [Wildcat] 0 +d 10040009 82C597-AFC2 0 +d 1004000c 82C541 [Lynx] 0 +d 1004000d 82C543 [Lynx] 0 +d 10040101 82C532 0 +d 10040102 82C534 [Eagle] 0 +d 10040103 82C538 0 +d 10040104 82C535 0 +d 10040105 82C147 0 +d 10040200 82C975 0 +d 10040280 82C925 0 +d 10040304 QSound ThunderBird PCI Audio 0 +s 1004030410040304 QSound ThunderBird PCI Audio 0 +s 10040304122d1206 DSP368 Audio 0 +s 1004030414835020 XWave Thunder 3D Audio 0 +d 10040305 QSound ThunderBird PCI Audio Gameport 0 +s 1004030510040305 QSound ThunderBird PCI Audio Gameport 0 +s 10040305122d1207 DSP368 Audio Gameport 0 +s 1004030514835021 XWave Thunder 3D Audio Gameport 0 +d 10040306 QSound ThunderBird PCI Audio Support Registers 0 +s 1004030610040306 QSound ThunderBird PCI Audio Support Registers 0 +s 10040306122d1208 DSP368 Audio Support Registers 0 +s 1004030614835022 XWave Thunder 3D Audio Support Registers 0 +d 10040702 VAS96011 [Golden Gate II] 0 +v 1005 Avance Logic Inc. [ALI] 0 +d 10052064 ALG2032/2064 0 +d 10052128 ALG2364A 0 +d 10052301 ALG2301 0 +d 10052302 ALG2302 0 +d 10052364 ALG2364 0 +d 10052464 ALG2364A 0 +d 10052501 ALG2564A/25128A 0 +v 1006 Reply Group 0 +v 1007 NetFrame Systems Inc 0 +v 1008 Epson 0 +v 100a Phoenix Technologies 0 +v 100b National Semiconductor Corporation 0 +v 100b 1 +d 100b0001 DP83810 0 +d 100b0002 87415/87560 IDE 0 +d 100b000e 87560 Legacy I/O 0 +d 100b000f OHCI Compliant FireWire Controller 0 +d 100b0011 NS87560 National PCI System I/O 0 +d 100b0012 USB Controller 0 +d 100b0020 DP83815 (MacPhyter) Ethernet Controller 0 +d 100b0022 DP83820 0 +d 100bd001 87410 IDE 0 +v 100c Tseng Labs Inc 0 +d 100c3202 ET4000/W32p rev A 0 +d 100c3205 ET4000/W32p rev B 0 +d 100c3206 ET4000/W32p rev C 0 +d 100c3207 ET4000/W32p rev D 0 +d 100c3208 ET6000 0 +d 100c4702 ET6300 0 +v 100d AST Research Inc 0 +v 100e Weitek 0 +d 100e9000 P9000 Viper 0 +d 100e9001 P9000 Viper 0 +d 100e9002 P9000 Viper 0 +d 100e9100 P9100 Viper Pro/SE 0 +v 1010 Video Logic, Ltd. 0 +v 1011 Digital Equipment Corporation 0 +d 10110001 DECchip 21050 0 +d 10110002 DECchip 21040 [Tulip] 0 +d 10110004 DECchip 21030 [TGA] 0 +d 10110007 NVRAM [Zephyr NVRAM] 0 +d 10110008 KZPSA [KZPSA] 0 +d 10110009 DECchip 21140 [FasterNet] 0 +s 1011000910b82001 SMC9332BDT EtherPower 10/100 0 +s 1011000910b82002 SMC9332BVT EtherPower T4 10/100 0 +s 1011000910b82003 SMC9334BDT EtherPower 10/100 (1-port) 0 +s 1011000911092400 ANA-6944A/TX Fast Ethernet 0 +s 1011000911122300 RNS2300 Fast Ethernet 0 +s 1011000911122320 RNS2320 Fast Ethernet 0 +s 1011000911122340 RNS2340 Fast Ethernet 0 +s 1011000911131207 EN-1207-TX Fast Ethernet 0 +s 1011000911861100 DFE-500TX Fast Ethernet 0 +s 1011000911861112 DFE-570TX Fast Ethernet 0 +s 1011000911861140 DFE-660 Cardbus Ethernet 10/100 0 +s 1011000911861142 DFE-660 Cardbus Ethernet 10/100 0 +s 1011000912829100 AEF-380TXD Fast Ethernet 0 +s 1011000913851100 FA310TX Fast Ethernet 0 +s 1011000926460001 KNE100TX Fast Ethernet 0 +d 1011000a 21230 Video Codec 0 +d 1011000d PBXGB [TGA2] 0 +d 1011000f DEFPA 0 +d 10110014 DECchip 21041 [Tulip Pass 3] 0 +s 1011001411860100 DE-530+ 0 +d 10110016 DGLPB [OPPO] 0 +d 10110019 DECchip 21142/43 0 +s 101100191011500b DE500 Fast Ethernet 0 +s 1011001910140001 10/100 EtherJet Cardbus 0 +s 1011001910250315 ALN315 Fast Ethernet 0 +s 10110019108d0016 Rapidfire 2327 10/100 Ethernet 0 +s 1011001910b82005 SMC8032DT Extreme Ethernet 10/100 0 +s 1011001910ef8169 Cardbus Fast Ethernet 0 +s 1011001911092a00 ANA-6911A/TX Fast Ethernet 0 +s 1011001911092b00 ANA-6911A/TXC Fast Ethernet 0 +s 1011001911093000 ANA-6922/TX Fast Ethernet 0 +s 1011001911131207 Cheetah Fast Ethernet 0 +s 1011001911132220 Cardbus Fast Ethernet 0 +s 10110019115d0002 Cardbus Ethernet 10/100 0 +s 1011001911790203 Fast Ethernet 0 +s 1011001911790204 Cardbus Fast Ethernet 0 +s 1011001911861100 DFE-500TX Fast Ethernet 0 +s 1011001911861101 DFE-500TX Fast Ethernet 0 +s 1011001911861102 DFE-500TX Fast Ethernet 0 +s 1011001912660004 Eagle Fast EtherMAX 0 +s 1011001912af0019 NetFlyer Cardbus Fast Ethernet 0 +s 1011001913740001 Cardbus Ethernet Card 10/100 0 +s 1011001913950001 10/100 Ethernet CardBus PC Card 0 +s 1011001980860001 EtherExpress PRO/100 Mobile CardBus 32 0 +d 10110021 DECchip 21052 0 +d 10110022 DECchip 21150 0 +d 10110023 DECchip 21150 0 +d 10110024 DECchip 21152 0 +d 10110025 DECchip 21153 0 +d 10110026 DECchip 21154 0 +d 10110045 DECchip 21553 0 +d 10110046 DECchip 21554 0 +s 10110046103c10c2 Hewlett-Packard NetRAID-4M 0 +s 1011004690050365 Adaptec 5400S 0 +s 1011004690051364 Dell PowerEdge RAID Controller 2 0 +s 1011004690051365 Dell PowerEdge RAID Controller 2 0 +d 10111065 StrongARM DC21285 0 +s 1011106510690020 DAC960P 0 +v 1012 Micronics Computers Inc 0 +v 1013 Cirrus Logic 0 +d 10130038 GD 7548 0 +d 10130040 GD 7555 Flat Panel GUI Accelerator 0 +d 1013004c GD 7556 Video/Graphics LCD/CRT Ctrlr 0 +d 101300a0 GD 5430/40 [Alpine] 0 +d 101300a2 GD 5432 [Alpine] 0 +d 101300a4 GD 5434-4 [Alpine] 0 +d 101300a8 GD 5434-8 [Alpine] 0 +d 101300ac GD 5436 [Alpine] 0 +d 101300b0 GD 5440 0 +d 101300b8 GD 5446 0 +d 101300bc GD 5480 0 +s 101300bc101300bc CL-GD5480 0 +d 101300d0 GD 5462 0 +d 101300d2 GD 5462 [Laguna I] 0 +d 101300d4 GD 5464 [Laguna] 0 +d 101300d6 GD 5465 [Laguna] 0 +d 101300e8 GD 5436U 0 +d 10131100 CL 6729 0 +d 10131110 PD 6832 PCMCIA/CardBus Ctrlr 0 +d 10131112 PD 6834 PCMCIA/CardBus Ctrlr 0 +d 10131113 PD 6833 PCMCIA/CardBus Ctrlr 0 +d 10131200 GD 7542 [Nordic] 0 +d 10131202 GD 7543 [Viking] 0 +d 10131204 GD 7541 [Nordic Light] 0 +d 10134400 CD 4400 0 +d 10136001 CS 4610/11 [CrystalClear SoundFusion Audio Accelerator] 0 +s 1013600110141010 CS4610 SoundFusion Audio Accelerator 0 +d 10136003 CS 4614/22/24 [CrystalClear SoundFusion Audio Accelerator] 0 +s 1013600310134280 Crystal SoundFusion PCI Audio Accelerator 0 +s 1013600316810050 Hercules Game Theater XP 0 +d 10136005 Crystal CS4281 PCI Audio 0 +s 1013600510134281 Crystal CS4281 PCI Audio 0 +s 1013600510cf10a8 Crystal CS4281 PCI Audio 0 +s 1013600510cf10a9 Crystal CS4281 PCI Audio 0 +s 1013600510cf10aa Crystal CS4281 PCI Audio 0 +s 1013600510cf10ab Crystal CS4281 PCI Audio 0 +s 1013600510cf10ac Crystal CS4281 PCI Audio 0 +s 1013600510cf10ad Crystal CS4281 PCI Audio 0 +s 1013600510cf10b4 Crystal CS4281 PCI Audio 0 +s 1013600511790001 Crystal CS4281 PCI Audio 0 +s 1013600514c0000c Crystal CS4281 PCI Audio 0 +v 1014 IBM 0 +d 10140002 PCI to MCA Bridge 0 +d 10140005 Alta Lite 0 +d 10140007 Alta MP 0 +d 1014000a Fire Coral 0 +d 10140017 CPU to PCI Bridge 0 +d 10140018 TR Auto LANstreamer 0 +d 1014001b GXT-150P 0 +d 1014001c Carrera 0 +d 1014001d 82G2675 0 +d 10140020 MCA 0 +d 10140022 IBM27-82351 0 +d 1014002d Python 0 +d 1014002e ServeRAID-3x 0 +d 10140036 Miami 0 +d 1014003a CPU to PCI Bridge 0 +d 1014003e 16/4 Token ring UTP/STP controller 0 +s 1014003e1014003e Token-Ring Adapter 0 +s 1014003e101400cd Token-Ring Adapter + Wake-On-LAN 0 +s 1014003e101400ce 16/4 Token-Ring Adapter 2 0 +s 1014003e101400cf 16/4 Token-Ring Adapter Special 0 +s 1014003e101400e4 High-Speed 100/16/4 Token-Ring Adapter 0 +s 1014003e101400e5 16/4 Token-Ring Adapter 2 + Wake-On-LAN 0 +s 1014003e1014016d iSeries 2744 Card 0 +d 10140045 SSA Adapter 0 +d 10140046 MPIC interrupt controller 0 +d 10140047 PCI to PCI Bridge 0 +d 10140048 PCI to PCI Bridge 0 +d 10140049 Warhead SCSI Controller 0 +d 1014004e ATM Controller (14104e00) 0 +d 1014004f ATM Controller (14104f00) 0 +d 10140050 ATM Controller (14105000) 0 +d 10140053 25 MBit ATM Controller 0 +d 10140057 MPEG PCI Bridge 0 +d 1014005c i82557B 10/100 0 +d 1014007c ATM Controller (14107c00) 0 +d 1014007d 3780IDSP [MWave] 0 +d 10140090 GXT 3000P 0 +s 101400901014008e GXT-3000P 0 +d 10140095 20H2999 PCI Docking Bridge 0 +d 10140096 Chukar chipset SCSI controller 0 +s 1014009610140097 iSeries 2778 DASD IOA 0 +s 1014009610140098 iSeries 2763 DASD IOA 0 +s 1014009610140099 iSeries 2748 DASD IOA 0 +d 101400a5 ATM Controller (1410a500) 0 +d 101400a6 ATM 155MBPS MM Controller (1410a600) 0 +d 101400b7 256-bit Graphics Rasterizer [Fire GL1] 0 +s 101400b7190200b8 Fire GL1 0 +d 101400be ATM 622MBPS Controller (1410be00) 0 +d 10140142 Yotta Video Compositor Input 0 +s 1014014210140143 Yotta Input Controller (ytin) 0 +d 10140144 Yotta Video Compositor Output 0 +s 1014014410140145 Yotta Output Controller (ytout) 0 +d 10140156 405GP PLB to PCI Bridge 0 +d 101401a7 PCI-X to PCI-X Bridge 0 +d 101401bd Netfinity ServeRAID controller 0 +d 101401be ServeRAID-4M 0 +d 101401bf ServeRAID-4L 0 +d 1014022e ServeRAID-4H 0 +d 1014ffff MPIC-2 interrupt controller 0 +v 1015 LSI Logic Corp of Canada 0 +v 1016 ICL Personal Systems 0 +v 1017 SPEA Software AG 0 +d 10175343 SPEA 3D Accelerator 0 +v 1018 Unisys Systems 0 +v 1019 Elitegroup Computer Systems 0 +v 101a AT&T GIS (NCR) 0 +d 101a0005 100VG ethernet 0 +v 101b Vitesse Semiconductor 0 +v 101c Western Digital 0 +d 101c0193 33C193A 0 +d 101c0196 33C196A 0 +d 101c0197 33C197A 0 +d 101c0296 33C296A 0 +d 101c3193 7193 0 +d 101c3197 7197 0 +d 101c3296 33C296A 0 +d 101c4296 34C296 0 +d 101c9710 Pipeline 9710 0 +d 101c9712 Pipeline 9712 0 +d 101cc24a 90C 0 +v 101e American Megatrends Inc. 0 +d 101e1960 MegaRAID 0 +s 101e1960101e0471 MegaRAID 471 Enterprise 1600 RAID Controller 0 +s 101e1960101e0475 MegaRAID 475 Express 500 RAID Controller 0 +s 101e1960101e0493 MegaRAID 493 Elite 1600 RAID Controller 0 +s 101e196010280471 PowerEdge RAID Controller 3/QC 0 +s 101e196010280493 PowerEdge RAID Controller 3/DC 0 +d 101e9010 MegaRAID 428 Ultra RAID Controller 0 +d 101e9030 EIDE Controller 0 +d 101e9031 EIDE Controller 0 +d 101e9032 EIDE & SCSI Controller 0 +d 101e9033 SCSI Controller 0 +d 101e9040 Multimedia card 0 +d 101e9060 MegaRAID 434 Ultra GT RAID Controller 0 +v 101f PictureTel 0 +v 1020 Hitachi Computer Products 0 +v 1021 OKI Electric Industry Co. Ltd. 0 +v 1022 Advanced Micro Devices [AMD] 0 +d 10222000 79c970 [PCnet LANCE] 0 +s 10222000103c104c Ethernet with LAN remote power Adapter 0 +s 10222000103c1064 Ethernet with LAN remote power Adapter 0 +s 10222000103c1065 Ethernet with LAN remote power Adapter 0 +s 10222000103c106c Ethernet with LAN remote power Adapter 0 +s 10222000103c106e Ethernet with LAN remote power Adapter 0 +s 10222000103c10ea Ethernet with LAN remote power Adapter 0 +s 1022200011131220 EN1220 10/100 Fast Ethernet 0 +s 1022200012592450 AT-2450 10/100 Fast Ethernet 0 +s 1022200012592454 AT-2450v4 10Mb Ethernet Adapter 1 +s 1022200012592700 AT-2700TX 10/100 Fast Ethernet 0 +s 1022200012592701 AT-2700FX 100Mb Ethernet 0 +d 10222001 79c978 [HomePNA] 0 +s 1022200110920a78 Multimedia Home Network Adapter 1 +s 1022200116680299 ActionLink Home Network Adapter 1 +d 10222020 53c974 [PCscsi] 0 +d 10222040 79c974 0 +d 10227006 AMD-751 [Irongate] System Controller 0 +d 10227007 AMD-751 [Irongate] AGP Bridge 0 +d 1022700c AMD-762 [AMD-760MP] System Controller 0 +d 1022700d AMD-760 [AMD-760MP] AGP Bridge 0 +d 1022700d AMD-762 [AMD-760MP] AGP Bridge 1 700c & 700d are on the same chip: the north bridge for the AMD-760MP chipset +d 1022700e AMD-760 [Irongate] System Controller 0 +d 1022700f AMD-760 [Irongate] AGP Bridge 0 +d 10227400 AMD-755 [Cobra] ISA 0 +d 10227401 AMD-755 [Cobra] IDE 0 +d 10227403 AMD-755 [Cobra] ACPI 0 +d 10227404 AMD-755 [Cobra] USB 0 +d 10227408 AMD-756 [Viper] ISA 0 +d 10227409 AMD-756 [Viper] IDE 0 +d 1022740b AMD-756 [Viper] ACPI 0 +d 1022740c AMD-756 [Viper] USB 0 +d 10227410 AMD-765 [Viper] ISA 0 +d 10227410 AMD-766 [ViperPlus] ISA 1 +d 10227410 AMD-766 [ViperPlus] ISA 1 The AMD765 chip never went into mass production, the 766 chip taking its place instead. Both were codenamed ViperPlus. +d 10227411 AMD-765 [Viper] IDE 0 +d 10227411 AMD-766 [ViperPlus] IDE 1 +d 10227413 AMD-765 [Viper] ACPI 0 +d 10227413 AMD-766 [ViperPlus] ACPI 1 +d 10227414 AMD-765 [Viper] USB 0 +d 10227414 AMD-766 [ViperPlus] USB 1 +d 10227440 AMD-768 [??] ISA 0 +d 10227440 AMD-768 [Opus] ISA 1 +d 10227441 AMD-768 [??] IDE 0 +d 10227441 AMD-768 [Opus] IDE 1 +d 10227443 AMD-768 [??] ACPI 0 +d 10227443 AMD-768 [Opus] ACPI 1 +d 10227448 AMD-768 [??] PCI 0 +d 10227448 AMD-768 [Opus] PCI 1 +d 10227449 AMD-768 [??] USB 0 +d 10227449 AMD-768 [Opus] USB 1 +v 1023 Trident Microsystems 0 +d 10230194 82C194 0 +d 10232000 4DWave DX 0 +d 10232001 4DWave NX 0 +d 10238400 CyberBlade/i7 0 +s 1023840010238400 CyberBlade i7 AGP 0 +d 10238420 CyberBlade/i7d 0 +s 102384200e11b15a CyberBlade i7 AGP 0 +d 10238500 CyberBlade/i1 0 +d 10238520 CyberBlade i1 0 +s 102385200e11b16e CyberBlade i1 AGP 0 +s 1023852010238520 CyberBlade i1 AGP 0 +d 10238820 CyberBlade XPAi1 0 +d 10239320 TGUI 9320 0 +d 10239350 GUI Accelerator 0 +d 10239360 Flat panel GUI Accelerator 0 +d 10239382 Cyber 9382 [Reference design] 0 +d 10239383 Cyber 9383 [Reference design] 0 +d 10239385 Cyber 9385 [Reference design] 0 +d 10239386 Cyber 9386 0 +d 10239388 Cyber 9388 0 +d 10239397 Cyber 9397 0 +d 1023939a Cyber 9397DVD 0 +d 10239420 TGUI 9420 0 +d 10239430 TGUI 9430 0 +d 10239440 TGUI 9440 0 +d 10239460 TGUI 9460 0 +d 10239470 TGUI 9470 0 +d 10239520 Cyber 9520 0 +d 10239525 Cyber 9525 0 +d 10239540 Cyber 9540 0 +d 10239660 TGUI 9660/968x/968x 0 +d 10239680 TGUI 9680 0 +d 10239682 TGUI 9682 0 +d 10239683 TGUI 9683 0 +d 10239685 ProVIDIA 9685 0 +d 10239750 3DImage 9750 0 +s 1023975010149750 3DImage 9750 0 +s 1023975010239750 3DImage 9750 0 +d 10239753 TGUI 9753 0 +d 10239754 TGUI 9754 0 +d 10239759 TGUI 975 0 +d 10239783 TGUI 9783 0 +d 10239785 TGUI 9785 0 +d 10239850 3DImage 9850 0 +d 10239880 Blade 3D PCI/AGP 0 +s 1023988010239880 Blade 3D 0 +d 10239910 CyberBlade/XP 0 +d 10239930 CyberBlade/XPm 0 +v 1024 Zenith Data Systems 0 +v 1025 Acer Incorporated [ALI] 0 +d 10251435 M1435 0 +d 10251445 M1445 0 +d 10251449 M1449 0 +d 10251451 M1451 0 +d 10251461 M1461 0 +d 10251489 M1489 0 +d 10251511 M1511 0 +d 10251512 ALI M1512 Aladdin 0 +d 10251513 M1513 0 +d 10251521 ALI M1521 Aladdin III CPU Bridge 0 +s 1025152110b91521 ALI M1521 Aladdin III CPU Bridge 0 +d 10251523 ALI M1523 ISA Bridge 0 +s 1025152310b91523 ALI M1523 ISA Bridge 0 +d 10251531 M1531 Northbridge [Aladdin IV/IV+] 0 +d 10251533 M1533 PCI-to-ISA Bridge 0 +s 1025153310b91533 ALI M1533 Aladdin IV/V ISA South Bridge 0 +d 10251535 M1535 PCI Bridge + Super I/O + FIR 0 +d 10251541 M1541 Northbridge [Aladdin V] 0 +s 1025154110b91541 ALI M1541 Aladdin V/V+ AGP+PCI North Bridge 0 +d 10251542 M1542 Northbridge [Aladdin V] 0 +d 10251543 M1543 PCI-to-ISA Bridge + Super I/O + FIR 0 +d 10251561 M1561 Northbridge [Aladdin 7] 0 +d 10251621 M1621 Northbridge [Aladdin-Pro II] 0 +d 10251631 M1631 Northbridge+3D Graphics [Aladdin TNT2] 0 +d 10251641 M1641 Northbridge [Aladdin-Pro IV] 0 +d 10251647 ALI M1647 PCI North Bridge 1 MaGiK1 chipset north bridge (as used on e.g. Asus A7A266 board) +d 10253141 M3141 0 +d 10253143 M3143 0 +d 10253145 M3145 0 +d 10253147 M3147 0 +d 10253149 M3149 0 +d 10253151 M3151 0 +d 10253307 M3307 MPEG-I Video Controller 0 +d 10253309 M3309 MPEG-II Video w/ Software Audio Decoder 0 +d 10253321 M3321 MPEG-II Audio/Video Decoder 0 +d 10255212 ALI M4803 0 +d 10255215 ALI PCI EIDE Controller 0 +d 10255217 M5217H 0 +d 10255219 M5219 0 +d 10255225 M5225 0 +d 10255229 M5229 0 +d 10255235 M5235 0 +d 10255237 ALI M5237 PCI USB Host Controller 0 +d 10255240 EIDE Controller 0 +d 10255241 PCMCIA Bridge 0 +d 10255242 General Purpose Controller 0 +d 10255243 PCI to PCI Bridge Controller 0 +d 10255244 Floppy Disk Controller 0 +d 10255247 ALI M1541 PCI to PCI Bridge 0 +d 10255251 M5251 P1394 OHCI Controller 0 +d 10255427 ALI PCI to AGP Bridge 0 +d 10255451 ALI M5451 PCI AC-Link Controller Audio Device 0 +d 10255453 ALI M5453 PCI AC-Link Controller Modem Device 0 +d 10257101 ALI M7101 PCI PMU Power Management Controller 0 +s 1025710110b97101 ALI M7101 PCI PMU Power Management Controller 0 +v 1028 Dell Computer Corporation 0 +d 10280001 PowerEdge Expandable RAID Controller 2/Si 0 +d 10280002 PowerEdge Expandable RAID Controller 3/Di 0 +d 10280003 PowerEdge Expandable RAID Controller 3/Si 0 +d 10280004 PowerEdge Expandable RAID Controller 3/Si 0 +d 10280005 PowerEdge Expandable RAID Controller 3/Di 0 +d 10280006 PowerEdge Expandable RAID Controller 3/Di 0 +d 10280008 PowerEdge Expandable RAID Controller 3/Di 0 +d 1028000a PowerEdge Expandable RAID Controller 3/Di 0 +v 1029 Siemens Nixdorf IS 0 +v 102a LSI Logic 0 +d 102a0000 HYDRA 0 +d 102a0010 ASPEN 0 +v 102b Matrox Graphics, Inc. 0 +d 102b0010 MGA-I [Impression?] 0 DJ: I've a suspicion that 0010 is a duplicate of 0d10. +d 102b0518 MGA-II [Athena] 0 +d 102b0519 MGA 2064W [Millennium] 0 +d 102b051a MGA 1064SG [Mystique] 0 +s 102b051a102b1100 MGA-1084SG Mystique 0 +s 102b051a102b1200 MGA-1084SG Mystique 0 +s 102b051a1100102b MGA-1084SG Mystique 0 +s 102b051a110a0018 Scenic Pro C5 (D1025) 0 +d 102b051b MGA 2164W [Millennium II] 0 +s 102b051b102b051b MGA-2164W Millennium II 0 +s 102b051b102b1100 MGA-2164W Millennium II 0 +s 102b051b102b1200 MGA-2164W Millennium II 0 +d 102b051e MGA 1064SG [Mystique] AGP 0 +d 102b051f MGA 2164W [Millennium II] AGP 0 +d 102b0520 MGA G200 0 +s 102b0520102bdbc2 G200 Multi-Monitor 0 +s 102b0520102bdbc8 G200 Multi-Monitor 0 +s 102b0520102bdbe2 G200 Multi-Monitor 0 +s 102b0520102bdbe8 G200 Multi-Monitor 0 +s 102b0520102bff03 Millennium G200 SD 0 +s 102b0520102bff04 Marvel G200 0 +d 102b0521 MGA G200 AGP 0 +s 102b05211014ff03 Millennium G200 AGP 0 +s 102b0521102b48e9 Mystique G200 AGP 0 +s 102b0521102b48f8 Millennium G200 SD AGP 0 +s 102b0521102b4a60 Millennium G200 LE AGP 0 +s 102b0521102b4a64 Millennium G200 AGP 0 +s 102b0521102bc93c Millennium G200 AGP 0 +s 102b0521102bc9b0 Millennium G200 AGP 0 +s 102b0521102bc9bc Millennium G200 AGP 0 +s 102b0521102bca60 Millennium G250 LE AGP 0 +s 102b0521102bca6c Millennium G250 AGP 0 +s 102b0521102bdbbc Millennium G200 AGP 0 +s 102b0521102bdbc2 Millennium G200 MMS (Dual G200) 0 +s 102b0521102bdbc3 G200 Multi-Monitor 0 +s 102b0521102bdbc8 Millennium G200 MMS (Dual G200) 0 +s 102b0521102bdbd2 G200 Multi-Monitor 0 +s 102b0521102bdbd3 G200 Multi-Monitor 0 +s 102b0521102bdbd4 G200 Multi-Monitor 0 +s 102b0521102bdbd5 G200 Multi-Monitor 0 +s 102b0521102bdbd8 G200 Multi-Monitor 0 +s 102b0521102bdbd9 G200 Multi-Monitor 0 +s 102b0521102bdbe2 Millennium G200 MMS (Quad G200) 0 +s 102b0521102bdbe3 G200 Multi-Monitor 0 +s 102b0521102bdbe8 Millennium G200 MMS (Quad G200) 0 +s 102b0521102bdbf2 G200 Multi-Monitor 0 +s 102b0521102bdbf3 G200 Multi-Monitor 0 +s 102b0521102bdbf4 G200 Multi-Monitor 0 +s 102b0521102bdbf5 G200 Multi-Monitor 0 +s 102b0521102bdbf8 G200 Multi-Monitor 0 +s 102b0521102bdbf9 G200 Multi-Monitor 0 +s 102b0521102bf806 Mystique G200 Video AGP 0 +s 102b0521102bff00 MGA-G200 AGP 0 +s 102b0521102bff02 Mystique G200 AGP 0 +s 102b0521102bff03 Millennium G200 AGP 0 +s 102b0521102bff04 Marvel G200 AGP 0 +s 102b0521110a0032 MGA-G200 AGP 0 +d 102b0525 MGA G400 AGP 0 +s 102b05250e11b16f MGA-G400 AGP 0 +s 102b0525102b0328 Millennium G400 16Mb SDRAM 0 +s 102b0525102b0338 Millennium G400 16Mb SDRAM 0 +s 102b0525102b0378 Millennium G400 32Mb SDRAM 0 +s 102b0525102b0541 Millennium G450 Dual Head 0 +s 102b0525102b0542 Millennium G450 Dual Head LX 0 +s 102b0525102b0543 Millennium G450 Single Head LX 0 +s 102b0525102b0641 Millennium G450 32Mb SDRAM Dual Head 0 +s 102b0525102b0642 Millennium G450 32Mb SDRAM Dual Head LX 0 +s 102b0525102b0643 Millennium G450 32Mb SDRAM Single Head LX 0 +s 102b0525102b07c0 Millennium G450 Dual Head LE 0 +s 102b0525102b07c1 Millennium G450 SDR Dual Head LE 0 +s 102b0525102b0d41 Millennium G450 Dual Head PCI 0 +s 102b0525102b0d42 Millennium G450 Dual Head LX PCI 0 +s 102b0525102b0e00 Marvel G450 eTV 0 +s 102b0525102b0e01 Marvel G450 eTV 0 +s 102b0525102b0e02 Marvel G450 eTV 0 +s 102b0525102b0e03 Marvel G450 eTV 0 +s 102b0525102b0f80 Millennium G450 Low Profile 0 +s 102b0525102b0f81 Millennium G450 Low Profile 0 +s 102b0525102b0f82 Millennium G450 Low Profile DVI 0 +s 102b0525102b0f83 Millennium G450 Low Profile DVI 0 +s 102b0525102b19d8 Millennium G400 16Mb SGRAM 0 +s 102b0525102b19f8 Millennium G400 32Mb SGRAM 0 +s 102b0525102b2159 Millennium G400 Dual Head 16Mb 0 +s 102b0525102b2179 Millennium G400 MAX/Dual Head 32Mb 0 +s 102b0525102b217d Millennium G400 Dual Head Max 0 +s 102b0525102b23c0 Millennium G450 0 +s 102b0525102b23c1 Millennium G450 0 +s 102b0525102b23c2 Millennium G450 DVI 0 +s 102b0525102b23c3 Millennium G450 DVI 0 +s 102b0525102b2f58 Millennium G400 0 +s 102b0525102b2f78 Millennium G400 0 +s 102b0525102b3693 Marvel G400 AGP 0 +s 102b0525102b5dd0 4Sight II 0 +s 102b0525102b5f50 4Sight II 0 +s 102b0525102b5f51 4Sight II 0 +s 102b0525102b5f52 4Sight II 0 +s 102b0525102b9010 Millennium G400 Dual Head 0 +s 102b052514580400 GA-G400 0 +s 102b052517050001 Digital First Millennium G450 32MB SGRAM 0 +s 102b052517050002 Digital First Millennium G450 16MB SGRAM 0 +s 102b052517050003 Digital First Millennium G450 32MB 0 +s 102b052517050004 Digital First Millennium G450 16MB 0 +s 102b0525b16f0e11 MGA-G400 AGP 0 +d 102b0d10 MGA Ultima/Impression 0 +d 102b1000 MGA G100 [Productiva] 0 +s 102b1000102bff01 Productiva G100 0 +s 102b1000102bff05 Productiva G100 Multi-Monitor 0 +d 102b1001 MGA G100 [Productiva] AGP 0 +s 102b1001102b1001 MGA-G100 AGP 0 +s 102b1001102bff00 MGA-G100 AGP 0 +s 102b1001102bff01 MGA-G100 Productiva AGP 0 +s 102b1001102bff03 Millennium G100 AGP 0 +s 102b1001102bff04 MGA-G100 AGP 0 +s 102b1001102bff05 MGA-G100 Productiva AGP Multi-Monitor 0 +s 102b1001110a001e MGA-G100 AGP 0 +d 102b2007 MGA Mistral 0 +d 102b2527 MGA G550 AGP 0 +s 102b2527102b0f83 Millennium G550 0 +s 102b2527102b0f84 Millennium G550 Dual Head DDR 32Mb 0 +s 102b2527102b1e41 Millennium G550 0 +d 102b4536 VIA Framegrabber 0 +d 102b6573 Shark 10/100 Multiport SwitchNIC 0 +v 102c Chips and Technologies 0 +d 102c00b8 F64310 0 +d 102c00c0 F69000 HiQVideo 0 +d 102c00d0 F65545 0 +d 102c00d8 F65545 0 +d 102c00dc F65548 0 +d 102c00e0 F65550 0 +d 102c00e4 F65554 0 +d 102c00e5 F65555 HiQVPro 0 +s 102c00e50e11b049 Armada 1700 Laptop Display Controller 0 +d 102c00f0 F68554 0 +d 102c00f4 F68554 HiQVision 0 +d 102c00f5 F68555 0 +v 102d Wyse Technology Inc. 0 +d 102d50dc 3328 Audio 0 +v 102e Olivetti Advanced Technology 0 +v 102f Toshiba America 0 +d 102f0009 r4x00 0 +d 102f0020 ATM Meteor 155 0 +v 1030 TMC Research 0 +v 1031 Miro Computer Products AG 0 +d 10315601 DC20 ASIC 0 +d 10315607 Video I/O & motion JPEG compressor 0 +d 10315631 Media 3D 0 +d 10316057 MiroVideo DC10/DC30+ 0 +v 1032 Compaq 0 +v 1033 NEC Corporation 0 +d 10330001 PCI to 486-like bus Bridge 0 +d 10330002 PCI to VL98 Bridge 0 +d 10330003 ATM Controller 0 +d 10330004 R4000 PCI Bridge 0 +d 10330005 PCI to 486-like bus Bridge 0 +d 10330006 GUI Accelerator 0 +d 10330007 PCI to UX-Bus Bridge 0 +d 10330008 GUI Accelerator 0 +d 10330009 GUI Accelerator for W98 0 +d 1033001a [Nile II] 0 +d 10330021 Vrc4373 [Nile I] 0 +d 10330029 PowerVR PCX1 0 +d 1033002a PowerVR 3D 0 +d 10330035 USB 0 +s 1033003512ee7000 Root Hub 0 +d 1033003e NAPCCARD Cardbus Controller 0 +d 10330046 PowerVR PCX2 [midas] 0 +d 1033005a Vrc5074 [Nile 4] 0 +d 10330063 Firewarden 0 +d 10330067 PowerVR Neon 250 Chipset 0 +s 1033006710100020 PowerVR Neon 250 AGP 32Mb 0 +s 1033006710100080 PowerVR Neon 250 AGP 16Mb 0 +s 1033006710100088 PowerVR Neon 250 16Mb 0 +s 1033006710100090 PowerVR Neon 250 AGP 16Mb 0 +s 1033006710100098 PowerVR Neon 250 16Mb 0 +s 10330067101000a0 PowerVR Neon 250 AGP 32Mb 0 +s 10330067101000a8 PowerVR Neon 250 32Mb 0 +s 1033006710100120 PowerVR Neon 250 AGP 32Mb 0 +d 10330074 56k Voice Modem 0 +s 1033007410338014 RCV56ACF 56k Voice Modem 0 +d 1033009b Vrc5476 0 +d 103300cd OHCI IEEE 1394 [OrangeLink] Host Controller 0 +s 103300cd12ee8011 Root hub 0 +d 103300e0 USB Enhanced Host Controller 0 +d 103300e0 USB 2.0 1 Originally submitted Nov 2000 ... current entry name is doesn't match 0035 +s 103300e012ee7001 Root hub 0 +v 1034 Framatome Connectors USA Inc. 0 +v 1035 Comp. & Comm. Research Lab 0 +v 1036 Future Domain Corp. 0 +d 10360000 TMC-18C30 [36C70] 0 +v 1037 Hitachi Micro Systems 0 +v 1038 AMP, Inc 0 +v 1039 Silicon Integrated Systems [SiS] 0 +d 10390001 5591/5592 AGP 0 +d 10390002 SG86C202 0 +d 10390006 85C501/2/3 0 +d 10390008 85C503/5513 0 +d 10390009 ACPI 0 +d 10390018 SiS85C503/5513 (LPC Bridge) 0 +d 10390200 5597/5598 VGA 0 +s 1039020010390000 SiS5597 SVGA (Shared RAM) 0 +d 10390204 82C204 0 +d 10390205 SG86C205 0 +d 10390406 85C501/2 0 +d 10390496 85C496 0 +d 10390530 530 Host 0 +d 10390540 540 Host 0 +d 10390597 5513C 0 +d 10390601 85C601 0 +d 10390620 620 Host 0 +d 10390630 630 Host 0 +d 10390730 730 Host 0 +d 10390735 735 Host 0 +d 10390900 SiS900 10/100 Ethernet 0 +s 1039090010390900 SiS900 10/100 Ethernet Adapter 0 +d 10393602 83C602 0 +d 10395107 5107 0 +d 10395300 SiS540 PCI Display Adapter 0 +d 10395401 486 PCI Chipset 0 +d 10395511 5511/5512 0 +d 10395513 5513 [IDE] 0 +s 1039551310395513 SiS5513 EIDE Controller (A,B step) 0 +d 10395517 5517 0 +d 10395571 5571 0 +d 10395581 5581 Pentium Chipset 0 +d 10395582 5582 0 +d 10395591 5591/5592 Host 0 +d 10395596 5596 Pentium Chipset 0 +d 10395597 5597 [SiS5582] 0 +d 10395600 5600 Host 0 +d 10396204 Video decoder & MPEG interface 0 +d 10396205 VGA Controller 0 +d 10396236 6236 3D-AGP 0 +d 10396300 SiS630 GUI Accelerator+3D 0 +d 10396306 6306 3D-AGP 0 +s 1039630610396306 SiS530,620 GUI Accelerator+3D 0 +d 10396326 86C326 0 +s 1039632610396326 SiS6326 GUI Accelerator 0 +s 1039632610920a50 SpeedStar A50 0 +s 1039632610920a70 SpeedStar A70 0 +s 1039632610924910 SpeedStar A70 0 +s 1039632610924920 SpeedStar A70 0 +s 1039632615696326 SiS6326 GUI Accelerator 0 +d 10397001 7001 0 +d 10397007 OHCI Compliant FireWire Controller 0 +d 10397012 SiS7012 PCI Audio Accelerator 0 +d 10397013 56k Winmodem (Smart Link HAMR5600 compatible) 0 +d 10397016 SiS7016 10/100 Ethernet Adapter 0 +s 1039701610397016 SiS7016 10/100 Ethernet Adapter 0 +d 10397018 SiS PCI Audio Accelerator 0 +s 10397018101401b6 SiS PCI Audio Accelerator 0 +s 10397018101401b7 SiS PCI Audio Accelerator 0 +s 1039701810197018 SiS PCI Audio Accelerator 0 +s 103970181025000e SiS PCI Audio Accelerator 0 +s 1039701810250018 SiS PCI Audio Accelerator 0 +s 1039701810397018 SiS PCI Audio Accelerator 0 +s 103970181043800b SiS PCI Audio Accelerator 0 +s 1039701810547018 SiS PCI Audio Accelerator 0 +s 10397018107d5330 SiS PCI Audio Accelerator 0 +s 10397018107d5350 SiS PCI Audio Accelerator 0 +s 1039701811703209 SiS PCI Audio Accelerator 0 +s 103970181462400a SiS PCI Audio Accelerator 0 +s 1039701814a42089 SiS PCI Audio Accelerator 0 +s 1039701814cd2194 SiS PCI Audio Accelerator 0 +s 1039701814ff1100 SiS PCI Audio Accelerator 0 +s 10397018152d8808 SiS PCI Audio Accelerator 0 +s 1039701815581103 SiS PCI Audio Accelerator 0 +s 1039701815582200 SiS PCI Audio Accelerator 0 +s 1039701815637018 SiS PCI Audio Accelerator 0 +s 1039701815c50111 SiS PCI Audio Accelerator 0 +s 10397018270fa171 SiS PCI Audio Accelerator 0 +s 10397018a0a00022 SiS PCI Audio Accelerator 0 +v 103a Seiko Epson Corporation 0 +v 103b Tatung Co. of America 0 +v 103c Hewlett-Packard Company 0 +d 103c1005 A4977A Visualize EG 0 +d 103c1028 Tach TL Fibre Channel Host Adapter 0 +d 103c1029 Tach XL2 Fibre Channel Host Adapter 0 +s 103c1029107e000f Interphase 5560 Fibre Channel Adapter 0 +s 103c102990049210 Adaptec 1Gb/2Gb Family Fibre Channel Controller 1 +s 103c102990049211 Adaptec 1Gb/2Gb Family Fibre Channel Controller 1 +d 103c102a Tach TS Fibre Channel Host Adapter 0 +s 103c102a107e000e Interphase 5540/5541 Fibre Channel Adapter 0 +s 103c102a90049110 Adaptec 1Gb/2Gb Family Fibre Channel Controller 1 +s 103c102a90049111 Adaptec 1Gb/2Gb Family Fibre Channel Controller 1 +d 103c1030 J2585A DeskDirect 10/100VG NIC 0 +d 103c1031 J2585B 0 +d 103c1031 J2585B HP 10/100VG PCI LAN Adapter 1 +s 103c1031103c1040 J2973A DeskDirect 10BaseT NIC 0 +s 103c1031103c1041 J2585B DeskDirect 10/100VG NIC 0 +s 103c1031103c1042 J2970A DeskDirect 10BaseT/2 NIC 0 +d 103c1040 J2973A DeskDirect 10BaseT NIC 0 +d 103c1041 J2585B DeskDirect 10/100 NIC 0 +d 103c1042 J2970A DeskDirect 10BaseT/2 NIC 0 +d 103c1064 79C970 PCnet Ethernet Controller 0 +d 103c10c1 NetServer Smart IRQ Router 0 +d 103c10ed TopTools Remote Control 0 +d 103c1200 82557B 10/100 NIC 0 +d 103c1219 NetServer PCI Hot-Plug Controller 0 +d 103c121a NetServer SMIC Controller 0 +d 103c121b NetServer Legacy COM Port Decoder 0 +d 103c121c NetServer PCI COM Port Decoder 0 +d 103c2910 E2910A 0 +d 103c2910 E2910A PCIBus Exerciser 1 +d 103c2925 E2925A 0 +d 103c2925 E2925A 32 Bit, 33 MHzPCI Exerciser & Analyzer 1 +v 103e Solliday Engineering 0 +v 103f Synopsys/Logic Modeling Group 0 +v 1040 Accelgraphics Inc. 0 +v 1041 Computrend 0 +v 1042 Micron 0 +d 10421000 FDC 37C665 0 +d 10421001 37C922 0 +d 10423000 Samurai_0 0 +d 10423010 Samurai_1 0 +d 10423020 Samurai_IDE 0 +v 1043 Asustek Computer, Inc. 0 +d 10430675 ISDNLink P-IN100-ST-D 0 +d 10434016 V7700 AGP Video Card Subsystem 1 nVidia 10de:0150 Subsystem 1043:4016 TV In/Out 3D Glasses +d 10438053 A7A266 Motherboard IDE 1 ALi 10b9:5229 Subsystem 1043:8053 A7A266 Motherboard IDE Interface +v 1044 Distributed Processing Technology 0 +d 10441012 Domino RAID Engine 0 +d 1044a400 SmartCache/Raid I-IV Controller 0 +d 1044a500 PCI Bridge 0 +d 1044a501 SmartRAID V Controller 0 +s 1044a5011044c001 PM1554U2 Ultra2 Single Channel 1 +s 1044a5011044c002 PM1654U2 Ultra2 Single Channel 1 +s 1044a5011044c003 PM1564U3 Ultra3 Single Channel 1 +s 1044a5011044c004 PM1564U3 Ultra3 Dual Channel 1 +s 1044a5011044c005 PM1554U2 Ultra2 Single Channel (NON ACPI) 1 +s 1044a5011044c00a PM2554U2 Ultra2 Single Channel 1 +s 1044a5011044c00b PM2654U2 Ultra2 Single Channel 1 +s 1044a5011044c00c PM2664U3 Ultra3 Single Channel 1 +s 1044a5011044c00d PM2664U3 Ultra3 Dual Channel 1 +s 1044a5011044c00e PM2554U2 Ultra2 Single Channel (NON ACPI) 1 +s 1044a5011044c00f PM2654U2 Ultra2 Single Channel (NON ACPI) 1 +s 1044a5011044c014 PM3754U2 Ultra2 Single Channel (NON ACPI) 1 +s 1044a5011044c015 PM3755U2B Ultra2 Single Channel (NON ACPI) 1 +s 1044a5011044c016 PM3755F Fibre Channel (NON ACPI) 1 +s 1044a5011044c01e PM3757U2 Ultra2 Single Channel 1 +s 1044a5011044c01f PM3757U2 Ultra2 Dual Channel 1 +s 1044a5011044c020 PM3767U3 Ultra3 Dual Channel 1 +s 1044a5011044c021 PM3767U3 Ultra3 Quad Channel 1 +s 1044a5011044c028 PM2865U3 Ultra3 Single Channel 1 +s 1044a5011044c029 PM2865U3 Ultra3 Dual Channel 1 +s 1044a5011044c02a PM2865F Fibre Channel 1 +s 1044a5011044c03c 2000S Ultra3 Single Channel 1 +s 1044a5011044c03d 2000S Ultra3 Dual Channel 1 +s 1044a5011044c03e 2000F Fibre Channel 1 +s 1044a5011044c046 3000S Ultra3 Single Channel 1 +s 1044a5011044c047 3000S Ultra3 Dual Channel 1 +s 1044a5011044c048 3000F Fibre Channel 1 +s 1044a5011044c050 5000S Ultra3 Single Channel 1 +s 1044a5011044c051 5000S Ultra3 Dual Channel 1 +s 1044a5011044c052 5000F Fibre Channel 1 +s 1044a5011044c05a 2400A UDMA Four Channel 1 +s 1044a5011044c05b 2400A UDMA Four Channel DAC 1 +s 1044a5011044c064 3010S Ultra3 Dual Channel 1 +s 1044a5011044c065 3010S Ultra3 Four Channel 1 +s 1044a5011044c066 3010S Fibre Channel 1 +v 1045 OPTi Inc. 0 +d 1045a0f8 82C750 [Vendetta] USB Controller 0 +d 1045c101 92C264 0 +d 1045c178 92C178 0 +d 1045c556 82X556 [Viper] 0 +d 1045c557 82C557 [Viper-M] 0 +d 1045c558 82C558 [Viper-M ISA+IDE] 0 +d 1045c567 82C750 [Vendetta], device 0 0 +d 1045c568 82C750 [Vendetta], device 1 0 +d 1045c569 82C579 [Viper XPress+ Chipset] 0 +d 1045c621 82C621 0 +d 1045c700 82C700 0 +d 1045c701 82C701 [FireStar Plus] 0 +d 1045c814 82C814 [Firebridge 1] 0 +d 1045c822 82C822 0 +d 1045c824 82C824 0 +d 1045c825 82C825 [Firebridge 2] 0 +d 1045c832 82C832 0 +d 1045c861 82C861 0 +d 1045c895 82C895 0 +d 1045c935 EV1935 ECTIVA MachOne PCI Audio 0 +d 1045d568 82C825 [Firebridge 2] 0 +v 1046 IPC Corporation, Ltd. 0 +v 1047 Genoa Systems Corp 0 +v 1048 Elsa AG 0 +d 10481000 QuickStep 1000 0 +d 10483000 QuickStep 3000 0 +v 1049 Fountain Technologies, Inc. 0 +v 104a SGS Thomson Microelectronics 0 +d 104a0008 STG 2000X 0 +d 104a0009 STG 1764X 0 +d 104a1746 STG 1764X 0 +d 104a3520 MPEG-II decoder card 0 +v 104b BusLogic 0 +d 104b0140 BT-946C (old) [multimaster 01] 0 +d 104b1040 BT-946C (BA80C30) [MultiMaster 10] 0 +d 104b8130 Flashpoint LT 0 +v 104c Texas Instruments 0 +d 104c0500 100 MBit LAN Controller 0 +d 104c0508 TMS380C2X Compressor Interface 0 +d 104c1000 Eagle i/f AS 0 +d 104c3d04 TVP4010 [Permedia] 0 +d 104c3d07 TVP4020 [Permedia 2] 0 +s 104c3d0710114d10 Comet 1 +s 104c3d071040000f AccelStar II 1 +s 104c3d0710400011 AccelStar II 1 +s 104c3d0710480a31 WINNER 2000 1 +s 104c3d0710480a32 GLoria Synergy 1 +s 104c3d0710480a35 GLoria Synergy 1 +s 104c3d07107d2633 WinFast 3D L2300 1 +s 104c3d0710920127 FIRE GL 1000 PRO 0 +s 104c3d0710920136 FIRE GL 1000 PRO 0 +s 104c3d0710920141 FIRE GL 1000 PRO 0 +s 104c3d0710920146 FIRE GL 1000 PRO 0 +s 104c3d0710920148 FIRE GL 1000 PRO 0 +s 104c3d0710920149 FIRE GL 1000 PRO 0 +s 104c3d0710920152 FIRE GL 1000 PRO 0 +s 104c3d0710920154 FIRE GL 1000 PRO 0 +s 104c3d0710920155 FIRE GL 1000 PRO 0 +s 104c3d0710920156 FIRE GL 1000 PRO 0 +s 104c3d0710920157 FIRE GL 1000 PRO 0 +s 104c3d0710973d01 Jeronimo Pro 0 +s 104c3d071102100f Graphics Blaster Extreme 1 +s 104c3d073d3d0100 Reference Permedia 2 3D 0 +d 104c8000 PCILynx/PCILynx2 IEEE 1394 Link Layer Controller 0 +s 104c8000e4bf1010 CF1-1-SNARE 0 +s 104c8000e4bf1020 CF1-2-SNARE 0 +d 104c8009 OHCI Compliant FireWire Controller 0 +s 104c8009104d8032 8032 OHCI i.LINK(IEEE 1394) Controller 1 +d 104c8017 PCI4410 OHCI FireWire Controller 0 +d 104c8019 TSB12LV23 OHCI Compliant IEEE-1394 Controller 0 +s 104c801911bd000a Studio DV500-1394 0 +s 104c801911bd000e Studio DV 0 +s 104c8019e4bf1010 CF2-1-CYMBAL 0 +d 104c8020 TSB12LV26 OHCI Compliant IEEE-1394 Controller (Link) 1 +d 104c8021 TSB43AA22 OHCI Compliant IEEE-1394 Controller (PHY/Link Integrated) 1 +d 104c8022 TSB43AB22 OHCI Compliant IEEE-1394 Controller (PHY/Link) 1394a-2000 1 +d 104c8024 TSB43AB23 OHCI Compliant IEEE-1394 Controller (PHY/Link) 1394a-2000 1 +d 104c8026 TSB43AB21 OHCI Compliant IEEE-1394 Controller (PHY/Link) 1394a-2000 1 +d 104ca001 TDC1570 0 +d 104ca100 TDC1561 0 +d 104cac10 PCI1050 0 +d 104cac11 PCI1053 0 +d 104cac12 PCI1130 0 +d 104cac13 PCI1031 0 +d 104cac15 PCI1131 0 +d 104cac16 PCI1250 0 +d 104cac17 PCI1220 0 +d 104cac18 PCI1260 0 +d 104cac19 PCI1221 0 +d 104cac1a PCI1210 0 +d 104cac1b PCI1450 0 +d 104cac1c PCI1225 0 +d 104cac1d PCI1251A 0 +d 104cac1e PCI1211 0 +d 104cac1f PCI1251B 0 +d 104cac20 TI 2030 0 +d 104cac30 PCI1260 PC card Cardbus Controller 0 +d 104cac40 PCI4450 PC card Cardbus Controller 0 +d 104cac41 PCI4410 PC card Cardbus Controller 0 +d 104cac42 PCI4451 PC card Cardbus Controller 0 +d 104cac50 PCI1410 PC card Cardbus Controller 0 +d 104cac51 PCI1420 0 +d 104cac52 PCI1451 PC card Cardbus Controller 0 +d 104cac53 PCI1421 PC card Cardbus Controller 0 +d 104cfe00 FireWire Host Controller 0 +d 104cfe03 12C01A FireWire Host Controller 0 +v 104d Sony Corporation 0 +d 104d8009 CXD1947Q i.LINK Controller 0 +d 104d8039 CXD3222 i.LINK Controller 0 +d 104d8056 Rockwell HCF 56K modem 0 +d 104d808a Memory Stick Controller 0 +v 104e Oak Technology, Inc 0 +d 104e0017 OTI-64017 0 +d 104e0107 OTI-107 [Spitfire] 0 +d 104e0109 Video Adapter 0 +d 104e0111 OTI-64111 [Spitfire] 0 +d 104e0217 OTI-64217 0 +d 104e0317 OTI-64317 0 +v 104f Co-time Computer Ltd 0 +v 1050 Winbond Electronics Corp 0 +d 10500000 NE2000 0 +d 10500001 W83769F 0 +d 10500105 W82C105 0 +d 10500840 W89C840 0 +s 1050084010500001 W89C840 Ethernet Adapter 0 +s 1050084010500840 W89C840 Ethernet Adapter 0 +d 10500940 W89C940 0 +d 10505a5a W89C940F 0 +d 10509970 W9970CF 0 +v 1051 Anigma, Inc. 0 +v 1052 ?Young Micro Systems 0 +v 1053 Young Micro Systems 0 +v 1054 Hitachi, Ltd 0 +v 1055 EFAR Microsystems 0 +d 10559130 EIDE Controller 0 +d 10559460 PCI to ISA Bridge 0 +d 10559462 USB Universal Host Controller [OHCI] 0 +d 10559463 Power Management Controller [Bridge] 0 +v 1056 ICL 0 +v 1057 Motorola 0 Motorola made a mistake and used 1507 instead of 1057 in some chips. Please look at the 1507 entry as well when updating this. +d 10570001 MPC105 [Eagle] 0 +d 10570002 MPC106 [Grackle] 0 +d 10570100 MC145575 [HFC-PCI] 0 +d 10570431 KTI829c 100VG 0 +d 10571801 Audio I/O Controller (MIDI) 0 +s 10571801ecc00030 Layla 0 +d 10574801 Raven 0 +d 10574802 Falcon 0 +d 10574803 Hawk 0 +d 10574806 CPX8216 0 +d 10574d68 20268 0 +d 10575600 SM56 PCI Modem 0 +s 1057560010570300 SM56 PCI Speakerphone Modem 0 +s 1057560010570301 SM56 PCI Voice Modem 0 +s 1057560010570302 SM56 PCI Fax Modem 0 +s 1057560010575600 SM56 PCI Voice modem 0 +s 1057560013d20300 SM56 PCI Speakerphone Modem 0 +s 1057560013d20301 SM56 PCI Voice modem 0 +s 1057560013d20302 SM56 PCI Fax Modem 0 +s 1057560014360300 SM56 PCI Speakerphone Modem 0 +s 1057560014360301 SM56 PCI Voice modem 0 +s 1057560014360302 SM56 PCI Fax Modem 0 +s 10575600144f100c SM56 PCI Fax Modem 0 +s 1057560014940300 SM56 PCI Speakerphone Modem 0 +s 1057560014940301 SM56 PCI Voice modem 0 +s 1057560014c80300 SM56 PCI Speakerphone Modem 0 +s 1057560014c80302 SM56 PCI Fax Modem 0 +s 1057560016680300 SM56 PCI Speakerphone Modem 0 +s 1057560016680302 SM56 PCI Fax Modem 0 +v 1058 Electronics & Telecommunications RSH 0 +v 1059 Teknor Industrial Computers Inc 0 +v 105a Promise Technology, Inc. 0 +d 105a0d30 20265 0 +s 105a0d30105a4d33 Ultra100 0 +d 105a0d38 20263 0 +s 105a0d38105a4d39 Fasttrak66 0 +d 105a4d30 20267 0 +s 105a4d30105a4d33 Ultra100 0 +s 105a4d30105a4d39 Fasttrak100 0 +d 105a4d33 20246 0 +d 105a4d38 20262 0 +s 105a4d38105a4d30 Ultra Device on SuperTrak 0 +s 105a4d38105a4d33 Ultra66 0 +s 105a4d38105a4d39 Fasttrak66 0 +d 105a4d68 20268 0 +s 105a4d68105a4d68 Ultra100TX2 0 +d 105a4d69 20269 0 +d 105a5275 PDC20276 IDE 1 Found on SuperTrak SX6000 RAID controller. +s 105a5275105a0275 SuperTrak SX6000 IDE 1 From SuperTrak SX6000 +d 105a5300 DC5300 0 +d 105a6268 20268R 0 +v 105b Foxconn International, Inc. 0 +v 105c Wipro Infotech Limited 0 +v 105d Number 9 Computer Company 0 +d 105d2309 Imagine 128 0 +d 105d2339 Imagine 128-II 0 +s 105d2339105d0000 Imagine 128 series 2 4Mb VRAM 0 +s 105d2339105d0001 Imagine 128 series 2 4Mb VRAM 0 +s 105d2339105d0002 Imagine 128 series 2 4Mb VRAM 0 +s 105d2339105d0003 Imagine 128 series 2 4Mb VRAM 0 +s 105d2339105d0004 Imagine 128 series 2 4Mb VRAM 0 +s 105d2339105d0005 Imagine 128 series 2 4Mb VRAM 0 +s 105d2339105d0006 Imagine 128 series 2 4Mb VRAM 0 +s 105d2339105d0007 Imagine 128 series 2 4Mb VRAM 0 +s 105d2339105d0008 Imagine 128 series 2e 4Mb DRAM 0 +s 105d2339105d0009 Imagine 128 series 2e 4Mb DRAM 0 +s 105d2339105d000a Imagine 128 series 2 8Mb VRAM 0 +s 105d2339105d000b Imagine 128 series 2 8Mb H-VRAM 0 +d 105d493d Imagine 128 T2R [Ticket to Ride] 0 +d 105d5348 Revolution 4 0 +v 105e Vtech Computers Ltd 0 +v 105f Infotronic America Inc 0 +v 1060 United Microelectronics [UMC] 0 +d 10600001 UM82C881 0 +d 10600002 UM82C886 0 +d 10600101 UM8673F 0 +d 10600881 UM8881 0 +d 10600886 UM8886F 0 +d 10600891 UM8891A 0 +d 10601001 UM886A 0 +d 1060673a UM8886BF 0 +d 1060673b EIDE Master/DMA 0 +d 10608710 UM8710 0 +d 1060886a UM8886A 0 +d 10608881 UM8881F 0 +d 10608886 UM8886F 0 +d 1060888a UM8886A 0 +d 10608891 UM8891A 0 +d 10609017 UM9017F 0 +d 10609018 UM9018 0 +d 10609026 UM9026 0 +d 1060e881 UM8881N 0 +d 1060e886 UM8886N 0 +d 1060e88a UM8886N 0 +d 1060e891 UM8891N 0 +v 1061 I.I.T. 0 +d 10610001 AGX016 0 +d 10610002 IIT3204/3501 0 +v 1062 Maspar Computer Corp 0 +v 1063 Ocean Office Automation 0 +v 1064 Alcatel 0 +v 1065 Texas Microsystems 0 +v 1066 PicoPower Technology 0 +d 10660000 PT80C826 0 +d 10660001 PT86C52x [Vesuvius] 0 +d 10660002 PT80C524 [Nile] 0 +d 10660005 National PC87550 System Controller 0 +d 10668002 PT80C524 [Nile] 0 +v 1067 Mitsubishi Electric 0 +d 10671002 VG500 [VolumePro Volume Rendering Accelerator] 0 +v 1068 Diversified Technology 0 +v 1069 Mylex Corporation 0 +d 10690001 DAC960P 0 +d 10690002 DAC960PD 0 +d 10690010 DAC960PX 0 +d 1069ba55 eXtremeRAID support Device 0 +v 106a Aten Research Inc 0 +v 106b Apple Computer Inc. 0 +d 106b0001 Bandit PowerPC host bridge 0 +d 106b0002 Grand Central I/O 0 +d 106b0003 Control Video 0 +d 106b0004 PlanB Video-In 0 +d 106b0007 O'Hare I/O 0 +d 106b000e Hydra Mac I/O 0 +d 106b0010 Heathrow Mac I/O 0 +d 106b0017 Paddington Mac I/O 0 +d 106b0018 UniNorth FireWire 0 +d 106b0019 KeyLargo USB 0 +d 106b001e UniNorth Internal PCI 0 +d 106b001f UniNorth PCI 0 +d 106b0020 UniNorth AGP 0 +d 106b0021 UniNorth GMAC (Sun GEM) 0 +d 106b0022 KeyLargo Mac I/O 0 +d 106b0024 UniNorth/Pangea GMAC (Sun GEM) 0 +d 106b0025 KeyLargo/Pangea Mac I/O 0 +d 106b0026 KeyLargo/Pangea USB 0 +d 106b0027 UniNorth/Pangea AGP 0 +d 106b0028 UniNorth/Pangea PCI 0 +d 106b0029 UniNorth/Pangea Internal PCI 0 +d 106b002d UniNorth 1.5 AGP 0 +d 106b002e UniNorth 1.5 PCI 0 +d 106b002f UniNorth 1.5 Internal PCI 0 +d 106b0030 UniNorth/Pangea FireWire 0 +v 106c Hyundai Electronics America 0 +d 106c8801 Dual Pentium ISA/PCI Motherboard 0 +d 106c8802 PowerPC ISA/PCI Motherboard 0 +d 106c8803 Dual Window Graphics Accelerator 0 +d 106c8804 LAN Controller 0 +d 106c8805 100-BaseT LAN 0 +v 106d Sequent Computer Systems 0 +v 106e DFI, Inc 0 +v 106f City Gate Development Ltd 0 +v 1070 Daewoo Telecom Ltd 0 +v 1071 Mitac 0 +v 1072 GIT Co Ltd 0 +v 1073 Yamaha Corporation 0 +d 10730001 3D GUI Accelerator 0 +d 10730002 YGV615 [RPA3 3D-Graphics Controller] 0 +d 10730003 YMF-740 0 +d 10730004 YMF-724 0 +s 1073000410730004 YMF724-Based PCI Audio Adapter 0 +d 10730005 DS1 Audio 0 +s 1073000510730005 DS-XG PCI Audio CODEC 0 +d 10730006 DS1 Audio 0 +d 10730008 DS1 Audio 0 +s 1073000810730008 DS-XG PCI Audio CODEC 0 +d 1073000a DS1L Audio 0 +s 1073000a10730004 DS-XG PCI Audio CODEC 0 +s 1073000a1073000a DS-XG PCI Audio CODEC 0 +d 1073000c YMF-740C [DS-1L Audio Controller] 0 +s 1073000c107a000c DS-XG PCI Audio CODEC 0 +d 1073000d YMF-724F [DS-1 Audio Controller] 0 +s 1073000d1073000d DS-XG PCI Audio CODEC 0 +d 10730010 YMF-744B [DS-1S Audio Controller] 0 +s 1073001010730006 DS-XG PCI Audio CODEC 0 +s 1073001010730010 DS-XG PCI Audio CODEC 0 +d 10730012 YMF-754 [DS-1E Audio Controller] 0 +s 1073001210730012 DS-XG PCI Audio Codec 0 +d 10730020 DS-1 Audio 0 +d 10732000 DS2416 Digital Mixing Card 0 +s 1073200010732000 DS2416 Digital Mixing Card 0 +v 1074 NexGen Microsystems 0 +d 10744e78 82c500/1 0 +v 1075 Advanced Integrations Research 0 +v 1076 Chaintech Computer Co. Ltd 0 +v 1077 QLogic Corp. 0 +d 10771016 ISP10160 Single Channel Ultra3 SCSI Processor 0 +d 10771020 ISP1020 Fast-wide SCSI 0 +d 10771022 ISP1022 Fast-wide SCSI 0 +d 10771080 ISP1080 SCSI Host Adapter 0 +d 10771216 ISP12160 Dual Channel Ultra3 SCSI Processor 0 +s 10771216101e8471 QLA12160 on AMI MegaRAID 0 +s 10771216101e8493 QLA12160 on AMI MegaRAID 0 +d 10771240 ISP1240 SCSI Host Adapter 0 +d 10771280 ISP1280 0 +d 10772020 ISP2020A Fast!SCSI Basic Adapter 0 +d 10772100 QLA2100 64-bit Fibre Channel Adapter 0 +s 1077210010770001 QLA2100 64 bit Fibre Channel Adapter 1 +d 10772200 QLA2200 0 +d 10772300 QLA2300 64-bit FC-AL Adapter 0 +d 10772312 QLA2312 Fibre Channel Adapter 0 +v 1078 Cyrix Corporation 0 +d 10780000 5510 [Grappa] 0 +d 10780001 PCI Master 0 +d 10780002 5520 [Cognac] 0 +d 10780100 5530 Legacy [Kahlua] 0 +d 10780101 5530 SMI [Kahlua] 0 +d 10780102 5530 IDE [Kahlua] 0 +d 10780103 5530 Audio [Kahlua] 0 +d 10780104 5530 Video [Kahlua] 0 +d 10780400 ZFMicro PCI Bridge 0 +d 10780401 ZFMicro Chipset SMI 0 +d 10780402 ZFMicro Chipset IDE 0 +d 10780403 ZFMicro Expansion Bus 0 +v 1079 I-Bus 0 +v 107a NetWorth 0 +v 107b Gateway 2000 0 +v 107c LG Electronics [Lucky Goldstar Co. Ltd] 0 +v 107d LeadTek Research Inc. 0 +d 107d0000 P86C850 0 +v 107e Interphase Corporation 0 +d 107e0001 5515 ATM Adapter [Flipper] 0 +d 107e0002 100 VG AnyLan Controller 0 +d 107e0004 5526 Fibre Channel Host Adapter 0 +d 107e0005 x526 Fibre Channel Host Adapter 0 +d 107e0008 5525/5575 ATM Adapter (155 Mbit) [Atlantic] 0 +d 107e9003 5535-4P-BRI-ST 0 +d 107e9007 5535-4P-BRI-U 0 +d 107e9008 5535-1P-SR 0 +d 107e900c 5535-1P-SR-ST 0 +d 107e900e 5535-1P-SR-U 0 +d 107e9011 5535-1P-PRI 0 +d 107e9013 5535-2P-PRI 0 +d 107e9023 5536-4P-BRI-ST 0 +d 107e9027 5536-4P-BRI-U 0 +d 107e9031 5536-1P-PRI 0 +d 107e9033 5536-2P-PRI 0 +v 107f Data Technology Corporation 0 +d 107f0802 SL82C105 0 +v 1080 Contaq Microsystems 0 +d 10800600 82C599 0 +d 1080c691 Cypress CY82C691 0 +d 1080c693 82c693 0 +v 1081 Supermac Technology 0 +d 10810d47 Radius PCI to NuBUS Bridge 0 +v 1082 EFA Corporation of America 0 +v 1083 Forex Computer Corporation 0 +d 10830001 FR710 0 +v 1084 Parador 0 +v 1085 Tulip Computers Int.B.V. 0 +v 1086 J. Bond Computer Systems 0 +v 1087 Cache Computer 0 +v 1088 Microcomputer Systems (M) Son 0 +v 1089 Data General Corporation 0 +v 108a Bit3 Computer Corp. 0 +d 108a0001 VME Bridge Model 617 0 +d 108a0010 VME Bridge Model 618 0 +d 108a3000 VME Bridge Model 2706 0 +v 108c Oakleigh Systems Inc. 0 +v 108d Olicom 0 +d 108d0001 Token-Ring 16/4 PCI Adapter (3136/3137) 0 +d 108d0002 16/4 Token Ring 0 +d 108d0004 RapidFire 3139 Token-Ring 16/4 PCI Adapter 0 +s 108d0004108d0004 OC-3139/3140 RapidFire Token-Ring 16/4 Adapter 0 +d 108d0005 GoCard 3250 Token-Ring 16/4 CardBus PC Card 0 +d 108d0006 OC-3530 RapidFire Token-Ring 100 0 +d 108d0007 RapidFire 3141 Token-Ring 16/4 PCI Fiber Adapter 0 +s 108d0007108d0007 OC-3141 RapidFire Token-Ring 16/4 Adapter 0 +d 108d0008 RapidFire 3540 HSTR 100/16/4 PCI Adapter 0 +s 108d0008108d0008 OC-3540 RapidFire HSTR 100/16/4 Adapter 0 +d 108d0011 OC-2315 0 +d 108d0012 OC-2325 0 +d 108d0013 OC-2183/2185 0 +d 108d0014 OC-2326 0 +d 108d0019 OC-2327/2250 10/100 Ethernet Adapter 0 +s 108d0019108d0016 OC-2327 Rapidfire 10/100 Ethernet Adapter 0 +s 108d0019108d0017 OC-2250 GoCard 10/100 Ethernet Adapter 0 +d 108d0021 OC-6151/6152 [RapidFire ATM 155] 0 +d 108d0022 ATM Adapter 0 +v 108e Sun Microsystems Computer Corp. 0 +d 108e0001 EBUS 0 +d 108e1000 EBUS 0 +d 108e1001 Happy Meal 0 +d 108e1100 RIO EBUS 0 +d 108e1101 RIO GEM 0 +d 108e1102 RIO 1394 0 +d 108e1103 RIO USB 0 +d 108e2bad GEM 0 +d 108e5000 Simba Advanced PCI Bridge 0 +d 108e5043 SunPCI Co-processor 0 +d 108e8000 Psycho PCI Bus Module 0 +d 108e8001 Schizo PCI Bus Module 0 +d 108ea000 Ultra IIi 0 +d 108ea001 Ultra IIe 0 +v 108f Systemsoft 0 +v 1090 Encore Computer Corporation 0 +v 1091 Intergraph Corporation 0 +d 10910020 3D graphics processor 0 +d 10910021 3D graphics processor w/Texturing 0 +d 10910040 3D graphics frame buffer 0 +d 10910041 3D graphics frame buffer 0 +d 10910060 Proprietary bus bridge 0 +d 109100e4 Powerstorm 4D50T 0 +d 10910720 Motion JPEG codec 0 +v 1092 Diamond Multimedia Systems 0 +d 109200a0 Speedstar Pro SE 0 +d 109200a8 Speedstar 64 0 +d 10920550 Viper V550 0 +d 109208d4 Supra 2260 Modem 0 +d 1092094c SupraExpress 56i Pro 0 +d 10921092 Viper V330 0 +d 10926120 Maximum DVD 0 +d 10928810 Stealth SE 0 +d 10928811 Stealth 64/SE 0 +d 10928880 Stealth 0 +d 10928881 Stealth 0 +d 109288b0 Stealth 64 0 +d 109288b1 Stealth 64 0 +d 109288c0 Stealth 64 0 +d 109288c1 Stealth 64 0 +d 109288d0 Stealth 64 0 +d 109288d1 Stealth 64 0 +d 109288f0 Stealth 64 0 +d 109288f1 Stealth 64 0 +d 10929999 DMD-I0928-1 "Monster sound" sound chip 0 +v 1093 National Instruments 0 +d 10930160 PCI-DIO-96 0 +d 10930162 PCI-MIO-16XE-50 0 +d 10931170 PCI-MIO-16XE-10 0 +d 10931180 PCI-MIO-16E-1 0 +d 10931190 PCI-MIO-16E-4 0 +d 10931330 PCI-6031E 0 +d 10931350 PCI-6071E 0 +d 10932a60 PCI-6023E 0 +d 1093b001 IMAQ-PCI-1408 0 +d 1093b011 IMAQ-PXI-1408 0 +d 1093b021 IMAQ-PCI-1424 0 +d 1093b031 IMAQ-PCI-1413 0 +d 1093b041 IMAQ-PCI-1407 0 +d 1093b051 IMAQ-PXI-1407 0 +d 1093b061 IMAQ-PCI-1411 0 +d 1093b071 IMAQ-PCI-1422 0 +d 1093b081 IMAQ-PXI-1422 0 +d 1093b091 IMAQ-PXI-1411 0 +d 1093c801 PCI-GPIB 0 +v 1094 First International Computers [FIC] 0 +v 1095 CMD Technology Inc 0 +d 10950640 PCI0640 0 +d 10950643 PCI0643 0 +d 10950646 PCI0646 0 +d 10950647 PCI0647 0 +d 10950648 PCI0648 0 +d 10950649 PCI0649 0 +s 109506490e11005d Integrated Ultra ATA-100 Dual Channel Controller 0 +s 109506490e11007e Integrated Ultra ATA-100 IDE RAID Controller 0 +s 10950649101e0649 AMI MegaRAID IDE 100 Controller 0 +d 10950650 PBC0650A 0 +d 10950670 USB0670 0 +d 10950673 USB0673 0 +d 10950680 PCI0680 0 +v 1096 Alacron 0 +v 1097 Appian Technology 0 +v 1098 Quantum Designs (H.K.) Ltd 0 +d 10980001 QD-8500 0 +d 10980002 QD-8580 0 +v 1099 Samsung Electronics Co., Ltd 0 +v 109a Packard Bell 0 +v 109b Gemlight Computer Ltd. 0 +v 109c Megachips Corporation 0 +v 109d Zida Technologies Ltd. 0 +v 109e Brooktree Corporation 0 +d 109e0350 Bt848 TV with DMA push 0 +d 109e0351 Bt849A Video capture 0 +d 109e036c Bt879(??) Video Capture 0 +s 109e036c13e90070 Win/TV (Video Section) 0 +d 109e036e Bt878 0 +s 109e036e007013eb WinTV/GO 0 +s 109e036e127a0001 Bt878 Mediastream Controller NTSC 0 +s 109e036e127a0002 Bt878 Mediastream Controller PAL BG 0 +s 109e036e127a0003 Bt878a Mediastream Controller PAL BG 0 +s 109e036e127a0048 Bt878/832 Mediastream Controller 0 +s 109e036e144f3000 MagicTView CPH060 - Video 0 +s 109e036e14f10001 Bt878 Mediastream Controller NTSC 0 +s 109e036e14f10002 Bt878 Mediastream Controller PAL BG 0 +s 109e036e14f10003 Bt878a Mediastream Controller PAL BG 0 +s 109e036e14f10048 Bt878/832 Mediastream Controller 0 +s 109e036e18511850 FlyVideo'98 - Video 0 +s 109e036e18511851 FlyVideo II 0 +s 109e036e18521852 FlyVideo'98 - Video (with FM Tuner) 0 +d 109e036f Bt879 0 +s 109e036f127a0044 Bt879 Video Capture NTSC 0 +s 109e036f127a0122 Bt879 Video Capture PAL I 0 +s 109e036f127a0144 Bt879 Video Capture NTSC 0 +s 109e036f127a0222 Bt879 Video Capture PAL BG 0 +s 109e036f127a0244 Bt879a Video Capture NTSC 0 +s 109e036f127a0322 Bt879 Video Capture NTSC 0 +s 109e036f127a0422 Bt879 Video Capture NTSC 0 +s 109e036f127a1122 Bt879 Video Capture PAL I 0 +s 109e036f127a1222 Bt879 Video Capture PAL BG 0 +s 109e036f127a1322 Bt879 Video Capture NTSC 0 +s 109e036f127a1522 Bt879a Video Capture PAL I 0 +s 109e036f127a1622 Bt879a Video Capture PAL BG 0 +s 109e036f127a1722 Bt879a Video Capture NTSC 0 +s 109e036f14f10044 Bt879 Video Capture NTSC 0 +s 109e036f14f10122 Bt879 Video Capture PAL I 0 +s 109e036f14f10144 Bt879 Video Capture NTSC 0 +s 109e036f14f10222 Bt879 Video Capture PAL BG 0 +s 109e036f14f10244 Bt879a Video Capture NTSC 0 +s 109e036f14f10322 Bt879 Video Capture NTSC 0 +s 109e036f14f10422 Bt879 Video Capture NTSC 0 +s 109e036f14f11122 Bt879 Video Capture PAL I 0 +s 109e036f14f11222 Bt879 Video Capture PAL BG 0 +s 109e036f14f11322 Bt879 Video Capture NTSC 0 +s 109e036f14f11522 Bt879a Video Capture PAL I 0 +s 109e036f14f11622 Bt879a Video Capture PAL BG 0 +s 109e036f14f11722 Bt879a Video Capture NTSC 0 +s 109e036f18511850 FlyVideo'98 - Video 0 +s 109e036f18511851 FlyVideo II 0 +s 109e036f18521852 FlyVideo'98 - Video (with FM Tuner) 0 +d 109e0370 Bt880 Video Capture 0 +s 109e037018511850 FlyVideo'98 0 +s 109e037018511851 FlyVideo'98 EZ - video 0 +s 109e037018521852 FlyVideo'98 (with FM Tuner) 0 +d 109e0878 Bt878 0 +s 109e0878007013eb WinTV/GO 0 +s 109e0878127a0001 Bt878 Video Capture (Audio Section) 0 +s 109e0878127a0002 Bt878 Video Capture (Audio Section) 0 +s 109e0878127a0003 Bt878 Video Capture (Audio Section) 0 +s 109e0878127a0048 Bt878 Video Capture (Audio Section) 0 +s 109e087813e90070 Win/TV (Audio Section) 0 +s 109e0878144f3000 MagicTView CPH060 - Audio 0 +s 109e087814f10001 Bt878 Video Capture (Audio Section) 0 +s 109e087814f10002 Bt878 Video Capture (Audio Section) 0 +s 109e087814f10003 Bt878 Video Capture (Audio Section) 0 +s 109e087814f10048 Bt878 Video Capture (Audio Section) 0 +d 109e0879 Bt879 Video Capture (Audio Section) 0 +s 109e0879127a0044 Bt879 Video Capture (Audio Section) 0 +s 109e0879127a0122 Bt879 Video Capture (Audio Section) 0 +s 109e0879127a0144 Bt879 Video Capture (Audio Section) 0 +s 109e0879127a0222 Bt879 Video Capture (Audio Section) 0 +s 109e0879127a0244 Bt879 Video Capture (Audio Section) 0 +s 109e0879127a0322 Bt879 Video Capture (Audio Section) 0 +s 109e0879127a0422 Bt879 Video Capture (Audio Section) 0 +s 109e0879127a1122 Bt879 Video Capture (Audio Section) 0 +s 109e0879127a1222 Bt879 Video Capture (Audio Section) 0 +s 109e0879127a1322 Bt879 Video Capture (Audio Section) 0 +s 109e0879127a1522 Bt879 Video Capture (Audio Section) 0 +s 109e0879127a1622 Bt879 Video Capture (Audio Section) 0 +s 109e0879127a1722 Bt879 Video Capture (Audio Section) 0 +s 109e087914f10044 Bt879 Video Capture (Audio Section) 0 +s 109e087914f10122 Bt879 Video Capture (Audio Section) 0 +s 109e087914f10144 Bt879 Video Capture (Audio Section) 0 +s 109e087914f10222 Bt879 Video Capture (Audio Section) 0 +s 109e087914f10244 Bt879 Video Capture (Audio Section) 0 +s 109e087914f10322 Bt879 Video Capture (Audio Section) 0 +s 109e087914f10422 Bt879 Video Capture (Audio Section) 0 +s 109e087914f11122 Bt879 Video Capture (Audio Section) 0 +s 109e087914f11222 Bt879 Video Capture (Audio Section) 0 +s 109e087914f11322 Bt879 Video Capture (Audio Section) 0 +s 109e087914f11522 Bt879 Video Capture (Audio Section) 0 +s 109e087914f11622 Bt879 Video Capture (Audio Section) 0 +s 109e087914f11722 Bt879 Video Capture (Audio Section) 0 +d 109e0880 Bt880 Video Capture (Audio Section) 0 +d 109e2115 BtV 2115 Mediastream controller 0 +d 109e2125 BtV 2125 Mediastream controller 0 +d 109e2164 BtV 2164 0 +d 109e2165 BtV 2165 0 +d 109e8230 Bt8230 ATM Segment/Reassembly Ctrlr (SRC) 0 +d 109e8472 Bt8472 0 +d 109e8474 Bt8474 0 +v 109f Trigem Computer Inc. 0 +v 10a0 Meidensha Corporation 0 +v 10a1 Juko Electronics Ind. Co. Ltd 0 +v 10a2 Quantum Corporation 0 +v 10a3 Everex Systems Inc 0 +v 10a4 Globe Manufacturing Sales 0 +v 10a5 Racal Interlan 0 +v 10a6 Informtech Industrial Ltd. 0 +v 10a7 Benchmarq Microelectronics 0 +v 10a8 Sierra Semiconductor 0 +d 10a80000 STB Horizon 64 0 +v 10a9 Silicon Graphics, Inc. 0 +d 10a90001 Crosstalk to PCI Bridge 0 +d 10a90002 Linc I/O controller 0 +d 10a90003 IOC3 I/O controller 0 +d 10a90004 O2 MACE 0 +d 10a90005 RAD Audio 0 +d 10a90006 HPCEX 0 +d 10a90007 RPCEX 0 +d 10a90008 DiVO VIP 0 +d 10a90009 Alteon Gigabit Ethernet 0 +d 10a90010 AMP Video I/O 0 +d 10a90011 GRIP 0 +d 10a90012 SGH PSHAC GSN 0 +d 10a91001 Magic Carpet 0 +d 10a91002 Lithium 0 +d 10a91003 Dual JPEG 1 0 +d 10a91004 Dual JPEG 2 0 +d 10a91005 Dual JPEG 3 0 +d 10a91006 Dual JPEG 4 0 +d 10a91007 Dual JPEG 5 0 +d 10a91008 Cesium 0 +d 10a92001 Fibre Channel 0 +d 10a92002 ASDE 0 +d 10a98001 O2 1394 0 +d 10a98002 G-net NT 0 +v 10aa ACC Microelectronics 0 +d 10aa0000 ACCM 2188 0 +v 10ab Digicom 0 +v 10ac Honeywell IAC 0 +v 10ad Symphony Labs 0 +d 10ad0001 W83769F 0 +d 10ad0003 SL82C103 0 +d 10ad0005 SL82C105 0 +d 10ad0103 SL82c103 0 +d 10ad0105 SL82c105 0 +d 10ad0565 W83C553 0 +v 10ae Cornerstone Technology 0 +v 10af Micro Computer Systems Inc 0 +v 10b0 CardExpert Technology 0 +v 10b1 Cabletron Systems Inc 0 +v 10b2 Raytheon Company 0 +v 10b3 Databook Inc 0 +d 10b33106 DB87144 0 +d 10b3b106 DB87144 0 +v 10b4 STB Systems Inc 0 +d 10b41b1d Velocity 128 3D 0 +s 10b41b1d10b4237e Velocity 4400 0 +v 10b5 PLX Technology, Inc. 0 +d 10b50001 i960 PCI bus interface 0 +d 10b51076 VScom 800 8 port serial adaptor 0 +d 10b51077 VScom 400 4 port serial adaptor 0 +d 10b51078 VScom 210 2 port serial and 1 port parallel adaptor 0 +d 10b51103 VScom 200 2 port serial adaptor 0 +d 10b51146 VScom 010 1 port parallel adaptor 0 +d 10b51147 VScom 020 2 port parallel adaptor 0 +d 10b59036 9036 0 +d 10b59050 PCI <-> IOBus Bridge 0 +s 10b5905010b52273 SH-ARC SoHard ARCnet card 0 +s 10b5905015220001 RockForce 4 Port V.90 Data/Fax/Voice Modem 1 +s 10b5905015220001 1 +s 10b5905015220001 RockForce 4 Port V.90 Data/Fax/Voice Modem 1 support@mainpine.com +s 10b5905015220002 RockForce 2 Port V.90 Data/Fax/Voice Modem 1 +s 10b5905015220010 RockForce2000 4 Port V.90 Data/Fax/Voice Modem 1 +s 10b5905015220020 RockForce2000 2 Port V.90 Data/Fax/Voice Modem 1 +s 10b5905015ed1000 Macrolink MCCS 8-port Serial 0 +s 10b5905015ed1001 Macrolink MCCS 16-port Serial 0 +s 10b5905015ed1002 Macrolink MCCS 8-port Serial Hot Swap 0 +s 10b5905015ed1003 Macrolink MCCS 16-port Serial Hot Swap 0 +s 10b59050d531c002 PCIntelliCAN 2xSJA1000 CAN bus 1 +s 10b59050d84d4006 EX-4006 1P 0 +s 10b59050d84d4008 EX-4008 1P EPP/ECP 0 +s 10b59050d84d4014 EX-4014 2P 0 +s 10b59050d84d4018 EX-4018 3P EPP/ECP 0 +s 10b59050d84d4025 EX-4025 1S(16C550) RS-232 0 +s 10b59050d84d4027 EX-4027 1S(16C650) RS-232 0 +s 10b59050d84d4028 EX-4028 1S(16C850) RS-232 0 +s 10b59050d84d4036 EX-4036 2S(16C650) RS-232 0 +s 10b59050d84d4037 EX-4037 2S(16C650) RS-232 0 +s 10b59050d84d4038 EX-4038 2S(16C850) RS-232 0 +s 10b59050d84d4052 EX-4052 1S(16C550) RS-422/485 0 +s 10b59050d84d4053 EX-4053 2S(16C550) RS-422/485 0 +s 10b59050d84d4055 EX-4055 4S(16C550) RS-232 0 +s 10b59050d84d4058 EX-4055 4S(16C650) RS-232 0 +s 10b59050d84d4065 EX-4065 8S(16C550) RS-232 0 +s 10b59050d84d4068 EX-4068 8S(16C650) RS-232 0 +s 10b59050d84d4078 EX-4078 2S(16C552) RS-232+1P 0 +d 10b59060 9060 0 +d 10b5906d 9060SD 0 +s 10b5906d125c0640 Aries 16000P 0 +d 10b5906e 9060ES 0 +d 10b59080 9080 0 +s 10b5908010b59080 9080 [real subsystem ID not set] 0 +d 10b5a001 GTEK Jetport II 2 port serial adaptor 0 +d 10b5c001 GTEK Cyclone 16/32 port serial adaptor 0 +v 10b6 Madge Networks 0 +d 10b60001 Smart 16/4 PCI Ringnode 0 +d 10b60002 Smart 16/4 PCI Ringnode Mk2 0 +s 10b6000210b60002 Smart 16/4 PCI Ringnode Mk2 0 +s 10b6000210b60006 16/4 CardBus Adapter 0 +d 10b60003 Smart 16/4 PCI Ringnode Mk3 0 +s 10b600030e11b0fd Compaq NC4621 PCI, 4/16, WOL 0 +s 10b6000310b60003 Smart 16/4 PCI Ringnode Mk3 0 +s 10b6000310b60007 Presto PCI Plus Adapter 0 +d 10b60004 Smart 16/4 PCI Ringnode Mk1 0 +d 10b60006 16/4 Cardbus Adapter 0 +s 10b6000610b60006 16/4 CardBus Adapter 0 +d 10b60007 Presto PCI Adapter 0 +s 10b6000710b60007 Presto PCI 0 +d 10b60009 Smart 100/16/4 PCI-HS Ringnode 0 +s 10b6000910b60009 Smart 100/16/4 PCI-HS Ringnode 0 +d 10b6000a Smart 100/16/4 PCI Ringnode 0 +s 10b6000a10b6000a Smart 100/16/4 PCI Ringnode 0 +d 10b6000b 16/4 CardBus Adapter Mk2 0 +s 10b6000b10b60008 16/4 CardBus Adapter Mk2 1 +s 10b6000b10b6000b 16/4 Cardbus Adapter Mk2 0 +d 10b6000c RapidFire 3140V2 16/4 TR Adapter 1 +s 10b6000c10b6000c RapidFire 3140V2 16/4 TR Adapter 1 +d 10b61000 Collage 25 ATM Adapter 0 +d 10b61000 Collage 25/155 ATM Client Adapter 1 +d 10b61001 Collage 155 ATM Server Adapter 0 +v 10b7 3Com Corporation 0 +d 10b70001 3c985 1000BaseSX (SX/TX) 0 +d 10b71007 Mini PCI 56k Winmodem 0 +s 10b7100710b7615c Mini PCI 56K Modem 1 +d 10b73390 3c339 TokenLink Velocity 0 +d 10b73590 3c359 TokenLink Velocity XL 0 +s 10b7359010b73590 TokenLink Velocity XL Adapter (3C359/359B) 0 +d 10b74500 3c450 Cyclone/unknown 0 +d 10b75055 3c555 Laptop Hurricane 0 +d 10b75057 3c575 [Megahertz] 10/100 LAN CardBus 0 +s 10b7505710b75a57 3C575 Megahertz 10/100 LAN Cardbus PC Card 0 +d 10b75157 3c575 [Megahertz] 10/100 LAN CardBus 0 +s 10b7515710b75b57 3C575 Megahertz 10/100 LAN Cardbus PC Card 0 +d 10b75257 3CCFE575CT Cyclone CardBus 0 +s 10b7525710b75c57 FE575C-3Com 10/100 LAN CardBus-Fast Ethernet 0 +d 10b75900 3c590 10BaseT [Vortex] 0 +d 10b75920 3c592 EISA 10mbps Demon/Vortex 0 +d 10b75950 3c595 100BaseTX [Vortex] 0 +d 10b75951 3c595 100BaseT4 [Vortex] 0 +d 10b75952 3c595 100Base-MII [Vortex] 0 +d 10b75970 3c597 EISA Fast Demon/Vortex 0 +d 10b75b57 3c595 [Megahertz] 10/100 LAN CardBus 0 +s 10b75b5710b75b57 3C575 Megahertz 10/100 LAN Cardbus PC Card 0 +d 10b76055 3c556 Hurricane CardBus 0 +d 10b76056 3c556B Hurricane CardBus 0 +s 10b7605610b76556 10/100 Mini PCI Ethernet Adapter 0 +d 10b76560 3CCFE656 Cyclone CardBus 0 +s 10b7656010b7656a 3CCFEM656 10/100 LAN 56K Modem CardBus 0 +d 10b76561 3CCFEM656 10/100 LAN 56K Modem CardBus 0 +s 10b7656110b7656b 3CCFEM656 10/100 LAN 56K Modem CardBus 0 +d 10b76562 3CCFEM656 [id 6562] Cyclone CardBus 0 +s 10b7656210b7656b 3CCFEM656B 10/100 LAN 56K Modem CardBus 0 +d 10b76563 3CCFEM656B 10/100 LAN 56K Modem CardBus 0 +s 10b7656310b7656b 3CCFEM656 10/100 LAN 56K Modem CardBus 0 +d 10b76564 3CCFEM656 [id 6564] Cyclone CardBus 0 +d 10b77646 3cSOHO100-TX Hurricane 0 +d 10b77940 3c803 FDDILink UTP Controller 0 +d 10b77980 3c804 FDDILink SAS Controller 0 +d 10b77990 3c805 FDDILink DAS Controller 0 +d 10b78811 Token ring 0 +d 10b79000 3c900 10BaseT [Boomerang] 0 +d 10b79001 3c900 Combo [Boomerang] 0 +d 10b79004 3c900B-TPO [Etherlink XL TPO] 0 +s 10b7900410b79004 3C900B-TPO Etherlink XL TPO 10Mb 0 +d 10b79005 3c900B-Combo [Etherlink XL Combo] 0 +s 10b7900510b79005 3C900B-Combo Etherlink XL Combo 0 +d 10b79006 3c900B-TPC [Etherlink XL TPC] 0 +d 10b7900a 3c900B-FL [Etherlink XL FL] 0 +d 10b79050 3c905 100BaseTX [Boomerang] 0 +d 10b79051 3c905 100BaseT4 [Boomerang] 0 +d 10b79055 3c905B 100BaseTX [Cyclone] 0 +s 10b7905510280080 3C905B Fast Etherlink XL 10/100 0 +s 10b7905510280081 3C905B Fast Etherlink XL 10/100 0 +s 10b7905510280082 3C905B Fast Etherlink XL 10/100 0 +s 10b7905510280083 3C905B Fast Etherlink XL 10/100 0 +s 10b7905510280084 3C905B Fast Etherlink XL 10/100 0 +s 10b7905510280085 3C905B Fast Etherlink XL 10/100 0 +s 10b7905510280086 3C905B Fast Etherlink XL 10/100 0 +s 10b7905510280087 3C905B Fast Etherlink XL 10/100 0 +s 10b7905510280088 3C905B Fast Etherlink XL 10/100 0 +s 10b7905510280089 3C905B Fast Etherlink XL 10/100 0 +s 10b7905510280090 3C905B Fast Etherlink XL 10/100 0 +s 10b7905510280091 3C905B Fast Etherlink XL 10/100 0 +s 10b7905510280092 3C905B Fast Etherlink XL 10/100 0 +s 10b7905510280093 3C905B Fast Etherlink XL 10/100 0 +s 10b7905510280094 3C905B Fast Etherlink XL 10/100 0 +s 10b7905510280095 3C905B Fast Etherlink XL 10/100 0 +s 10b7905510280096 3C905B Fast Etherlink XL 10/100 0 +s 10b7905510280097 3C905B Fast Etherlink XL 10/100 0 +s 10b7905510280098 3C905B Fast Etherlink XL 10/100 0 +s 10b7905510280099 3C905B Fast Etherlink XL 10/100 0 +s 10b7905510b79055 3C905B Fast Etherlink XL 10/100 0 +d 10b79056 3c905B-T4 [Fast EtherLink XL 10/100] 0 +d 10b79058 3c905B-Combo [Deluxe Etherlink XL 10/100] 0 +d 10b7905a 3c905B-FX [Fast Etherlink XL FX 10/100] 0 +d 10b79200 3c905C-TX [Fast Etherlink] 0 +d 10b79200 3c905C-TX/TX-M [Tornado] 1 +s 10b7920010b71000 3C905C-TX Fast Etherlink for PC Management NIC 0 +s 10b7920010b71000 EtherLink 10/100 NIC for Complete PC Management 1 +s 10b7920010b77000 10/100 Mini PCI Ethernet Adapter 0 +d 10b79800 3c980-TX [Fast Etherlink XL Server Adapter] 0 +s 10b7980010b79800 3c980-TX Fast Etherlink XL Server Adapter 0 +d 10b79805 3c980-TX 10/100baseTX NIC [Python-T] 0 +s 10b7980510b71201 3c982-TXM 10/100baseTX Dual Port A [Hydra] 0 +s 10b7980510b71202 3c982-TXM 10/100baseTX Dual Port B [Hydra] 0 +s 10b7980510b79805 3c980 10/100baseTX NIC [Python-T] 0 +d 10b79902 3CR990-TX-95 56-bit Typhoon Client 0 +d 10b79903 3CR990-TX-97 168-bit Typhoon Client 0 +d 10b79908 3CR990SVR95 56-bit Typhoon Server 0 +d 10b79909 3CR990SVR97 Typhoon Server 0 +v 10b8 Standard Microsystems Corp [SMC] 0 +d 10b80005 83C170QF 0 +s 10b800051055e000 LANEPIC 0 +s 10b800051055e000 LANEPIC 10/100 [EVB171Q-PCI] 1 +s 10b800051055e002 LANEPIC 0 +s 10b800051055e002 LANEPIC 10/100 [EVB171G-PCI] 1 +s 10b8000510b8a011 EtherPower II 10/100 0 +s 10b8000510b8a014 EtherPower II 10/100 0 +s 10b8000510b8a015 EtherPower II 10/100 0 +s 10b8000510b8a016 EtherPower II 10/100 0 +s 10b8000510b8a017 EtherPower II 10/100 0 +d 10b80006 LANEPIC 0 +s 10b800061055e100 LANEPIC Cardbus Fast Ethernet Adapter 0 +s 10b800061055e102 LANEPIC Cardbus Fast Ethernet Adapter 0 +s 10b800061055e300 LANEPIC Cardbus Fast Ethernet Adapter 0 +s 10b800061055e302 LANEPIC Cardbus Fast Ethernet Adapter 0 +s 10b8000610b8a012 LANEPIC Cardbus Fast Ethernet Adapter 0 +s 10b8000613a28002 LANEPIC Cardbus Fast Ethernet Adapter 0 +s 10b8000613a28006 LANEPIC Cardbus Fast Ethernet Adapter 0 +d 10b81000 FDC 37c665 0 +d 10b81001 FDC 37C922 0 +d 10b8a011 83C170QF 0 +d 10b8b106 SMC34C90 0 +v 10b9 Acer Laboratories Inc. [ALi] 0 +d 10b90111 C-Media CMI8738/C3DX Audio Device (OEM) 0 +s 10b9011110b90111 C-Media CMI8738/C3DX Audio Device (OEM) 0 +d 10b91435 M1435 0 +d 10b91445 M1445 0 +d 10b91449 M1449 0 +d 10b91451 M1451 0 +d 10b91461 M1461 0 +d 10b91489 M1489 0 +d 10b91511 M1511 [Aladdin] 0 +d 10b91512 M1512 [Aladdin] 0 +d 10b91513 M1513 [Aladdin] 0 +d 10b91521 M1521 [Aladdin III] 0 +s 10b9152110b91521 ALI M1521 Aladdin III CPU Bridge 0 +d 10b91523 M1523 0 +s 10b9152310b91523 ALI M1523 ISA Bridge 0 +d 10b91531 M1531 [Aladdin IV] 0 +d 10b91533 M1533 PCI to ISA Bridge [Aladdin IV] 0 +s 10b9153310b91533 ALI M1533 Aladdin IV ISA Bridge 0 +d 10b91541 M1541 0 +s 10b9154110b91541 ALI M1541 Aladdin V/V+ AGP System Controller 0 +d 10b91543 M1543 0 +d 10b91621 M1621 0 +d 10b91631 ALI M1631 PCI North Bridge Aladdin Pro III 0 +d 10b91641 ALI M1641 PCI North Bridge Aladdin Pro IV 0 +d 10b91647 ALI M1647 PCI North Bridge ALiMAGIK_1 1 Used on ASUS A7A266 Motherboards +d 10b93141 M3141 0 +d 10b93143 M3143 0 +d 10b93145 M3145 0 +d 10b93147 M3147 0 +d 10b93149 M3149 0 +d 10b93151 M3151 0 +d 10b93307 M3307 0 +d 10b93309 M3309 0 +d 10b95212 M4803 0 +d 10b95215 MS4803 0 +d 10b95217 M5217H 0 +d 10b95219 M5219 0 +d 10b95225 M5225 0 +d 10b95229 M5229 IDE 0 +d 10b95235 M5225 0 +d 10b95237 M5237 USB 0 +d 10b95243 M5243 0 +d 10b95247 M5247 0 +d 10b95247 M5247 PCI Bridge 1 +d 10b95451 M5451 PCI South Bridge Audio 0 +d 10b97101 M7101 PMU 0 +s 10b9710110b97101 ALI M7101 Power Management Controller 0 +v 10ba Mitsubishi Electric Corp. 0 +d 10ba0301 AccelGraphics AccelECLIPSE 0 +v 10bb Dapha Electronics Corporation 0 +v 10bc Advanced Logic Research 0 +v 10bd Surecom Technology 0 +d 10bd0e34 NE-34 0 +v 10be Tseng Labs International Co. 0 +v 10bf Most Inc 0 +v 10c0 Boca Research Inc. 0 +v 10c1 ICM Co., Ltd. 0 +v 10c2 Auspex Systems Inc. 0 +v 10c3 Samsung Semiconductors, Inc. 0 +d 10c31100 Smartether100 SC1100 LAN Adapter (i82557B) 0 +v 10c4 Award Software International Inc. 0 +v 10c5 Xerox Corporation 0 +v 10c6 Rambus Inc. 0 +v 10c7 Media Vision 0 +v 10c8 Neomagic Corporation 0 +d 10c80001 NM2070 [MagicGraph NM2070] 0 +d 10c80002 NM2090 [MagicGraph 128V] 0 +d 10c80003 NM2093 [MagicGraph 128ZV] 0 +d 10c80004 NM2160 [MagicGraph 128XD] 0 +s 10c80004101400ba MagicGraph 128XD 0 +s 10c8000410251007 MagicGraph 128XD 0 +s 10c8000410280074 MagicGraph 128XD 0 +s 10c8000410280075 MagicGraph 128XD 0 +s 10c800041028007d MagicGraph 128XD 0 +s 10c800041028007e MagicGraph 128XD 0 +s 10c800041033802f MagicGraph 128XD 0 +s 10c80004104d801b MagicGraph 128XD 0 +s 10c80004104d802f MagicGraph 128XD 0 +s 10c80004104d830b MagicGraph 128XD 0 +s 10c8000410ba0e00 MagicGraph 128XD 0 +s 10c8000410c80004 MagicGraph 128XD 0 +s 10c8000410cf1029 MagicGraph 128XD 0 +s 10c8000410f78308 MagicGraph 128XD 0 +s 10c8000410f78309 MagicGraph 128XD 0 +s 10c8000410f7830b MagicGraph 128XD 0 +s 10c8000410f7830d MagicGraph 128XD 0 +s 10c8000410f78312 MagicGraph 128XD 0 +d 10c80005 [MagicMedia 256AV] 0 +d 10c80006 NM2360 [MagicMedia 256ZX] 0 +d 10c80016 NM2380 [MagicMedia 256XL+] 0 +s 10c8001610c80016 MagicMedia 256XL+ 0 +d 10c80025 [MagicMedia 256AV+] 0 +d 10c80083 [MagicGraph 128ZV Plus] 0 +d 10c88005 [MagicMedia 256AV Audio] 0 +s 10c880050e11b0d1 MagicMedia 256AV Audio Device on Discovery 0 +s 10c880050e11b126 MagicMedia 256AV Audio Device on Durango 0 +s 10c88005101400dd MagicMedia 256AV Audio Device on BlackTip Thinkpad 0 +s 10c8800510251003 MagicMedia 256AV Audio Device on TravelMate 720 0 +s 10c880051028008f MagicMedia 256AV Audio Device on Colorado Inspiron 0 +s 10c88005103c0007 MagicMedia 256AV Audio Device on Voyager II 0 +s 10c88005103c0008 MagicMedia 256AV Audio Device on Voyager III 0 +s 10c88005103c000d MagicMedia 256AV Audio Device on Omnibook 900 0 +s 10c8800510c88005 MagicMedia 256AV Audio Device on FireAnt 0 +s 10c88005110a8005 MagicMedia 256AV Audio Device 0 +s 10c8800514c00004 MagicMedia 256AV Audio Device 0 +d 10c88006 NM2360 [MagicMedia 256ZX Audio] 0 +d 10c88016 NM2360 [MagicMedia 256ZX Audio] 1 +v 10c9 Dataexpert Corporation 0 +v 10ca Fujitsu Microelectr., Inc. 0 +v 10cb Omron Corporation 0 +v 10cc Mentor ARC Inc 0 +v 10cd Advanced System Products, Inc 0 +d 10cd1100 ASC1100 0 +d 10cd1200 ASC1200 [(abp940) Fast SCSI-II] 0 +d 10cd1300 ABP940-U / ABP960-U 0 +s 10cd130010cd1310 ASC1300 SCSI Adapter 0 +d 10cd2300 ABP940-UW 0 +d 10cd2500 ABP940-U2W 0 +v 10ce Radius 0 +v 10cf Citicorp TTI 0 +d 10cf2001 mb86605 0 +v 10d0 Fujitsu Limited 0 +v 10d1 FuturePlus Systems Corp. 0 +v 10d2 Molex Incorporated 0 +v 10d3 Jabil Circuit Inc 0 +v 10d4 Hualon Microelectronics 0 +v 10d5 Autologic Inc. 0 +v 10d6 Cetia 0 +v 10d7 BCM Advanced Research 0 +v 10d8 Advanced Peripherals Labs 0 +v 10d9 Macronix, Inc. [MXIC] 0 +d 10d90512 MX98713 0 +d 10d90531 MX987x5 0 +d 10d90531 MX987x5 (ACPI) 1 +s 10d9053111861200 D-Link DFE-540TX ProFAST 10/100 Adapter 1 +d 10d98625 MX86250 0 +d 10d98888 MX86200 0 +v 10da Compaq IPG-Austin 0 +d 10da0508 TC4048 Token Ring 4/16 0 +d 10da3390 Tl3c3x9 0 +v 10db Rohm LSI Systems, Inc. 0 +v 10dc CERN/ECP/EDU 0 +d 10dc0001 STAR/RD24 SCI-PCI (PMC) 0 +d 10dc0002 TAR/RD24 SCI-PCI (PMC) 0 +d 10dc0021 HIPPI destination 0 +d 10dc0022 HIPPI source 0 +d 10dc10dc ATT2C15-3 FPGA 0 +v 10dd Evans & Sutherland 0 +v 10de nVidia Corporation 0 +d 10de0008 EDGE 3D [NV1] 0 +d 10de0009 EDGE 3D [NV1] 0 +d 10de0010 Mutara V08 [NV2] 0 +d 10de0020 Riva TnT [NV04] 0 +s 10de002010430200 V3400 TNT 0 +s 10de002010480c18 Erazor II SGRAM 0 +s 10de002010920550 Viper V550 0 +s 10de002010920552 Viper V550 0 +s 10de002010924804 Viper V550 0 +s 10de002010924808 Viper V550 0 +s 10de002010924810 Viper V550 0 +s 10de002010924812 Viper V550 0 +s 10de002010924815 Viper V550 0 +s 10de002010924820 Viper V550 with TV out 0 +s 10de002010924822 Viper V550 0 +s 10de002010924904 Viper V550 0 +s 10de002010924914 Viper V550 0 +s 10de002010928225 Viper V550 0 +s 10de002010de0020 Riva TNT 0 +s 10de002011021015 Graphics Blaster CT6710 0 +s 10de002011021016 Graphics Blaster RIVA TNT 0 +d 10de0028 Riva TnT2 [NV5] 0 +s 10de002810430200 AGP-V3800 SGRAM 0 +s 10de002810430201 AGP-V3800 SDRAM 0 +s 10de002810430205 PCI-V3800 0 +s 10de002810434000 AGP-V3800PRO 0 +s 10de002810924804 Viper V770 0 +s 10de002810924a00 Viper V770 0 +s 10de002810924a02 Viper V770 Ultra 0 +s 10de002810926a02 Viper V770 Ultra 0 +s 10de002810927a02 Viper V770 Ultra 0 +s 10de002810de0005 RIVA TNT2 Pro 0 +s 10de002811021020 3D Blaster RIVA TNT2 0 +s 10de002811021026 3D Blaster RIVA TNT2 Digital 0 +s 10de002814af5810 Maxi Gamer Xentor 0 +d 10de0029 Riva TnT2 Ultra [NV5] 0 +s 10de002910430200 AGP-V3800 Deluxe 0 +s 10de002910430201 AGP-V3800 Ultra SDRAM 0 +s 10de002910430205 PCI-V3800 Ultra 0 +s 10de002911021021 3D Blaster RIVA TNT2 Ultra 0 +s 10de002911021029 3D Blaster RIVA TNT2 Ultra 0 +s 10de00291102102f 3D Blaster RIVA TNT2 Ultra 0 +s 10de002914af5820 Maxi Gamer Xentor 32 0 +d 10de002a Riva TnT2 [NV5] 0 +d 10de002b Riva TnT2 [NV5] 0 +d 10de002c Vanta [NV6] 0 +s 10de002c10430200 AGP-V3800 Combat SDRAM 0 +s 10de002c10430201 AGP-V3800 Combat 0 +s 10de002c10926820 Viper V730 0 +s 10de002c11021031 CT6938 VANTA 8MB 0 +s 10de002c11021034 CT6894 VANTA 16MB 0 +s 10de002c14af5008 Maxi Gamer Phoenix 2 0 +d 10de002d Vanta [NV6] 0 +s 10de002d10430200 AGP-V3800M 0 +s 10de002d10430201 AGP-V3800M 0 +s 10de002d11021023 CT6892 RIVA TNT2 Value 0 +s 10de002d11021024 CT6932 RIVA TNT2 Value 32Mb 0 +s 10de002d1102102c CT6931 RIVA TNT2 Value (Jumper) 0 +s 10de002d14628808 MSI-8808 0 +d 10de002e Vanta [NV6] 0 +d 10de002f Vanta [NV6] 0 +d 10de00a0 Riva TNT2 0 +s 10de00a014af5810 Maxi Gamer Xentor 0 +d 10de0100 GeForce 256 0 +s 10de010010430200 AGP-V6600 SGRAM 0 +s 10de010010430201 AGP-V6600 SDRAM 0 +s 10de010010434008 AGP-V6600 SGRAM 0 +s 10de010010434009 AGP-V6600 SDRAM 0 +s 10de01001102102d CT6941 GeForce 256 0 +s 10de010014af5022 3D Prophet SE 1 +d 10de0101 GeForce 256 DDR 0 +s 10de010110430202 AGP-V6800 DDR 0 +s 10de01011043400a AGP-V6800 DDR SGRAM 0 +s 10de01011043400b AGP-V6800 DDR SDRAM 0 +s 10de01011102102e CT6971 GeForce 256 DDR 0 +s 10de010114af5021 3D Prophet DDR-DVI 0 +d 10de0103 Quadro (GeForce 256 GL) 0 +d 10de0110 NV11 (GeForce2 MX) 0 +s 10de011010434015 AGP-7100 Pro with TV output 0 +s 10de011010434031 V7100 Pro with TV output 1 +d 10de0111 NV11 (GeForce2 MX DDR) 0 +d 10de0112 GeForce2 Go 0 +d 10de0113 NV11 (GeForce2 MXR) 0 +d 10de0150 NV15 (GeForce2 Pro) 0 +s 10de0150107d2840 WinFast GeForce2 GTS with TV output 0 +s 10de015014628831 Creative GeForce2 Pro 0 +d 10de0151 NV15 DDR (GeForce2 GTS) 0 +d 10de0152 NV15 Bladerunner (GeForce2 Ultra) 0 +d 10de0153 NV15 GL (Quadro2 Pro) 0 +d 10de0200 NV20 (GeForce3) 0 +s 10de02001043402f AGP-V8200 DDR 0 +d 10de0203 Quadro DCC 0 +v 10df Emulex Corporation 0 +d 10df10df Light Pulse Fibre Channel Adapter 0 +d 10df1ae5 LP6000 Fibre Channel Host Adapter 0 +d 10dff700 LP7000 Fibre Channel Host Adapter 0 +v 10e0 Integrated Micro Solutions Inc. 0 +d 10e05026 IMS5026/27/28 0 +d 10e05027 IMS5027 0 +d 10e05028 IMS5028 0 +d 10e08849 IMS8849 0 +d 10e08853 IMS8853 0 +d 10e09128 IMS9129 [Twin turbo 128] 0 +v 10e1 Tekram Technology Co.,Ltd. 0 +d 10e10391 TRM-S1040 0 +s 10e1039110e10391 DC-315U SCSI-3 Host Adapter 0 +d 10e1690c DC-690c 0 +d 10e1dc29 DC-290 0 +v 10e2 Aptix Corporation 0 +v 10e3 Tundra Semiconductor Corp. 0 +d 10e30000 CA91C042 [Universe] 0 +d 10e30860 CA91C860 [QSpan] 0 +v 10e4 Tandem Computers 0 +v 10e5 Micro Industries Corporation 0 +v 10e6 Gainbery Computer Products Inc. 0 +v 10e7 Vadem 0 +v 10e8 Applied Micro Circuits Corp. 0 +d 10e82011 Q-Motion Video Capture/Edit board 0 +d 10e84750 S5930 [Matchmaker] 0 +d 10e85920 S5920 0 +d 10e88043 LANai4.x [Myrinet LANai interface chip] 0 +d 10e88062 S5933_PARASTATION 0 +d 10e8807d S5933 [Matchmaker] 0 +d 10e88088 Kongsberg Spacetec Format Synchronizer 0 +d 10e88089 Kongsberg Spacetec Serial Output Board 0 +d 10e8809c S5933_HEPC3 0 +d 10e880d7 PCI-9112 0 +d 10e880d9 PCI-9118 0 +d 10e880da PCI-9812 0 +d 10e8811a PCI-IEEE1355-DS-DE Interface 0 +d 10e88170 S5933 [Matchmaker] (Chipset Development Tool) 0 +v 10e9 Alps Electric Co., Ltd. 0 +v 10ea Intergraphics Systems 0 +d 10ea1680 IGA-1680 0 +d 10ea1682 IGA-1682 0 +d 10ea1683 IGA-1683 0 +d 10ea2000 CyberPro 2000 0 +d 10ea2010 CyberPro 2000A 0 +d 10ea5000 CyberPro 5000 0 +d 10ea5050 CyberPro 5050 0 +v 10eb Artists Graphics 0 +d 10eb0101 3GA 0 +d 10eb8111 Twist3 Frame Grabber 0 +v 10ec Realtek Semiconductor Co., Ltd. 0 +v 10ec 1 +d 10ec1274 1 +d 10ec4724 1 +d 10ec8029 RTL-8029(AS) 0 +s 10ec802910b82011 EZ-Card 0 +s 10ec802910ec8029 RT8029(AS) 0 +s 10ec802911131208 EN1208 0 +s 10ec802911860300 DE-528 0 +s 10ec802912592400 AT-2400 0 +d 10ec8129 RTL-8129 0 +s 10ec812910ec8129 RT8129 Fast Ethernet Adapter 0 +d 10ec8138 RT8139 (B/C) Cardbus Fast Ethernet Adapter 0 +s 10ec813810ec8138 RT8139 (B/C) Fast Ethernet Adapter 0 +d 10ec8139 RTL-8139 0 +d 10ec8139 RTL-8139/8139C 1 +s 10ec813910258920 ALN-325 0 +s 10ec813910258921 ALN-325 0 +s 10ec813910bd0320 EP-320X-R 0 +s 10ec813910ec8139 RT8139 0 +s 10ec813911861300 DFE-538TX 0 +s 10ec813911861320 SN5200 0 +s 10ec813912592500 AT-2500TX 0 +s 10ec81391429d010 ND010 0 +s 10ec813914329130 EN-9130TX 0 +s 10ec813914368139 RT8139 0 +s 10ec8139146c1439 FE-1439TX 0 +s 10ec813914896001 GF100TXRII 0 +s 10ec813914896002 GF100TXRA 0 +s 10ec8139149c139a LFE-8139ATX 0 +s 10ec8139149c8139 LFE-8139TX 0 +s 10ec813926460001 EtheRx 0 +s 10ec81398e2e7000 KF-230TX 0 +s 10ec81398e2e7100 KF-230TX/2 0 +s 10ec8139a0a00007 ALN-325C 0 +v 10ed Ascii Corporation 0 +d 10ed7310 V7310 0 +v 10ee Xilinx, Inc. 0 +d 10ee3fc0 RME Digi96 0 +d 10ee3fc1 RME Digi96/8 0 +d 10ee3fc2 RME Digi96/8 Pro 0 +d 10ee3fc3 RME Digi96/8 Pad 0 +v 10ef Racore Computer Products, Inc. 0 +d 10ef8154 M815x Token Ring Adapter 0 +v 10f0 Peritek Corporation 0 +v 10f1 Tyan Computer 0 +v 10f2 Achme Computer, Inc. 0 +v 10f3 Alaris, Inc. 0 +v 10f4 S-MOS Systems, Inc. 0 +v 10f5 NKK Corporation 0 +d 10f5a001 NDR4000 [NR4600 Bridge] 0 +v 10f6 Creative Electronic Systems SA 0 +v 10f7 Matsushita Electric Industrial Co., Ltd. 0 +v 10f8 Altos India Ltd 0 +v 10f9 PC Direct 0 +v 10fa Truevision 0 +d 10fa000c TARGA 1000 0 +v 10fb Thesys Gesellschaft für Mikroelektronik mbH 0 +v 10fc I-O Data Device, Inc. 0 +d 10fc0003 Cardbus IDE Controller 1 What's in the cardbus end of a Sony ACR-A01 card, comes with newer Vaio CD-RW drives +v 10fd Soyo Computer, Inc 0 +v 10fe Fast Multimedia AG 0 +v 10ff NCube 0 +v 1100 Jazz Multimedia 0 +v 1101 Initio Corporation 0 +d 11011060 INI-A100U2W 0 +d 11019100 INI-9100/9100W 0 +d 11019400 INI-940 0 +d 11019401 INI-950 0 +d 11019500 360P 0 +v 1102 Creative Labs 0 +d 11020002 SB Live! EMU10k1 0 +s 1102000211020020 CT4850 SBLive! Value 0 +s 1102000211020021 CT4620 SBLive! 0 +s 110200021102002f SBLive! mainboard implementation 0 +s 1102000211024001 E-mu APS 0 +s 1102000211028022 CT4780 SBLive! Value 0 +s 1102000211028023 CT4790 SoundBlaster PCI512 0 +s 1102000211028024 CT4760 SBLive! 0 +s 1102000211028025 SBLive! Mainboard Implementation 0 +s 1102000211028026 CT4830 SBLive! Value 0 +s 1102000211028027 CT4832 SBLive! Value 0 +s 1102000211028031 CT4831 SBLive! Value 0 +s 1102000211028040 CT4760 SBLive! 0 +s 1102000211028051 CT4850 SBLive! Value 0 +d 11020004 SB Audigy 0 +d 11024001 SB Audigy FireWire Port 0 +d 11027002 SB Live! 0 +d 11027002 SB Live! MIDI/Game Port 1 +s 1102700211020020 Gameport Joystick 0 +d 11027003 SB Audigy MIDI/Game port 0 +d 11028938 ES1371 0 +v 1103 Triones Technologies, Inc. 0 +d 11030003 HPT343 0 +d 11030004 HPT366 / HPT370 0 +s 1103000411030005 HPT370 UDMA100 0 +d 11030005 HPT370 1 Not HPT370A, It's HPT370. I don't know what ID HPT370A has. +v 1104 RasterOps Corp. 0 +v 1105 Sigma Designs, Inc. 0 +d 11058300 REALmagic Hollywood Plus DVD Decoder 0 +d 11058400 EM840x REALmagic DVD/MPEG-2 Audio/Video Decoder 0 +v 1106 VIA Technologies, Inc. 0 +d 11060305 VT8363/8365 [KT133/KM133] 0 +s 1106030510438042 ATV133/A7V133-C 1 +s 11060305147ba401 KT7/KT7-RAID/KT7A/KT7A-RAID 1 +d 11060391 VT8371 [KX133] 0 +d 11060501 VT8501 [Apollo MVP4] 0 +d 11060505 VT82C505 0 +d 11060561 VT82C561 0 +d 11060571 Bus Master IDE 0 +d 11060576 VT82C576 3V [Apollo Master] 0 +d 11060585 VT82C585VP [Apollo VP1/VPX] 0 +d 11060586 VT82C586/A/B PCI-to-ISA [Apollo VP] 0 +s 1106058611060000 MVP3 ISA Bridge 0 +d 11060595 VT82C595 [Apollo VP2] 0 +d 11060596 VT82C596 ISA [Mobile South] 0 +s 1106059611060000 VT82C596/A/B PCI to ISA Bridge 0 +s 1106059614580596 VT82C596/A/B PCI to ISA Bridge 0 +d 11060597 VT82C597 [Apollo VP3] 0 +d 11060598 VT82C598 [Apollo MVP3] 0 +d 11060601 VT8601 [Apollo ProMedia] 0 +d 11060605 VT8605 [ProSavage PM133] 0 +d 11060680 VT82C680 [Apollo P6] 0 +d 11060686 VT82C686 [Apollo Super South] 0 +s 1106068610438042 ATV133/A7V133-C 1 +s 1106068611060000 VT82C686/A PCI to ISA Bridge 0 +s 1106068611060686 VT82C686/A PCI to ISA Bridge 0 +d 11060691 VT82C693A/694x [Apollo PRO133x] 0 +s 1106069114580691 VT82C691 Apollo Pro System Controller 0 +d 11060693 VT82C693 [Apollo Pro Plus] 0 +d 11060698 VT82C693A [Apollo Pro133 AGP] 0 +d 11060926 VT82C926 [Amazon] 0 +d 11061000 VT82C570MV 0 +d 11061106 VT82C570MV 0 +d 11061571 VT82C416MV 0 +d 11061595 VT82C595/97 [Apollo VP2/97] 0 +d 11063038 UHCI USB 0 +s 1106303809251234 MVP3 USB Controller 1 +s 1106303809251234 UHCI USB Controller 1 Not just MVP3, also found on via82c68a southbridge. (GigaByte board) +s 1106303812340925 MVP3 USB Controller 0 +s 1106303812340925 1 I don't think this ever existed. But I may be wrong. +d 11063040 VT82C586B ACPI 0 +d 11063043 VT86C100A [Rhine 10/100] 0 +d 11063043 VT3043 [Rhine] 1 +s 1106304310bd0000 VT86C100A Fast Ethernet Adapter 0 +s 1106304311060100 VT86C100A Fast Ethernet Adapter 0 +s 1106304311861400 DFE-530TX 0 +s 1106304311861400 DFE-530TX rev A 1 +d 11063044 OHCI Compliant IEEE 1394 Host Controller 0 +d 11063050 VT82C596 Power Management 0 +d 11063051 VT82C596 Power Management 0 +d 11063057 VT82C686 [Apollo Super ACPI] 0 +s 1106305710438042 ATV133/A7V133-C 1 +d 11063058 AC97 Audio Controller 0 +d 11063058 VT82C686 AC97 Audio Controller 1 To distinguish from other AC97 Audio Controllers +s 1106305814587600 Onboard Audio 1 Found on a GigaByte board. +s 1106305814623091 MS-6309 Onboard Audio 0 +d 11063059 AC97 Audio Controller 0 +d 11063059 VT8233 AC97 Audio Controller 1 To distinguish from the 3058 entry for device that is incompatible, ALSA has separate driver specific to this chip +d 11063065 VT6102 [Rhine-II] 1 +d 11063065 Ethernet Controller 0 +s 1106306511861401 DFE-530TX rev B 1 +d 11063068 AC97 Modem Controller 0 +d 11063074 VT8233 PCI to ISA Bridge 0 +d 11063091 VT8633 [Apollo Pro266] 0 +d 11063099 VT8367 [KT266] 0 +d 11063109 VT8233C PCI to ISA Bridge 0 +d 11063128 VT8233 PCI to PCI Bridge 1 I have recently upgraded my machine to a new motherboard using a P4 chip and the Via 8133 chipset. All PCI resouces were identif +d 11065030 VT82C596 ACPI [Apollo PRO] 0 +d 11066100 VT85C100A [Rhine II] 0 +d 11066100 VT86C100A [Rhine-II] 1 +d 11068231 VT8231 [PCI-to-ISA Bridge] 0 +d 11068235 VT8235 Power Management 0 +d 11068305 VT8363/8365 [KT133/KM133 AGP] 0 +d 11068391 VT8371 [KX133 AGP] 0 +d 11068501 VT8501 [Apollo MVP4 AGP] 0 +d 11068596 VT82C596 [Apollo PRO AGP] 0 +d 11068597 VT82C597 [Apollo VP3 AGP] 0 +d 11068598 VT82C598/694x [Apollo MVP3/Pro133x AGP] 0 +d 11068601 VT8601 [Apollo ProMedia AGP] 0 +d 11068601 VIA 8601 Chipset 1 Need a video driver for Linux. +d 11068605 VT8605 [PM133 AGP] 0 +d 11068691 VT82C691 [Apollo Pro] 0 +d 1106b091 VT8633 [Apollo Pro266 AGP] 0 +d 1106b099 VT8367 [KT266 AGP] 0 +v 1107 Stratus Computers 0 +d 11070576 VIA VT82C570MV [Apollo] (Wrong vendor ID!) 0 +v 1108 Proteon, Inc. 0 +d 11080100 p1690plus_AA 0 +d 11080101 p1690plus_AB 0 +d 11080105 P1690Plus 0 +d 11080108 P1690Plus 0 +d 11080138 P1690Plus 0 +d 11080139 P1690Plus 0 +d 1108013c P1690Plus 0 +d 1108013d P1690Plus 0 +v 1109 Cogent Data Technologies, Inc. 0 +d 11091400 EM110TX [EX110TX] 0 +v 110a Siemens Nixdorf AG 0 +d 110a0002 Pirahna 2-port 0 +d 110a0005 Tulip controller, power management, switch extender 0 +d 110a2102 DSCC4 WAN adapter 0 +d 110a4942 FPGA I-Bus Tracer for MBD 0 +d 110a6020 D1180 U2W-SCSI controller (SYM 53C895A chipset) 1 +d 110a6120 SZB6120 0 +v 110b Chromatic Research Inc. 0 +d 110b0001 Mpact Media Processor 0 +d 110b0004 Mpact 2 0 +v 110c Mini-Max Technology, Inc. 0 +v 110d Znyx Advanced Systems 0 +v 110e CPU Technology 0 +v 110f Ross Technology 0 +v 1110 Powerhouse Systems 0 +d 11106037 Firepower Powerized SMP I/O ASIC 0 +d 11106073 Firepower Powerized SMP I/O ASIC 0 +v 1111 Santa Cruz Operation 0 +v 1112 RNS - Div. of Meret Communications Inc 0 DJ: Some people say that 0x1112 is Rockwell International +d 11122200 FDDI Adapter 0 +d 11122300 Fast Ethernet Adapter 0 +d 11122340 4 Port Fast Ethernet Adapter 0 +d 11122400 ATM Adapter 0 +v 1113 Accton Technology Corporation 0 +d 11131211 SMC2-1211TX 0 +s 11131211103c1207 EN-1207D Fast Ethernet Adapter 0 +s 1113121111131211 EN-1207D Fast Ethernet Adapter 0 +d 11131216 EN-1216 Ethernet Adapter 0 +d 11131217 EN-1217 Ethernet Adapter 0 +d 11135105 10Mbps Network card 0 +d 11139211 EN-1207D Fast Ethernet Adapter 0 +s 1113921111139211 EN-1207D Fast Ethernet Adapter 0 +v 1114 Atmel Corporation 0 +v 1115 3D Labs 0 +v 1116 Data Translation 0 +d 11160022 DT3001 0 +d 11160023 DT3002 0 +d 11160024 DT3003 0 +d 11160025 DT3004 0 +d 11160026 DT3005 0 +d 11160027 DT3001-PGL 0 +d 11160028 DT3003-PGL 0 +v 1117 Datacube, Inc 0 +d 11179500 Max-1C SVGA card 0 +d 11179501 Max-1C image processing 0 +v 1118 Berg Electronics 0 +v 1119 ICP Vortex Computersysteme GmbH 0 +d 11190000 GDT 6000/6020/6050 0 +d 11190001 GDT 6000B/6010 0 +d 11190002 GDT 6110/6510 0 +d 11190003 GDT 6120/6520 0 +d 11190004 GDT 6530 0 +d 11190005 GDT 6550 0 +d 11190006 GDT 6x17 0 +d 11190007 GDT 6x27 0 +d 11190008 GDT 6537 0 +d 11190009 GDT 6557 0 +d 1119000a GDT 6115/6515 0 +d 1119000b GDT 6125/6525 0 +d 1119000c GDT 6535 0 +d 1119000d GDT 6555 0 +d 11190100 GDT 6117RP/6517RP 0 +d 11190101 GDT 6127RP/6527RP 0 +d 11190102 GDT 6537RP 0 +d 11190103 GDT 6557RP 0 +d 11190104 GDT 6111RP/6511RP 0 +d 11190105 GDT 6121RP/6521RP 0 +d 11190110 GDT 6117RD/6517RD 0 +d 11190111 GDT 6127RD/6527RD 0 +d 11190112 GDT 6537RD 0 +d 11190113 GDT 6557RD 0 +d 11190114 GDT 6111RD/6511RD 0 +d 11190115 GDT 6121RD/6521RD 0 +d 11190118 GDT 6118RD/6518RD/6618RD 0 +d 11190119 GDT 6128RD/6528RD/6628RD 0 +d 1119011a GDT 6538RD/6638RD 0 +d 1119011b GDT 6558RD/6658RD 0 +d 11190120 GDT 6117RP2/6517RP2 0 +d 11190121 GDT 6127RP2/6527RP2 0 +d 11190122 GDT 6537RP2 0 +d 11190123 GDT 6557RP2 0 +d 11190124 GDT 6111RP2/6511RP2 0 +d 11190125 GDT 6121RP2/6521RP2 0 +d 11190136 GDT 6113RS/6513RS 0 +d 11190137 GDT 6123RS/6523RS 0 +d 11190138 GDT 6118RS/6518RS/6618RS 0 +d 11190139 GDT 6128RS/6528RS/6628RS 0 +d 1119013a GDT 6538RS/6638RS 0 +d 1119013b GDT 6558RS/6658RS 0 +d 1119013c GDT 6533RS/6633RS 0 +d 1119013d GDT 6543RS/6643RS 0 +d 1119013e GDT 6553RS/6653RS 0 +d 1119013f GDT 6563RS/6663RS 0 +d 11190166 GDT 7113RN/7513RN/7613RN 0 +d 11190167 GDT 7123RN/7523RN/7623RN 0 +d 11190168 GDT 7118RN/7518RN/7518RN 0 +d 11190169 GDT 7128RN/7528RN/7628RN 0 +d 1119016a GDT 7538RN/7638RN 0 +d 1119016b GDT 7558RN/7658RN 0 +d 1119016c GDT 7533RN/7633RN 0 +d 1119016d GDT 7543RN/7643RN 0 +d 1119016e GDT 7553RN/7653RN 0 +d 1119016f GDT 7563RN/7663RN 0 +d 111901d6 GDT 4x13RZ 0 +d 111901d7 GDT 4x23RZ 0 +d 111901f6 GDT 8x13RZ 0 +d 111901f7 GDT 8x23RZ 0 +d 111901fc GDT 8x33RZ 0 +d 111901fd GDT 8x43RZ 0 +d 111901fe GDT 8x53RZ 0 +d 111901ff GDT 8x63RZ 0 +d 11190210 GDT 6519RD/6619RD 0 +d 11190211 GDT 6529RD/6629RD 0 +d 11190260 GDT 7519RN/7619RN 0 +d 11190261 GDT 7529RN/7629RN 0 +d 11190300 GDT Raid Controller 0 +v 111a Efficient Networks, Inc 0 +d 111a0000 155P-MF1 (FPGA) 0 +d 111a0002 155P-MF1 (ASIC) 0 +d 111a0003 ENI-25P ATM 0 +s 111a0003111a0000 ENI-25p Miniport ATM Adapter 0 +d 111a0005 SpeedStream (LANAI) 0 +s 111a0005111a0001 ENI-3010 ATM 0 +s 111a0005111a0009 ENI-3060 ADSL (VPI=0) 0 +s 111a0005111a0101 ENI-3010 ATM 0 +s 111a0005111a0109 ENI-3060CO ADSL (VPI=0) 0 +s 111a0005111a0809 ENI-3060 ADSL (VPI=0 or 8) 0 +s 111a0005111a0909 ENI-3060CO ADSL (VPI=0 or 8) 0 +s 111a0005111a0a09 ENI-3060 ADSL (VPI=<0..15>) 0 +d 111a0007 SpeedStream ADSL 0 +s 111a0007111a1001 ENI-3061 ADSL [ASIC] 0 +v 111b Teledyne Electronic Systems 0 +v 111c Tricord Systems Inc. 0 +d 111c0001 Powerbis Bridge 0 +v 111d Integrated Device Tech 0 +d 111d0001 IDT77211 ATM Adapter 0 +d 111d0003 IDT77252 ATM network controller 0 +v 111e Eldec 0 +v 111f Precision Digital Images 0 +d 111f4a47 Precision MX Video engine interface 0 +d 111f5243 Frame capture bus interface 0 +v 1120 EMC Corporation 0 +v 1121 Zilog 0 +v 1122 Multi-tech Systems, Inc. 0 +v 1123 Excellent Design, Inc. 0 +v 1124 Leutron Vision AG 0 +v 1125 Eurocore 0 +v 1126 Vigra 0 +v 1127 FORE Systems Inc 0 +d 11270200 ForeRunner PCA-200 ATM 0 +d 11270210 PCA-200PC 0 +d 11270250 ATM 0 +d 11270300 PCA-200E 0 +d 11270310 ATM 0 +d 11270400 ForeRunnerHE ATM Adapter 0 +v 1129 Firmworks 0 +v 112a Hermes Electronics Company, Ltd. 0 +v 112b Linotype - Hell AG 0 +v 112c Zenith Data Systems 0 +v 112d Ravicad 0 +v 112e Infomedia Microelectronics Inc. 0 +v 112f Imaging Technology Inc 0 +d 112f0000 MVC IC-PCI 0 +d 112f0001 MVC IM-PCI Video frame grabber/processor 0 +v 1130 Computervision 0 +v 1131 Philips Semiconductors 0 +d 11317145 SAA7145 0 +d 11317146 SAA7146 0 +s 11317146114b2003 DVRaptor Video Edit/Capture Card 0 +s 1131714611bd0006 DV500 Overlay 0 +s 1131714611bd000a DV500 Overlay 0 +v 1132 Mitel Corp. 0 +v 1133 Eicon Technology Corporation 0 +d 11337901 EiconCard S90 0 +d 11337902 EiconCard S90 0 +d 11337911 EiconCard S91 0 +d 11337912 EiconCard S91 0 +d 11337941 EiconCard S94 0 +d 11337942 EiconCard S94 0 +d 11337943 EiconCard S94 0 +d 11337944 EiconCard S94 0 +d 1133b921 EiconCard P92 0 +d 1133b922 EiconCard P92 0 +d 1133b923 EiconCard P92 0 +d 1133e001 DIVA 20PRO 0 +s 1133e0011133e001 DIVA Pro 2.0 S/T 0 +d 1133e002 DIVA 20 0 +s 1133e0021133e002 DIVA 2.0 S/T 0 +d 1133e003 DIVA 20PRO_U 0 +s 1133e0031133e003 DIVA Pro 2.0 U 0 +d 1133e004 DIVA 20_U 0 +s 1133e0041133e004 DIVA 2.0 U 0 +d 1133e005 DIVA LOW 0 +s 1133e0051133e005 DIVA 2.01 S/T 0 +d 1133e010 DIVA Server BRI-2M 0 +s 1133e0101133e010 DIVA Server BRI-2M 0 +d 1133e012 DIVA Server BRI-8M 0 +s 1133e0121133e012 DIVA Server BRI-8M 0 +d 1133e014 DIVA Server PRI-30M 0 +s 1133e0141133e014 DIVA Server PRI-30M 0 +v 1134 Mercury Computer Systems 0 +d 11340001 Raceway Bridge 0 +v 1135 Fuji Xerox Co Ltd 0 +d 11350001 Printer controller 0 +v 1136 Momentum Data Systems 0 +v 1137 Cisco Systems Inc 0 +v 1138 Ziatech Corporation 0 +d 11388905 8905 [STD 32 Bridge] 0 +v 1139 Dynamic Pictures, Inc 0 +d 11390001 VGA Compatable 3D Graphics 0 +v 113a FWB Inc 0 +v 113b Network Computing Devices 0 +v 113c Cyclone Microsystems, Inc. 0 +d 113c0000 PCI-9060 i960 Bridge 0 +d 113c0001 PCI-SDK [PCI i960 Evaluation Platform] 0 +d 113c0911 PCI-911 [i960Jx-based Intelligent I/O Controller] 0 +d 113c0912 PCI-912 [i960CF-based Intelligent I/O Controller] 0 +d 113c0913 PCI-913 0 +d 113c0914 PCI-914 [I/O Controller w/ secondary PCI bus] 0 +v 113d Leading Edge Products Inc 0 +v 113e Sanyo Electric Co - Computer Engineering Dept 0 +v 113f Equinox Systems, Inc. 0 +d 113f0808 SST-64P Adapter 0 +d 113f1010 SST-128P Adapter 0 +d 113f80c0 SST-16P DB Adapter 0 +d 113f80c4 SST-16P RJ Adapter 0 +d 113f80c8 SST-16P Adapter 0 +d 113f8888 SST-4P Adapter 0 +d 113f9090 SST-8P Adapter 0 +v 1140 Intervoice Inc 0 +v 1141 Crest Microsystem Inc 0 +v 1142 Alliance Semiconductor Corporation 0 +d 11423210 AP6410 0 +d 11426422 ProVideo 6422 0 +d 11426424 ProVideo 6424 0 +d 11426425 ProMotion AT25 0 +d 1142643d ProMotion AT3D 0 +v 1143 NetPower, Inc 0 +v 1144 Cincinnati Milacron 0 +d 11440001 Noservo controller 0 +v 1145 Workbit Corporation 0 +v 1146 Force Computers 0 +v 1147 Interface Corp 0 +v 1148 Syskonnect (Schneider & Koch) 0 +d 11484000 FDDI Adapter 0 +s 114840000e11b03b Netelligent 100 FDDI DAS Fibre SC 0 +s 114840000e11b03c Netelligent 100 FDDI SAS Fibre SC 0 +s 114840000e11b03d Netelligent 100 FDDI DAS UTP 0 +s 114840000e11b03e Netelligent 100 FDDI SAS UTP 0 +s 114840000e11b03f Netelligent 100 FDDI SAS Fibre MIC 0 +s 1148400011485521 FDDI SK-5521 (SK-NET FDDI-UP) 0 +s 1148400011485522 FDDI SK-5522 (SK-NET FDDI-UP DAS) 0 +s 1148400011485541 FDDI SK-5541 (SK-NET FDDI-FP) 0 +s 1148400011485543 FDDI SK-5543 (SK-NET FDDI-LP) 0 +s 1148400011485544 FDDI SK-5544 (SK-NET FDDI-LP DAS) 0 +s 1148400011485821 FDDI SK-5821 (SK-NET FDDI-UP64) 0 +s 1148400011485822 FDDI SK-5822 (SK-NET FDDI-UP64 DAS) 0 +s 1148400011485841 FDDI SK-5841 (SK-NET FDDI-FP64) 0 +s 1148400011485843 FDDI SK-5843 (SK-NET FDDI-LP64) 0 +s 1148400011485844 FDDI SK-5844 (SK-NET FDDI-LP64 DAS) 0 +d 11484200 Token Ring adapter 0 +d 11484300 Gigabit Ethernet 0 +s 1148430011489821 SK-9821 (1000Base-T single link) 0 +s 1148430011489822 SK-9822 (1000Base-T dual link) 0 +s 1148430011489841 SK-9841 (1000Base-LX single link) 0 +s 1148430011489842 SK-9842 (1000Base-LX dual link) 0 +s 1148430011489843 SK-9843 (1000Base-SX single link) 0 +s 1148430011489844 SK-9844 (1000Base-SX dual link) 0 +s 1148430011489861 SK-9861 (1000Base-SX VF45 single link) 0 +s 1148430011489862 SK-9862 (1000Base-SX VF45 dual link) 0 +v 1149 Win System Corporation 0 +v 114a VMIC 0 +d 114a5579 VMIPCI-5579 1 Reflective Memory Card +d 114a7587 VMIVME-7587 0 +v 114b Canopus Co., Ltd 0 +v 114c Annabooks 0 +v 114d IC Corporation 0 +v 114e Nikon Systems Inc 0 +v 114f Digi International 0 +d 114f0002 AccelePort EPC 0 +d 114f0003 RightSwitch SE-6 0 +d 114f0004 AccelePort Xem 0 +d 114f0005 AccelePort Xr 0 +d 114f0006 AccelePort Xr,C/X 0 +d 114f0009 AccelePort Xr/J 0 +d 114f000a AccelePort EPC/J 0 +d 114f000c DataFirePRIme T1 (1-port) 0 +d 114f000d SyncPort 2-Port (x.25/FR) 0 +d 114f0011 AccelePort 8r EIA-232 (IBM) 0 +d 114f0012 AccelePort 8r EIA-422 0 +d 114f0013 AccelePort Xr 0 +d 114f0014 AccelePort 8r EIA-422 0 +d 114f0015 AccelePort Xem 0 +d 114f0016 AccelePort EPC/X 0 +d 114f0017 AccelePort C/X 0 +d 114f001a DataFirePRIme E1 (1-port) 0 +d 114f001b AccelePort C/X (IBM) 0 +d 114f001d DataFire RAS T1/E1/PRI 0 +s 114f001d114f0050 DataFire RAS E1 Adapter 0 +s 114f001d114f0051 DataFire RAS Dual E1 Adapter 0 +s 114f001d114f0052 DataFire RAS T1 Adapter 0 +s 114f001d114f0053 DataFire RAS Dual T1 Adapter 0 +d 114f0023 AccelePort RAS 0 +d 114f0024 DataFire RAS B4 ST/U 0 +s 114f0024114f0030 DataFire RAS BRI U Adapter 0 +s 114f0024114f0031 DataFire RAS BRI S/T Adapter 0 +d 114f0026 AccelePort 4r 920 0 +d 114f0027 AccelePort Xr 920 0 +d 114f0034 AccelePort 2r 920 0 +d 114f0035 DataFire DSP T1/E1/PRI cPCI 0 +d 114f0040 AccelePort Xp 1 +d 114f0042 AccelePort 2p PCI 1 This (0042) is a subdevice of 0040, and is a 2 port model of the Xp family. +d 114f0070 Datafire Micro V IOM2 (Europe) 1 +d 114f0071 Datafire Micro V (Europe) 1 +d 114f0072 Datfire Micro V IOM2 (North America) 1 +d 114f0072 Datafire Micro V IOM2 (North America) 1 +d 114f0072 1 +d 114f0073 Datafire Micro V (North America) 1 +d 114f6001 Avanstar 0 +v 1150 Thinking Machines Corp 0 +v 1151 JAE Electronics Inc. 0 +v 1152 Megatek 0 +v 1153 Land Win Electronic Corp 0 +v 1154 Melco Inc 0 +v 1155 Pine Technology Ltd 0 +v 1156 Periscope Engineering 0 +v 1157 Avsys Corporation 0 +v 1158 Voarx R & D Inc 0 +d 11583011 Tokenet/vg 1001/10m anylan 0 +d 11589050 Lanfleet/Truevalue 0 +d 11589051 Lanfleet/Truevalue 0 +v 1159 Mutech Corp 0 +d 11590001 MV-1000 0 +v 115a Harlequin Ltd 0 +v 115b Parallax Graphics 0 +v 115c Photron Ltd. 0 +v 115d Xircom 0 +d 115d0003 Cardbus Ethernet 10/100 0 +s 115d000310140181 10/100 EtherJet Cardbus Adapter 0 +s 115d000310141181 10/100 EtherJet Cardbus Adapter 0 +s 115d000310148181 10/100 EtherJet Cardbus Adapter 1 +s 115d000310149181 10/100 EtherJet Cardbus Adapter 1 +s 115d0003115d0181 Cardbus Ethernet 10/100 0 +s 115d0003115d0181 Cardbus Ethernet II 10/100 1 +s 115d0003115d1181 Cardbus Ethernet 10/100 0 +s 115d0003115d1181 Cardbus Ethernet 10/100 56k Modem 1 +s 115d000311790181 10 100 CardBus Ethernet 1 +s 115d000380868181 EtherExpress PRO/100 Mobile CardBus 32 Adapter 0 +s 115d000380869181 EtherExpress PRO/100 Mobile CardBus 32 Adapter 0 +d 115d0005 Cardbus Ethernet 10/100 0 +s 115d000510140182 10/100 EtherJet Cardbus Adapter 0 +s 115d000510141182 10/100 EtherJet Cardbus Adapter 0 +s 115d0005115d0182 Cardbus Ethernet 10/100 0 +s 115d0005115d1182 Cardbus Ethernet 10/100 0 +d 115d0007 Cardbus Ethernet 10/100 0 +s 115d000710140182 10/100 EtherJet Cardbus Adapter 0 +s 115d000710141182 10/100 EtherJet Cardbus Adapter 0 +s 115d0007115d0182 Cardbus Ethernet 10/100 0 +s 115d0007115d1182 Cardbus Ethernet 10/100 0 +d 115d000b Cardbus Ethernet 10/100 0 +s 115d000b10140183 10/100 EtherJet Cardbus Adapter 0 +s 115d000b115d0183 Cardbus Ethernet 10/100 0 +d 115d000c Mini-PCI V.90 56k Modem 1 Linmodem +d 115d000f Cardbus Ethernet 10/100 0 +s 115d000f10140183 10/100 EtherJet Cardbus Adapter 0 +s 115d000f115d0183 Cardbus Ethernet 10/100 0 +d 115d0101 Cardbus 56k modem 0 +s 115d0101115d1081 Cardbus 56k Modem 0 +d 115d0103 Cardbus Ethernet + 56k Modem 0 +s 115d010310149181 CardBus 56k Modem 1 +s 115d010311151181 Cardbus Ethernet 100 56k Modem 1 +s 115d0103115d1181 CBEM56G-100 Ethernet + 56k Modem 0 +s 115d010380869181 PRO/100 LAN + Modem56 CardBus 0 +v 115e Peer Protocols Inc 0 +v 115f Maxtor Corporation 0 +v 1160 Megasoft Inc 0 +v 1161 PFU Limited 0 +v 1162 OA Laboratory Co Ltd 0 +v 1163 Rendition 0 +d 11630001 Verite 1000 0 +d 11632000 Verite V2000/V2100/V2200 0 +s 1163200010922000 Stealth II S220 0 +v 1164 Advanced Peripherals Technologies 0 +v 1165 Imagraph Corporation 0 +d 11650001 Motion TPEG Recorder/Player with audio 0 +v 1166 ServerWorks 0 +d 11660007 CNB20-LE Host Bridge 0 +d 11660008 CNB20HE Host Bridge 0 +d 11660009 CNB20LE Host Bridge 0 +d 11660010 CIOB30 0 +d 11660011 CMIC-HE 0 +d 11660200 OSB4 South Bridge 0 +d 11660201 CSB5 South Bridge 0 +d 11660211 OSB4 IDE Controller 0 +d 11660212 CSB5 IDE Controller 0 +d 11660220 OSB4/CSB5 OHCI USB Controller 0 +v 1167 Mutoh Industries Inc 0 +v 1168 Thine Electronics Inc 0 +v 1169 Centre for Development of Advanced Computing 0 +v 116a Polaris Communications 0 +d 116a6100 Bus/Tag Channel 0 +d 116a6800 Escon Channel 0 +d 116a7100 Bus/Tag Channel 0 +d 116a7800 Escon Channel 0 +v 116b Connectware Inc 0 +v 116c Intelligent Resources Integrated Systems 0 +v 116d Martin-Marietta 0 +v 116e Electronics for Imaging 0 +v 116f Workstation Technology 0 +v 1170 Inventec Corporation 0 +v 1171 Loughborough Sound Images Plc 0 +v 1172 Altera Corporation 0 +v 1173 Adobe Systems, Inc 0 +v 1174 Bridgeport Machines 0 +v 1175 Mitron Computer Inc. 0 +v 1176 SBE Incorporated 0 +v 1177 Silicon Engineering 0 +v 1178 Alfa, Inc. 0 +d 1178afa1 Fast Ethernet Adapter 0 +v 1179 Toshiba America Info Systems 0 +d 11790404 DVD Decoder card 0 +d 11790406 Tecra Video Capture device 0 +d 11790407 DVD Decoder card (Version 2) 0 +d 11790601 601 0 +d 11790603 ToPIC95 PCI to CardBus Bridge for Notebooks 0 +d 1179060a ToPIC95 0 +d 1179060f ToPIC97 0 +d 11790617 ToPIC95 PCI to Cardbus Bridge with ZV Support 0 +d 11790618 CPU to PCI and PCI to ISA bridge 0 +d 11790701 FIR Port 0 Claimed to be Lucent DSP1645 [Mars], but that's apparently incorrect. Does anyone know the correct ID? +d 11790d01 FIR Port Type-DO 0 +s 11790d0111790001 FIR Port Type-DO 0 +v 117a A-Trend Technology 0 +v 117b L G Electronics, Inc. 0 +v 117c Atto Technology 0 +v 117d Becton & Dickinson 0 +v 117e T/R Systems 0 +v 117f Integrated Circuit Systems 0 +v 1180 Ricoh Co Ltd 0 +d 11800465 RL5c465 0 +d 11800466 RL5c466 0 +d 11800475 RL5c475 0 +d 11800476 RL5c476 II 0 +d 11800477 RL5c477 0 +d 11800478 RL5c478 0 +v 1181 Telmatics International 0 +v 1183 Fujikura Ltd 0 +v 1184 Forks Inc 0 +v 1185 Dataworld International Ltd 0 +v 1186 D-Link System Inc 0 +d 11860100 DC21041 0 +d 11861002 Sundance Ethernet 0 +d 11861300 RTL8139 Ethernet 0 +d 11861340 DFE-690TXD CardBus PC Card 0 +d 11864000 DL2K Ethernet 0 +v 1187 Advanced Technology Laboratories, Inc. 0 +v 1188 Shima Seiki Manufacturing Ltd. 0 +v 1189 Matsushita Electronics Co Ltd 0 +v 118a Hilevel Technology 0 +v 118b Hypertec Pty Limited 0 +v 118c Corollary, Inc 0 +d 118c0014 PCIB [C-bus II to PCI bus host bridge chip] 0 +d 118c1117 Intel 8-way XEON Profusion Chipset [Cache Coherency Filter] 0 +v 118d BitFlow Inc 0 +d 118d0001 Raptor-PCI framegrabber 0 +d 118d0012 Model 12 Road Runner Frame Grabber 0 +d 118d0014 Model 14 Road Runner Frame Grabber 0 +d 118d0024 Model 24 Road Runner Frame Grabber 0 +d 118d0044 Model 44 Road Runner Frame Grabber 0 +d 118d0112 Model 12 Road Runner Frame Grabber 0 +d 118d0114 Model 14 Road Runner Frame Grabber 0 +d 118d0124 Model 24 Road Runner Frame Grabber 0 +d 118d0144 Model 44 Road Runner Frame Grabber 0 +d 118d0212 Model 12 Road Runner Frame Grabber 0 +d 118d0214 Model 14 Road Runner Frame Grabber 0 +d 118d0224 Model 24 Road Runner Frame Grabber 0 +d 118d0244 Model 44 Road Runner Frame Grabber 0 +d 118d0312 Model 12 Road Runner Frame Grabber 0 +d 118d0314 Model 14 Road Runner Frame Grabber 0 +d 118d0324 Model 24 Road Runner Frame Grabber 0 +d 118d0344 Model 44 Road Runner Frame Grabber 0 +v 118e Hermstedt GmbH 0 +v 118f Green Logic 0 +v 1190 Tripace 0 +d 1190c731 TP-910/920/940 PCI Ultra(Wide) SCSI Adapter 0 +v 1191 Artop Electronic Corp 0 +d 11910003 SCSI Cache Host Adapter 0 +d 11910004 ATP8400 0 +d 11910005 ATP850UF 0 +d 11910006 ATP860 NO-BIOS 0 +d 11910007 ATP860 0 +d 11910008 ATP865 NO-ROM 0 +d 11910009 ATP865 0 +d 11918002 AEC6710 SCSI-2 Host Adapter 0 +d 11918010 AEC6712UW SCSI 0 +d 11918020 AEC6712U SCSI 0 +d 11918030 AEC6712S SCSI 0 +d 11918040 AEC6712D SCSI 0 +d 11918050 AEC6712SUW SCSI 0 +v 1192 Densan Company Ltd 0 +v 1193 Zeitnet Inc. 0 +d 11930001 1221 0 +d 11930002 1225 0 +v 1194 Toucan Technology 0 +v 1195 Ratoc System Inc 0 +v 1196 Hytec Electronics Ltd 0 +v 1197 Gage Applied Sciences, Inc. 0 +v 1198 Lambda Systems Inc 0 +v 1199 Attachmate Corporation 0 +v 119a Mind Share, Inc. 0 +v 119b Omega Micro Inc. 0 +d 119b1221 82C092G 0 +v 119c Information Technology Inst. 0 +v 119d Bug, Inc. Sapporo Japan 0 +v 119e Fujitsu Microelectronics Ltd. 0 +d 119e0001 FireStream 155 0 +d 119e0003 FireStream 50 0 +v 119f Bull HN Information Systems 0 +v 11a0 Convex Computer Corporation 0 +v 11a1 Hamamatsu Photonics K.K. 0 +v 11a2 Sierra Research and Technology 0 +v 11a3 Deuretzbacher GmbH & Co. Eng. KG 0 +v 11a4 Barco Graphics NV 0 +v 11a5 Microunity Systems Eng. Inc 0 +v 11a6 Pure Data Ltd. 0 +v 11a7 Power Computing Corp. 0 +v 11a8 Systech Corp. 0 +v 11a9 InnoSys Inc. 0 +d 11a94240 AMCC S933Q Intelligent Serial Card 0 +v 11aa Actel 0 +v 11ab Galileo Technology Ltd. 0 +d 11ab0146 GT-64010 0 +d 11ab4801 GT-48001 0 +d 11abf003 GT-64010 Primary Image Piranha Image Generator 0 +v 11ac Canon Information Systems Research Aust. 0 +v 11ad Lite-On Communications Inc 0 +d 11ad0002 LNE100TX 0 +s 11ad000211ad0002 LNE100TX 0 +s 11ad000211ad0003 LNE100TX 0 +s 11ad000211adf003 LNE100TX 0 +s 11ad000211adffff LNE100TX 0 +s 11ad00021385f004 FA310TX 0 +d 11adc115 LNE100TX [Linksys EtherFast 10/100] 0 +v 11ae Aztech System Ltd 0 +v 11af Avid Technology Inc. 0 +v 11b0 V3 Semiconductor Inc. 0 +d 11b00002 V300PSC 0 +d 11b00292 V292PBC [Am29030/40 Bridge] 0 +d 11b00960 V96xPBC 0 +d 11b0c960 V96DPC 0 +v 11b1 Apricot Computers 0 +v 11b2 Eastman Kodak 0 +v 11b3 Barr Systems Inc. 0 +v 11b4 Leitch Technology International 0 +v 11b5 Radstone Technology Plc 0 +v 11b6 United Video Corp 0 +v 11b7 Motorola 0 +v 11b8 XPoint Technologies, Inc 0 +d 11b80001 Quad PeerMaster 0 +v 11b9 Pathlight Technology Inc. 0 +d 11b9c0ed SSA Controller 0 +v 11ba Videotron Corp 0 +v 11bb Pyramid Technology 0 +v 11bc Network Peripherals Inc 0 +d 11bc0001 NP-PCI 0 +v 11bd Pinnacle Systems Inc. 0 +v 11be International Microcircuits Inc 0 +v 11bf Astrodesign, Inc. 0 +v 11c0 Hewlett Packard 0 +v 11c1 Lucent Microelectronics 0 +d 11c10440 56k WinModem 0 +s 11c1044000010440 LT WinModem 56k Data+Fax+Voice+Dsvd 0 +s 11c1044010338015 LT WinModem 56k Data+Fax+Voice+Dsvd 0 +s 11c1044010338047 LT WinModem 56k Data Fax Voice Dsvd 0 +s 11c104401033804f LT WinModem 56k Data+Fax+Voice+Dsvd 0 +s 11c1044010cf102c LB LT Modem V.90 56k 0 +s 11c1044010cf104a BIBLO LT Modem 56k 0 +s 11c1044010cf105f LB2 LT Modem V.90 56k 0 +s 11c1044011790001 Internal V.90 Modem 0 +s 11c1044011c10440 LT WinModem 56k Data+Fax+Voice+Dsvd 0 +s 11c10440122d4101 MDP7800-U Modem 0 +s 11c10440122d4102 MDP7800SP-U Modem 0 +s 11c1044013e00040 LT WinModem 56k Data+Fax+Voice+Dsvd 0 +s 11c1044013e00440 LT WinModem 56k Data+Fax+Voice+Dsvd 0 +s 11c1044013e00441 LT WinModem 56k Data+Fax+Voice+Dsvd 0 +s 11c1044013e00450 56k Voice Modem 0 +s 11c1044013e0f100 LT WinModem 56k Data+Fax+Voice+Dsvd 0 +s 11c1044013e0f101 LT WinModem 56k Data+Fax+Voice+Dsvd 0 +s 11c10440144d2101 LT56PV Modem 0 +s 11c10440149f0440 LT WinModem 56k Data+Fax+Voice+Dsvd 0 +d 11c10441 56k WinModem 0 +s 11c104411033804d LT WinModem 56k Data+Fax 0 +s 11c1044110338065 LT WinModem 56k Data Fax 0 +s 11c1044110920440 Supra 56i 0 +s 11c1044111790001 Internal V.90 Modem 0 +s 11c1044111c10440 LT WinModem 56k Data+Fax 0 +s 11c1044111c10441 LT WinModem 56k Data+Fax 0 +s 11c10441122d4100 MDP7800-U Modem 0 +s 11c1044113e00040 LT WinModem 56k Data+Fax 0 +s 11c1044113e00100 LT WinModem 56k Data+Fax 0 +s 11c1044113e00410 LT WinModem 56k Data+Fax 0 +s 11c1044113e00420 TelePath Internet 56k WinModem 0 +s 11c1044113e00440 LT WinModem 56k Data Fax 0 +s 11c1044113e00443 LT WinModem 56k Data+Fax 0 +s 11c1044113e0f102 LT WinModem 56k Data Fax 0 +s 11c1044114169804 CommWave 56k Modem 0 +s 11c10441141d0440 LT WinModem 56k Data+Fax 0 +s 11c10441144f0441 Lucent 56k V.90 DF Modem 0 +s 11c10441144f0449 Lucent 56k V.90 DF Modem 0 +s 11c10441144f110d Lucent Win Modem 0 +s 11c1044114680441 Presario 56k V.90 DF Modem 0 +s 11c1044116680440 Lucent Win Modem 0 +d 11c10442 56k WinModem 0 +s 11c1044200010440 LT WinModem 56k Data+Fax+Voice+VoiceView+Dsvd 0 +s 11c1044211c10440 LT WinModem 56k Data+Fax+Voice+VoiceView+Dsvd 0 +s 11c1044211c10442 LT WinModem 56k Data+Fax+Voice+VoiceView+Dsvd 0 +s 11c1044213e00412 LT WinModem 56k Data+Fax+Voice+VoiceView+Dsvd 0 +s 11c1044213e00442 LT WinModem 56k Data+Fax+Voice+VoiceView+Dsvd 0 +s 11c1044213fc2471 LT WinModem 56k Data+Fax+Voice+VoiceView+Dsvd 0 +s 11c10442144d2104 LT56PT Modem 0 +s 11c10442144f1104 LT WinModem 56k Data Fax Voice VoiceView Dsvd 0 +s 11c10442149f0440 LT WinModem 56k Data+Fax+Voice+VoiceView+Dsvd 0 +s 11c1044216680440 LT WinModem 56k Data+Fax+Voice+VoiceView+Dsvd 0 +d 11c10443 LT WinModem 0 +d 11c10444 LT WinModem 0 +d 11c10445 LT WinModem 0 +d 11c10446 LT WinModem 0 +d 11c10447 LT WinModem 0 +d 11c10448 WinModem 56k 0 +s 11c1044810140131 Lucent Win Modem 0 +s 11c1044810338066 LT WinModem 56k Data Fax Voice Dsvd 0 +s 11c1044813e00030 56k Voice Modem 0 +s 11c1044813e00040 LT WinModem 56k Data+Fax+Voice+Dsvd 0 +d 11c10449 WinModem 56k 0 +s 11c104490e11b14d 56k V.90 Modem 0 +s 11c1044913e00020 LT WinModem 56k Data+Fax 0 +s 11c1044913e00041 TelePath Internet 56k WinModem 0 +s 11c1044914360440 Lucent Win Modem 0 +s 11c10449144f0449 Lucent 56k V.90 DFi Modem 0 +s 11c1044914680440 Lucent Win Modem 0 +s 11c1044914680449 Presario 56k V.90 DFi Modem 0 +d 11c1044a F-1156IV WinModem (V90, 56KFlex) 0 +s 11c1044a10cf1072 LB Global LT Modem 0 +s 11c1044a13e00012 LT WinModem 56k Data+Fax+Voice+VoiceView+Dsvd 0 +s 11c1044a13e00042 LT WinModem 56k Data+Fax+Voice+VoiceView+Dsvd 0 +s 11c1044a144f1005 LT WinModem 56k Data+Fax+Voice+VoiceView+Dsvd 0 +d 11c1044b LT WinModem 0 +d 11c1044c LT WinModem 0 +d 11c1044d LT WinModem 0 +d 11c1044e LT WinModem 0 +d 11c1044f V90 WildWire Modem 0 +d 11c10450 LT WinModem 0 +d 11c10451 LT WinModem 0 +d 11c10452 LT WinModem 0 +d 11c10453 LT WinModem 0 +d 11c10454 LT WinModem 0 +d 11c10455 LT WinModem 0 +d 11c10456 LT WinModem 0 +d 11c10457 LT WinModem 0 +d 11c10458 LT WinModem 0 +d 11c10459 LT WinModem 0 +d 11c1045a LT WinModem 0 +d 11c10461 V90 WildWire Modem 0 +d 11c10462 V90 WildWire Modem 0 +d 11c10480 Venus Modem (V90, 56KFlex) 0 +d 11c15811 FW323 0 +s 11c15811dead0800 FireWire Host Bus Adapter 0 +v 11c2 Sand Microelectronics 0 +v 11c3 NEC Corp 0 +v 11c4 Document Technologies, Inc 0 +v 11c5 Shiva Corporation 0 +v 11c6 Dainippon Screen Mfg. Co. Ltd 0 +v 11c7 D.C.M. Data Systems 0 +v 11c8 Dolphin Interconnect Solutions AS 0 +d 11c80658 PSB32 SCI-Adapter D31x 0 +d 11c8d665 PSB64 SCI-Adapter D32x 0 +d 11c8d667 PSB66 SCI-Adapter D33x 0 +v 11c9 Magma 0 +d 11c90010 16-line serial port w/- DMA 0 +d 11c90011 4-line serial port w/- DMA 0 +v 11ca LSI Systems, Inc 0 +v 11cb Specialix Research Ltd. 0 +d 11cb2000 PCI_9050 0 +s 11cb200011cb0200 SX 0 +s 11cb200011cbb008 I/O8+ 0 +d 11cb4000 SUPI_1 0 +d 11cb8000 T225 0 +v 11cc Michels & Kleberhoff Computer GmbH 0 +v 11cd HAL Computer Systems, Inc. 0 +v 11ce Netaccess 0 +v 11cf Pioneer Electronic Corporation 0 +v 11d0 Lockheed Martin Federal Systems-Manassas 0 +v 11d1 Auravision 0 +d 11d101f7 VxP524 0 +v 11d2 Intercom Inc. 0 +v 11d3 Trancell Systems Inc 0 +v 11d4 Analog Devices 0 +d 11d41889 AD1889 sound chip 0 +v 11d5 Ikon Corporation 0 +d 11d50115 10115 0 +d 11d50117 10117 0 +v 11d6 Tekelec Telecom 0 +v 11d7 Trenton Technology, Inc. 0 +v 11d8 Image Technologies Development 0 +v 11d9 TEC Corporation 0 +v 11da Novell 0 +v 11db Sega Enterprises Ltd 0 +v 11dc Questra Corporation 0 +v 11dd Crosfield Electronics Limited 0 +v 11de Zoran Corporation 0 +d 11de6057 ZR36057PQC Video cutting chipset 0 +s 11de605710317efe DC10 Plus 0 +s 11de60571031fc00 MiroVIDEO DC50, Motion JPEG Capture/CODEC Board 0 +s 11de605713ca4231 JPEG/TV Card 0 +d 11de6120 ZR36120 0 +s 11de61201328f001 Cinemaster C DVD Decoder 0 +v 11df New Wave PDG 0 +v 11e0 Cray Communications A/S 0 +v 11e1 GEC Plessey Semi Inc. 0 +v 11e2 Samsung Information Systems America 0 +v 11e3 Quicklogic Corporation 0 +v 11e4 Second Wave Inc 0 +v 11e5 IIX Consulting 0 +v 11e6 Mitsui-Zosen System Research 0 +v 11e7 Toshiba America, Elec. Company 0 +v 11e8 Digital Processing Systems Inc. 0 +v 11e9 Highwater Designs Ltd. 0 +v 11ea Elsag Bailey 0 +v 11eb Formation Inc. 0 +v 11ec Coreco Inc 0 +v 11ed Mediamatics 0 +v 11ee Dome Imaging Systems Inc 0 +v 11ef Nicolet Technologies B.V. 0 +v 11f0 Compu-Shack 0 +d 11f04231 FDDI 0 +d 11f04232 FASTline UTP Quattro 0 +d 11f04233 FASTline FO 0 +d 11f04234 FASTline UTP 0 +d 11f04235 FASTline-II UTP 0 +d 11f04236 FASTline-II FO 0 +d 11f04731 GIGAline 0 +v 11f1 Symbios Logic Inc 0 +v 11f2 Picture Tel Japan K.K. 0 +v 11f3 Keithley Metrabyte 0 +v 11f4 Kinetic Systems Corporation 0 +d 11f42915 CAMAC controller 0 +v 11f5 Computing Devices International 0 +v 11f6 Compex 0 +d 11f60112 ENet100VG4 0 +d 11f60113 FreedomLine 100 0 +d 11f61401 ReadyLink 2000 0 +d 11f62011 RL100-ATX 10/100 0 +d 11f62201 ReadyLink 100TX (Winbond W89C840) 0 +s 11f6220111f62011 ReadyLink 100TX 0 +d 11f69881 RL100TX 0 +v 11f7 Scientific Atlanta 0 +v 11f8 PMC-Sierra Inc. 0 +d 11f87375 PM7375 [LASAR-155 ATM SAR] 0 +v 11f9 I-Cube Inc 0 +v 11fa Kasan Electronics Company, Ltd. 0 +v 11fb Datel Inc 0 +v 11fc Silicon Magic 0 +v 11fd High Street Consultants 0 +v 11fe Comtrol Corporation 0 +d 11fe0001 RocketPort 8 Oct 0 +d 11fe0002 RocketPort 8 Intf 0 +d 11fe0003 RocketPort 16 Intf 0 +d 11fe0004 RocketPort 32 Intf 0 +d 11fe0005 RocketPort Octacable 0 +d 11fe0006 RocketPort 8J 0 +d 11fe0008 RocketPort 8-port 0 +d 11fe0009 RocketPort 16-port 0 +d 11fe000a RocketPort Plus Quadcable 0 +d 11fe000b RocketPort Plus Octacable 0 +d 11fe000c RocketPort 8-port Modem 0 +v 11ff Scion Corporation 0 +v 1200 CSS Corporation 0 +v 1201 Vista Controls Corp 0 +v 1202 Network General Corp. 0 +v 1203 Bayer Corporation, Agfa Division 0 +v 1204 Lattice Semiconductor Corporation 0 +v 1205 Array Corporation 0 +v 1206 Amdahl Corporation 0 +v 1208 Parsytec GmbH 0 +d 12084853 HS-Link Device 0 +v 1209 SCI Systems Inc 0 +v 120a Synaptel 0 +v 120b Adaptive Solutions 0 +v 120c Technical Corp. 0 +v 120d Compression Labs, Inc. 0 +v 120e Cyclades Corporation 0 +d 120e0100 Cyclom_Y below first megabyte 0 +d 120e0101 Cyclom_Y above first megabyte 0 +d 120e0102 Cyclom_4Y below first megabyte 0 +d 120e0103 Cyclom_4Y above first megabyte 0 +d 120e0104 Cyclom_8Y below first megabyte 0 +d 120e0105 Cyclom_8Y above first megabyte 0 +d 120e0200 Cyclom_Z below first megabyte 0 +d 120e0201 Cyclom_Z above first megabyte 0 +d 120e0300 PC300 RX 2 0 +d 120e0301 PC300 RX 1 0 +d 120e0310 PC300 TE 2 0 +d 120e0311 PC300 TE 1 0 +v 120f Essential Communications 0 +d 120f0001 Roadrunner serial HIPPI 0 +v 1210 Hyperparallel Technologies 0 +v 1211 Braintech Inc 0 +v 1212 Kingston Technology Corp. 0 +v 1213 Applied Intelligent Systems, Inc. 0 +v 1214 Performance Technologies, Inc. 0 +v 1215 Interware Co., Ltd 0 +v 1216 Purup Prepress A/S 0 +v 1217 O2 Micro, Inc. 0 +d 12176729 6729 0 +d 1217673a 6730 0 +d 12176832 6832 0 +d 12176836 6836 0 +d 12176872 OZ6812 Cardbus Controller 0 +d 12176933 OZ6933 Cardbus Controller 0 +v 1218 Hybricon Corp. 0 +v 1219 First Virtual Corporation 0 +v 121a 3Dfx Interactive, Inc. 0 +d 121a0001 Voodoo 0 +d 121a0002 Voodoo 2 0 +d 121a0003 Voodoo Banshee 0 +s 121a000310920003 Monster Fusion 0 +s 121a000310924000 Monster Fusion 0 +s 121a000310924002 Monster Fusion 0 +s 121a000310924801 Monster Fusion AGP 0 +s 121a000310924803 Monster Fusion AGP 0 +s 121a000310928030 Monster Fusion 0 +s 121a000310928035 Monster Fusion AGP 0 +s 121a000310b00001 Dragon 4000 0 +s 121a000311021018 3D Blaster Banshee VE 0 +s 121a0003121a0001 Voodoo Banshee AGP 0 +s 121a0003121a0003 Voodoo Banshee AGP SGRAM 0 +s 121a0003121a0004 Voodoo Banshee 0 +s 121a0003139c0016 Raven 0 +s 121a0003139c0017 Raven 0 +s 121a000314af0002 Maxi Gamer Phoenix 0 +s 121a000330303030 Skywell Magic TwinPower 0 +d 121a0004 Voodoo Banshee [Velocity 100] 0 +d 121a0005 Voodoo 3 0 +s 121a0005121a0004 Voodoo3 AGP 0 +s 121a0005121a0030 Voodoo3 AGP 0 +s 121a0005121a0031 Voodoo3 AGP 0 +s 121a0005121a0034 Voodoo3 AGP 0 +s 121a0005121a0036 Voodoo3 0 +s 121a0005121a0037 Voodoo3 AGP 0 +s 121a0005121a0038 Voodoo3 AGP 0 +s 121a0005121a003a Voodoo3 AGP 0 +s 121a0005121a0044 Voodoo3 0 +s 121a0005121a004b Velocity 100 0 +s 121a0005121a004c Velocity 200 0 +s 121a0005121a004d Voodoo3 AGP 0 +s 121a0005121a004e Voodoo3 AGP 0 +s 121a0005121a0051 Voodoo3 AGP 0 +s 121a0005121a0052 Voodoo3 AGP 0 +s 121a0005121a0060 Voodoo3 3500 TV (NTSC) 0 +s 121a0005121a0061 Voodoo3 3500 TV (PAL) 0 +s 121a0005121a0062 Voodoo3 3500 TV (SECAM) 0 +d 121a0009 Voodoo 4 / Voodoo 5 0 +s 121a0009121a0009 Voodoo5 AGP 5500/6000 0 +v 121b Advanced Telecommunications Modules 0 +v 121c Nippon Texaco., Ltd 0 +v 121d Lippert Automationstechnik GmbH 0 +v 121e CSPI 0 +v 121f Arcus Technology, Inc. 0 +v 1220 Ariel Corporation 0 +d 12201220 AMCC 5933 TMS320C80 DSP/Imaging board 0 +v 1221 Contec Co., Ltd 0 +v 1222 Ancor Communications, Inc. 0 +v 1223 Artesyn Communication Products 0 +d 12230003 PM/Link 0 +d 12230004 PM/T1 0 +d 12230005 PM/E1 0 +d 12230008 PM/SLS 0 +d 12230009 BajaSpan Resource Target 0 +d 1223000a BajaSpan Section 0 0 +d 1223000b BajaSpan Section 1 0 +d 1223000c BajaSpan Section 2 0 +d 1223000d BajaSpan Section 3 0 +d 1223000e PM/PPC 0 +v 1224 Interactive Images 0 +v 1225 Power I/O, Inc. 0 +v 1227 Tech-Source 0 +v 1228 Norsk Elektro Optikk A/S 0 +v 1229 Data Kinesis Inc. 0 +v 122a Integrated Telecom 0 +v 122b LG Industrial Systems Co., Ltd 0 +v 122c Sican GmbH 0 +v 122d Aztech System Ltd 0 +d 122d1206 368DSP 0 +d 122d50dc 3328 Audio 0 +s 122d50dc122d0001 3328 Audio 0 +d 122d80da 3328 Audio 0 +s 122d80da122d0001 3328 Audio 0 +v 122e Xyratex 0 +v 122f Andrew Corporation 0 +v 1230 Fishcamp Engineering 0 +v 1231 Woodward McCoach, Inc. 0 +v 1232 GPT Limited 0 +v 1233 Bus-Tech, Inc. 0 +v 1234 Technical Corp. 0 +v 1235 Risq Modular Systems, Inc. 0 +v 1236 Sigma Designs Corporation 0 +d 12360000 RealMagic64/GX 0 +d 12366401 REALmagic 64/GX (SD 6425) 0 +v 1237 Alta Technology Corporation 0 +v 1238 Adtran 0 +v 1239 3DO Company 0 +v 123a Visicom Laboratories, Inc. 0 +v 123b Seeq Technology, Inc. 0 +v 123c Century Systems, Inc. 0 +v 123d Engineering Design Team, Inc. 0 +d 123d0000 EasyConnect 8/32 0 +d 123d0002 EasyConnect 8/64 0 +d 123d0003 EasyIO 0 +v 123e Simutech, Inc. 0 +v 123f C-Cube Microsystems 0 +d 123f00e4 MPEG 0 +d 123f8120 E4? 0 +s 123f812011bd0006 DV500 E4 0 +s 123f812011bd000a DV500 E4 0 +d 123f8888 Cinemaster C 3.0 DVD Decoder 0 +s 123f888810020001 Cinemaster C 3.0 DVD Decoder 0 +s 123f888810020002 Cinemaster C 3.0 DVD Decoder 0 +s 123f888813280001 Cinemaster C 3.0 DVD Decoder 0 +v 1240 Marathon Technologies Corp. 0 +v 1241 DSC Communications 0 +v 1242 Jaycor Networks, Inc. 0 +d 12424643 FCI-1063 Fibre Channel Adapter 0 +v 1243 Delphax 0 +v 1244 AVM Audiovisuelles MKTG & Computer System GmbH 0 +d 12440700 B1 ISDN 0 +d 12440800 C4 ISDN 0 +d 12440a00 A1 ISDN [Fritz] 0 +s 12440a0012440a00 FRITZ!Card ISDN Controller 0 +d 12440e00 Fritz!PCI v2.0 ISDN 0 +d 12441100 C2 ISDN 0 +d 12441200 T1 ISDN 0 +v 1245 A.P.D., S.A. 0 +v 1246 Dipix Technologies, Inc. 0 +v 1247 Xylon Research, Inc. 0 +v 1248 Central Data Corporation 0 +v 1249 Samsung Electronics Co., Ltd. 0 +v 124a AEG Electrocom GmbH 0 +v 124b SBS/Greenspring Modular I/O 0 +d 124b0040 cPCI-200 Four Slot IndustryPack Carrier 1 The chip is PCI9080, but the vendor and device ID is by the card http://www.powerbridge.de/download/data/cpci/cpci-io/CPCI-200A_ +d 124b0040 cPCI-200 four IndustryPack carrier 1 +s 124b0040124b9080 PCI9080 Bridge 1 http://www1.plxtech.com/TEMP/34826/9080db-106.pdf +v 124c Solitron Technologies, Inc. 0 +v 124d Stallion Technologies, Inc. 0 +d 124d0000 EasyConnection 8/32 0 +d 124d0002 EasyConnection 8/64 0 +d 124d0003 EasyIO 0 +d 124d0004 EasyConnection/RA 0 +v 124e Cylink 0 +v 124f Infotrend Technology, Inc. 0 +d 124f0041 IFT-2000 Series RAID Controller 0 +v 1250 Hitachi Microcomputer System Ltd 0 +v 1251 VLSI Solutions Oy 0 +v 1253 Guzik Technical Enterprises 0 +v 1254 Linear Systems Ltd. 0 +v 1255 Optibase Ltd 0 +d 12551110 MPEG Forge 0 +d 12551210 MPEG Fusion 0 +d 12552110 VideoPlex 0 +d 12552120 VideoPlex CC 0 +d 12552130 VideoQuest 0 +v 1256 Perceptive Solutions, Inc. 0 +d 12564201 PCI-2220I 0 +d 12564401 PCI-2240I 0 +d 12565201 PCI-2000 0 +v 1257 Vertex Networks, Inc. 0 +v 1258 Gilbarco, Inc. 0 +v 1259 Allied Telesyn International 0 +d 12592560 AT-2560 Fast Ethernet Adapter (i82557B) 0 +v 125a ABB Power Systems 0 +v 125b Asix Electronics Corporation 0 +d 125b125b 1 +d 125b1400 ALFA GFC2204 0 +v 125c Aurora Technologies, Inc. 0 +v 125d ESS Technology 0 +d 125d0000 ES336H Fax Modem (Early Model) 0 +d 125d1948 Solo? 0 +d 125d1968 ES1968 Maestro 2 0 +s 125d196810280085 ES1968 Maestro-2 PCI 0 +s 125d196810338051 ES1968 Maestro-2 Audiodrive 0 +d 125d1969 ES1969 Solo-1 Audiodrive 0 +s 125d196910140166 ES1969 SOLO-1 AudioDrive on IBM Aptiva Mainboard 0 +s 125d1969125d8888 Solo-1 Audio Adapter 0 +s 125d1969525fc888 ES1969 SOLO-1 AudioDrive (+ES1938) 0 +d 125d1978 ES1978 Maestro 2E 0 +s 125d19781033803c ES1978 Maestro-2E Audiodrive 0 +s 125d197810338058 ES1978 Maestro-2E Audiodrive 0 +s 125d197810924000 Monster Sound MX400 0 +s 125d197811790001 ES1978 Maestro-2E Audiodrive 0 +d 125d1988 ES1988 Allegro-1 0 +s 125d198810924100 Sonic Impact S100 0 +s 125d1988125d1988 ESS Allegro-1 Audiodrive 0 +d 125d1989 ESS Modem 0 +s 125d1989125d1989 ESS Modem 0 +d 125d1998 ES1983S Maestro-3i PCI Audio Accelerator 0 +d 125d1999 ES1983S Maestro-3i PCI Modem Accelerator 0 +d 125d2808 ES336H Fax Modem (Later Model) 0 +d 125d2838 ES2838/2839 SuperLink Modem 0 +d 125d2898 ES2898 Modem 0 +s 125d2898125d0424 ES56-PI Data Fax Modem 0 +s 125d2898125d0425 ES56T-PI Data Fax Modem 0 +s 125d2898125d0426 ES56V-PI Data Fax Modem 0 +s 125d2898125d0427 VW-PI Data Fax Modem 0 +s 125d2898125d0428 ES56ST-PI Data Fax Modem 0 +s 125d2898125d0429 ES56SV-PI Data Fax Modem 0 +s 125d2898147ac001 ES56-PI Data Fax Modem 0 +s 125d289814fe0428 ES56-PI Data Fax Modem 0 +s 125d289814fe0429 ES56-PI Data Fax Modem 0 +v 125e Specialvideo Engineering SRL 0 +v 125f Concurrent Technologies, Inc. 0 +v 1260 Harris Semiconductor 0 +d 12608130 HMP8130 NTSC/PAL Video Decoder 0 +d 12608131 HMP8131 NTSC/PAL Video Decoder 0 +v 1261 Matsushita-Kotobuki Electronics Industries, Ltd. 0 +v 1262 ES Computer Company, Ltd. 0 +v 1263 Sonic Solutions 0 +v 1264 Aval Nagasaki Corporation 0 +v 1265 Casio Computer Co., Ltd. 0 +v 1266 Microdyne Corporation 0 +d 12660001 NE10/100 Adapter (i82557B) 0 +d 12661910 NE2000Plus (RT8029) Ethernet Adapter 0 +s 1266191012661910 NE2000Plus Ethernet Adapter 0 +v 1267 S. A. Telecommunications 0 +d 12675352 PCR2101 0 +d 12675a4b Telsat Turbo 0 +v 1268 Tektronix 0 +v 1269 Thomson-CSF/TTM 0 +v 126a Lexmark International, Inc. 0 +v 126b Adax, Inc. 0 +v 126c Northern Telecom 0 +v 126d Splash Technology, Inc. 0 +v 126e Sumitomo Metal Industries, Ltd. 0 +v 126f Silicon Motion, Inc. 0 +d 126f0710 SM710 LynxEM 0 +d 126f0712 SM712 LynxEM+ 0 +d 126f0720 SM720 Lynx3DM 0 +d 126f0810 SM810 LynxE 0 +d 126f0811 SM811 LynxE 0 +d 126f0820 SM820 Lynx3D 0 +d 126f0910 SM910 0 +v 1270 Olympus Optical Co., Ltd. 0 +v 1271 GW Instruments 0 +v 1272 Telematics International 0 +v 1273 Hughes Network Systems 0 +d 12730002 DirecPC 0 +v 1274 Ensoniq 0 +d 12741371 ES1371 [AudioPCI-97] 0 +s 127413710e11b1a7 ES1371, ES1373 AudioPCI 0 +s 12741371103380ac ES1371, ES1373 AudioPCI 0 +s 1274137110421854 Tazer 0 +s 12741371107b8054 Tabor2 0 +s 1274137112741371 Creative Sound Blaster AudioPCI64V, AudioPCI128 0 +s 1274137114626470 ES1371, ES1373 AudioPCI On Motherboard MS-6147 1.1A 0 +s 1274137114626560 ES1371, ES1373 AudioPCI On Motherboard MS-6156 1.10 0 +s 1274137114626630 ES1371, ES1373 AudioPCI On Motherboard MS-6163BX 1.0A 0 +s 1274137114626631 ES1371, ES1373 AudioPCI On Motherboard MS-6163VIA 1.0A 0 +s 1274137114626632 ES1371, ES1373 AudioPCI On Motherboard MS-6163BX 2.0A 0 +s 1274137114626633 ES1371, ES1373 AudioPCI On Motherboard MS-6163VIA 2.0A 0 +s 1274137114626820 ES1371, ES1373 AudioPCI On Motherboard MS-6182 1.00 0 +s 1274137114626822 ES1371, ES1373 AudioPCI On Motherboard MS-6182 1.00A 0 +s 1274137114626830 ES1371, ES1373 AudioPCI On Motherboard MS-6183 1.00 0 +s 1274137114626880 ES1371, ES1373 AudioPCI On Motherboard MS-6188 1.00 0 +s 1274137114626900 ES1371, ES1373 AudioPCI On Motherboard MS-6190 1.00 0 +s 1274137114626910 ES1371, ES1373 AudioPCI On Motherboard MS-6191 0 +s 1274137114626930 ES1371, ES1373 AudioPCI On Motherboard MS-6193 0 +s 1274137114626990 ES1371, ES1373 AudioPCI On Motherboard MS-6199BX 2.0A 0 +s 1274137114626991 ES1371, ES1373 AudioPCI On Motherboard MS-6199VIA 2.0A 0 +s 1274137114a42077 ES1371, ES1373 AudioPCI On Motherboard KR639 0 +s 1274137114a42105 ES1371, ES1373 AudioPCI On Motherboard MR800 0 +s 1274137114a42107 ES1371, ES1373 AudioPCI On Motherboard MR801 0 +s 1274137114a42172 ES1371, ES1373 AudioPCI On Motherboard DR739 0 +s 1274137115099902 ES1371, ES1373 AudioPCI On Motherboard KW11 0 +s 1274137115099903 ES1371, ES1373 AudioPCI On Motherboard KW31 0 +s 1274137115099904 ES1371, ES1373 AudioPCI On Motherboard KA11 0 +s 1274137115099905 ES1371, ES1373 AudioPCI On Motherboard KC13 0 +s 12741371152d8801 ES1371, ES1373 AudioPCI On Motherboard CP810E 0 +s 12741371152d8802 ES1371, ES1373 AudioPCI On Motherboard CP810 0 +s 12741371152d8803 ES1371, ES1373 AudioPCI On Motherboard P3810E 0 +s 12741371152d8804 ES1371, ES1373 AudioPCI On Motherboard P3810-S 0 +s 12741371152d8805 ES1371, ES1373 AudioPCI On Motherboard P3820-S 0 +s 12741371270f2001 ES1371, ES1373 AudioPCI On Motherboard 6CTR 0 +s 12741371270f2200 ES1371, ES1373 AudioPCI On Motherboard 6WTX 0 +s 12741371270f3000 ES1371, ES1373 AudioPCI On Motherboard 6WSV 0 +s 12741371270f3100 ES1371, ES1373 AudioPCI On Motherboard 6WIV2 0 +s 12741371270f3102 ES1371, ES1373 AudioPCI On Motherboard 6WIV 0 +s 12741371270f7060 ES1371, ES1373 AudioPCI On Motherboard 6ASA2 0 +s 1274137180864249 ES1371, ES1373 AudioPCI On Motherboard BI440ZX 0 +s 127413718086424c ES1371, ES1373 AudioPCI On Motherboard BL440ZX 0 +s 127413718086425a ES1371, ES1373 AudioPCI On Motherboard BZ440ZX 0 +s 1274137180864341 ES1371, ES1373 AudioPCI On Motherboard Cayman 0 +s 1274137180864343 ES1371, ES1373 AudioPCI On Motherboard Cape Cod 0 +s 1274137180864649 ES1371, ES1373 AudioPCI On Motherboard Fire Island 0 +s 127413718086464a ES1371, ES1373 AudioPCI On Motherboard FJ440ZX 0 +s 1274137180864d4f ES1371, ES1373 AudioPCI On Motherboard Montreal 0 +s 1274137180864f43 ES1371, ES1373 AudioPCI On Motherboard OC440LX 0 +s 1274137180865243 ES1371, ES1373 AudioPCI On Motherboard RC440BX 0 +s 1274137180865352 ES1371, ES1373 AudioPCI On Motherboard SunRiver 0 +s 1274137180865643 ES1371, ES1373 AudioPCI On Motherboard Vancouver 0 +s 1274137180865753 ES1371, ES1373 AudioPCI On Motherboard WS440BX 0 +d 12745000 ES1370 [AudioPCI] 0 +s 1274500049424c4c Creative Sound Blaster AudioPCI128 0 +d 12745880 5880 AudioPCI 0 +s 1274588012742000 Creative Sound Blaster AudioPCI128 0 +s 1274588012742003 Creative SoundBlaster AudioPCI 128 1 +s 1274588012745880 Creative Sound Blaster AudioPCI128 0 +s 127458801458a000 5880 AudioPCI On Motherboard 6OXET 0 +s 1274588014626880 5880 AudioPCI On Motherboard MS-6188 1.00 0 +s 12745880270f2001 5880 AudioPCI On Motherboard 6CTR 0 +s 12745880270f2200 5880 AudioPCI On Motherboard 6WTX 0 +s 12745880270f7040 5880 AudioPCI On Motherboard 6ATA4 0 +v 1275 Network Appliance Corporation 0 +v 1276 Switched Network Technologies, Inc. 0 +v 1277 Comstream 0 +v 1278 Transtech Parallel Systems Ltd. 0 +d 12780701 TPE3/TM3 PowerPC Node 0 +v 1279 Transmeta Corporation 0 +d 12790295 Northbridge 0 +d 12790395 LongRun Northbridge 0 +d 12790396 SDRAM controller 0 +d 12790397 BIOS scratchpad 0 +v 127a Rockwell International 0 +d 127a1002 HCF 56k Data/Fax Modem 0 +s 127a10021092094c SupraExpress 56i PRO [Diamond SUP2380] 0 +s 127a1002122d4002 HPG / MDP3858-U # Aztech 0 +s 127a1002122d4005 MDP3858-E # Aztech 0 +s 127a1002122d4007 MDP3858-A/-NZ # Aztech 0 +s 127a1002122d4012 MDP3858-SA # Aztech 0 +s 127a1002122d4017 MDP3858-W # Aztech 0 +s 127a1002122d4018 MDP3858-W # Aztech 0 +d 127a1003 HCF 56k Data/Fax Modem 0 +s 127a10030e11b0bc 229-DF Zephyr # Compaq 0 +s 127a10030e11b114 229-DF Cheetah # Compaq 0 +s 127a10031033802b 229-DF # NEC 0 +s 127a100313df1003 PCI56RX Modem # E-Tech Inc 0 +s 127a100313e00117 IBM # GVC 0 +s 127a100313e00147 IBM # GVC F-1156IV /R3 Spain V.90 Modem 0 +s 127a100313e00197 IBM # GVC 0 +s 127a100313e001c7 IBM # GVC F-1156IV /R3 WW V.90 Modem 0 +s 127a100313e001f7 IBM # GVC 0 +s 127a100314361003 IBM # CIS 0 +s 127a100314361103 IBM # CIS 5614PM3G V.90 Modem 0 +s 127a100314361602 Compaq 229-DF Ducati 0 +d 127a1004 HCF 56k Data/Fax/Voice Modem 0 +s 127a100410481500 MicroLink 56k Modem 0 +s 127a100410cf1059 Fujitsu 229-DFRT 0 +d 127a1005 HCF 56k Data/Fax/Voice/Spkp (w/Handset) Modem 0 +s 127a100510338029 229-DFSV # NEC 0 +s 127a100510338054 Modem # NEC 0 +s 127a100510cf103c Fujitsu 0 +s 127a100510cf1055 Fujitsu 229-DFSV 0 +s 127a100510cf1056 Fujitsu 229-DFSV 0 +s 127a1005122d4003 MDP3858SP-U # Aztech 0 +s 127a1005122d4006 Packard Bell MDP3858V-E # Aztech 0 +s 127a1005122d4008 MDP3858SP-A/SP-NZ # Aztech 0 +s 127a1005122d4009 MDP3858SP-E # Aztech 0 +s 127a1005122d4010 MDP3858V-U # Aztech 0 +s 127a1005122d4011 MDP3858SP-SA # Aztech 0 +s 127a1005122d4013 MDP3858V-A/V-NZ # Aztech 0 +s 127a1005122d4015 MDP3858SP-W # Aztech 0 +s 127a1005122d4016 MDP3858V-W # Aztech 0 +s 127a1005122d4019 MDP3858V-SA # Aztech 0 +s 127a100513df1005 PCI56RVP Modem # E-Tech Inc 0 +s 127a100513e00187 IBM # GVC 0 +s 127a100513e001a7 IBM # GVC 0 +s 127a100513e001b7 IBM # GVC DF-1156IV /R3 Spain V.90 Modem 0 +s 127a100513e001d7 IBM # GVC DF-1156IV /R3 WW V.90 Modem 0 +s 127a100514361005 IBM # CIS 0 +s 127a100514361105 IBM # CIS 0 +s 127a100514371105 IBM # CIS 5614PS3G V.90 Modem 0 +d 127a1022 HCF 56k Modem 0 +s 127a102214361303 M3-5614PM3G V.90 Modem 0 +d 127a1023 HCF 56k Data/Fax Modem 0 +s 127a1023122d4020 Packard Bell MDP3858-WE # Aztech 0 +s 127a1023122d4023 MDP3858-UE # Aztech 0 +s 127a102313e00247 IBM # GVC F-1156IV /R6 Spain V.90 Modem 0 +s 127a102313e00297 IBM # GVC 0 +s 127a102313e002c7 IBM # GVC F-1156IV /R6 WW V.90 Modem 0 +s 127a102314361203 IBM # CIS 0 +s 127a102314361303 IBM # CIS 0 +d 127a1024 HCF 56k Data/Fax/Voice Modem 0 +d 127a1025 HCF 56k Data/Fax/Voice/Spkp (w/Handset) Modem 0 +s 127a102510cf106a Fujitsu 235-DFSV 0 +s 127a1025122d4021 Packard Bell MDP3858V-WE # Aztech 0 +s 127a1025122d4022 MDP3858SP-WE # Aztech 0 +s 127a1025122d4024 MDP3858V-UE # Aztech 0 +s 127a1025122d4025 MDP3858SP-UE # Aztech 0 +d 127a1026 HCF 56k PCI Speakerphone Modem 0 +d 127a1032 HCF 56k Modem 0 +d 127a1033 HCF 56k Modem 0 +d 127a1034 HCF 56k Modem 0 +d 127a1035 HCF 56k PCI Speakerphone Modem 0 +d 127a1036 HCF 56k Modem 0 +d 127a1085 HCF 56k Volcano PCI Modem 0 +d 127a2005 HCF 56k Data/Fax Modem 0 +d 127a2005 HSF Data/Fax/Voice/Speakerphone 1 The name you list is incorrect, I'm the author of the Conexant/Rockwell modem HOWTO and I've verified from several sources that +s 127a2005104d8044 229-DFSV # Sony 0 +s 127a2005104d8045 229-DFSV # Sony 0 +s 127a2005104d8055 PBE/Aztech 235W-DFSV # Sony 0 +s 127a2005104d8056 235-DFSV # Sony 0 +s 127a2005104d805a Modem # Sony 0 +s 127a2005104d805f Modem # Sony 0 +s 127a2005104d8074 Modem # Sony 0 +d 127a2013 HSF 56k Data/Fax Modem 0 +s 127a201311790001 Modem # Toshiba 0 +s 127a20131179ff00 Modem # Toshiba 0 +d 127a2014 HSF 56k Data/Fax/Voice Modem 0 +s 127a201410cf1057 Fujitsu Citicorp III 0 +s 127a2014122d4050 MSP3880-U # Aztech 0 +s 127a2014122d4055 MSP3880-W # Aztech 0 +d 127a2015 HSF 56k Data/Fax/Voice/Spkp (w/Handset) Modem 0 +s 127a201510cf1063 Fujitsu 0 +s 127a201510cf1064 Fujitsu 0 +s 127a201514682015 Fujitsu 0 +d 127a2016 HSF 56k Data/Fax/Voice/Spkp Modem 0 +s 127a2016122d4051 MSP3880V-W # Aztech 0 +s 127a2016122d4052 MSP3880SP-W # Aztech 0 +s 127a2016122d4054 MSP3880V-U # Aztech 0 +s 127a2016122d4056 MSP3880SP-U # Aztech 0 +s 127a2016122d4057 MSP3880SP-A # Aztech 0 +d 127a4311 Riptide HSF 56k PCI Modem 0 +s 127a4311127a4311 Ring Modular? Riptide HSF RT HP Dom 0 +s 127a431113e00210 HP-GVC 0 +d 127a4320 Riptide PCI Audio Controller 0 +s 127a432012354320 Riptide PCI Audio Controller 0 +d 127a4321 Riptide HCF 56k PCI Modem 0 +s 127a432112354321 Hewlett Packard DF 0 +s 127a432112354324 Hewlett Packard DF 0 +s 127a432113e00210 Hewlett Packard DF 0 +s 127a4321144d2321 Riptide # Samsung 0 +d 127a4322 Riptide PCI Game Controller 0 +s 127a432212354322 Riptide PCI Game Controller 0 +d 127a8234 RapidFire 616X ATM155 Adapter 0 +s 127a8234108d0022 RapidFire 616X ATM155 Adapter 1 +s 127a8234108d0027 RapidFire 616X ATM155 Adapter 0 +v 127b Pixera Corporation 0 +v 127c Crosspoint Solutions, Inc. 0 +v 127d Vela Research 0 +v 127e Winnov, L.P. 0 +v 127f Fujifilm 0 +v 1280 Photoscript Group Ltd. 0 +v 1281 Yokogawa Electric Corporation 0 +v 1282 Davicom Semiconductor, Inc. 0 +d 12829009 Ethernet 100/10 MBit 0 +d 12829100 Ethernet 100/10 MBit 0 +d 12829102 Ethernet 100/10 MBit 0 +d 12829132 Ethernet 100/10 MBit 0 +v 1283 Integrated Technology Express, Inc. 0 +d 1283673a IT8330G 0 +d 12838330 IT8330G 0 +d 12838888 IT8888F PCI to ISA Bridge with SMB 0 +d 12838889 IT8889F PCI to ISA Bridge 0 +d 1283e886 IT8330G 0 +v 1284 Sahara Networks, Inc. 0 +v 1285 Platform Technologies, Inc. 0 +d 12850100 AGOGO sound chip (aka ESS Maestro 1) 0 +v 1286 Mazet GmbH 0 +v 1287 M-Pact, Inc. 0 +d 1287001e LS220D DVD Decoder 0 +d 1287001f LS220C DVD Decoder 0 +v 1288 Timestep Corporation 0 +v 1289 AVC Technology, Inc. 0 +v 128a Asante Technologies, Inc. 0 +v 128b Transwitch Corporation 0 +v 128c Retix Corporation 0 +v 128d G2 Networks, Inc. 0 +d 128d0021 ATM155 Adapter 0 +v 128e Hoontech Corporation/Samho Multi Tech Ltd. 0 +d 128e0008 ST128 WSS/SB 0 +d 128e0009 ST128 SAM9407 0 +d 128e000a ST128 Game Port 0 +d 128e000b ST128 MPU Port 0 +d 128e000c ST128 Ctrl Port 0 +v 128f Tateno Dennou, Inc. 0 +v 1290 Sord Computer Corporation 0 +v 1291 NCS Computer Italia 0 +v 1292 Tritech Microelectronics Inc 0 +v 1293 Media Reality Technology 0 +v 1294 Rhetorex, Inc. 0 +v 1295 Imagenation Corporation 0 +v 1296 Kofax Image Products 0 +v 1297 Holco Enterprise Co, Ltd/Shuttle Computer 0 +v 1298 Spellcaster Telecommunications Inc. 0 +v 1299 Knowledge Technology Lab. 0 +v 129a VMetro, inc. 0 +d 129a0615 PBT-615 PCI-X Bus Analyzer 0 +v 129b Image Access 0 +v 129c Jaycor 0 +v 129d Compcore Multimedia, Inc. 0 +v 129e Victor Company of Japan, Ltd. 0 +v 129f OEC Medical Systems, Inc. 0 +v 12a0 Allen-Bradley Company 0 +v 12a1 Simpact Associates, Inc. 0 +v 12a2 Newgen Systems Corporation 0 +v 12a3 Lucent Technologies 0 +v 12a4 NTT Electronics Technology Company 0 +v 12a5 Vision Dynamics Ltd. 0 +v 12a6 Scalable Networks, Inc. 0 +v 12a7 AMO GmbH 0 +v 12a8 News Datacom 0 +v 12a9 Xiotech Corporation 0 +v 12aa SDL Communications, Inc. 0 +v 12ab Yuan Yuan Enterprise Co., Ltd. 0 +d 12ab3000 MPG-200C PCI DVD Decoder Card 0 +v 12ac Measurex Corporation 0 +v 12ad Multidata GmbH 0 +v 12ae Alteon Networks Inc. 0 +d 12ae0001 AceNIC Gigabit Ethernet (Fibre) 0 +s 12ae000112ae0001 Gigabit Ethernet-SX (Universal) 0 +s 12ae000114100104 Gigabit Ethernet-SX PCI Adapter (14100401) 0 +d 12ae0002 AceNIC Gigabit Ethernet (Copper) 0 +s 12ae000212ae0002 Gigabit Ethernet-T (3C986-T) 0 +v 12af TDK USA Corp 0 +v 12b0 Jorge Scientific Corp 0 +v 12b1 GammaLink 0 +v 12b2 General Signal Networks 0 +v 12b3 Inter-Face Co Ltd 0 +v 12b4 FutureTel Inc 0 +v 12b5 Granite Systems Inc. 0 +v 12b6 Natural Microsystems 0 +v 12b7 Cognex Modular Vision Systems Div. - Acumen Inc. 0 +v 12b8 Korg 0 +v 12b9 US Robotics/3Com 0 +d 12b91006 WinModem 0 +s 12b9100612b9005c USR 56k Internal Voice WinModem (Model 3472) 0 +s 12b9100612b9005e USR 56k Internal WinModem (Models 662975) 0 +s 12b9100612b90062 USR 56k Internal Voice WinModem (Model 662978) 0 +s 12b9100612b90068 USR 56k Internal Voice WinModem (Model 5690) 0 +s 12b9100612b9007a USR 56k Internal Voice WinModem (Model 662974) 0 +s 12b9100612b9007f USR 56k Internal WinModem (Models 5698, 5699) 0 +s 12b9100612b90080 USR 56k Internal WinModem (Models 2975, 3528) 0 +s 12b9100612b90081 USR 56k Internal Voice WinModem (Models 2974, 3529) 0 +s 12b9100612b90091 USR 56k Internal Voice WinModem (Model 2978) 0 +d 12b91007 USR 56k Internal WinModem 0 +s 12b9100712b900a3 USR 56k Internal WinModem (Model 3595) 0 +d 12b91008 56K FaxModem Model 5610 0 +s 12b9100812b900a2 USR 56k Internal FAX Modem (Model 2977) 0 +s 12b9100812b900aa USR 56k Internal Voice Modem (Model 2976) 0 +s 12b9100812b900ab USR 56k Internal Voice Modem (Model 5609) 0 +s 12b9100812b900ac USR 56k Internal Voice Modem (Model 3298) 0 +s 12b9100812b900ad USR 56k Internal FAX Modem (Model 5610) 0 +v 12ba PMC Sierra 0 +v 12bb Nippon Unisoft Corporation 0 +v 12bc Array Microsystems 0 +v 12bd Computerm Corp. 0 +v 12be Anchor Chips Inc. 0 +d 12be3041 AN3041Q CO-MEM 0 +d 12be3042 AN3042Q CO-MEM Lite 0 +s 12be304212be3042 Anchor Chips Lite Evaluation Board 0 +v 12bf Fujifilm Microdevices 0 +v 12c0 Infimed 0 +v 12c1 GMM Research Corp 0 +v 12c2 Mentec Limited 0 +v 12c3 Holtek Microelectronics Inc 0 +d 12c30058 PCI NE2K Ethernet 0 +d 12c35598 PCI NE2K Ethernet 0 +v 12c4 Connect Tech Inc 0 +v 12c5 Picture Elements Incorporated 0 +d 12c50081 PCIVST [Grayscale Thresholding Engine] 0 +d 12c50085 Video Simulator/Sender 0 +d 12c50086 THR2 Multi-scale Thresholder 0 +v 12c6 Mitani Corporation 0 +v 12c7 Dialogic Corp 0 +v 12c8 G Force Co, Ltd 0 +v 12c9 Gigi Operations 0 +v 12ca Integrated Computing Engines 0 +v 12cb Antex Electronics Corporation 0 +v 12cc Pluto Technologies International 0 +v 12cd Aims Lab 0 +v 12ce Netspeed Inc. 0 +v 12cf Prophet Systems, Inc. 0 +v 12d0 GDE Systems, Inc. 0 +v 12d1 PSITech 0 +v 12d2 NVidia / SGS Thomson (Joint Venture) 0 +d 12d20008 NV1 0 +d 12d20009 DAC64 0 +d 12d20018 Riva128 0 +d 12d20018 Riva128/128ZX 1 +s 12d2001810480c10 VICTORY Erazor 1 +s 12d20018107b8030 STB Velocity 128 0 +s 12d2001810920350 Viper V330 0 +s 12d2001810921092 Viper V330 0 +s 12d2001810b41b1b STB Velocity 128 0 +s 12d2001810b41b1d STB Velocity 128 1 +s 12d2001810b41b1e STB Velocity 128, PAL TV-Out 1 +s 12d2001810b41b1e STB Velocity 128 1 +s 12d2001810b41b20 STB Velocity 128 0 +s 12d2001810b41b20 STB Velocity 128 Sapphire 1 +s 12d2001810b41b21 STB Velocity 128 0 +s 12d2001810b41b22 STB Velocity 128 AGP, NTSC TV-Out 0 +s 12d2001810b41b23 STB Velocity 128 AGP, PAL TV-Out 0 +s 12d2001810b41b27 STB Velocity 128 DVD 0 +s 12d2001810b41b88 MVP Pro 128 1 +s 12d2001810b4222a STB Velocity 128 AGP 0 +s 12d2001810b42230 STB Velocity 128 0 +s 12d2001810b42232 STB Velocity 128 1 +s 12d2001810b42235 STB Velocity 128 AGP 0 +s 12d200182a1554a3 3DVision-SAGP 0 +s 12d200182a1554a3 3DVision-SAGP / 3DexPlorer 3000 1 +d 12d20019 Riva128ZX 0 +d 12d20020 TNT 0 +d 12d20028 TNT2 0 +d 12d20029 UTNT2 0 +d 12d2002c VTNT2 0 +d 12d200a0 ITNT2 0 +v 12d3 Vingmed Sound A/S 0 +v 12d4 DGM&S 0 +v 12d5 Equator Technologies 0 +v 12d6 Analogic Corp 0 +v 12d7 Biotronic SRL 0 +v 12d8 Pericom Semiconductor 0 +v 12d9 Aculab PLC 0 +v 12da True Time Inc. 0 +v 12db Annapolis Micro Systems, Inc 0 +v 12dc Symicron Computer Communication Ltd. 0 +v 12dd Management Graphics 0 +v 12de Rainbow Technologies 0 +v 12df SBS Technologies Inc 0 +v 12e0 Chase Research 0 +d 12e00010 ST16C654 Quad UART 0 +d 12e00020 ST16C654 Quad UART 0 +d 12e00030 ST16C654 Quad UART 0 +v 12e1 Nintendo Co, Ltd 0 +v 12e2 Datum Inc. Bancomm-Timing Division 0 +v 12e3 Imation Corp - Medical Imaging Systems 0 +v 12e4 Brooktrout Technology Inc 0 +v 12e5 Apex Semiconductor Inc 0 +v 12e6 Cirel Systems 0 +v 12e7 Sunsgroup Corporation 0 +v 12e8 Crisc Corp 0 +v 12e9 GE Spacenet 0 +v 12ea Zuken 0 +v 12eb Aureal Semiconductor 0 +d 12eb0001 Vortex 1 0 +s 12eb0001104d8036 AU8820 Vortex Digital Audio Processor 0 +s 12eb000110922000 Sonic Impact A3D 0 +s 12eb000110922100 Sonic Impact A3D 0 +s 12eb000110922110 Sonic Impact A3D 0 +s 12eb000110922200 Sonic Impact A3D 0 +s 12eb000112eb0001 AU8820 Vortex Digital Audio Processor 0 +s 12eb000150533355 Montego 0 +d 12eb0002 Vortex 2 0 +s 12eb0002104d8049 AU8830 Vortex 3D Digital Audio Processor 0 +s 12eb0002104d807b AU8830 Vortex 3D Digital Audio Processor 0 +s 12eb000210923000 Monster Sound II 0 +s 12eb000210923001 Monster Sound II 0 +s 12eb000210923002 Monster Sound II 0 +s 12eb000210923003 Monster Sound II 0 +s 12eb000210923004 Monster Sound II 0 +s 12eb000212eb0001 AU8830 Vortex 3D Digital Audio Processor 0 +s 12eb000212eb0002 AU8830 Vortex 3D Digital Audio Processor 0 +s 12eb000212eb0088 AU8830 Vortex 3D Digital Audio Processor 0 +s 12eb0002144d3510 AU8830 Vortex 3D Digital Audio Processor 0 +s 12eb000250533356 Montego II 0 +d 12eb0003 AU8810 Vortex Digital Audio Processor 0 +s 12eb0003104d8049 AU8810 Vortex Digital Audio Processor 0 +s 12eb0003104d8077 AU8810 Vortex Digital Audio Processor 0 +s 12eb0003109f1000 AU8810 Vortex Digital Audio Processor 0 +s 12eb000312eb0003 AU8810 Vortex Digital Audio Processor 0 +s 12eb000314626780 AU8810 Vortex Digital Audio Processor 0 +s 12eb000314a42073 AU8810 Vortex Digital Audio Processor 0 +s 12eb000314a42091 AU8810 Vortex Digital Audio Processor 0 +s 12eb000314a42104 AU8810 Vortex Digital Audio Processor 0 +s 12eb000314a42106 AU8810 Vortex Digital Audio Processor 0 +d 12eb8803 Vortex 56k Software Modem 0 +s 12eb880312eb8803 Vortex 56k Software Modem 0 +v 12ec 3A International, Inc. 0 +v 12ed Optivision Inc. 0 +v 12ee Orange Micro 0 +v 12ef Vienna Systems 0 +v 12f0 Pentek 0 +v 12f1 Sorenson Vision Inc 0 +v 12f2 Gammagraphx, Inc. 0 +v 12f3 Radstone Technology 0 +v 12f4 Megatel 0 +v 12f5 Forks 0 +v 12f6 Dawson France 0 +v 12f7 Cognex 0 +v 12f8 Electronic Design GmbH 0 +d 12f80002 VideoMaker 0 +v 12f9 Four Fold Ltd 0 +v 12fb Spectrum Signal Processing 0 +v 12fc Capital Equipment Corp 0 +v 12fd I2S 0 +v 12fe ESD Electronic System Design GmbH 0 +v 12ff Lexicon 0 +v 1300 Harman International Industries Inc 0 +v 1302 Computer Sciences Corp 0 +v 1303 Innovative Integration 0 +v 1304 Juniper Networks 0 +v 1305 Netphone, Inc 0 +v 1306 Duet Technologies 0 +v 1307 Computer Boards 0 +d 13070001 PCI-DAS1602/16 0 +d 1307000b PCI-DIO48H 0 +d 1307000c PCI-PDISO8 0 +d 1307000d PCI-PDISO16 0 +d 1307000f PCI-DAS1200 0 +d 13070010 PCI-DAS1602/12 0 +d 13070014 PCI-DIO24H 0 +d 13070015 PCI-DIO24H/CTR3 0 +d 13070016 PCI-DIO48H/CTR15 0 +d 13070017 PCI-DIO96H 0 +d 13070018 PCI-CTR05 0 +d 13070019 PCI-DAS1200/JR 0 +d 1307001a PCI-DAS1001 0 +d 1307001b PCI-DAS1002 0 +d 1307001c PCI-DAS1602JR/16 0 +d 1307001d PCI-DAS6402/16 0 +d 1307001e PCI-DAS6402/12 0 +d 1307001f PCI-DAS16/M1 0 +d 13070020 PCI-DDA02/12 0 +d 13070021 PCI-DDA04/12 0 +d 13070022 PCI-DDA08/12 0 +d 13070023 PCI-DDA02/16 0 +d 13070024 PCI-DDA04/16 0 +d 13070025 PCI-DDA08/16 0 +d 13070026 PCI-DAC04/12-HS 0 +d 13070027 PCI-DAC04/16-HS 0 +d 13070028 PCI-DIO24 0 +d 13070029 PCI-DAS08 0 +d 1307002c PCI-INT32 0 +d 13070033 PCI-DUAL-AC5 0 +d 13070034 PCI-DAS-TC 0 +d 13070035 PCI-DAS64/M1/16 0 +d 13070036 PCI-DAS64/M2/16 0 +d 13070037 PCI-DAS64/M3/16 0 +d 1307004c PCI-DAS1000 0 +v 1308 Jato Technologies Inc. 0 +d 13080001 NetCelerator Adapter 0 +s 1308000113080001 NetCelerator Adapter 0 +v 1309 AB Semiconductor Ltd 0 +v 130a Mitsubishi Electric Microcomputer 0 +v 130b Colorgraphic Communications Corp 0 +v 130c Ambex Technologies, Inc 0 +v 130d Accelerix Inc 0 +v 130e Yamatake-Honeywell Co. Ltd 0 +v 130f Advanet Inc 0 +v 1310 Gespac 0 +v 1311 Videoserver, Inc 0 +v 1312 Acuity Imaging, Inc 0 +v 1313 Yaskawa Electric Co. 0 +v 1316 Teradyne Inc 0 +v 1317 Linksys 0 +d 13170981 Fast Ethernet 10/100 0 +d 13170985 Network Everywhere Fast Ethernet 10/100 model NC100 0 +d 13171985 Fast Ethernet 10/100 0 +v 1318 Packet Engines Inc. 0 +d 13180911 PCI Ethernet Adapter 0 +v 1319 Fortemedia, Inc 0 +d 13190801 Xwave QS3000A [FM801] 0 +d 13190802 Xwave QS3000A [FM801 game port] 0 +d 13191000 FM801 PCI Audio 0 +d 13191001 FM801 PCI Joystick 0 +v 131a Finisar Corp. 0 +v 131c Nippon Electro-Sensory Devices Corp 0 +v 131d Sysmic, Inc. 0 +v 131e Xinex Networks Inc 0 +v 131f Siig Inc 0 +d 131f1000 CyberSerial (1-port) 16550 0 +d 131f1001 CyberSerial (1-port) 16650 0 +d 131f1002 CyberSerial (1-port) 16850 0 +d 131f1010 Duet 1S(16550)+1P 0 +d 131f1011 Duet 1S(16650)+1P 0 +d 131f1012 Duet 1S(16850)+1P 0 +d 131f1020 CyberParallel (1-port) 0 +d 131f1021 CyberParallel (2-port) 0 +d 131f1030 CyberSerial (2-port) 16550 0 +d 131f1031 CyberSerial (2-port) 16650 0 +d 131f1032 CyberSerial (2-port) 16850 0 +d 131f1034 Trio 2S(16550)+1P 0 +d 131f1035 Trio 2S(16650)+1P 0 +d 131f1036 Trio 2S(16850)+1P 0 +d 131f1050 CyberSerial (4-port) 16550 0 +d 131f1051 CyberSerial (4-port) 16650 0 +d 131f1052 CyberSerial (4-port) 16850 0 +d 131f2000 CyberSerial (1-port) 16550 0 +d 131f2001 CyberSerial (1-port) 16650 0 +d 131f2002 CyberSerial (1-port) 16850 0 +d 131f2010 Duet 1S(16550)+1P 0 +d 131f2011 Duet 1S(16650)+1P 0 +d 131f2012 Duet 1S(16850)+1P 0 +d 131f2020 CyberParallel (1-port) 0 +d 131f2021 CyberParallel (2-port) 0 +d 131f2030 CyberSerial (2-port) 16550 0 +s 131f2030131f2030 PCI Serial Card 0 +d 131f2031 CyberSerial (2-port) 16650 0 +d 131f2032 CyberSerial (2-port) 16850 0 +d 131f2040 Trio 1S(16550)+2P 0 +d 131f2041 Trio 1S(16650)+2P 0 +d 131f2042 Trio 1S(16850)+2P 0 +d 131f2050 CyberSerial (4-port) 16550 0 +d 131f2051 CyberSerial (4-port) 16650 0 +d 131f2052 CyberSerial (4-port) 16850 0 +d 131f2060 Trio 2S(16550)+1P 0 +d 131f2061 Trio 2S(16650)+1P 0 +d 131f2062 Trio 2S(16850)+1P 0 +v 1320 Crypto AG 0 +v 1321 Arcobel Graphics BV 0 +v 1322 MTT Co., Ltd 0 +v 1323 Dome Inc 0 +v 1324 Sphere Communications 0 +v 1325 Salix Technologies, Inc 0 +v 1326 Seachange international 0 +v 1327 Voss scientific 0 +v 1328 quadrant international 0 +v 1329 Productivity Enhancement 0 +v 132a Microcom Inc. 0 +v 132b Broadband Technologies 0 +v 132c Micrel Inc 0 +v 132d Integrated Silicon Solution, Inc. 0 +v 1330 MMC Networks 0 +v 1331 Radisys Corp. 0 +v 1332 Micro Memory 0 +v 1334 Redcreek Communications, Inc 0 +v 1335 Videomail, Inc 0 +v 1337 Third Planet Publishing 0 +v 1338 BT Electronics 0 +v 133a Vtel Corp 0 +v 133b Softcom Microsystems 0 +v 133c Holontech Corp 0 +v 133d SS Technologies 0 +v 133e Virtual Computer Corp 0 +v 133f SCM Microsystems 0 +v 1340 Atalla Corp 0 +v 1341 Kyoto Microcomputer Co 0 +v 1342 Promax Systems Inc 0 +v 1343 Phylon Communications Inc 0 +v 1344 Crucial Technology 0 +v 1345 Arescom Inc 0 +v 1347 Odetics 0 +v 1349 Sumitomo Electric Industries, Ltd. 0 +v 134a DTC Technology Corp. 0 +d 134a0001 Domex 536 0 +d 134a0002 Domex DMX3194UP SCSI Adapter 0 +v 134b ARK Research Corp. 0 +v 134c Chori Joho System Co. Ltd 0 +v 134d PCTel Inc 0 +d 134d7890 HSP MicroModem 56 0 +d 134d7891 HSP MicroModem 56 0 +s 134d7891134d0001 HSP MicroModem 56 0 +d 134d7892 HSP MicroModem 56 0 +d 134d7893 HSP MicroModem 56 0 +d 134d7894 HSP MicroModem 56 0 +d 134d7895 HSP MicroModem 56 0 +d 134d7896 HSP MicroModem 56 0 +d 134d7897 HSP MicroModem 56 0 +v 134e CSTI 0 +v 134f Algo System Co Ltd 0 +v 1350 Systec Co. Ltd 0 +v 1351 Sonix Inc 0 +v 1353 Dassault A.T. 0 +v 1354 Dwave System Inc 0 +v 1355 Kratos Analytical Ltd 0 +v 1356 The Logical Co 0 +v 1359 Prisa Networks 0 +v 135a Brain Boxes 0 +v 135b Giganet Inc 0 +v 135c Quatech Inc 0 +v 135d ABB Network Partner AB 0 +v 135e Sealevel Systems Inc 0 +d 135e7101 Single Port RS-232/422/485/530 0 +d 135e7201 Dual Port RS-232/422/485 Interface 0 +d 135e7202 Dual Port RS-232 Interface 0 +d 135e7401 Four Port RS-232 Interface 0 +d 135e7402 Four Port RS-422/485 Interface 0 +d 135e7801 Eight Port RS-232 Interface 0 +d 135e8001 8001 Digital I/O Adapter 0 +v 135f I-Data International A-S 0 +v 1360 Meinberg Funkuhren 0 +v 1361 Soliton Systems K.K. 0 +v 1362 Fujifacom Corporation 0 +v 1363 Phoenix Technology Ltd 0 +v 1364 ATM Communications Inc 0 +v 1365 Hypercope GmbH 0 +v 1366 Teijin Seiki Co. Ltd 0 +v 1367 Hitachi Zosen Corporation 0 +v 1368 Skyware Corporation 0 +v 1369 Digigram 0 +v 136a High Soft Tech 0 +v 136b Kawasaki Steel Corporation 0 +v 136c Adtek System Science Co Ltd 0 +v 136d Gigalabs Inc 0 +v 136f Applied Magic Inc 0 +v 1370 ATL Products 0 +v 1371 CNet Technology Inc 0 +v 1373 Silicon Vision Inc 0 +v 1374 Silicom Ltd 0 +v 1375 Argosystems Inc 0 +v 1376 LMC 0 +v 1377 Electronic Equipment Production & Distribution GmbH 0 +v 1378 Telemann Co. Ltd 0 +v 1379 Asahi Kasei Microsystems Co Ltd 0 +v 137a Mark of the Unicorn Inc 0 +v 137b PPT Vision 0 +v 137c Iwatsu Electric Co Ltd 0 +v 137d Dynachip Corporation 0 +v 137e Patriot Scientific Corporation 0 +v 137f Japan Satellite Systems Inc 0 +v 1380 Sanritz Automation Co Ltd 0 +v 1381 Brains Co. Ltd 0 +v 1382 Marian - Electronic & Software 0 +v 1383 Controlnet Inc 0 +v 1384 Reality Simulation Systems Inc 0 +v 1385 Netgear 0 +d 1385620a GA620 0 +d 1385622a GA622 0 +d 1385630a GA630 0 +d 1385f311 FA311 0 +v 1386 Video Domain Technologies 0 +v 1387 Systran Corp 0 +v 1388 Hitachi Information Technology Co Ltd 0 +v 1389 Applicom International 0 +d 13890001 PCI1500PFB [Intelligent fieldbus adaptor] 0 +v 138a Fusion Micromedia Corp 0 +v 138b Tokimec Inc 0 +v 138c Silicon Reality 0 +v 138d Future Techno Designs pte Ltd 0 +v 138e Basler GmbH 0 +v 138f Patapsco Designs Inc 0 +v 1390 Concept Development Inc 0 +v 1391 Development Concepts Inc 0 +v 1392 Medialight Inc 0 +v 1393 Moxa Technologies Co Ltd 0 +d 13931040 Smartio C104H/PCI 0 +d 13931680 Smartio C168H/PCI 0 +d 13932040 Intellio CP-204J 0 +d 13932180 Intellio C218 Turbo PCI 0 +d 13933200 Intellio C320 Turbo PCI 0 +v 1394 Level One Communications 0 +v 1395 Ambicom Inc 0 +v 1396 Cipher Systems Inc 0 +v 1397 Cologne Chip Designs GmbH 0 +d 13972bd0 ISDN network controller [HFC-PCI] 0 +s 13972bd013972bd0 ISDN Board 0 +s 13972bd0e4bf1000 CI1-1-Harp 0 +v 1398 Clarion co. Ltd 0 +v 1399 Rios systems Co Ltd 0 +v 139a Alacritech Inc 0 +v 139b Mediasonic Multimedia Systems Ltd 0 +v 139c Quantum 3d Inc 0 +v 139d EPL limited 0 +v 139e Media4 0 +v 139f Aethra s.r.l. 0 +v 13a0 Crystal Group Inc 0 +v 13a1 Kawasaki Heavy Industries Ltd 0 +v 13a2 Ositech Communications Inc 0 +v 13a3 Hifn Inc. 0 +d 13a30005 7751 Security Processor 0 +d 13a30006 6500 Public Key Processor 0 +d 13a30007 7811 Security Processor 0 +d 13a30012 7951 Security Processor 0 +v 13a4 Rascom Inc 0 +v 13a5 Audio Digital Imaging Inc 0 +v 13a6 Videonics Inc 0 +v 13a7 Teles AG 0 +v 13a8 Exar Corp. 0 +v 13a9 Siemens Medical Systems, Ultrasound Group 0 +v 13aa Broadband Networks Inc 0 +v 13ab Arcom Control Systems Ltd 0 +v 13ac Motion Media Technology Ltd 0 +v 13ad Nexus Inc 0 +v 13ae ALD Technology Ltd 0 +v 13af T.Sqware 0 +v 13b0 Maxspeed Corp 0 +v 13b1 Tamura corporation 0 +v 13b2 Techno Chips Co. Ltd 0 +v 13b3 Lanart Corporation 0 +v 13b4 Wellbean Co Inc 0 +v 13b5 ARM 0 +v 13b6 Dlog GmbH 0 +v 13b7 Logic Devices Inc 0 +v 13b8 Nokia Telecommunications oy 0 +v 13b9 Elecom Co Ltd 0 +v 13ba Oxford Instruments 0 +v 13bb Sanyo Technosound Co Ltd 0 +v 13bc Bitran Corporation 0 +v 13bd Sharp corporation 0 +v 13be Miroku Jyoho Service Co. Ltd 0 +v 13bf Sharewave Inc 0 +v 13c0 Microgate Corporation 0 +d 13c00010 SyncLink WAN Adapter 0 +v 13c1 3ware Inc 0 +d 13c11000 3ware ATA-RAID 0 +d 13c11001 3ware 7000-series ATA-RAID 0 +v 13c2 Technotrend Systemtechnik GmbH 0 +v 13c3 Janz Computer AG 0 +v 13c4 Phase Metrics 0 +v 13c5 Alphi Technology Corp 0 +v 13c6 Condor Engineering Inc 0 +v 13c7 Blue Chip Technology Ltd 0 +v 13c8 Apptech Inc 0 +v 13c9 Eaton Corporation 0 +v 13ca Iomega Corporation 0 +v 13cb Yano Electric Co Ltd 0 +v 13cc Metheus Corporation 0 +v 13cd Compatible Systems Corporation 0 +v 13ce Cocom A/S 0 +v 13cf Studio Audio & Video Ltd 0 +v 13d0 Techsan Electronics Co Ltd 0 +v 13d1 Abocom Systems Inc 0 +v 13d2 Shark Multimedia Inc 0 +v 13d3 IMC Networks 0 +v 13d4 Graphics Microsystems Inc 0 +v 13d5 Media 100 Inc 0 +v 13d6 K.I. Technology Co Ltd 0 +v 13d7 Toshiba Engineering Corporation 0 +v 13d8 Phobos corporation 0 +v 13d9 Apex PC Solutions Inc 0 +v 13da Intresource Systems pte Ltd 0 +v 13db Janich & Klass Computertechnik GmbH 0 +v 13dc Netboost Corporation 0 +v 13dd Multimedia Bundle Inc 0 +v 13de ABB Robotics Products AB 0 +v 13df E-Tech Inc 0 +d 13df0001 PCI56RVP Modem 0 +s 13df000113df0001 PCI56RVP Modem 0 +v 13e0 GVC Corporation 0 +v 13e1 Silicom Multimedia Systems Inc 0 +v 13e2 Dynamics Research Corporation 0 +v 13e3 Nest Inc 0 +v 13e4 Calculex Inc 0 +v 13e5 Telesoft Design Ltd 0 +v 13e6 Argosy research Inc 0 +v 13e7 NAC Incorporated 0 +v 13e8 Chip Express Corporation 0 +v 13e9 Chip Express Corporation 0 +v 13ea Dallas Semiconductor 0 +v 13eb Hauppauge Computer Works Inc 0 +v 13ec Zydacron Inc 0 +v 13ed Raytheion E-Systems 0 +v 13ee Hayes Microcomputer Products Inc 0 +v 13ef Coppercom Inc 0 +v 13f0 Sundance Technology Inc 0 +d 13f00201 Sundance Ethernet 0 +v 13f1 Oce' - Technologies B.V. 0 +v 13f2 Ford Microelectronics Inc 0 +v 13f3 Mcdata Corporation 0 +v 13f4 Troika Networks, Inc. 0 +d 13f41401 Zentai Fibre Channel Adapter 0 +v 13f5 Kansai Electric Co. Ltd 0 +v 13f6 C-Media Electronics Inc 0 +d 13f60100 CM8338A 0 +s 13f6010013f6ffff CMI8338/C3DX PCI Audio Device 0 +d 13f60101 CM8338B 0 +s 13f6010113f60101 CMI8338-031 PCI Audio Device 0 +d 13f60111 CM8738 0 +s 13f6011113f60111 CMI8738/C3DX PCI Audio Device 0 +d 13f60211 CM8738 0 +d 13f61106 1 +v 13f7 Wildfire Communications 0 +v 13f8 Ad Lib Multimedia Inc 0 +v 13f9 NTT Advanced Technology Corp. 0 +v 13fa Pentland Systems Ltd 0 +v 13fb Aydin Corp 0 +v 13fc Computer Peripherals International 0 +v 13fd Micro Science Inc 0 +v 13fe Advantech Co. Ltd 0 +v 13ff Silicon Spice Inc 0 +v 1400 Artx Inc 0 +d 14001401 9432 TX 0 +v 1401 CR-Systems A/S 0 +v 1402 Meilhaus Electronic GmbH 0 +v 1403 Ascor Inc 0 +v 1404 Fundamental Software Inc 0 +v 1405 Excalibur Systems Inc 0 +v 1406 Oce' Printing Systems GmbH 0 +v 1407 Lava Computer mfg Inc 0 +v 1407 Lava Computer mfg Inc 1 The quad card have a new number 120 121 +d 14070100 Lava Dual Serial 0 +d 14070101 Lava Quatro A 0 +d 14070102 Lava Quatro B 0 +d 14070200 Lava Port Plus 0 +d 14070201 Lava Quad A 0 +d 14070202 Lava Quad B 0 +d 14070500 Lava Single Serial 0 +d 14070600 Lava Port 650 0 +d 14078000 Lava Parallel 0 +d 14078002 Lava Dual Parallel port A 0 +d 14078003 Lava Dual Parallel port B 0 +d 14078800 BOCA Research IOPPAR 0 +v 1408 Aloka Co. Ltd 0 +v 1409 Timedia Technology Co Ltd 0 +v 140a DSP Research Inc 0 +v 140b Ramix Inc 0 +v 140c Elmic Systems Inc 0 +v 140d Matsushita Electric Works Ltd 0 +v 140e Goepel Electronic GmbH 0 +v 140f Salient Systems Corp 0 +v 1410 Midas lab Inc 0 +v 1411 Ikos Systems Inc 0 +v 1412 IC Ensemble Inc 0 +d 14121712 ICE1712 [Envy24] 0 +v 1413 Addonics 0 +v 1414 Microsoft Corporation 0 +v 1415 Oxford Semiconductor Ltd 0 +d 14158403 VScom 011H-EP1 1 port parallel adaptor 0 +v 1416 Multiwave Innovation pte Ltd 0 +v 1417 Convergenet Technologies Inc 0 +v 1418 Kyushu electronics systems Inc 0 +v 1419 Excel Switching Corp 0 +v 141a Apache Micro Peripherals Inc 0 +v 141b Zoom Telephonics Inc 0 +v 141d Digitan Systems Inc 0 +v 141e Fanuc Ltd 0 +v 141f Visiontech Ltd 0 +v 1420 Psion Dacom plc 0 +v 1421 Ads Technologies Inc 0 +v 1422 Ygrec Systems Co Ltd 0 +v 1423 Custom Technology Corp. 0 +v 1424 Videoserver Connections 0 +v 1425 ASIC Designers Inc 0 +v 1426 Storage Technology Corp. 0 +v 1427 Better On-Line Solutions 0 +v 1428 Edec Co Ltd 0 +v 1429 Unex Technology Corp. 0 +v 142a Kingmax Technology Inc 0 +v 142b Radiolan 0 +v 142c Minton Optic Industry Co Ltd 0 +v 142d Pix stream Inc 0 +v 142e Vitec Multimedia 0 +v 142f Radicom Research Inc 0 +v 1430 ITT Aerospace/Communications Division 0 +v 1431 Gilat Satellite Networks 0 +v 1432 Edimax Computer Co. 0 +v 1433 Eltec Elektronik GmbH 0 +v 1435 Real Time Devices US Inc. 0 +v 1436 CIS Technology Inc 0 +v 1437 Nissin Inc Co 0 +v 1438 Atmel-dream 0 +v 1439 Outsource Engineering & Mfg. Inc 0 +v 143a Stargate Solutions Inc 0 +v 143b Canon Research Center, America 0 +v 143c Amlogic Inc 0 +v 143d Tamarack Microelectronics Inc 0 +v 143e Jones Futurex Inc 0 +v 143f Lightwell Co Ltd - Zax Division 0 +v 1440 ALGOL Corp. 0 +v 1441 AGIE Ltd 0 +v 1442 Phoenix Contact GmbH & Co. 0 +v 1443 Unibrain S.A. 0 +v 1444 TRW 0 +v 1445 Logical DO Ltd 0 +v 1446 Graphin Co Ltd 0 +v 1447 AIM GmBH 0 +v 1448 Alesis Studio Electronics 0 +v 1449 TUT Systems Inc 0 +v 144a Adlink Technology 0 +d 144a7296 PCI-7296 0 +d 144a7432 PCI-7432 0 +d 144a7433 PCI-7433 0 +d 144a7434 PCI-7434 0 +d 144a7841 PCI-7841 0 +d 144a8133 PCI-8133 0 +d 144a8554 PCI-8554 0 +d 144a9111 PCI-9111 0 +d 144a9113 PCI-9113 0 +d 144a9114 PCI-9114 0 +v 144b Loronix Information Systems Inc 0 +v 144c Catalina Research Inc 0 +v 144d Samsung Electronics Co Ltd 0 +v 144e OLITEC 0 +v 144f Askey Computer Corp. 0 +v 1450 Octave Communications Ind. 0 +v 1451 SP3D Chip Design GmBH 0 +v 1453 MYCOM Inc 0 +v 1454 Altiga Networks 0 +v 1455 Logic Plus Plus Inc 0 +v 1456 Advanced Hardware Architectures 0 +v 1457 Nuera Communications Inc 0 +v 1458 Giga-byte Technology 0 +v 1459 DOOIN Electronics 0 +v 145a Escalate Networks Inc 0 +v 145b PRAIM SRL 0 +v 145c Cryptek 0 +v 145d Gallant Computer Inc 0 +v 145e Aashima Technology B.V. 0 +v 145f Baldor Electric Company 0 +d 145f0001 NextMove PCI 0 +v 1460 DYNARC INC 0 +v 1461 Avermedia Technologies Inc 0 +v 1462 Micro-star International Co Ltd 0 +v 1463 Fast Corporation 0 +v 1464 Interactive Circuits & Systems Ltd 0 +v 1465 GN NETTEST Telecom DIV. 0 +v 1466 Designpro Inc. 0 +v 1467 DIGICOM SPA 0 +v 1468 AMBIT Microsystem Corp. 0 +v 1469 Cleveland Motion Controls 0 +v 146a IFR 0 +v 146b Parascan Technologies Ltd 0 +v 146c Ruby Tech Corp. 0 +v 146d Tachyon, INC. 0 +v 146e Williams Electronics Games, Inc. 0 +v 146f Multi Dimensional Consulting Inc 0 +v 1470 Bay Networks 0 +v 1471 Integrated Telecom Express Inc 0 +v 1472 DAIKIN Industries, Ltd 0 +v 1473 ZAPEX Technologies Inc 0 +v 1474 Doug Carson & Associates 0 +v 1475 PICAZO Communications 0 +v 1476 MORTARA Instrument Inc 0 +v 1477 Net Insight 0 +v 1478 DIATREND Corporation 0 +v 1479 TORAY Industries Inc 0 +v 147a FORMOSA Industrial Computing 0 +v 147b ABIT Computer Corp. 0 +v 147c AWARE, Inc. 0 +v 147d Interworks Computer Products 0 +v 147e Matsushita Graphic Communication Systems, Inc. 0 +v 147f NIHON UNISYS, Ltd. 0 +v 1480 SCII Telecom 0 +v 1481 BIOPAC Systems Inc 0 +v 1482 ISYTEC - Integrierte Systemtechnik GmBH 0 +v 1483 LABWAY Corporation 0 +v 1484 Logic Corporation 0 +v 1485 ERMA - Electronic GmBH 0 +v 1486 L3 Communications Telemetry & Instrumentation 0 +v 1487 MARQUETTE Medical Systems 0 +v 1488 KONTRON Electronik GmBH 0 +v 1489 KYE Systems Corporation 0 +v 148a OPTO 0 +v 148b INNOMEDIALOGIC Inc. 0 +v 148c C.P. Technology Co. Ltd 0 +v 148d DIGICOM Systems, Inc. 0 +d 148d1003 HCF 56k Data/Fax Modem 0 +v 148e OSI Plus Corporation 0 +v 148f Plant Equipment, Inc. 0 +v 1490 Stone Microsystems PTY Ltd. 0 +v 1491 ZEAL Corporation 0 +v 1492 Time Logic Corporation 0 +v 1493 MAKER Communications 0 +v 1494 WINTOP Technology, Inc. 0 +v 1495 TOKAI Communications Industry Co. Ltd 0 +v 1496 JOYTECH Computer Co., Ltd. 0 +v 1497 SMA Regelsysteme GmBH 0 +v 1498 TEWS Datentechnik GmBH 0 +v 1499 EMTEC CO., Ltd 0 +v 149a ANDOR Technology Ltd 0 +v 149b SEIKO Instruments Inc 0 +v 149c OVISLINK Corp. 0 +v 149d NEWTEK Inc 0 +v 149e Mapletree Networks Inc. 0 +v 149f LECTRON Co Ltd 0 +v 14a0 SOFTING GmBH 0 +v 14a1 Systembase Co Ltd 0 +v 14a2 Millennium Engineering Inc 0 +v 14a3 Maverick Networks 0 +v 14a4 GVC/BCM Advanced Research 0 +v 14a5 XIONICS Document Technologies Inc 0 +v 14a6 INOVA Computers GmBH & Co KG 0 +v 14a7 MYTHOS Systems Inc 0 +v 14a8 FEATRON Technologies Corporation 0 +v 14a9 HIVERTEC Inc 0 +v 14aa Advanced MOS Technology Inc 0 +v 14ab Mentor Graphics Corp. 0 +v 14ac Novaweb Technologies Inc 0 +v 14ad Time Space Radio AB 0 +v 14ae CTI, Inc 0 +v 14af Guillemot Corporation 0 +v 14b0 BST Communication Technology Ltd 0 +v 14b1 Nextcom K.K. 0 +v 14b2 ENNOVATE Networks Inc 0 +v 14b3 XPEED Inc 0 +d 14b30000 DSL NIC 0 +v 14b4 PHILIPS Business Electronics B.V. 0 +v 14b5 Creamware GmBH 0 +v 14b6 Quantum Data Corp. 0 +v 14b7 PROXIM Inc 0 +d 14b70001 Symphony 4110 0 +v 14b8 Techsoft Technology Co Ltd 0 +v 14b9 AIRONET Wireless Communications 0 +d 14b90001 PC4800 0 +v 14ba INTERNIX Inc. 0 +v 14bb SEMTECH Corporation 0 +v 14bc Globespan Semiconductor Inc. 0 +v 14bd CARDIO Control N.V. 0 +v 14be L3 Communications 0 +v 14bf SPIDER Communications Inc. 0 +v 14c0 COMPAL Electronics Inc 0 +v 14c1 MYRICOM Inc. 0 +v 14c2 DTK Computer 0 +v 14c3 MEDIATEK Corp. 0 +v 14c4 IWASAKI Information Systems Co Ltd 0 +v 14c5 Automation Products AB 0 +v 14c6 Data Race Inc 0 +v 14c7 Modular Technology Holdings Ltd 0 +v 14c8 Turbocomm Tech. Inc. 0 +v 14c9 ODIN Telesystems Inc 0 +v 14ca PE Logic Corp. 0 +v 14cb Billionton Systems Inc 0 +v 14cc NAKAYO Telecommunications Inc 0 +v 14cd Universal Scientific Ind. 0 +v 14ce Whistle Communications 0 +v 14cf TEK Microsystems Inc. 0 +v 14d0 Ericsson Axe R & D 0 +v 14d1 Computer Hi-Tech Co Ltd 0 +v 14d2 Titan Electronics Inc 0 +d 14d28001 VScom 010L 1 port parallel adaptor 0 +d 14d28002 VScom 020L 2 port parallel adaptor 0 +d 14d28010 VScom 100L 1 port serial adaptor 0 +d 14d28011 VScom 110L 1 port serial and 1 port parallel adaptor 0 +d 14d28020 VScom 200L 1 port serial adaptor 0 +d 14d28021 VScom 210L 2 port serial and 1 port parallel adaptor 0 +d 14d28040 VScom 400L 4 port serial adaptor 0 +d 14d28080 VScom 800L 8 port serial adaptor 0 +d 14d2a000 VScom 010H 1 port parallel adaptor 0 +d 14d2a001 VScom 100H 1 port serial adaptor 0 +d 14d2a003 VScom 400H 4 port serial adaptor 0 +d 14d2a004 VScom 400HF1 4 port serial adaptor 0 +d 14d2a005 VScom 200H 2 port serial adaptor 0 +d 14d2e001 VScom 010HV2 1 port parallel adaptor 0 +d 14d2e010 VScom 100HV2 1 port serial adaptor 0 +d 14d2e020 VScom 200HV2 2 port serial adaptor 0 +v 14d3 CIRTECH (UK) Ltd 0 +v 14d4 Panacom Technology Corp 0 +v 14d5 Nitsuko Corporation 0 +v 14d6 Accusys Inc 0 +v 14d7 Hirakawa Hewtech Corp 0 +v 14d8 HOPF Elektronik GmBH 0 +v 14d9 Alpha Processor Inc 0 +v 14da National Aerospace Laboratories 0 +v 14db AFAVLAB Technology Inc 0 +d 14db2120 TK9902 0 +v 14dc Amplicon Liveline Ltd 0 +d 14dc0000 PCI230 0 +d 14dc0001 PCI242 0 +d 14dc0002 PCI244 0 +d 14dc0003 PCI247 0 +d 14dc0004 PCI248 0 +d 14dc0005 PCI249 0 +d 14dc0006 PCI260 0 +d 14dc0007 PCI224 0 +d 14dc0008 PCI234 0 +d 14dc0009 PCI236 0 +v 14dd Boulder Design Labs Inc 0 +v 14de Applied Integration Corporation 0 +v 14df ASIC Communications Corp 0 +v 14e1 INVERTEX 0 +v 14e2 INFOLIBRIA 0 +v 14e3 AMTELCO 0 +v 14e4 BROADCOM Corporation 0 +d 14e41644 NetXtreme BCM5700 Gigabit Ethernet 0 +s 14e4164410b71000 3C996-T 1000BaseTX 0 +s 14e4164410b71001 3C996B-T 1000BaseTX 0 +s 14e4164410b71002 3C996C-T 1000BaseTX 0 +s 14e4164410b71003 3C997-T 1000BaseTX Dual Port 0 +s 14e4164410b71004 3C996-SX 1000BaseSX 0 +s 14e4164410b71005 3C997-SX 1000BaseSX Dual Port 0 +s 14e4164414e40002 NetXtreme 1000BaseSX 0 +s 14e4164414e40003 NetXtreme 1000BaseSX 0 +s 14e4164414e40004 NetXtreme 1000BaseTX 0 +s 14e4164414e41028 NetXtreme 1000BaseTX 0 +s 14e4164414e41644 NetXtreme BCM5700 1000BaseTX 0 +d 14e41645 NetXtreme BCM5701 Gigabit Ethernet 0 +s 14e416450e11007c NC7770 Gigabit Server Adapter (PCI-X, 10/100/1000-T) 0 +s 14e416450e11007d NC6770 Gigabit Server Adapter (PCI-X, 1000-SX) 0 +s 14e416450e110085 NC7780 Gigabit Server Adapter (embedded, WOL) 0 +s 14e416450e110099 NC7780 Gigabit Server Adapter (embedded, WOL) 0 +s 14e416450e11009a NC7770 Gigabit Server Adapter (PCI-X, 10/100/1000-T) 0 +s 14e4164510b71004 3C996-SX 1000BaseSX 0 +s 14e4164510b71006 3C996B-T 1000BaseTX 0 +s 14e4164510b71007 3C1000-T 1000BaseTX 0 +s 14e4164510b71008 3C940-BR01 1000BaseTX 0 +s 14e4164514e40001 NetXtreme BCM5701 1000BaseTX 0 +s 14e4164514e40005 NetXtreme BCM5701 1000BaseTX 0 +s 14e4164514e40006 NetXtreme BCM5701 1000BaseTX 0 +s 14e4164514e40007 NetXtreme BCM5701 1000BaseSX 0 +s 14e4164514e40008 NetXtreme BCM5701 1000BaseTX 0 +s 14e4164514e48008 NetXtreme BCM5701 1000BaseTX 0 +d 14e41647 NetXtreme BCM5703 Gigabit Ethernet 0 +d 14e44212 BCM v.90 56k modem 1 Controllerless PCI modem +d 14e45820 BCM5820 Crypto Accelerator 0 +v 14e5 Pixelfusion Ltd 0 +v 14e6 SHINING Technology Inc 0 +v 14e7 3CX 0 +v 14e8 RAYCER Inc 0 +v 14e9 GARNETS System CO Ltd 0 +v 14ea PLANEX COMMUNICATIONS Inc 0 +v 14eb SEIKO EPSON Corp 0 +v 14ec ACQIRIS 0 +v 14ed DATAKINETICS Ltd 0 +v 14ee MASPRO KENKOH Corp 0 +v 14ef CARRY Computer ENG. CO Ltd 0 +v 14f0 CANON RESEACH CENTRE FRANCE 0 +v 14f1 Conexant 0 +d 14f11002 HCF 56k Modem 0 +d 14f11003 HCF 56k Modem 0 +d 14f11004 HCF 56k Modem 0 +d 14f11005 HCF 56k Modem 0 +d 14f11006 HCF 56k Modem 0 +d 14f11022 HCF 56k Modem 0 +d 14f11023 HCF 56k Modem 0 +d 14f11024 HCF 56k Modem 0 +d 14f11025 HCF 56k Modem 0 +d 14f11026 HCF 56k Modem 0 +d 14f11032 HCF 56k Modem 0 +d 14f11033 HCF 56k Data/Fax Modem 0 +s 14f1103310338077 NEC 0 +s 14f11033122d4027 Dell Zeus - MDP3880-W(B) Data Fax Modem 0 +s 14f11033122d4030 Dell Mercury - MDP3880-U(B) Data Fax Modem 0 +s 14f11033122d4034 Dell Thor - MDP3880-W(U) Data Fax Modem 0 +s 14f1103313e0020d Dell Copper 0 +s 14f1103313e0020e Dell Silver 0 +s 14f1103313e00261 IBM # GVC 0 +s 14f1103313e00290 Compaq Goldwing 0 +s 14f1103313e002a0 IBM # GVC 0 +s 14f1103313e002b0 IBM # GVC 0 +s 14f1103313e002c0 Compaq Scooter 0 +s 14f1103313e002d0 IBM # GVC 0 +s 14f11033144f1500 IBM P85-DF (1) 0 +s 14f11033144f1501 IBM P85-DF (2) 0 +s 14f11033144f150a IBM P85-DF (3) 0 +s 14f11033144f150b IBM P85-DF Low Profile (1) 0 +s 14f11033144f1510 IBM P85-DF Low Profile (2) 0 +d 14f11034 HCF 56k Data/Fax/Voice Modem 0 +d 14f11035 HCF 56k Data/Fax/Voice/Spkp (w/Handset) Modem 0 +s 14f1103510cf1098 Fujitsu P85-DFSV 0 +d 14f11036 HCF 56k Data/Fax/Voice/Spkp Modem 0 +s 14f11036104d8067 HCF 56k Modem 0 +s 14f11036122d4029 MDP3880SP-W 0 +s 14f11036122d4031 MDP3880SP-U 0 +s 14f1103613e00209 Dell Titanium 0 +s 14f1103613e0020a Dell Graphite 0 +s 14f1103613e00260 Gateway Red Owl 0 +s 14f1103613e00270 Gateway White Horse 0 +d 14f11052 HCF 56k Data/Fax Modem (Worldwide) 0 +d 14f11053 HCF 56k Data/Fax Modem (Worldwide) 0 +d 14f11054 HCF 56k Data/Fax/Voice Modem (Worldwide) 0 +d 14f11055 HCF 56k Data/Fax/Voice/Spkp (w/Handset) Modem (Worldwide) 0 +d 14f11056 HCF 56k Data/Fax/Voice/Spkp Modem (Worldwide) 0 +d 14f11057 HCF 56k Data/Fax/Voice/Spkp Modem (Worldwide) 0 +d 14f11059 HCF 56k Data/Fax/Voice Modem (Worldwide) 0 +d 14f11063 HCF 56k Data/Fax Modem 0 +d 14f11064 HCF 56k Data/Fax/Voice Modem 0 +d 14f11065 HCF 56k Data/Fax/Voice/Spkp (w/Handset) Modem 0 +d 14f11066 HCF 56k Data/Fax/Voice/Spkp Modem 0 +s 14f11066122d4033 Dell Athena - MDP3900V-U 0 +d 14f11433 HCF 56k Data/Fax Modem 0 +d 14f11434 HCF 56k Data/Fax/Voice Modem 0 +d 14f11435 HCF 56k Data/Fax/Voice/Spkp (w/Handset) Modem 0 +d 14f11436 HCF 56k Data/Fax Modem 0 +d 14f11453 HCF 56k Data/Fax Modem 0 +s 14f1145313e00240 IBM # GVC 0 +s 14f1145313e00250 IBM # GVC 0 +s 14f11453144f1502 IBM P95-DF (1) 0 +s 14f11453144f1503 IBM P95-DF (2) 0 +d 14f11454 HCF 56k Data/Fax/Voice Modem 0 +d 14f11455 HCF 56k Data/Fax/Voice/Spkp (w/Handset) Modem 0 +d 14f11456 HCF 56k Data/Fax/Voice/Spkp Modem 0 +s 14f11456122d4035 Dell Europa - MDP3900V-W 0 +s 14f11456122d4302 Dell MP3930V-W(C) MiniPCI 0 +d 14f11803 HCF 56k Modem 0 +s 14f118030e110023 623-LAN Grizzly 0 +s 14f118030e110043 623-LAN Yogi 0 +d 14f11815 HCF 56k Modem 0 +s 14f118150e110022 Grizzly 0 +s 14f118150e110042 Yogi 0 +d 14f12003 HSF 56k Data/Fax Modem 0 +d 14f12004 HSF 56k Data/Fax/Voice Modem 0 +d 14f12005 HSF 56k Data/Fax/Voice/Spkp (w/Handset) Modem 0 +d 14f12006 HSF 56k Data/Fax/Voice/Spkp Modem 0 +d 14f12013 HSF 56k Data/Fax Modem 0 +s 14f120130e11b195 Bear 0 +s 14f120130e11b196 Seminole 1 0 +s 14f120130e11b1be Seminole 2 0 +s 14f1201310258013 Acer 0 +s 14f120131033809d NEC 0 +s 14f12013103380bc NEC 0 +s 14f12013155d6793 HP 0 +s 14f12013155d8850 E Machines 0 +d 14f12014 HSF 56k Data/Fax/Voice Modem 0 +d 14f12015 HSF 56k Data/Fax/Voice/Spkp (w/Handset) Modem 0 +d 14f12016 HSF 56k Data/Fax/Voice/Spkp Modem 0 +d 14f12043 HSF 56k Data/Fax Modem (WorldW SmartDAA) 0 +d 14f12044 HSF 56k Data/Fax/Voice Modem (WorldW SmartDAA) 0 +d 14f12045 HSF 56k Data/Fax/Voice/Spkp (w/Handset) Modem (WorldW SmartDAA) 0 +d 14f12046 HSF 56k Data/Fax/Voice/Spkp Modem (WorldW SmartDAA) 0 +d 14f12063 HSF 56k Data/Fax Modem (SmartDAA) 0 +d 14f12064 HSF 56k Data/Fax/Voice Modem (SmartDAA) 0 +d 14f12065 HSF 56k Data/Fax/Voice/Spkp (w/Handset) Modem (SmartDAA) 0 +d 14f12066 HSF 56k Data/Fax/Voice/Spkp Modem (SmartDAA) 0 +d 14f12093 HSF 56k Modem 0 +s 14f12093155d2f07 Legend 0 +d 14f12143 HSF 56k Data/Fax/Cell Modem (Mob WorldW SmartDAA) 0 +d 14f12144 HSF 56k Data/Fax/Voice/Cell Modem (Mob WorldW SmartDAA) 0 +d 14f12145 HSF 56k Data/Fax/Voice/Spkp (w/HS)/Cell Modem (Mob WorldW SmartDAA) 0 +d 14f12146 HSF 56k Data/Fax/Voice/Spkp/Cell Modem (Mob WorldW SmartDAA) 0 +d 14f12163 HSF 56k Data/Fax/Cell Modem (Mob SmartDAA) 0 +d 14f12164 HSF 56k Data/Fax/Voice/Cell Modem (Mob SmartDAA) 0 +d 14f12165 HSF 56k Data/Fax/Voice/Spkp (w/HS)/Cell Modem (Mob SmartDAA) 0 +d 14f12166 HSF 56k Data/Fax/Voice/Spkp/Cell Modem (Mob SmartDAA) 0 +d 14f12343 HSF 56k Data/Fax CardBus Modem (Mob WorldW SmartDAA) 0 +d 14f12344 HSF 56k Data/Fax/Voice CardBus Modem (Mob WorldW SmartDAA) 0 +d 14f12345 HSF 56k Data/Fax/Voice/Spkp (w/HS) CardBus Modem (Mob WorldW SmartDAA) 0 +d 14f12346 HSF 56k Data/Fax/Voice/Spkp CardBus Modem (Mob WorldW SmartDAA) 0 +d 14f12363 HSF 56k Data/Fax CardBus Modem (Mob SmartDAA) 0 +d 14f12364 HSF 56k Data/Fax/Voice CardBus Modem (Mob SmartDAA) 0 +d 14f12365 HSF 56k Data/Fax/Voice/Spkp (w/HS) CardBus Modem (Mob SmartDAA) 0 +d 14f12366 HSF 56k Data/Fax/Voice/Spkp CardBus Modem (Mob SmartDAA) 0 +d 14f12443 HSF 56k Data/Fax Modem (Mob WorldW SmartDAA) 0 +s 14f12443104d8075 Modem # Sony 0 +s 14f12443104d8083 Modem # Sony 0 +s 14f12443104d8097 Modem # Sony 0 +d 14f12444 HSF 56k Data/Fax/Voice Modem (Mob WorldW SmartDAA) 0 +d 14f12445 HSF 56k Data/Fax/Voice/Spkp (w/HS) Modem (Mob WorldW SmartDAA) 0 +d 14f12446 HSF 56k Data/Fax/Voice/Spkp Modem (Mob WorldW SmartDAA) 0 +d 14f12463 HSF 56k Data/Fax Modem (Mob SmartDAA) 0 +d 14f12464 HSF 56k Data/Fax/Voice Modem (Mob SmartDAA) 0 +d 14f12465 HSF 56k Data/Fax/Voice/Spkp (w/HS) Modem (Mob SmartDAA) 0 +d 14f12466 HSF 56k Data/Fax/Voice/Spkp Modem (Mob SmartDAA) 0 +d 14f12f00 HSF 56k HSFi Modem 0 +s 14f12f0013e08d84 IBM HSFi V.90 0 +s 14f12f0013e08d85 Compaq Stinger 0 +v 14f2 MOBILITY Electronics 0 +v 14f3 BROADLOGIC 0 +v 14f4 TOKYO Electronic Industry CO Ltd 0 +v 14f5 SOPAC Ltd 0 +v 14f6 COYOTE Technologies LLC 0 +v 14f7 WOLF Technology Inc 0 +v 14f8 AUDIOCODES Inc 0 +v 14f9 AG COMMUNICATIONS 0 +v 14fa WANDEL & GOCHERMANN 0 +v 14fb TRANSAS MARINE (UK) Ltd 0 +v 14fc QUADRICS Supercomputers World 0 +v 14fd JAPAN Computer Industry Inc 0 +v 14fe ARCHTEK TELECOM Corp 0 +v 14ff TWINHEAD INTERNATIONAL Corp 0 +v 1500 DELTA Electronics, Inc 0 +v 1501 BANKSOFT CANADA Ltd 0 +v 1502 MITSUBISHI ELECTRIC LOGISTICS SUPPORT Co Ltd 0 +v 1503 KAWASAKI LSI USA Inc 0 +v 1504 KAISER Electronics 0 +v 1505 ITA INGENIEURBURO FUR TESTAUFGABEN GmbH 0 +v 1506 CHAMELEON Systems Inc 0 +v 1507 Motorola ?? / HTEC 0 Should be HTEC Ltd, but there are no known HTEC chips and 1507 is already used by mistake by Motorola (see vendor ID 1057). +d 15070001 MPC105 [Eagle] 0 +d 15070002 MPC106 [Grackle] 0 +d 15070003 MPC8240 [Kahlua] 0 +d 15070100 MC145575 [HFC-PCI] 0 +d 15070431 KTI829c 100VG 0 +d 15074801 Raven 0 +d 15074802 Falcon 0 +d 15074803 Hawk 0 +d 15074806 CPX8216 0 +v 1508 HONDA CONNECTORS/MHOTRONICS Inc 0 +v 1509 FIRST INTERNATIONAL Computer Inc 0 +v 150a FORVUS RESEARCH Inc 0 +v 150b YAMASHITA Systems Corp 0 +v 150c KYOPAL CO Ltd 0 +v 150d WARPSPPED Inc 0 +v 150e C-PORT Corp 0 +v 150f INTEC GmbH 0 +v 1510 BEHAVIOR TECH Computer Corp 0 +v 1511 CENTILLIUM Technology Corp 0 +v 1512 ROSUN Technologies Inc 0 +v 1513 Raychem 0 +v 1514 TFL LAN Inc 0 +v 1515 Advent design 0 +v 1516 MYSON Technology Inc 0 +v 1517 ECHOTEK Corp 0 +v 1518 PEP MODULAR Computers GmbH 0 +v 1519 TELEFON AKTIEBOLAGET LM Ericsson 0 +v 151a Globetek 0 +d 151a1002 PCI-1002 0 +d 151a1004 PCI-1004 0 +d 151a1008 PCI-1008 0 +v 151b COMBOX Ltd 0 +v 151c DIGITAL AUDIO LABS Inc 0 +v 151d Fujitsu Computer Products Of America 0 +v 151e MATRIX Corp 0 +v 151f TOPIC SEMICONDUCTOR Corp 0 +d 151f0000 TP560 Data/Fax/Voice 56k modem 0 +v 1520 CHAPLET System Inc 0 +v 1521 BELL Corp 0 +v 1522 MainPine Ltd 0 +d 15220100 PCI <_> IOBus Bridge 1 +s 1522010015220100 RockForceDUO 2 Port V.92/V.44 Data/Fax/Voice Modem 1 +s 1522010015220100 1 +s 1522010015220200 RockForceDUO 2 Port V.92/V.44 Data/Fax/Voice Modem 1 +s 1522010015220300 RockForceQUATRO 4 Port V.92/V.44 Data/Fax/Voice Modem 1 +v 1523 MUSIC Semiconductors 0 +v 1524 ENE Technology Inc 0 +v 1525 IMPACT Technologies 0 +v 1526 ISS, Inc 0 +v 1527 SOLECTRON 0 +v 1528 ACKSYS 0 +v 1529 AMERICAN MICROSystems Inc 0 +v 152a QUICKTURN DESIGN Systems 0 +v 152b FLYTECH Technology CO Ltd 0 +v 152c MACRAIGOR Systems LLC 0 +v 152d QUANTA Computer Inc 0 +v 152e MELEC Inc 0 +v 152f PHILIPS - CRYPTO 0 +v 1530 ACQIS Technology Inc 0 +v 1531 CHRYON Corp 0 +v 1532 ECHELON Corp 0 +v 1533 BALTIMORE 0 +v 1534 ROAD Corp 0 +v 1535 EVERGREEN Technologies Inc 0 +v 1537 DATALEX COMMUNCATIONS 0 +v 1538 ARALION Inc 0 +v 1539 ATELIER INFORMATIQUES et ELECTRONIQUE ETUDES S.A. 0 +v 153a ONO SOKKI 0 +v 153b TERRATEC Electronic GmbH 0 +v 153c ANTAL Electronic 0 +v 153d FILANET Corp 0 +v 153e TECHWELL Inc 0 +v 153f MIPS DENMARK 0 +v 1540 PROVIDEO MULTIMEDIA Co Ltd 0 +v 1541 MACHONE Communications 0 +v 1542 VIVID Technology Inc 0 +v 1543 SILICON Laboratories 0 +v 1544 DCM DATA Systems 0 +v 1545 VISIONTEK 0 +v 1546 IOI Technology Corp 0 +v 1547 MITUTOYO Corp 0 +v 1548 JET PROPULSION Laboratory 0 +v 1549 INTERCONNECT Systems Solutions 0 +v 154a MAX Technologies Inc 0 +v 154b COMPUTEX Co Ltd 0 +v 154c VISUAL Technology Inc 0 +v 154d PAN INTERNATIONAL Industrial Corp 0 +v 154e SERVOTEST Ltd 0 +v 154f STRATABEAM Technology 0 +v 1550 OPEN NETWORK Co Ltd 0 +v 1551 SMART Electronic DEVELOPMENT GmBH 0 +v 1552 RACAL AIRTECH Ltd 0 +v 1553 CHICONY Electronics Co Ltd 0 +v 1554 PROLINK Microsystems Corp 0 +v 1555 GESYTEC GmBH 0 +v 1556 PLD APPLICATIONS 0 +v 1557 MEDIASTAR Co Ltd 0 +v 1558 CLEVO/KAPOK Computer 0 +v 1559 SI LOGIC Ltd 0 +v 155a INNOMEDIA Inc 0 +v 155b PROTAC INTERNATIONAL Corp 0 +v 155c Cemax-Icon Inc 0 +v 155d Mac System Co Ltd 0 +v 155e LP Elektronik GmbH 0 +v 155f Perle Systems Ltd 0 +v 1560 Terayon Communications Systems 0 +v 1561 Viewgraphics Inc 0 +v 1562 Symbol Technologies 0 +v 1563 A-Trend Technology Co Ltd 0 +v 1564 Yamakatsu Electronics Industry Co Ltd 0 +v 1565 Biostar Microtech Int'l Corp 0 +v 1566 Ardent Technologies Inc 0 +v 1567 Jungsoft 0 +v 1568 DDK Electronics Inc 0 +v 1569 Palit Microsystems Inc. 0 +v 156a Avtec Systems 0 +v 156b 2wire Inc 0 +v 156c Vidac Electronics GmbH 0 +v 156d Alpha-Top Corp 0 +v 156e Alfa Inc 0 +v 156f M-Systems Flash Disk Pioneers Ltd 0 +v 1570 Lecroy Corp 0 +v 1571 Contemporary Controls 0 +d 1571a001 CCSI PCI20-485 ARCnet 0 +d 1571a002 CCSI PCI20-485D ARCnet 0 +d 1571a003 CCSI PCI20-485X ARCnet 0 +d 1571a004 CCSI PCI20-CXB ARCnet 0 +d 1571a005 CCSI PCI20-CXS ARCnet 0 +d 1571a006 CCSI PCI20-FOG-SMA ARCnet 0 +d 1571a007 CCSI PCI20-FOG-ST ARCnet 0 +d 1571a008 CCSI PCI20-TB5 ARCnet 0 +d 1571a009 CCSI PCI20-5-485 5Mbit ARCnet 0 +d 1571a00a CCSI PCI20-5-485D 5Mbit ARCnet 0 +d 1571a00b CCSI PCI20-5-485X 5Mbit ARCnet 0 +d 1571a00c CCSI PCI20-5-FOG-ST 5Mbit ARCnet 0 +d 1571a00d CCSI PCI20-5-FOG-SMA 5Mbit ARCnet 0 +d 1571a201 CCSI PCI22-485 10Mbit ARCnet 0 +d 1571a202 CCSI PCI22-485D 10Mbit ARCnet 0 +d 1571a203 CCSI PCI22-485X 10Mbit ARCnet 0 +d 1571a204 CCSI PCI22-CHB 10Mbit ARCnet 0 +d 1571a205 CCSI PCI22-FOG_ST 10Mbit ARCnet 0 +d 1571a206 CCSI PCI22-THB 10Mbit ARCnet 0 +v 1572 Otis Elevator Company 0 +v 1573 Lattice - Vantis 0 +v 1574 Fairchild Semiconductor 0 +v 1575 Voltaire Advanced Data Security Ltd 0 +v 1576 Viewcast COM 0 +v 1578 HITT 0 +v 1579 Dual Technology Corp 0 +v 157a Japan Elecronics Ind Inc 0 +v 157b Star Multimedia Corp 0 +v 157c Eurosoft (UK) 0 +d 157c8001 Fix2000 PCI Y2K Compliance Card 0 +v 157d Gemflex Networks 0 +v 157e Transition Networks 0 +v 157f PX Instruments Technology Ltd 0 +v 1580 Primex Aerospace Co 0 +v 1581 SEH Computertechnik GmbH 0 +v 1582 Cytec Corp 0 +v 1583 Inet Technologies Inc 0 +v 1584 Uniwill Computer Corp 0 +v 1585 Logitron 0 +v 1586 Lancast Inc 0 +v 1587 Konica Corp 0 +v 1588 Solidum Systems Corp 0 +v 1589 Atlantek Microsystems Pty Ltd 0 +v 158a Digalog Systems Inc 0 +v 158b Allied Data Technologies 0 +v 158c Hitachi Semiconductor & Devices Sales Co Ltd 0 +v 158d Point Multimedia Systems 0 +v 158e Lara Technology Inc 0 +v 158f Ditect Coop 0 +v 1590 3pardata Inc 0 +v 1591 ARN 0 +v 1592 Syba Tech Ltd 0 +d 15920781 Multi-IO Card 0 +d 15920782 Parallel Port Card 2xEPP 0 +d 15920783 Multi-IO Card 0 +d 15920785 Multi-IO Card 0 +d 15920786 Multi-IO Card 0 +d 15920787 Multi-IO Card 0 +d 15920788 Multi-IO Card 0 +d 1592078a Multi-IO Card 0 +v 1593 Bops Inc 0 +v 1594 Netgame Ltd 0 +v 1595 Diva Systems Corp 0 +v 1596 Folsom Research Inc 0 +v 1597 Memec Design Services 0 +v 1598 Granite Microsystems 0 +v 1599 Delta Electronics Inc 0 +v 159a General Instrument 0 +v 159b Faraday Technology Corp 0 +v 159c Stratus Computer Systems 0 +v 159d Ningbo Harrison Electronics Co Ltd 0 +v 159e A-Max Technology Co Ltd 0 +v 159f Galea Network Security 0 +v 15a0 Compumaster SRL 0 +v 15a1 Geocast Network Systems 0 +v 15a2 Catalyst Enterprises Inc 0 +v 15a3 Italtel 0 +v 15a4 X-Net OY 0 +v 15a5 Toyota Macs Inc 0 +v 15a6 Sunlight Ultrasound Technologies Ltd 0 +v 15a7 SSE Telecom Inc 0 +v 15a8 Shanghai Communications Technologies Center 0 +v 15aa Moreton Bay 0 +v 15ab Bluesteel Networks Inc 0 +v 15ac North Atlantic Instruments 0 +v 15ad VMWare Inc 0 +d 15ad0710 Virtual SVGA 0 +v 15ae Amersham Pharmacia Biotech 0 +v 15b0 Zoltrix International Ltd 0 +v 15b1 Source Technology Inc 0 +v 15b2 Mosaid Technologies Inc 0 +v 15b3 Mellanox Technology 0 +d 15b35274 MT21108 InfiniBridge 0 +v 15b4 CCI/TRIAD 0 +v 15b5 Cimetrics Inc 0 +v 15b6 Texas Memory Systems Inc 0 +v 15b7 Sandisk Corp 0 +v 15b8 ADDI-DATA GmbH 0 +v 15b9 Maestro Digital Communications 0 +v 15ba Impacct Technology Corp 0 +v 15bb Portwell Inc 0 +v 15bc Agilent Technologies 0 +d 15bc2929 E2929A PCI/PCI-X Bus Analyzer 0 +v 15bd DFI Inc 0 +v 15be Sola Electronics 0 +v 15bf High Tech Computer Corp (HTC) 0 +v 15c0 BVM Ltd 0 +v 15c1 Quantel 0 +v 15c2 Newer Technology Inc 0 +v 15c3 Taiwan Mycomp Co Ltd 0 +v 15c4 EVSX Inc 0 +v 15c5 Procomp Informatics Ltd 0 +v 15c6 Technical University of Budapest 0 +v 15c7 Tateyama Dystem Laboratory Co Ltd 0 +v 15c8 Penta Media Co Ltd 0 +v 15c9 Serome Technology Inc 0 +v 15ca Bitboys OY 0 +v 15cb AG Electronics Ltd 0 +v 15cc Hotrail Inc 0 +v 15cd Dreamtech Co Ltd 0 +v 15ce Genrad Inc 0 +v 15cf Hilscher GmbH 0 +v 15d1 Infineon Technologies AG 0 +v 15d2 FIC (First International Computer Inc) 0 +v 15d3 NDS Technologies Israel Ltd 0 +v 15d4 Iwill Corp 0 +v 15d5 Tatung Co 0 +v 15d6 Entridia Corp 0 +v 15d7 Rockwell-Collins Inc 0 +v 15d8 Cybernetics Technology Co Ltd 0 +v 15d9 Super Micro Computer Inc 0 +v 15da Cyberfirm Inc 0 +v 15db Applied Computing Systems Inc 0 +v 15dc Litronic Inc 0 +d 15dc0001 Argus 300 PCI Cryptography Module 0 +v 15dd Sigmatel Inc 0 +v 15de Malleable Technologies Inc 0 +v 15df Infinilink Corp 0 +v 15e0 Cacheflow Inc 0 +v 15e1 Voice Technologies Group Inc 0 +v 15e2 Quicknet Technologies Inc 0 +v 15e3 Networth Technologies Inc 0 +v 15e4 VSN Systemen BV 0 +v 15e5 Valley technologies Inc 0 +v 15e6 Agere Inc 0 +v 15e7 Get Engineering Corp 0 +v 15e8 National Datacomm Corp 0 +v 15e9 Pacific Digital Corp 0 +v 15ea Tokyo Denshi Sekei K.K. 0 +v 15eb Drsearch GmbH 0 +v 15ec Beckhoff GmbH 0 +v 15ed Macrolink Inc 0 +v 15ee In Win Development Inc 0 +v 15ef Intelligent Paradigm Inc 0 +v 15f0 B-Tree Systems Inc 0 +v 15f1 Times N Systems Inc 0 +v 15f2 Diagnostic Instruments Inc 0 +v 15f3 Digitmedia Corp 0 +v 15f4 Valuesoft 0 +v 15f5 Power Micro Research 0 +v 15f6 Extreme Packet Device Inc 0 +v 15f7 Banctec 0 +v 15f8 Koga Electronics Co 0 +v 15f9 Zenith Electronics Corp 0 +v 15fa J.P. Axzam Corp 0 +v 15fb Zilog Inc 0 +v 15fc Techsan Electronics Co Ltd 0 +v 15fd N-CUBED.NET 0 +v 15fe Kinpo Electronics Inc 0 +v 15ff Fastpoint Technologies Inc 0 +v 1600 Northrop Grumman - Canada Ltd 0 +v 1601 Tenta Technology 0 +v 1602 Prosys-tec Inc 0 +v 1603 Nokia Wireless Communications 0 +v 1604 Central System Research Co Ltd 0 +v 1605 Pairgain Technologies 0 +v 1606 Europop AG 0 +v 1607 Lava Semiconductor Manufacturing Inc 0 +v 1608 Automated Wagering International 0 +v 1609 Scimetric Instruments Inc 0 +v 1619 FarSite Communications Ltd 0 +d 16190400 FarSync T2P (2 port X.21/V.35/V.24) 0 +d 16190440 FarSync T4P (4 port X.21/V.35/V.24) 0 +v 1629 Kongsberg Spacetec AS 0 +d 16291003 Format synchronizer v3.0 0 +d 16292002 Fast Universal Data Output 0 +v 1657 Brocade Communications Systems, Inc. 0 +v 1668 Action Tec Electronics Inc 0 +v 16f6 VideoTele.com, Inc. 0 +v 170c YottaYotta Inc. 0 +v 1743 Peppercon AG 1 +d 17438139 ROL/F-100 Fast Ethernet Adapter with ROL 1 +v 1813 Ambient Technologies Inc 0 +v 1a08 Sierra semiconductor 0 +d 1a080000 SC15064 0 +v 1b13 Jaton Corp 0 +v 1c1c Symphony 0 +d 1c1c0001 82C101 0 +v 1d44 DPT 0 +d 1d44a400 PM2x24/PM3224 0 +v 1de1 Tekram Technology Co.,Ltd. 0 +d 1de10391 TRM-S1040 0 +d 1de12020 DC-390 0 +d 1de1690c 690c 0 +d 1de1dc29 DC290 0 +v 2001 Temporal Research Ltd 0 +v 21c3 21st Century Computer Corp. 0 +v 2348 Racore 0 +d 23482010 8142 100VG/AnyLAN 0 +v 2646 Kingston Technologies 0 +v 270b Xantel Corporation 0 +v 270f Chaintech Computer Co. Ltd 0 +v 2711 AVID Technology Inc. 0 +v 2a15 3D Vision(???) 0 +v 3000 Hansol Electronics Inc. 0 +v 3142 Post Impression Systems. 0 +v 3388 Hint Corp 0 +d 33888011 VXPro II Chipset 0 +s 3388801133888011 VXPro II Chipset CPU to PCI Bridge 0 +d 33888012 VXPro II Chipset 0 +s 3388801233888012 VXPro II Chipset PCI to ISA Bridge 0 +d 33888013 VXPro II Chipset 0 +s 3388801333888013 VXPro II Chipset EIDE Controller 0 +v 3411 Quantum Designs (H.K.) Inc 0 +v 3513 ARCOM Control Systems Ltd 0 +v 38ef 4Links 0 +v 3d3d 3DLabs 0 +d 3d3d0001 GLINT 300SX 0 +d 3d3d0002 GLINT 500TX 0 +d 3d3d0003 GLINT Delta 0 +d 3d3d0004 Permedia 0 +d 3d3d0005 Permedia 0 +d 3d3d0006 GLINT MX 0 +d 3d3d0007 3D Extreme 0 +d 3d3d0008 GLINT Gamma G1 0 +d 3d3d0009 Permedia II 2D+3D 0 +s 3d3d000910400011 AccelStar II 1 +s 3d3d00093d3d0100 AccelStar II 3D Accelerator 0 +s 3d3d00093d3d0111 Permedia 3:16 0 +s 3d3d00093d3d0114 Santa Ana 0 +s 3d3d00093d3d0116 Oxygen GVX1 0 +s 3d3d00093d3d0119 Scirocco 0 +s 3d3d00093d3d0120 Santa Ana PCL 0 +s 3d3d00093d3d0125 Oxygen VX1 0 +s 3d3d00093d3d0127 Permedia3 Create! 0 +d 3d3d000a GLINT R3 0 +s 3d3d000a3d3d0121 Oxygen VX1 0 +d 3d3d0100 Permedia II 2D+3D 0 +d 3d3d1004 Permedia 0 +d 3d3d3d04 Permedia 0 +d 3d3dffff Glint VGA 0 +v 4005 Avance Logic Inc. 0 +d 40050300 ALS300 PCI Audio Device 0 +d 40050308 ALS300+ PCI Audio Device 0 +d 40050309 PCI Input Controller 0 +d 40051064 ALG-2064 0 +d 40052064 ALG-2064i 0 +d 40052128 ALG-2364A GUI Accelerator 0 +d 40052301 ALG-2301 0 +d 40052302 ALG-2302 0 +d 40052303 AVG-2302 GUI Accelerator 0 +d 40052364 ALG-2364A 0 +d 40052464 ALG-2464 0 +d 40052501 ALG-2564A/25128A 0 +d 40054000 ALS4000 Audio Chipset 0 +s 4005400040054000 ALS4000 Audio Chipset 0 +d 40054710 ALC200/200P 1 as reported by alsa for the builtin audio of the VIA KT266A +v 4033 Addtron Technology Co, Inc. 0 +d 40331360 RTL8139 Ethernet 0 +v 4143 Digital Equipment Corp 0 +v 416c Aladdin Knowledge Systems 0 +d 416c0100 AladdinCARD 0 +d 416c0200 CPC 0 +v 4444 Internext Compression Inc 0 +v 4468 Bridgeport machines 0 +v 4594 Cogetec Informatique Inc 0 +v 45fb Baldor Electric Company 0 +v 4680 Umax Computer Corp 0 +v 4843 Hercules Computer Technology Inc 0 +v 4916 RedCreek Communications Inc 0 +d 49161960 RedCreek PCI adapter 0 +v 4943 Growth Networks 0 +v 4978 Axil Computer Inc 0 +v 4a14 NetVin 0 +d 4a145000 NV5000SC 0 +s 4a1450004a145000 RT8029-Based Ethernet Adapter 0 +v 4b10 Buslogic Inc. 0 +v 4c48 LUNG HWA Electronics 0 +v 4ca1 Seanix Technology Inc 0 +v 4d51 MediaQ Inc. 0 +d 4d510200 MQ-200 0 +v 4d54 Microtechnica Co Ltd 0 +v 4ddc ILC Data Device Corp 0 +v 5046 GemTek Technology Corporation 1 +d 50461001 Gemtek PCI Radio 1 +v 5053 Voyetra Technologies 0 +d 50532010 Daytona Audio Adapter 0 +v 5136 S S Technologies 0 +v 5143 Qualcomm Inc 0 +v 5145 Ensoniq (Old) 0 +d 51453031 Concert AudioPCI 0 +v 5301 Alliance Semiconductor Corp. 0 +d 53010001 ProMotion aT3D 0 +v 5333 S3 Inc. 0 +d 53330551 Plato/PX (system) 0 +d 53335631 86c325 [ViRGE] 0 +d 53338800 86c866 [Vision 866] 0 +d 53338801 86c964 [Vision 964] 0 +d 53338810 86c764_0 [Trio 32 vers 0] 0 +d 53338811 86c764/765 [Trio32/64/64V+] 0 +d 53338812 86cM65 [Aurora64V+] 0 +d 53338813 86c764_3 [Trio 32/64 vers 3] 0 +d 53338814 86c767 [Trio 64UV+] 0 +d 53338815 86cM65 [Aurora 128] 0 +d 5333883d 86c988 [ViRGE/VX] 0 +d 53338870 FireGL 0 +d 53338880 86c868 [Vision 868 VRAM] vers 0 0 +d 53338881 86c868 [Vision 868 VRAM] vers 1 0 +d 53338882 86c868 [Vision 868 VRAM] vers 2 0 +d 53338883 86c868 [Vision 868 VRAM] vers 3 0 +d 533388b0 86c928 [Vision 928 VRAM] vers 0 0 +d 533388b1 86c928 [Vision 928 VRAM] vers 1 0 +d 533388b2 86c928 [Vision 928 VRAM] vers 2 0 +d 533388b3 86c928 [Vision 928 VRAM] vers 3 0 +d 533388c0 86c864 [Vision 864 DRAM] vers 0 0 +d 533388c1 86c864 [Vision 864 DRAM] vers 1 0 +d 533388c2 86c864 [Vision 864-P DRAM] vers 2 0 +d 533388c3 86c864 [Vision 864-P DRAM] vers 3 0 +d 533388d0 86c964 [Vision 964 VRAM] vers 0 0 +d 533388d1 86c964 [Vision 964 VRAM] vers 1 0 +d 533388d2 86c964 [Vision 964-P VRAM] vers 2 0 +d 533388d3 86c964 [Vision 964-P VRAM] vers 3 0 +d 533388f0 86c968 [Vision 968 VRAM] rev 0 0 +d 533388f1 86c968 [Vision 968 VRAM] rev 1 0 +d 533388f2 86c968 [Vision 968 VRAM] rev 2 0 +d 533388f3 86c968 [Vision 968 VRAM] rev 3 0 +d 53338900 86c755 [Trio 64V2/DX] 0 +s 5333890053338900 86C775 Trio64V2/DX 0 +d 53338901 86c775/86c785 Trio 64V2/DX or /GX 0 +s 5333890153338901 86C775 Trio64V2/DX, 86C785 Trio64V2/GX 0 +d 53338902 Plato/PX 0 +d 53338903 Trio 3D business multimedia 0 +d 53338904 Trio 64 3D 0 +s 53338904101400db Integrated Trio3D 0 +s 5333890453338904 86C365 Trio3D AGP 0 +d 53338905 Trio 64V+ family 0 +d 53338906 Trio 64V+ family 0 +d 53338907 Trio 64V+ family 0 +d 53338908 Trio 64V+ family 0 +d 53338909 Trio 64V+ family 0 +d 5333890a Trio 64V+ family 0 +d 5333890b Trio 64V+ family 0 +d 5333890c Trio 64V+ family 0 +d 5333890d Trio 64V+ family 0 +d 5333890e Trio 64V+ family 0 +d 5333890f Trio 64V+ family 0 +d 53338a01 ViRGE/DX or /GX 0 +s 53338a010e11b032 ViRGE/GX 0 +s 53338a0110b41617 Nitro 3D 0 +s 53338a0110b41717 Nitro 3D 0 +s 53338a0153338a01 ViRGE/DX 0 +d 53338a10 ViRGE/GX2 0 +s 53338a1010928a10 Stealth 3D 4000 0 +d 53338a13 86c368 [Trio 3D/2X] 0 +s 53338a1353338a13 Trio3D/2X 0 +d 53338a20 86c794 [Savage 3D] 0 +s 53338a2053338a20 86C391 Savage3D 0 +d 53338a21 86c795 [Savage 3D/MV] 0 +s 53338a2153338a21 86C390 Savage3D/MV 0 +d 53338a22 Savage 4 0 +s 53338a2210338068 Savage 4 1 +s 53338a2210338069 Savage 4 1 +s 53338a22105d0018 SR9 8Mb SDRAM 0 +s 53338a22105d002a SR9 Pro 16Mb SDRAM 0 +s 53338a22105d003a SR9 Pro 32Mb SDRAM 0 +s 53338a22105d092f SR9 Pro+ 16Mb SGRAM 0 +s 53338a2210924207 Stealth III S540 0 +s 53338a2210924800 Stealth III S540 0 +s 53338a2210924807 SpeedStar A90 0 +s 53338a2210924808 Stealth III S540 0 +s 53338a2210924809 Stealth III S540 0 +s 53338a221092480e Stealth III S540 0 +s 53338a2210924904 Stealth III S520 0 +s 53338a2210924905 SpeedStar A200 0 +s 53338a2210924a09 Stealth III S540 0 +s 53338a2210924a0b Stealth III S540 Xtreme 0 +s 53338a2210924a0f Stealth III S540 0 +s 53338a2210924e01 Stealth III S540 0 +s 53338a221102101d 3d Blaster Savage 4 0 +s 53338a221102101e 3d Blaster Savage 4 0 +s 53338a2253338100 86C394-397 Savage4 SDRAM 100 0 +s 53338a2253338110 86C394-397 Savage4 SDRAM 110 0 +s 53338a2253338125 86C394-397 Savage4 SDRAM 125 0 +s 53338a2253338143 86C394-397 Savage4 SDRAM 143 0 +s 53338a2253338a22 86C394-397 Savage4 0 +s 53338a2253338a2e 86C394-397 Savage4 32bit 0 +s 53338a2253339125 86C394-397 Savage4 SGRAM 125 0 +s 53338a2253339143 86C394-397 Savage4 SGRAM 143 0 +d 53338a23 Savage 4 0 +d 53338a25 ProSavage PM133 0 +d 53338a26 ProSavage KM133 0 +d 53338c00 ViRGE/M3 0 +d 53338c01 ViRGE/MX 0 +s 53338c0111790001 ViRGE MX 1 +d 53338c02 ViRGE/MX+ 0 +d 53338c03 ViRGE/MX+MV 0 +d 53338c10 86C270-294 Savage/MX-MV 0 +d 53338c11 82C270-294 Savage/MX 0 +d 53338c12 86C270-294 Savage/IX-MV 0 +d 53338c13 86C270-294 Savage/IX 0 +d 53339102 86C410 Savage 2000 0 +s 5333910210925932 Viper II Z200 0 +s 5333910210925934 Viper II Z200 0 +s 5333910210925952 Viper II Z200 0 +s 5333910210925954 Viper II Z200 0 +s 5333910210925a35 Viper II Z200 0 +s 5333910210925a37 Viper II Z200 0 +s 5333910210925a55 Viper II Z200 0 +s 5333910210925a57 Viper II Z200 0 +d 5333ca00 SonicVibes 0 +v 544c Teralogic Inc 0 +v 5455 Technische University Berlin 0 +d 54554458 S5933 0 +v 5519 Cnet Technologies, Inc. 0 +v 5544 Dunord Technologies 0 +d 55440001 I-30xx Scanner Interface 0 +v 5555 Genroco, Inc 0 +d 55550003 TURBOstor HFP-832 [HiPPI NIC] 0 +v 5700 Netpower 0 +v 6356 UltraStor 0 +v 6374 c't Magazin für Computertechnik 0 +d 63746773 GPPCI 0 +v 6409 Logitec Corp. 0 +v 6666 Decision Computer International Co. 0 +d 66660001 PCCOM4 0 +d 66660002 PCCOM8 0 +v 7604 O.N. Electronic Co Ltd. 0 +v 7bde MIDAC Corporation 0 +v 7fed PowerTV 0 +v 8008 Quancom Electronic GmbH 0 +d 80080010 WDOG1 [PCI-Watchdog 1] 0 +d 80080011 PWDOG2 [PCI-Watchdog 2] 0 +v 8086 Intel Corp. 0 +d 80860007 82379AB 0 +d 80860039 21145 0 +d 80860122 82437FX 0 +d 80860482 82375EB 0 +d 80860483 82424ZX [Saturn] 0 +d 80860484 82378IB [SIO ISA Bridge] 0 +d 80860486 82430ZX [Aries] 0 +d 808604a3 82434LX [Mercury/Neptune] 0 +d 808604d0 82437FX [Triton FX] 0 +d 80860600 RAID Controller 0 +d 80860960 80960RP [i960 RP Microprocessor/Bridge] 0 +d 80860962 80960RM [i960RM Bridge] 1 From SuperTrak SX6000 +d 80860964 80960RP [i960 RP Microprocessor/Bridge] 0 +d 80861000 82542 Gigabit Ethernet Controller 0 +s 808610000e11b0df NC6132 Gigabit Module (1000-SX) 0 +s 808610000e11b0e0 NC6133 Gigabit Module (1000-LX) 0 +s 808610000e11b123 NC6134 Gigabit NIC (1000-SX) 0 +s 8086100010140119 Netfinity Gigabit Ethernet SX Adapter 0 +s 8086100080861000 EtherExpress PRO/1000 Gigabit Server Adapter 0 +s 8086100080861000 PRO/1000 Gigabit Server Adapter 1 Intel never used the EtherExpress name on the PRO/1000 product line +d 80861001 82543GC Gigabit Ethernet Controller (fiber) 0 +s 808610010e11004a NC6136 Gigabit Server Adapter 0 +s 80861001101401ea Netfinity Gigabit Ethernet SX Adapter 0 +s 8086100180861003 PRO/1000 Gigabit Server Adapter 0 +s 8086100180861003 PRO/1000 F Server Adapter 1 +d 80861002 Pro 100 LAN Modem 56 Cardbus II 0 +d 80861002 1 +s 808610028086200e Pro 100 LAN Modem 56 Cardbus II 0 +s 8086100280862013 Pro 100 SR Mobile Combo Adapter 1 +s 8086100280862017 Pro 100 S Combo Mobile Adapter 1 +d 80861004 82543GC Gigabit Ethernet Controller (copper) 0 +s 808610040e110049 NC7132 Gigabit Upgrade Module 0 +s 808610040e11b1a4 NC7131 Gigabit Server Adapter 0 +s 80861004101410f2 Gigabit Ethernet Server Adapter 1 +s 8086100480861004 PRO/1000 Gigabit Server Adapter 0 +s 8086100480861004 PRO/1000 T Server Adapter 1 +s 8086100480862004 PRO/1000 T Server Adapter 1 +s 8086100480862004 PRO/1000 Gigabit Server Adapter 1 +d 80861008 82544EI Gigabit Ethernet Controller (copper) 0 +s 8086100880861107 PRO/1000 XT Server Adapter 1 +s 8086100880861107 PRO/1000 Gigabit Server Adapter 1 +s 8086100880862107 PRO/1000 XT Server Adapter 1 +s 8086100880862107 PRO/1000 Gigabit Server Adapter 1 +s 8086100880862110 PRO/1000 XT Server Adapter 1 +s 8086100880862110 PRO/1000 XT Desktop Adapter 1 +d 80861009 82544EI Gigabit Ethernet Controller (fiber) 0 +s 8086100980861109 PRO/1000 Gigabit Server Adapter 0 +s 8086100980861109 PRO/1000 XF Server Adapter 1 +s 8086100980862109 PRO/1000 XF Server Adapter 1 +d 8086100c 82544GC Gigabit Ethernet Controller 0 +s 8086100c80861109 PRO/1000 T Desktop Adapter 1 +s 8086100c80861109 1 +s 8086100c80861112 PRO/1000 Gigabit Desktop Adapter 1 +s 8086100c80861112 PRO/1000 T Desktop Adapter 1 +s 8086100c80862109 PRO/1000 T Desktop Adapter 1 +s 8086100c80862109 1 +s 8086100c80862112 PRO/1000 Gigabit Desktop Adapter 1 +s 8086100c80862112 PRO/1000 T Desktop Adapter 1 +d 8086100d 82544GC Gigabit Ethernet Controller 0 +s 8086100d8086110d 82544GC Gigabit Ethernet Controller 1 +d 80861029 82559 Ethernet Controller 0 +d 80861030 82559 InBusiness 10/100 0 +d 80861031 82801CAM (ICH3) Chipset Ethernet Controller 0 +d 80861031 EtherExpress PRO/100 VE Network Connection 1 +s 8086103110140209 EtherExpress PRO/100 VE Network Connection 1 +s 80861031107b5350 EtherExpress PRO/100 VE Network Connection 1 +s 8086103111790001 EtherExpress PRO/100 VE Network Connection 1 +s 80861031144dc000 EtherExpress PRO/100 VE Network Connection 1 +s 80861031144dc001 EtherExpress PRO/100 VE Network Connection 1 +s 80861031144dc003 EtherExpress PRO/100 VE Network Connection 1 +d 80861032 82801CAM (ICH3) Chipset Ethernet Controller 0 +d 80861032 EtherExpress PRO/100 VE Network Connection 1 +d 80861033 82801CAM (ICH3) Chipset Ethernet Controller 0 +d 80861033 EtherExpress PRO/100 VM Network Connection 1 +d 80861034 82801CAM (ICH3) Chipset Ethernet Controller 0 +d 80861034 EtherExpress PRO/100 VM Network Connection 1 +d 80861035 82801CAM (ICH3) Chipset Ethernet Controller 0 +d 80861035 82562EH based Phoneline Network Connection 1 +d 80861036 82801CAM (ICH3) Chipset Ethernet Controller 0 +d 80861036 82562EH based Phoneline Network Connection 1 +d 80861037 82801CAM (ICH3) Chipset Ethernet Controller 0 +d 80861038 82801CAM (ICH3) Chipset Ethernet Controller 0 +d 80861038 EtherExpress PRO/100 VM Network Connection 1 +d 80861130 82815 815 Chipset Host Bridge and Memory Controller Hub 0 +d 80861131 82815 815 Chipset AGP Bridge 0 +d 80861132 82815 CGC [Chipset Graphics Controller] 0 +d 80861161 82806AA PCI64 Hub Advanced Programmable Interrupt Controller 0 +s 8086116180861161 82806AA PCI64 Hub - APIC 1 +d 80861209 82559ER 0 +d 80861221 82092AA_0 0 +d 80861222 82092AA_1 0 +d 80861223 SAA7116 0 +d 80861225 82452KX/GX [Orion] 0 +d 80861226 82596 PRO/10 PCI 0 +d 80861227 82865 EtherExpress PRO/100A 0 +d 80861228 82556 EtherExpress PRO/100 Smart 0 +d 80861229 82557/8/9 [Ethernet Pro 100] 0 the revision field differentiates between them (1-3 is 82557, 4-5 is 82558, 6-8 is 82559, 9 is 82559ER) +s 808612290e113001 82559 Fast Ethernet LOM with Alert on LAN* 1 +s 808612290e113002 82559 Fast Ethernet LOM with Alert on LAN* 1 +s 808612290e113003 82559 Fast Ethernet LOM with Alert on LAN* 1 +s 808612290e113004 82559 Fast Ethernet LOM with Alert on LAN* 1 +s 808612290e113005 82559 Fast Ethernet LOM with Alert on LAN* 1 +s 808612290e113006 82559 Fast Ethernet LOM with Alert on LAN* 1 +s 808612290e113007 82559 Fast Ethernet LOM with Alert on LAN* 1 +s 808612290e11b01e NC3120 Fast Ethernet NIC 0 +s 808612290e11b01f NC3122 Fast Ethernet NIC (dual port) 0 +s 808612290e11b02f NC1120 Ethernet NIC 0 +s 808612290e11b04a Netelligent 10/100TX NIC with Wake on LAN 0 +s 808612290e11b0c6 NC3161 Fast Ethernet NIC (embedded, WOL) 0 +s 808612290e11b0c7 NC3160 Fast Ethernet NIC (embedded) 0 +s 808612290e11b0d7 NC3121 Fast Ethernet NIC (WOL) 0 +s 808612290e11b0dd NC3131 Fast Ethernet NIC (dual port) 0 +s 808612290e11b0de NC3132 Fast Ethernet Module (dual port) 0 +s 808612290e11b0e1 NC3133 Fast Ethernet Module (100-FX) 0 +s 808612290e11b134 NC3163 Fast Ethernet NIC (embedded, WOL) 0 +s 808612290e11b13c NC3162 Fast Ethernet NIC (embedded) 0 +s 808612290e11b144 NC3123 Fast Ethernet NIC (WOL) 0 +s 808612290e11b163 NC3134 Fast Ethernet NIC (dual port) 0 +s 808612290e11b164 NC3135 Fast Ethernet Upgrade Module (dual port) 0 +s 808612291014005c 82558B Ethernet Pro 10/100 0 +s 80861229101401bc 82559 Fast Ethernet LAN On Motherboard 1 +s 80861229101401f1 10/100 Ethernet Server Adapter 1 +s 80861229101401f2 10/100 Ethernet Server Adapter 1 +s 8086122910140207 Ethernet Pro/100 S Network Connection 1 +s 8086122910140232 10/100 Dual Port Server Adapter 1 +s 808612291014105c Netfinity 10/100 0 +s 808612291014305c 10/100 EtherJet Management Adapter 1 +s 808612291014405c 10/100 EtherJet Adapter with Alert on LAN 1 +s 808612291014505c 10/100 10/100 EtherJet Secure Management Adapter 1 +s 808612291014605c 10/100 10/100 EtherJet Secure Management Adapter 1 +s 808612291014705c 10/100 Netfinity 10/100 Ethernet Security Adapter 1 +s 808612291014805c 10/100 Netfinity 10/100 Ethernet Security Adapter 1 +s 8086122910338000 PC-9821X-B06 0 +s 8086122910338000 PC-9821X-B06 (82557C) 1 +s 8086122910338016 PK-UG-X006 0 +s 8086122910338016 PK-UG-X006 (82558A) 1 +s 808612291033801f PK-UG-X006 0 +s 808612291033801f PK-UG-X006 (82558B) 1 +s 8086122910338026 PK-UG-X006 (82558B) 1 +s 8086122910338063 82559-based Fast Ethernet Adapter 1 +s 8086122910338064 82559-based Fast Ethernet Adapter 1 +s 80861229103c10c0 Ethernet Pro 10/100TX 0 +s 80861229103c10c0 NetServer 10/100TX 1 +s 80861229103c10c3 Ethernet Pro 10/100TX 0 +s 80861229103c10c3 NetServer 10/100TX 1 +s 80861229103c10ca NetServer 10/100TX 1 +s 80861229103c10cb NetServer 10/100TX 1 +s 80861229103c10e3 NetServer 10/100TX 1 +s 80861229103c10e4 NetServer 10/100TX 1 +s 80861229103c1200 Ethernet Pro 10/100TX 0 +s 80861229103c1200 NetServer 10/100TX 1 +s 8086122910c31100 SmartEther100 SC1100 0 +s 8086122910c31100 SmartEther100 SC1100 (82557C) 1 +s 8086122910cf1115 8255x-based Ethernet Adapter (10/100) 1 +s 8086122910cf1143 8255x-based Ethernet Adapter (10/100) 1 +s 8086122911790001 8255x-based Ethernet Adapter (10/100) 1 +s 8086122911790002 PCI FastEther LAN on Docker 0 +s 8086122911790003 8255x-based Fast Ethernet 1 +s 8086122912592560 AT-2560 100 0 +s 8086122912592560 AT-2560 100 (82557C) 1 +s 8086122912592561 AT-2560 100 FX Ethernet Adapter 0 +s 8086122912592561 AT-2560 100 FX Ethernet Adapter (82557C) 1 +s 8086122912660001 NE10/100 Adapter 0 +s 8086122912660001 NE10/100 Adapter (82557C) 1 +s 80861229144d2501 SEM-2000 MiniPCI LAN Adapter 1 +s 80861229144d2502 SEM-2100IL MiniPCI LAN Adapter 1 +s 8086122980860001 EtherExpress PRO/100B (TX) 0 +s 8086122980860002 EtherExpress PRO/100B (T4) 0 +s 8086122980860003 EtherExpress PRO/10+ 0 +s 8086122980860004 EtherExpress PRO/100 WfM 0 +s 8086122980860005 82557 10/100 0 +s 8086122980860006 82557 10/100 with Wake on LAN 0 +s 8086122980860007 82558 10/100 Adapter 0 +s 8086122980860008 82558 10/100 with Wake on LAN 0 +s 8086122980860009 EtherExpress PRO/100+ 0 +s 808612298086000a EtherExpress PRO/100+ Management Adapter 0 +s 808612298086000b EtherExpress PRO/100+ 0 +s 808612298086000c EtherExpress PRO/100+ Management Adapter 0 +s 808612298086000d EtherExpress PRO/100+ Alert On LAN II* Adapter 0 +s 808612298086000d EtherExpress PRO/100 Alert On LAN* 2 Management Adapter 1 +s 808612298086000e EtherExpress PRO/100+ Management Adapter with Alert On LAN* 0 +s 808612298086000e EtherExpress PRO/100 Alert on LAN* Management Adapter 1 +s 808612298086000f EtherExpress PRO/100 Desktop Adapter 1 +s 8086122980860010 EtherExpress PRO/100 S Management Adapter 1 +s 8086122980860011 EtherExpress PRO/100 S Management Adapter 1 +s 8086122980860012 EtherExpress PRO/100 S Advanced Management Adapter (D) 1 +s 8086122980860013 EtherExpress PRO/100 S Advanced Management Adapter (E) 1 +s 8086122980860030 EtherExpress PRO/100 Management Adapter with Alert On LAN* GC 1 +s 8086122980860031 EtherExpress PRO/100 Desktop Adapter 1 +s 8086122980860040 EtherExpress PRO/100 S Desktop Adapter 1 +s 8086122980860041 EtherExpress PRO/100 S Desktop Adapter 1 +s 8086122980860042 EtherExpress PRO/100 Desktop Adapter 1 +s 8086122980860050 EtherExpress PRO/100 S Desktop Adapter 1 +s 8086122980861009 EtherExpress PRO/100+ Server Adapter 0 +s 808612298086100c EtherExpress PRO/100+ Server Adapter (PILA8470B) 0 +s 8086122980861012 EtherExpress PRO/100 S Server Adapter (D) 1 +s 8086122980861013 EtherExpress PRO/100 S Server Adapter (E) 1 +s 8086122980861015 EtherExpress PRO/100 S Dual Port Server Adapter 1 +s 8086122980861017 EtherExpress PRO/100 Dual Port Server Adapter 1 +s 8086122980861030 EtherExpress PRO/100 Management Adapter with Alert On LAN* G Server 1 +s 8086122980861040 EtherExpress PRO/100 S Server Adapter 1 +s 8086122980861041 EtherExpress PRO/100 S Server Adapter 1 +s 8086122980861042 EtherExpress PRO/100 Server Adapter 1 +s 8086122980861050 EtherExpress PRO/100 S Server Adapter 1 +s 8086122980861051 EtherExpress PRO/100 Server Adapter 1 +s 8086122980861052 EtherExpress PRO/100 Server Adapter 1 +s 80861229808610f0 EtherExpress PRO/100+ Dual Port Adapter 0 +s 80861229808610f0 EtherExpress PRO/100 Dual Port Server Adapter 1 +s 8086122980862009 EtherExpress PRO/100 S Mobile Adapter 1 +s 808612298086200d EtherExpress PRO/100 Cardbus 0 +s 808612298086200d EtherExpress PRO/100 Cardbus II 1 +s 808612298086200e EtherExpress PRO/100 LAN+V90 Cardbus Modem 0 +s 808612298086200e EtherExpress PRO/100 LAN Modem56 Cardbus II 1 +s 808612298086200f EtherExpress PRO/100 SR Mobile Adapter 1 +s 8086122980862010 EtherExpress PRO/100 S Mobile Combo Adapter 1 +s 8086122980862013 EtherExpress PRO/100 SR Mobile Combo Adapter 1 +s 8086122980862016 EtherExpress PRO/100 S Mobile Adapter 1 +s 8086122980862017 EtherExpress PRO/100 S Combo Mobile Adapter 1 +s 8086122980862018 EtherExpress PRO/100 SR Mobile Adapter 1 +s 8086122980862019 EtherExpress PRO/100 SR Combo Mobile Adapter 1 +s 8086122980862101 EtherExpress PRO/100 P Mobile Adapter 1 +s 8086122980862102 EtherExpress PRO/100 SP Mobile Adapter 1 +s 8086122980862103 EtherExpress PRO/100 SP Mobile Adapter 1 +s 8086122980862104 EtherExpress PRO/100 SP Mobile Adapter 1 +s 8086122980862105 EtherExpress PRO/100 SP Mobile Adapter 1 +s 8086122980862106 EtherExpress PRO/100 P Mobile Adapter 1 +s 8086122980862107 EtherExpress PRO/100 Network Connection 1 +s 8086122980862108 EtherExpress PRO/100 Network Connection 1 +s 8086122980862200 EtherExpress PRO/100 P Mobile Combo Adapter 1 +s 8086122980862201 EtherExpress PRO/100 P Mobile Combo Adapter 1 +s 8086122980862202 EtherExpress PRO/100 SP Mobile Combo Adapter 1 +s 8086122980862203 EtherExpress PRO/100 MiniPCI 1 +s 8086122980862204 EtherExpress PRO/100 MiniPCI 1 +s 8086122980862205 EtherExpress PRO/100 SP Mobile Combo Adapter 1 +s 8086122980862206 EtherExpress PRO/100 SP Mobile Combo Adapter 1 +s 8086122980862207 EtherExpress PRO/100 SP Mobile Combo Adapter 1 +s 8086122980862208 EtherExpress PRO/100 P Mobile Combo Adapter 1 +s 8086122980862402 EtherExpress PRO/100 MiniPCI 1 +s 8086122980862407 EtherExpress PRO/100 MiniPCI 1 +s 8086122980862408 EtherExpress PRO/100 MiniPCI 1 +s 8086122980862409 EtherExpress PRO/100 MiniPCI 1 +s 808612298086240f EtherExpress PRO/100 MiniPCI 1 +s 8086122980862410 EtherExpress PRO/100 MiniPCI 1 +s 8086122980862411 EtherExpress PRO/100 MiniPCI 1 +s 8086122980862412 EtherExpress PRO/100 MiniPCI 1 +s 8086122980862413 EtherExpress PRO/100 MiniPCI 1 +s 8086122980863000 82559 Fast Ethernet LAN on Motherboard 0 +s 8086122980863001 82559 Fast Ethernet LOM with Basic Alert on LAN* 0 +s 8086122980863001 82559 Fast Ethernet LOM with Alert on LAN* 1 +s 8086122980863002 82559 Fast Ethernet LOM with Alert on LAN II* 0 +s 8086122980863002 82559 Fast Ethernet LOM with Alert on LAN* 2 1 +s 8086122980863006 EtherExpress PRO/100 S Network Connection 1 +s 8086122980863007 EtherExpress PRO/100 S Network Connection 1 +s 8086122980863008 EtherExpress PRO/100 Network Connection 1 +s 8086122980863010 EtherExpress PRO/100 S Network Connection 1 +s 8086122980863011 EtherExpress PRO/100 S Network Connection 1 +s 8086122980863012 EtherExpress PRO/100 Network Connection 1 +d 8086122d 430FX - 82437FX TSC [Triton I] 0 +d 8086122e 82371FB PIIX ISA [Triton I] 0 +d 80861230 82371FB PIIX IDE [Triton I] 0 +d 80861231 DSVD Modem 0 +d 80861234 430MX - 82371MX Mobile PCI I/O IDE Xcelerator (MPIIX) 0 +d 80861235 430MX - 82437MX Mob. System Ctrlr (MTSC) & 82438MX Data Path (MTDP) 0 +d 80861237 440FX - 82441FX PMC [Natoma] 0 +d 80861239 82371FB 0 +d 8086123b 82380PB 0 +d 8086123c 82380AB 0 +d 8086123d 683053 Programmable Interrupt Device 0 +d 8086123f 82466GX Integrated Hot-Plug Controller (IHPC) 0 +d 80861240 752 AGP 0 +d 8086124b 82380FB 0 +d 80861250 430HX - 82439HX TXC [Triton II] 0 +d 80861360 82806AA PCI64 Hub PCI Bridge 0 +d 80861361 82806AA PCI64 Hub Controller (HRes) 0 +d 80861960 80960RP [i960RP Microprocessor] 0 +s 80861960101e0431 MegaRAID 431 RAID Controller 0 +s 80861960101e0438 MegaRAID 438 Ultra2 LVD RAID Controller 0 +s 80861960101e0466 MegaRAID 466 Express Plus RAID Controller 0 +s 80861960101e0467 MegaRAID 467 Enterprise 1500 RAID Controller 0 +s 80861960101e0490 MegaRAID 490 Express 300 RAID Controller 0 +s 80861960101e0762 MegaRAID 762 Express RAID Controller 0 +s 80861960101e09a0 PowerEdge Expandable RAID Controller 2/SC 0 +s 8086196010280467 PowerEdge Expandable RAID Controller 2/DC 0 +s 8086196010281111 PowerEdge Expandable RAID Controller 2/SC 0 +s 80861960103c03a2 MegaRAID 0 +s 80861960103c10c6 MegaRAID 438, HP NetRAID-3Si 0 +s 80861960103c10c7 MegaRAID T5, Integrated HP NetRAID 0 +s 80861960103c10cc MegaRAID, Integrated HP NetRAID 0 +s 80861960103c10cd HP NetRAID-1Si 0 +s 80861960105a0000 SuperTrak 0 +s 80861960105a2168 SuperTrak Pro 0 +s 80861960105a5168 SuperTrak66/100 0 +s 8086196011111111 MegaRAID 466, PowerEdge Expandable RAID Controller 2/SC 0 +s 8086196011111112 PowerEdge Expandable RAID Controller 2/SC 0 +s 80861960113c03a2 MegaRAID 0 +d 80861962 80960RM [i960RM Microprocessor] 1 On SuperTrak SX6000 +s 80861962105a0000 SuperTrak I2O CPU 1 From SuperTrak SX6000 +d 80861a21 82840 840 (Carmel) Chipset Host Bridge (Hub A) 0 +d 80861a23 82840 840 (Carmel) Chipset AGP Bridge 0 +d 80861a24 82840 840 (Carmel) Chipset PCI Bridge (Hub B) 0 +d 80861a30 82845 845 (Brookdale) Chipset Host Bridge 0 +d 80861a31 82845 845 (Brookdale) Chipset AGP Bridge 0 +d 80862410 82801AA ISA Bridge (LPC) 0 +d 80862411 82801AA IDE 0 +d 80862412 82801AA USB 0 +d 80862413 82801AA SMBus 0 +d 80862415 82801AA AC'97 Audio 0 +s 8086241511d40040 SoundMAX Integrated Digital Audio 0 +s 8086241511d40048 SoundMAX Integrated Digital Audio 0 +s 8086241511d45340 SoundMAX Integrated Digital Audio 0 +d 80862416 82801AA AC'97 Modem 0 +d 80862418 82801AA PCI Bridge 0 +d 80862420 82801AB ISA Bridge (LPC) 0 +d 80862421 82801AB IDE 0 +d 80862422 82801AB USB 0 +d 80862423 82801AB SMBus 0 +d 80862425 82801AB AC'97 Audio 0 +s 8086242511d40040 SoundMAX Integrated Digital Audio 0 +s 8086242511d40048 SoundMAX Integrated Digital Audio 0 +d 80862426 82801AB AC'97 Modem 0 +d 80862428 82801AB PCI Bridge 0 +d 80862440 82801BA ISA Bridge (LPC) 0 +d 80862442 82801BA/BAM USB (Hub #1) 0 +d 80862443 82801BA/BAM SMBus 0 +d 80862444 82801BA/BAM USB (Hub #2) 0 +d 80862445 82801BA/BAM AC'97 Audio 0 +d 80862446 82801BA/BAM AC'97 Modem 0 +d 80862448 82801BAM/CAM PCI Bridge 0 +d 80862449 82801BA/BAM/CA/CAM Ethernet Controller 0 +s 808624490e110012 EtherExpress PRO/100 VM Network Connection 1 +s 808624490e110091 EtherExpress PRO/100 VE Network Connection 1 +s 80862449101401ce EtherExpress PRO/100 VE Desktop Connection 1 +s 80862449101401dc EtherExpress PRO/100 VE Desktop Connection 1 +s 80862449101401eb EtherExpress PRO/100 VE Desktop Connection 1 +s 80862449101401ec EtherExpress PRO/100 VE Desktop Connection 1 +s 8086244910140202 EtherExpress PRO/100 VE Desktop Connection 1 +s 8086244910140205 EtherExpress PRO/100 VE Desktop Connection 1 +s 8086244910140217 EtherExpress PRO/100 VE Desktop Connection 1 +s 8086244910140234 EtherExpress PRO/100 VE Desktop Connection 1 +s 808624491014023d EtherExpress PRO/100 VE Desktop Connection 1 +s 8086244910140244 EtherExpress PRO/100 VE Desktop Connection 1 +s 8086244910140245 EtherExpress PRO/100 VE Desktop Connection 1 +s 80862449109f315d EtherExpress PRO/100 VE Network Connection 1 +s 80862449109f3181 EtherExpress PRO/100 VE Network Connection 1 +s 8086244911867801 EtherExpress PRO/100 VE Adapter 1 +s 80862449144d2602 HomePNA 1M CNR 1 +s 8086244980863010 EtherExpress PRO/100 VE Desktop Adapter 1 +s 8086244980863011 EtherExpress PRO/100 VM Desktop Adapter 1 +s 8086244980863012 82562EH based Phoneline Desktop Adapter 1 +s 8086244980863013 EtherExpress PRO/100 VE Network Connection 1 +s 8086244980863014 EtherExpress PRO/100 VM Network Connection 1 +s 8086244980863015 82562EH based Phoneline Network Connection 1 +s 8086244980863016 EtherExpress PRO/100 P Mobile Combo Adapter 1 +s 8086244980863017 EtherExpress PRO/100 P Mobile Adapter 1 +s 8086244980863018 EtherExpress PRO/100 Network Connection 1 +d 8086244a 82801BAM IDE U100 0 +d 8086244b 82801BA IDE U100 0 +d 8086244c 82801BAM ISA Bridge (LPC) 0 +d 8086244e 82801BA/CA PCI Bridge 0 +d 80862480 82801CA ISA Bridge (LPC) 0 +d 80862482 82801CA/CAM USB (Hub #1) 0 +d 80862483 82801CA/CAM SMBus 0 +d 80862484 82801CA/CAM USB (Hub #2) 0 +d 80862485 82801CA/CAM AC'97 Audio 0 +d 80862486 82801CA/CAM AC'97 Modem 0 +d 80862487 82801CA/CAM USB (Hub #3) 0 +d 8086248a 82801CAM IDE U100 0 +d 8086248b 82801CA IDE U100 0 +d 8086248c 82801CAM ISA Bridge (LPC) 0 +d 80862500 82820 820 (Camino) Chipset Host Bridge (MCH) 0 +s 808625001043801c P3C-2000 system chipset 0 +d 80862501 82820 820 (Camino) Chipset Host Bridge (MCH) 0 +s 808625011043801c P3C-2000 system chipset 0 +d 8086250b 82820 820 (Camino) Chipset Host Bridge 0 +d 8086250f 82820 820 (Camino) Chipset AGP Bridge 0 +d 80862520 82805AA MTH Memory Translator Hub 0 +d 80862521 82804AA MRH-S Memory Repeater Hub for SDRAM 0 +d 80862530 82850 850 (Tehama) Chipset Host Bridge (MCH) 0 +d 80862531 82850 860 (Wombat) Chipset Host Bridge (MCH) 0 +d 80862532 82850/82860 850/860 (Tehama/Wombat) Chipset AGP Bridge 0 +d 80862533 82860 860 (Wombat) Chipset PCI Bridge 0 +d 80862534 82860 860 (Wombat) Chipset PCI Bridge 0 +d 80863092 Integrated RAID 0 +d 80863575 82830 830 Chipset Host Bridge 0 +d 80863576 82830 830 Chipset AGP Bridge 0 +d 80863577 82830 CGC [Chipset Graphics Controller] 0 +d 80863578 82830 830 Chipset Host Bridge 0 +d 80865200 EtherExpress PRO/100 Intelligent Server 0 +d 80865201 EtherExpress PRO/100 Intelligent Server 0 +s 8086520180860001 EtherExpress PRO/100 Server Ethernet Adapter 0 +d 8086530d 80310 IOP [IO Processor] 0 +d 80867000 82371SB PIIX3 ISA [Natoma/Triton II] 0 +d 80867010 82371SB PIIX3 IDE [Natoma/Triton II] 0 +d 80867020 82371SB PIIX3 USB [Natoma/Triton II] 0 +d 80867030 430VX - 82437VX TVX [Triton VX] 0 +d 80867100 430TX - 82439TX MTXC 0 +d 80867110 82371AB/EB/MB PIIX4 ISA 0 +d 80867111 82371AB/EB/MB PIIX4 IDE 0 +d 80867112 82371AB/EB/MB PIIX4 USB 0 +d 80867113 82371AB/EB/MB PIIX4 ACPI 0 +d 80867120 82810 GMCH [Graphics Memory Controller Hub] 0 +d 80867121 82810 CGC [Chipset Graphics Controller] 0 +d 80867122 82810 DC-100 GMCH [Graphics Memory Controller Hub] 0 +d 80867123 82810 DC-100 CGC [Chipset Graphics Controller] 0 +d 80867124 82810E DC-133 GMCH [Graphics Memory Controller Hub] 0 +d 80867125 82810E DC-133 CGC [Chipset Graphics Controller] 0 +d 80867126 82810 DC-133 System and Graphics Controller 0 +d 80867128 82810-M DC-100 System and Graphics Controller 0 +d 8086712a 82810-M DC-133 System and Graphics Controller 0 +d 80867180 440LX/EX - 82443LX/EX Host bridge 0 +d 80867181 440LX/EX - 82443LX/EX AGP bridge 0 +d 80867190 440BX/ZX/DX - 82443BX/ZX/DX Host bridge 0 +s 808671900e110500 Armada 1750 Laptop System Chipset 0 +s 8086719011790001 Toshiba Tecra 8100 Laptop System Chipset 0 +d 80867191 440BX/ZX/DX - 82443BX/ZX/DX AGP bridge 0 +d 80867192 440BX/ZX/DX - 82443BX/ZX/DX Host bridge (AGP disabled) 0 +s 808671920e110460 Armada 1700 Laptop System Chipset 0 +d 80867194 82440MX Host Bridge 0 +d 80867195 82440MX AC'97 Audio Controller 0 +s 8086719510cf1099 QSound_SigmaTel Stac97 PCI Audio 0 +s 8086719511d40040 SoundMAX Integrated Digital Audio 0 +s 8086719511d40048 SoundMAX Integrated Digital Audio 0 +d 80867196 82440MX AC'97 Modem Controller 0 +d 80867198 82440MX ISA Bridge 0 +d 80867199 82440MX EIDE Controller 0 +d 8086719a 82440MX USB Universal Host Controller 0 +d 8086719b 82440MX Power Management Controller 0 +d 808671a0 440GX - 82443GX Host bridge 0 +d 808671a1 440GX - 82443GX AGP bridge 0 +d 808671a2 440GX - 82443GX Host bridge (AGP disabled) 0 +d 80867600 82372FB PCI to ISA Bridge 0 +d 80867601 82372FB PIIX4 IDE 0 +d 80867602 82372FB [PCI-to-USB UHCI] 0 +d 80867603 82372FB System Management Bus Controller 0 +d 80867800 i740 0 +s 80867800003d0008 Starfighter AGP 0 +s 80867800003d000b Starfighter AGP 0 +s 8086780010920100 Stealth II G460 0 +s 8086780010b4201a Lightspeed 740 0 +s 8086780010b4202f Lightspeed 740 0 +s 8086780080860000 Terminator 2x/i 0 +s 8086780080860100 Intel740 Graphics Accelerator 0 +d 80868086 1 +d 808684c4 450KX/GX [Orion] - 82454KX/GX PCI bridge 0 +d 808684c5 450KX/GX [Orion] - 82453KX/GX Memory controller 0 +d 808684ca 450NX - 82451NX Memory & I/O Controller 0 +d 808684cb 450NX - 82454NX/84460GX PCI Expander Bridge 0 +d 808684e0 460GX - 84460GX System Address Controller (SAC) 0 +d 808684e1 460GX - 84460GX System Data Controller (SDC) 0 +d 808684e2 460GX - 84460GX AGP Bridge (GXB) 0 +d 808684e3 460GX - 84460GX Memory Address Controller (MAC) 0 +d 808684e4 460GX - 84460GX Memory Data Controller (MDC) 0 +d 808684e6 460GX - 82466GX Wide and fast PCI eXpander Bridge (WXB) 0 +d 80869621 Integrated RAID 0 +d 80869622 Integrated RAID 0 +d 80869641 Integrated RAID 0 +d 808696a1 Integrated RAID 0 +d 8086ffff 450NX/GX [Orion] - 82453KX/GX Memory controller [BUG] 0 +v 8800 Trigem Computer Inc. 0 +d 88002008 Video assistent component 0 +v 8866 T-Square Design Inc. 0 +v 8888 Silicon Magic 0 +v 8e0e Computone Corporation 0 +v 8e2e KTI 0 +d 8e2e3000 ET32P2 0 +v 9004 Adaptec 0 +d 90041078 AIC-7810 0 +d 90041160 AIC-1160 [Family Fibre Channel Adapter] 0 +d 90042178 AIC-7821 0 +d 90043860 AHA-2930CU 0 +d 90043b78 AHA-4844W/4844UW 0 +d 90045075 AIC-755x 0 +d 90045078 AHA-7850 0 +s 9004507890047850 AHA-2904/Integrated AIC-7850 0 +d 90045175 AIC-755x 0 +d 90045178 AIC-7851 0 +d 90045275 AIC-755x 0 +d 90045278 AIC-7852 0 +d 90045375 AIC-755x 0 +d 90045378 AIC-7850 0 +d 90045475 AIC-755x 0 +d 90045478 AIC-7850 0 +d 90045575 AVA-2930 0 +d 90045578 AIC-7855 0 +d 90045675 AIC-755x 0 +d 90045678 AIC-7856 0 +d 90045775 AIC-755x 0 +d 90045778 AIC-7850 0 +d 90045800 AIC-5800 0 +d 90045900 ANA-5910/5930/5940 ATM155 & 25 LAN Adapter 0 +d 90045905 ANA-5910A/5930A/5940A ATM Adapter 0 +d 90046038 AIC-3860 0 +d 90046075 AIC-1480 / APA-1480 0 +s 9004607590047560 AIC-1480 / APA-1480 Cardbus 0 +d 90046078 AIC-7860 0 +d 90046178 AIC-7861 0 +s 9004617890047861 AHA-2940AU Single 0 +d 90046278 AIC-7860 0 +d 90046378 AIC-7860 0 +d 90046478 AIC-786x 0 +d 90046578 AIC-786x 0 +d 90046678 AIC-786x 0 +d 90046778 AIC-786x 0 +d 90046915 ANA620xx/ANA69011A 0 +s 9004691590040008 ANA69011A/TX 10/100 0 +s 9004691590040009 ANA69011A/TX 10/100 0 +s 9004691590040010 ANA62022 2-port 10/100 0 +s 9004691590040018 ANA62044 4-port 10/100 0 +s 9004691590040019 ANA62044 4-port 10/100 0 +s 9004691590040020 ANA62022 2-port 10/100 0 +s 9004691590040028 ANA69011A/TX 10/100 0 +s 9004691590048008 ANA69011A/TX 64 bit 10/100 0 +s 9004691590048009 ANA69011A/TX 64 bit 10/100 0 +s 9004691590048010 ANA62022 2-port 64 bit 10/100 0 +s 9004691590048018 ANA62044 4-port 64 bit 10/100 0 +s 9004691590048019 ANA62044 4-port 64 bit 10/100 0 +s 9004691590048020 ANA62022 2-port 64 bit 10/100 0 +s 9004691590048028 ANA69011A/TX 64 bit 10/100 0 +d 90047078 AHA-294x / AIC-7870 0 +d 90047178 AHA-2940/2940W / AIC-7871 0 +d 90047278 AHA-3940/3940W / AIC-7872 0 +d 90047378 AHA-3985 / AIC-7873 0 +d 90047478 AHA-2944/2944W / AIC-7874 0 +d 90047578 AHA-3944/3944W / AIC-7875 0 +d 90047678 AHA-4944W/UW / AIC-7876 0 +d 90047778 AIC-787x 0 +d 90047810 AIC-7810 0 +d 90047815 AIC-7815 RAID+Memory Controller IC 0 +s 9004781590047815 ARO-1130U2 RAID Controller 0 +s 9004781590047840 AIC-7815 RAID+Memory Controller IC 0 +d 90047850 AIC-7850 0 +d 90047855 AHA-2930 0 +d 90047860 AIC-7860 0 +d 90047870 AIC-7870 0 +d 90047871 AHA-2940 0 +d 90047872 AHA-3940 0 +d 90047873 AHA-3980 0 +d 90047874 AHA-2944 0 +d 90047880 AIC-7880P 0 +d 90047890 AIC-7890 0 +d 90047891 AIC-789x 0 +d 90047892 AIC-789x 0 +d 90047893 AIC-789x 0 +d 90047894 AIC-789x 0 +d 90047895 AHA-2940U/UW / AHA-39xx / AIC-7895 0 +s 9004789590047890 AHA-2940U/2940UW Dual AHA-394xAU/AUW/AUWD AIC-7895B 0 +s 9004789590047891 AHA-2940U/2940UW Dual 0 +s 9004789590047892 AHA-3940AU/AUW/AUWD/UWD 0 +s 9004789590047894 AHA-3944AUWD 0 +s 9004789590047895 AHA-2940U/2940UW Dual AHA-394xAU/AUW/AUWD AIC-7895B 0 +s 9004789590047896 AHA-2940U/2940UW Dual AHA-394xAU/AUW/AUWD AIC-7895B 0 +s 9004789590047897 AHA-2940U/2940UW Dual AHA-394xAU/AUW/AUWD AIC-7895B 0 +d 90047896 AIC-789x 0 +d 90047897 AIC-789x 0 +d 90048078 AIC-7880U 0 +s 9004807890047880 AIC-7880P Ultra/Ultra Wide SCSI Chipset 0 +d 90048178 AHA-2940U/UW/D / AIC-7881U 0 +s 9004817890047881 AHA-2940UW SCSI Host Adapter 0 +d 90048278 AHA-3940U/UW/UWD / AIC-7882U 0 +d 90048378 AHA-3940U/UW / AIC-7883U 0 +d 90048478 AHA-2944UW / AIC-7884U 0 +d 90048578 AHA-3944U/UWD / AIC-7885 0 +d 90048678 AHA-4944UW / AIC-7886 0 +d 90048778 AHA-2940UW Pro / AIC-788x 0 +s 9004877890047887 2940UW Pro Ultra-Wide SCSI Controller 0 +d 90048878 AHA-2930UW / AIC-7888 0 +s 9004887890047888 AHA-2930UW SCSI Controller 0 +d 90048b78 ABA-1030 0 +d 9004ec78 AHA-4944W/UW 0 +v 9005 Adaptec 0 +d 90050010 AHA-2940U2/U2W 0 +s 9005001090052180 AHA-2940U2 SCSI Controller 0 +s 9005001090058100 AHA-2940U2B SCSI Controller 0 +s 900500109005a180 AHA-2940U2W SCSI Controller 0 +s 900500109005e100 AHA-2950U2B SCSI Controller 0 +d 90050011 AHA-2930U2 0 +d 90050013 78902 0 +s 9005001390050003 AAA-131U2 Array1000 1 Channel RAID Controller 0 +d 9005001f AHA-2940U2/U2W / 7890/7891 0 +s 9005001f9005000f 2940U2W SCSI Controller 0 +s 9005001f9005a180 2940U2W SCSI Controller 0 +d 90050020 AIC-7890 0 +d 9005002f AIC-7890 0 +d 90050030 AIC-7890 0 +d 9005003f AIC-7890 0 +d 90050050 AHA-3940U2x/395U2x 0 +s 900500509005f500 AHA-3950U2B 0 +d 90050051 AHA-3950U2D 0 +s 900500519005b500 AHA-3950U2D 0 +d 90050053 AIC-7896 SCSI Controller 0 +s 900500539005ffff AIC-7896 SCSI Controller mainboard implementation 0 +d 9005005f AIC-7896U2/7897U2 0 +d 90050080 AIC-7892A U160/m 0 +s 900500800e11e2a0 Compaq 64-Bit/66MHz Wide Ultra3 SCSI Adapter 0 +s 90050080900562a0 29160N Ultra160 SCSI Controller 0 +s 900500809005e220 29160LP Low Profile Ultra160 SCSI Controller 0 +s 900500809005e2a0 29160 Ultra160 SCSI Controller 0 +d 90050081 AIC-7892B U160/m 0 +s 90050081900562a1 19160 Ultra160 SCSI Controller 0 +d 90050083 AIC-7892D U160/m 0 +d 9005008f AIC-7892P U160/m 0 +d 900500c0 AHA-3960D / AIC-7899A U160/m 0 +s 900500c00e11f620 Compaq 64-Bit/66MHz Dual Channel Wide Ultra3 SCSI Adapter 0 +s 900500c09005f620 AHA-3960D U160/m 0 +d 900500c1 AIC-7899B U160/m 0 +d 900500c3 AIC-7899D U160/m 0 +d 900500c5 RAID subsystem HBA 0 +d 900500cf AIC-7899P U160/m 0 +v 907f Atronics 0 +d 907f2015 IDE-2015PL 0 +v 919a Gigapixel Corp 0 +v 9412 Holtek 0 +d 94126565 6565 0 +v 9699 Omni Media Technology Inc 0 +d 96996565 6565 0 +v 9710 NetMos Technology 0 +d 97109815 VScom 021H-EP2 2 port parallel adaptor 0 +d 97109835 2xserial 1xparallel port adapter 0 +v a0a0 AOPEN Inc. 0 +v a0f1 UNISYS Corporation 0 +v a200 NEC Corporation 0 +v a259 Hewlett Packard 0 +v a25b Hewlett Packard GmbH PL24-MKT 0 +v a304 Sony 0 +v a727 3Com Corporation 0 +v aa42 Scitex Digital Video 0 +v ac1e Digital Receiver Technology Inc 0 +v b1b3 Shiva Europe Limited 0 +v c001 TSI Telsys 0 +v c0a9 Micron/Crucial Technology 0 +v c0de Motorola 0 +v c0fe Motion Engineering, Inc. 0 +v ca50 Varian Australia Pty Ltd 0 +v cafe Chrysalis-ITS 0 +v cccc Catapult Communications 0 +v d4d4 Dy4 Systems Inc 0 +d d4d40601 PCI Mezzanine Card 0 +v d531 I+ME ACTIA GmbH 1 +v d84d Exsys 0 +v dead Indigita Corporation 0 +v e000 Winbond 0 +d e000e000 W89C940 0 +v e159 Tiger Jet Network Inc. 0 +d e1590001 Model 300 128k 0 +s e159000100590001 128k ISDN-S/T Adapter 0 +s e159000100590003 128k ISDN-U Adapter 0 +v e4bf EKF Elektronik GmbH 0 +v ea01 Eagle Technology 0 +v eabb Aashima Technology B.V. 0 +v eace Endace Measurement Systems, Ltd 1 +v ecc0 Echo Corporation 0 +v edd8 ARK Logic Inc 0 +d edd8a091 1000PV [Stingray] 0 +d edd8a099 2000PV [Stingray] 0 +d edd8a0a1 2000MT 0 +d edd8a0a9 2000MI 0 +v fa57 Fast Search & Transfer ASA 0 +v febd Ultraview Corp. 0 +v feda Epigram Inc 0 +v fffe VMWare Inc 0 +d fffe0710 Virtual SVGA 0 +v ffff Illegal Vendor ID 0 diff --git a/src/video_out/libdha/pci.c b/src/video_out/libdha/pci.c new file mode 100644 index 000000000..350a5be42 --- /dev/null +++ b/src/video_out/libdha/pci.c @@ -0,0 +1,739 @@ +/* + (C) 2002 - library implementation by Nick Kyrshev + XFree86 3.3.3 scanpci.c, modified for GATOS/win/gfxdump by Øyvind Aabling. + */ +/* $XConsortium: scanpci.c /main/25 1996/10/27 11:48:40 kaleb $ */ +/* + * name: scanpci.c + * + * purpose: This program will scan for and print details of + * devices on the PCI bus. + + * author: Robin Cutshaw (robin@xfree86.org) + * + * supported O/S's: SVR4, UnixWare, SCO, Solaris, + * FreeBSD, NetBSD, 386BSD, BSDI BSD/386, + * Linux, Mach/386, ISC + * DOS (WATCOM 9.5 compiler) + * + * compiling: [g]cc scanpci.c -o scanpci + * for SVR4 (not Solaris), UnixWare use: + * [g]cc -DSVR4 scanpci.c -o scanpci + * for DOS, watcom 9.5: + * wcc386p -zq -omaxet -7 -4s -s -w3 -d2 name.c + * and link with PharLap or other dos extender for exe + * + */ + +/* $XFree86: xc/programs/Xserver/hw/xfree86/etc/scanpci.c,v 3.34.2.17 1998/11/10 11:55:40 dawes Exp $ */ + +/* + * Copyright 1995 by Robin Cutshaw + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that + * copyright notice and this permission notice appear in supporting + * documentation, and that the names of the above listed copyright holder(s) + * not be used in advertising or publicity pertaining to distribution of + * the software without specific, written prior permission. The above listed + * copyright holder(s) make(s) no representations about the suitability of this + * software for any purpose. It is provided "as is" without express or + * implied warranty. + * + * THE ABOVE LISTED COPYRIGHT HOLDER(S) DISCLAIM(S) ALL WARRANTIES WITH REGARD + * TO THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY + * AND FITNESS, IN NO EVENT SHALL THE ABOVE LISTED COPYRIGHT HOLDER(S) BE + * LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY + * DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER + * IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING + * OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +#include "libdha.h" +#include +#include +#include +#ifdef __unix__ +#include +#endif +#include "AsmMacros.h" +/* OS depended stuff */ +#if defined (linux) +#include "sysdep/pci_linux.c" +#elif defined (__FreeBSD__) +#include "sysdep/pci_freebsd.c" +#elif defined (__386BSD__) +#include "sysdep/pci_386bsd.c" +#elif defined (__NetBSD__) +#include "sysdep/pci_netbsd.c" +#elif defined (__OpenBSD__) +#include "sysdep/pci_openbsd.c" +#elif defined (__bsdi__) +#include "sysdep/pci_bsdi.c" +#elif defined (Lynx) +#include "sysdep/pci_lynx.c" +#elif defined (MACH386) +#include "sysdep/pci_mach386.c" +#elif defined (__SVR4) +#if !defined(SVR4) +#define SVR4 +#endif +#include "sysdep/pci_svr4.c" +#elif defined (SCO) +#include "sysdep/pci_sco.c" +#elif defined (ISC) +#include "sysdep/pci_isc.c" +#elif defined (__EMX__) +#include "sysdep/pci_os2.c" +#elif defined (_WIN32) || defined(__CYGWIN__) +#include "sysdep/pci_win32.c" +#endif + +#if 0 +#if defined(__SUNPRO_C) || defined(sun) || defined(__sun) +#include +#else +#include +#endif +#include +#endif + +#if defined(Lynx) && defined(__powerpc__) +/* let's mimick the Linux Alpha stuff for LynxOS so we don't have + * to change too much code + */ +#include + +static unsigned char *pciConfBase; + +static __inline__ unsigned long +static swapl(unsigned long val) +{ + unsigned char *p = (unsigned char *)&val; + return ((p[3] << 24) | (p[2] << 16) | (p[1] << 8) | (p[0] << 0)); +} + + +#define BUS(tag) (((tag)>>16)&0xff) +#define DFN(tag) (((tag)>>8)&0xff) + +#define PCIBIOS_DEVICE_NOT_FOUND 0x86 +#define PCIBIOS_SUCCESSFUL 0x00 + +int pciconfig_read( + unsigned char bus, + unsigned char dev, + unsigned char offset, + int len, /* unused, alway 4 */ + unsigned long *val) +{ + unsigned long _val; + unsigned long *ptr; + + dev >>= 3; + if (bus || dev >= 16) { + *val = 0xFFFFFFFF; + return PCIBIOS_DEVICE_NOT_FOUND; + } else { + ptr = (unsigned long *)(pciConfBase + ((1<>= 3; + _val = swapl(val); + if (bus || dev >= 16) { + return PCIBIOS_DEVICE_NOT_FOUND; + } else { + ptr = (unsigned long *)(pciConfBase + ((1<=MAX_PCI_DEVICES) return ; + + pci_lst[pcicards].bus = pcibus ; + pci_lst[pcicards].card = pcicard ; + pci_lst[pcicards].func = pcifunc ; + pci_lst[pcicards].vendor = pcr->_vendor ; + pci_lst[pcicards].device = pcr->_device ; + pci_lst[pcicards].base0 = 0xFFFFFFFF ; + pci_lst[pcicards].base1 = 0xFFFFFFFF ; + pci_lst[pcicards].base2 = 0xFFFFFFFF ; + pci_lst[pcicards].baserom = 0x000C0000 ; + if (pcr->_base0) pci_lst[pcicards].base0 = pcr->_base0 & + ((pcr->_base0&0x1) ? 0xFFFFFFFC : 0xFFFFFFF0) ; + if (pcr->_base1) pci_lst[pcicards].base1 = pcr->_base1 & + ((pcr->_base1&0x1) ? 0xFFFFFFFC : 0xFFFFFFF0) ; + if (pcr->_base2) pci_lst[pcicards].base2 = pcr->_base2 & + ((pcr->_base2&0x1) ? 0xFFFFFFFC : 0xFFFFFFF0) ; + if (pcr->_baserom) pci_lst[pcicards].baserom = pcr->_baserom ; + + pcicards++; +} + +/*main(int argc, char *argv[])*/ +int pci_scan(pciinfo_t *pci_list,unsigned *num_pci) +{ + unsigned int idx; + struct pci_config_reg pcr; + int do_mode1_scan = 0, do_mode2_scan = 0; + int func, hostbridges=0; + int ret = -1; + + pci_lst = pci_list; + + ret = enable_os_io(); + if (ret != 0) + return(ret); + + if((pcr._configtype = pci_config_type()) == 0xFFFF) return ENODEV; + + /* Try pci config 1 probe first */ + + if ((pcr._configtype == 1) || do_mode1_scan) { + /*printf("\nPCI probing configuration type 1\n");*/ + + pcr._ioaddr = 0xFFFF; + + pcr._pcibuses[0] = 0; + pcr._pcinumbus = 1; + pcr._pcibusidx = 0; + idx = 0; + + do { + /*printf("Probing for devices on PCI bus %d:\n\n", pcr._pcibusidx);*/ + + for (pcr._cardnum = 0x0; pcr._cardnum < MAX_PCI_DEVICES_PER_BUS; + pcr._cardnum += 0x1) { + func = 0; + do { /* loop over the different functions, if present */ + pcr._device_vendor = pci_get_vendor(pcr._pcibuses[pcr._pcibusidx], pcr._cardnum, + func); + if ((pcr._vendor == 0xFFFF) || (pcr._device == 0xFFFF)) + break; /* nothing there */ + + /*printf("\npci bus 0x%x cardnum 0x%02x function 0x%04x: vendor 0x%04x device 0x%04x\n", + pcr._pcibuses[pcr._pcibusidx], pcr._cardnum, func, + pcr._vendor, pcr._device);*/ + pcibus = pcr._pcibuses[pcr._pcibusidx]; + pcicard = pcr._cardnum; + pcifunc = func; + + pcr._status_command = pci_config_read_long(pcr._pcibuses[pcr._pcibusidx], + pcr._cardnum,func,PCI_CMD_STAT_REG); + pcr._class_revision = pci_config_read_long(pcr._pcibuses[pcr._pcibusidx], + pcr._cardnum,func,PCI_CLASS_REG); + pcr._bist_header_latency_cache = pci_config_read_long(pcr._pcibuses[pcr._pcibusidx], + pcr._cardnum,func,PCI_HEADER_MISC); + pcr._base0 = pci_config_read_long(pcr._pcibuses[pcr._pcibusidx], + pcr._cardnum,func,PCI_MAP_REG_START); + pcr._base1 = pci_config_read_long(pcr._pcibuses[pcr._pcibusidx], + pcr._cardnum,func,PCI_MAP_REG_START+4); + pcr._base2 = pci_config_read_long(pcr._pcibuses[pcr._pcibusidx], + pcr._cardnum,func,PCI_MAP_REG_START+8); + pcr._base3 = pci_config_read_long(pcr._pcibuses[pcr._pcibusidx], + pcr._cardnum,func,PCI_MAP_REG_START+0x0C); + pcr._base4 = pci_config_read_long(pcr._pcibuses[pcr._pcibusidx], + pcr._cardnum,func,PCI_MAP_REG_START+0x10); + pcr._base5 = pci_config_read_long(pcr._pcibuses[pcr._pcibusidx], + pcr._cardnum,func,PCI_MAP_REG_START+0x14); + pcr._baserom = pci_config_read_long(pcr._pcibuses[pcr._pcibusidx], + pcr._cardnum,func,PCI_MAP_ROM_REG); + pcr._max_min_ipin_iline = pci_config_read_long(pcr._pcibuses[pcr._pcibusidx], + pcr._cardnum,func,PCI_INTERRUPT_REG); + pcr._user_config = pci_config_read_long(pcr._pcibuses[pcr._pcibusidx], + pcr._cardnum,func,PCI_REG_USERCONFIG); + /* check for pci-pci bridges */ +#define PCI_CLASS_MASK 0xff000000 +#define PCI_SUBCLASS_MASK 0x00ff0000 +#define PCI_CLASS_BRIDGE 0x06000000 +#define PCI_SUBCLASS_BRIDGE_PCI 0x00040000 + switch(pcr._class_revision & (PCI_CLASS_MASK|PCI_SUBCLASS_MASK)) { + case PCI_CLASS_BRIDGE|PCI_SUBCLASS_BRIDGE_PCI: + if (pcr._secondary_bus_number > 0) { + pcr._pcibuses[pcr._pcinumbus++] = pcr._secondary_bus_number; + } + break; + case PCI_CLASS_BRIDGE: + if ( ++hostbridges > 1) { + pcr._pcibuses[pcr._pcinumbus] = pcr._pcinumbus; + pcr._pcinumbus++; + } + break; + default: + break; + } + if((func==0) && ((pcr._header_type & PCI_MULTIFUNC_DEV) == 0)) { + /* not a multi function device */ + func = 8; + } else { + func++; + } + + if (idx++ >= MAX_PCI_DEVICES) + continue; + + identify_card(&pcr); + } while( func < 8 ); + } + } while (++pcr._pcibusidx < pcr._pcinumbus); + } + +#if !defined(__alpha__) && !defined(__powerpc__) + /* Now try pci config 2 probe (deprecated) */ + + if ((pcr._configtype == 2) || do_mode2_scan) { + outb(PCI_MODE2_ENABLE_REG, 0xF1); + outb(PCI_MODE2_FORWARD_REG, 0x00); /* bus 0 for now */ + + /*printf("\nPCI probing configuration type 2\n");*/ + + pcr._pcibuses[0] = 0; + pcr._pcinumbus = 1; + pcr._pcibusidx = 0; + idx = 0; + + do { + for (pcr._ioaddr = 0xC000; pcr._ioaddr < 0xD000; pcr._ioaddr += 0x0100){ + outb(PCI_MODE2_FORWARD_REG, pcr._pcibuses[pcr._pcibusidx]); /* bus 0 for now */ + pcr._device_vendor = inl(pcr._ioaddr); + outb(PCI_MODE2_FORWARD_REG, 0x00); /* bus 0 for now */ + + if ((pcr._vendor == 0xFFFF) || (pcr._device == 0xFFFF)) + continue; + if ((pcr._vendor == 0xF0F0) || (pcr._device == 0xF0F0)) + continue; /* catch ASUS P55TP4XE motherboards */ + + /*printf("\npci bus 0x%x slot at 0x%04x, vendor 0x%04x device 0x%04x\n", + pcr._pcibuses[pcr._pcibusidx], pcr._ioaddr, pcr._vendor, + pcr._device);*/ + pcibus = pcr._pcibuses[pcr._pcibusidx] ; + pcicard = pcr._ioaddr ; pcifunc = 0 ; + + outb(PCI_MODE2_FORWARD_REG, pcr._pcibuses[pcr._pcibusidx]); /* bus 0 for now */ + pcr._status_command = inl(pcr._ioaddr + 0x04); + pcr._class_revision = inl(pcr._ioaddr + 0x08); + pcr._bist_header_latency_cache = inl(pcr._ioaddr + 0x0C); + pcr._base0 = inl(pcr._ioaddr + 0x10); + pcr._base1 = inl(pcr._ioaddr + 0x14); + pcr._base2 = inl(pcr._ioaddr + 0x18); + pcr._base3 = inl(pcr._ioaddr + 0x1C); + pcr._base4 = inl(pcr._ioaddr + 0x20); + pcr._base5 = inl(pcr._ioaddr + 0x24); + pcr._baserom = inl(pcr._ioaddr + 0x30); + pcr._max_min_ipin_iline = inl(pcr._ioaddr + 0x3C); + pcr._user_config = inl(pcr._ioaddr + 0x40); + outb(PCI_MODE2_FORWARD_REG, 0x00); /* bus 0 for now */ + + /* check for pci-pci bridges (currently we only know Digital) */ + if ((pcr._vendor == 0x1011) && (pcr._device == 0x0001)) + if (pcr._secondary_bus_number > 0) + pcr._pcibuses[pcr._pcinumbus++] = pcr._secondary_bus_number; + + if (idx++ >= MAX_PCI_DEVICES) + continue; + + identify_card(&pcr); + } + } while (++pcr._pcibusidx < pcr._pcinumbus); + + outb(PCI_MODE2_ENABLE_REG, 0x00); + } + +#endif /* __alpha__ */ + + disable_os_io(); + *num_pci = pcicards; + + return 0 ; + +} + +#if !defined(ENOTSUP) +#if defined(EOPNOTSUPP) +#define ENOTSUP EOPNOTSUPP +#else +#warning "ENOTSUP nor EOPNOTSUPP defined!" +#endif +#endif + +int pci_config_read(unsigned char bus, unsigned char dev, unsigned char func, + unsigned char cmd, int len, unsigned long *val) +{ + int ret; + + if (len != 4) + { + printf("pci_config_read: reading non-dword not supported!\n"); + return(ENOTSUP); + } + + ret = enable_os_io(); + if (ret != 0) + return(ret); + ret = pci_config_read_long(bus, dev, func, cmd); + disable_os_io(); + + *val = ret; + return(0); +} + +int enable_app_io( void ) +{ + return enable_os_io(); +} + +int disable_app_io( void ) +{ + return disable_os_io(); +} diff --git a/src/video_out/libdha/pci_db2c.awk b/src/video_out/libdha/pci_db2c.awk new file mode 100644 index 000000000..feaa1c7a1 --- /dev/null +++ b/src/video_out/libdha/pci_db2c.awk @@ -0,0 +1,267 @@ +# This file converts given pci.db to "C" source and header files +# For latest version of pci ids see: http://pciids.sf.net +# Copyright 2002 Nick Kurshev +# +# Usage: awk -f pci_db2c.awk pci.db +# +# Tested with Gawk v 3.0.x and Mawk 1.3.3 +# But it should work with standard Awk implementations (hopefully). +# (Nobody tested it with Nawk, but it should work, too). +# + +BEGIN { + + if(ARGC != 2) { +# check for arguments: + print "Usage awk -f pci_db2c.awk pci.db (and make sure pci.db file exists first)"; + exit(1); + } + in_file = ARGV[1]; + vendor_file = "pci_vendors.h"; + ids_file = "pci_ids.h" + name_file = "pci_names.c" + name_h_file = "pci_names.h" + dev_ids_file = "pci_dev_ids.c" + line=0; +# print out head lines + print_head(vendor_file); + print_head(ids_file); + print_head(name_file); + print_head(name_h_file); + print_head(dev_ids_file); + print "#ifndef PCI_VENDORS_INCLUDED" >vendor_file + print "#define PCI_VENDORS_INCLUDED 1">vendor_file + print "" >vendor_file + print "#ifndef PCI_IDS_INCLUDED" >ids_file + print "#define PCI_IDS_INCLUDED 1">ids_file + print "" >ids_file + print "#include \"pci_vendors.h\"">ids_file + print "" >ids_file + + print "#ifndef PCI_NAMES_INCLUDED" >name_h_file + print "#define PCI_NAMES_INCLUDED 1">name_h_file + print "" >name_h_file + print_name_struct(name_h_file); + print "#include ">name_file + print "#include \"pci_names.h\"">name_file + print "#include \"pci_dev_ids.c\"">name_file + print "">name_file + print "static struct vendor_id_s vendor_ids[] = {">name_file + first_pass=1; + init_name_db(); + while(getline 0 && field[4] == "0") + { + init_device_db() + svend_name = get_short_vendor_name(field[3]) + printf("#define VENDOR_%s\t", svend_name) >vendor_file; + if(length(svend_name) < 9) printf("\t") >vendor_file; + printf("0x%s /*%s*/\n",field[2], name_field) >vendor_file; + printf("{ 0x%s, \"%s\", dev_lst_%s },\n",field[2], name_field, field[2]) >name_file; + printf("/* Vendor: %s: %s */\n", field[2], name_field) > ids_file + if(first_pass == 1) { first_pass=0; } + else { print "{ 0xFFFF, NULL }\n};" >dev_ids_file; } + printf("static const struct device_id_s dev_lst_%s[]={\n", field[2])>dev_ids_file + } + if(field[1] == "d" && length(field[3])>0 && field[4] == "0") + { + sdev_name = get_short_device_name(field[3]) + full_name = sprintf("#define DEVICE_%s_%s", svend_name, sdev_name); + printf("%s\t", full_name) >ids_file + if(length(full_name) < 9) printf("\t") >ids_file; + if(length(full_name) < 17) printf("\t") >ids_file; + if(length(full_name) < 25) printf("\t") >ids_file; + if(length(full_name) < 32) printf("\t") >ids_file; + if(length(full_name) < 40) printf("\t") >ids_file; + if(length(full_name) < 48) printf("\t") >ids_file; + printf("0x%s /*%s*/\n", substr(field[2], 5), name_field) >ids_file + printf("{ 0x%s, \"%s\" },\n", substr(field[2], 5), name_field) >dev_ids_file + } + if(field[1] == "s" && length(field[3])>0 && field[4] == "0") + { + subdev_name = get_short_subdevice_name(field[3]) + full_name = sprintf("#define SUBDEVICE_%s_%s", svend_name, subdev_name) + printf("\t%s\t", full_name) >ids_file + if(length(full_name) < 9) printf("\t") >ids_file; + if(length(full_name) < 17) printf("\t") >ids_file; + if(length(full_name) < 25) printf("\t") >ids_file; + if(length(full_name) < 32) printf("\t") >ids_file; + if(length(full_name) < 40) printf("\t") >ids_file; + printf("0x%s /*%s*/\n", substr(field[2], 9), name_field) >ids_file + } + } + print "Total lines parsed:", line; + print "">vendor_file + print "#endif/*PCI_VENDORS_INCLUDED*/">vendor_file + print "">ids_file + print "#endif/*PCI_IDS_INCLUDED*/">ids_file + print "">name_h_file + print "#endif/*PCI_NAMES_INCLUDED*/">name_h_file + print "};">name_file + print "{ 0xFFFF, NULL }" >dev_ids_file; + print "};">dev_ids_file + print_func_bodies(name_file); +} + +function print_head( out_file) +{ + print "/*" >out_file; + printf(" * File: %s\n", out_file) >out_file; + printf(" * This file was generated automatically. Don't modify it.\n") >out_file; + print "*/" >out_file; + return; +} + +function print_name_struct(out_file) +{ + print "#ifdef __cplusplus" >out_file + print "extern \"C\" {" >out_file + print "#endif" >out_file + print "">out_file + print "struct device_id_s" >out_file + print "{" >out_file + print "\tunsigned short\tid;" >out_file + print "\tconst char *\tname;" >out_file + print "};" >out_file + print "">out_file + print "struct vendor_id_s" >out_file + print "{" >out_file + print "\tunsigned short\tid;" >out_file + print "\tconst char *\tname;" >out_file + print "\tconst struct device_id_s *\tdev_list;" >out_file + print "};" >out_file + print "extern const char *pci_vendor_name(unsigned short id);">out_file + print "extern const char *pci_device_name(unsigned short vendor_id, unsigned short device_id);">out_file + print "">out_file + print "#ifdef __cplusplus" >out_file + print "}" >out_file + print "#endif" >out_file + return +} + +function print_func_bodies(out_file) +{ + print "">out_file + print "const char *pci_vendor_name(unsigned short id)" >out_file + print "{" >out_file + print " unsigned i;" >out_file + print " for(i=0;iout_file + print " {" >out_file + print "\tif(vendor_ids[i].id == id) return vendor_ids[i].name;" >out_file + print " }" >out_file + print " return NULL;" >out_file + print "}">out_file + print "" >out_file + print "const char *pci_device_name(unsigned short vendor_id, unsigned short device_id)" >out_file + print "{" >out_file + print " unsigned i, j;" >out_file + print " for(i=0;iout_file + print " {" >out_file + print "\tif(vendor_ids[i].id == vendor_id)" >out_file + print "\t{" >out_file + print "\t j=0;" >out_file + print "\t while(vendor_ids[i].dev_list[j].id != 0xFFFF)" >out_file + print "\t {">out_file + print "\t\tif(vendor_ids[i].dev_list[j].id == device_id) return vendor_ids[i].dev_list[j].name;">out_file + print "\t\tj++;">out_file + print "\t };">out_file + print "\t break;" >out_file + print "\t}" >out_file + print " }" >out_file + print " return NULL;">out_file + print "}">out_file + return +} + +function kill_double_quoting(fld) +{ + n=split(fld,phrases, "[\"]"); + new_fld = phrases[1] + for(i=2;i<=n;i++) new_fld = sprintf("%s\\\"%s", new_fld, phrases[i]) + return new_fld +} + +function init_name_db() +{ + vendor_names[1]="" +} + +function init_device_db() +{ +# delete device_names + for( i in device_names ) delete device_names[i]; + device_names[1]="" +# delete subdevice_names + for( i in subdevice_names ) delete subdevice_names[i]; + subdevice_names[1] = "" +} + +function get_short_vendor_name(from) +{ + n=split(from, name, "[ ]"); + new_name = toupper(name[1]); + if(length(new_name)<3) new_name = sprintf("%s_%s", new_name, toupper(name[2])); + n=split(new_name, name, "[^0-9A-Za-z]"); + svendor = name[1]; + for(i=2;i<=n;i++) svendor=sprintf("%s%s%s", svendor, length(name[i])?"_":"", name[i]); + new_name = svendor; + vend_suffix = 2; +# check for unique + while(new_name in vendor_names) + { + new_name = sprintf("%s%u", svendor, vend_suffix) + vend_suffix = vend_suffix + 1; + } +# Add new name in array of vendor's names + vendor_names[new_name] = new_name + return new_name; +} + +function get_short_device_name(from_name) +{ + n=split(from_name, name, "[ ]"); + new_name = toupper(name[1]); + if(length(name[2])) new_name = sprintf("%s_%s", new_name, toupper(name[2])); + if(length(name[3])) new_name = sprintf("%s_%s", new_name, toupper(name[3])); + n=split(new_name, name, "[^0-9A-Za-z]"); + sdevice = name[1]; + for(i=2;i<=n;i++) sdevice=sprintf("%s%s%s", sdevice, length(name[i])?"_":"", name[i]); + new_name = sdevice; + dev_suffix = 2; +# check for unique + while(new_name in device_names) + { + new_name = sprintf("%s%u", sdevice, dev_suffix) + dev_suffix = dev_suffix + 1; + } +# Add new name in array of device names + device_names[new_name] = new_name + return new_name; +} + +function get_short_subdevice_name(from_name) +{ + n=split(from_name, name, "[ ]"); + new_name = toupper(name[1]); + if(length(name[2])) new_name = sprintf("%s_%s", new_name, toupper(name[2])); + if(length(name[3])) new_name = sprintf("%s_%s", new_name, toupper(name[3])); + n=split(new_name, name, "[^0-9A-Za-z]"); + ssdevice = name[1]; + for(i=2;i<=n;i++) ssdevice=sprintf("%s%s%s", ssdevice, length(name[i])?"_":"", name[i]); + new_name = ssdevice; + sdev_suffix = 2; +# check for unique + while(new_name in subdevice_names) + { + new_name = sprintf("%s%u", ssdevice, sdev_suffix) + sdev_suffix = sdev_suffix + 1; + } +# Add new name in array of subdevice names + subdevice_names[new_name] = new_name + return new_name; +} diff --git a/src/video_out/libdha/sysdep/AsmMacros_alpha.h b/src/video_out/libdha/sysdep/AsmMacros_alpha.h new file mode 100644 index 000000000..482b59000 --- /dev/null +++ b/src/video_out/libdha/sysdep/AsmMacros_alpha.h @@ -0,0 +1,26 @@ +/* + This file is based on: + $XFree86: xc/programs/Xserver/hw/xfree86/drivers/chips/util/AsmMacros.h,v 1.1 2001/11/16 21:13:34 tsi Exp $ + Modified for readability by Nick Kurshev +*/ + +#ifndef __ASM_MACROS_ALPHA_H +#define __ASM_MACROS_ALPHA_H +#if defined (linux) +#include +#elif defined (__FreeBSD__) +#include +extern void outb(u_int32_t port, u_int8_t val); +extern void outw(u_int32_t port, u_int16_t val); +extern void outl(u_int32_t port, u_int32_t val); +extern u_int8_t inb(u_int32_t port); +extern u_int16_t inw(u_int32_t port); +extern u_int32_t inl(u_int32_t port); +#else +#error This stuff is not ported on your system +#endif + +#define intr_disable() +#define intr_enable() + +#endif diff --git a/src/video_out/libdha/sysdep/AsmMacros_arm32.h b/src/video_out/libdha/sysdep/AsmMacros_arm32.h new file mode 100644 index 000000000..e618d32ee --- /dev/null +++ b/src/video_out/libdha/sysdep/AsmMacros_arm32.h @@ -0,0 +1,50 @@ +/* + This file is based on: + $XFree86: xc/programs/Xserver/hw/xfree86/drivers/chips/util/AsmMacros.h,v 1.1 2001/11/16 21:13:34 tsi Exp $ + Modified for readability by Nick Kurshev +*/ + +#ifndef __ASM_MACROS_ARM32_H +#define __ASM_MACROS_ARM32_H +unsigned int IOPortBase; /* Memory mapped I/O port area */ + +static __inline__ void outb(short port,char val) +{ + if ((unsigned short)port >= 0x400) return; + *(volatile unsigned char*)(((unsigned short)(port))+IOPortBase) = val; +} + +static __inline__ void outw(short port,short val) +{ + if ((unsigned short)port >= 0x400) return; + *(volatile unsigned short*)(((unsigned short)(port))+IOPortBase) = val; +} + +static __inline__ void outl(short port,int val) +{ + if ((unsigned short)port >= 0x400) return; + *(volatile unsigned long*)(((unsigned short)(port))+IOPortBase) = val; +} + +static __inline__ unsigned int inb(short port) +{ + if ((unsigned short)port >= 0x400) return((unsigned int)-1); + return(*(volatile unsigned char*)(((unsigned short)(port))+IOPortBase)); +} + +static __inline__ unsigned int inw(short port) +{ + if ((unsigned short)port >= 0x400) return((unsigned int)-1); + return(*(volatile unsigned short*)(((unsigned short)(port))+IOPortBase)); +} + +static __inline__ unsigned int inl(short port) +{ + if ((unsigned short)port >= 0x400) return((unsigned int)-1); + return(*(volatile unsigned long*)(((unsigned short)(port))+IOPortBase)); +} + +#define intr_disable() +#define intr_enable() + +#endif diff --git a/src/video_out/libdha/sysdep/AsmMacros_ia64.h b/src/video_out/libdha/sysdep/AsmMacros_ia64.h new file mode 100644 index 000000000..e59732fda --- /dev/null +++ b/src/video_out/libdha/sysdep/AsmMacros_ia64.h @@ -0,0 +1,16 @@ +/* + This file is based on: + $XFree86: xc/programs/Xserver/hw/xfree86/drivers/chips/util/AsmMacros.h,v 1.1 2001/11/16 21:13:34 tsi Exp $ + Modified for readability by Nick Kurshev +*/ + +#ifndef __ASM_MACROS_IA64_H +#define __ASM_MACROS_IA64_H + +#if defined(linux) +#include +#else +#error This stuff is not ported on your system +#endif + +#endif diff --git a/src/video_out/libdha/sysdep/AsmMacros_powerpc.h b/src/video_out/libdha/sysdep/AsmMacros_powerpc.h new file mode 100644 index 000000000..b17daddbd --- /dev/null +++ b/src/video_out/libdha/sysdep/AsmMacros_powerpc.h @@ -0,0 +1,62 @@ +/* + This file is based on: + $XFree86: xc/programs/Xserver/hw/xfree86/drivers/chips/util/AsmMacros.h,v 1.1 2001/11/16 21:13:34 tsi Exp $ + Modified for readability by Nick Kurshev +*/ + +#ifndef __ASM_MACROS_POWERPC_H +#define __ASM_MACROS_POWERPC_H + +#if defined(Lynx) + +extern unsigned char *ioBase; + +static __inline__ volatile void eieio() +{ + __asm__ __volatile__ ("eieio"); +} + +static __inline__ void outb(short port, unsigned char value) +{ + *(uchar *)(ioBase + port) = value; eieio(); +} + +static __inline__ void outw(short port, unsigned short value) +{ + *(unsigned short *)(ioBase + port) = value; eieio(); +} + +static __inline__ void outl(short port, unsigned short value) +{ + *(unsigned long *)(ioBase + port) = value; eieio(); +} + +static __inline__ unsigned char inb(short port) +{ + unsigned char val; + val = *((unsigned char *)(ioBase + port)); eieio(); + return(val); +} + +static __inline__ unsigned short inw(short port) +{ + unsigned short val; + val = *((unsigned short *)(ioBase + port)); eieio(); + return(val); +} + +static __inline__ unsigned long inl(short port) +{ + unsigned long val; + val = *((unsigned long *)(ioBase + port)); eieio(); + return(val); +} + +#define intr_disable() +#define intr_enable() + +#else +#error This stuff is not ported on your system +#endif + +#endif diff --git a/src/video_out/libdha/sysdep/AsmMacros_sparc.h b/src/video_out/libdha/sysdep/AsmMacros_sparc.h new file mode 100644 index 000000000..f6717b4bb --- /dev/null +++ b/src/video_out/libdha/sysdep/AsmMacros_sparc.h @@ -0,0 +1,53 @@ +/* + This file is based on: + $XFree86: xc/programs/Xserver/hw/xfree86/drivers/chips/util/AsmMacros.h,v 1.1 2001/11/16 21:13:34 tsi Exp $ + Modified for readability by Nick Kurshev +*/ + +#ifndef __ASM_MACROS_SPARC_H +#define __ASM_MACROS_SPARC_H + +#ifndef ASI_PL +#define ASI_PL 0x88 +#endif + +static __inline__ void outb(unsigned long port, char val) +{ + __asm__ __volatile__("stba %0, [%1] %2" : : "r" (val), "r" (port), "i" (ASI_PL)); +} + +static __inline__ void outw(unsigned long port, char val) +{ + __asm__ __volatile__("stha %0, [%1] %2" : : "r" (val), "r" (port), "i" (ASI_PL)); +} + +static __inline__ void outl(unsigned long port, char val) +{ + __asm__ __volatile__("sta %0, [%1] %2" : : "r" (val), "r" (port), "i" (ASI_PL)); +} + +static __inline__ unsigned int inb(unsigned long port) +{ + unsigned char ret; + __asm__ __volatile__("lduba [%1] %2, %0" : "=r" (ret) : "r" (port), "i" (ASI_PL)); + return ret; +} + +static __inline__ unsigned int inw(unsigned long port) +{ + unsigned char ret; + __asm__ __volatile__("lduha [%1] %2, %0" : "=r" (ret) : "r" (port), "i" (ASI_PL)); + return ret; +} + +static __inline__ unsigned int inl(unsigned long port) +{ + unsigned char ret; + __asm__ __volatile__("lda [%1] %2, %0" : "=r" (ret) : "r" (port), "i" (ASI_PL)); + return ret; +} + +#define intr_disable() +#define intr_enable() + +#endif diff --git a/src/video_out/libdha/sysdep/AsmMacros_x86.h b/src/video_out/libdha/sysdep/AsmMacros_x86.h new file mode 100644 index 000000000..c10f24f2d --- /dev/null +++ b/src/video_out/libdha/sysdep/AsmMacros_x86.h @@ -0,0 +1,162 @@ +/* + This file is based on: + $XFree86: xc/programs/Xserver/hw/xfree86/drivers/chips/util/AsmMacros.h,v 1.1 2001/11/16 21:13:34 tsi Exp $ + Modified for readability by Nick Kurshev +*/ + +#ifndef __ASM_MACROS_X86_H +#define __ASM_MACROS_X86_H + +#if defined (WINNT) +#error This stuff is not ported on your system +#else + +#include "config.h" + +#ifdef CONFIG_DHAHELPER +#include +#include "../kernelhelper/dhahelper.h" + +extern int dhahelper_fd; +extern int dhahelper_initialized; +#endif + +static __inline__ void outb(short port,char val) +{ +#ifdef CONFIG_DHAHELPER + if (dhahelper_initialized == 1) + { + dhahelper_port_t _port; + + _port.operation = PORT_OP_WRITE; + _port.addr = port; + _port.size = 1; + _port.value = val; + if (ioctl(dhahelper_fd, DHAHELPER_PORT, &_port) == 0) + return; + } + else +#endif + __asm__ __volatile__("outb %0,%1" : :"a" (val), "d" (port)); + return; +} + +static __inline__ void outw(short port,short val) +{ +#ifdef CONFIG_DHAHELPER + if (dhahelper_initialized == 1) + { + dhahelper_port_t _port; + + _port.operation = PORT_OP_WRITE; + _port.addr = port; + _port.size = 2; + _port.value = val; + if (ioctl(dhahelper_fd, DHAHELPER_PORT, &_port) == 0) + return; + } + else +#endif + __asm__ __volatile__("outw %0,%1" : :"a" (val), "d" (port)); + return; +} + +static __inline__ void outl(short port,unsigned int val) +{ +#ifdef CONFIG_DHAHELPER + if (dhahelper_initialized == 1) + { + dhahelper_port_t _port; + + _port.operation = PORT_OP_WRITE; + _port.addr = port; + _port.size = 4; + _port.value = val; + if (ioctl(dhahelper_fd, DHAHELPER_PORT, &_port) == 0) + return; + } + else +#endif + __asm__ __volatile__("outl %0,%1" : :"a" (val), "d" (port)); + return; +} + +static __inline__ unsigned int inb(short port) +{ + unsigned char ret; +#ifdef CONFIG_DHAHELPER + if (dhahelper_initialized == 1) + { + dhahelper_port_t _port; + + _port.operation = PORT_OP_READ; + _port.addr = port; + _port.size = 1; + if (ioctl(dhahelper_fd, DHAHELPER_PORT, &_port) == 0) + return _port.value; + } + else +#endif + __asm__ __volatile__("inb %1,%0" : + "=a" (ret) : + "d" (port)); + return ret; +} + +static __inline__ unsigned int inw(short port) +{ + unsigned short ret; +#ifdef CONFIG_DHAHELPER + if (dhahelper_initialized == 1) + { + dhahelper_port_t _port; + + _port.operation = PORT_OP_READ; + _port.addr = port; + _port.size = 2; + if (ioctl(dhahelper_fd, DHAHELPER_PORT, &_port) == 0) + return _port.value; + } + else +#endif + __asm__ __volatile__("inw %1,%0" : + "=a" (ret) : + "d" (port)); + return ret; +} + +static __inline__ unsigned int inl(short port) +{ + unsigned int ret; +#ifdef CONFIG_DHAHELPER + if (dhahelper_initialized == 1) + { + dhahelper_port_t _port; + + _port.operation = PORT_OP_READ; + _port.addr = port; + _port.size = 4; + if (ioctl(dhahelper_fd, DHAHELPER_PORT, &_port) == 0) + return _port.value; + } + else +#endif + __asm__ __volatile__("inl %1,%0" : + "=a" (ret) : + "d" (port)); + return ret; +} + +static __inline__ void intr_disable() +{ + __asm__ __volatile__("cli"); +} + +static __inline__ void intr_enable() +{ + __asm__ __volatile__("sti"); +} + +#endif + +#endif diff --git a/src/video_out/libdha/sysdep/Makefile.am b/src/video_out/libdha/sysdep/Makefile.am new file mode 100644 index 000000000..70fc43949 --- /dev/null +++ b/src/video_out/libdha/sysdep/Makefile.am @@ -0,0 +1,18 @@ +EXTRA_DIST = libdha_os2.c pci_arm32.c pci_isc.c pci_netbsd.c pci_sco.c pci_x86.c \ + libdha_win32.c pci_bsdi.c pci_linux.c pci_openbsd.c pci_sparc.c pci_386bsd.c \ + pci_freebsd.c pci_lynx.c pci_os2.c pci_svr4.c pci_alpha.c pci_ia64.c pci_mach386.c \ + pci_powerpc.c pci_win32.c + +noinst_HEADERS = AsmMacros_alpha.h AsmMacros_ia64.h AsmMacros_sparc.h AsmMacros_arm32.h \ + AsmMacros_powerpc.h AsmMacros_x86.h + +debug: +install-debug: + +mostlyclean-generic: + -rm -f *~ \#* .*~ .\#* + +maintainer-clean-generic: + -@echo "This command is intended for maintainers to use;" + -@echo "it deletes files that may require special tools to rebuild." + -rm -f Makefile.in diff --git a/src/video_out/libdha/sysdep/libdha_os2.c b/src/video_out/libdha/sysdep/libdha_os2.c new file mode 100644 index 000000000..041f6be71 --- /dev/null +++ b/src/video_out/libdha/sysdep/libdha_os2.c @@ -0,0 +1,161 @@ +/* $XFree86: xc/programs/Xserver/hw/xfree86/os-support/os2/os2_video.c,v 3.14 2000/10/28 01:42:28 mvojkovi Exp $ */ +/* Modified for libdha by Nick Kurshev. */ +/* + * (c) Copyright 1994,1999 by Holger Veit + * + * Modified 1996 by Sebastien Marineau + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * HOLGER VEIT BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF + * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + * + * Except as contained in this notice, the name of Holger Veit shall not be + * used in advertising or otherwise to promote the sale, use or other dealings + * in this Software without prior written authorization from Holger Veit. + * + */ +/* $XConsortium: os2_video.c /main/8 1996/10/27 11:49:02 kaleb $ */ + +#define INCL_DOSFILEMGR +#include "os2.h" + +/***************************************************************************/ +/* Video Memory Mapping helper functions */ +/***************************************************************************/ + +/* This section uses the xf86sup.sys driver developed for xfree86. + * The driver allows mapping of physical memory + * You must install it with a line DEVICE=path\xf86sup.sys in config.sys. + */ + +static HFILE mapdev = -1; +static ULONG stored_virt_addr; +static char* mappath = "\\DEV\\PMAP$"; +static HFILE open_mmap() +{ + APIRET rc; + ULONG action; + + if (mapdev != -1) + return mapdev; + + rc = DosOpen((PSZ)mappath, (PHFILE)&mapdev, (PULONG)&action, + (ULONG)0, FILE_SYSTEM, FILE_OPEN, + OPEN_SHARE_DENYNONE|OPEN_FLAGS_NOINHERIT|OPEN_ACCESS_READONLY, + (ULONG)0); + if (rc!=0) + mapdev = -1; + return mapdev; +} + +static void close_mmap() +{ + if (mapdev != -1) + DosClose(mapdev); + mapdev = -1; +} + +/* this structure is used as a parameter packet for the direct access + * ioctl of pmap$ + */ + +/* Changed here for structure of driver PMAP$ */ + +typedef struct{ + ULONG addr; + ULONG size; +} DIOParPkt; + +/* This is the data packet for the mapping function */ + +typedef struct { + ULONG addr; + USHORT sel; +} DIODtaPkt; + +/***************************************************************************/ +/* Video Memory Mapping section */ +/***************************************************************************/ + +static long callcount = 0L; + +/* ARGSUSED */ +void * map_phys_mem(unsigned long base, unsigned long size) +{ + DIOParPkt par; + ULONG plen; + DIODtaPkt dta; + ULONG dlen; + static BOOL ErrRedir = FALSE; + APIRET rc; + + par.addr = (ULONG)base; + par.size = (ULONG)size; + plen = sizeof(par); + dlen = sizeof(dta); + + open_mmap(); + if (mapdev == -1) + { + perror("libdha: device xf86sup.sys is not installed"); + exit(1); + } + if ((rc=DosDevIOCtl(mapdev, (ULONG)0x76, (ULONG)0x44, + (PVOID)&par, (ULONG)plen, (PULONG)&plen, + (PVOID)&dta, (ULONG)dlen, (PULONG)&dlen)) == 0) { + if (dlen==sizeof(dta)) { + callcount++; + return (void *)dta.addr; + } + /*else fail*/ + } + return (void *)-1; +} + +/* ARGSUSED */ +void unmap_phys_mem(void * base, unsigned long size) +{ + DIOParPkt par; + ULONG plen,vmaddr; + +/* We need here the VIRTADDR for unmapping, not the physical address */ +/* This should be taken care of either here by keeping track of allocated */ +/* pointers, but this is also already done in the driver... Thus it would */ +/* be a waste to do this tracking twice. Can this be changed when the fn. */ +/* is called? This would require tracking this function in all servers, */ +/* and changing it appropriately to call this with the virtual adress */ +/* If the above mapping function is only called once, then we can store */ +/* the virtual adress and use it here.... */ + + par.addr = (ULONG)base; + par.size = 0xffffffff; /* This is the virtual address parameter. Set this to ignore */ + plen = sizeof(par); + + if (mapdev != -1) + { + DosDevIOCtl(mapdev, (ULONG)0x76, (ULONG)0x46, + (PVOID)&par, (ULONG)plen, (PULONG)&plen, + &vmaddr, sizeof(ULONG), &plen); + callcount--; + } +/* Now if more than one region has been allocated and we close the driver, + * the other pointers will immediately become invalid. We avoid closing + * driver for now, but this should be fixed for server exit + */ + + if(!callcount) close_mmap(); +} diff --git a/src/video_out/libdha/sysdep/libdha_win32.c b/src/video_out/libdha/sysdep/libdha_win32.c new file mode 100644 index 000000000..75c5dfb94 --- /dev/null +++ b/src/video_out/libdha/sysdep/libdha_win32.c @@ -0,0 +1,70 @@ +/* + MAPDEV.h - include file for VxD MAPDEV + Copyright (c) 1996 Vireo Software, Inc. + Modified for libdha by Nick Kurshev. +*/ + +#include + +/* + This is the request structure that applications use + to request services from the MAPDEV VxD. +*/ + +typedef struct _MapDevRequest +{ + DWORD mdr_ServiceID; /* supplied by caller */ + LPVOID mdr_PhysicalAddress; /* supplied by caller */ + DWORD mdr_SizeInBytes; /* supplied by caller */ + LPVOID mdr_LinearAddress; /* returned by VxD */ + WORD mdr_Selector; /* returned if 16-bit caller */ + WORD mdr_Status; /* MDR_xxxx code below */ +} MAPDEVREQUEST, *PMAPDEVREQUEST; + +#define MDR_SERVICE_MAP CTL_CODE(FILE_DEVICE_UNKNOWN, 1, METHOD_NEITHER, FILE_ANY_ACCESS) +#define MDR_SERVICE_UNMAP CTL_CODE(FILE_DEVICE_UNKNOWN, 2, METHOD_NEITHER, FILE_ANY_ACCESS) + +#define MDR_STATUS_SUCCESS 1 +#define MDR_STATUS_ERROR 0 +/*#include "winioctl.h"*/ +#define FILE_DEVICE_UNKNOWN 0x00000022 +#define METHOD_NEITHER 3 +#define FILE_ANY_ACCESS 0 +#define CTL_CODE( DeviceType, Function, Method, Access ) ( \ + ((DeviceType)<<16) | ((Access)<<14) | ((Function)<<2) | (Method) ) + +/* Memory Map a piece of Real Memory */ +void *map_phys_mem(unsigned base, unsigned size) { + + HANDLE hDevice ; + PVOID inBuf[1] ; /* buffer for struct pointer to VxD */ + DWORD RetInfo[2] ; /* buffer to receive data from VxD */ + DWORD cbBytesReturned ; /* count of bytes returned from VxD */ + MAPDEVREQUEST req ; /* map device request structure */ + DWORD *pNicstar, Status, Time ; int i ; char *endptr ; + const PCHAR VxDName = "\\\\.\\MAPDEV.VXD" ; + const PCHAR VxDNameAlreadyLoaded = "\\\\.\\MAPDEV" ; + + hDevice = CreateFile(VxDName, 0,0,0, + CREATE_NEW, FILE_FLAG_DELETE_ON_CLOSE, 0) ; + if (hDevice == INVALID_HANDLE_VALUE) + hDevice = CreateFile(VxDNameAlreadyLoaded, 0,0,0, + CREATE_NEW, FILE_FLAG_DELETE_ON_CLOSE, 0) ; + if (hDevice == INVALID_HANDLE_VALUE) { + fprintf(stderr, "Cannot open driver, error=%08lx\n", GetLastError()) ; + exit(1) ; } + + req.mdr_ServiceID = MDR_SERVICE_MAP ; + req.mdr_PhysicalAddress = (PVOID)base ; + req.mdr_SizeInBytes = size ; + inBuf[0] = &req ; + + if ( ! DeviceIoControl(hDevice, MDR_SERVICE_MAP, inBuf, sizeof(PVOID), + NULL, 0, &cbBytesReturned, NULL) ) { + fprintf(stderr, "Failed to map device\n") ; exit(1) ; } + + return (void*)req.mdr_LinearAddress ; +} + +void unmap_phys_mem(void *ptr, unsigned size) { } + diff --git a/src/video_out/libdha/sysdep/pci_386bsd.c b/src/video_out/libdha/sysdep/pci_386bsd.c new file mode 100644 index 000000000..d00ecb078 --- /dev/null +++ b/src/video_out/libdha/sysdep/pci_386bsd.c @@ -0,0 +1,38 @@ +/* + This file is based on: + $XFree86: xc/programs/Xserver/hw/xfree86/etc/scanpci.c,v 3.34.2.17 1998/11/10 11:55:40 dawes Exp $ + Modified for readability by Nick Kurshev +*/ +#include +#include +#include +#ifndef GCCUSESGAS +#define GCCUSESGAS +#endif + +static int io_fd; + +static __inline__ int enable_os_io(void) +{ + io_fd = -1 ; + if ((io_fd = open("/dev/console", O_RDWR, 0)) < 0) { + perror("/dev/console"); + return(errno); + } + if (ioctl(io_fd, KDENABIO, 0) < 0) { + perror("ioctl(KDENABIO)"); + return(errno); + } + return(0); +} + +static __inline__ int disable_os_io(void) +{ + if (ioctl(io_fd, KDDISABIO, 0) < 0) { + perror("ioctl(KDDISABIO)"); + close(io_fd); + return(errno); + } + close(io_fd); + return(0); +} diff --git a/src/video_out/libdha/sysdep/pci_alpha.c b/src/video_out/libdha/sysdep/pci_alpha.c new file mode 100644 index 000000000..e968b3e12 --- /dev/null +++ b/src/video_out/libdha/sysdep/pci_alpha.c @@ -0,0 +1,29 @@ +/* + This file is based on: + $XFree86: xc/programs/Xserver/hw/xfree86/etc/scanpci.c,v 3.34.2.17 1998/11/10 11:55:40 dawes Exp $ + Modified for readability by Nick Kurshev +*/ + +static int pci_config_type( void ) { return 1; } + +static int pci_get_vendor( + unsigned char bus, + unsigned char dev, + int func) +{ + unsigned long retval; + pciconfig_read(bus, dev<<3, PCI_ID_REG, 4, &retval); + return retval; +} + +static long pci_config_read_long( + unsigned char bus, + unsigned char dev, + int func, + unsigned cmd) +{ + unsigned long retval; + pciconfig_read(bus, dev<<3, cmd, 4, &retval); + return retval; +} + diff --git a/src/video_out/libdha/sysdep/pci_arm32.c b/src/video_out/libdha/sysdep/pci_arm32.c new file mode 100644 index 000000000..a631887da --- /dev/null +++ b/src/video_out/libdha/sysdep/pci_arm32.c @@ -0,0 +1,60 @@ +/* + This file is based on: + $XFree86: xc/programs/Xserver/hw/xfree86/etc/scanpci.c,v 3.34.2.17 1998/11/10 11:55:40 dawes Exp $ + Modified for readability by Nick Kurshev +*/ + +static int pci_config_type( void ) +{ + unsigned long tmplong1, tmplong2; + unsigned char tmp1, tmp2; + int retval; + retval = 0; + + outb(PCI_MODE2_ENABLE_REG, 0x00); + outb(PCI_MODE2_FORWARD_REG, 0x00); + tmp1 = inb(PCI_MODE2_ENABLE_REG); + tmp2 = inb(PCI_MODE2_FORWARD_REG); + if ((tmp1 == 0x00) && (tmp2 == 0x00)) { + retval = 2; + /*printf("PCI says configuration type 2\n");*/ + } else { + tmplong1 = inl(PCI_MODE1_ADDRESS_REG); + outl(PCI_MODE1_ADDRESS_REG, PCI_EN); + tmplong2 = inl(PCI_MODE1_ADDRESS_REG); + outl(PCI_MODE1_ADDRESS_REG, tmplong1); + if (tmplong2 == PCI_EN) { + retval = 1; + /*printf("PCI says configuration type 1\n");*/ + } else { + /*printf("No PCI !\n");*/ + disable_os_io(); + /*exit(1);*/ + retval = 0xFFFF; + } + } + return retval; +} + +static int pci_get_vendor( + unsigned char bus, + unsigned char dev, + int func) +{ + unsigned long config_cmd; + config_cmd = PCI_EN | (bus<<16) | (dev<<11) | (func<<8); + outl(PCI_MODE1_ADDRESS_REG, config_cmd); + return inl(PCI_MODE1_DATA_REG); +} + +static long pci_config_read_long( + unsigned char bus, + unsigned char dev, + int func, + unsigned cmd) +{ + unsigned long config_cmd; + config_cmd = PCI_EN | (bus<<16) | (dev<<11) | (func<<8); + outl(PCI_MODE1_ADDRESS_REG, config_cmd | cmd); + return inl(PCI_MODE1_DATA_REG); +} diff --git a/src/video_out/libdha/sysdep/pci_bsdi.c b/src/video_out/libdha/sysdep/pci_bsdi.c new file mode 100644 index 000000000..b6b142054 --- /dev/null +++ b/src/video_out/libdha/sysdep/pci_bsdi.c @@ -0,0 +1,39 @@ +/* + This file is based on: + $XFree86: xc/programs/Xserver/hw/xfree86/etc/scanpci.c,v 3.34.2.17 1998/11/10 11:55:40 dawes Exp $ + Modified for readability by Nick Kurshev +*/ +#include +#include +#include +#include +#ifndef GCCUSESGAS +#define GCCUSESGAS +#endif + +static int io_fd; + +static __inline__ int enable_os_io(void) +{ + io_fd = -1 ; + if ((io_fd = open("/dev/console", O_RDWR, 0)) < 0) { + perror("/dev/console"); + return(errno); + } + if (ioctl(io_fd, PCCONENABIOPL, 0) < 0) { + perror("ioctl(PCCONENABIOPL)"); + return(errno); + } + return(0); +} + +static __inline__ int disable_os_io(void) +{ + if (ioctl(io_fd, PCCONDISABIOPL, 0) < 0) { + perror("ioctl(PCCONDISABIOPL)"); + close(io_fd); + return(errno); + } + close(io_fd); + return(0); +} diff --git a/src/video_out/libdha/sysdep/pci_freebsd.c b/src/video_out/libdha/sysdep/pci_freebsd.c new file mode 100644 index 000000000..9ad4b15f2 --- /dev/null +++ b/src/video_out/libdha/sysdep/pci_freebsd.c @@ -0,0 +1,41 @@ +/* + This file is based on: + $XFree86: xc/programs/Xserver/hw/xfree86/etc/scanpci.c,v 3.34.2.17 1998/11/10 11:55:40 dawes Exp $ + Modified for readability by Nick Kurshev +*/ +#include +#include +/* machine/console.h seems to be outdated by recent FreeBSD * + * however pcvt_ioctl.h seems to exist for very long time */ +/* #include */ +#include +#ifndef GCCUSESGAS +#define GCCUSESGAS +#endif + +static int io_fd; + +static __inline__ int enable_os_io(void) +{ + io_fd = -1 ; + if ((io_fd = open("/dev/console", O_RDWR, 0)) < 0) { + perror("/dev/console"); + return(errno); + } + if (ioctl(io_fd, KDENABIO, 0) < 0) { + perror("ioctl(KDENABIO)"); + return(errno); + } + return(0); +} + +static __inline__ int disable_os_io(void) +{ + if (ioctl(io_fd, KDDISABIO, 0) < 0) { + perror("ioctl(KDDISABIO)"); + close(io_fd); + return(errno); + } + close(io_fd); + return(0); +} diff --git a/src/video_out/libdha/sysdep/pci_ia64.c b/src/video_out/libdha/sysdep/pci_ia64.c new file mode 100644 index 000000000..a631887da --- /dev/null +++ b/src/video_out/libdha/sysdep/pci_ia64.c @@ -0,0 +1,60 @@ +/* + This file is based on: + $XFree86: xc/programs/Xserver/hw/xfree86/etc/scanpci.c,v 3.34.2.17 1998/11/10 11:55:40 dawes Exp $ + Modified for readability by Nick Kurshev +*/ + +static int pci_config_type( void ) +{ + unsigned long tmplong1, tmplong2; + unsigned char tmp1, tmp2; + int retval; + retval = 0; + + outb(PCI_MODE2_ENABLE_REG, 0x00); + outb(PCI_MODE2_FORWARD_REG, 0x00); + tmp1 = inb(PCI_MODE2_ENABLE_REG); + tmp2 = inb(PCI_MODE2_FORWARD_REG); + if ((tmp1 == 0x00) && (tmp2 == 0x00)) { + retval = 2; + /*printf("PCI says configuration type 2\n");*/ + } else { + tmplong1 = inl(PCI_MODE1_ADDRESS_REG); + outl(PCI_MODE1_ADDRESS_REG, PCI_EN); + tmplong2 = inl(PCI_MODE1_ADDRESS_REG); + outl(PCI_MODE1_ADDRESS_REG, tmplong1); + if (tmplong2 == PCI_EN) { + retval = 1; + /*printf("PCI says configuration type 1\n");*/ + } else { + /*printf("No PCI !\n");*/ + disable_os_io(); + /*exit(1);*/ + retval = 0xFFFF; + } + } + return retval; +} + +static int pci_get_vendor( + unsigned char bus, + unsigned char dev, + int func) +{ + unsigned long config_cmd; + config_cmd = PCI_EN | (bus<<16) | (dev<<11) | (func<<8); + outl(PCI_MODE1_ADDRESS_REG, config_cmd); + return inl(PCI_MODE1_DATA_REG); +} + +static long pci_config_read_long( + unsigned char bus, + unsigned char dev, + int func, + unsigned cmd) +{ + unsigned long config_cmd; + config_cmd = PCI_EN | (bus<<16) | (dev<<11) | (func<<8); + outl(PCI_MODE1_ADDRESS_REG, config_cmd | cmd); + return inl(PCI_MODE1_DATA_REG); +} diff --git a/src/video_out/libdha/sysdep/pci_isc.c b/src/video_out/libdha/sysdep/pci_isc.c new file mode 100644 index 000000000..5b5a59182 --- /dev/null +++ b/src/video_out/libdha/sysdep/pci_isc.c @@ -0,0 +1,32 @@ +/* + This file is based on: + $XFree86: xc/programs/Xserver/hw/xfree86/etc/scanpci.c,v 3.34.2.17 1998/11/10 11:55:40 dawes Exp $ + Modified for readability by Nick Kurshev +*/ +#include +#include +#include +#include +#include +#include +#include + +static __inline__ int enable_os_io(void) +{ +#if defined(SI86IOPL) + sysi86(SI86IOPL, 3); +#else + sysi86(SI86V86, V86SC_IOPL, PS_IOPL); +#endif + return(0); +} + +static __inline__ int disable_os_io(void) +{ +#if defined(SI86IOPL) + sysi86(SI86IOPL, 0); +#else + sysi86(SI86V86, V86SC_IOPL, 0); +#endif + return(0); +} diff --git a/src/video_out/libdha/sysdep/pci_linux.c b/src/video_out/libdha/sysdep/pci_linux.c new file mode 100644 index 000000000..9382ebf2d --- /dev/null +++ b/src/video_out/libdha/sysdep/pci_linux.c @@ -0,0 +1,48 @@ +/* + This file is based on: + $XFree86: xc/programs/Xserver/hw/xfree86/etc/scanpci.c,v 3.34.2.17 1998/11/10 11:55:40 dawes Exp $ + Modified for readability by Nick Kurshev +*/ +#include +#ifdef __i386__ +#include +#else +#include +#endif + +#include "config.h" + +#ifdef CONFIG_DHAHELPER +#include +int dhahelper_initialized = 0; +int dhahelper_fd = 0; +#endif + +static __inline__ int enable_os_io(void) +{ +#ifdef CONFIG_DHAHELPER + dhahelper_fd = open("/dev/dhahelper", O_RDWR); + if (dhahelper_fd > 0) + { + dhahelper_initialized = 1; + return(0); + } + dhahelper_initialized = -1; +#endif + + if (iopl(3) != 0) + return(errno); + return(0); +} + +static __inline__ int disable_os_io(void) +{ +#ifdef CONFIG_DHAHELPER + if (dhahelper_initialized == 1) + close(dhahelper_fd); + else +#endif + if (iopl(0) != 0) + return(errno); + return(0); +} diff --git a/src/video_out/libdha/sysdep/pci_lynx.c b/src/video_out/libdha/sysdep/pci_lynx.c new file mode 100644 index 000000000..b698f6308 --- /dev/null +++ b/src/video_out/libdha/sysdep/pci_lynx.c @@ -0,0 +1,93 @@ +/* + This file is based on: + $XFree86: xc/programs/Xserver/hw/xfree86/etc/scanpci.c,v 3.34.2.17 1998/11/10 11:55:40 dawes Exp $ + Modified for readability by Nick Kurshev +*/ + +#if defined(Lynx_22) +#ifndef GCCUSESGAS +#define GCCUSESGAS +#endif + +/* let's mimick the Linux Alpha stuff for LynxOS so we don't have + * to change too much code + */ +#include + +static unsigned char *pciConfBase; + +static __inline__ void enable_os_io(void) +{ + pciConfBase = (unsigned char *) smem_create("PCI-CONF", + (char *)0x80800000, 64*1024, SM_READ|SM_WRITE); + if (pciConfBase == (void *) -1) + exit(1); +} + +static __inline__ void disable_os_io(void) +{ + smem_create(NULL, (char *) pciConfBase, 0, SM_DETACH); + smem_remove("PCI-CONF"); + pciConfBase = NULL; +} + +#include + +static unsigned char *pciConfBase; + +static __inline__ unsigned long +static swapl(unsigned long val) +{ + unsigned char *p = (unsigned char *)&val; + return ((p[3] << 24) | (p[2] << 16) | (p[1] << 8) | (p[0] << 0)); +} + + +#define BUS(tag) (((tag)>>16)&0xff) +#define DFN(tag) (((tag)>>8)&0xff) + +#define PCIBIOS_DEVICE_NOT_FOUND 0x86 +#define PCIBIOS_SUCCESSFUL 0x00 + +static int pciconfig_read( + unsigned char bus, + unsigned char dev, + unsigned char offset, + int len, /* unused, alway 4 */ + unsigned long *val) +{ + unsigned long _val; + unsigned long *ptr; + + dev >>= 3; + if (bus || dev >= 16) { + *val = 0xFFFFFFFF; + return PCIBIOS_DEVICE_NOT_FOUND; + } else { + ptr = (unsigned long *)(pciConfBase + ((1<>= 3; + _val = swapl(val); + if (bus || dev >= 16) { + return PCIBIOS_DEVICE_NOT_FOUND; + } else { + ptr = (unsigned long *)(pciConfBase + ((1< + +static int io_fd; + +static __inline__ int enable_os_io(void) +{ + io_fd = -1 ; + if ((io_fd = open("/dev/iopl", O_RDWR, 0)) < 0) { + perror("/dev/iopl"); + return(errno); + } + return(0); +} + +static __inline__ int disable_os_io(void) +{ + close(io_fd); + return(0); +} diff --git a/src/video_out/libdha/sysdep/pci_netbsd.c b/src/video_out/libdha/sysdep/pci_netbsd.c new file mode 100644 index 000000000..793944beb --- /dev/null +++ b/src/video_out/libdha/sysdep/pci_netbsd.c @@ -0,0 +1,44 @@ +/* + This file is based on: + $XFree86: xc/programs/Xserver/hw/xfree86/etc/scanpci.c,v 3.34.2.17 1998/11/10 11:55:40 dawes Exp $ + Modified for readability by Nick Kurshev +*/ +#include +#include +#include +#include +#ifndef GCCUSESGAS +#define GCCUSESGAS +#endif + +static int io_fd; + +static __inline__ int enable_os_io(void) +{ + io_fd = -1 ; +#if !defined(USE_I386_IOPL) + if ((io_fd = open("/dev/io", O_RDWR, 0)) < 0) { + perror("/dev/io"); + return(errno); + } +#else + if (i386_iopl(1) < 0) { + perror("i386_iopl"); + return(errno); + } +#endif /* USE_I386_IOPL */ + return(0); +} + +static __inline__ int disable_os_io(void) +{ +#if !defined(USE_I386_IOPL) + close(io_fd); +#else + if (i386_iopl(0) < 0) { + perror("i386_iopl"); + return(errno); + } +#endif /* NetBSD1_1 */ + return(0); +} diff --git a/src/video_out/libdha/sysdep/pci_openbsd.c b/src/video_out/libdha/sysdep/pci_openbsd.c new file mode 100644 index 000000000..13504db81 --- /dev/null +++ b/src/video_out/libdha/sysdep/pci_openbsd.c @@ -0,0 +1,24 @@ +/* + This file is based on: + $XFree86: xc/programs/Xserver/hw/xfree86/etc/scanpci.c,v 3.34.2.17 1998/11/10 11:55:40 dawes Exp $ + Modified for readability by Nick Kurshev +*/ + +#include +#include +#include + +static __inline__ int enable_os_io(void) +{ + if (i386_iopl(1) < 0) { + perror("i386_iopl"); + return(errno); + } + return(0); +} + +static __inline__ int disable_os_io(void) +{ + /* Nothing to do */ + return(0); +} diff --git a/src/video_out/libdha/sysdep/pci_os2.c b/src/video_out/libdha/sysdep/pci_os2.c new file mode 100644 index 000000000..ddfc0c0ea --- /dev/null +++ b/src/video_out/libdha/sysdep/pci_os2.c @@ -0,0 +1,55 @@ +/* + This file is based on: + $XFree86: xc/programs/Xserver/hw/xfree86/etc/scanpci.c,v 3.34.2.17 1998/11/10 11:55:40 dawes Exp $ + Modified for readability by Nick Kurshev +*/ +#define INCL_DOSFILEMGR +#include + +static USHORT callgate[3] = {0,0,0}; + +static __inline__ int enable_os_io(void) +{ + HFILE hfd; + ULONG dlen,action; + APIRET rc; + static char *ioDrvPath = "/dev/fastio$"; + + if (DosOpen((PSZ)ioDrvPath, (PHFILE)&hfd, (PULONG)&action, + (ULONG)0, FILE_SYSTEM, FILE_OPEN, + OPEN_SHARE_DENYNONE|OPEN_FLAGS_NOINHERIT|OPEN_ACCESS_READONLY, + (ULONG)0) != 0) { + fprintf(stderr,"Error opening fastio$ driver...\n"); + fprintf(stderr,"Please install xf86sup.sys in config.sys!\n"); + return(42); + } + callgate[0] = callgate[1] = 0; + +/* Get callgate from driver for fast io to ports and other stuff */ + + rc = DosDevIOCtl(hfd, (ULONG)0x76, (ULONG)0x64, + NULL, 0, NULL, + (ULONG*)&callgate[2], sizeof(USHORT), &dlen); + if (rc) { + fprintf(stderr,"xf86-OS/2: EnableIOPorts failed, rc=%d, dlen=%d; emergency exit\n", + rc,dlen); + DosClose(hfd); + return(42); + } + +/* Calling callgate with function 13 sets IOPL for the program */ + + asm volatile ("movl $13,%%ebx;.byte 0xff,0x1d;.long _callgate" + : /*no outputs */ + : /*no inputs */ + : "eax","ebx","ecx","edx","cc"); + + DosClose(hfd); + return(0); +} + +static __inline__ int disable_os_io(void) +{ +/* Nothing to do */ + return(0); +} diff --git a/src/video_out/libdha/sysdep/pci_powerpc.c b/src/video_out/libdha/sysdep/pci_powerpc.c new file mode 100644 index 000000000..9239521ec --- /dev/null +++ b/src/video_out/libdha/sysdep/pci_powerpc.c @@ -0,0 +1,28 @@ +/* + This file is based on: + $XFree86: xc/programs/Xserver/hw/xfree86/etc/scanpci.c,v 3.34.2.17 1998/11/10 11:55:40 dawes Exp $ + Modified for readability by Nick Kurshev +*/ + +static int pci_config_type( void ) { return 1; } + +static int pci_get_vendor( + unsigned char bus, + unsigned char dev, + int func) +{ + int retval; + pciconfig_read(bus, dev<<3, PCI_ID_REG, 4, &retval); + return retval; +} + +static long pci_config_read_long( + unsigned char bus, + unsigned char dev, + int func, + unsigned cmd) +{ + long retval; + pciconfig_read(bus, dev<<3, cmd, 4, &retval); + return retval; +} diff --git a/src/video_out/libdha/sysdep/pci_sco.c b/src/video_out/libdha/sysdep/pci_sco.c new file mode 100644 index 000000000..9cb2282ad --- /dev/null +++ b/src/video_out/libdha/sysdep/pci_sco.c @@ -0,0 +1,33 @@ +/* + This file is based on: + $XFree86: xc/programs/Xserver/hw/xfree86/etc/scanpci.c,v 3.34.2.17 1998/11/10 11:55:40 dawes Exp $ + Modified for readability by Nick Kurshev +*/ +#include +#include +#include +#include +#include +#include +#include +#include + +static __inline__ int enable_os_io(void) +{ +#if defined(SI86IOPL) + sysi86(SI86IOPL, 3); +#else + sysi86(SI86V86, V86SC_IOPL, PS_IOPL); +#endif + return(0); +} + +static __inline__ int disable_os_io(void) +{ +#if defined(SI86IOPL) + sysi86(SI86IOPL, 0); +#else + sysi86(SI86V86, V86SC_IOPL, 0); +#endif + return(0); +} diff --git a/src/video_out/libdha/sysdep/pci_sparc.c b/src/video_out/libdha/sysdep/pci_sparc.c new file mode 100644 index 000000000..a631887da --- /dev/null +++ b/src/video_out/libdha/sysdep/pci_sparc.c @@ -0,0 +1,60 @@ +/* + This file is based on: + $XFree86: xc/programs/Xserver/hw/xfree86/etc/scanpci.c,v 3.34.2.17 1998/11/10 11:55:40 dawes Exp $ + Modified for readability by Nick Kurshev +*/ + +static int pci_config_type( void ) +{ + unsigned long tmplong1, tmplong2; + unsigned char tmp1, tmp2; + int retval; + retval = 0; + + outb(PCI_MODE2_ENABLE_REG, 0x00); + outb(PCI_MODE2_FORWARD_REG, 0x00); + tmp1 = inb(PCI_MODE2_ENABLE_REG); + tmp2 = inb(PCI_MODE2_FORWARD_REG); + if ((tmp1 == 0x00) && (tmp2 == 0x00)) { + retval = 2; + /*printf("PCI says configuration type 2\n");*/ + } else { + tmplong1 = inl(PCI_MODE1_ADDRESS_REG); + outl(PCI_MODE1_ADDRESS_REG, PCI_EN); + tmplong2 = inl(PCI_MODE1_ADDRESS_REG); + outl(PCI_MODE1_ADDRESS_REG, tmplong1); + if (tmplong2 == PCI_EN) { + retval = 1; + /*printf("PCI says configuration type 1\n");*/ + } else { + /*printf("No PCI !\n");*/ + disable_os_io(); + /*exit(1);*/ + retval = 0xFFFF; + } + } + return retval; +} + +static int pci_get_vendor( + unsigned char bus, + unsigned char dev, + int func) +{ + unsigned long config_cmd; + config_cmd = PCI_EN | (bus<<16) | (dev<<11) | (func<<8); + outl(PCI_MODE1_ADDRESS_REG, config_cmd); + return inl(PCI_MODE1_DATA_REG); +} + +static long pci_config_read_long( + unsigned char bus, + unsigned char dev, + int func, + unsigned cmd) +{ + unsigned long config_cmd; + config_cmd = PCI_EN | (bus<<16) | (dev<<11) | (func<<8); + outl(PCI_MODE1_ADDRESS_REG, config_cmd | cmd); + return inl(PCI_MODE1_DATA_REG); +} diff --git a/src/video_out/libdha/sysdep/pci_svr4.c b/src/video_out/libdha/sysdep/pci_svr4.c new file mode 100644 index 000000000..bcce5c901 --- /dev/null +++ b/src/video_out/libdha/sysdep/pci_svr4.c @@ -0,0 +1,42 @@ +/* + This file is based on: + $XFree86: xc/programs/Xserver/hw/xfree86/etc/scanpci.c,v 3.34.2.17 1998/11/10 11:55:40 dawes Exp $ + Modified for readability by Nick Kurshev +*/ +#include +#include +#include +#if defined(NCR) +#define __STDC +#include +#undef __STDC +#else +#include +#endif + +#if defined(sun) +# ifndef __EXTENSIONS__ +# define __EXTENSIONS__ +# endif +# include +#endif + +static __inline__ int enable_os_io(void) +{ +#if defined(SI86IOPL) + sysi86(SI86IOPL, 3); +#else + sysi86(SI86V86, V86SC_IOPL, PS_IOPL); +#endif + return(0); +} + +static __inline__ int disable_os_io(void) +{ +#if defined(SI86IOPL) + sysi86(SI86IOPL, 0); +#else + sysi86(SI86V86, V86SC_IOPL, 0); +#endif + return(0); +} diff --git a/src/video_out/libdha/sysdep/pci_win32.c b/src/video_out/libdha/sysdep/pci_win32.c new file mode 100644 index 000000000..1c88cb13e --- /dev/null +++ b/src/video_out/libdha/sysdep/pci_win32.c @@ -0,0 +1,18 @@ +/* + This file is based on: + $XFree86: xc/programs/Xserver/hw/xfree86/etc/scanpci.c,v 3.34.2.17 1998/11/10 11:55:40 dawes Exp $ + Modified for readability by Nick Kurshev +*/ +#include + +/* Nothing to do for Win9x. For WinNT I have no solution */ + +static __inline__ int enable_os_io(void) +{ + return(0); +} + +static __inline__ int disable_os_io(void) +{ + return(0); +} diff --git a/src/video_out/libdha/sysdep/pci_x86.c b/src/video_out/libdha/sysdep/pci_x86.c new file mode 100644 index 000000000..a631887da --- /dev/null +++ b/src/video_out/libdha/sysdep/pci_x86.c @@ -0,0 +1,60 @@ +/* + This file is based on: + $XFree86: xc/programs/Xserver/hw/xfree86/etc/scanpci.c,v 3.34.2.17 1998/11/10 11:55:40 dawes Exp $ + Modified for readability by Nick Kurshev +*/ + +static int pci_config_type( void ) +{ + unsigned long tmplong1, tmplong2; + unsigned char tmp1, tmp2; + int retval; + retval = 0; + + outb(PCI_MODE2_ENABLE_REG, 0x00); + outb(PCI_MODE2_FORWARD_REG, 0x00); + tmp1 = inb(PCI_MODE2_ENABLE_REG); + tmp2 = inb(PCI_MODE2_FORWARD_REG); + if ((tmp1 == 0x00) && (tmp2 == 0x00)) { + retval = 2; + /*printf("PCI says configuration type 2\n");*/ + } else { + tmplong1 = inl(PCI_MODE1_ADDRESS_REG); + outl(PCI_MODE1_ADDRESS_REG, PCI_EN); + tmplong2 = inl(PCI_MODE1_ADDRESS_REG); + outl(PCI_MODE1_ADDRESS_REG, tmplong1); + if (tmplong2 == PCI_EN) { + retval = 1; + /*printf("PCI says configuration type 1\n");*/ + } else { + /*printf("No PCI !\n");*/ + disable_os_io(); + /*exit(1);*/ + retval = 0xFFFF; + } + } + return retval; +} + +static int pci_get_vendor( + unsigned char bus, + unsigned char dev, + int func) +{ + unsigned long config_cmd; + config_cmd = PCI_EN | (bus<<16) | (dev<<11) | (func<<8); + outl(PCI_MODE1_ADDRESS_REG, config_cmd); + return inl(PCI_MODE1_DATA_REG); +} + +static long pci_config_read_long( + unsigned char bus, + unsigned char dev, + int func, + unsigned cmd) +{ + unsigned long config_cmd; + config_cmd = PCI_EN | (bus<<16) | (dev<<11) | (func<<8); + outl(PCI_MODE1_ADDRESS_REG, config_cmd | cmd); + return inl(PCI_MODE1_DATA_REG); +} diff --git a/src/video_out/libdha/test.c b/src/video_out/libdha/test.c new file mode 100644 index 000000000..41aa466d1 --- /dev/null +++ b/src/video_out/libdha/test.c @@ -0,0 +1,27 @@ +#include "libdha.h" +#include +#include +#include + +int main( void ) +{ + pciinfo_t lst[MAX_PCI_DEVICES]; + unsigned i,num_pci; + int err; + err = pci_scan(lst,&num_pci); + if(err) + { + printf("Error occured during pci scan: %s\n",strerror(err)); + return EXIT_FAILURE; + } + else + { + printf(" Bus:card:func vend:dev base0 :base1 :base2 :baserom\n"); + for(i=0;i +#include +#include +#include +#include +#include "vidixlib.h" + +#include "video_out.h" +#include "xine_internal.h" +#include "alphablend.h" +#include "xineutils.h" + +#include +#include "video_out_x11.h" + + +#define LOG + + +#define LIBDIR "/usr/local/lib" +#define NUM_FRAMES 1 + +typedef struct vidix_driver_s vidix_driver_t; + +typedef struct vidix_frame_s { + vo_frame_t vo_frame; + int width, height, ratio_code, format; +} vidix_frame_t; + + +struct vidix_driver_s { + + vo_driver_t vo_driver; + + config_values_t *config; + + char *vidix_name; + VDL_HANDLE vidix_handler; + uint8_t *vidix_mem; + vidix_capability_t vidix_cap; + vidix_playback_t vidix_play; + vidix_fourcc_t vidix_fourcc; + vidix_yuv_t dstrides; + int vidix_started; + int next_frame; + + int yuv_format; + + pthread_mutex_t mutex; + + int user_ratio; + + uint32_t capabilities; + + /* X11 / Xv related stuff */ + Display *display; + int screen; + Drawable drawable; + + /* + * "delivered" size: + * frame dimension / aspect as delivered by the decoder + * used (among other things) to detect frame size changes + */ + int delivered_width; + int delivered_height; + int delivered_ratio_code; + int delivered_format; + + /* + * displayed part of delivered images, + * taking zoom into account + */ + + int displayed_xoffset; + int displayed_yoffset; + int displayed_width; + int displayed_height; + + /* + * "ideal" size : + * displayed width/height corrected by aspect ratio + */ + + int ideal_width, ideal_height; + double ratio_factor; /* output frame must fullfill: + height = width * ratio_factor */ + + /* + * "gui" size / offset: + * what gui told us about where to display the video + */ + + int gui_x, gui_y; + int gui_width, gui_height; + int gui_win_x, gui_win_y; + + /* + * "output" size: + * + * this is finally the ideal size "fitted" into the + * gui size while maintaining the aspect ratio + * + */ + + /* Window */ + int output_width; + int output_height; + int output_xoffset; + int output_yoffset; + + /* display anatomy */ + double display_ratio; /* given by visual parameter + from init function */ + + void *user_data; + + /* gui callback */ + + void (*frame_output_cb) (void *user_data, + int video_width, int video_height, + int *dest_x, int *dest_y, + int *dest_height, int *dest_width, + int *win_x, int *win_y); +}; + +static void free_framedata(vidix_frame_t* frame) +{ + if(frame->vo_frame.base[0]) { + free(frame->vo_frame.base[0]); + frame->vo_frame.base[0] = NULL; + } + + if(frame->vo_frame.base[1]) { + free(frame->vo_frame.base[1]); + frame->vo_frame.base[1] = NULL; + } + + if(frame->vo_frame.base[2]) { + free(frame->vo_frame.base[2]); + frame->vo_frame.base[2] = NULL; + } +} + + +static void write_frame_YUV422(vidix_driver_t* this, vidix_frame_t* frame) +{ + uint8_t* y = (uint8_t *)frame->vo_frame.base[0]; + uint8_t* cb = (uint8_t *)frame->vo_frame.base[1]; + uint8_t* cr = (uint8_t *)frame->vo_frame.base[2]; + uint8_t* crp; + uint8_t* cbp; + uint32_t* dst32 = (uint32_t *)(this->vidix_mem + + this->vidix_play.offsets[this->next_frame] + + this->vidix_play.offset.y); + int h,w; + + for(h = 0; h < (frame->height / 2); h++) { + cbp = cb; + crp = cr; + + for(w = 0; w < (frame->width / 2); w++) { + *dst32++ = (*y) + ((*cb)<<8) + ((*(y+1))<<16) + ((*cr)<<24); + y++; y++; cb++; cr++; + } + + dst32 += (this->dstrides.y - frame->width) / 2; + + for(w=0; w < (frame->width / 2); w++) { + *dst32++ = (*y) + ((*cbp)<<8) + ((*(y+1))<<16) + ((*crp)<<24); + y++; y++; cbp++; crp++; + } + + dst32 += (this->dstrides.y - frame->width) / 2; + } +} + +static void write_frame_YUV420P2(vidix_driver_t* this, vidix_frame_t* frame) +{ + uint8_t* y = (uint8_t *)frame->vo_frame.base[0]; + uint8_t* cb = (uint8_t *)frame->vo_frame.base[1]; + uint8_t* cr = (uint8_t *)frame->vo_frame.base[2]; + uint8_t* dst8 = (this->vidix_mem + this->vidix_play.offset.u + + this->vidix_play.offsets[this->next_frame] + + this->vidix_play.offset.u); + int h, w; + + register uint32_t* tmp32; + register uint8_t* rcr; + register uint8_t* rcb; + + rcr = cr; + rcb = cb; + + for(h = 0; h < (frame->height / 2); h++) { + tmp32 = (uint32_t *)dst8; + w = (frame->width / 8) * 2; + + while(w--) { + register uint32_t temp; + + temp = (*rcb) | (*rcr << 8); + rcr++; + rcb++; + temp |= (*rcb << 16) | (*rcr << 24); + rcr++; + rcb++; + *tmp32 = temp; + tmp32++; + } + + dst8 += this->dstrides.y; + } + + dst8 = (this->vidix_mem + + this->vidix_play.offsets[this->next_frame] + + this->vidix_play.offset.y); + for(h = 0; h < frame->height; h++) { + xine_fast_memcpy(dst8, y, frame->width); + y += frame->width; + dst8 += this->dstrides.y; + } +} + +static void write_frame_YUV420P3(vidix_driver_t* this, vidix_frame_t* frame) +{ + uint8_t* y = (uint8_t *)frame->vo_frame.base[0]; + uint8_t* cb = (uint8_t *)frame->vo_frame.base[1]; + uint8_t* cr = (uint8_t *)frame->vo_frame.base[2]; + uint8_t* dst8 = (this->vidix_mem + + this->vidix_play.offsets[this->next_frame] + + this->vidix_play.offset.y); + int h, half_width = (frame->width/2); + + for(h = 0; h < frame->height; h++) { + xine_fast_memcpy(dst8, y, frame->width); + y += frame->width; + dst8 += this->dstrides.y; + } + + dst8 = (this->vidix_mem + + this->vidix_play.offsets[this->next_frame]); + for(h = 0; h < (frame->height / 2); h++) { + xine_fast_memcpy((dst8 + this->vidix_play.offset.v), cb, half_width); + xine_fast_memcpy((dst8 + this->vidix_play.offset.u), cr, half_width); + + cb += half_width; + cr += half_width; + + dst8 += (this->dstrides.y / 2); + } +} + +static void write_frame_YUY2(vidix_driver_t* this, vidix_frame_t* frame) +{ + uint8_t* src8 = (uint8_t *)frame->vo_frame.base[0]; + uint8_t* dst8 = (uint8_t *)(this->vidix_mem + + this->vidix_play.offsets[this->next_frame] + + this->vidix_play.offset.y); + int h, double_width = (frame->width * 2); + + for(h = 0; h < frame->height; h++) { + xine_fast_memcpy(dst8, src8, double_width); + + dst8 += (this->dstrides.y * 2); + src8 += double_width; + } +} + +static void write_frame_sfb(vidix_driver_t* this, vidix_frame_t* frame) +{ + switch(frame->format) { + case IMGFMT_YUY2: + write_frame_YUY2(this, frame); +/* + else + printf("video_out_vidix: error. (YUY2 not supported by your graphic card)\n"); +*/ + break; + + case IMGFMT_YV12: + write_frame_YUV420P3(this, frame); +/* switch(this->yuv_format) { + case VIDEO_PALETTE_YUV422: + write_frame_YUV422(this, frame); + break; + case VIDEO_PALETTE_YUV420P2: + write_frame_YUV420P2(this, frame); + break; + case VIDEO_PALETTE_YUV420P3: + write_frame_YUV420P3(this, frame); + break; + default: + printf("video_out_vidix: error. (YV12 not supported by your graphic card)\n"); + } +*/ + break; + + default: + printf("video_out_vidix: error. (unknown frame format)\n"); + break; + } + + frame->vo_frame.displayed(&frame->vo_frame); +} + + +static uint32_t vidix_get_capabilities (vo_driver_t *this_gen) { + + vidix_driver_t *this = (vidix_driver_t *) this_gen; + + return this->capabilities; +} + +static void vidix_frame_field (vo_frame_t *vo_img, int which_field) { + /* not needed for vidix */ +} + +static void vidix_frame_dispose (vo_frame_t *vo_img) { + + vidix_frame_t *frame = (vidix_frame_t *) vo_img ; + + free_framedata(frame); + free (frame); +} + +static vo_frame_t *vidix_alloc_frame (vo_driver_t *this_gen) { + + vidix_frame_t *frame ; + + frame = (vidix_frame_t *) malloc (sizeof (vidix_frame_t)); + memset (frame, 0, sizeof(vidix_frame_t)); + + if (frame==NULL) { + printf ("vidix_alloc_frame: out of memory\n"); + } + + pthread_mutex_init (&frame->vo_frame.mutex, NULL); + + frame->vo_frame.base[0] = NULL; + frame->vo_frame.base[1] = NULL; + frame->vo_frame.base[2] = NULL; + + /* + * supply required functions + */ + + frame->vo_frame.copy = NULL; + frame->vo_frame.field = vidix_frame_field; + frame->vo_frame.dispose = vidix_frame_dispose; + + return (vo_frame_t *) frame; +} +/* + * make ideal width/height "fit" into the gui + */ + +static void vidix_compute_output_size (vidix_driver_t *this) { + + double x_factor, y_factor; + uint32_t apitch; + int err,i; + + if( !this->ideal_width || !this->ideal_height ) + return; + + x_factor = (double) this->gui_width / (double) this->ideal_width; + y_factor = (double) this->gui_height / (double) this->ideal_height; + + if ( x_factor < y_factor ) { + this->output_width = (double) this->gui_width; + this->output_height = (double) this->ideal_height * x_factor ; + } else { + this->output_width = (double) this->ideal_width * y_factor ; + this->output_height = (double) this->gui_height; + } + + this->output_xoffset = (this->gui_width - this->output_width) / 2 + this->gui_x; + this->output_yoffset = (this->gui_height - this->output_height) / 2 + this->gui_y; + +#ifdef LOG + printf ("video_out_vidix: frame source %d x %d => screen output %d x %d\n", + this->delivered_width, this->delivered_height, + this->output_width, this->output_height); +#endif + + if( this->vidix_started ) { + vdlPlaybackOff(this->vidix_handler); + } + + memset(&this->vidix_play,0,sizeof(vidix_playback_t)); + + this->vidix_play.fourcc = this->delivered_format; + this->vidix_play.capability = this->vidix_cap.flags; /* every ;) */ + this->vidix_play.blend_factor = 0; /* for now */ + this->vidix_play.src.x = this->vidix_play.src.y = 0; + this->vidix_play.src.w = this->delivered_width; + this->vidix_play.src.h = this->delivered_height; + this->vidix_play.dest.x = this->gui_win_x+this->output_xoffset; + this->vidix_play.dest.y = this->gui_win_y+this->output_yoffset; + this->vidix_play.dest.w = this->output_width; + this->vidix_play.dest.h = this->output_height; + this->vidix_play.num_frames=NUM_FRAMES; + this->vidix_play.src.pitch.y = this->vidix_play.src.pitch.u = this->vidix_play.src.pitch.v = 0; + + if((err=vdlConfigPlayback(this->vidix_handler,&this->vidix_play))!=0) + { + printf("video_out_vidix: Can't configure playback: %s\n",strerror(err)); + } + +#ifdef LOG + printf("video_out_vidix: dga_addr = %p frame_size = %d frames = %d\n", + this->vidix_play.dga_addr, this->vidix_play.frame_size, + this->vidix_play.num_frames ); + + printf("video_out_vidix: offsets[0..2] = %d %d %d\n", + this->vidix_play.offsets[0], this->vidix_play.offsets[1], + this->vidix_play.offsets[2] ); + + printf("video_out_vidix: offset.y/u/v = %d/%d/%d\n", + this->vidix_play.offset.y, this->vidix_play.offset.u, + this->vidix_play.offset.v ); + + printf("video_out_vidix: dest.pitch.y/u/v = %d/%d/%d\n", + this->vidix_play.dest.pitch.y, this->vidix_play.dest.pitch.u, + this->vidix_play.dest.pitch.v ); +#endif + + this->vidix_mem = this->vidix_play.dga_addr; + + this->next_frame = 0; + + /* clear every frame with correct address and frame_size */ + for (i = 0; i < this->vidix_play.num_frames; i++) + memset(this->vidix_mem + this->vidix_play.offsets[i], 0x80, + this->vidix_play.frame_size); + + apitch = this->vidix_play.dest.pitch.y-1; + this->dstrides.y = (this->delivered_width + apitch) & ~apitch; + apitch = this->vidix_play.dest.pitch.v-1; + this->dstrides.v = (this->delivered_width + apitch) & ~apitch; + apitch = this->vidix_play.dest.pitch.u-1; + this->dstrides.u = (this->delivered_width + apitch) & ~apitch; + + vdlPlaybackOn(this->vidix_handler); + this->vidix_started = 1; +} + +static void vidix_compute_ideal_size (vidix_driver_t *this) { + + double image_ratio, desired_ratio, corr_factor; + + this->displayed_xoffset = (this->delivered_width - this->displayed_width) / 2; + this->displayed_yoffset = (this->delivered_height - this->displayed_height) / 2; + + /* + * aspect ratio + */ + + image_ratio = (double) this->delivered_width / (double) this->delivered_height; + + switch (this->user_ratio) { + case ASPECT_AUTO: + switch (this->delivered_ratio_code) { + case XINE_ASPECT_RATIO_ANAMORPHIC: /* anamorphic */ + desired_ratio = 16.0 /9.0; + break; + case XINE_ASPECT_RATIO_211_1: /* 2.11:1 */ + desired_ratio = 2.11/1.0; + break; + case XINE_ASPECT_RATIO_SQUARE: /* square pels */ + case XINE_ASPECT_RATIO_DONT_TOUCH: /* probably non-mpeg stream => don't touch aspect ratio */ + desired_ratio = image_ratio; + break; + case 0: /* forbidden -> 4:3 */ + printf ("video_out_vidix: invalid ratio, using 4:3\n"); + default: + printf ("video_out_vidix: unknown aspect ratio (%d) in stream => using 4:3\n", + this->delivered_ratio_code); + case XINE_ASPECT_RATIO_4_3: /* 4:3 */ + desired_ratio = 4.0 / 3.0; + break; + } + break; + case ASPECT_ANAMORPHIC: + desired_ratio = 16.0 / 9.0; + break; + case ASPECT_DVB: + desired_ratio = 2.0 / 1.0; + break; + case ASPECT_SQUARE: + desired_ratio = image_ratio; + break; + case ASPECT_FULL: + default: + desired_ratio = 4.0 / 3.0; + } + + this->ratio_factor = this->display_ratio * desired_ratio; + + corr_factor = this->ratio_factor / image_ratio ; + + if (fabs(corr_factor - 1.0) < 0.005) { + this->ideal_width = this->delivered_width; + this->ideal_height = this->delivered_height; + + } else { + + if (corr_factor >= 1.0) { + this->ideal_width = this->delivered_width * corr_factor + 0.5; + this->ideal_height = this->delivered_height; + } else { + this->ideal_width = this->delivered_width; + this->ideal_height = this->delivered_height / corr_factor + 0.5; + } + } +} + + +static void vidix_update_frame_format (vo_driver_t *this_gen, + vo_frame_t *frame_gen, + uint32_t width, uint32_t height, + int ratio_code, int format, int flags) { + + vidix_frame_t *frame = (vidix_frame_t *) frame_gen; + uint32_t frame_size = width*height; + + if ((frame->width != width) + || (frame->height != height) + || (frame->format != format)) { + + /* + * (re-) allocate image + */ + + free_framedata(frame); + + frame->width = width; + frame->height = height; + frame->format = format; + + switch(format) { + case IMGFMT_YV12: + frame->vo_frame.base[0] = malloc(frame_size); + frame->vo_frame.base[1] = malloc(frame_size/4); + frame->vo_frame.base[2] = malloc(frame_size/4); + break; + case IMGFMT_YUY2: + frame->vo_frame.base[0] = malloc(frame_size*2); + frame->vo_frame.base[1] = NULL; + frame->vo_frame.base[2] = NULL; + break; + default: + printf("video_out_vidix: error. (unable to allocate framedata because of unknown frame format: %04x)\n", format); + } + + if((format == IMGFMT_YV12 && (frame->vo_frame.base[0] == NULL || frame->vo_frame.base[1] == NULL || frame->vo_frame.base[2] == NULL)) + || (format == IMGFMT_YUY2 && frame->vo_frame.base[0] == NULL)) { + printf("video_out_vidix: error. (framedata allocation failed: out of memory)\n"); + + free_framedata(frame); + } + } + + frame->ratio_code = ratio_code; +} + + +/* + * + */ +static void vidix_overlay_blend (vo_driver_t *this_gen, vo_frame_t *frame_gen, vo_overlay_t *overlay) { + + vidix_frame_t *frame = (vidix_frame_t *) frame_gen; + + if (overlay->rle) { + if( frame->format == IMGFMT_YV12 ) + blend_yuv( frame->vo_frame.base, overlay, frame->width, frame->height); + else + blend_yuy2( frame->vo_frame.base[0], overlay, frame->width, frame->height); + } +} + +static int vidix_redraw_needed (vo_driver_t *this_gen) { + vidix_driver_t *this = (vidix_driver_t *) this_gen; + int ret = 0; + + int gui_x, gui_y, gui_width, gui_height, gui_win_x, gui_win_y; + + this->frame_output_cb (this->user_data, + this->ideal_width, this->ideal_height, + &gui_x, &gui_y, &gui_width, &gui_height, + &gui_win_x, &gui_win_y ); + + if ( (gui_x != this->gui_x) || (gui_y != this->gui_y) + || (gui_width != this->gui_width) || (gui_height != this->gui_height) + || (gui_win_x != this->gui_win_x) || (gui_win_y != this->gui_win_y) ) { + + this->gui_x = gui_x; + this->gui_y = gui_y; + this->gui_width = gui_width; + this->gui_height = gui_height; + this->gui_win_x = gui_win_x; + this->gui_win_y = gui_win_y; + + vidix_compute_output_size (this); + + ret = 1; + } + + return ret; +} + + +static void vidix_display_frame (vo_driver_t *this_gen, vo_frame_t *frame_gen) { + + vidix_driver_t *this = (vidix_driver_t *) this_gen; + vidix_frame_t *frame = (vidix_frame_t *) frame_gen; + + pthread_mutex_lock(&this->mutex); + + if ( (frame->width != this->delivered_width) + || (frame->height != this->delivered_height) + || (frame->ratio_code != this->delivered_ratio_code) + || (frame->format != this->delivered_format ) ) { + printf("video_out_vidix: change frame format\n"); + + this->delivered_width = frame->width; + this->delivered_height = frame->height; + this->delivered_ratio_code = frame->ratio_code; + this->delivered_format = frame->format; + + vidix_compute_ideal_size( this ); + this->gui_width = 0; /* trigger re-calc of output size */ + } + + /* + * tell gui that we are about to display a frame, + * ask for offset and output size + */ + vidix_redraw_needed (this_gen); + + write_frame_sfb(this, frame); + if( this->vidix_play.num_frames > 1 ) { + vdlPlaybackFrameSelect(this->vidix_handler,this->next_frame); + this->next_frame=(this->next_frame+1)%this->vidix_play.num_frames; + } + + pthread_mutex_unlock(&this->mutex); +} + +static int vidix_get_property (vo_driver_t *this_gen, int property) { + + vidix_driver_t *this = (vidix_driver_t *) this_gen; + + if ( property == VO_PROP_ASPECT_RATIO) + return this->user_ratio ; + + return 0; +} + +static char *aspect_ratio_name(int a) +{ + switch (a) { + case ASPECT_AUTO: + return "auto"; + case ASPECT_SQUARE: + return "square"; + case ASPECT_FULL: + return "4:3"; + case ASPECT_ANAMORPHIC: + return "16:9"; + case ASPECT_DVB: + return "2:1"; + default: + return "unknown"; + } +} + +static int vidix_set_property (vo_driver_t *this_gen, + int property, int value) { + + vidix_driver_t *this = (vidix_driver_t *) this_gen; + + if ( property == VO_PROP_ASPECT_RATIO) { + if (value>=NUM_ASPECT_RATIOS) + value = ASPECT_AUTO; + this->user_ratio = value; + printf("video_out_vidix: aspect ratio changed to %s\n", + aspect_ratio_name(value)); + + vidix_compute_ideal_size (this); + } + + return value; +} + +static void vidix_get_property_min_max (vo_driver_t *this_gen, + int property, int *min, int *max) { + +/* vidix_driver_t *this = (vidix_driver_t *) this_gen; */ +} + +static void vidix_translate_gui2video(vidix_driver_t *this, + int x, int y, + int *vid_x, int *vid_y) +{ +} + +static int vidix_gui_data_exchange (vo_driver_t *this_gen, + int data_type, void *data) { + + int ret = 0; + vidix_driver_t *this = (vidix_driver_t *) this_gen; + + pthread_mutex_lock(&this->mutex); + + switch (data_type) { + + case GUI_DATA_EX_DRAWABLE_CHANGED: +#ifdef LOG + printf ("video_out_vidix: GUI_DATA_EX_DRAWABLE_CHANGED\n"); +#endif + + this->drawable = (Drawable) data; + break; + + case GUI_DATA_EX_EXPOSE_EVENT: +#ifdef LOG + printf ("video_out_vidix: GUI_DATA_EX_EXPOSE_EVENT\n"); +#endif + break; + + default: + ret = -1; + } + pthread_mutex_unlock(&this->mutex); + + return ret; +} + +static void vidix_exit (vo_driver_t *this_gen) { + + vidix_driver_t *this = (vidix_driver_t *) this_gen; + + if( this->vidix_started ) { + vdlPlaybackOff(this->vidix_handler); + } + vdlClose(this->vidix_handler); +} + +vo_driver_t *init_video_out_plugin (config_values_t *config, void *visual_gen) { + + vidix_driver_t *this; + x11_visual_t *visual = (x11_visual_t *) visual_gen; + XWindowAttributes window_attributes; + int err; + + this = malloc (sizeof (vidix_driver_t)); + + if (!this) { + printf ("video_out_vidix: malloc failed\n"); + return NULL; + } + memset (this, 0, sizeof(vidix_driver_t)); + + + if(vdlGetVersion() != VIDIX_VERSION) + { + printf("video_out_vidix: You have wrong version of VIDIX library\n"); + return NULL; + } + this->vidix_handler = vdlOpen((XINE_PLUGINDIR"/vidix/"), NULL, TYPE_OUTPUT, 0); + if(this->vidix_handler == NULL) + { + printf("video_out_vidix: Couldn't find working VIDIX driver\n"); + return NULL; + } + if((err=vdlGetCapability(this->vidix_handler,&this->vidix_cap)) != 0) + { + printf("video_out_vidix: Couldn't get capability: %s\n",strerror(err)); + return NULL; + } + printf("video_out_vidix: Using: %s by %s\n",this->vidix_cap.name,this->vidix_cap.author); + + this->display = visual->display; + this->screen = visual->screen; + this->display_ratio = visual->display_ratio; + this->drawable = visual->d; + this->frame_output_cb = visual->frame_output_cb; + this->user_data = visual->user_data; + + + this->config = config; + pthread_mutex_init (&this->mutex, NULL); + + this->output_xoffset = 0; + this->output_yoffset = 0; + this->output_width = 0; + this->output_height = 0; + this->capabilities = VO_CAP_YUY2 | VO_CAP_YV12; + + XGetWindowAttributes(this->display, this->drawable, &window_attributes); + this->gui_width = window_attributes.width; + this->gui_height = window_attributes.height; + + + + this->vo_driver.get_capabilities = vidix_get_capabilities; + this->vo_driver.alloc_frame = vidix_alloc_frame; + this->vo_driver.update_frame_format = vidix_update_frame_format; + this->vo_driver.overlay_blend = vidix_overlay_blend; + this->vo_driver.display_frame = vidix_display_frame; + this->vo_driver.get_property = vidix_get_property; + this->vo_driver.set_property = vidix_set_property; + this->vo_driver.get_property_min_max = vidix_get_property_min_max; + this->vo_driver.gui_data_exchange = vidix_gui_data_exchange; + this->vo_driver.exit = vidix_exit; + this->vo_driver.redraw_needed = vidix_redraw_needed; + + printf ("video_out_vidix: warning, xine's vidix driver is EXPERIMENTAL\n"); + return &this->vo_driver; +} + +static vo_info_t vo_info_vidix = { + 5, + "vidix", + "xine video output plugin using libvidix", + VISUAL_TYPE_X11, + 4 +}; + +vo_info_t *get_video_out_plugin_info() { + return &vo_info_vidix; +} + + diff --git a/src/video_out/vidix/Makefile.am b/src/video_out/vidix/Makefile.am new file mode 100644 index 000000000..c32751d1a --- /dev/null +++ b/src/video_out/vidix/Makefile.am @@ -0,0 +1,32 @@ +EXTRA_DIST = README vidix.txt + +SUBDIRS = drivers + +CFLAGS = @CFLAGS@ @STATIC@ + +if HAVE_VIDIX +vidix_lib = libvidix.la +endif + +noinst_LTLIBRARIES = $(vidix_lib) + +libvidix_la_SOURCES = vidixlib.c + +noinst_HEADERS = fourcc.h vidix.h vidixlib.h + +debug: + @$(MAKE) CFLAGS="$(DEBUG_CFLAGS) @STATIC@ -DXINE_COMPILE" + +install-debug: debug + @list='$(SUBDIRS)'; for subdir in $$list; do \ + (cd $$subdir && $(MAKE) $@) || exit;\ + done; + @$(MAKE) $(AM_MAKEFLAGS) install-exec-am install-data-am + +mostlyclean-generic: + -rm -f *~ \#* .*~ .\#* + +maintainer-clean-generic: + -@echo "This command is intended for maintainers to use;" + -@echo "it deletes files that may require special tools to rebuild." + -rm -f Makefile.in diff --git a/src/video_out/vidix/README b/src/video_out/vidix/README new file mode 100644 index 000000000..23bcaca30 --- /dev/null +++ b/src/video_out/vidix/README @@ -0,0 +1,7 @@ +VIDIX - Video Interface for *niX. +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +This library was designed and introduced as interface to userspace drivers +to provide DGA everywhere where it's possible (unline X11). +I hope that these drivers will be portable same as X11 (not only on *nix). + +For detail on how to develop new driver see vidix.txt diff --git a/src/video_out/vidix/drivers/Makefile.am b/src/video_out/vidix/drivers/Makefile.am new file mode 100644 index 000000000..d5346f850 --- /dev/null +++ b/src/video_out/vidix/drivers/Makefile.am @@ -0,0 +1,59 @@ + +LIBTOOL = $(SHELL) $(top_builddir)/libtool-nofpic + +libdir = $(XINE_PLUGINDIR)/vidix + +if HAVE_VIDIX +vidix_drivers = radeon_vid.la rage128_vid.la pm3_vid.la mach64_vid.la nvidia_vid.la \ + genfb_vid.la mga_vid.la mga_crtc2_vid.la +endif + +lib_LTLIBRARIES = $(vidix_drivers) + +radeon_vid_la_SOURCES = radeon_vid.c +radeon_vid_la_LIBADD = $(top_builddir)/src/video_out/libdha/libdha.la -lm +radeon_vid_la_LDFLAGS = -avoid-version -module + +rage128_vid_la_SOURCES = radeon_vid.c +rage128_vid_la_LIBADD = $(top_builddir)/src/video_out/libdha/libdha.la +rage128_vid_la_LDFLAGS = -avoid-version -module -DRAGE128 + +pm3_vid_la_SOURCES = pm3_vid.c +pm3_vid_la_LIBADD = $(top_builddir)/src/video_out/libdha/libdha.la +pm3_vid_la_LDFLAGS = -avoid-version -module + +mach64_vid_la_SOURCES = mach64_vid.c +mach64_vid_la_LIBADD = $(top_builddir)/src/video_out/libdha/libdha.la +mach64_vid_la_LDFLAGS = -avoid-version -module -DRAGE128 + +nvidia_vid_la_SOURCES = nvidia_vid.c +nvidia_vid_la_LIBADD = $(top_builddir)/src/video_out/libdha/libdha.la -lm +nvidia_vid_la_LDFLAGS = -avoid-version -module + +genfb_vid_la_SOURCES = genfb_vid.c +genfb_vid_la_LIBADD = $(top_builddir)/src/video_out/libdha/libdha.la -lm +genfb_vid_la_LDFLAGS = -avoid-version -module + +mga_vid_la_SOURCES = mga_vid.c +mga_vid_la_LIBADD = $(top_builddir)/src/video_out/libdha/libdha.la -lm +mga_vid_la_LDFLAGS = -avoid-version -module + +mga_crtc2_vid_la_SOURCES = mga_vid.c +mga_crtc2_vid_la_LIBADD = $(top_builddir)/src/video_out/libdha/libdha.la -lm +mga_crtc2_vid_la_LDFLAGS = -avoid-version -module -DCRTC2 + +noinst_HEADERS = mach64.h nvidia.h pm3_regs.h radeon.h + +debug: + @$(MAKE) CFLAGS="$(DEBUG_CFLAGS) -DXINE_COMPILE" + +install-debug: debug + @$(MAKE) $(AM_MAKEFLAGS) install-exec-am install-data-am + +mostlyclean-generic: + -rm -f *~ \#* .*~ .\#* + +maintainer-clean-generic: + -@echo "This command is intended for maintainers to use;" + -@echo "it deletes files that may require special tools to rebuild." + -rm -f Makefile.in diff --git a/src/video_out/vidix/drivers/genfb_vid.c b/src/video_out/vidix/drivers/genfb_vid.c new file mode 100644 index 000000000..40340842d --- /dev/null +++ b/src/video_out/vidix/drivers/genfb_vid.c @@ -0,0 +1,145 @@ +#include +#include +#include +#include +#include +#include +#include + +#include "../vidix.h" +#include "../fourcc.h" +#include "../../libdha/libdha.h" +#include "../../libdha/pci_ids.h" + +#define DEMO_DRIVER 1 + +static int fd; + +static void *mmio_base = 0; +static void *mem_base = 0; +static int32_t overlay_offset = 0; +static uint32_t ram_size = 0; + +static int probed = 0; + +/* VIDIX exports */ + +static vidix_capability_t genfb_cap = +{ + "General Framebuffer", + "alex", + TYPE_OUTPUT, + { 0, 0, 0, 0 }, + 2048, + 2048, + 4, + 4, + -1, + FLAG_UPSCALER|FLAG_DOWNSCALER, + -1, + -1, + { 0, 0, 0, 0 } +}; + +unsigned int vixGetVersion(void) +{ + return(VIDIX_VERSION); +} + +int vixProbe(int verbose,int force) +{ + int err = 0; +#ifdef DEMO_DRIVER + err = ENOSYS; +#endif + + printf("[genfb] probe\n"); + + fd = open("/dev/fb0", O_RDWR); + if (fd < 0) + { + printf("Error occured durint open: %s\n", strerror(errno)); + err = errno; + } + + probed = 1; + + return(err); +} + +int vixInit(void) +{ + printf("[genfb] init\n"); + + if (!probed) + { + printf("Driver was not probed but is being initialized\n"); + return(EINTR); + } + + return(0); +} + +void vixDestroy(void) +{ + printf("[genfb] destory\n"); + return; +} + +int vixGetCapability(vidix_capability_t *to) +{ + memcpy(to, &genfb_cap, sizeof(vidix_capability_t)); + return(0); +} + +int vixQueryFourcc(vidix_fourcc_t *to) +{ + printf("[genfb] query fourcc (%x)\n", to->fourcc); + + to->depth = VID_DEPTH_1BPP | VID_DEPTH_2BPP | + VID_DEPTH_4BPP | VID_DEPTH_8BPP | + VID_DEPTH_12BPP | VID_DEPTH_15BPP | + VID_DEPTH_16BPP | VID_DEPTH_24BPP | + VID_DEPTH_32BPP; + + to->flags = 0; + return(0); +} + +int vixConfigPlayback(vidix_playback_t *info) +{ + printf("[genfb] config playback\n"); + + info->num_frames = 2; + info->frame_size = info->src.w*info->src.h+(info->src.w*info->src.h)/2; + info->dest.pitch.y = 32; + info->dest.pitch.u = info->dest.pitch.v = 16; + info->offsets[0] = 0; + info->offsets[1] = info->frame_size; + info->offset.y = 0; + info->offset.v = ((info->src.w+31) & ~31) * info->src.h; + info->offset.u = info->offset.v+((info->src.w+31) & ~31) * info->src.h/4; + info->dga_addr = malloc(info->num_frames*info->frame_size); + printf("[genfb] frame_size: %d, dga_addr: %x\n", + info->frame_size, info->dga_addr); + + return(0); +} + +int vixPlaybackOn(void) +{ + printf("[genfb] playback on\n"); + return(0); +} + +int vixPlaybackOff(void) +{ + printf("[genfb] playback off\n"); + return(0); +} + +int vixPlaybackFrameSelect(unsigned int frame) +{ + printf("[genfb] frameselect: %d\n", frame); + return(0); +} diff --git a/src/video_out/vidix/drivers/mach64.h b/src/video_out/vidix/drivers/mach64.h new file mode 100644 index 000000000..085d40151 --- /dev/null +++ b/src/video_out/vidix/drivers/mach64.h @@ -0,0 +1,2481 @@ +/* + * mach64.h + * This software has been released under the terms of the GNU Public + * license. See http://www.gnu.org/copyleft/gpl.html for details. + * + * It's based on radeonfb, X11, GATOS sources +*/ + +#ifndef __MACH64_INCLUDED +#define __MACH64_INCLUDED 1 + +/* Note: this model of accessing to IO space is based on MMIO technology. +This means that this sources don't support ISA and VLB cards */ +#define BlockIOTag(val) (val) +#define IOPortTag(sparce,val) (val) + +/* MDA/[M]CGA/EGA/VGA I/O ports */ +#define GENVS 0x0102u /* Write (and Read on uC only) */ + +#define R_GENLPS 0x03b9u /* Read */ + +#define GENHP 0x03bfu + +#define ATTRX 0x03c0u +#define ATTRD 0x03c1u +#define GENS0 0x03c2u /* Read */ +#define GENMO 0x03c2u /* Write */ +#define GENENB 0x03c3u /* Read */ +#define SEQX 0x03c4u +#define SEQD 0x03c5u +#define VGA_DAC_MASK 0x03c6u +#define VGA_DAC_READ 0x03c7u +#define VGA_DAC_WRITE 0x03c8u +#define VGA_DAC_DATA 0x03c9u +#define R_GENFC 0x03cau /* Read */ +/* ? 0x03cbu */ +#define R_GENMO 0x03ccu /* Read */ +/* ? 0x03cdu */ +#define GRAX 0x03ceu +#define GRAD 0x03cfu + +#define GENB 0x03d9u + +#define GENLPS 0x03dcu /* Write */ +#define KCX 0x03ddu +#define KCD 0x03deu + +#define GENENA 0x46e8u /* Write */ + +/* I/O port base numbers */ +#define MonochromeIOBase 0x03b0u +#define ColourIOBase 0x03d0u + +/* Other MDA/[M]CGA/EGA/VGA I/O ports */ +/* ?(_IOBase) ((_IOBase) + 0x00u) */ /* CRTX synonym */ +/* ?(_IOBase) ((_IOBase) + 0x01u) */ /* CRTD synonym */ +/* ?(_IOBase) ((_IOBase) + 0x02u) */ /* CRTX synonym */ +/* ?(_IOBase) ((_IOBase) + 0x03u) */ /* CRTD synonym */ +#define CRTX(_IOBase) ((_IOBase) + 0x04u) +#define CRTD(_IOBase) ((_IOBase) + 0x05u) +/* ?(_IOBase) ((_IOBase) + 0x06u) */ +/* ?(_IOBase) ((_IOBase) + 0x07u) */ +#define GENMC(_IOBase) ((_IOBase) + 0x08u) +/* ?(_IOBase) ((_IOBase) + 0x09u) */ /* R_GENLPS/GENB */ +#define GENS1(_IOBase) ((_IOBase) + 0x0au) /* Read */ +#define GENFC(_IOBase) ((_IOBase) + 0x0au) /* Write */ +#define GENLPC(_IOBase) ((_IOBase) + 0x0bu) +/* ?(_IOBase) ((_IOBase) + 0x0cu) */ /* /GENLPS */ +/* ?(_IOBase) ((_IOBase) + 0x0du) */ /* /KCX */ +/* ?(_IOBase) ((_IOBase) + 0x0eu) */ /* /KCD */ +/* ?(_IOBase) ((_IOBase) + 0x0fu) */ /* GENHP/ */ + +/* 8514/A VESA approved register definitions */ +#define DISP_STAT 0x02e8u /* Read */ +#define SENSE 0x0001u /* Presumably belong here */ +#define VBLANK 0x0002u +#define HORTOG 0x0004u +#define H_TOTAL 0x02e8u /* Write */ +#define IBM_DAC_MASK 0x02eau +#define IBM_DAC_READ 0x02ebu +#define IBM_DAC_WRITE 0x02ecu +#define IBM_DAC_DATA 0x02edu +#define H_DISP 0x06e8u /* Write */ +#define H_SYNC_STRT 0x0ae8u /* Write */ +#define H_SYNC_WID 0x0ee8u /* Write */ +#define HSYNCPOL_POS 0x0000u +#define HSYNCPOL_NEG 0x0020u +#define H_POLARITY_POS HSYNCPOL_POS /* Sigh */ +#define H_POLARITY_NEG HSYNCPOL_NEG /* Sigh */ +#define V_TOTAL 0x12e8u /* Write */ +#define V_DISP 0x16e8u /* Write */ +#define V_SYNC_STRT 0x1ae8u /* Write */ +#define V_SYNC_WID 0x1ee8u /* Write */ +#define VSYNCPOL_POS 0x0000u +#define VSYNCPOL_NEG 0x0020u +#define V_POLARITY_POS VSYNCPOL_POS /* Sigh */ +#define V_POLARITY_NEG VSYNCPOL_NEG /* Sigh */ +#define DISP_CNTL 0x22e8u /* Write */ +#define ODDBNKENAB 0x0001u +#define MEMCFG_2 0x0000u +#define MEMCFG_4 0x0002u +#define MEMCFG_6 0x0004u +#define MEMCFG_8 0x0006u +#define DBLSCAN 0x0008u +#define INTERLACE 0x0010u +#define DISPEN_NC 0x0000u +#define DISPEN_ENAB 0x0020u +#define DISPEN_DISAB 0x0040u +#define R_H_TOTAL 0x26e8u /* Read */ +/* ? 0x2ae8u */ +/* ? 0x2ee8u */ +/* ? 0x32e8u */ +/* ? 0x36e8u */ +/* ? 0x3ae8u */ +/* ? 0x3ee8u */ +#define SUBSYS_STAT 0x42e8u /* Read */ +#define VBLNKFLG 0x0001u +#define PICKFLAG 0x0002u +#define INVALIDIO 0x0004u +#define GPIDLE 0x0008u +#define MONITORID_MASK 0x0070u +/* MONITORID_? 0x0000u */ +#define MONITORID_8507 0x0010u +#define MONITORID_8514 0x0020u +/* MONITORID_? 0x0030u */ +/* MONITORID_? 0x0040u */ +#define MONITORID_8503 0x0050u +#define MONITORID_8512 0x0060u +#define MONITORID_8513 0x0060u +#define MONITORID_NONE 0x0070u +#define _8PLANE 0x0080u +#define SUBSYS_CNTL 0x42e8u /* Write */ +#define RVBLNKFLG 0x0001u +#define RPICKFLAG 0x0002u +#define RINVALIDIO 0x0004u +#define RGPIDLE 0x0008u +#define IVBLNKFLG 0x0100u +#define IPICKFLAG 0x0200u +#define IINVALIDIO 0x0400u +#define IGPIDLE 0x0800u +#define CHPTEST_NC 0x0000u +#define CHPTEST_NORMAL 0x1000u +#define CHPTEST_ENAB 0x2000u +#define GPCTRL_NC 0x0000u +#define GPCTRL_ENAB 0x4000u +#define GPCTRL_RESET 0x8000u +#define ROM_PAGE_SEL 0x46e8u /* Write */ +#define ADVFUNC_CNTL 0x4ae8u /* Write */ +#define DISABPASSTHRU 0x0001u +#define CLOKSEL 0x0004u +/* ? 0x4ee8u */ +#define EXT_CONFIG_0 0x52e8u /* C & T 82C480 */ +#define EXT_CONFIG_1 0x56e8u /* C & T 82C480 */ +#define EXT_CONFIG_2 0x5ae8u /* C & T 82C480 */ +#define EXT_CONFIG_3 0x5ee8u /* C & T 82C480 */ +/* ? 0x62e8u */ +/* ? 0x66e8u */ +/* ? 0x6ae8u */ +/* ? 0x6ee8u */ +/* ? 0x72e8u */ +/* ? 0x76e8u */ +/* ? 0x7ae8u */ +/* ? 0x7ee8u */ +#define CUR_Y 0x82e8u +#define CUR_X 0x86e8u +#define DESTY_AXSTP 0x8ae8u /* Write */ +#define DESTX_DIASTP 0x8ee8u /* Write */ +#define ERR_TERM 0x92e8u +#define MAJ_AXIS_PCNT 0x96e8u /* Write */ +#define GP_STAT 0x9ae8u /* Read */ +#define GE_STAT 0x9ae8u /* Alias */ +#define DATARDY 0x0100u +#define DATA_READY DATARDY /* Alias */ +#define GPBUSY 0x0200u +#define CMD 0x9ae8u /* Write */ +#define WRTDATA 0x0001u +#define PLANAR 0x0002u +#define LASTPIX 0x0004u +#define LINETYPE 0x0008u +#define DRAW 0x0010u +#define INC_X 0x0020u +#define YMAJAXIS 0x0040u +#define INC_Y 0x0080u +#define PCDATA 0x0100u +#define _16BIT 0x0200u +#define CMD_NOP 0x0000u +#define CMD_OP_MSK 0xf000u +#define BYTSEQ 0x1000u +#define CMD_LINE 0x2000u +#define CMD_RECT 0x4000u +#define CMD_RECTV1 0x6000u +#define CMD_RECTV2 0x8000u +#define CMD_LINEAF 0xa000u +#define CMD_BITBLT 0xc000u +#define SHORT_STROKE 0x9ee8u /* Write */ +#define SSVDRAW 0x0010u +#define VECDIR_000 0x0000u +#define VECDIR_045 0x0020u +#define VECDIR_090 0x0040u +#define VECDIR_135 0x0060u +#define VECDIR_180 0x0080u +#define VECDIR_225 0x00a0u +#define VECDIR_270 0x00c0u +#define VECDIR_315 0x00e0u +#define BKGD_COLOR 0xa2e8u /* Write */ +#define FRGD_COLOR 0xa6e8u /* Write */ +#define WRT_MASK 0xaae8u /* Write */ +#define RD_MASK 0xaee8u /* Write */ +#define COLOR_CMP 0xb2e8u /* Write */ +#define BKGD_MIX 0xb6e8u /* Write */ +/* 0x001fu See MIX_* definitions below */ +#define BSS_BKGDCOL 0x0000u +#define BSS_FRGDCOL 0x0020u +#define BSS_PCDATA 0x0040u +#define BSS_BITBLT 0x0060u +#define FRGD_MIX 0xbae8u /* Write */ +/* 0x001fu See MIX_* definitions below */ +#define FSS_BKGDCOL 0x0000u +#define FSS_FRGDCOL 0x0020u +#define FSS_PCDATA 0x0040u +#define FSS_BITBLT 0x0060u +#define MULTIFUNC_CNTL 0xbee8u /* Write */ +#define MIN_AXIS_PCNT 0x0000u +#define SCISSORS_T 0x1000u +#define SCISSORS_L 0x2000u +#define SCISSORS_B 0x3000u +#define SCISSORS_R 0x4000u +#define M32_MEM_CNTL 0x5000u +#define HORCFG_4 0x0000u +#define HORCFG_5 0x0001u +#define HORCFG_8 0x0002u +#define HORCFG_10 0x0003u +#define VRTCFG_2 0x0000u +#define VRTCFG_4 0x0004u +#define VRTCFG_6 0x0008u +#define VRTCFG_8 0x000cu +#define BUFSWP 0x0010u +#define PATTERN_L 0x8000u +#define PATTERN_H 0x9000u +#define PIX_CNTL 0xa000u +#define PLANEMODE 0x0004u +#define COLCMPOP_F 0x0000u +#define COLCMPOP_T 0x0008u +#define COLCMPOP_GE 0x0010u +#define COLCMPOP_LT 0x0018u +#define COLCMPOP_NE 0x0020u +#define COLCMPOP_EQ 0x0028u +#define COLCMPOP_LE 0x0030u +#define COLCMPOP_GT 0x0038u +#define MIXSEL_FRGDMIX 0x0000u +#define MIXSEL_PATT 0x0040u +#define MIXSEL_EXPPC 0x0080u +#define MIXSEL_EXPBLT 0x00c0u +/* ? 0xc2e8u */ +/* ? 0xc6e8u */ +/* ? 0xcae8u */ +/* ? 0xcee8u */ +/* ? 0xd2e8u */ +/* ? 0xd6e8u */ +/* ? 0xdae8u */ +/* ? 0xdee8u */ +#define PIX_TRANS 0xe2e8u +/* ? 0xe6e8u */ +/* ? 0xeae8u */ +/* ? 0xeee8u */ +/* ? 0xf2e8u */ +/* ? 0xf6e8u */ +/* ? 0xfae8u */ +/* ? 0xfee8u */ + +/* ATI Mach8 & Mach32 register definitions */ +#define OVERSCAN_COLOR_8 0x02eeu /* Write */ /* Mach32 */ +#define OVERSCAN_BLUE_24 0x02efu /* Write */ /* Mach32 */ +#define OVERSCAN_GREEN_24 0x06eeu /* Write */ /* Mach32 */ +#define OVERSCAN_RED_24 0x06efu /* Write */ /* Mach32 */ +#define CURSOR_OFFSET_LO 0x0aeeu /* Write */ /* Mach32 */ +#define CURSOR_OFFSET_HI 0x0eeeu /* Write */ /* Mach32 */ +#define CONFIG_STATUS_1 0x12eeu /* Read */ +#define CLK_MODE 0x0001u /* Mach8 */ +#define BUS_16 0x0002u /* Mach8 */ +#define MC_BUS 0x0004u /* Mach8 */ +#define EEPROM_ENA 0x0008u /* Mach8 */ +#define DRAM_ENA 0x0010u /* Mach8 */ +#define MEM_INSTALLED 0x0060u /* Mach8 */ +#define ROM_ENA 0x0080u /* Mach8 */ +#define ROM_PAGE_ENA 0x0100u /* Mach8 */ +#define ROM_LOCATION 0xfe00u /* Mach8 */ +#define _8514_ONLY 0x0001u /* Mach32 */ +#define BUS_TYPE 0x000eu /* Mach32 */ +#define ISA_16_BIT 0x0000u /* Mach32 */ +#define EISA 0x0002u /* Mach32 */ +#define MICRO_C_16_BIT 0x0004u /* Mach32 */ +#define MICRO_C_8_BIT 0x0006u /* Mach32 */ +#define LOCAL_386SX 0x0008u /* Mach32 */ +#define LOCAL_386DX 0x000au /* Mach32 */ +#define LOCAL_486 0x000cu /* Mach32 */ +#define PCI 0x000eu /* Mach32 */ +#define MEM_TYPE 0x0070u /* Mach32 */ +#define CHIP_DIS 0x0080u /* Mach32 */ +#define TST_VCTR_ENA 0x0100u /* Mach32 */ +#define DACTYPE 0x0e00u /* Mach32 */ +#define MC_ADR_DECODE 0x1000u /* Mach32 */ +#define CARD_ID 0xe000u /* Mach32 */ +#define HORZ_CURSOR_POSN 0x12eeu /* Write */ /* Mach32 */ +#define CONFIG_STATUS_2 0x16eeu /* Read */ +#define SHARE_CLOCK 0x0001u /* Mach8 */ +#define HIRES_BOOT 0x0002u /* Mach8 */ +#define EPROM_16_ENA 0x0004u /* Mach8 */ +#define WRITE_PER_BIT 0x0008u /* Mach8 */ +#define FLASH_ENA 0x0010u /* Mach8 */ +#define SLOW_SEQ_EN 0x0001u /* Mach32 */ +#define MEM_ADDR_DIS 0x0002u /* Mach32 */ +#define ISA_16_ENA 0x0004u /* Mach32 */ +#define KOR_TXT_MODE_ENA 0x0008u /* Mach32 */ +#define LOCAL_BUS_SUPPORT 0x0030u /* Mach32 */ +#define LOCAL_BUS_CONFIG_2 0x0040u /* Mach32 */ +#define LOCAL_BUS_RD_DLY_ENA 0x0080u /* Mach32 */ +#define LOCAL_DAC_EN 0x0100u /* Mach32 */ +#define LOCAL_RDY_EN 0x0200u /* Mach32 */ +#define EEPROM_ADR_SEL 0x0400u /* Mach32 */ +#define GE_STRAP_SEL 0x0800u /* Mach32 */ +#define VESA_RDY 0x1000u /* Mach32 */ +#define Z4GB 0x2000u /* Mach32 */ +#define LOC2_MDRAM 0x4000u /* Mach32 */ +#define VERT_CURSOR_POSN 0x16eeu /* Write */ /* Mach32 */ +#define FIFO_TEST_DATA 0x1aeeu /* Read */ /* Mach32 */ +#define CURSOR_COLOR_0 0x1aeeu /* Write */ /* Mach32 */ +#define CURSOR_COLOR_1 0x1aefu /* Write */ /* Mach32 */ +#define HORZ_CURSOR_OFFSET 0x1eeeu /* Write */ /* Mach32 */ +#define VERT_CURSOR_OFFSET 0x1eefu /* Write */ /* Mach32 */ +#define PCI_CNTL 0x22eeu /* Mach32-PCI */ +#define CRT_PITCH 0x26eeu /* Write */ +#define CRT_OFFSET_LO 0x2aeeu /* Write */ +#define CRT_OFFSET_HI 0x2eeeu /* Write */ +#define LOCAL_CNTL 0x32eeu /* Mach32 */ +#define FIFO_OPT 0x36eeu /* Write */ /* Mach8 */ +#define MISC_OPTIONS 0x36eeu /* Mach32 */ +#define W_STATE_ENA 0x0000u /* Mach32 */ +#define HOST_8_ENA 0x0001u /* Mach32 */ +#define MEM_SIZE_ALIAS 0x000cu /* Mach32 */ +#define MEM_SIZE_512K 0x0000u /* Mach32 */ +#define MEM_SIZE_1M 0x0004u /* Mach32 */ +#define MEM_SIZE_2M 0x0008u /* Mach32 */ +#define MEM_SIZE_4M 0x000cu /* Mach32 */ +#define DISABLE_VGA 0x0010u /* Mach32 */ +#define _16_BIT_IO 0x0020u /* Mach32 */ +#define DISABLE_DAC 0x0040u /* Mach32 */ +#define DLY_LATCH_ENA 0x0080u /* Mach32 */ +#define TEST_MODE 0x0100u /* Mach32 */ +#define BLK_WR_ENA 0x0400u /* Mach32 */ +#define _64_DRAW_ENA 0x0800u /* Mach32 */ +#define FIFO_TEST_TAG 0x3aeeu /* Read */ /* Mach32 */ +#define EXT_CURSOR_COLOR_0 0x3aeeu /* Write */ /* Mach32 */ +#define EXT_CURSOR_COLOR_1 0x3eeeu /* Write */ /* Mach32 */ +#define MEM_BNDRY 0x42eeu /* Mach32 */ +#define MEM_PAGE_BNDRY 0x000fu /* Mach32 */ +#define MEM_BNDRY_ENA 0x0010u /* Mach32 */ +#define SHADOW_CTL 0x46eeu /* Write */ +#define CLOCK_SEL 0x4aeeu +/* DISABPASSTHRU 0x0001u See ADVFUNC_CNTL */ +#define VFIFO_DEPTH_1 0x0100u /* Mach32 */ +#define VFIFO_DEPTH_2 0x0200u /* Mach32 */ +#define VFIFO_DEPTH_3 0x0300u /* Mach32 */ +#define VFIFO_DEPTH_4 0x0400u /* Mach32 */ +#define VFIFO_DEPTH_5 0x0500u /* Mach32 */ +#define VFIFO_DEPTH_6 0x0600u /* Mach32 */ +#define VFIFO_DEPTH_7 0x0700u /* Mach32 */ +#define VFIFO_DEPTH_8 0x0800u /* Mach32 */ +#define VFIFO_DEPTH_9 0x0900u /* Mach32 */ +#define VFIFO_DEPTH_A 0x0a00u /* Mach32 */ +#define VFIFO_DEPTH_B 0x0b00u /* Mach32 */ +#define VFIFO_DEPTH_C 0x0c00u /* Mach32 */ +#define VFIFO_DEPTH_D 0x0d00u /* Mach32 */ +#define VFIFO_DEPTH_E 0x0e00u /* Mach32 */ +#define VFIFO_DEPTH_F 0x0f00u /* Mach32 */ +#define COMPOSITE_SYNC 0x1000u +/* ? 0x4eeeu */ +#define ROM_ADDR_1 0x52eeu +#define BIOS_BASE_SEGMENT 0x007fu /* Mach32 */ +/* ? 0xff80u */ /* Mach32 */ +#define ROM_ADDR_2 0x56eeu /* Sick ... */ +#define SHADOW_SET 0x5aeeu /* Write */ +#define MEM_CFG 0x5eeeu /* Mach32 */ +#define MEM_APERT_SEL 0x0003u /* Mach32 */ +#define MEM_APERT_PAGE 0x000cu /* Mach32 */ +#define MEM_APERT_LOC 0xfff0u /* Mach32 */ +#define EXT_GE_STATUS 0x62eeu /* Read */ /* Mach32 */ +#define HORZ_OVERSCAN 0x62eeu /* Write */ /* Mach32 */ +#define VERT_OVERSCAN 0x66eeu /* Write */ /* Mach32 */ +#define MAX_WAITSTATES 0x6aeeu +#define GE_OFFSET_LO 0x6eeeu /* Write */ +#define BOUNDS_LEFT 0x72eeu /* Read */ +#define GE_OFFSET_HI 0x72eeu /* Write */ +#define BOUNDS_TOP 0x76eeu /* Read */ +#define GE_PITCH 0x76eeu /* Write */ +#define BOUNDS_RIGHT 0x7aeeu /* Read */ +#define EXT_GE_CONFIG 0x7aeeu /* Write */ /* Mach32 */ +#define MONITOR_ALIAS 0x0007u /* Mach32 */ +/* MONITOR_? 0x0000u */ /* Mach32 */ +#define MONITOR_8507 0x0001u /* Mach32 */ +#define MONITOR_8514 0x0002u /* Mach32 */ +/* MONITOR_? 0x0003u */ /* Mach32 */ +/* MONITOR_? 0x0004u */ /* Mach32 */ +#define MONITOR_8503 0x0005u /* Mach32 */ +#define MONITOR_8512 0x0006u /* Mach32 */ +#define MONITOR_8513 0x0006u /* Mach32 */ +#define MONITOR_NONE 0x0007u /* Mach32 */ +#define ALIAS_ENA 0x0008u /* Mach32 */ +#define PIXEL_WIDTH_4 0x0000u /* Mach32 */ +#define PIXEL_WIDTH_8 0x0010u /* Mach32 */ +#define PIXEL_WIDTH_16 0x0020u /* Mach32 */ +#define PIXEL_WIDTH_24 0x0030u /* Mach32 */ +#define RGB16_555 0x0000u /* Mach32 */ +#define RGB16_565 0x0040u /* Mach32 */ +#define RGB16_655 0x0080u /* Mach32 */ +#define RGB16_664 0x00c0u /* Mach32 */ +#define MULTIPLEX_PIXELS 0x0100u /* Mach32 */ +#define RGB24 0x0000u /* Mach32 */ +#define RGBx24 0x0200u /* Mach32 */ +#define BGR24 0x0400u /* Mach32 */ +#define xBGR24 0x0600u /* Mach32 */ +#define DAC_8_BIT_EN 0x4000u /* Mach32 */ +#define ORDER_16BPP_565 RGB16_565 /* Mach32 */ +#define BOUNDS_BOTTOM 0x7eeeu /* Read */ +#define MISC_CNTL 0x7eeeu /* Write */ /* Mach32 */ +#define PATT_DATA_INDEX 0x82eeu +/* ? 0x86eeu */ +/* ? 0x8aeeu */ +#define R_EXT_GE_CONFIG 0x8eeeu /* Read */ /* Mach32 */ +#define PATT_DATA 0x8eeeu /* Write */ +#define R_MISC_CNTL 0x92eeu /* Read */ /* Mach32 */ +#define BRES_COUNT 0x96eeu +#define EXT_FIFO_STATUS 0x9aeeu /* Read */ +#define LINEDRAW_INDEX 0x9aeeu /* Write */ +/* ? 0x9eeeu */ +#define LINEDRAW_OPT 0xa2eeu +#define BOUNDS_RESET 0x0100u +#define CLIP_MODE_0 0x0000u /* Clip exception disabled */ +#define CLIP_MODE_1 0x0200u /* Line segments */ +#define CLIP_MODE_2 0x0400u /* Polygon boundary lines */ +#define CLIP_MODE_3 0x0600u /* Patterned lines */ +#define DEST_X_START 0xa6eeu /* Write */ +#define DEST_X_END 0xaaeeu /* Write */ +#define DEST_Y_END 0xaeeeu /* Write */ +#define R_H_TOTAL_DISP 0xb2eeu /* Read */ /* Mach32 */ +#define SRC_X_STRT 0xb2eeu /* Write */ +#define R_H_SYNC_STRT 0xb6eeu /* Read */ /* Mach32 */ +#define ALU_BG_FN 0xb6eeu /* Write */ +#define R_H_SYNC_WID 0xbaeeu /* Read */ /* Mach32 */ +#define ALU_FG_FN 0xbaeeu /* Write */ +#define SRC_X_END 0xbeeeu /* Write */ +#define R_V_TOTAL 0xc2eeu /* Read */ +#define SRC_Y_DIR 0xc2eeu /* Write */ +#define R_V_DISP 0xc6eeu /* Read */ /* Mach32 */ +#define EXT_SHORT_STROKE 0xc6eeu /* Write */ +#define R_V_SYNC_STRT 0xcaeeu /* Read */ /* Mach32 */ +#define SCAN_X 0xcaeeu /* Write */ +#define VERT_LINE_CNTR 0xceeeu /* Read */ /* Mach32 */ +#define DP_CONFIG 0xceeeu /* Write */ +#define READ_WRITE 0x0001u +#define DATA_WIDTH 0x0200u +#define DATA_ORDER 0x1000u +#define FG_COLOR_SRC_FG 0x2000u +#define FG_COLOR_SRC_BLIT 0x6000u +#define R_V_SYNC_WID 0xd2eeu /* Read */ +#define PATT_LENGTH 0xd2eeu /* Write */ +#define PATT_INDEX 0xd6eeu /* Write */ +#define READ_SRC_X 0xdaeeu /* Read */ /* Mach32 */ +#define EXT_SCISSOR_L 0xdaeeu /* Write */ +#define READ_SRC_Y 0xdeeeu /* Read */ /* Mach32 */ +#define EXT_SCISSOR_T 0xdeeeu /* Write */ +#define EXT_SCISSOR_R 0xe2eeu /* Write */ +#define EXT_SCISSOR_B 0xe6eeu /* Write */ +/* ? 0xeaeeu */ +#define DEST_COMP_FN 0xeeeeu /* Write */ +#define DEST_COLOR_CMP_MASK 0xf2eeu /* Write */ /* Mach32 */ +/* ? 0xf6eeu */ +#define CHIP_ID 0xfaeeu /* Read */ /* Mach32 */ +#define CHIP_CODE_0 0x001fu /* Mach32 */ +#define CHIP_CODE_1 0x03e0u /* Mach32 */ +#define CHIP_CLASS 0x0c00u /* Mach32 */ +#define CHIP_REV 0xf000u /* Mach32 */ +#define LINEDRAW 0xfeeeu /* Write */ + +/* ATI Mach64 register definitions */ +#define CRTC_H_TOTAL_DISP IOPortTag(0x00u, 0x00u) +#define CRTC_H_TOTAL 0x000001fful +/* ? 0x0000fe00ul */ +#define CRTC_H_DISP 0x01ff0000ul +/* ? 0xfe000000ul */ +#define CRTC_H_SYNC_STRT_WID IOPortTag(0x01u, 0x01u) +#define CRTC_H_SYNC_STRT 0x000000fful +#define CRTC_H_SYNC_DLY 0x00000700ul +/* ? 0x00000800ul */ +#define CRTC_H_SYNC_STRT_HI 0x00001000ul +/* ? 0x0000e000ul */ +#define CRTC_H_SYNC_WID 0x001f0000ul +#define CRTC_H_SYNC_POL 0x00200000ul +/* ? 0xffc00000ul */ +#define CRTC_V_TOTAL_DISP IOPortTag(0x02u, 0x02u) +#define CRTC_V_TOTAL 0x000007fful +/* ? 0x0000f800ul */ +#define CRTC_V_DISP 0x07ff0000ul +/* ? 0xf8000000ul */ +#define CRTC_V_SYNC_STRT_WID IOPortTag(0x03u, 0x03u) +#define CRTC_V_SYNC_STRT 0x000007fful +/* ? 0x0000f800ul */ +#define CRTC_V_SYNC_WID 0x001f0000ul +#define CRTC_V_SYNC_POL 0x00200000ul +/* ? 0xffc00000ul */ +#define CRTC_VLINE_CRNT_VLINE IOPortTag(0x04u, 0x04u) +#define CRTC_VLINE 0x000007fful +/* ? 0x0000f800ul */ +#define CRTC_CRNT_VLINE 0x07ff0000ul +/* ? 0xf8000000ul */ +#define CRTC_OFF_PITCH IOPortTag(0x05u, 0x05u) +#define CRTC_OFFSET 0x000ffffful +#define CRTC_OFFSET_VGA 0x0003fffful +#define CRTC_OFFSET_LOCK 0x00100000ul /* XC/XL */ +/* ? 0x00200000ul */ +#define CRTC_PITCH 0xffc00000ul +#define CRTC_INT_CNTL IOPortTag(0x06u, 0x06u) +#define CRTC_VBLANK 0x00000001ul +#define CRTC_VBLANK_INT_EN 0x00000002ul +#define CRTC_VBLANK_INT 0x00000004ul +#define CRTC_VLINE_INT_EN 0x00000008ul +#define CRTC_VLINE_INT 0x00000010ul +#define CRTC_VLINE_SYNC 0x00000020ul +#define CRTC_FRAME 0x00000040ul +#define CRTC_SNAPSHOT_INT_EN 0x00000080ul /* GTPro */ +#define CRTC_SNAPSHOT_INT 0x00000100ul /* GTPro */ +#define CRTC_I2C_INT_EN 0x00000200ul /* GTPro */ +#define CRTC_I2C_INT 0x00000400ul /* GTPro */ +#define CRTC2_VBLANK 0x00000800ul /* LTPro */ +#define CRTC2_VBLANK_INT_EN 0x00001000ul /* LTPro */ +#define CRTC2_VBLANK_INT 0x00002000ul /* LTPro */ +#define CRTC2_VLINE_INT_EN 0x00004000ul /* LTPro */ +#define CRTC2_VLINE_INT 0x00008000ul /* LTPro */ +#define CRTC_CAPBUF0_INT_EN 0x00010000ul /* VT/GT */ +#define CRTC_CAPBUF0_INT 0x00020000ul /* VT/GT */ +#define CRTC_CAPBUF1_INT_EN 0x00040000ul /* VT/GT */ +#define CRTC_CAPBUF1_INT 0x00080000ul /* VT/GT */ +#define CRTC_OVERLAY_EOF_INT_EN 0x00100000ul /* VT/GT */ +#define CRTC_OVERLAY_EOF_INT 0x00200000ul /* VT/GT */ +#define CRTC_ONESHOT_CAP_INT_EN 0x00400000ul /* VT/GT */ +#define CRTC_ONESHOT_CAP_INT 0x00800000ul /* VT/GT */ +#define CRTC_BUSMASTER_EOL_INT_EN 0x01000000ul /* VTB/GTB/LT */ +#define CRTC_BUSMASTER_EOL_INT 0x02000000ul /* VTB/GTB/LT */ +#define CRTC_GP_INT_EN 0x04000000ul /* VTB/GTB/LT */ +#define CRTC_GP_INT 0x08000000ul /* VTB/GTB/LT */ +#define CRTC2_VLINE_SYNC 0x10000000ul /* LTPro */ +#define CRTC_SNAPSHOT2_INT_EN 0x20000000ul /* LTPro */ +#define CRTC_SNAPSHOT2_INT 0x40000000ul /* LTPro */ +#define CRTC_VBLANK_BIT2_INT 0x80000000ul /* GTPro */ +#define CRTC_INT_ENS /* *** UPDATE ME *** */ \ + ( \ + CRTC_VBLANK_INT_EN | \ + CRTC_VLINE_INT_EN | \ + CRTC_SNAPSHOT_INT_EN | \ + CRTC_I2C_INT_EN | \ + CRTC2_VBLANK_INT_EN | \ + CRTC2_VLINE_INT_EN | \ + CRTC_CAPBUF0_INT_EN | \ + CRTC_CAPBUF1_INT_EN | \ + CRTC_OVERLAY_EOF_INT_EN | \ + CRTC_ONESHOT_CAP_INT_EN | \ + CRTC_BUSMASTER_EOL_INT_EN | \ + CRTC_GP_INT_EN | \ + CRTC_SNAPSHOT2_INT_EN | \ + 0 \ + ) +#define CRTC_INT_ACKS /* *** UPDATE ME *** */ \ + ( \ + CRTC_VBLANK_INT | \ + CRTC_VLINE_INT | \ + CRTC_SNAPSHOT_INT | \ + CRTC_I2C_INT | \ + CRTC2_VBLANK_INT | \ + CRTC2_VLINE_INT | \ + CRTC_CAPBUF0_INT | \ + CRTC_CAPBUF1_INT | \ + CRTC_OVERLAY_EOF_INT | \ + CRTC_ONESHOT_CAP_INT | \ + CRTC_BUSMASTER_EOL_INT | \ + CRTC_GP_INT | \ + CRTC_SNAPSHOT2_INT | \ + CRTC_VBLANK_BIT2_INT | \ + 0 \ + ) +#define CRTC_GEN_CNTL IOPortTag(0x07u, 0x07u) +#define CRTC_DBL_SCAN_EN 0x00000001ul +#define CRTC_INTERLACE_EN 0x00000002ul +#define CRTC_HSYNC_DIS 0x00000004ul +#define CRTC_VSYNC_DIS 0x00000008ul +#define CRTC_CSYNC_EN 0x00000010ul +#define CRTC_PIX_BY_2_EN 0x00000020ul +#define CRTC2_DBL_SCAN_EN 0x00000020ul /* LTPro */ +#define CRTC_DISPLAY_DIS 0x00000040ul +#define CRTC_VGA_XOVERSCAN 0x00000080ul +#define CRTC_PIX_WIDTH 0x00000700ul +#define CRTC_BYTE_PIX_ORDER 0x00000800ul +#define CRTC_VSYNC_INT_EN 0x00001000ul /* XC/XL */ +#define CRTC_VSYNC_INT 0x00002000ul /* XC/XL */ +#define CRTC_FIFO_OVERFILL 0x0000c000ul /* VT/GT */ +#define CRTC2_VSYNC_INT_EN 0x00004000ul /* XC/XL */ +#define CRTC2_VSYNC_INT 0x00008000ul /* XC/XL */ +#define CRTC_FIFO_LWM 0x000f0000ul +#define CRTC_HVSYNC_IO_DRIVE 0x00010000ul /* XC/XL */ +#define CRTC2_PIX_WIDTH 0x000e0000ul /* LTPro */ +#define CRTC_VGA_128KAP_PAGING 0x00100000ul /* VT/GT */ +#define CRTC_DISPREQ_ONLY 0x00200000ul /* VT/GT */ +#define CRTC_VFC_SYNC_TRISTATE 0x00200000ul /* VTB/GTB/LT */ +#define CRTC2_EN 0x00200000ul /* LTPro */ +#define CRTC_LOCK_REGS 0x00400000ul /* VT/GT */ +#define CRTC_SYNC_TRISTATE 0x00800000ul /* VT/GT */ +#define CRTC_EXT_DISP_EN 0x01000000ul +#define CRTC_EN 0x02000000ul +#define CRTC_DISP_REQ_EN 0x04000000ul +#define CRTC_VGA_LINEAR 0x08000000ul +#define CRTC_VSYNC_FALL_EDGE 0x10000000ul +#define CRTC_VGA_TEXT_132 0x20000000ul +#define CRTC_CNT_EN 0x40000000ul +#define CRTC_CUR_B_TEST 0x80000000ul +#define CRTC_INT_ENS_X /* *** UPDATE ME *** */ \ + ( \ + CRTC_VSYNC_INT_EN | \ + CRTC2_VSYNC_INT_EN | \ + 0 \ + ) +#define CRTC_INT_ACKS_X /* *** UPDATE ME *** */ \ + ( \ + CRTC_VSYNC_INT | \ + CRTC2_VSYNC_INT | \ + 0 \ + ) +#define DSP_CONFIG BlockIOTag(0x08u) /* VTB/GTB/LT */ +#define DSP_XCLKS_PER_QW 0x00003ffful +/* ? 0x00004000ul */ +#define DSP_FLUSH_WB 0x00008000ul +#define DSP_LOOP_LATENCY 0x000f0000ul +#define DSP_PRECISION 0x00700000ul +/* ? 0xff800000ul */ +#define DSP_ON_OFF BlockIOTag(0x09u) /* VTB/GTB/LT */ +#define DSP_OFF 0x000007fful +/* ? 0x0000f800ul */ +#define DSP_ON 0x07ff0000ul +/* ? 0xf8000000ul */ +#define TIMER_CONFIG BlockIOTag(0x0au) /* VTB/GTB/LT */ +#define MEM_BUF_CNTL BlockIOTag(0x0bu) /* VTB/GTB/LT */ +#define SHARED_CNTL BlockIOTag(0x0cu) /* VTB/GTB/LT */ +#define SHARED_MEM_CONFIG BlockIOTag(0x0du) /* VTB/GTB/LT */ +#define MEM_ADDR_CONFIG BlockIOTag(0x0du) /* GTPro */ +#define SHARED_CNTL_CTD BlockIOTag(0x0eu) /* CTD */ +/* ? 0x00fffffful */ +#define CTD_FIFO5 0x01000000ul +/* ? 0xfe000000ul */ +#define CRT_TRAP BlockIOTag(0x0eu) /* VTB/GTB/LT */ +#define DSTN_CONTROL BlockIOTag(0x0fu) /* LT */ +#define I2C_CNTL_0 BlockIOTag(0x0fu) /* GTPro */ +#define OVR_CLR IOPortTag(0x08u, 0x10u) +#define OVR_CLR_8 0x000000fful +#define OVR_CLR_B 0x0000ff00ul +#define OVR_CLR_G 0x00ff0000ul +#define OVR_CLR_R 0xff000000ul +#define OVR_WID_LEFT_RIGHT IOPortTag(0x09u, 0x11u) +#define OVR_WID_LEFT 0x0000003ful /* 0x0f on +#include +#include +#include +#include +#include +#include + +#include "../vidix.h" +#include "../fourcc.h" +#include "../../libdha/libdha.h" +#include "../../libdha/pci_ids.h" +#include "../../libdha/pci_names.h" + +#include "mach64.h" + +#define UNUSED(x) ((void)(x)) /**< Removes warning about unused arguments */ + +static void *mach64_mmio_base = 0; +static void *mach64_mem_base = 0; +static int32_t mach64_overlay_offset = 0; +static uint32_t mach64_ram_size = 0; +static uint32_t mach64_buffer_base[10][3]; +static int num_mach64_buffers=-1; +static int supports_planar=0; +static int supports_lcd_v_stretch=0; + +pciinfo_t pci_info; +static int probed = 0; +static int __verbose = 0; + +#define VERBOSE_LEVEL 1 + +typedef struct bes_registers_s +{ + /* base address of yuv framebuffer */ + uint32_t yuv_base; + uint32_t fourcc; + /* YUV BES registers */ + uint32_t reg_load_cntl; + uint32_t scale_inc; + uint32_t y_x_start; + uint32_t y_x_end; + uint32_t vid_buf_pitch; + uint32_t height_width; + + uint32_t scale_cntl; + uint32_t exclusive_horz; + uint32_t auto_flip_cntl; + uint32_t filter_cntl; + uint32_t key_cntl; + uint32_t test; + /* Configurable stuff */ + + int brightness; + int saturation; + + int ckey_on; + uint32_t graphics_key_clr; + uint32_t graphics_key_msk; + + int deinterlace_on; + uint32_t deinterlace_pattern; + +} bes_registers_t; + +static bes_registers_t besr; + +typedef struct video_registers_s +{ + const char * sname; + uint32_t name; + uint32_t value; +}video_registers_t; + +static bes_registers_t besr; + +/* Graphic keys */ +static vidix_grkey_t mach64_grkey; + +#define DECLARE_VREG(name) { #name, name, 0 } +static video_registers_t vregs[] = +{ + DECLARE_VREG(OVERLAY_SCALE_INC), + DECLARE_VREG(OVERLAY_Y_X_START), + DECLARE_VREG(OVERLAY_Y_X_END), + DECLARE_VREG(OVERLAY_SCALE_CNTL), + DECLARE_VREG(OVERLAY_EXCLUSIVE_HORZ), + DECLARE_VREG(OVERLAY_EXCLUSIVE_VERT), + DECLARE_VREG(OVERLAY_TEST), + DECLARE_VREG(SCALER_BUF_PITCH), + DECLARE_VREG(SCALER_HEIGHT_WIDTH), + DECLARE_VREG(SCALER_BUF0_OFFSET), + DECLARE_VREG(SCALER_BUF0_OFFSET_U), + DECLARE_VREG(SCALER_BUF0_OFFSET_V), + DECLARE_VREG(SCALER_BUF1_OFFSET), + DECLARE_VREG(SCALER_BUF1_OFFSET_U), + DECLARE_VREG(SCALER_BUF1_OFFSET_V), + DECLARE_VREG(SCALER_H_COEFF0), + DECLARE_VREG(SCALER_H_COEFF1), + DECLARE_VREG(SCALER_H_COEFF2), + DECLARE_VREG(SCALER_H_COEFF3), + DECLARE_VREG(SCALER_H_COEFF4), + DECLARE_VREG(SCALER_COLOUR_CNTL), + DECLARE_VREG(SCALER_THRESHOLD), + DECLARE_VREG(VIDEO_FORMAT), + DECLARE_VREG(VIDEO_CONFIG), + DECLARE_VREG(VIDEO_SYNC_TEST), + DECLARE_VREG(VIDEO_SYNC_TEST_B) +}; + +/* VIDIX exports */ + +/* MMIO space*/ +#define GETREG(TYPE,PTR,OFFZ) (*((volatile TYPE*)((PTR)+(OFFZ)))) +#define SETREG(TYPE,PTR,OFFZ,VAL) (*((volatile TYPE*)((PTR)+(OFFZ))))=VAL + +#define INREG8(addr) GETREG(uint8_t,(uint32_t)mach64_mmio_base,((addr)^0x100)<<2) +#define OUTREG8(addr,val) SETREG(uint8_t,(uint32_t)mach64_mmio_base,((addr)^0x100)<<2,val) +#define INREG(addr) GETREG(uint32_t,(uint32_t)mach64_mmio_base,((addr)^0x100)<<2) +#define OUTREG(addr,val) SETREG(uint32_t,(uint32_t)mach64_mmio_base,((addr)^0x100)<<2,val) + +#define OUTREGP(addr,val,mask) \ + do { \ + unsigned int _tmp = INREG(addr); \ + _tmp &= (mask); \ + _tmp |= (val); \ + OUTREG(addr, _tmp); \ + } while (0) + +static __inline__ int ATIGetMach64LCDReg(int _Index) +{ + OUTREG8(LCD_INDEX, _Index); + return INREG(LCD_DATA); +} + +static __inline__ uint32_t INPLL(uint32_t addr) +{ + uint32_t res; + uint32_t in; + + in= INREG(CLOCK_CNTL); + in &= ~((PLL_WR_EN | PLL_ADDR)); //clean some stuff + OUTREG(CLOCK_CNTL, in | (addr<<10)); + + /* read the register value */ + res = (INREG(CLOCK_CNTL)>>16)&0xFF; + return res; +} + +static __inline__ void OUTPLL(uint32_t addr,uint32_t val) +{ +//FIXME buggy but its not used + /* write addr byte */ + OUTREG8(CLOCK_CNTL + 1, (addr << 2) | PLL_WR_EN); + /* write the register value */ + OUTREG(CLOCK_CNTL + 2, val); + OUTREG8(CLOCK_CNTL + 1, (addr << 2) & ~PLL_WR_EN); +} + +#define OUTPLLP(addr,val,mask) \ + do { \ + unsigned int _tmp = INPLL(addr); \ + _tmp &= (mask); \ + _tmp |= (val); \ + OUTPLL(addr, _tmp); \ + } while (0) + +static void mach64_fifo_wait(unsigned n) +{ + while ((INREG(FIFO_STAT) & 0xffff) > ((uint32_t)(0x8000 >> n))); +} + +static void mach64_wait_for_idle( void ) +{ + mach64_fifo_wait(16); + while ((INREG(GUI_STAT) & 1)!= 0); +} + +static void mach64_wait_vsync( void ) +{ + int i; + + for(i=0; i<2000000; i++) + if( (INREG(CRTC_INT_CNTL)&CRTC_VBLANK)==0 ) break; + for(i=0; i<2000000; i++) + if( (INREG(CRTC_INT_CNTL)&CRTC_VBLANK) ) break; + +} + +static vidix_capability_t mach64_cap = +{ + "BES driver for Mach64/3DRage cards", + "Nick Kurshev and Michael Niedermayer", + TYPE_OUTPUT, + { 0, 0, 0, 0 }, + 2048, + 2048, + 4, + 4, + -1, + FLAG_UPSCALER|FLAG_DOWNSCALER, + VENDOR_ATI, + -1, + { 0, 0, 0, 0 } +}; + +static uint32_t mach64_vid_get_dbpp( void ) +{ + uint32_t dbpp,retval; + dbpp = (INREG(CRTC_GEN_CNTL)>>8)& 0x7; + switch(dbpp) + { + case 1: retval = 4; break; + case 2: retval = 8; break; + case 3: retval = 15; break; + case 4: retval = 16; break; + case 5: retval = 24; break; + default: retval=32; break; + } + return retval; +} + +static int mach64_is_dbl_scan( void ) +{ + return INREG(CRTC_GEN_CNTL) & CRTC_DBL_SCAN_EN; +} + +static int mach64_is_interlace( void ) +{ + return INREG(CRTC_GEN_CNTL) & CRTC_INTERLACE_EN; +} + +static uint32_t mach64_get_xres( void ) +{ + /* FIXME: currently we extract that from CRTC!!!*/ + uint32_t xres,h_total; + h_total = INREG(CRTC_H_TOTAL_DISP); + xres = (h_total >> 16) & 0xffff; + return (xres + 1)*8; +} + +static uint32_t mach64_get_yres( void ) +{ + /* FIXME: currently we extract that from CRTC!!!*/ + uint32_t yres,v_total; + v_total = INREG(CRTC_V_TOTAL_DISP); + yres = (v_total >> 16) & 0xffff; + return yres + 1; +} + +// returns the verical stretch factor in 16.16 +static int mach64_get_vert_stretch(void) +{ + int lcd_index; + int vert_stretching; + int ext_vert_stretch; + int ret; + int yres= mach64_get_yres(); + + if(!supports_lcd_v_stretch){ + if(__verbose>0) printf("[mach64] vertical stretching not supported\n"); + return 1<<16; + } + + lcd_index= INREG(LCD_INDEX); + + vert_stretching= ATIGetMach64LCDReg(LCD_VERT_STRETCHING); + if(!(vert_stretching&VERT_STRETCH_EN)) ret= 1<<16; + else + { + int panel_size; + + ext_vert_stretch= ATIGetMach64LCDReg(LCD_EXT_VERT_STRETCH); + panel_size= (ext_vert_stretch&VERT_PANEL_SIZE)>>11; + panel_size++; + + ret= ((yres<<16) + (panel_size>>1))/panel_size; + } + +// lcd_gen_ctrl = ATIGetMach64LCDReg(LCD_GEN_CNTL); + + OUTREG(LCD_INDEX, lcd_index); + + if(__verbose>0) printf("[mach64] vertical stretching factor= %d\n", ret); + + return ret; +} + +static void mach64_vid_make_default() +{ + mach64_fifo_wait(5); + OUTREG(SCALER_COLOUR_CNTL,0x00101000); + + besr.ckey_on=0; + besr.graphics_key_msk=0; + besr.graphics_key_clr=0; + + OUTREG(OVERLAY_GRAPHICS_KEY_MSK, besr.graphics_key_msk); + OUTREG(OVERLAY_GRAPHICS_KEY_CLR, besr.graphics_key_clr); + OUTREG(OVERLAY_KEY_CNTL,VIDEO_KEY_FN_TRUE|GRAPHIC_KEY_FN_EQ|CMP_MIX_AND); + +} + +static void mach64_vid_dump_regs( void ) +{ + size_t i; + printf("[mach64] *** Begin of DRIVER variables dump ***\n"); + printf("[mach64] mach64_mmio_base=%p\n",mach64_mmio_base); + printf("[mach64] mach64_mem_base=%p\n",mach64_mem_base); + printf("[mach64] mach64_overlay_off=%08X\n",mach64_overlay_offset); + printf("[mach64] mach64_ram_size=%08X\n",mach64_ram_size); + printf("[mach64] video mode: %ux%u@%u\n",mach64_get_xres(),mach64_get_yres(),mach64_vid_get_dbpp()); + printf("[mach64] *** Begin of OV0 registers dump ***\n"); + for(i=0;i PROBE_NORMAL) + { + printf("[mach64] Driver was forced. Was found %sknown chip\n",idx == -1 ? "un" : ""); + if(idx == -1) + printf("[mach64] Assuming it as Mach64\n"); + } + mach64_cap.device_id = lst[i].device; + err = 0; + memcpy(&pci_info,&lst[i],sizeof(pciinfo_t)); + probed=1; + break; + } + } + } + if(err && verbose) printf("[mach64] Can't find chip\n"); + return err; +} + +static void reset_regs( void ) +{ + size_t i; + for(i=0;i0) printf("[mach64] version %s\n", VERSION); + + if((mach64_mmio_base = map_phys_mem(pci_info.base2,0x4000))==(void *)-1) return ENOMEM; + mach64_wait_for_idle(); + mach64_ram_size = INREG(MEM_CNTL) & CTL_MEM_SIZEB; + if (mach64_ram_size < 8) mach64_ram_size = (mach64_ram_size + 1) * 512; + else if (mach64_ram_size < 12) mach64_ram_size = (mach64_ram_size - 3) * 1024; + else mach64_ram_size = (mach64_ram_size - 7) * 2048; + mach64_ram_size *= 0x400; /* KB -> bytes */ + if((mach64_mem_base = map_phys_mem(pci_info.base0,mach64_ram_size))==(void *)-1) return ENOMEM; + memset(&besr,0,sizeof(bes_registers_t)); + printf("[mach64] Video memory = %uMb\n",mach64_ram_size/0x100000); + err = mtrr_set_type(pci_info.base0,mach64_ram_size,MTRR_TYPE_WRCOMB); + if(!err) printf("[mach64] Set write-combining type of video memory\n"); + + /* check if planar formats are supported */ + supports_planar=0; + mach64_wait_for_idle(); + mach64_fifo_wait(2); + if(INREG(SCALER_BUF0_OFFSET_U)) supports_planar=1; + else + { + OUTREG(SCALER_BUF0_OFFSET_U, -1); + + mach64_wait_vsync(); + mach64_wait_for_idle(); + mach64_fifo_wait(2); + + if(INREG(SCALER_BUF0_OFFSET_U)) supports_planar=1; + } + if(supports_planar) printf("[mach64] Planar YUV formats are supported :)\n"); + else printf("[mach64] Planar YUV formats are not supported :(\n"); + + if( mach64_cap.device_id==DEVICE_ATI_RAGE_MOBILITY_P_M + || mach64_cap.device_id==DEVICE_ATI_RAGE_MOBILITY_P_M2 + || mach64_cap.device_id==DEVICE_ATI_RAGE_MOBILITY_L + || mach64_cap.device_id==DEVICE_ATI_RAGE_MOBILITY_L2) + supports_lcd_v_stretch=1; + else + supports_lcd_v_stretch=0; + + reset_regs(); + mach64_vid_make_default(); + + if(__verbose > VERBOSE_LEVEL) mach64_vid_dump_regs(); + if(bm_open() == 0) mach64_cap.flags |= FLAG_DMA | FLAG_EQ_DMA; + else + if(__verbose) printf("[mach64] Can't initialize busmastering: %s\n",strerror(errno)); + return 0; +} + +void vixDestroy(void) +{ + unmap_phys_mem(mach64_mem_base,mach64_ram_size); + unmap_phys_mem(mach64_mmio_base,0x4000); + bm_close(); +} + +int vixGetCapability(vidix_capability_t *to) +{ + memcpy(to, &mach64_cap, sizeof(vidix_capability_t)); + return 0; +} + +static unsigned mach64_query_pitch(unsigned fourcc,const vidix_yuv_t *spitch) +{ + unsigned pitch,spy,spv,spu; + spy = spv = spu = 0; + switch(spitch->y) + { + case 16: + case 32: + case 64: + case 128: + case 256: spy = spitch->y; break; + default: break; + } + switch(spitch->u) + { + case 16: + case 32: + case 64: + case 128: + case 256: spu = spitch->u; break; + default: break; + } + switch(spitch->v) + { + case 16: + case 32: + case 64: + case 128: + case 256: spv = spitch->v; break; + default: break; + } + switch(fourcc) + { + /* 4:2:0 */ + case IMGFMT_IYUV: + case IMGFMT_YV12: + case IMGFMT_I420: + if(spy > 16 && spu == spy/2 && spv == spy/2) pitch = spy; + else pitch = 32; + break; + case IMGFMT_YVU9: + if(spy > 32 && spu == spy/4 && spv == spy/4) pitch = spy; + else pitch = 64; + break; + default: + if(spy >= 16) pitch = spy; + else pitch = 16; + break; + } + return pitch; +} + +static void mach64_compute_framesize(vidix_playback_t *info) +{ + unsigned pitch,awidth; + pitch = mach64_query_pitch(info->fourcc,&info->src.pitch); + switch(info->fourcc) + { + case IMGFMT_I420: + case IMGFMT_YV12: + case IMGFMT_IYUV: + awidth = (info->src.w + (pitch-1)) & ~(pitch-1); + info->frame_size = awidth*(info->src.h+info->src.h/2); + break; + case IMGFMT_YVU9: + awidth = (info->src.w + (pitch-1)) & ~(pitch-1); + info->frame_size = awidth*(info->src.h+info->src.h/8); + break; +// case IMGFMT_RGB32: + case IMGFMT_BGR32: + awidth = (info->src.w*4 + (pitch-1)) & ~(pitch-1); + info->frame_size = (awidth*info->src.h); + break; + /* YUY2 YVYU, RGB15, RGB16 */ + default: + awidth = (info->src.w*2 + (pitch-1)) & ~(pitch-1); + info->frame_size = (awidth*info->src.h); + break; + } + info->frame_size+=256; // so we have some space for alignment & such + info->frame_size&=~16; +} + +static void mach64_vid_stop_video( void ) +{ + mach64_fifo_wait(14); + OUTREG(OVERLAY_SCALE_CNTL, 0x80000000); + OUTREG(OVERLAY_EXCLUSIVE_HORZ, 0); + OUTREG(OVERLAY_EXCLUSIVE_VERT, 0); + OUTREG(SCALER_H_COEFF0, 0x00002000); + OUTREG(SCALER_H_COEFF1, 0x0D06200D); + OUTREG(SCALER_H_COEFF2, 0x0D0A1C0D); + OUTREG(SCALER_H_COEFF3, 0x0C0E1A0C); + OUTREG(SCALER_H_COEFF4, 0x0C14140C); + OUTREG(VIDEO_FORMAT, 0xB000B); + OUTREG(OVERLAY_TEST, 0x0); +} + +static void mach64_vid_display_video( void ) +{ + uint32_t vf; + mach64_fifo_wait(14); + + OUTREG(OVERLAY_Y_X_START, besr.y_x_start); + OUTREG(OVERLAY_Y_X_END, besr.y_x_end); + OUTREG(OVERLAY_SCALE_INC, besr.scale_inc); + OUTREG(SCALER_BUF_PITCH, besr.vid_buf_pitch); + OUTREG(SCALER_HEIGHT_WIDTH, besr.height_width); + OUTREG(SCALER_BUF0_OFFSET, mach64_buffer_base[0][0]); + OUTREG(SCALER_BUF0_OFFSET_U, mach64_buffer_base[0][1]); + OUTREG(SCALER_BUF0_OFFSET_V, mach64_buffer_base[0][2]); + OUTREG(SCALER_BUF1_OFFSET, mach64_buffer_base[0][0]); + OUTREG(SCALER_BUF1_OFFSET_U, mach64_buffer_base[0][1]); + OUTREG(SCALER_BUF1_OFFSET_V, mach64_buffer_base[0][2]); + mach64_wait_vsync(); + + mach64_fifo_wait(4); + OUTREG(OVERLAY_SCALE_CNTL, 0xC4000003); +// OVERLAY_SCALE_CNTL bits & what they seem to affect +// bit 0 no effect +// bit 1 yuv2rgb coeff related +// bit 2 horizontal interpolation if 0 +// bit 3 vertical interpolation if 0 +// bit 4 chroma encoding (0-> 128=neutral / 1-> 0->neutral) +// bit 5-6 gamma correction +// bit 7 nothing visible if set +// bit 8-27 no effect +// bit 28-31 nothing interresting just crashed my system when i played with them :( + + mach64_wait_for_idle(); + vf = INREG(VIDEO_FORMAT); + +// Bits 16-19 seem to select the format +// 0x0 dunno behaves strange +// 0x1 dunno behaves strange +// 0x2 dunno behaves strange +// 0x3 BGR15 +// 0x4 BGR16 +// 0x5 BGR16 (hmm, that need investigation, 2 BGR16 formats, i guess 1 will have only 5bits for green) +// 0x6 BGR32 +// 0x7 BGR32 with somehow mixed even / odd pixels ? +// 0x8 YYYYUVUV +// 0x9 YVU9 +// 0xA YV12 +// 0xB YUY2 +// 0xC UYVY +// 0xD UYVY (no difference is visible if i switch between C/D for every even/odd frame) +// 0xE dunno behaves strange +// 0xF dunno behaves strange +// Bit 28 all values are assumed to be 7 bit with chroma=64 for black (tested with YV12 & YUY2) +// the remaining bits seem to have no effect + + + switch(besr.fourcc) + { + /* BGR formats */ + case IMGFMT_BGR15: OUTREG(VIDEO_FORMAT, 0x00030000); break; + case IMGFMT_BGR16: OUTREG(VIDEO_FORMAT, 0x00040000); break; + case IMGFMT_BGR32: OUTREG(VIDEO_FORMAT, 0x00060000); break; + /* 4:2:0 */ + case IMGFMT_IYUV: + case IMGFMT_I420: + case IMGFMT_YV12: OUTREG(VIDEO_FORMAT, 0x000A0000); break; + + case IMGFMT_YVU9: OUTREG(VIDEO_FORMAT, 0x00090000); break; + /* 4:2:2 */ + case IMGFMT_YVYU: + case IMGFMT_UYVY: OUTREG(VIDEO_FORMAT, 0x000C0000); break; + case IMGFMT_YUY2: + default: OUTREG(VIDEO_FORMAT, 0x000B0000); break; + } + if(__verbose > VERBOSE_LEVEL) mach64_vid_dump_regs(); +} + +static int mach64_vid_init_video( vidix_playback_t *config ) +{ + uint32_t src_w,src_h,dest_w,dest_h,pitch,h_inc,v_inc,left,leftUV,top,ecp,y_pos; + int is_420,best_pitch,mpitch; + int src_offset_y, src_offset_u, src_offset_v; + unsigned int i; + + mach64_vid_stop_video(); +/* warning, if left or top are != 0 this will fail, as the framesize is too small then */ + left = config->src.x; + top = config->src.y; + src_h = config->src.h; + src_w = config->src.w; + is_420 = 0; + if(config->fourcc == IMGFMT_YV12 || + config->fourcc == IMGFMT_I420 || + config->fourcc == IMGFMT_IYUV) is_420 = 1; + best_pitch = mach64_query_pitch(config->fourcc,&config->src.pitch); + mpitch = best_pitch-1; + switch(config->fourcc) + { + case IMGFMT_YVU9: + /* 4:2:0 */ + case IMGFMT_IYUV: + case IMGFMT_YV12: + case IMGFMT_I420: pitch = (src_w + mpitch) & ~mpitch; + config->dest.pitch.y = + config->dest.pitch.u = + config->dest.pitch.v = best_pitch; + besr.vid_buf_pitch= pitch; + break; + /* RGB 4:4:4:4 */ + case IMGFMT_RGB32: + case IMGFMT_BGR32: pitch = (src_w*4 + mpitch) & ~mpitch; + config->dest.pitch.y = + config->dest.pitch.u = + config->dest.pitch.v = best_pitch; + besr.vid_buf_pitch= pitch>>2; + break; + /* 4:2:2 */ + default: /* RGB15, RGB16, YVYU, UYVY, YUY2 */ + pitch = ((src_w*2) + mpitch) & ~mpitch; + config->dest.pitch.y = + config->dest.pitch.u = + config->dest.pitch.v = best_pitch; + besr.vid_buf_pitch= pitch>>1; + break; + } + dest_w = config->dest.w; + dest_h = config->dest.h; + besr.fourcc = config->fourcc; + ecp = (INPLL(PLL_VCLK_CNTL) & PLL_ECP_DIV) >> 4; +#if 0 +{ +int i; +for(i=0; i<32; i++){ + printf("%X ", INPLL(i)); +} +} +#endif + if(__verbose>0) printf("[mach64] ecp: %d\n", ecp); + v_inc = src_h * mach64_get_vert_stretch(); + + if(mach64_is_interlace()) v_inc<<=1; + if(mach64_is_dbl_scan() ) v_inc>>=1; + v_inc>>=4; // convert 16.16 -> 20.12 + v_inc/= dest_h; + + h_inc = (src_w << (12+ecp)) / dest_w; + /* keep everything in 16.16 */ + config->offsets[0] = 0; + for(i=1; inum_frames; i++) + config->offsets[i] = config->offsets[i-1] + config->frame_size; + + /*FIXME the left / top stuff is broken (= zoom a src rectangle from a larger one) + 1. the framesize isnt known as the outer src rectangle dimensions arent known + 2. the mach64 needs aligned addresses so it cant work anyway + -> so we could shift the outer buffer to compensate that but that would mean + alignment problems for the code which writes into it + */ + + if(is_420) + { + config->offset.y= 0; + config->offset.u= (pitch*src_h + 15)&~15; + config->offset.v= (config->offset.u + (pitch*src_h>>2) + 15)&~15; + + src_offset_y= config->offset.y + top*pitch + left; + src_offset_u= config->offset.u + (top*pitch>>2) + (left>>1); + src_offset_v= config->offset.v + (top*pitch>>2) + (left>>1); + + if(besr.fourcc == IMGFMT_I420 || besr.fourcc == IMGFMT_IYUV) + { + uint32_t tmp; + tmp = config->offset.u; + config->offset.u = config->offset.v; + config->offset.v = tmp; + } + } + else if(besr.fourcc == IMGFMT_YVU9) + { + config->offset.y= 0; + config->offset.u= (pitch*src_h + 15)&~15; + config->offset.v= (config->offset.u + (pitch*src_h>>4) + 15)&~15; + + src_offset_y= config->offset.y + top*pitch + left; + src_offset_u= config->offset.u + (top*pitch>>4) + (left>>1); + src_offset_v= config->offset.v + (top*pitch>>4) + (left>>1); + } + else if(besr.fourcc == IMGFMT_BGR32) + { + config->offset.y = config->offset.u = config->offset.v = 0; + src_offset_y= src_offset_u= src_offset_v= top*pitch + (left << 2); + } + else + { + config->offset.y = config->offset.u = config->offset.v = 0; + src_offset_y= src_offset_u= src_offset_v= top*pitch + (left << 1); + } + + num_mach64_buffers= config->num_frames; + for(i=0; inum_frames; i++) + { + mach64_buffer_base[i][0]= (mach64_overlay_offset + config->offsets[i] + src_offset_y)&~15; + mach64_buffer_base[i][1]= (mach64_overlay_offset + config->offsets[i] + src_offset_u)&~15; + mach64_buffer_base[i][2]= (mach64_overlay_offset + config->offsets[i] + src_offset_v)&~15; + } + + leftUV = (left >> 17) & 15; + left = (left >> 16) & 15; + besr.scale_inc = ( h_inc << 16 ) | v_inc; + y_pos = config->dest.y; + if(mach64_is_dbl_scan()) y_pos*=2; + else + if(mach64_is_interlace()) y_pos/=2; + besr.y_x_start = y_pos | (config->dest.x << 16); + y_pos =config->dest.y + dest_h; + if(mach64_is_dbl_scan()) y_pos*=2; + else + if(mach64_is_interlace()) y_pos/=2; + besr.y_x_end = y_pos | ((config->dest.x + dest_w) << 16); + besr.height_width = ((src_w - left)<<16) | (src_h - top); + + return 0; +} + +static int is_supported_fourcc(uint32_t fourcc) +{ + switch(fourcc) + { + case IMGFMT_YV12: + case IMGFMT_I420: + case IMGFMT_YVU9: + case IMGFMT_IYUV: + return supports_planar; + case IMGFMT_YUY2: + case IMGFMT_UYVY: + case IMGFMT_BGR15: + case IMGFMT_BGR16: + case IMGFMT_BGR32: + return 1; + default: + return 0; + } +} + +int vixQueryFourcc(vidix_fourcc_t *to) +{ + if(is_supported_fourcc(to->fourcc)) + { + to->depth = VID_DEPTH_1BPP | VID_DEPTH_2BPP | + VID_DEPTH_4BPP | VID_DEPTH_8BPP | + VID_DEPTH_12BPP| VID_DEPTH_15BPP| + VID_DEPTH_16BPP| VID_DEPTH_24BPP| + VID_DEPTH_32BPP; + to->flags = VID_CAP_EXPAND | VID_CAP_SHRINK | VID_CAP_COLORKEY; + return 0; + } + else to->depth = to->flags = 0; + return ENOSYS; +} + +int vixConfigPlayback(vidix_playback_t *info) +{ + unsigned rgb_size,nfr; + if(!is_supported_fourcc(info->fourcc)) return ENOSYS; + if(info->num_frames>VID_PLAY_MAXFRAMES) info->num_frames=VID_PLAY_MAXFRAMES; + + mach64_compute_framesize(info); + rgb_size = mach64_get_xres()*mach64_get_yres()*((mach64_vid_get_dbpp()+7)/8); + nfr = info->num_frames; + for(;nfr>0;nfr--) + { + mach64_overlay_offset = mach64_ram_size - info->frame_size*nfr; + mach64_overlay_offset &= 0xffff0000; + if(mach64_overlay_offset >= (int)rgb_size ) break; + } + if(nfr <= 3) + { + nfr = info->num_frames; + for(;nfr>0;nfr--) + { + mach64_overlay_offset = mach64_ram_size - info->frame_size*nfr; + mach64_overlay_offset &= 0xffff0000; + if(mach64_overlay_offset>=0) break; + } + } + if(nfr <= 0) return EINVAL; + info->num_frames=nfr; + num_mach64_buffers = info->num_frames; + info->dga_addr = (char *)mach64_mem_base + mach64_overlay_offset; + mach64_vid_init_video(info); + return 0; +} + +int vixPlaybackOn(void) +{ + int err; + mach64_vid_display_video(); + err = INREG(SCALER_BUF_PITCH) == besr.vid_buf_pitch ? 0 : EINTR; + if(err) + { + printf("[mach64] *** Internal fatal error ***: Detected pitch corruption\n" + "[mach64] Try decrease number of buffers\n"); + } + return err; +} + +int vixPlaybackOff(void) +{ + mach64_vid_stop_video(); + return 0; +} + +int vixPlaybackFrameSelect(unsigned int frame) +{ + uint32_t off[6]; + int i; + int last_frame= (frame-1+num_mach64_buffers) % num_mach64_buffers; +//printf("Selecting frame %d\n", frame); + /* + buf3-5 always should point onto second buffer for better + deinterlacing and TV-in + */ + if(num_mach64_buffers==1) return 0; + for(i=0; i<3; i++) + { + off[i] = mach64_buffer_base[frame][i]; + off[i+3]= mach64_buffer_base[last_frame][i]; + } + if(__verbose > VERBOSE_LEVEL) printf("mach64_vid: flip_page = %u\n",frame); + +#if 0 // delay routine so the individual frames can be ssen better +{ +volatile int i=0; +for(i=0; i<10000000; i++); +} +#endif + + mach64_wait_for_idle(); + mach64_fifo_wait(7); + + OUTREG(SCALER_BUF0_OFFSET, off[0]); + OUTREG(SCALER_BUF0_OFFSET_U, off[1]); + OUTREG(SCALER_BUF0_OFFSET_V, off[2]); + OUTREG(SCALER_BUF1_OFFSET, off[3]); + OUTREG(SCALER_BUF1_OFFSET_U, off[4]); + OUTREG(SCALER_BUF1_OFFSET_V, off[5]); + if(num_mach64_buffers==2) mach64_wait_vsync(); //only wait for vsync if we do double buffering + + if(__verbose > VERBOSE_LEVEL) mach64_vid_dump_regs(); + return 0; +} + +vidix_video_eq_t equal = +{ + VEQ_CAP_BRIGHTNESS | VEQ_CAP_SATURATION + , + 0, 0, 0, 0, 0, 0, 0, 0 }; + +int vixPlaybackGetEq( vidix_video_eq_t * eq) +{ + memcpy(eq,&equal,sizeof(vidix_video_eq_t)); + return 0; +} + +int vixPlaybackSetEq( const vidix_video_eq_t * eq) +{ + int br,sat; + if(eq->cap & VEQ_CAP_BRIGHTNESS) equal.brightness = eq->brightness; + if(eq->cap & VEQ_CAP_CONTRAST) equal.contrast = eq->contrast; + if(eq->cap & VEQ_CAP_SATURATION) equal.saturation = eq->saturation; + if(eq->cap & VEQ_CAP_HUE) equal.hue = eq->hue; + if(eq->cap & VEQ_CAP_RGB_INTENSITY) + { + equal.red_intensity = eq->red_intensity; + equal.green_intensity = eq->green_intensity; + equal.blue_intensity = eq->blue_intensity; + } + equal.flags = eq->flags; + br = equal.brightness * 64 / 1000; + if(br < -64) br = -64; if(br > 63) br = 63; + sat = (equal.saturation + 1000) * 16 / 1000; + if(sat < 0) sat = 0; if(sat > 31) sat = 31; + OUTREG(SCALER_COLOUR_CNTL, (br & 0x7f) | (sat << 8) | (sat << 16)); + return 0; +} + +int vixGetGrKeys(vidix_grkey_t *grkey) +{ + memcpy(grkey, &mach64_grkey, sizeof(vidix_grkey_t)); + return(0); +} + +int vixSetGrKeys(const vidix_grkey_t *grkey) +{ + memcpy(&mach64_grkey, grkey, sizeof(vidix_grkey_t)); + + if(mach64_grkey.ckey.op == CKEY_TRUE) + { + besr.ckey_on=1; + + switch(mach64_vid_get_dbpp()) + { + case 15: + besr.graphics_key_msk=0x7FFF; + besr.graphics_key_clr= + ((mach64_grkey.ckey.blue &0xF8)>>3) + | ((mach64_grkey.ckey.green&0xF8)<<2) + | ((mach64_grkey.ckey.red &0xF8)<<7); + break; + case 16: + besr.graphics_key_msk=0xFFFF; + besr.graphics_key_clr= + ((mach64_grkey.ckey.blue &0xF8)>>3) + | ((mach64_grkey.ckey.green&0xFC)<<3) + | ((mach64_grkey.ckey.red &0xF8)<<8); + break; + case 24: + besr.graphics_key_msk=0xFFFFFF; + besr.graphics_key_clr= + ((mach64_grkey.ckey.blue &0xFF)) + | ((mach64_grkey.ckey.green&0xFF)<<8) + | ((mach64_grkey.ckey.red &0xFF)<<16); + break; + case 32: + besr.graphics_key_msk=0xFFFFFF; + besr.graphics_key_clr= + ((mach64_grkey.ckey.blue &0xFF)) + | ((mach64_grkey.ckey.green&0xFF)<<8) + | ((mach64_grkey.ckey.red &0xFF)<<16); + break; + default: + besr.ckey_on=0; + besr.graphics_key_msk=0; + besr.graphics_key_clr=0; + } + } + else + { + besr.ckey_on=0; + besr.graphics_key_msk=0; + besr.graphics_key_clr=0; + } + + mach64_fifo_wait(4); + OUTREG(OVERLAY_GRAPHICS_KEY_MSK, besr.graphics_key_msk); + OUTREG(OVERLAY_GRAPHICS_KEY_CLR, besr.graphics_key_clr); +// OUTREG(OVERLAY_VIDEO_KEY_MSK, 0); +// OUTREG(OVERLAY_VIDEO_KEY_CLR, 0); + if(besr.ckey_on) + OUTREG(OVERLAY_KEY_CNTL,VIDEO_KEY_FN_TRUE|GRAPHIC_KEY_FN_EQ|CMP_MIX_AND); + else + OUTREG(OVERLAY_KEY_CNTL,VIDEO_KEY_FN_TRUE|GRAPHIC_KEY_FN_TRUE|CMP_MIX_AND); + + return(0); +} diff --git a/src/video_out/vidix/drivers/mga_vid.c b/src/video_out/vidix/drivers/mga_vid.c new file mode 100644 index 000000000..a5442bd0f --- /dev/null +++ b/src/video_out/vidix/drivers/mga_vid.c @@ -0,0 +1,1488 @@ +/* + Matrox MGA driver + + ported to VIDIX by Alex Beregszaszi + + YUY2 support (see config.format) added by A'rpi/ESP-team + double buffering added by A'rpi/ESP-team + + Brightness/contrast support by Nick Kurshev + + TODO: + * fix doublebuffering for vidix + * fix memory size detection (current reading pci userconfig isn't + working as requested - returns the max avail. ram on arch?) + * fix/complete brightness/contrast handling (Nick) + MGA users: please test this! (#define MGA_EQUALIZER) + * translate all non-english comments to english +*/ + +/* + * Original copyright: + * + * mga_vid.c + * + * Copyright (C) 1999 Aaron Holtzman + * + * Module skeleton based on gutted agpgart module by Jeff Hartmann + * + * + * Matrox MGA G200/G400 YUV Video Interface module Version 0.1.0 + * + * BES == Back End Scaler + * + * This software has been released under the terms of the GNU Public + * license. See http://www.gnu.org/copyleft/gpl.html for details. + */ + +//#define CRTC2 + +// Set this value, if autodetection fails! (video ram size in megabytes) +// #define MGA_MEMORY_SIZE 16 + +/* No irq support in userspace implemented yet, do not enable this! */ +/* disable irq */ +#undef MGA_ALLOW_IRQ + +#define MGA_VSYNC_POS 2 + +#undef MGA_EQUALIZER + +#undef MGA_PCICONFIG_MEMDETECT + +#define MGA_DEFAULT_FRAMES 1 + +#include +#include +#include +#include +#include +#include + +#include "../vidix.h" +#include "../fourcc.h" +#include "../../libdha/libdha.h" +#include "../../libdha/pci_ids.h" +#include "../../libdha/pci_names.h" + +#if !defined(ENOTSUP) && defined(EOPNOTSUPP) +#define ENOTSUP EOPNOTSUPP +#endif + +/* from radeon_vid */ +#define GETREG(TYPE,PTR,OFFZ) (*((volatile TYPE*)((PTR)+(OFFZ)))) +#define SETREG(TYPE,PTR,OFFZ,VAL) (*((volatile TYPE*)((PTR)+(OFFZ))))=VAL + +#define readb(addr) GETREG(uint8_t,(uint32_t)(addr),0) +#define writeb(val,addr) SETREG(uint8_t,(uint32_t)(addr),0,val) +#define readl(addr) GETREG(uint32_t,(uint32_t)(addr),0) +#define writel(val,addr) SETREG(uint32_t,(uint32_t)(addr),0,val) + +static int mga_verbose = 0; + +/* for device detection */ +static int probed = 0; +static pciinfo_t pci_info; + +/* internal booleans */ +static int mga_vid_in_use = 0; +static int is_g400 = 0; +static int vid_src_ready = 0; +static int vid_overlay_on = 0; + +/* mapped physical addresses */ +static uint8_t *mga_mmio_base = 0; +static uint32_t mga_mem_base = 0; + +static int mga_src_base = 0; /* YUV buffer position in video memory */ + +static uint32_t mga_ram_size = 0; /* how much megabytes videoram we have */ + +/* Graphic keys */ +static vidix_grkey_t mga_grkey; + +static int colkey_saved = 0; +static int colkey_on = 0; +static unsigned char colkey_color[4]; +static unsigned char colkey_mask[4]; + +/* for IRQ */ +static int mga_irq = -1; + +static int mga_next_frame = 0; + +static vidix_capability_t mga_cap = +{ + "Matrox MGA G200/G400 YUV Video", + "Aaron Holtzman, Arpad Gereoffy, Alex Beregszaszi, Nick Kurshev", + TYPE_OUTPUT, + { 0, 0, 0, 0 }, + 1600, /* 2048x2048 is supported if Pontscho is right */ + 1200, + 4, + 4, + -1, + FLAG_UPSCALER | FLAG_DOWNSCALER +#ifdef MGA_EQUALIZER + | FLAG_EQUALIZER +#endif + , + VENDOR_MATROX, + -1, /* will be set in vixProbe */ + { 0, 0, 0, 0} +}; + +/* MATROX BES registers */ +typedef struct bes_registers_s +{ + //BES Control + uint32_t besctl; + //BES Global control + uint32_t besglobctl; + //Luma control (brightness and contrast) + uint32_t beslumactl; + //Line pitch + uint32_t bespitch; + + //Buffer A-1 Chroma 3 plane org + uint32_t besa1c3org; + //Buffer A-1 Chroma org + uint32_t besa1corg; + //Buffer A-1 Luma org + uint32_t besa1org; + + //Buffer A-2 Chroma 3 plane org + uint32_t besa2c3org; + //Buffer A-2 Chroma org + uint32_t besa2corg; + //Buffer A-2 Luma org + uint32_t besa2org; + + //Buffer B-1 Chroma 3 plane org + uint32_t besb1c3org; + //Buffer B-1 Chroma org + uint32_t besb1corg; + //Buffer B-1 Luma org + uint32_t besb1org; + + //Buffer B-2 Chroma 3 plane org + uint32_t besb2c3org; + //Buffer B-2 Chroma org + uint32_t besb2corg; + //Buffer B-2 Luma org + uint32_t besb2org; + + //BES Horizontal coord + uint32_t beshcoord; + //BES Horizontal inverse scaling [5.14] + uint32_t beshiscal; + //BES Horizontal source start [10.14] (for scaling) + uint32_t beshsrcst; + //BES Horizontal source ending [10.14] (for scaling) + uint32_t beshsrcend; + //BES Horizontal source last + uint32_t beshsrclst; + + + //BES Vertical coord + uint32_t besvcoord; + //BES Vertical inverse scaling [5.14] + uint32_t besviscal; + //BES Field 1 vertical source last position + uint32_t besv1srclst; + //BES Field 1 weight start + uint32_t besv1wght; + //BES Field 2 vertical source last position + uint32_t besv2srclst; + //BES Field 2 weight start + uint32_t besv2wght; + +} bes_registers_t; +static bes_registers_t regs; + +#ifdef CRTC2 +typedef struct crtc2_registers_s +{ + uint32_t c2ctl; + uint32_t c2datactl; + uint32_t c2misc; + uint32_t c2hparam; + uint32_t c2hsync; + uint32_t c2offset; + uint32_t c2pl2startadd0; + uint32_t c2pl2startadd1; + uint32_t c2pl3startadd0; + uint32_t c2pl3startadd1; + uint32_t c2preload; + uint32_t c2spicstartadd0; + uint32_t c2spicstartadd1; + uint32_t c2startadd0; + uint32_t c2startadd1; + uint32_t c2subpiclut; + uint32_t c2vcount; + uint32_t c2vparam; + uint32_t c2vsync; +} crtc2_registers_t; +static crtc2_registers_t cregs; +#endif + +//All register offsets are converted to word aligned offsets (32 bit) +//because we want all our register accesses to be 32 bits +#define VCOUNT 0x1e20 + +#define PALWTADD 0x3c00 // Index register for X_DATAREG port +#define X_DATAREG 0x3c0a + +#define XMULCTRL 0x19 +#define BPP_8 0x00 +#define BPP_15 0x01 +#define BPP_16 0x02 +#define BPP_24 0x03 +#define BPP_32_DIR 0x04 +#define BPP_32_PAL 0x07 + +#define XCOLMSK 0x40 +#define X_COLKEY 0x42 +#define XKEYOPMODE 0x51 +#define XCOLMSK0RED 0x52 +#define XCOLMSK0GREEN 0x53 +#define XCOLMSK0BLUE 0x54 +#define XCOLKEY0RED 0x55 +#define XCOLKEY0GREEN 0x56 +#define XCOLKEY0BLUE 0x57 + +#ifdef CRTC2 +/*CRTC2 registers*/ +#define XMISCCTRL 0x1e +#define C2CTL 0x3c10 +#define C2DATACTL 0x3c4c +#define C2MISC 0x3c44 +#define C2HPARAM 0x3c14 +#define C2HSYNC 0x3c18 +#define C2OFFSET 0x3c40 +#define C2PL2STARTADD0 0x3c30 // like BESA1CORG +#define C2PL2STARTADD1 0x3c34 // like BESA2CORG +#define C2PL3STARTADD0 0x3c38 // like BESA1C3ORG +#define C2PL3STARTADD1 0x3c3c // like BESA2C3ORG +#define C2PRELOAD 0x3c24 +#define C2SPICSTARTADD0 0x3c54 +#define C2SPICSTARTADD1 0x3c58 +#define C2STARTADD0 0x3c28 // like BESA1ORG +#define C2STARTADD1 0x3c2c // like BESA2ORG +#define C2SUBPICLUT 0x3c50 +#define C2VCOUNT 0x3c48 +#define C2VPARAM 0x3c1c +#define C2VSYNC 0x3c20 +#endif /* CRTC2 */ + +// Backend Scaler registers +#define BESCTL 0x3d20 +#define BESGLOBCTL 0x3dc0 +#define BESLUMACTL 0x3d40 +#define BESPITCH 0x3d24 + +#define BESA1C3ORG 0x3d60 +#define BESA1CORG 0x3d10 +#define BESA1ORG 0x3d00 + +#define BESA2C3ORG 0x3d64 +#define BESA2CORG 0x3d14 +#define BESA2ORG 0x3d04 + +#define BESB1C3ORG 0x3d68 +#define BESB1CORG 0x3d18 +#define BESB1ORG 0x3d08 + +#define BESB2C3ORG 0x3d6C +#define BESB2CORG 0x3d1C +#define BESB2ORG 0x3d0C + +#define BESHCOORD 0x3d28 +#define BESHISCAL 0x3d30 +#define BESHSRCEND 0x3d3C +#define BESHSRCLST 0x3d50 +#define BESHSRCST 0x3d38 +#define BESV1WGHT 0x3d48 +#define BESV2WGHT 0x3d4c +#define BESV1SRCLST 0x3d54 +#define BESV2SRCLST 0x3d58 +#define BESVISCAL 0x3d34 +#define BESVCOORD 0x3d2c +#define BESSTATUS 0x3dc4 + +#define CRTCX 0x1fd4 +#define CRTCD 0x1fd5 +#define IEN 0x1e1c +#define ICLEAR 0x1e18 +#define STATUS 0x1e14 + + +#ifdef CRTC2 +static void crtc2_frame_sel(int frame) +{ +switch(frame) { +case 0: + cregs.c2pl2startadd0=regs.besa1corg; + cregs.c2pl3startadd0=regs.besa1c3org; + cregs.c2startadd0=regs.besa1org; + break; +case 1: + cregs.c2pl2startadd0=regs.besa2corg; + cregs.c2pl3startadd0=regs.besa2c3org; + cregs.c2startadd0=regs.besa2org; + break; +case 2: + cregs.c2pl2startadd0=regs.besb1corg; + cregs.c2pl3startadd0=regs.besb1c3org; + cregs.c2startadd0=regs.besb1org; + break; +case 3: + cregs.c2pl2startadd0=regs.besb2corg; + cregs.c2pl3startadd0=regs.besb2c3org; + cregs.c2startadd0=regs.besb2org; + break; +} + writel(cregs.c2startadd0, mga_mmio_base + C2STARTADD0); + writel(cregs.c2pl2startadd0, mga_mmio_base + C2PL2STARTADD0); + writel(cregs.c2pl3startadd0, mga_mmio_base + C2PL3STARTADD0); +} +#endif + +int vixPlaybackFrameSelect(unsigned int frame) +{ + printf("[mga] frameselect: %d\n", frame); +#if MGA_ALLOW_IRQ + if (mga_irq != -1) + { + mga_next_frame = frame; + } + else +#endif + { + //we don't need the vcount protection as we're only hitting + //one register (and it doesn't seem to be double buffered) + regs.besctl = (regs.besctl & ~0x07000000) + (frame << 25); + writel( regs.besctl, mga_mmio_base + BESCTL ); + +// writel( regs.besglobctl + ((readl(mga_mmio_base + VCOUNT)+2)<<16), + writel( regs.besglobctl + (MGA_VSYNC_POS<<16), + mga_mmio_base + BESGLOBCTL); +#ifdef CRTC2 + crtc2_frame_sel(frame); +#endif + } + + return(0); +} + + +static void mga_vid_write_regs(int restore) +{ + //Make sure internal registers don't get updated until we're done + writel( (readl(mga_mmio_base + VCOUNT)-1)<<16, + mga_mmio_base + BESGLOBCTL); + + // color or coordinate keying + + if(restore && colkey_saved){ + // restore it + colkey_saved=0; + + printf("[mga] Restoring colorkey (ON: %d %02X:%02X:%02X)\n", + colkey_on,colkey_color[0],colkey_color[1],colkey_color[2]); + + // Set color key registers: + writeb( XKEYOPMODE, mga_mmio_base + PALWTADD); + writeb( colkey_on, mga_mmio_base + X_DATAREG); + + writeb( XCOLKEY0RED, mga_mmio_base + PALWTADD); + writeb( colkey_color[0], mga_mmio_base + X_DATAREG); + writeb( XCOLKEY0GREEN, mga_mmio_base + PALWTADD); + writeb( colkey_color[1], mga_mmio_base + X_DATAREG); + writeb( XCOLKEY0BLUE, mga_mmio_base + PALWTADD); + writeb( colkey_color[2], mga_mmio_base + X_DATAREG); + writeb( X_COLKEY, mga_mmio_base + PALWTADD); + writeb( colkey_color[3], mga_mmio_base + X_DATAREG); + + writeb( XCOLMSK0RED, mga_mmio_base + PALWTADD); + writeb( colkey_mask[0], mga_mmio_base + X_DATAREG); + writeb( XCOLMSK0GREEN, mga_mmio_base + PALWTADD); + writeb( colkey_mask[1], mga_mmio_base + X_DATAREG); + writeb( XCOLMSK0BLUE, mga_mmio_base + PALWTADD); + writeb( colkey_mask[2], mga_mmio_base + X_DATAREG); + writeb( XCOLMSK, mga_mmio_base + PALWTADD); + writeb( colkey_mask[3], mga_mmio_base + X_DATAREG); + + } else if(!colkey_saved){ + // save it + colkey_saved=1; + // Get color key registers: + writeb( XKEYOPMODE, mga_mmio_base + PALWTADD); + colkey_on=(unsigned char)readb(mga_mmio_base + X_DATAREG) & 1; + + writeb( XCOLKEY0RED, mga_mmio_base + PALWTADD); + colkey_color[0]=(unsigned char)readb(mga_mmio_base + X_DATAREG); + writeb( XCOLKEY0GREEN, mga_mmio_base + PALWTADD); + colkey_color[1]=(unsigned char)readb(mga_mmio_base + X_DATAREG); + writeb( XCOLKEY0BLUE, mga_mmio_base + PALWTADD); + colkey_color[2]=(unsigned char)readb(mga_mmio_base + X_DATAREG); + writeb( X_COLKEY, mga_mmio_base + PALWTADD); + colkey_color[3]=(unsigned char)readb(mga_mmio_base + X_DATAREG); + + writeb( XCOLMSK0RED, mga_mmio_base + PALWTADD); + colkey_mask[0]=(unsigned char)readb(mga_mmio_base + X_DATAREG); + writeb( XCOLMSK0GREEN, mga_mmio_base + PALWTADD); + colkey_mask[1]=(unsigned char)readb(mga_mmio_base + X_DATAREG); + writeb( XCOLMSK0BLUE, mga_mmio_base + PALWTADD); + colkey_mask[2]=(unsigned char)readb(mga_mmio_base + X_DATAREG); + writeb( XCOLMSK, mga_mmio_base + PALWTADD); + colkey_mask[3]=(unsigned char)readb(mga_mmio_base + X_DATAREG); + + printf("[mga] Saved colorkey (ON: %d %02X:%02X:%02X)\n", + colkey_on,colkey_color[0],colkey_color[1],colkey_color[2]); + + } + +if(!restore){ + writeb( XKEYOPMODE, mga_mmio_base + PALWTADD); + writeb( mga_grkey.ckey.op == CKEY_TRUE, mga_mmio_base + X_DATAREG); + if ( mga_grkey.ckey.op == CKEY_TRUE ) + { + uint32_t r=0, g=0, b=0; + + writeb( XMULCTRL, mga_mmio_base + PALWTADD); + switch (readb (mga_mmio_base + X_DATAREG)) + { + case BPP_8: + /* Need to look up the color index, just using + color 0 for now. */ + break; + + case BPP_15: + r = mga_grkey.ckey.red >> 3; + g = mga_grkey.ckey.green >> 3; + b = mga_grkey.ckey.blue >> 3; + break; + + case BPP_16: + r = mga_grkey.ckey.red >> 3; + g = mga_grkey.ckey.green >> 2; + b = mga_grkey.ckey.blue >> 3; + break; + + case BPP_24: + case BPP_32_DIR: + case BPP_32_PAL: + r = mga_grkey.ckey.red; + g = mga_grkey.ckey.green; + b = mga_grkey.ckey.blue; + break; + } + + // Disable color keying on alpha channel + writeb( XCOLMSK, mga_mmio_base + PALWTADD); + writeb( 0x00, mga_mmio_base + X_DATAREG); + writeb( X_COLKEY, mga_mmio_base + PALWTADD); + writeb( 0x00, mga_mmio_base + X_DATAREG); + + + // Set up color key registers + writeb( XCOLKEY0RED, mga_mmio_base + PALWTADD); + writeb( r, mga_mmio_base + X_DATAREG); + writeb( XCOLKEY0GREEN, mga_mmio_base + PALWTADD); + writeb( g, mga_mmio_base + X_DATAREG); + writeb( XCOLKEY0BLUE, mga_mmio_base + PALWTADD); + writeb( b, mga_mmio_base + X_DATAREG); + + // Set up color key mask registers + writeb( XCOLMSK0RED, mga_mmio_base + PALWTADD); + writeb( 0xff, mga_mmio_base + X_DATAREG); + writeb( XCOLMSK0GREEN, mga_mmio_base + PALWTADD); + writeb( 0xff, mga_mmio_base + X_DATAREG); + writeb( XCOLMSK0BLUE, mga_mmio_base + PALWTADD); + writeb( 0xff, mga_mmio_base + X_DATAREG); + } + +} + + // Backend Scaler + writel( regs.besctl, mga_mmio_base + BESCTL); + if(is_g400) + writel( regs.beslumactl, mga_mmio_base + BESLUMACTL); + writel( regs.bespitch, mga_mmio_base + BESPITCH); + + writel( regs.besa1org, mga_mmio_base + BESA1ORG); + writel( regs.besa1corg, mga_mmio_base + BESA1CORG); + writel( regs.besa2org, mga_mmio_base + BESA2ORG); + writel( regs.besa2corg, mga_mmio_base + BESA2CORG); + writel( regs.besb1org, mga_mmio_base + BESB1ORG); + writel( regs.besb1corg, mga_mmio_base + BESB1CORG); + writel( regs.besb2org, mga_mmio_base + BESB2ORG); + writel( regs.besb2corg, mga_mmio_base + BESB2CORG); + if(is_g400) + { + writel( regs.besa1c3org, mga_mmio_base + BESA1C3ORG); + writel( regs.besa2c3org, mga_mmio_base + BESA2C3ORG); + writel( regs.besb1c3org, mga_mmio_base + BESB1C3ORG); + writel( regs.besb2c3org, mga_mmio_base + BESB2C3ORG); + } + + writel( regs.beshcoord, mga_mmio_base + BESHCOORD); + writel( regs.beshiscal, mga_mmio_base + BESHISCAL); + writel( regs.beshsrcst, mga_mmio_base + BESHSRCST); + writel( regs.beshsrcend, mga_mmio_base + BESHSRCEND); + writel( regs.beshsrclst, mga_mmio_base + BESHSRCLST); + + writel( regs.besvcoord, mga_mmio_base + BESVCOORD); + writel( regs.besviscal, mga_mmio_base + BESVISCAL); + + writel( regs.besv1srclst, mga_mmio_base + BESV1SRCLST); + writel( regs.besv1wght, mga_mmio_base + BESV1WGHT); + writel( regs.besv2srclst, mga_mmio_base + BESV2SRCLST); + writel( regs.besv2wght, mga_mmio_base + BESV2WGHT); + + //update the registers somewhere between 1 and 2 frames from now. + writel( regs.besglobctl + ((readl(mga_mmio_base + VCOUNT)+2)<<16), + mga_mmio_base + BESGLOBCTL); + +#if 0 + printf("[mga] wrote BES registers\n"); + printf("[mga] BESCTL = 0x%08x\n", + readl(mga_mmio_base + BESCTL)); + printf("[mga] BESGLOBCTL = 0x%08x\n", + readl(mga_mmio_base + BESGLOBCTL)); + printf("[mga] BESSTATUS= 0x%08x\n", + readl(mga_mmio_base + BESSTATUS)); +#endif +#ifdef CRTC2 +// printf("c2ctl:0x%08x c2datactl:0x%08x\n",readl(mga_mmio_base + C2CTL),readl(mga_mmio_base + C2DATACTL)); +// printf("c2misc:0x%08x\n",readl(mga_mmio_base + C2MISC)); +// printf("c2ctl:0x%08x c2datactl:0x%08x\n",cregs.c2ctl,cregs.c2datactl); + +// writel(cregs.c2ctl, mga_mmio_base + C2CTL); + + writel(((readl(mga_mmio_base + C2CTL) & ~0x03e00000) + (cregs.c2ctl & 0x03e00000)), mga_mmio_base + C2CTL); + writel(((readl(mga_mmio_base + C2DATACTL) & ~0x000000ff) + (cregs.c2datactl & 0x000000ff)), mga_mmio_base + C2DATACTL); + // ctrc2 + // disable CRTC2 acording to specs +// writel(cregs.c2ctl & 0xfffffff0, mga_mmio_base + C2CTL); + // je to treba ??? +// writeb((readb(mga_mmio_base + XMISCCTRL) & 0x19) | 0xa2, mga_mmio_base + XMISCCTRL); // MAFC - mfcsel & vdoutsel +// writeb((readb(mga_mmio_base + XMISCCTRL) & 0x19) | 0x92, mga_mmio_base + XMISCCTRL); +// writeb((readb(mga_mmio_base + XMISCCTRL) & ~0xe9) + 0xa2, mga_mmio_base + XMISCCTRL); +// writel(cregs.c2datactl, mga_mmio_base + C2DATACTL); +// writel(cregs.c2hparam, mga_mmio_base + C2HPARAM); +// writel(cregs.c2hsync, mga_mmio_base + C2HSYNC); +// writel(cregs.c2vparam, mga_mmio_base + C2VPARAM); +// writel(cregs.c2vsync, mga_mmio_base + C2VSYNC); + writel(cregs.c2misc, mga_mmio_base + C2MISC); + + printf("c2offset = %d\n",cregs.c2offset); + + writel(cregs.c2offset, mga_mmio_base + C2OFFSET); + writel(cregs.c2startadd0, mga_mmio_base + C2STARTADD0); +// writel(cregs.c2startadd1, mga_mmio_base + C2STARTADD1); + writel(cregs.c2pl2startadd0, mga_mmio_base + C2PL2STARTADD0); +// writel(cregs.c2pl2startadd1, mga_mmio_base + C2PL2STARTADD1); + writel(cregs.c2pl3startadd0, mga_mmio_base + C2PL3STARTADD0); +// writel(cregs.c2pl3startadd1, mga_mmio_base + C2PL3STARTADD1); + writel(cregs.c2spicstartadd0, mga_mmio_base + C2SPICSTARTADD0); +// writel(cregs.c2spicstartadd1, mga_mmio_base + C2SPICSTARTADD1); +// writel(cregs.c2subpiclut, mga_mmio_base + C2SUBPICLUT); +// writel(cregs.c2preload, mga_mmio_base + C2PRELOAD); + // finaly enable everything +// writel(cregs.c2ctl, mga_mmio_base + C2CTL); +// printf("c2ctl:0x%08x c2datactl:0x%08x\n",readl(mga_mmio_base + C2CTL),readl(mga_mmio_base + C2DATACTL)); +// printf("c2misc:0x%08x\n", readl(mga_mmio_base + C2MISC)); +#endif +} + +#ifdef MGA_ALLOW_IRQ +static void enable_irq(){ + long int cc; + + cc = readl(mga_mmio_base + IEN); +// printf("*** !!! IRQREG = %d\n", (int)(cc&0xff)); + + writeb( 0x11, mga_mmio_base + CRTCX); + + writeb(0x20, mga_mmio_base + CRTCD ); /* clear 0, enable off */ + writeb(0x00, mga_mmio_base + CRTCD ); /* enable on */ + writeb(0x10, mga_mmio_base + CRTCD ); /* clear = 1 */ + + writel( regs.besglobctl , mga_mmio_base + BESGLOBCTL); + + return; +} + +static void disable_irq() +{ + writeb( 0x11, mga_mmio_base + CRTCX); + writeb(0x20, mga_mmio_base + CRTCD ); /* clear 0, enable off */ + + return; +} + +void mga_handle_irq(int irq, void *dev_id/*, struct pt_regs *pregs*/) { +// static int frame=0; +// static int counter=0; + long int cc; +// if ( ! mga_enabled_flag ) return; + +// printf("vcount = %d\n",readl(mga_mmio_base + VCOUNT)); + + //printf("mga_interrupt #%d\n", irq); + + if ( irq != -1 ) { + + cc = readl(mga_mmio_base + STATUS); + if ( ! (cc & 0x10) ) return; /* vsyncpen */ +// debug_irqcnt++; + } + +// if ( debug_irqignore ) { +// debug_irqignore = 0; + + +/* + if ( mga_conf_deinterlace ) { + if ( mga_first_field ) { + // printf("mga_interrupt first field\n"); + if ( syncfb_interrupt() ) + mga_first_field = 0; + } else { + // printf("mga_interrupt second field\n"); + mga_select_buffer( mga_current_field | 2 ); + mga_first_field = 1; + } + } else { + syncfb_interrupt(); + } +*/ + +// frame=(frame+1)&1; + regs.besctl = (regs.besctl & ~0x07000000) + (mga_next_frame << 25); + writel( regs.besctl, mga_mmio_base + BESCTL ); + +#ifdef CRTC2 +// sem pridat vyber obrazku !!!! + crtc2_frame_sel(mga_next_frame); +#endif + +#if 0 + ++counter; + if(!(counter&63)){ + printf("mga irq counter = %d\n",counter); + } +#endif + +// } else { +// debug_irqignore = 1; +// } + + if ( irq != -1 ) { + writeb( 0x11, mga_mmio_base + CRTCX); + writeb( 0, mga_mmio_base + CRTCD ); + writeb( 0x10, mga_mmio_base + CRTCD ); + } + +// writel( regs.besglobctl, mga_mmio_base + BESGLOBCTL); + + + return; + +} +#endif /* MGA_ALLOW_IRQ */ + +int vixConfigPlayback(vidix_playback_t *config) +{ + int x, y, sw, sh, dw, dh; + int besleft, bestop, ifactor, ofsleft, ofstop, baseadrofs, weight, weights; +#ifdef CRTC2 +#define right_margin 0 +#define left_margin 18 +#define hsync_len 46 +#define lower_margin 10 +#define vsync_len 4 +#define upper_margin 39 + + unsigned int hdispend = (config->src.w + 31) & ~31; + unsigned int hsyncstart = hdispend + (right_margin & ~7); + unsigned int hsyncend = hsyncstart + (hsync_len & ~7); + unsigned int htotal = hsyncend + (left_margin & ~7); + unsigned int vdispend = config->src.h; + unsigned int vsyncstart = vdispend + lower_margin; + unsigned int vsyncend = vsyncstart + vsync_len; + unsigned int vtotal = vsyncend + upper_margin; +#endif + + if ((config->num_frames < 1) || (config->num_frames > 4)) + { + printf("[mga] illegal num_frames: %d, setting to %d\n", + config->num_frames, MGA_DEFAULT_FRAMES); + config->num_frames = MGA_DEFAULT_FRAMES; +// return(EINVAL); + } + + x = config->dest.x; + y = config->dest.y; + sw = config->src.w; + sh = config->src.h; + dw = config->dest.w; + dh = config->dest.h; + + config->dest.pitch.y=32; + config->dest.pitch.u=config->dest.pitch.v=16; + + printf("[mga] Setting up a %dx%d+%d+%d video window (src %dx%d) format %X\n", + dw, dh, x, y, sw, sh, config->fourcc); + + if ((sw < 4) || (sh < 4) || (dw < 4) || (dh < 4)) + { + printf("[mga] Invalid src/dest dimensions\n"); + return(EINVAL); + } + + //FIXME check that window is valid and inside desktop + +// printf("[mga] vcount = %d\n", readl(mga_mmio_base + VCOUNT)); + + config->offsets[0] = 0; + config->offsets[1] = config->frame_size; + config->offsets[2] = 2*config->frame_size; + config->offsets[3] = 3*config->frame_size; + + config->offset.y=0; + config->offset.v=((sw + 31) & ~31) * sh; + config->offset.u=config->offset.v+((sw + 31) & ~31) * sh /4; + + switch(config->fourcc) + { + case IMGFMT_I420: + case IMGFMT_IYUV: + case IMGFMT_YV12: + config->frame_size = ((sw + 31) & ~31) * sh + (((sw + 31) & ~31) * sh) / 2; + break; + case IMGFMT_YUY2: + case IMGFMT_UYVY: + config->frame_size = ((sw + 31) & ~31) * sh * 2; + break; + default: + printf("[mga] Unsupported pixel format: %x\n", config->fourcc); + return(ENOTSUP); + } + +// config->frame_size = config->src.h*config->src.w+(config->src.w*config->src.h)/2; + + //FIXME figure out a better way to allocate memory on card + //allocate 2 megs + //mga_src_base = mga_mem_base + (MGA_VIDMEM_SIZE-2) * 0x100000; + //mga_src_base = (MGA_VIDMEM_SIZE-3) * 0x100000; + + mga_src_base = (mga_ram_size*0x100000-config->num_frames*config->frame_size); + if (mga_src_base < 0) + { + printf("[mga] not enough memory for frames!\n"); + return(EFAULT); + } + mga_src_base &= (~0xFFFF); /* 64k boundary */ + printf("[mga] YUV buffer base: %p\n", mga_src_base); + + config->dga_addr = mga_mem_base + mga_src_base; + + /* for G200 set Interleaved UV planes */ + if (!is_g400) + config->flags = VID_PLAY_INTERLEAVED_UV | INTERLEAVING_UV; + + //Setup the BES registers for a three plane 4:2:0 video source + + regs.besglobctl = 0; + + switch(config->fourcc) + { + case IMGFMT_YV12: + case IMGFMT_I420: + case IMGFMT_IYUV: + regs.besctl = 1 // BES enabled + + (0<<6) // even start polarity + + (1<<10) // x filtering enabled + + (1<<11) // y filtering enabled + + (1<<16) // chroma upsampling + + (1<<17) // 4:2:0 mode + + (1<<18); // dither enabled +#if 0 + if(is_g400) + { + //zoom disabled, zoom filter disabled, 420 3 plane format, proc amp + //disabled, rgb mode disabled + regs.besglobctl = (1<<5); + } + else + { + //zoom disabled, zoom filter disabled, Cb samples in 0246, Cr + //in 1357, BES register update on besvcnt + regs.besglobctl = 0; + } +#endif + break; + + case IMGFMT_YUY2: + regs.besctl = 1 // BES enabled + + (0<<6) // even start polarity + + (1<<10) // x filtering enabled + + (1<<11) // y filtering enabled + + (1<<16) // chroma upsampling + + (0<<17) // 4:2:2 mode + + (1<<18); // dither enabled + + regs.besglobctl = 0; // YUY2 format selected + break; + + case IMGFMT_UYVY: + regs.besctl = 1 // BES enabled + + (0<<6) // even start polarity + + (1<<10) // x filtering enabled + + (1<<11) // y filtering enabled + + (1<<16) // chroma upsampling + + (0<<17) // 4:2:2 mode + + (1<<18); // dither enabled + + regs.besglobctl = 1<<6; // UYVY format selected + break; + + } + + + //Disable contrast and brightness control + regs.besglobctl |= (1<<5) + (1<<7); + regs.beslumactl = (0x7f << 16) + (0x80<<0); + regs.beslumactl = 0x80<<0; + + //Setup destination window boundaries + besleft = x > 0 ? x : 0; + bestop = y > 0 ? y : 0; + regs.beshcoord = (besleft<<16) + (x + dw-1); + regs.besvcoord = (bestop<<16) + (y + dh-1); + + //Setup source dimensions + regs.beshsrclst = (sw - 1) << 16; + regs.bespitch = (sw + 31) & ~31 ; + + //Setup horizontal scaling + ifactor = ((sw-1)<<14)/(dw-1); + ofsleft = besleft - x; + + regs.beshiscal = ifactor<<2; + regs.beshsrcst = (ofsleft*ifactor)<<2; + regs.beshsrcend = regs.beshsrcst + (((dw - ofsleft - 1) * ifactor) << 2); + + //Setup vertical scaling + ifactor = ((sh-1)<<14)/(dh-1); + ofstop = bestop - y; + + regs.besviscal = ifactor<<2; + + baseadrofs = ((ofstop*regs.besviscal)>>16)*regs.bespitch; + //frame_size = ((sw + 31) & ~31) * sh + (((sw + 31) & ~31) * sh) / 2; + regs.besa1org = (uint32_t) mga_src_base + baseadrofs; + regs.besa2org = (uint32_t) mga_src_base + baseadrofs + 1*config->frame_size; + regs.besb1org = (uint32_t) mga_src_base + baseadrofs + 2*config->frame_size; + regs.besb2org = (uint32_t) mga_src_base + baseadrofs + 3*config->frame_size; + +if(config->fourcc==IMGFMT_YV12 + ||config->fourcc==IMGFMT_IYUV + ||config->fourcc==IMGFMT_I420 + ){ + // planar YUV frames: + if (is_g400) + baseadrofs = (((ofstop*regs.besviscal)/4)>>16)*regs.bespitch; + else + baseadrofs = (((ofstop*regs.besviscal)/2)>>16)*regs.bespitch; + + if(config->fourcc==IMGFMT_YV12){ + regs.besa1corg = (uint32_t) mga_src_base + baseadrofs + regs.bespitch * sh ; + regs.besa2corg = (uint32_t) mga_src_base + baseadrofs + 1*config->frame_size + regs.bespitch * sh; + regs.besb1corg = (uint32_t) mga_src_base + baseadrofs + 2*config->frame_size + regs.bespitch * sh; + regs.besb2corg = (uint32_t) mga_src_base + baseadrofs + 3*config->frame_size + regs.bespitch * sh; + regs.besa1c3org = regs.besa1corg + ((regs.bespitch * sh) / 4); + regs.besa2c3org = regs.besa2corg + ((regs.bespitch * sh) / 4); + regs.besb1c3org = regs.besb1corg + ((regs.bespitch * sh) / 4); + regs.besb2c3org = regs.besb2corg + ((regs.bespitch * sh) / 4); + } else { + regs.besa1c3org = (uint32_t) mga_src_base + baseadrofs + regs.bespitch * sh ; + regs.besa2c3org = (uint32_t) mga_src_base + baseadrofs + 1*config->frame_size + regs.bespitch * sh; + regs.besb1c3org = (uint32_t) mga_src_base + baseadrofs + 2*config->frame_size + regs.bespitch * sh; + regs.besb2c3org = (uint32_t) mga_src_base + baseadrofs + 3*config->frame_size + regs.bespitch * sh; + regs.besa1corg = regs.besa1c3org + ((regs.bespitch * sh) / 4); + regs.besa2corg = regs.besa2c3org + ((regs.bespitch * sh) / 4); + regs.besb1corg = regs.besb1c3org + ((regs.bespitch * sh) / 4); + regs.besb2corg = regs.besb2c3org + ((regs.bespitch * sh) / 4); + } + +} + + weight = ofstop * (regs.besviscal >> 2); + weights = weight < 0 ? 1 : 0; + regs.besv2wght = regs.besv1wght = (weights << 16) + ((weight & 0x3FFF) << 2); + regs.besv2srclst = regs.besv1srclst = sh - 1 - (((ofstop * regs.besviscal) >> 16) & 0x03FF); + +#ifdef CRTC2 + // pridat hlavni registry - tj. casovani ... + + +switch(config->fourcc){ + case IMGFMT_YV12: + case IMGFMT_I420: + case IMGFMT_IYUV: + cregs.c2ctl = 1 // CRTC2 enabled + + (1<<1) // external clock + + (0<<2) // external clock + + (1<<3) // pixel clock enable - not needed ??? + + (0<<4) // high prioryty req + + (1<<5) // high prioryty req + + (0<<6) // high prioryty req + + (1<<8) // high prioryty req max + + (0<<9) // high prioryty req max + + (0<<10) // high prioryty req max + + (0<<20) // CRTC1 to DAC + + (1<<21) // 420 mode + + (1<<22) // 420 mode + + (1<<23) // 420 mode + + (0<<24) // single chroma line for 420 mode - need to be corrected + + (0<<25) /*/ interlace mode - need to be corrected*/ + + (0<<26) // field legth polariry + + (0<<27) // field identification polariry + + (1<<28) // VIDRST detection mode + + (0<<29) // VIDRST detection mode + + (1<<30) // Horizontal counter preload + + (1<<31) // Vertical counter preload + ; + cregs.c2datactl = 1 // disable dither - propably not needed, we are already in YUV mode + + (1<<1) // Y filter enable + + (1<<2) // CbCr filter enable + + (0<<3) // subpicture enable (disabled) + + (0<<4) // NTSC enable (disabled - PAL) + + (0<<5) // C2 static subpicture enable (disabled) + + (0<<6) // C2 subpicture offset division (disabled) + + (0<<7) // 422 subformat selection ! +/* + (0<<8) // 15 bpp high alpha + + (0<<9) // 15 bpp high alpha + + (0<<10) // 15 bpp high alpha + + (0<<11) // 15 bpp high alpha + + (0<<12) // 15 bpp high alpha + + (0<<13) // 15 bpp high alpha + + (0<<14) // 15 bpp high alpha + + (0<<15) // 15 bpp high alpha + + (0<<16) // 15 bpp low alpha + + (0<<17) // 15 bpp low alpha + + (0<<18) // 15 bpp low alpha + + (0<<19) // 15 bpp low alpha + + (0<<20) // 15 bpp low alpha + + (0<<21) // 15 bpp low alpha + + (0<<22) // 15 bpp low alpha + + (0<<23) // 15 bpp low alpha + + (0<<24) // static subpicture key + + (0<<25) // static subpicture key + + (0<<26) // static subpicture key + + (0<<27) // static subpicture key + + (0<<28) // static subpicture key +*/ ; + break; + + case IMGFMT_YUY2: + cregs.c2ctl = 1 // CRTC2 enabled + + (1<<1) // external clock + + (0<<2) // external clock + + (1<<3) // pixel clock enable - not needed ??? + + (0<<4) // high prioryty req - acc to spec + + (1<<5) // high prioryty req + + (0<<6) // high prioryty req + // 7 reserved + + (1<<8) // high prioryty req max + + (0<<9) // high prioryty req max + + (0<<10) // high prioryty req max + // 11-19 reserved + + (0<<20) // CRTC1 to DAC + + (1<<21) // 422 mode + + (0<<22) // 422 mode + + (1<<23) // 422 mode + + (0<<24) // single chroma line for 420 mode - need to be corrected + + (0<<25) /*/ interlace mode - need to be corrected*/ + + (0<<26) // field legth polariry + + (0<<27) // field identification polariry + + (1<<28) // VIDRST detection mode + + (0<<29) // VIDRST detection mode + + (1<<30) // Horizontal counter preload + + (1<<31) // Vertical counter preload + ; + cregs.c2datactl = 1 // disable dither - propably not needed, we are already in YUV mode + + (1<<1) // Y filter enable + + (1<<2) // CbCr filter enable + + (0<<3) // subpicture enable (disabled) + + (0<<4) // NTSC enable (disabled - PAL) + + (0<<5) // C2 static subpicture enable (disabled) + + (0<<6) // C2 subpicture offset division (disabled) + + (0<<7) // 422 subformat selection ! +/* + (0<<8) // 15 bpp high alpha + + (0<<9) // 15 bpp high alpha + + (0<<10) // 15 bpp high alpha + + (0<<11) // 15 bpp high alpha + + (0<<12) // 15 bpp high alpha + + (0<<13) // 15 bpp high alpha + + (0<<14) // 15 bpp high alpha + + (0<<15) // 15 bpp high alpha + + (0<<16) // 15 bpp low alpha + + (0<<17) // 15 bpp low alpha + + (0<<18) // 15 bpp low alpha + + (0<<19) // 15 bpp low alpha + + (0<<20) // 15 bpp low alpha + + (0<<21) // 15 bpp low alpha + + (0<<22) // 15 bpp low alpha + + (0<<23) // 15 bpp low alpha + + (0<<24) // static subpicture key + + (0<<25) // static subpicture key + + (0<<26) // static subpicture key + + (0<<27) // static subpicture key + + (0<<28) // static subpicture key +*/ ; + break; + + case IMGFMT_UYVY: + cregs.c2ctl = 1 // CRTC2 enabled + + (1<<1) // external clock + + (0<<2) // external clock + + (1<<3) // pixel clock enable - not needed ??? + + (0<<4) // high prioryty req + + (1<<5) // high prioryty req + + (0<<6) // high prioryty req + + (1<<8) // high prioryty req max + + (0<<9) // high prioryty req max + + (0<<10) // high prioryty req max + + (0<<20) // CRTC1 to DAC + + (1<<21) // 422 mode + + (0<<22) // 422 mode + + (1<<23) // 422 mode + + (1<<24) // single chroma line for 420 mode - need to be corrected + + (1<<25) /*/ interlace mode - need to be corrected*/ + + (0<<26) // field legth polariry + + (0<<27) // field identification polariry + + (1<<28) // VIDRST detection mode + + (0<<29) // VIDRST detection mode + + (1<<30) // Horizontal counter preload + + (1<<31) // Vertical counter preload + ; + cregs.c2datactl = 0 // enable dither - propably not needed, we are already in YUV mode + + (1<<1) // Y filter enable + + (1<<2) // CbCr filter enable + + (0<<3) // subpicture enable (disabled) + + (0<<4) // NTSC enable (disabled - PAL) + + (0<<5) // C2 static subpicture enable (disabled) + + (0<<6) // C2 subpicture offset division (disabled) + + (1<<7) // 422 subformat selection ! +/* + (0<<8) // 15 bpp high alpha + + (0<<9) // 15 bpp high alpha + + (0<<10) // 15 bpp high alpha + + (0<<11) // 15 bpp high alpha + + (0<<12) // 15 bpp high alpha + + (0<<13) // 15 bpp high alpha + + (0<<14) // 15 bpp high alpha + + (0<<15) // 15 bpp high alpha + + (0<<16) // 15 bpp low alpha + + (0<<17) // 15 bpp low alpha + + (0<<18) // 15 bpp low alpha + + (0<<19) // 15 bpp low alpha + + (0<<20) // 15 bpp low alpha + + (0<<21) // 15 bpp low alpha + + (0<<22) // 15 bpp low alpha + + (0<<23) // 15 bpp low alpha + + (0<<24) // static subpicture key + + (0<<25) // static subpicture key + + (0<<26) // static subpicture key + + (0<<27) // static subpicture key + + (0<<28) // static subpicture key +*/ ; + break; + } + + cregs.c2hparam=((hdispend - 8) << 16) | (htotal - 8); + cregs.c2hsync=((hsyncend - 8) << 16) | (hsyncstart - 8); + + cregs.c2misc=0 // CRTCV2 656 togg f0 + +(0<<1) // CRTCV2 656 togg f0 + +(0<<2) // CRTCV2 656 togg f0 + +(0<<4) // CRTCV2 656 togg f1 + +(0<<5) // CRTCV2 656 togg f1 + +(0<<6) // CRTCV2 656 togg f1 + +(0<<8) // Hsync active high + +(0<<9) // Vsync active high + // 16-27 c2vlinecomp - nevim co tam dat + ; + cregs.c2offset=(regs.bespitch << 1); + + cregs.c2pl2startadd0=regs.besa1corg; +// cregs.c2pl2startadd1=regs.besa2corg; + cregs.c2pl3startadd0=regs.besa1c3org; +// cregs.c2pl3startadd1=regs.besa2c3org; + + cregs.c2preload=(vsyncstart << 16) | (hsyncstart); // from + + cregs.c2spicstartadd0=0; // not used +// cregs.c2spicstartadd1=0; // not used + + cregs.c2startadd0=regs.besa1org; +// cregs.c2startadd1=regs.besa2org; + + cregs.c2subpiclut=0; //not used + + cregs.c2vparam=((vdispend - 1) << 16) | (vtotal - 1); + cregs.c2vsync=((vsyncend - 1) << 16) | (vsyncstart - 1); +#endif /* CRTC2 */ + + mga_vid_write_regs(0); + return(0); +} + +int vixPlaybackOn(void) +{ + printf("[mga] playback on\n"); + + vid_src_ready = 1; + if(vid_overlay_on) + { + regs.besctl |= 1; + mga_vid_write_regs(0); + } +#ifdef MGA_ALLOW_IRQ + if (mga_irq != -1) + enable_irq(); +#endif + mga_next_frame=0; + + return(0); +} + +int vixPlaybackOff(void) +{ + printf("[mga] playback off\n"); + + vid_src_ready = 0; +#ifdef MGA_ALLOW_IRQ + if (mga_irq != -1) + disable_irq(); +#endif + regs.besctl &= ~1; + regs.besglobctl &= ~(1<<6); /* UYVY format selected */ + mga_vid_write_regs(0); + + return(0); +} + +int vixProbe(int verbose,int force) +{ + pciinfo_t lst[MAX_PCI_DEVICES]; + unsigned int i, num_pci; + int err; + + printf("[mga] probe\n"); + + mga_verbose = verbose; + + is_g400 = -1; + + err = pci_scan(&lst, &num_pci); + if (err) + { + printf("[mga] Error occured during pci scan: %s\n", strerror(err)); + return(err); + } + + if (mga_verbose > 1) + printf("[mga] found %d pci devices\n", num_pci); + + for (i = 0; i < num_pci; i++) + { + if (mga_verbose > 2) + printf("[mga] pci[%d] vendor: %d device: %d\n", + i, lst[i].vendor, lst[i].device); + if (lst[i].vendor == VENDOR_MATROX) + { + switch(lst[i].device) + { + case DEVICE_MATROX_MGA_G550_AGP: + printf("[mga] Found MGA G550\n"); + is_g400 = 1; + goto card_found; + case DEVICE_MATROX_MGA_G400_AGP: + printf("[mga] Found MGA G400/G450\n"); + is_g400 = 1; + goto card_found; + case DEVICE_MATROX_MGA_G200_AGP: + printf("[mga] Found MGA G200 AGP\n"); + is_g400 = 0; + goto card_found; + case DEVICE_MATROX_MGA_G200: + printf("[mga] Found MGA G200 PCI\n"); + is_g400 = 0; + goto card_found; + } + } + } + + if (is_g400 == -1) + { + printf("[mga] No supported cards found\n"); + return(ENXIO); + } + +card_found: + probed = 1; + memcpy(&pci_info, &lst[i], sizeof(pciinfo_t)); + + mga_cap.device_id = pci_info.device; /* set device id in capabilites */ + + return(0); +} + +int vixInit(void) +{ + unsigned int card_option = 0; + int err; + printf("[mga] init\n"); + + mga_vid_in_use = 0; + + printf("Matrox MGA G200/G400/G450 YUV Video interface v2.01 (c) Aaron Holtzman & A'rpi\n"); + + if (!probed) + { + printf("[mga] driver was not probed but is being initializing\n"); + return(EINTR); + } + +#ifdef MGA_PCICONFIG_MEMDETECT + pci_config_read(pci_info.bus, pci_info.card, pci_info.func, + 0x40, 4, &card_option); + printf("[mga] OPTION word: 0x%08X mem: 0x%02X %s\n", card_option, + (card_option>>10)&0x17, ((card_option>>14)&1)?"SGRAM":"SDRAM"); +#endif + +// temp = (card_option >> 10) & 0x17; + + if (mga_ram_size) + { + printf("[mga] RAMSIZE forced to %d MB\n", mga_ram_size); + } + else + { +#ifdef MGA_MEMORY_SIZE + mga_ram_size = MGA_MEMORY_SIZE; + printf("[mga] hard-coded RAMSIZE is %d MB\n", (unsigned int) mga_ram_size); +#else + if (is_g400) + { + switch((card_option>>10)&0x17) + { + // SDRAM: + case 0x00: + case 0x04: mga_ram_size = 16; break; + case 0x03: mga_ram_size = 32; break; + // SGRAM: + case 0x10: + case 0x14: mga_ram_size = 32; break; + case 0x11: + case 0x12: mga_ram_size = 16; break; + default: + mga_ram_size = 16; + printf("[mga] Couldn't detect RAMSIZE, assuming 16MB!\n"); + } + } + else + { + switch((card_option>>10)&0x17) + { +// case 0x10: +// case 0x13: mga_ram_size = 8; break; + default: mga_ram_size = 8; + } + } + +#if 0 +// printf("List resources -----------\n"); + for(temp=0;tempresource[temp]; + if(res->flags){ + int size=(1+res->end-res->start)>>20; + printf("res %d: start: 0x%X end: 0x%X (%d MB) flags=0x%X\n",temp,res->start,res->end,size,res->flags); + if(res->flags&(IORESOURCE_MEM|IORESOURCE_PREFETCH)){ + if(size>mga_ram_size && size<=64) mga_ram_size=size; + } + } + } +#endif + + printf("[mga] detected RAMSIZE is %d MB\n", (unsigned int) mga_ram_size); +#endif + } + + if (mga_ram_size) + { + if ((mga_ram_size < 4) || (mga_ram_size > 64)) + { + printf("[mga] invalid RAMSIZE: %d MB\n", mga_ram_size); + return(EINVAL); + } + } + + printf("[mga] hardware addresses: mmio: %p, framebuffer: %p\n", + pci_info.base1, pci_info.base0); + + mga_mmio_base = map_phys_mem(pci_info.base1,0x4000); + mga_mem_base = map_phys_mem(pci_info.base0,mga_ram_size*1024*1024); + + printf("[mga] MMIO at %p, IRQ: %d, framebuffer: %p\n", + mga_mmio_base, mga_irq, mga_mem_base); + err = mtrr_set_type(pci_info.base0,mga_ram_size*1024*1024,MTRR_TYPE_WRCOMB); + if(!err) printf("[mga] Set write-combining type of video memory\n"); +#ifdef MGA_ALLOW_IRQ + if (mga_irq != -1) + { + int tmp = request_irq(mga_irq, mga_handle_irq, SA_INTERRUPT | SA_SHIRQ, "Syncfb Time Base", &mga_irq); + if (tmp) + { + printf("syncfb (mga): cannot register irq %d (Err: %d)\n", mga_irq, tmp); + mga_irq=-1; + } + else + { + printf("syncfb (mga): registered irq %d\n", mga_irq); + } + } + else + { + printf("syncfb (mga): No valid irq was found\n"); + mga_irq=-1; + } +#else + printf("syncfb (mga): IRQ disabled in mga_vid.c\n"); + mga_irq=-1; +#endif + + return(0); +} + +void vixDestroy(void) +{ + printf("[mga] destroy\n"); + + vid_src_ready = 0; + regs.besctl &= ~1; + regs.besglobctl &= ~(1<<6); // UYVY format selected +// mga_config.colkey_on=0; //!!! + mga_vid_write_regs(1); + mga_vid_in_use = 0; + +#ifdef MGA_ALLOW_IRQ + if (mga_irq != -1) + free_irq(mga_irq, &mga_irq); +#endif + + if (mga_mmio_base) + unmap_phys_mem(mga_mmio_base, 0x4000); + if (mga_mem_base) + unmap_phys_mem(mga_mem_base, mga_ram_size); + + /* FIXME turn off BES */ + + return; +} + +int vixQueryFourcc(vidix_fourcc_t *to) +{ + printf("[mga] query fourcc (%x)\n", to->fourcc); + + switch(to->fourcc) + { + case IMGFMT_YV12: + case IMGFMT_IYUV: + case IMGFMT_I420: + case IMGFMT_YUY2: + case IMGFMT_UYVY: + break; + default: + to->depth = to->flags = 0; + return(ENOTSUP); + } + + to->depth = VID_DEPTH_12BPP | + VID_DEPTH_15BPP | VID_DEPTH_16BPP | + VID_DEPTH_24BPP | VID_DEPTH_32BPP; + to->flags = VID_CAP_EXPAND | VID_CAP_SHRINK | VID_CAP_COLORKEY; + return(0); +} + +unsigned int vixGetVersion(void) +{ + return(VIDIX_VERSION); +} + +int vixGetCapability(vidix_capability_t *to) +{ + memcpy(to, &mga_cap, sizeof(vidix_capability_t)); + return(0); +} + +int vixGetGrKeys(vidix_grkey_t *grkey) +{ + memcpy(grkey, &mga_grkey, sizeof(vidix_grkey_t)); + return(0); +} + +int vixSetGrKeys(const vidix_grkey_t *grkey) +{ + memcpy(&mga_grkey, grkey, sizeof(vidix_grkey_t)); + return(0); +} + +#ifdef MGA_EQUALIZER +static vidix_video_eq_t equal = +{ + VEQ_CAP_BRIGHTNESS | VEQ_CAP_CONTRAST, + 0, 0, 0, 0, 0, 0, 0, 0 }; +int vixPlaybackSetEq( const vidix_video_eq_t * eq) +{ + uint32_t beslumactl; + int brightness,contrast; + + /* contrast and brightness control isn't supported with G200, + don't enable c/b control and set values, just return error -- alex */ + if (!is_g400) + { + if (mga_verbose > 1) + printf("[mga] equalizer isn't supported with G200\n"); + return ENOSYS; + } + + if(eq->cap & VEQ_CAP_BRIGHTNESS) equal.brightness = eq->brightness; + if(eq->cap & VEQ_CAP_CONTRAST) equal.contrast = eq->contrast; + equal.flags = eq->flags; + + //Enable contrast and brightness control + writel(readl(mga_mmio_base + BESGLOBCTL) & ~((1<<5) + (1<<7)),mga_mmio_base + BESGLOBCTL); + brightness = (equal.brightness * 128) / 1000; + if(brightness < -128) brightness = -128; + if(brightness > 127) brightness = 127; + contrast = ((equal.contrast + 1000) * 128) / 1000; + if(contrast < 0) contrast = 0; + if(contrast > 255) contrast = 255; + beslumactl = ((brightness & 0xff) << 16) | (contrast & 0xff); + + writel(beslumactl,mga_mmio_base + BESLUMACTL); + return 0; +} + +int vixPlaybackGetEq( vidix_video_eq_t * eq) +{ + memcpy(eq,&equal,sizeof(vidix_video_eq_t)); + return 0; +} +#endif diff --git a/src/video_out/vidix/drivers/nvidia.h b/src/video_out/vidix/drivers/nvidia.h new file mode 100644 index 000000000..f19e9a634 --- /dev/null +++ b/src/video_out/vidix/drivers/nvidia.h @@ -0,0 +1,55 @@ +#include + +#define RIVA_FIFO_FREE(hwptr, cnt) \ +{ \ + while (nv_fifo_space < (cnt)) { \ + nv_fifo_space = hwptr->fifo_free >> 2; \ + } \ + nv_fifo_space -= (cnt); \ +} + +typedef struct { + uint32_t reserved00[4]; + uint16_t fifo_free; + uint16_t nop[1]; + uint32_t reserved01[0x03b]; + + uint32_t no_operation; + uint32_t notify; + uint32_t reserved02[0x01e]; + uint32_t set_context_dma_notifies; + uint32_t set_context_dma_image; + uint32_t set_context_pattern; + uint32_t set_context_rop; + uint32_t set_context_beta1; + uint32_t set_context_surface; + uint32_t reserved03[0x05a]; + uint32_t set_color_format; + uint32_t set_operation; + int16_t clip_x; + int16_t clip_y; + uint16_t clip_height; + uint16_t clip_width; + int16_t image_out_x; + int16_t image_out_y; + uint16_t image_out_height; + uint16_t image_out_width; + uint32_t du_dx; + uint32_t du_dy; + uint32_t reserved04[0x38]; + uint16_t image_in_height; + uint16_t image_in_width; + uint32_t image_in_format; + uint32_t image_in_offset; + uint32_t image_in_point; + uint32_t reserved05[0x6fc]; +} RivaScaledImage; + +#define dump_scaledimage(x) { \ + printf("clip: pos: %dx%d, size: %dx%d\n", \ + x->clip_x, x->clip_y, x->clip_height, x->clip_width); \ + printf("image_out: pos: %dx%d, size: %dx%d\n", \ + x->image_out_x, x->image_out_y, x->image_out_height, x->image_out_width); \ + printf("image_in: size: %dx%d format: %x offset: %x\n", \ + x->image_in_height, x->image_in_width, x->image_in_format, x->image_in_offset); \ +} diff --git a/src/video_out/vidix/drivers/nvidia_vid.c b/src/video_out/vidix/drivers/nvidia_vid.c new file mode 100644 index 000000000..941011256 --- /dev/null +++ b/src/video_out/vidix/drivers/nvidia_vid.c @@ -0,0 +1,326 @@ +#include +#include +#include +#include +#include +#include + +#include "../vidix.h" +#include "../fourcc.h" +#include "../../libdha/libdha.h" +#include "../../libdha/pci_ids.h" +#include "../../libdha/pci_names.h" + +#include "nvidia.h" + +static void *ctrl_base = 0; +static void *fb_base = 0; +static int32_t overlay_offset = 0; +static uint32_t ram_size = 0; + +static unsigned int *PFB; +static unsigned int *PCIO; +static unsigned int *PGRAPH; +static unsigned int *PRAMIN; +static unsigned int *FIFO; +static unsigned int *PMC; + +typedef unsigned char U008; + +#define NV_WR08(p,i,d) (((U008 *)(p))[i]=(d)) + +unsigned int nv_fifo_space = 0; + +void CRTCout(unsigned char index, unsigned char val) +{ + NV_WR08(PCIO, 0x3d4, index); + NV_WR08(PCIO, 0x3d5, val); +} + +volatile RivaScaledImage *ScaledImage; + +#define CARD_FLAGS_NONE 0x00 +#define CARD_FLAGS_NOTSUPPORTED 0x01 + +struct nv_card_id_s +{ + const unsigned int id ; + const char name[32]; + const int core; + const int flags; +}; + +static const struct nv_card_id_s nv_card_id; + +static const struct nv_card_id_s nv_card_ids[]= +{ + { DEVICE_NVIDIA_RIVA_TNT2_NV5, "nVidia TNT2 (NV5) ", 5, CARD_FLAGS_NOTSUPPORTED}, + { DEVICE_NVIDIA_VANTA_NV6, "nVidia Vanta (NV6.1)", 6, CARD_FLAGS_NOTSUPPORTED}, + { DEVICE_NVIDIA_VANTA_NV62, "nVidia Vanta (NV6.2)", 6, CARD_FLAGS_NOTSUPPORTED} +}; + +static int find_chip(unsigned int chip_id) +{ + unsigned int i; + + for (i = 0; i < sizeof(nv_card_ids)/sizeof(struct nv_card_id_s); i++) + if (chip_id == nv_card_ids[i].id) + return(i); + return(-1); +} + +static pciinfo_t pci_info; +static int probed = 0; + +/* VIDIX exports */ + +static vidix_capability_t nvidia_cap = +{ + "NVIDIA driver for VIDIX", + "alex", + TYPE_OUTPUT, + { 0, 0, 0, 0 }, + 2046, + 2047, + 4, + 4, + -1, + FLAG_NONE, + VENDOR_NVIDIA, + 0, + { 0, 0, 0, 0 } +}; + +unsigned int vixGetVersion(void) +{ + return(VIDIX_VERSION); +} + +int vixProbe(int verbose,int force) +{ + pciinfo_t lst[MAX_PCI_DEVICES]; + unsigned int i, num_pci; + int err; + + printf("[nvidia] probe\n"); + + err = pci_scan(lst, &num_pci); + if (err) + { + printf("Error occured during pci scan: %s\n", strerror(err)); + return err; + } + else + { + err = ENXIO; + + for (i = 0; i < num_pci; i++) + { + if (lst[i].vendor == VENDOR_NVIDIA) + { + int idx; + + idx = find_chip(lst[i].device); + if (idx == -1) + continue; + if (nv_card_ids[idx].flags & CARD_FLAGS_NOTSUPPORTED) + { + printf("Found chip: %s, but not supported!\n", + nv_card_ids[idx].name); + continue; + } + else + + printf("Found chip: %s\n", nv_card_ids[idx].name); + + memcpy(&nv_card_id, &nv_card_ids[idx], sizeof(struct nv_card_id_s)); + nvidia_cap.device_id = nv_card_ids[idx].id; + err = 0; + memcpy(&pci_info, &lst[i], sizeof(pciinfo_t)); + probed = 1; + + printf("bus:card:func = %x:%x:%x\n", + pci_info.bus, pci_info.card, pci_info.func); + printf("vendor:device = %x:%x\n", + pci_info.vendor, pci_info.device); + printf("base0:base1:base2:baserom = %x:%x:%x:%x\n", + pci_info.base0, pci_info.base1, pci_info.base2, + pci_info.baserom); + break; + } + } + } + + if (err) + printf("No chip found\n"); + return(err); +} + +int vixInit(void) +{ + int card_option; + + printf("[nvidia] init\n"); + + pci_config_read(pci_info.bus, pci_info.card, pci_info.func, 0x40, + 4, &card_option); + printf("card_option: %x\n", card_option); + + if (!probed) + { + printf("Driver was not probed but is being initialized\n"); + return(EINTR); + } + + ctrl_base = map_phys_mem(pci_info.base0, 0x00800000); + if (ctrl_base == (void *)-1) + return(ENOMEM); + fb_base = map_phys_mem(pci_info.base1, 0x01000000); + if (fb_base == (void *)-1) + return(ENOMEM); + + printf("ctrl_base: %p, fb_base: %p\n", ctrl_base, fb_base); + + PFB = ctrl_base+0x00100000; + PGRAPH = ctrl_base+0x00400000; + PRAMIN = ctrl_base+0x00710000; + FIFO = ctrl_base+0x00800000; + PCIO = ctrl_base+0x00601000; + PMC = ctrl_base+0x00000000; + printf("pfb: %p, pgraph: %p, pramin: %p, fifo: %p, pcio: %p\n", + PFB, PGRAPH, PRAMIN, FIFO, PCIO); + + ScaledImage = FIFO+0x8000/4; + printf("ScaledImage: %p\n", ScaledImage); + + /* unlock */ + CRTCout(0x11, 0xff); + + printf("fifo_free: %d\n", ScaledImage->fifo_free); + + RIVA_FIFO_FREE(ScaledImage, 10); + + dump_scaledimage(ScaledImage); + + /* create scaled image object */ + *(PRAMIN+0x518) = 0x0100A037; + *(PRAMIN+0x519) = 0x00000C02; + + /* put scaled image object into subchannel */ + *(FIFO+0x2000) = 0x80000011; + + /* ram size detection */ + switch(nv_card_id.core) + { + case 5: + { + if (*(PFB+0x0) & 0x00000100) + { + printf("first ver\n"); + ram_size = ((*(PFB+0x0) >> 12) & 0x0f) * 1024 * 2 + 1024 * 2; + } + else + { + printf("second ver (code: %d)\n", + *(PFB+0x0) & 0x00000003); + switch(*(PFB+0x0) & 0x00000003) + { + case 0: + ram_size = 1024*32; + break; + case 1: + ram_size = 1024*4; + break; + case 2: + ram_size = 1024*8; + break; + case 3: + ram_size = 1024*16; + break; + default: + printf("Unknown ram size code: %d\n", + *(PFB+0x0) & 0x00000003); + break; + } + } + break; + } + default: + printf("Unknown core: %d\n", nv_card_id.core); + } + + printf("ram_size: %d\n", ram_size); + return 0; +} + +void vixDestroy(void) +{ + printf("[nvidia] destory\n"); +} + +int vixGetCapability(vidix_capability_t *to) +{ + memcpy(to, &nvidia_cap, sizeof(vidix_capability_t)); + return(0); +} + +int vixQueryFourcc(vidix_fourcc_t *to) +{ + printf("[nvidia] query fourcc (%x)\n", to->fourcc); + to->flags = 0; + to->depth = VID_DEPTH_32BPP; + return 0; +} + +int vixConfigPlayback(vidix_playback_t *info) +{ + int fb_pixel_size = 32/8; + int fb_line_len = 1280*4; + char buffer = 0; + int offset = 0; + int x,y,h,w; + int bpp = 32 >> 3; + int size; + + printf("[nvidia] config playback\n"); + + x = info->src.x; + y = info->src.y; + h = info->src.h; + w = info->src.w; + + w = (w + 1) & ~1; + + size = h * (((w << 1) + 63) & ~63) / bpp; + + + PMC[(0x8900/4)+buffer] = offset; + PMC[(0x8928/4)+buffer] = (h << 16) | w; + PMC[(0x8930/4)+buffer] = ((y << 4) & 0xffff0000) | (x >> 12); + PMC[(0x8938/4)+buffer] = (w << 20) / info->dest.w; + PMC[(0x8938/4)+buffer] = (h << 20) / info->dest.h; + + info->dga_addr = fb_base + (info->dest.w - info->src.w) * fb_pixel_size / + 2 + (info->dest.h - info->src.h) * fb_line_len / 2; + + info->num_frames = 1; + info->frame_size = info->src.w*info->src.h+(info->src.w*info->src.h)/2; + info->offsets[0] = 0; + info->offset.y = 0; + info->offset.v = ((info->src.w + 31) & ~31) * info->src.h; + info->offset.u = info->offset.v+((info->src.w + 31) & ~31) * info->src.h / 4; +// info->dga_addr = malloc(info->num_frames*info->frame_size); + return 0; +} + +int vixPlaybackOn(void) +{ + printf("[nvidia] playback on\n"); + return 0; +} + +int vixPlaybackOff(void) +{ + printf("[nvidia] playback off\n"); + return 0; +} diff --git a/src/video_out/vidix/drivers/pm3_regs.h b/src/video_out/vidix/drivers/pm3_regs.h new file mode 100644 index 000000000..c976c3210 --- /dev/null +++ b/src/video_out/vidix/drivers/pm3_regs.h @@ -0,0 +1,1113 @@ +/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/glint/pm3_regs.h,v 1.9 2001/11/20 00:09:15 alanh Exp $ */ + +/* + * glint register file + * + * Copyright by Sven Luther + * Authors: Sven Luther, + * Thomas Witzel, + * + * this work is sponsored by Appian Graphics. + * + */ + +#ifndef _PM3_REG_H_ +#define _PM3_REG_H_ + +/********************************************** +* GLINT Permedia3 Control Status registers * +***********************************************/ +/* Control Status Registers */ +#define PM3ResetStatus 0x0000 +#define PM3IntEnable 0x0008 +#define PM3IntFlags 0x0010 +#define PM3InFIFOSpace 0x0018 +#define PM3OutFIFOWords 0x0020 +#define PM3DMAAddress 0x0028 +#define PM3DMACount 0x0030 +#define PM3ErrorFlags 0x0038 +#define PM3VClkCtl 0x0040 +#define PM3TestRegister 0x0048 +#define PM3Aperture0 0x0050 +#define PM3Aperture1 0x0058 +#define PM3DMAControl 0x0060 +#define PM3FIFODis 0x0068 +#define PM3ChipConfig 0x0070 +#define PM3AGPControl 0x0078 + +#define PM3GPOutDMAAddress 0x0080 +#define PM3PCIFeedbackCount 0x0088 +#define PM3PCIAbortStatus 0x0090 +#define PM3PCIAbortAddress 0x0098 + +#define PM3PCIPLLStatus 0x00f0 + +#define PM3HostTextureAddress 0x0100 +#define PM3TextureDownloadControl 0x0108 +#define PM3TextureOperation 0x0110 +#define PM3LogicalTexturePage 0x0118 +#define PM3TexDMAAddress 0x0120 +#define PM3TexFIFOSpace 0x0128 + +/********************************************** +* GLINT Permedia3 Region 0 Bypass Controls * +***********************************************/ +#define PM3ByAperture1Mode 0x0300 + #define PM3ByApertureMode_BYTESWAP_ABCD (0<<0) + #define PM3ByApertureMode_BYTESWAP_BADC (1<<0) + #define PM3ByApertureMode_BYTESWAP_CDAB (2<<0) + #define PM3ByApertureMode_BYTESWAP_DCBA (3<<0) + #define PM3ByApertureMode_PATCH_DISABLE (0<<2) + #define PM3ByApertureMode_PATCH_ENABLE (1<<2) + #define PM3ByApertureMode_FORMAT_RAW (0<<3) + #define PM3ByApertureMode_FORMAT_YUYV (1<<3) + #define PM3ByApertureMode_FORMAT_UYVY (2<<3) + #define PM3ByApertureMode_PIXELSIZE_8BIT (0<<5) + #define PM3ByApertureMode_PIXELSIZE_16BIT (1<<5) + #define PM3ByApertureMode_PIXELSIZE_32BIT (2<<5) + #define PM3ByApertureMode_EFFECTIVE_STRIDE_1024 (0<<7) + #define PM3ByApertureMode_EFFECTIVE_STRIDE_2048 (1<<7) + #define PM3ByApertureMode_EFFECTIVE_STRIDE_4096 (2<<7) + #define PM3ByApertureMode_EFFECTIVE_STRIDE_8192 (3<<7) + #define PM3ByApertureMode_PATCH_OFFSET_X(off) (((off)&7f)<<9) + #define PM3ByApertureMode_PATCH_OFFSET_Y(off) (((off)&7f)<<16) + #define PM3ByApertureMode_FRAMEBUFFER (0<<21) + #define PM3ByApertureMode_LOCALBUFFER (1<<21) + #define PM3ByApertureMode_DOUBLE_WRITE_OFF (0<<22) + #define PM3ByApertureMode_DOUBLE_WRITE_1MB (1<<22) + #define PM3ByApertureMode_DOUBLE_WRITE_2MB (2<<22) + #define PM3ByApertureMode_DOUBLE_WRITE_4MB (3<<22) + #define PM3ByApertureMode_DOUBLE_WRITE_8MB (4<<22) + #define PM3ByApertureMode_DOUBLE_WRITE_16MB (5<<22) + #define PM3ByApertureMode_DOUBLE_WRITE_32MB (6<<22) + +#define PM3ByAperture2Mode 0x0328 + +/********************************************** +* GLINT Permedia3 Memory Control (0x1000) * +***********************************************/ +#define PM3MemCounter 0x1000 +#define PM3MemBypassWriteMask 0x1008 +#define PM3MemScratch 0x1010 +#define PM3LocalMemCaps 0x1018 + #define PM3LocalMemCaps_NoWriteMask (1<<28) +#define PM3LocalMemTimings 0x1020 +#define PM3LocalMemControl 0x1028 +#define PM3LocalMemRefresh 0x1030 +#define PM3LocalMemPowerDown 0x1038 +#define PM3RemoteMemControl 0x1100 + +/********************************************** +* GLINT Permedia3 Video Control (0x3000) * +***********************************************/ + +#define PM3ScreenBase 0x3000 +#define PM3ScreenStride 0x3008 +#define PM3HTotal 0x3010 +#define PM3HgEnd 0x3018 +#define PM3HbEnd 0x3020 +#define PM3HsStart 0x3028 +#define PM3HsEnd 0x3030 +#define PM3VTotal 0x3038 +#define PM3VbEnd 0x3040 +#define PM3VsStart 0x3048 +#define PM3VsEnd 0x3050 +#define PM3VideoControl 0x3058 + #define PM3VideoControl_DISABLE (0<<0) + #define PM3VideoControl_ENABLE (1<<0) + #define PM3VideoControl_BLANK_ACTIVE_HIGH (0<<1) + #define PM3VideoControl_BLANK_ACTIVE_LOW (1<<1) + #define PM3VideoControl_LINE_DOUBLE_OFF (0<<2) + #define PM3VideoControl_LINE_DOUBLE_ON (1<<2) + #define PM3VideoControl_HSYNC_FORCE_HIGH (0<<3) + #define PM3VideoControl_HSYNC_ACTIVE_HIGH (1<<3) + #define PM3VideoControl_HSYNC_FORCE_LOW (2<<3) + #define PM3VideoControl_HSYNC_ACTIVE_LOW (3<<3) + #define PM3VideoControl_VSYNC_FORCE_HIGH (0<<5) + #define PM3VideoControl_VSYNC_ACTIVE_HIGH (1<<5) + #define PM3VideoControl_VSYNC_FORCE_LOW (2<<5) + #define PM3VideoControl_VSYNC_ACTIVE_LOW (3<<5) + #define PM3VideoControl_BYTE_DOUBLE_OFF (0<<7) + #define PM3VideoControl_BYTE_DOUBLE_ON (1<<7) + #define PM3VideoControl_BUFFER_SWAP_SYNCON_FRAMEBLANK (0<<9) + #define PM3VideoControl_BUFFER_SWAP_FREE_RUNNING (1<<9) + #define PM3VideoControl_BUFFER_SWAP_LIMITETO_FRAMERATE (2<<9) + #define PM3VideoControl_STEREO_DISABLE (0<<11) + #define PM3VideoControl_STEREO_ENABLE (1<<11) + #define PM3VideoControl_RIGHT_EYE_ACTIVE_HIGH (0<<12) + #define PM3VideoControl_RIGHT_EYE_ACTIVE_LOW (1<<12) + #define PM3VideoControl_VIDEO_EXT_LOW (0<<14) + #define PM3VideoControl_VIDEO_EXT_HIGH (1<<14) + #define PM3VideoControl_SYNC_MODE_INDEPENDENT (0<<16) + #define PM3VideoControl_SYNC_MODE_SYNCTO_VSA (1<<16) + #define PM3VideoControl_SYNC_MODE_SYNCTO_VSB (2<<16) + #define PM3VideoControl_PATCH_DISABLE (0<<18) + #define PM3VideoControl_PATCH_ENABLE (1<<18) + #define PM3VideoControl_PIXELSIZE_8BIT (0<<19) + #define PM3VideoControl_PIXELSIZE_16BIT (1<<19) + #define PM3VideoControl_PIXELSIZE_32BIT (2<<19) + #define PM3VideoControl_DISPLAY_DISABLE (0<<21) + #define PM3VideoControl_DISPLAY_ENABLE (1<<21) + #define PM3VideoControl_PATCH_OFFSET_X(off) (((off)&0x3f)<<22) + #define PM3VideoControl_PATCH_OFFSET_Y(off) (((off)&0x3f)<<28) +#define PM3InterruptLine 0x3060 +#define PM3DisplayData 0x3068 +#define PM3VerticalLineCount 0x3070 +#define PM3FifoControl 0x3078 +#define PM3ScreenBaseRight 0x3080 +#define PM3MiscControl 0x3088 + +#define PM3VideoOverlayUpdate 0x3100 + #define PM3VideoOverlayUpdate_DISABLE (0<<0) + #define PM3VideoOverlayUpdate_ENABLE (1<<0) +#define PM3VideoOverlayMode 0x3108 + #define PM3VideoOverlayMode_DISABLE (0<<0) + #define PM3VideoOverlayMode_ENABLE (1<<0) + #define PM3VideoOverlayMode_BUFFERSYNC_MANUAL (0<<1) + #define PM3VideoOverlayMode_BUFFERSYNC_VIDEOSTREAMA (1<<1) + #define PM3VideoOverlayMode_BUFFERSYNC_VIDEOSTREAMB (2<<1) + #define PM3VideoOverlayMode_FIELDPOLARITY_NORMAL (0<<4) + #define PM3VideoOverlayMode_FIELDPOLARITY_INVERT (1<<4) + #define PM3VideoOverlayMode_PIXELSIZE_8BIT (0<<5) + #define PM3VideoOverlayMode_PIXELSIZE_16BIT (1<<5) + #define PM3VideoOverlayMode_PIXELSIZE_32BIT (2<<5) + #define PM3VideoOverlayMode_COLORFORMAT_RGB8888 ((0<<7)|(1<<12)|(2<<5)) + #define PM3VideoOverlayMode_COLORFORMAT_RGB4444 ((1<<7)|(1<<12)|(1<<5)) + #define PM3VideoOverlayMode_COLORFORMAT_RGB5551 ((2<<7)|(1<<12)|(1<<5)) + #define PM3VideoOverlayMode_COLORFORMAT_RGB565 ((3<<7)|(1<<12)|(1<<5)) + #define PM3VideoOverlayMode_COLORFORMAT_RGB332 ((4<<7)|(1<<12)|(0<<5)) + #define PM3VideoOverlayMode_COLORFORMAT_BGR8888 ((0<<7)|(2<<5)) + #define PM3VideoOverlayMode_COLORFORMAT_BGR4444 ((1<<7)|(1<<5)) + #define PM3VideoOverlayMode_COLORFORMAT_BGR5551 ((2<<7)|(1<<5)) + #define PM3VideoOverlayMode_COLORFORMAT_BGR565 ((3<<7)|(1<<5)) + #define PM3VideoOverlayMode_COLORFORMAT_BGR332 ((4<<7)|(0<<5)) + #define PM3VideoOverlayMode_COLORFORMAT_CI8 ((5<<7)|(1<<12)|(0<<5)) + #define PM3VideoOverlayMode_COLORFORMAT_VUY444 ((2<<10)|(1<<12)|(2<<5)) + #define PM3VideoOverlayMode_COLORFORMAT_YUV444 ((2<<10)|(2<<5)) + #define PM3VideoOverlayMode_COLORFORMAT_VUY422 ((1<<10)|(1<<12)|(1<<5)) + #define PM3VideoOverlayMode_COLORFORMAT_YUV422 ((1<<10)|(1<<5)) + #define PM3VideoOverlayMode_COLORORDER_BGR (0<<12) + #define PM3VideoOverlayMode_COLORORDER_RGB (1<<12) + #define PM3VideoOverlayMode_LINEARCOLOREXT_OFF (0<<13) + #define PM3VideoOverlayMode_LINEARCOLOREXT_ON (1<<13) + #define PM3VideoOverlayMode_FILTER_MASK (3<<14) + #define PM3VideoOverlayMode_FILTER_OFF (0<<14) + #define PM3VideoOverlayMode_FILTER_FULL (1<<14) + #define PM3VideoOverlayMode_FILTER_PARTIAL (2<<14) + #define PM3VideoOverlayMode_DEINTERLACE_OFF (0<<16) + #define PM3VideoOverlayMode_DEINTERLACE_BOB (1<<16) + #define PM3VideoOverlayMode_PATCHMODE_OFF (0<<18) + #define PM3VideoOverlayMode_PATCHMODE_ON (1<<18) + #define PM3VideoOverlayMode_FLIP_VIDEO (0<<20) + #define PM3VideoOverlayMode_FLIP_VIDEOSTREAMA (1<<20) + #define PM3VideoOverlayMode_FLIP_VIDEOSTREAMB (2<<20) + #define PM3VideoOverlayMode_MIRROR_MASK (3<<23) + #define PM3VideoOverlayMode_MIRRORX_OFF (0<<23) + #define PM3VideoOverlayMode_MIRRORX_ON (1<<23) + #define PM3VideoOverlayMode_MIRRORY_OFF (0<<24) + #define PM3VideoOverlayMode_MIRRORY_ON (1<<24) +#define PM3VideoOverlayFifoControl 0x3110 +#define PM3VideoOverlayIndex 0x3118 +#define PM3VideoOverlayBase 0x3120 +#define PM3VideoOverlayBase0 0x3120 +#define PM3VideoOverlayBase1 0x3128 +#define PM3VideoOverlayBase2 0x3130 +#define PM3VideoOverlayStride 0x3138 + #define PM3VideoOverlayStride_STRIDE(s) (((s)&0xfff)<<0) +#define PM3VideoOverlayWidth 0x3140 + #define PM3VideoOverlayWidth_WIDTH(w) (((w)&0xfff)<<0) +#define PM3VideoOverlayHeight 0x3148 + #define PM3VideoOverlayHeight_HEIGHT(h) (((h)&0xfff)<<0) +#define PM3VideoOverlayOrigin 0x3150 + #define PM3VideoOverlayOrigin_XORIGIN(x) (((x)&0xfff)<<0) + #define PM3VideoOverlayOrigin_YORIGIN(y) (((y)&0xfff)<<16) +#define PM3VideoOverlayShrinkXDelta 0x3158 + #define PM3VideoOverlayShrinkXDelta_NONE (1<<16) + #define PM3VideoOverlayShrinkXDelta_DELTA(s,d) \ + ((((s)<<16)/(d))&0x0ffffff0) +#define PM3VideoOverlayZoomXDelta 0x3160 + #define PM3VideoOverlayZoomXDelta_NONE (1<<16) + #define PM3VideoOverlayZoomXDelta_DELTA(s,d) \ + ((((s)<<16)/(d))&0x0001fff0) +#define PM3VideoOverlayYDelta 0x3168 + #define PM3VideoOverlayYDelta_NONE (1<<16) + #define PM3VideoOverlayYDelta_DELTA(s,d) \ + ((((s)<<16)/(d))&0x0ffffff0) +#define PM3VideoOverlayFieldOffset 0x3170 +#define PM3VideoOverlayStatus 0x3178 + +/********************************************** +* GLINT Permedia3 RAMDAC Registers (0x4000) * +***********************************************/ +/* Direct Registers */ +#define PM3RD_PaletteWriteAddress 0x4000 +#define PM3RD_PaletteData 0x4008 +#define PM3RD_PixelMask 0x4010 +#define PM3RD_PaletteReadAddress 0x4018 + +#define PM3RD_IndexLow 0x4020 +#define PM3RD_IndexHigh 0x4028 +#define PM3RD_IndexedData 0x4030 +#define PM3RD_IndexControl 0x4038 + #define PM3RD_IndexControl_AUTOINCREMENT_ENABLE (1<<0) + #define PM3RD_IndexControl_AUTOINCREMENT_DISABLE (0<<0) + +/* Indirect Registers */ +#define PM3RD_MiscControl 0x000 + #define PM3RD_MiscControl_HIGHCOLOR_RES_DISABLE (0<<0) + #define PM3RD_MiscControl_HIGHCOLOR_RES_ENABLE (1<<0) + #define PM3RD_MiscControl_PIXELDOUBLE_DISABLE (0<<1) + #define PM3RD_MiscControl_PIXELDOUBLE_ENABLE (1<<1) + #define PM3RD_MiscControl_LASTREAD_ADDR_DISABLE (0<<2) + #define PM3RD_MiscControl_LASTREAD_ADDR_ENABLE (1<<2) + #define PM3RD_MiscControl_DIRECTCOLOR_DISABLE (0<<3) + #define PM3RD_MiscControl_DIRECTCOLOR_ENABLE (1<<3) + #define PM3RD_MiscControl_OVERLAY_DISABLE (0<<4) + #define PM3RD_MiscControl_OVERLAY_ENABLE (1<<4) + #define PM3RD_MiscControl_PIXELDOUBLE_BUFFER_DISABLE (0<<5) + #define PM3RD_MiscControl_PIXELDOUBLE_BUFFER_ENABLE (1<<5) + #define PM3RD_MiscControl_VSB_OUTPUT_DISABLE (0<<6) + #define PM3RD_MiscControl_VSB_OUTPUT_ENABLE (1<<6) + #define PM3RD_MiscControl_STEREODOUBLE_BUFFER_DISABLE (0<<7) + #define PM3RD_MiscControl_STEREODOUBLE_BUFFER_ENABLE (1<<7) +#define PM3RD_SyncControl 0x001 + #define PM3RD_SyncControl_HSYNC_ACTIVE_LOW (0<<0) + #define PM3RD_SyncControl_HSYNC_ACTIVE_HIGH (1<<0) + #define PM3RD_SyncControl_HSYNC_FORCE_ACTIVE (3<<0) + #define PM3RD_SyncControl_HSYNC_FORCE_INACTIVE (4<<0) + #define PM3RD_SyncControl_HSYNC_TRI_STATE (2<<0) + #define PM3RD_SyncControl_VSYNC_ACTIVE_LOW (0<<3) + #define PM3RD_SyncControl_VSYNC_ACTIVE_HIGH (1<<3) + #define PM3RD_SyncControl_VSYNC_TRI_STATE (2<<3) + #define PM3RD_SyncControl_VSYNC_FORCE_ACTIVE (3<<3) + #define PM3RD_SyncControl_VSYNC_FORCE_INACTIVE (4<<3) + #define PM3RD_SyncControl_HSYNC_OVERRIDE_SETBY_HSYNC (0<<6) + #define PM3RD_SyncControl_HSYNC_OVERRIDE_FORCE_HIGH (1<<6) + #define PM3RD_SyncControl_VSYNC_OVERRIDE_SETBY_VSYNC (0<<7) + #define PM3RD_SyncControl_VSYNC_OVERRIDE_FORCE_HIGH (1<<7) +#define PM3RD_DACControl 0x002 + #define PM3RD_DACControl_DAC_POWER_ON (0<<0) + #define PM3RD_DACControl_DAC_POWER_OFF (1<<0) + #define PM3RD_DACControl_SYNC_ON_GREEN_DISABLE (0<<3) + #define PM3RD_DACControl_SYNC_ON_GREEN_ENABLE (1<<3) + #define PM3RD_DACControl_BLANK_RED_DAC_DISABLE (0<<4) + #define PM3RD_DACControl_BLANK_RED_DAC_ENABLE (1<<4) + #define PM3RD_DACControl_BLANK_GREEN_DAC_DISABLE (0<<5) + #define PM3RD_DACControl_BLANK_GREEN_DAC_ENABLE (1<<5) + #define PM3RD_DACControl_BLANK_BLUE_DAC_DISABLE (0<<6) + #define PM3RD_DACControl_BLANK_BLUE_DAC_ENABLE (1<<6) + #define PM3RD_DACControl_BLANK_PEDESTAL_DISABLE (0<<7) + #define PM3RD_DACControl_BLANK_PEDESTAL_ENABLE (1<<7) +#define PM3RD_PixelSize 0x003 + #define PM3RD_PixelSize_24_BIT_PIXELS (4<<0) + #define PM3RD_PixelSize_32_BIT_PIXELS (2<<0) + #define PM3RD_PixelSize_16_BIT_PIXELS (1<<0) + #define PM3RD_PixelSize_8_BIT_PIXELS (0<<0) +#define PM3RD_ColorFormat 0x004 + #define PM3RD_ColorFormat_LINEAR_COLOR_EXT_ENABLE (1<<6) + #define PM3RD_ColorFormat_LINEAR_COLOR_EXT_DISABLE (0<<6) + #define PM3RD_ColorFormat_COLOR_ORDER_BLUE_LOW (1<<5) + #define PM3RD_ColorFormat_COLOR_ORDER_RED_LOW (0<<5) + #define PM3RD_ColorFormat_COLOR_FORMAT_MASK (0x1f<<0) + #define PM3RD_ColorFormat_8888_COLOR (0<<0) + #define PM3RD_ColorFormat_5551_FRONT_COLOR (1<<0) + #define PM3RD_ColorFormat_4444_COLOR (2<<0) + #define PM3RD_ColorFormat_332_FRONT_COLOR (5<<0) + #define PM3RD_ColorFormat_332_BACK_COLOR (6<<0) + #define PM3RD_ColorFormat_2321_FRONT_COLOR (9<<0) + #define PM3RD_ColorFormat_2321_BACK_COLOR (10<<0) + #define PM3RD_ColorFormat_232_FRONTOFF_COLOR (11<<0) + #define PM3RD_ColorFormat_232_BACKOFF_COLOR (12<<0) + #define PM3RD_ColorFormat_5551_BACK_COLOR (13<<0) + #define PM3RD_ColorFormat_CI8_COLOR (14<<0) + #define PM3RD_ColorFormat_565_FRONT_COLOR (16<<0) + #define PM3RD_ColorFormat_565_BACK_COLOR (17<<0) +#define PM3RD_CursorMode 0x005 + #define PM3RD_CursorMode_CURSOR_DISABLE (0<<0) + #define PM3RD_CursorMode_CURSOR_ENABLE (1<<0) + #define PM3RD_CursorMode_FORMAT_64x64_2BPE_P0123 (0<<2) + #define PM3RD_CursorMode_FORMAT_32x32_2BPE_P0 (1<<2) + #define PM3RD_CursorMode_FORMAT_32x32_2BPE_P1 (2<<2) + #define PM3RD_CursorMode_FORMAT_32x32_2BPE_P2 (3<<2) + #define PM3RD_CursorMode_FORMAT_32x32_2BPE_P3 (4<<2) + #define PM3RD_CursorMode_FORMAT_32x32_4BPE_P01 (5<<2) + #define PM3RD_CursorMode_FORMAT_32x32_4BPE_P23 (6<<2) + #define PM3RD_CursorMode_TYPE_MS (0<<4) + #define PM3RD_CursorMode_TYPE_X (1<<4) + #define PM3RD_CursorMode_REVERSE_PIXEL_ORDER_DISABLE (0<<6) + #define PM3RD_CursorMode_REVERSE_PIXEL_ORDER_ENABLE (1<<6) + #define PM3RD_CursorMode_REVERSE_PIXEL_ORDER_3_COLOR (2<<6) + #define PM3RD_CursorMode_REVERSE_PIXEL_ORDER_15_COLOR (3<<6) +#define PM3RD_CursorControl 0x006 + #define PM3RD_CursorControl_DOUBLE_X_DISABLED (0<<0) + #define PM3RD_CursorControl_DOUBLE_X_ENABLED (1<<0) + #define PM3RD_CursorControl_DOUBLE_Y_DISABLED (0<<1) + #define PM3RD_CursorControl_DOUBLE_Y_ENABLED (1<<1) + #define PM3RD_CursorControl_READBACK_POS_DISABLED (0<<2) + #define PM3RD_CursorControl_READBACK_POS_ENABLED (1<<2) + +#define PM3RD_CursorXLow 0x007 +#define PM3RD_CursorXHigh 0x008 +#define PM3RD_CursorYLow 0x009 +#define PM3RD_CursorYHigh 0x00a +#define PM3RD_CursorHotSpotX 0x00b +#define PM3RD_CursorHotSpotY 0x00c +#define PM3RD_OverlayKey 0x00d +#define PM3RD_Pan 0x00e + #define PM3RD_Pan_DISABLE (0<<0) + #define PM3RD_Pan_ENABLE (1<<0) + #define PM3RD_Pan_GATE_DISABLE (0<<1) + #define PM3RD_Pan_GATE_ENABLE (1<<1) +#define PM3RD_Sense 0x00f + +#define PM3RD_CheckControl 0x018 + #define PM3RD_CheckControl_PIXEL_DISABLED (0<<0) + #define PM3RD_CheckControl_PIXEL_ENABLED (1<<0) + #define PM3RD_CheckControl_LUT_DISABLED (0<<1) + #define PM3RD_CheckControl_LUT_ENABLED (1<<1) +#define PM3RD_CheckPixelRed 0x019 +#define PM3RD_CheckPixelGreen 0x01a +#define PM3RD_CheckPixelBlue 0x01b +#define PM3RD_CheckLUTRed 0x01c +#define PM3RD_CheckLUTGreen 0x01d +#define PM3RD_CheckLUTBlue 0x01e +#define PM3RD_Scratch 0x01f + +#define PM3RD_VideoOverlayControl 0x020 + #define PM3RD_VideoOverlayControl_DISABLE (0<<0) + #define PM3RD_VideoOverlayControl_ENABLE (1<<0) + #define PM3RD_VideoOverlayControl_MODE_MASK (3<<1) + #define PM3RD_VideoOverlayControl_MODE_MAINKEY (0<<1) + #define PM3RD_VideoOverlayControl_MODE_OVERLAYKEY (1<<1) + #define PM3RD_VideoOverlayControl_MODE_ALWAYS (2<<1) + #define PM3RD_VideoOverlayControl_MODE_BLEND (3<<1) + #define PM3RD_VideoOverlayControl_DIRECTCOLOR_DISABLED (0<<3) + #define PM3RD_VideoOverlayControl_DIRECTCOLOR_ENABLED (1<<3) + #define PM3RD_VideoOverlayControl_BLENDSRC_MAIN (0<<4) + #define PM3RD_VideoOverlayControl_BLENDSRC_REGISTER (1<<4) + #define PM3RD_VideoOverlayControl_KEY_COLOR (0<<5) + #define PM3RD_VideoOverlayControl_KEY_ALPHA (1<<5) +#define PM3RD_VideoOverlayXStartLow 0x021 +#define PM3RD_VideoOverlayXStartHigh 0x022 +#define PM3RD_VideoOverlayYStartLow 0x023 +#define PM3RD_VideoOverlayYStartHigh 0x024 +#define PM3RD_VideoOverlayXEndLow 0x025 +#define PM3RD_VideoOverlayXEndHigh 0x026 +#define PM3RD_VideoOverlayYEndLow 0x027 +#define PM3RD_VideoOverlayYEndHigh 0x028 +#define PM3RD_VideoOverlayKeyR 0x029 +#define PM3RD_VideoOverlayKeyG 0x02a +#define PM3RD_VideoOverlayKeyB 0x02b +#define PM3RD_VideoOverlayBlend 0x02c + #define PM3RD_VideoOverlayBlend_FACTOR_0_PERCENT (0<<6) + #define PM3RD_VideoOverlayBlend_FACTOR_25_PERCENT (1<<6) + #define PM3RD_VideoOverlayBlend_FACTOR_75_PERCENT (2<<6) + #define PM3RD_VideoOverlayBlend_FACTOR_100_PERCENT (3<<6) + +#define PM3RD_DClkSetup1 0x1f0 +#define PM3RD_DClkSetup2 0x1f1 +#define PM3RD_KClkSetup1 0x1f2 +#define PM3RD_KClkSetup2 0x1f3 + +#define PM3RD_DClkControl 0x200 + #define PM3RD_DClkControl_SOURCE_PLL (0<<4) + #define PM3RD_DClkControl_SOURCE_VSA (1<<4) + #define PM3RD_DClkControl_SOURCE_VSB (2<<4) + #define PM3RD_DClkControl_SOURCE_EXT (3<<4) + #define PM3RD_DClkControl_STATE_RUN (2<<2) + #define PM3RD_DClkControl_STATE_HIGH (1<<2) + #define PM3RD_DClkControl_STATE_LOW (0<<2) + #define PM3RD_DClkControl_LOCKED (1<<1) + #define PM3RD_DClkControl_NOT_LOCKED (0<<1) + #define PM3RD_DClkControl_ENABLE (1<<0) + #define PM3RD_DClkControl_DISABLE (0<<0) +#define PM3RD_DClk0PreScale 0x201 +#define PM3RD_DClk0FeedbackScale 0x202 +#define PM3RD_DClk0PostScale 0x203 +#define PM3RD_DClk1PreScale 0x204 +#define PM3RD_DClk1FeedbackScale 0x205 +#define PM3RD_DClk1PostScale 0x206 +#define PM3RD_DClk2PreScale 0x207 +#define PM3RD_DClk2FeedbackScale 0x208 +#define PM3RD_DClk2PostScale 0x209 +#define PM3RD_DClk3PreScale 0x20a +#define PM3RD_DClk3FeedbackScale 0x20b +#define PM3RD_DClk3PostScale 0x20c +#define PM3RD_KClkControl 0x20d + #define PM3RD_KClkControl_DISABLE (0<<0) + #define PM3RD_KClkControl_ENABLE (1<<0) + #define PM3RD_KClkControl_NOT_LOCKED (0<<1) + #define PM3RD_KClkControl_LOCKED (1<<1) + #define PM3RD_KClkControl_STATE_LOW (0<<2) + #define PM3RD_KClkControl_STATE_HIGH (1<<2) + #define PM3RD_KClkControl_STATE_RUN (2<<2) + #define PM3RD_KClkControl_STATE_LOW_POWER (3<<2) + #define PM3RD_KClkControl_SOURCE_PCLK (0<<4) + #define PM3RD_KClkControl_SOURCE_HALF_PCLK (1<<4) + #define PM3RD_KClkControl_SOURCE_PLL (2<<4) +#define PM3RD_KClkPreScale 0x20e +#define PM3RD_KClkFeedbackScale 0x20f +#define PM3RD_KClkPostScale 0x210 +#define PM3RD_MClkControl 0x211 + #define PM3RD_MClkControl_DISABLE (0<<0) + #define PM3RD_MClkControl_ENABLE (1<<0) + #define PM3RD_MClkControl_NOT_LOCKED (0<<1) + #define PM3RD_MClkControl_LOCKED (1<<1) + #define PM3RD_MClkControl_STATE_LOW (0<<2) + #define PM3RD_MClkControl_STATE_HIGH (1<<2) + #define PM3RD_MClkControl_STATE_RUN (2<<2) + #define PM3RD_MClkControl_STATE_LOW_POWER (3<<2) + #define PM3RD_MClkControl_SOURCE_PCLK (0<<4) + #define PM3RD_MClkControl_SOURCE_HALF_PCLK (1<<4) + #define PM3RD_MClkControl_SOURCE_HALF_EXT (3<<4) + #define PM3RD_MClkControl_SOURCE_EXT (4<<4) + #define PM3RD_MClkControl_SOURCE_HALF_KCLK (5<<4) + #define PM3RD_MClkControl_SOURCE_KCLK (6<<4) +#define PM3RD_MClkPreScale 0x212 +#define PM3RD_MClkFeedbackScale 0x213 +#define PM3RD_MClkPostScale 0x214 +#define PM3RD_SClkControl 0x215 + #define PM3RD_SClkControl_DISABLE (0<<0) + #define PM3RD_SClkControl_ENABLE (1<<0) + #define PM3RD_SClkControl_NOT_LOCKED (0<<1) + #define PM3RD_SClkControl_LOCKED (1<<1) + #define PM3RD_SClkControl_STATE_LOW (0<<2) + #define PM3RD_SClkControl_STATE_HIGH (1<<2) + #define PM3RD_SClkControl_STATE_RUN (2<<2) + #define PM3RD_SClkControl_STATE_LOW_POWER (3<<2) + #define PM3RD_SClkControl_SOURCE_PCLK (0<<4) + #define PM3RD_SClkControl_SOURCE_HALF_PCLK (1<<4) + #define PM3RD_SClkControl_SOURCE_HALF_EXT (3<<4) + #define PM3RD_SClkControl_SOURCE_EXT (4<<4) + #define PM3RD_SClkControl_SOURCE_HALF_KCLK (5<<4) + #define PM3RD_SClkControl_SOURCE_KCLK (6<<4) +#define PM3RD_SClkPreScale 0x216 +#define PM3RD_SClkFeedbackScale 0x217 +#define PM3RD_SClkPostScale 0x218 + +#define PM3RD_CursorPalette(p) (0x303+(p)) +#define PM3RD_CursorPattern(p) (0x400+(p)) +/****************************************************** +* GLINT Permedia3 Video Streaming Registers (0x5000) * +*******************************************************/ + +#define PM3VSConfiguration 0x5800 + +/********************************************** +* GLINT Permedia3 Core Registers (0x8000+) * +***********************************************/ +#define PM3AALineWidth 0x94c0 +#define PM3AAPointsize 0x94a0 +#define PM3AlphaBlendAlphaMode 0xafa8 +#define PM3AlphaBlendAlphaModeAnd 0xad30 +#define PM3AlphaBlendAlphaModeOr 0xad38 +#define PM3AlphaBlendColorMode 0xafa0 +#define PM3AlphaBlendColorModeAnd 0xacb0 +#define PM3AlphaBlendColorModeOr 0xacb8 +#define PM3AlphaDestColor 0xaf88 +#define PM3AlphaSourceColor 0xaf80 +#define PM3AlphaTestMode 0x8800 +#define PM3AlphaTestModeAnd 0xabf0 +#define PM3AlphaTestModeOr 0xabf8 +#define PM3AntialiasMode 0x8808 +#define PM3AntialiasModeAnd 0xac00 +#define PM3AntialiasModeOr 0xac08 +/* ... */ +#define PM3BackgroundColor 0xb0c8 +/* ... */ +#define PM3ColorDDAMode 0x87e0 +#define PM3ColorDDAModeAnd 0xabe0 +#define PM3ColorDDAModeOr 0xabe8 +#define PM3CommandInterrupt 0xa990 +#define PM3ConstantColorDDA 0xafb0 + #define PM3ConstantColorDDA_R(r) ((r)&0xff) + #define PM3ConstantColorDDA_G(g) (((g)&0xff)<<8) + #define PM3ConstantColorDDA_B(b) (((b)&0xff)<<16) + #define PM3ConstantColorDDA_A(a) (((a)&0xff)<<24) +#define PM3ContextData 0x8dd0 +#define PM3ContextDump 0x8dc0 +#define PM3ContextRestore 0x8dc8 +#define PM3Continue 0x8058 +#define PM3ContinueNewDom 0x8048 +#define PM3ContinueNewLine 0x8040 +#define PM3ContinueNewSub 0x8050 +#define PM3Count 0x8030 +/* ... */ +#define PM3DeltaControl 0x9350 +#define PM3DeltaControlAnd 0xab20 +#define PM3DeltaControlOr 0xab28 +#define PM3DeltaMode 0x9300 +#define PM3DeltaModeAnd 0xaad0 +#define PM3DeltaModeOr 0xaad8 +/* ... */ +#define PM3DitherMode 0x8818 +#define PM3DitherModeAnd 0xacd0 +#define PM3DitherModeOr 0xacd8 +/* ... */ +#define PM3dXDom 0x8008 +#define PM3dXSub 0x8018 +#define PM3dY 0x8028 +/* ... */ +#define PM3FBBlockColor 0x8ac8 +#define PM3FBBlockColor0 0xb060 +#define PM3FBBlockColor1 0xb068 +#define PM3FBBlockColor2 0xb070 +#define PM3FBBlockColor3 0xb078 +#define PM3FBBlockColorBack 0xb0a0 +#define PM3FBBlockColorBack0 0xb080 +#define PM3FBBlockColorBack1 0xb088 +#define PM3FBBlockColorBack2 0xb090 +#define PM3FBBlockColorBack3 0xb098 +#define PM3FBColor 0x8a98 +#define PM3FBDestReadBufferAddr0 0xae80 +#define PM3FBDestReadBufferAddr1 0xae88 +#define PM3FBDestReadBufferAddr2 0xae90 +#define PM3FBDestReadBufferAddr3 0xae98 +#define PM3FBDestReadBufferOffset0 0xaea0 +#define PM3FBDestReadBufferOffset1 0xaea8 +#define PM3FBDestReadBufferOffset2 0xaeb0 +#define PM3FBDestReadBufferOffset3 0xaeb8 + #define PM3FBDestReadBufferOffset_XOffset(x) ((x)&0xffff) + #define PM3FBDestReadBufferOffset_YOffset(y) (((y)&0xffff)<<16) +#define PM3FBDestReadBufferWidth0 0xaec0 +#define PM3FBDestReadBufferWidth1 0xaec8 +#define PM3FBDestReadBufferWidth2 0xaed0 +#define PM3FBDestReadBufferWidth3 0xaed8 + #define PM3FBDestReadBufferWidth_Width(w) ((w)&0x0fff) + +#define PM3FBDestReadEnables 0xaee8 +#define PM3FBDestReadEnablesAnd 0xad20 +#define PM3FBDestReadEnablesOr 0xad28 + #define PM3FBDestReadEnables_E(e) ((e)&0xff) + #define PM3FBDestReadEnables_E0 1<<0 + #define PM3FBDestReadEnables_E1 1<<1 + #define PM3FBDestReadEnables_E2 1<<2 + #define PM3FBDestReadEnables_E3 1<<3 + #define PM3FBDestReadEnables_E4 1<<4 + #define PM3FBDestReadEnables_E5 1<<5 + #define PM3FBDestReadEnables_E6 1<<6 + #define PM3FBDestReadEnables_E7 1<<7 + #define PM3FBDestReadEnables_R(r) (((r)&0xff)<<8) + #define PM3FBDestReadEnables_R0 1<<8 + #define PM3FBDestReadEnables_R1 1<<9 + #define PM3FBDestReadEnables_R2 1<<10 + #define PM3FBDestReadEnables_R3 1<<11 + #define PM3FBDestReadEnables_R4 1<<12 + #define PM3FBDestReadEnables_R5 1<<13 + #define PM3FBDestReadEnables_R6 1<<14 + #define PM3FBDestReadEnables_R7 1<<15 + #define PM3FBDestReadEnables_ReferenceAlpha(a) (((a)&0xff)<<24) + +#define PM3FBDestReadMode 0xaee0 +#define PM3FBDestReadModeAnd 0xac90 +#define PM3FBDestReadModeOr 0xac98 + #define PM3FBDestReadMode_ReadDisable 0<<0 + #define PM3FBDestReadMode_ReadEnable 1<<0 + #define PM3FBDestReadMode_StripePitch(sp) (((sp)&0x7)<<2) + #define PM3FBDestReadMode_StripeHeight(sh) (((sh)&0x7)<<7) + #define PM3FBDestReadMode_Enable0 1<<8 + #define PM3FBDestReadMode_Enable1 1<<9 + #define PM3FBDestReadMode_Enable2 1<<10 + #define PM3FBDestReadMode_Enable3 1<<11 + #define PM3FBDestReadMode_Layout0(l) (((l)&0x3)<<12) + #define PM3FBDestReadMode_Layout1(l) (((l)&0x3)<<14) + #define PM3FBDestReadMode_Layout2(l) (((l)&0x3)<<16) + #define PM3FBDestReadMode_Layout3(l) (((l)&0x3)<<18) + #define PM3FBDestReadMode_Origin0 1<<20 + #define PM3FBDestReadMode_Origin1 1<<21 + #define PM3FBDestReadMode_Origin2 1<<22 + #define PM3FBDestReadMode_Origin3 1<<23 + #define PM3FBDestReadMode_Blocking 1<<24 + #define PM3FBDestReadMode_UseReadEnabled 1<<26 + #define PM3FBDestReadMode_AlphaFiltering 1<<27 + +#define PM3FBHardwareWriteMask 0x8ac0 +#define PM3FBSoftwareWriteMask 0x8820 +#define PM3FBData 0x8aa0 +#define PM3FBSourceData 0x8aa8 +#define PM3FBSourceReadBufferAddr 0xaf08 +#define PM3FBSourceReadBufferOffset 0xaf10 + #define PM3FBSourceReadBufferOffset_XOffset(x) ((x)&0xffff) + #define PM3FBSourceReadBufferOffset_YOffset(y) (((y)&0xffff)<<16) +#define PM3FBSourceReadBufferWidth 0xaf18 + #define PM3FBSourceReadBufferWidth_Width(w) ((w)&0x0fff) +#define PM3FBSourceReadMode 0xaf00 +#define PM3FBSourceReadModeAnd 0xaca0 +#define PM3FBSourceReadModeOr 0xaca8 + #define PM3FBSourceReadMode_ReadDisable (0<<0) + #define PM3FBSourceReadMode_ReadEnable (1<<0) + #define PM3FBSourceReadMode_StripePitch(sp) (((sp)&0x7)<<2) + #define PM3FBSourceReadMode_StripeHeight(sh) (((sh)&0x7)<<7) + #define PM3FBSourceReadMode_Layout(l) (((l)&0x3)<<8) + #define PM3FBSourceReadMode_Origin 1<<10 + #define PM3FBSourceReadMode_Blocking 1<<11 + #define PM3FBSourceReadMode_UserTexelCoord 1<<13 + #define PM3FBSourceReadMode_WrapXEnable 1<<14 + #define PM3FBSourceReadMode_WrapYEnable 1<<15 + #define PM3FBSourceReadMode_WrapX(w) (((w)&0xf)<<16) + #define PM3FBSourceReadMode_WrapY(w) (((w)&0xf)<<20) + #define PM3FBSourceReadMode_ExternalSourceData 1<<24 +#define PM3FBWriteBufferAddr0 0xb000 +#define PM3FBWriteBufferAddr1 0xb008 +#define PM3FBWriteBufferAddr2 0xb010 +#define PM3FBWriteBufferAddr3 0xb018 + +#define PM3FBWriteBufferOffset0 0xb020 +#define PM3FBWriteBufferOffset1 0xb028 +#define PM3FBWriteBufferOffset2 0xb030 +#define PM3FBWriteBufferOffset3 0xb038 + #define PM3FBWriteBufferOffset_XOffset(x) ((x)&0xffff) + #define PM3FBWriteBufferOffset_YOffset(y) (((y)&0xffff)<<16) + +#define PM3FBWriteBufferWidth0 0xb040 +#define PM3FBWriteBufferWidth1 0xb048 +#define PM3FBWriteBufferWidth2 0xb050 +#define PM3FBWriteBufferWidth3 0xb058 + #define PM3FBWriteBufferWidth_Width(w) ((w)&0x0fff) + +#define PM3FBWriteMode 0x8ab8 +#define PM3FBWriteModeAnd 0xacf0 +#define PM3FBWriteModeOr 0xacf8 + #define PM3FBWriteMode_WriteDisable 0<<0 + #define PM3FBWriteMode_WriteEnable 1<<0 + #define PM3FBWriteMode_Replicate 1<<4 + #define PM3FBWriteMode_OpaqueSpan 1<<5 + #define PM3FBWriteMode_StripePitch(p) (((p)&0x7)<<6) + #define PM3FBWriteMode_StripeHeight(h) (((h)&0x7)<<9) + #define PM3FBWriteMode_Enable0 1<<12 + #define PM3FBWriteMode_Enable1 1<<13 + #define PM3FBWriteMode_Enable2 1<<14 + #define PM3FBWriteMode_Enable3 1<<15 + #define PM3FBWriteMode_Layout0(l) (((l)&0x3)<<16) + #define PM3FBWriteMode_Layout1(l) (((l)&0x3)<<18) + #define PM3FBWriteMode_Layout2(l) (((l)&0x3)<<20) + #define PM3FBWriteMode_Layout3(l) (((l)&0x3)<<22) + #define PM3FBWriteMode_Origin0 1<<24 + #define PM3FBWriteMode_Origin1 1<<25 + #define PM3FBWriteMode_Origin2 1<<26 + #define PM3FBWriteMode_Origin3 1<<27 +#define PM3ForegroundColor 0xb0c0 +/* ... */ +#define PM3GIDMode 0xb538 +#define PM3GIDModeAnd 0xb5b0 +#define PM3GIDModeOr 0xb5b8 +/* ... */ +#define PM3LBDestReadBufferAddr 0xb510 +#define PM3LBDestReadBufferOffset 0xb518 +#define PM3LBDestReadEnables 0xb508 +#define PM3LBDestReadEnablesAnd 0xb590 +#define PM3LBDestReadEnablesOr 0xb598 +#define PM3LBDestReadMode 0xb500 +#define PM3LBDestReadModeAnd 0xb580 +#define PM3LBDestReadModeOr 0xb588 + #define PM3LBDestReadMode_Disable 0<<0 + #define PM3LBDestReadMode_Enable 1<<0 + #define PM3LBDestReadMode_StripePitch(p) (((p)&0x7)<<2) + #define PM3LBDestReadMode_StripeHeight(h) (((h)&0x7)<<5) + #define PM3LBDestReadMode_Layout 1<<8 + #define PM3LBDestReadMode_Origin 1<<9 + #define PM3LBDestReadMode_UserReadEnables 1<<10 + #define PM3LBDestReadMode_Packed16 1<<11 + #define PM3LBDestReadMode_Width(w) (((w)&0xfff)<<12) +#define PM3LBReadFormat 0x8888 + #define PM3LBReadFormat_DepthWidth(w) (((w)&0x3)<<0) + #define PM3LBReadFormat_StencilWidth(w) (((w)&0xf)<<2) + #define PM3LBReadFormat_StencilPosition(p) (((p)&0x1f)<<6) + #define PM3LBReadFormat_FCPWidth(w) (((w)&0xf)<<11) + #define PM3LBReadFormat_FCPPosition(p) (((p)&0x1f)<<15) + #define PM3LBReadFormat_GIDWidth(w) (((w)&0x7)<<20) + #define PM3LBReadFormat_GIDPosition(p) (((p)&0x1f)<<23) +#define PM3LBSourceReadBufferAddr 0xb528 +#define PM3LBSourceReadBufferOffset 0xb530 +#define PM3LBSourceReadMode 0xb520 +#define PM3LBSourceReadModeAnd 0xb5a0 +#define PM3LBSourceReadModeOr 0xb5a8 + #define PM3LBSourceReadMode_Enable 1<<0 + #define PM3LBSourceReadMode_StripePitch(p) (((p)&0x7)<<2) + #define PM3LBSourceReadMode_StripeHeight(h) (((h)&0x7)<<5) + #define PM3LBSourceReadMode_Layout 1<<8 + #define PM3LBSourceReadMode_Origin 1<<9 + #define PM3LBSourceReadMode_Packed16 1<<10 + #define PM3LBSourceReadMode_Width(w) (((w)&0xfff)<<11) +#define PM3LBStencil 0x88a8 +#define PM3LBWriteBufferAddr 0xb540 +#define PM3LBWriteBufferOffset 0xb548 +#define PM3LBWriteFormat 0x88c8 + #define PM3LBWriteFormat_DepthWidth(w) (((w)&0x3)<<0) + #define PM3LBWriteFormat_StencilWidth(w) (((w)&0xf)<<2) + #define PM3LBWriteFormat_StencilPosition(p) (((p)&0x1f)<<6) + #define PM3LBWriteFormat_GIDWidth(w) (((w)&0x7)<<20) + #define PM3LBWriteFormat_GIDPosition(p) (((p)&0x1f)<<23) +#define PM3LBWriteMode 0x88c0 +#define PM3LBWriteModeAnd 0xac80 +#define PM3LBWriteModeOr 0xac88 + #define PM3LBWriteMode_WriteDisable 0<<0 + #define PM3LBWriteMode_WriteEnable 1<<0 + #define PM3LBWriteMode_StripePitch(p) (((p)&0x7)<<3) + #define PM3LBWriteMode_StripeHeight(h) (((h)&0x7)<<6) + #define PM3LBWriteMode_Layout 1<<9 + #define PM3LBWriteMode_Origin 1<<10 + #define PM3LBWriteMode_Packed16 1<<11 + #define PM3LBWriteMode_Width(w) (((w)&0xfff)<<12) +/* ... */ +#define PM3LineStippleMode 0x81a8 +#define PM3LineStippleModeAnd 0xabc0 +#define PM3LineStippleModeOr 0xabc8 +#define PM3LoadLineStippleCounters 0x81b0 +/* ... */ +#define PM3LogicalOpMode 0x8828 +#define PM3LogicalOpModeAnd 0xace0 +#define PM3LogicalOpModeOr 0xace8 + #define PM3LogicalOpMode_Disable (0<<0) + #define PM3LogicalOpMode_Enable (1<<0) + #define PM3LogicalOpMode_LogicOp(op) (((op)&0xf)<<1) + #define PM3LogicalOpMode_UseConstantWriteData_Disable (0<<5) + #define PM3LogicalOpMode_UseConstantWriteData_Enable (1<<5) + #define PM3LogicalOpMode_Background_Disable (0<<6) + #define PM3LogicalOpMode_Background_Enable (1<<6) + #define PM3LogicalOpMode_Background_LogicOp(op) (((op)&0xf)<<7) + #define PM3LogicalOpMode_UseConstantSource_Disable (0<<11) + #define PM3LogicalOpMode_UseConstantSource_Enable (1<<11) + +/* ... */ +#define PM3LUT 0x8e80 +/* ... */ +#define PM3LUT 0x8e80 +#define PM3LUTAddress 0x84d0 +#define PM3LUTData 0x84c8 +#define PM3LUTIndex 0x84c0 +#define PM3LUTMode 0xb378 +#define PM3LUTModeAnd 0xad70 +#define PM3LUTModeOr 0xad78 +#define PM3LUTTransfer 0x84d8 +/* ... */ +#define PM3PixelSize 0x80c0 + #define PM3PixelSize_GLOBAL_32BIT (0<<0) + #define PM3PixelSize_GLOBAL_16BIT (1<<0) + #define PM3PixelSize_GLOBAL_8BIT (2<<0) + #define PM3PixelSize_RASTERIZER_32BIT (0<<2) + #define PM3PixelSize_RASTERIZER_16BIT (1<<2) + #define PM3PixelSize_RASTERIZER_8BIT (2<<2) + #define PM3PixelSize_SCISSOR_AND_STIPPLE_32BIT (0<<4) + #define PM3PixelSize_SCISSOR_AND_STIPPLE_16BIT (1<<4) + #define PM3PixelSize_SCISSOR_AND_STIPPLE_8BIT (2<<4) + #define PM3PixelSize_TEXTURE_32BIT (0<<6) + #define PM3PixelSize_TEXTURE_16BIT (1<<6) + #define PM3PixelSize_TEXTURE_8BIT (2<<6) + #define PM3PixelSize_LUT_32BIT (0<<8) + #define PM3PixelSize_LUT_16BIT (1<<8) + #define PM3PixelSize_LUT_8BIT (2<<8) + #define PM3PixelSize_FRAMEBUFFER_32BIT (0<<10) + #define PM3PixelSize_FRAMEBUFFER_16BIT (1<<10) + #define PM3PixelSize_FRAMEBUFFER_8BIT (2<<10) + #define PM3PixelSize_LOGICAL_OP_32BIT (0<<12) + #define PM3PixelSize_LOGICAL_OP_16BIT (1<<12) + #define PM3PixelSize_LOGICAL_OP_8BIT (2<<12) + #define PM3PixelSize_LOCALBUFFER_32BIT (0<<14) + #define PM3PixelSize_LOCALBUFFER_16BIT (1<<14) + #define PM3PixelSize_LOCALBUFFER_8BIT (2<<14) + #define PM3PixelSize_SETUP_32BIT (0<<16) + #define PM3PixelSize_SETUP_16BIT (1<<16) + #define PM3PixelSize_SETUP_8BIT (2<<16) + #define PM3PixelSize_GLOBAL (0<<31) + #define PM3PixelSize_INDIVIDUAL (1<<31) +/* ... */ +#define PM3Render 0x8038 + #define PM3Render_AreaStipple_Disable (0<<0) + #define PM3Render_AreaStipple_Enable (1<<0) + #define PM3Render_LineStipple_Disable (0<<1) + #define PM3Render_LineStipple_Enable (1<<1) + #define PM3Render_ResetLine_Disable (0<<2) + #define PM3Render_ResetLine_Enable (1<<2) + #define PM3Render_FastFill_Disable (0<<3) + #define PM3Render_FastFill_Enable (1<<3) + #define PM3Render_Primitive_Line (0<<6) + #define PM3Render_Primitive_Trapezoid (1<<6) + #define PM3Render_Primitive_Point (2<<6) + #define PM3Render_Antialias_Disable (0<<8) + #define PM3Render_Antialias_Enable (1<<8) + #define PM3Render_Antialias_SubPixelRes_4x4 (0<<9) + #define PM3Render_Antialias_SubPixelRes_8x8 (1<<9) + #define PM3Render_UsePointTable_Disable (0<<10) + #define PM3Render_UsePointTable_Enable (1<<10) + #define PM3Render_SyncOnbitMask_Disable (0<<11) + #define PM3Render_SyncOnBitMask_Enable (1<<11) + #define PM3Render_SyncOnHostData_Disable (0<<12) + #define PM3Render_SyncOnHostData_Enable (1<<12) + #define PM3Render_Texture_Disable (0<<13) + #define PM3Render_Texture_Enable (1<<13) + #define PM3Render_Fog_Disable (0<<14) + #define PM3Render_Fog_Enable (1<<14) + #define PM3Render_Coverage_Disable (0<<15) + #define PM3Render_Coverage_Enable (1<<15) + #define PM3Render_SubPixelCorrection_Disable (0<<16) + #define PM3Render_SubPixelCorrection_Enable (1<<16) + #define PM3Render_SpanOperation_Disable (0<<18) + #define PM3Render_SpanOperation_Enable (1<<18) + #define PM3Render_FBSourceRead_Disable (0<<27) + #define PM3Render_FBSourceRead_Enable (1<<27) +#define PM3RasterizerMode 0x80a0 +#define PM3RasterizerModeAnd 0xaba0 +#define PM3RasterizerModeOr 0xabb8 +#define PM3RectangleHeight 0x94e0 +#define PM3Render 0x8038 +#define PM3RepeatLine 0x9328 +#define PM3ResetPickResult 0x8c20 +#define PM3RLEMask 0x8c48 +#define PM3RouterMode 0x8840 +#define PM3RStart 0x8780 +#define PM3S1Start 0x8400 +#define PM3aveLineStippleCounters 0x81c0 +#define PM3ScissorMaxXY 0x8190 +#define PM3ScissorMinXY 0x8188 +#define PM3ScissorMode 0x8180 +#define PM3ScissorModeAnd 0xabb0 +#define PM3ScissorModeOr 0xabb8 +#define PM3ScreenSize 0x8198 +#define PM3Security 0x8908 +#define PM3SetLogicalTexturePage 0xb360 +#define PM3SizeOfFramebuffer 0xb0a8 +#define PM3SStart 0x8388 +#define PM3StartXDom 0x8000 +#define PM3StartXSub 0x8010 +#define PM3StartY 0x8020 +/* ... */ +#define PM3SpanColorMask 0x8168 +/* ... */ +#define PM3TextureApplicationMode 0x8680 +#define PM3TextureApplicationModeAnd 0xac50 +#define PM3TextureApplicationModeOr 0xac58 +#define PM3TextureBaseAddr 0x8500 +#define PM3TextureCacheControl 0x8490 +#define PM3TextureChromaLower0 0x84f0 +#define PM3TextureChromaLower1 0x8608 +#define PM3TextureChromaUpper0 0x84e8 +#define PM3TextureChromaUpper1 0x8600 +#define PM3TextureCompositeAlphaMode0 0xb310 +#define PM3TextureCompositeAlphaMode0And 0xb390 +#define PM3TextureCompositeAlphaMode0Or 0xb398 +#define PM3TextureCompositeAlphaMode1 0xb320 +#define PM3TextureCompositeAlphaMode1And 0xb3b0 +#define PM3TextureCompositeAlphaMode1Or 0xb3b8 +#define PM3TextureCompositeColorMode0 0xb308 +#define PM3TextureCompositeColorMode0And 0xb380 +#define PM3TextureCompositeColorMode0Or 0xb388 +#define PM3TextureCompositeColorMode1 0xb318 +#define PM3TextureCompositeColorMode1And 0xb3a0 +#define PM3TextureCompositeColorMode1Or 0xb3a8 +#define PM3TextureCompositeFactor0 0xb328 +#define PM3TextureCompositeFactor1 0xb330 +#define PM3TextureCompositeMode 0xb300 +#define PM3TextureCoordMode 0x8380 +#define PM3TextureCoordModeAnd 0xac20 +#define PM3TextureCoordModeOr 0xac28 +#define PM3TextureData 0x88e8 +/* +#define PM3TextureDownloadControl 0x0108 +*/ +#define PM3TextureDownloadOffset 0x88f0 +#define PM3TextureEnvColor 0x8688 +#define PM3TextureFilterMode 0x84e0 +#define PM3TextureFilterModeAnd 0xad50 +#define PM3TextureFilterModeOr 0xad58 +#define PM3TextureIndexMode0 0xb338 +#define PM3TextureIndexMode0And 0xb3c0 +#define PM3TextureIndexMode0Or 0xb3c8 +#define PM3TextureIndexMode1 0xb340 +#define PM3TextureIndexMode1And 0xb3d0 +#define PM3TextureIndexMode1Or 0xb3d8 +#define PM3TextureLODBiasS 0x8450 +#define PM3TextureLODBiasT 0x8458 +/* ... */ +#define PM3TextureMapSize 0xb428 +#define PM3TextureMapWidth0 0x8580 +#define PM3TextureMapWidth1 0x8588 + #define PM3TextureMapWidth_Width(w) ((w&0xfff)<<0) + #define PM3TextureMapWidth_BorderLayout (1<<12) + #define PM3TextureMapWidth_Layout_Linear (0<<13) + #define PM3TextureMapWidth_Layout_Patch64 (1<<13) + #define PM3TextureMapWidth_Layout_Patch32_2 (2<<13) + #define PM3TextureMapWidth_Layout_Patch2 (3<<13) + #define PM3TextureMapWidth_HostTexture (1<<15) +#define PM3TextureReadMode0 0xb400 +#define PM3TextureReadMode0And 0xac30 +#define PM3TextureReadMode0Or 0xac38 +#define PM3TextureReadMode1 0xb408 +#define PM3TextureReadMode1And 0xad40 +#define PM3TextureReadMode1Or 0xad48 +/* ... */ +#define PM3WaitForCompletion 0x80b8 +#define PM3Window 0x8980 + #define PM3Window_ForceLBUpdate 1<<3 + #define PM3Window_LBUpdateSource 1<<4 + #define PM3Window_FrameCount(c) (((c)&0xff)<<9) + #define PM3Window_StencilFCP 1<<17 + #define PM3Window_DepthFCP 1<<18 + #define PM3Window_OverrideWriteFiltering 1<<19 +#define PM3WindowAnd 0xab80 +#define PM3WindowOr 0xab88 +#define PM3WindowOrigin 0x81c8 +#define PM3XBias 0x9480 +#define PM3YBias 0x9488 +#define PM3YLimits 0x80a8 +#define PM3UVMode 0x8f00 +#define PM3ZFogBias 0x86b8 +#define PM3ZStart 0xadd8 +#define PM3ZStartL 0x89b8 +#define PM3ZStartU 0x89b0 + + +/********************************************** +* GLINT Permedia3 2D setup Unit * +***********************************************/ +#define PM3Config2D 0xb618 + #define PM3Config2D_OpaqueSpan 1<<0 + #define PM3Config2D_MultiRXBlit 1<<1 + #define PM3Config2D_UserScissorEnable 1<<2 + #define PM3Config2D_FBDestReadEnable 1<<3 + #define PM3Config2D_AlphaBlendEnable 1<<4 + #define PM3Config2D_DitherEnable 1<<5 + #define PM3Config2D_ForegroundROPEnable 1<<6 + #define PM3Config2D_ForegroundROP(rop) (((rop)&0xf)<<7) + #define PM3Config2D_BackgroundROPEnable 1<<11 + #define PM3Config2D_BackgroundROP(rop) (((rop)&0xf)<<12) + #define PM3Config2D_UseConstantSource 1<<16 + #define PM3Config2D_FBWriteEnable 1<<17 + #define PM3Config2D_Blocking 1<<18 + #define PM3Config2D_ExternalSourceData 1<<19 + #define PM3Config2D_LUTModeEnable 1<<20 +#define PM3DownloadGlyphwidth 0xb658 + #define PM3DownloadGlyphwidth_GlyphWidth(gw) ((gw)&0xffff) +#define PM3DownloadTarget 0xb650 + #define PM3DownloadTarget_TagName(tag) ((tag)&0x1fff) +#define PM3GlyphData 0xb660 +#define PM3GlyphPosition 0xb608 + #define PM3GlyphPosition_XOffset(x) ((x)&0xffff) + #define PM3GlyphPosition_YOffset(y) (((y)&0xffff)<<16) +#define PM3Packed4Pixels 0xb668 +#define PM3Packed8Pixels 0xb630 +#define PM3Packed16Pixels 0xb638 +#define PM3RectanglePosition 0xb600 + #define PM3RectanglePosition_XOffset(x) ((x)&0xffff) + #define PM3RectanglePosition_YOffset(y) (((y)&0xffff)<<16) +#define PM3Render2D 0xb640 + #define PM3Render2D_Width(w) ((w)&0x0fff) + #define PM3Render2D_Operation_Normal 0<<12 + #define PM3Render2D_Operation_SyncOnHostData 1<<12 + #define PM3Render2D_Operation_SyncOnBitMask 2<<12 + #define PM3Render2D_Operation_PatchOrderRendering 3<<12 + #define PM3Render2D_FBSourceReadEnable 1<<14 + #define PM3Render2D_SpanOperation 1<<15 + #define PM3Render2D_Height(h) (((h)&0x0fff)<<16) + #define PM3Render2D_XPositive 1<<28 + #define PM3Render2D_YPositive 1<<29 + #define PM3Render2D_AreaStippleEnable 1<<30 + #define PM3Render2D_TextureEnable 1<<31 +#define PM3Render2DGlyph 0xb648 + #define PM3Render2DGlyph_Width(w) ((w)&0x7f) + #define PM3Render2DGlyph_Height(h) (((h)&0x7f)<<7) + #define PM3Render2DGlyph_XOffset(x) (((x)&0x1ff)<<14) + #define PM3Render2DGlyph_YOffset(y) (((y)&0x1ff)<<23) +#define PM3RenderPatchOffset 0xb610 + #define PM3RenderPatchOffset_XOffset(x) ((x)&0xffff) + #define PM3RenderPatchOffset_YOffset(y) (((y)&0xffff)<<16) +#define PM3RLCount 0xb678 + #define PM3RLCount_Count(c) ((c)&0x0fff) +#define PM3RLData 0xb670 + +/********************************************** +* GLINT Permedia3 Alias Register * +***********************************************/ +#define PM3FillBackgroundColor 0x8330 +#define PM3FillConfig2D0 0x8338 +#define PM3FillConfig2D1 0x8360 + #define PM3FillConfig2D_OpaqueSpan 1<<0 + #define PM3FillConfig2D_MultiRXBlit 1<<1 + #define PM3FillConfig2D_UserScissorEnable 1<<2 + #define PM3FillConfig2D_FBDestReadEnable 1<<3 + #define PM3FillConfig2D_AlphaBlendEnable 1<<4 + #define PM3FillConfig2D_DitherEnable 1<<5 + #define PM3FillConfig2D_ForegroundROPEnable 1<<6 + #define PM3FillConfig2D_ForegroundROP(rop) (((rop)&0xf)<<7) + #define PM3FillConfig2D_BackgroundROPEnable 1<<11 + #define PM3FillConfig2D_BackgroundROP(rop) (((rop)&0xf)<<12) + #define PM3FillConfig2D_UseConstantSource 1<<16 + #define PM3FillConfig2D_FBWriteEnable 1<<17 + #define PM3FillConfig2D_Blocking 1<<18 + #define PM3FillConfig2D_ExternalSourceData 1<<19 + #define PM3FillConfig2D_LUTModeEnable 1<<20 +#define PM3FillFBDestReadBufferAddr 0x8310 +#define PM3FillFBSourceReadBufferAddr 0x8308 +#define PM3FillFBSourceReadBufferOffset 0x8340 + #define PM3FillFBSourceReadBufferOffset_XOffset(x) ((x)&0xffff) + #define PM3FillFBSourceReadBufferOffset_YOffset(y) (((y)&0xffff)<<16) +#define PM3FillFBWriteBufferAddr 0x8300 +#define PM3FillForegroundColor0 0x8328 +#define PM3FillForegroundColor1 0x8358 +#define PM3FillGlyphPosition 0x8368 + #define PM3FillGlyphPosition_XOffset(x) ((x)&0xffff) + #define PM3FillGlyphPosition_YOffset(y) (((y)&0xffff)<<16) +#define PM3FillRectanglePosition 0x8348 + #define PM3FillRectanglePosition_XOffset(x) ((x)&0xffff) + #define PM3FillRectanglePosition_YOffset(y) (((y)&0xffff)<<16) + +#if 1 + +/********************************************** +* GLINT Permedia3 Macros * +***********************************************/ + +extern void *pm3_reg_base; + +#define WRITE_REG(offset,val) \ + *(volatile unsigned long *)(((unsigned char *)(pm3_reg_base)) + offset) = (val) + +#define READ_REG(offset) \ + *(volatile unsigned long *)(((unsigned char *)(pm3_reg_base)) + offset) + +#define UPDATE_SET_REG(offset,val) \ + { \ + unsigned long temp; \ + temp = READ_REG(offset); \ + WRITE_REG(offset,temp|(val)); \ + } + +#define UPDATE_CLEAR_REG(offset,val) \ + { \ + unsigned long temp; \ + temp = READ_REG(offset); \ + WRITE_REG(offset,temp&(~(val))); \ + } + +#define RAMDAC_DELAY(x) do { \ + int delay = x; \ + unsigned char tmp; \ + while(delay--){tmp = READ_REG(PM3InFIFOSpace);}; \ +} while(0) + +#define SLOW_WRITE_REG(v,r) \ +do{ \ + RAMDAC_DELAY(5); \ + WRITE_REG(v,r); \ + RAMDAC_DELAY(5); \ +}while(0) + +#define RAMDAC_SET_INDEX(index) \ +{ \ + SLOW_WRITE_REG (PM3RD_IndexHigh,(index>>8)&0xff); \ + SLOW_WRITE_REG (PM3RD_IndexLow,index&0xff); \ +} + +#define RAMDAC_SET_REG(index, data) \ +{ \ + RAMDAC_SET_INDEX(index); \ + SLOW_WRITE_REG(PM3RD_IndexedData, data); \ +} + +#define RAMDAC_GET_REG(index, temp) \ +{ \ + RAMDAC_SET_INDEX(index); \ + temp = READ_REG(PM3RD_IndexedData); \ +} +#endif +#endif /* _PM3_REG_H_ */ diff --git a/src/video_out/vidix/drivers/pm3_vid.c b/src/video_out/vidix/drivers/pm3_vid.c new file mode 100644 index 000000000..73c30c543 --- /dev/null +++ b/src/video_out/vidix/drivers/pm3_vid.c @@ -0,0 +1,370 @@ +/** + Driver for 3DLabs GLINT R3 and Permedia3 chips. + + Copyright (C) 2002 Måns Rullgård + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +**/ + +#include +#include +#include +#include +#include +#include + +#include "../vidix.h" +#include "../fourcc.h" +#include "../../libdha/libdha.h" +#include "../../libdha/pci_ids.h" +#include "../../libdha/pci_names.h" +#include "../../config.h" + +#include "pm3_regs.h" + +#if 0 +#define TRACE_ENTER() fprintf(stderr, "%s: enter\n", __FUNCTION__) +#define TRACE_EXIT() fprintf(stderr, "%s: exit\n", __FUNCTION__) +#else +#define TRACE_ENTER() +#define TRACE_EXIT() +#endif + +pciinfo_t pci_info; + +void *pm3_reg_base; +void *pm3_mem; + +static vidix_capability_t pm3_cap = +{ + "3DLabs GLINT R3/Permedia3 driver", + "Måns Rullgård ", + TYPE_OUTPUT, + { 0, 0, 0, 0 }, + 2048, + 2048, + 4, + 4, + -1, + FLAG_UPSCALER|FLAG_DOWNSCALER, + VENDOR_3DLABS, + -1, + { 0, 0, 0, 0 } +}; + + +unsigned int vixGetVersion(void) +{ + return(VIDIX_VERSION); +} + +static unsigned short pm3_card_ids[] = +{ + DEVICE_3DLABS_GLINT_R3 +}; + +static int find_chip(unsigned chip_id) +{ + unsigned i; + for(i = 0;i < sizeof(pm3_card_ids)/sizeof(unsigned short);i++) + { + if(chip_id == pm3_card_ids[i]) return i; + } + return -1; +} + +int vixProbe(int verbose, int force) +{ + pciinfo_t lst[MAX_PCI_DEVICES]; + unsigned i,num_pci; + int err; + + err = pci_scan(lst,&num_pci); + if(err) + { + printf("[pm3] Error occured during pci scan: %s\n",strerror(err)); + return err; + } + else + { + err = ENXIO; + for(i=0; i < num_pci; i++) + { + if(lst[i].vendor == VENDOR_3DLABS) + { + int idx; + const char *dname; + idx = find_chip(lst[i].device); + if(idx == -1) + continue; + dname = pci_device_name(VENDOR_3DLABS, lst[i].device); + dname = dname ? dname : "Unknown chip"; + printf("[pm3] Found chip: %s\n", dname); + pm3_cap.device_id = lst[i].device; + err = 0; + memcpy(&pci_info, &lst[i], sizeof(pciinfo_t)); + break; + } + } + } + if(err && verbose) printf("[pm3] Can't find chip\n"); + return err; +} + +#define PRINT_REG(reg) \ +{ \ + long _foo = READ_REG(reg); \ + printf("[pm3] " #reg " (%x) = %#lx (%li)\n", reg, _foo, _foo); \ +} + +int vixInit(void) +{ + pm3_reg_base = map_phys_mem(pci_info.base0, 0x20000); + pm3_mem = map_phys_mem(pci_info.base2, 0x2000000); + return 0; +} + +void vixDestroy(void) +{ + unmap_phys_mem(pm3_reg_base, 0x20000); + unmap_phys_mem(pm3_mem, 0x2000000); +} + +int vixGetCapability(vidix_capability_t *to) +{ + memcpy(to, &pm3_cap, sizeof(vidix_capability_t)); + return 0; +} + +static int is_supported_fourcc(uint32_t fourcc) +{ + switch(fourcc){ + case IMGFMT_YUY2: + case IMGFMT_UYVY: + return 1; + default: + return 0; + } +} + +int vixQueryFourcc(vidix_fourcc_t *to) +{ + if(is_supported_fourcc(to->fourcc)) + { + to->depth = VID_DEPTH_1BPP | VID_DEPTH_2BPP | + VID_DEPTH_4BPP | VID_DEPTH_8BPP | + VID_DEPTH_12BPP| VID_DEPTH_15BPP| + VID_DEPTH_16BPP| VID_DEPTH_24BPP| + VID_DEPTH_32BPP; + to->flags = VID_CAP_EXPAND | VID_CAP_SHRINK | VID_CAP_COLORKEY; + return 0; + } + else to->depth = to->flags = 0; + return ENOSYS; +} + +#define FORMAT_RGB8888 PM3VideoOverlayMode_COLORFORMAT_RGB8888 +#define FORMAT_RGB4444 PM3VideoOverlayMode_COLORFORMAT_RGB4444 +#define FORMAT_RGB5551 PM3VideoOverlayMode_COLORFORMAT_RGB5551 +#define FORMAT_RGB565 PM3VideoOverlayMode_COLORFORMAT_RGB565 +#define FORMAT_RGB332 PM3VideoOverlayMode_COLORFORMAT_RGB332 +#define FORMAT_BGR8888 PM3VideoOverlayMode_COLORFORMAT_BGR8888 +#define FORMAT_BGR4444 PM3VideoOverlayMode_COLORFORMAT_BGR4444 +#define FORMAT_BGR5551 PM3VideoOverlayMode_COLORFORMAT_BGR5551 +#define FORMAT_BGR565 PM3VideoOverlayMode_COLORFORMAT_BGR565 +#define FORMAT_BGR332 PM3VideoOverlayMode_COLORFORMAT_BGR332 +#define FORMAT_CI8 PM3VideoOverlayMode_COLORFORMAT_CI8 +#define FORMAT_VUY444 PM3VideoOverlayMode_COLORFORMAT_VUY444 +#define FORMAT_YUV444 PM3VideoOverlayMode_COLORFORMAT_YUV444 +#define FORMAT_VUY422 PM3VideoOverlayMode_COLORFORMAT_VUY422 +#define FORMAT_YUV422 PM3VideoOverlayMode_COLORFORMAT_YUV422 + +/* Notice, have to check that we dont overflow the deltas here ... */ +static void +compute_scale_factor( + short* src_w, short* dst_w, + unsigned int* shrink_delta, unsigned int* zoom_delta) +{ + /* NOTE: If we don't return reasonable values here then the video + * unit can potential shut off and won't display an image until re-enabled. + * Seems as though the zoom_delta is o.k, and I've not had the problem. + * The 'shrink_delta' is prone to this the most - FIXME ! */ + + if (*src_w >= *dst_w) { + *src_w &= ~0x3; + *dst_w &= ~0x3; + *shrink_delta = (((*src_w << 16) / *dst_w) + 0x0f) & 0x0ffffff0; + *zoom_delta = 1<<16; + if ( ((*shrink_delta * *dst_w) >> 16) & 0x03 ) + *shrink_delta += 0x10; + } else { + *src_w &= ~0x3; + *dst_w &= ~0x3; + *zoom_delta = (((*src_w << 16) / *dst_w) + 0x0f) & 0x0001fff0; + *shrink_delta = 1<<16; + if ( ((*zoom_delta * *dst_w) >> 16) & 0x03 ) + *zoom_delta += 0x10; + } +} + +static int frames[VID_PLAY_MAXFRAMES]; + +static long overlay_mode, overlay_control; + +int vixConfigPlayback(vidix_playback_t *info) +{ + int shrink, zoom; + short src_w, drw_w; + short src_h, drw_h; + long base0; + int pitch; + int format; + unsigned int i; + + TRACE_ENTER(); + + if(!is_supported_fourcc(info->fourcc)) + return -1; + + switch(info->fourcc){ + case IMGFMT_YUY2: + format = FORMAT_YUV422; + break; + case IMGFMT_UYVY: + format = FORMAT_VUY422; + break; + default: + return -1; + } + + src_w = info->src.w; + src_h = info->src.h; + + drw_w = info->dest.w; + drw_h = info->dest.h; + + pitch = src_w; + + /* Assume we have 16 MB to play with */ + info->num_frames = 0x1000000 / (pitch * src_h * 2); + if(info->num_frames > VID_PLAY_MAXFRAMES) + info->num_frames = VID_PLAY_MAXFRAMES; + + /* Start at 16 MB. Let's hope it's not in use. */ + base0 = 0x1000000; + info->dga_addr = pm3_mem + base0; + + info->dest.pitch.y = 2; + info->dest.pitch.u = 0; + info->dest.pitch.v = 0; + info->offset.y = 0; + info->offset.v = 0; + info->offset.u = 0; + info->frame_size = pitch * src_h * 2; + for(i = 0; i < info->num_frames; i++){ + info->offsets[i] = info->frame_size * i; + frames[i] = (base0 + info->offsets[i]) >> 1; + } + + compute_scale_factor(&src_w, &drw_w, &shrink, &zoom); + + WRITE_REG(PM3VideoOverlayBase0, base0 >> 1); + WRITE_REG(PM3VideoOverlayStride, PM3VideoOverlayStride_STRIDE(pitch)); + WRITE_REG(PM3VideoOverlayWidth, PM3VideoOverlayWidth_WIDTH(src_w)); + WRITE_REG(PM3VideoOverlayHeight, PM3VideoOverlayHeight_HEIGHT(src_h)); + WRITE_REG(PM3VideoOverlayOrigin, 0); + + /* Scale the source to the destinationsize */ + if (src_h == drw_h) { + WRITE_REG(PM3VideoOverlayYDelta, PM3VideoOverlayYDelta_NONE); + } else { + WRITE_REG(PM3VideoOverlayYDelta, + PM3VideoOverlayYDelta_DELTA(src_h, drw_h)); + } + if (src_w == drw_w) { + WRITE_REG(PM3VideoOverlayShrinkXDelta, 1<<16); + WRITE_REG(PM3VideoOverlayZoomXDelta, 1<<16); + } else { + WRITE_REG(PM3VideoOverlayShrinkXDelta, shrink); + WRITE_REG(PM3VideoOverlayZoomXDelta, zoom); + } + WRITE_REG(PM3VideoOverlayIndex, 0); + + /* Now set the ramdac video overlay region and mode */ + RAMDAC_SET_REG(PM3RD_VideoOverlayXStartLow, (info->dest.x & 0xff)); + RAMDAC_SET_REG(PM3RD_VideoOverlayXStartHigh, (info->dest.x & 0xf00)>>8); + RAMDAC_SET_REG(PM3RD_VideoOverlayXEndLow, (info->dest.x+drw_w) & 0xff); + RAMDAC_SET_REG(PM3RD_VideoOverlayXEndHigh, + ((info->dest.x+drw_w) & 0xf00)>>8); + RAMDAC_SET_REG(PM3RD_VideoOverlayYStartLow, (info->dest.y & 0xff)); + RAMDAC_SET_REG(PM3RD_VideoOverlayYStartHigh, (info->dest.y & 0xf00)>>8); + RAMDAC_SET_REG(PM3RD_VideoOverlayYEndLow, (info->dest.y+drw_h) & 0xff); + RAMDAC_SET_REG(PM3RD_VideoOverlayYEndHigh, + ((info->dest.y+drw_h) & 0xf00)>>8); + + RAMDAC_SET_REG(PM3RD_VideoOverlayKeyR, 0xff); + RAMDAC_SET_REG(PM3RD_VideoOverlayKeyG, 0x00); + RAMDAC_SET_REG(PM3RD_VideoOverlayKeyB, 0xff); + + overlay_mode = + 1 << 5 | + format | + PM3VideoOverlayMode_FILTER_FULL | + PM3VideoOverlayMode_BUFFERSYNC_MANUAL | + PM3VideoOverlayMode_FLIP_VIDEO; + + overlay_control = + PM3RD_VideoOverlayControl_KEY_COLOR | + PM3RD_VideoOverlayControl_MODE_MAINKEY | + PM3RD_VideoOverlayControl_DIRECTCOLOR_ENABLED; + + TRACE_EXIT(); + return 0; +} + +int vixPlaybackOn(void) +{ + TRACE_ENTER(); + + WRITE_REG(PM3VideoOverlayMode, + overlay_mode | PM3VideoOverlayMode_ENABLE); + RAMDAC_SET_REG(PM3RD_VideoOverlayControl, + overlay_control | PM3RD_VideoOverlayControl_ENABLE); + WRITE_REG(PM3VideoOverlayUpdate, + PM3VideoOverlayUpdate_ENABLE); + + TRACE_EXIT(); + return 0; +} + +int vixPlaybackOff(void) +{ + RAMDAC_SET_REG(PM3RD_VideoOverlayControl, + PM3RD_VideoOverlayControl_DISABLE); + WRITE_REG(PM3VideoOverlayMode, + PM3VideoOverlayMode_DISABLE); + + RAMDAC_SET_REG(PM3RD_VideoOverlayKeyR, 0x01); + RAMDAC_SET_REG(PM3RD_VideoOverlayKeyG, 0x01); + RAMDAC_SET_REG(PM3RD_VideoOverlayKeyB, 0xfe); + + return 0; +} + +int vixPlaybackFrameSelect(unsigned int frame) +{ + WRITE_REG(PM3VideoOverlayBase0, frames[frame]); + return 0; +} diff --git a/src/video_out/vidix/drivers/radeon.h b/src/video_out/vidix/drivers/radeon.h new file mode 100644 index 000000000..6093356c1 --- /dev/null +++ b/src/video_out/vidix/drivers/radeon.h @@ -0,0 +1,2156 @@ +/* + * radeon.h + * This software has been released under the terms of the GNU Public + * license. See http://www.gnu.org/copyleft/gpl.html for details. + * + * This collection of definition was written by Nick Kurshev + * It's based on radeonfb, X11, GATOS sources + * and partly compatible with Rage128 set (in OV0, CAP0, CAP1 parts) +*/ + +#ifndef _RADEON_H +#define _RADEON_H + +#define RADEON_REGSIZE 0x4000 +#define MM_INDEX 0x0000 +/* MM_INDEX bit constants */ +# define MM_APER 0x80000000 +#define MM_DATA 0x0004 +#define BUS_CNTL 0x0030 +/* BUS_CNTL bit constants */ +# define BUS_DBL_RESYNC 0x00000001 +# define BUS_MSTR_RESET 0x00000002 +# define BUS_FLUSH_BUF 0x00000004 +# define BUS_STOP_REQ_DIS 0x00000008 +# define BUS_ROTATION_DIS 0x00000010 +# define BUS_MASTER_DIS 0x00000040 +# define BUS_ROM_WRT_EN 0x00000080 +# define BUS_DIS_ROM 0x00001000 +# define BUS_PCI_READ_RETRY_EN 0x00002000 +# define BUS_AGP_AD_STEPPING_EN 0x00004000 +# define BUS_PCI_WRT_RETRY_EN 0x00008000 +# define BUS_MSTR_RD_MULT 0x00100000 +# define BUS_MSTR_RD_LINE 0x00200000 +# define BUS_SUSPEND 0x00400000 +# define LAT_16X 0x00800000 +# define BUS_RD_DISCARD_EN 0x01000000 +# define BUS_RD_ABORT_EN 0x02000000 +# define BUS_MSTR_WS 0x04000000 +# define BUS_PARKING_DIS 0x08000000 +# define BUS_MSTR_DISCONNECT_EN 0x10000000 +# define BUS_WRT_BURST 0x20000000 +# define BUS_READ_BURST 0x40000000 +# define BUS_RDY_READ_DLY 0x80000000 +#define HI_STAT 0x004C +#define BUS_CNTL1 0x0034 +# define BUS_WAIT_ON_LOCK_EN (1 << 4) +#define I2C_CNTL_0 0x0090 +# define I2C_DONE (1<<0) +# define I2C_NACK (1<<1) +# define I2C_HALT (1<<2) +# define I2C_SOFT_RST (1<<5) +# define I2C_DRIVE_EN (1<<6) +# define I2C_DRIVE_SEL (1<<7) +# define I2C_START (1<<8) +# define I2C_STOP (1<<9) +# define I2C_RECEIVE (1<<10) +# define I2C_ABORT (1<<11) +# define I2C_GO (1<<12) +# define I2C_SEL (1<<16) +# define I2C_EN (1<<17) +#define I2C_CNTL_1 0x0094 +#define I2C_DATA 0x0098 +#define CONFIG_CNTL 0x00E0 +/* CONFIG_CNTL bit constants */ +# define CFG_VGA_RAM_EN 0x00000100 +#ifdef RAGE128 +#define GEN_RESET_CNTL 0x00f0 +# define SOFT_RESET_GUI 0x00000001 +# define SOFT_RESET_VCLK 0x00000100 +# define SOFT_RESET_PCLK 0x00000200 +# define SOFT_RESET_ECP 0x00000400 +# define SOFT_RESET_DISPENG_XCLK 0x00000800 +# define SOFT_RESET_MEMCTLR_XCLK 0x00001000 +#endif +#define CONFIG_MEMSIZE 0x00F8 +#define CONFIG_APER_0_BASE 0x0100 +#define CONFIG_APER_1_BASE 0x0104 +#define CONFIG_APER_SIZE 0x0108 +#define CONFIG_REG_1_BASE 0x010C +#define CONFIG_REG_APER_SIZE 0x0110 +#define PAD_AGPINPUT_DELAY 0x0164 +#define PAD_CTLR_STRENGTH 0x0168 +#define PAD_CTLR_UPDATE 0x016C +#define AGP_CNTL 0x0174 +# define AGP_APER_SIZE_256MB (0x00 << 0) +# define AGP_APER_SIZE_128MB (0x20 << 0) +# define AGP_APER_SIZE_64MB (0x30 << 0) +# define AGP_APER_SIZE_32MB (0x38 << 0) +# define AGP_APER_SIZE_16MB (0x3c << 0) +# define AGP_APER_SIZE_8MB (0x3e << 0) +# define AGP_APER_SIZE_4MB (0x3f << 0) +# define AGP_APER_SIZE_MASK (0x3f << 0) +#define AMCGPIO_A_REG 0x01a0 +#define AMCGPIO_EN_REG 0x01a8 +#define AMCGPIO_MASK 0x0194 +#define AMCGPIO_Y_REG 0x01a4 +/*#define BM_STATUS 0x0160*/ +#define MPP_TB_CONFIG 0x01c0 /* ? */ +#define MPP_GP_CONFIG 0x01c8 /* ? */ +#define VENDOR_ID 0x0F00 +#define DEVICE_ID 0x0F02 +#define COMMAND 0x0F04 +#define STATUS 0x0F06 +#define REVISION_ID 0x0F08 +#define REGPROG_INF 0x0F09 +#define SUB_CLASS 0x0F0A +#define CACHE_LINE 0x0F0C +#define LATENCY 0x0F0D +#define HEADER 0x0F0E +#define BIST 0x0F0F +#define REG_MEM_BASE 0x0F10 +#define REG_IO_BASE 0x0F14 +#define REG_REG_BASE 0x0F18 +#define ADAPTER_ID 0x0F2C +#define BIOS_ROM 0x0F30 +#define CAPABILITIES_PTR 0x0F34 +#define INTERRUPT_LINE 0x0F3C +#define INTERRUPT_PIN 0x0F3D +#define MIN_GRANT 0x0F3E +#define MAX_LATENCY 0x0F3F +#define ADAPTER_ID_W 0x0F4C +#define PMI_CAP_ID 0x0F50 +#define PMI_NXT_CAP_PTR 0x0F51 +#define PMI_PMC_REG 0x0F52 +#define PM_STATUS 0x0F54 +#define PMI_DATA 0x0F57 +#define AGP_CAP_ID 0x0F58 +#define AGP_STATUS 0x0F5C +# define AGP_1X_MODE 0x01 +# define AGP_2X_MODE 0x02 +# define AGP_4X_MODE 0x04 +# define AGP_MODE_MASK 0x07 +#define AGP_COMMAND 0x0F60 + +/* Video muxer unit */ +#define VIDEOMUX_CNTL 0x0190 +#define VIPPAD_MASK 0x0198 +#define VIPPAD1_A 0x01AC +#define VIPPAD1_EN 0x01B0 +#define VIPPAD1_Y 0x01B4 + +#define AIC_CTRL 0x01D0 +#define AIC_STAT 0x01D4 +#define AIC_PT_BASE 0x01D8 +#define AIC_LO_ADDR 0x01DC +#define AIC_HI_ADDR 0x01E0 +#define AIC_TLB_ADDR 0x01E4 +#define AIC_TLB_DATA 0x01E8 +#define DAC_CNTL 0x0058 +/* DAC_CNTL bit constants */ +# define DAC_8BIT_EN 0x00000100 +# define DAC_4BPP_PIX_ORDER 0x00000200 +# define DAC_CRC_EN 0x00080000 +# define DAC_MASK_ALL (0xff << 24) +# define DAC_VGA_ADR_EN (1 << 13) +# define DAC_RANGE_CNTL (3 << 0) +# define DAC_BLANKING (1 << 2) +#define DAC_CNTL2 0x007c +/* DAC_CNTL2 bit constants */ +# define DAC2_DAC_CLK_SEL (1 << 0) +# define DAC2_DAC2_CLK_SEL (1 << 1) +# define DAC2_PALETTE_ACC_CTL (1 << 5) +#define TV_DAC_CNTL 0x088c +/* TV_DAC_CNTL bit constants */ +# define TV_DAC_STD_MASK 0x0300 +# define TV_DAC_RDACPD (1 << 24) +# define TV_DAC_GDACPD (1 << 25) +# define TV_DAC_BDACPD (1 << 26) +#define CRTC_GEN_CNTL 0x0050 +/* CRTC_GEN_CNTL bit constants */ +# define CRTC_DBL_SCAN_EN 0x00000001 +# define CRTC_INTERLACE_EN (1 << 1) +# define CRTC_CSYNC_EN (1 << 4) +# define CRTC_CUR_EN 0x00010000 +# define CRTC_CUR_MODE_MASK (7 << 17) +# define CRTC_ICON_EN (1 << 20) +# define CRTC_EXT_DISP_EN (1 << 24) +# define CRTC_EN (1 << 25) +# define CRTC_DISP_REQ_EN_B (1 << 26) +#define CRTC2_GEN_CNTL 0x03f8 +/* CRTC2_GEN_CNTL bit constants */ +# define CRTC2_DBL_SCAN_EN (1 << 0) +# define CRTC2_INTERLACE_EN (1 << 1) +# define CRTC2_SYNC_TRISTAT (1 << 4) +# define CRTC2_HSYNC_TRISTAT (1 << 5) +# define CRTC2_VSYNC_TRISTAT (1 << 6) +# define CRTC2_CRT2_ON (1 << 7) +# define CRTC2_ICON_EN (1 << 15) +# define CRTC2_CUR_EN (1 << 16) +# define CRTC2_CUR_MODE_MASK (7 << 20) +# define CRTC2_DISP_DIS (1 << 23) +# define CRTC2_EN (1 << 25) +# define CRTC2_DISP_REQ_EN_B (1 << 26) +# define CRTC2_HSYNC_DIS (1 << 28) +# define CRTC2_VSYNC_DIS (1 << 29) +#define MEM_CNTL 0x0140 +/* MEM_CNTL bit constants */ +# define MEM_CTLR_STATUS_IDLE 0x00000000 +# define MEM_CTLR_STATUS_BUSY 0x00100000 +# define MEM_SEQNCR_STATUS_IDLE 0x00000000 +# define MEM_SEQNCR_STATUS_BUSY 0x00200000 +# define MEM_ARBITER_STATUS_IDLE 0x00000000 +# define MEM_ARBITER_STATUS_BUSY 0x00400000 +# define MEM_REQ_UNLOCK 0x00000000 +# define MEM_REQ_LOCK 0x00800000 +#define EXT_MEM_CNTL 0x0144 +#define MC_AGP_LOCATION 0x014C +#define MEM_IO_CNTL_A0 0x0178 +#define MEM_INIT_LATENCY_TIMER 0x0154 +#define MEM_SDRAM_MODE_REG 0x0158 +#define AGP_BASE 0x0170 +#ifdef RAGE128 +#define PCI_GART_PAGE 0x017c +#define PC_NGUI_MODE 0x0180 +#define PC_NGUI_CTLSTAT 0x0184 +# define PC_FLUSH_GUI (3 << 0) +# define PC_RI_GUI (1 << 2) +# define PC_FLUSH_ALL 0x00ff +# define PC_BUSY (1 << 31) +#define PC_MISC_CNTL 0x0188 +#else +#define MEM_IO_CNTL_A1 0x017C +#define MEM_IO_CNTL_B0 0x0180 +#define MEM_IO_CNTL_B1 0x0184 +#define MC_DEBUG 0x0188 +#endif +#define MC_STATUS 0x0150 +#define MEM_IO_OE_CNTL 0x018C +#define MC_FB_LOCATION 0x0148 +#define HOST_PATH_CNTL 0x0130 +#define MEM_VGA_WP_SEL 0x0038 +#define MEM_VGA_RP_SEL 0x003C +#define HDP_DEBUG 0x0138 +#define SW_SEMAPHORE 0x013C +#define SURFACE_CNTL 0x0B00 +/* SURFACE_CNTL bit constants */ +# define SURF_TRANSLATION_DIS (1 << 8) +# define NONSURF_AP0_SWP_16BPP (1 << 20) +# define NONSURF_AP0_SWP_32BPP (2 << 20) +#define SURFACE0_LOWER_BOUND 0x0B04 +#define SURFACE1_LOWER_BOUND 0x0B14 +#define SURFACE2_LOWER_BOUND 0x0B24 +#define SURFACE3_LOWER_BOUND 0x0B34 +#define SURFACE4_LOWER_BOUND 0x0B44 +#define SURFACE5_LOWER_BOUND 0x0B54 +#define SURFACE6_LOWER_BOUND 0x0B64 +#define SURFACE7_LOWER_BOUND 0x0B74 +#define SURFACE0_UPPER_BOUND 0x0B08 +#define SURFACE1_UPPER_BOUND 0x0B18 +#define SURFACE2_UPPER_BOUND 0x0B28 +#define SURFACE3_UPPER_BOUND 0x0B38 +#define SURFACE4_UPPER_BOUND 0x0B48 +#define SURFACE5_UPPER_BOUND 0x0B58 +#define SURFACE6_UPPER_BOUND 0x0B68 +#define SURFACE7_UPPER_BOUND 0x0B78 +#define SURFACE0_INFO 0x0B0C +#define SURFACE1_INFO 0x0B1C +#define SURFACE2_INFO 0x0B2C +#define SURFACE3_INFO 0x0B3C +#define SURFACE4_INFO 0x0B4C +#define SURFACE5_INFO 0x0B5C +#define SURFACE6_INFO 0x0B6C +#define SURFACE7_INFO 0x0B7C +#define SURFACE_ACCESS_FLAGS 0x0BF8 +#define SURFACE_ACCESS_CLR 0x0BFC +#define GEN_INT_CNTL 0x0040 +#define GEN_INT_STATUS 0x0044 +# define VSYNC_INT_AK (1 << 2) +# define VSYNC_INT (1 << 2) +#define CRTC_EXT_CNTL 0x0054 +/* CRTC_EXT_CNTL bit constants */ +# define CRTC_VGA_XOVERSCAN (1 << 0) +# define VGA_ATI_LINEAR 0x00000008 +# define VGA_128KAP_PAGING 0x00000010 +# define XCRT_CNT_EN (1 << 6) +# define CRTC_HSYNC_DIS (1 << 8) +# define CRTC_VSYNC_DIS (1 << 9) +# define CRTC_DISPLAY_DIS (1 << 10) +# define CRTC_SYNC_TRISTAT (1 << 11) +# define CRTC_CRT_ON (1 << 15) +#define CRTC_EXT_CNTL_DPMS_BYTE 0x0055 +# define CRTC_HSYNC_DIS_BYTE (1 << 0) +# define CRTC_VSYNC_DIS_BYTE (1 << 1) +# define CRTC_DISPLAY_DIS_BYTE (1 << 2) +#define RB3D_CNTL 0x1C3C +#define WAIT_UNTIL 0x1720 +#define ISYNC_CNTL 0x1724 +#define RBBM_GUICNTL 0x172C +#define RBBM_STATUS 0x0E40 +# define RBBM_FIFOCNT_MASK 0x007f +# define RBBM_ACTIVE (1 << 31) +#define RBBM_STATUS_alt_1 0x1740 +#define RBBM_CNTL 0x00EC +#define RBBM_CNTL_alt_1 0x0E44 +#define RBBM_SOFT_RESET 0x00F0 +/* RBBM_SOFT_RESET bit constants */ +# define SOFT_RESET_CP (1 << 0) +# define SOFT_RESET_HI (1 << 1) +# define SOFT_RESET_SE (1 << 2) +# define SOFT_RESET_RE (1 << 3) +# define SOFT_RESET_PP (1 << 4) +# define SOFT_RESET_E2 (1 << 5) +# define SOFT_RESET_RB (1 << 6) +# define SOFT_RESET_HDP (1 << 7) +#define RBBM_SOFT_RESET_alt_1 0x0E48 +#define NQWAIT_UNTIL 0x0E50 +#define RBBM_DEBUG 0x0E6C +#define RBBM_CMDFIFO_ADDR 0x0E70 +#define RBBM_CMDFIFO_DATAL 0x0E74 +#define RBBM_CMDFIFO_DATAH 0x0E78 +#define RBBM_CMDFIFO_STAT 0x0E7C +#define CRTC_STATUS 0x005C +/* CRTC_STATUS bit constants */ +# define CRTC_VBLANK 0x00000001 +# define CRTC_VBLANK_SAVE ( 1 << 1) +#define GPIO_VGA_DDC 0x0060 +#define GPIO_DVI_DDC 0x0064 +#define GPIO_MONID 0x0068 +#define PALETTE_INDEX 0x00B0 +#define PALETTE_DATA 0x00B4 +#define PALETTE_30_DATA 0x00B8 +#define CRTC_H_TOTAL_DISP 0x0200 +# define CRTC_H_TOTAL (0x03ff << 0) +# define CRTC_H_TOTAL_SHIFT 0 +# define CRTC_H_DISP (0x01ff << 16) +# define CRTC_H_DISP_SHIFT 16 +#define CRTC2_H_TOTAL_DISP 0x0300 +# define CRTC2_H_TOTAL (0x03ff << 0) +# define CRTC2_H_TOTAL_SHIFT 0 +# define CRTC2_H_DISP (0x01ff << 16) +# define CRTC2_H_DISP_SHIFT 16 +#define CRTC_H_SYNC_STRT_WID 0x0204 +# define CRTC_H_SYNC_STRT_PIX (0x07 << 0) +# define CRTC_H_SYNC_STRT_CHAR (0x3ff << 3) +# define CRTC_H_SYNC_STRT_CHAR_SHIFT 3 +# define CRTC_H_SYNC_WID (0x3f << 16) +# define CRTC_H_SYNC_WID_SHIFT 16 +# define CRTC_H_SYNC_POL (1 << 23) +#define CRTC2_H_SYNC_STRT_WID 0x0304 +# define CRTC2_H_SYNC_STRT_PIX (0x07 << 0) +# define CRTC2_H_SYNC_STRT_CHAR (0x3ff << 3) +# define CRTC2_H_SYNC_STRT_CHAR_SHIFT 3 +# define CRTC2_H_SYNC_WID (0x3f << 16) +# define CRTC2_H_SYNC_WID_SHIFT 16 +# define CRTC2_H_SYNC_POL (1 << 23) +#define CRTC_V_TOTAL_DISP 0x0208 +# define CRTC_V_TOTAL (0x07ff << 0) +# define CRTC_V_TOTAL_SHIFT 0 +# define CRTC_V_DISP (0x07ff << 16) +# define CRTC_V_DISP_SHIFT 16 +#define CRTC2_V_TOTAL_DISP 0x0308 +# define CRTC2_V_TOTAL (0x07ff << 0) +# define CRTC2_V_TOTAL_SHIFT 0 +# define CRTC2_V_DISP (0x07ff << 16) +# define CRTC2_V_DISP_SHIFT 16 +#define CRTC_V_SYNC_STRT_WID 0x020C +# define CRTC_V_SYNC_STRT (0x7ff << 0) +# define CRTC_V_SYNC_STRT_SHIFT 0 +# define CRTC_V_SYNC_WID (0x1f << 16) +# define CRTC_V_SYNC_WID_SHIFT 16 +# define CRTC_V_SYNC_POL (1 << 23) +#define CRTC2_V_SYNC_STRT_WID 0x030C +# define CRTC2_V_SYNC_STRT (0x7ff << 0) +# define CRTC2_V_SYNC_STRT_SHIFT 0 +# define CRTC2_V_SYNC_WID (0x1f << 16) +# define CRTC2_V_SYNC_WID_SHIFT 16 +# define CRTC2_V_SYNC_POL (1 << 23) +#define CRTC_VLINE_CRNT_VLINE 0x0210 +# define CRTC_CRNT_VLINE_MASK (0x7ff << 16) +#define CRTC2_VLINE_CRNT_VLINE 0x0310 +#define CRTC_CRNT_FRAME 0x0214 +#define CRTC2_CRNT_FRAME 0x0314 +#define CRTC_GUI_TRIG_VLINE 0x0218 +#define CRTC2_GUI_TRIG_VLINE 0x0318 +#define CRTC_DEBUG 0x021C +#define CRTC2_DEBUG 0x031C +#define CRTC_OFFSET_RIGHT 0x0220 +#define CRTC_OFFSET 0x0224 +#define CRTC2_OFFSET 0x0324 +#define CRTC_OFFSET_CNTL 0x0228 +# define CRTC_TILE_EN (1 << 15) +#define CRTC2_OFFSET_CNTL 0x0328 +# define CRTC2_TILE_EN (1 << 15) +#define CRTC_PITCH 0x022C +#define CRTC2_PITCH 0x032C +#define TMDS_CRC 0x02a0 +#define OVR_CLR 0x0230 +#define OVR_WID_LEFT_RIGHT 0x0234 +#define OVR_WID_TOP_BOTTOM 0x0238 +#define DISPLAY_BASE_ADDR 0x023C +#define SNAPSHOT_VH_COUNTS 0x0240 +#define SNAPSHOT_F_COUNT 0x0244 +#define N_VIF_COUNT 0x0248 +#define SNAPSHOT_VIF_COUNT 0x024C +#define FP_CRTC_H_TOTAL_DISP 0x0250 +#define FP_CRTC2_H_TOTAL_DISP 0x0350 +#define FP_CRTC_V_TOTAL_DISP 0x0254 +#define FP_CRTC2_V_TOTAL_DISP 0x0354 +# define FP_CRTC_H_TOTAL_MASK 0x000003ff +# define FP_CRTC_H_DISP_MASK 0x01ff0000 +# define FP_CRTC_V_TOTAL_MASK 0x00000fff +# define FP_CRTC_V_DISP_MASK 0x0fff0000 +# define FP_H_SYNC_STRT_CHAR_MASK 0x00001ff8 +# define FP_H_SYNC_WID_MASK 0x003f0000 +# define FP_V_SYNC_STRT_MASK 0x00000fff +# define FP_V_SYNC_WID_MASK 0x001f0000 +# define FP_CRTC_H_TOTAL_SHIFT 0x00000000 +# define FP_CRTC_H_DISP_SHIFT 0x00000010 +# define FP_CRTC_V_TOTAL_SHIFT 0x00000000 +# define FP_CRTC_V_DISP_SHIFT 0x00000010 +# define FP_H_SYNC_STRT_CHAR_SHIFT 0x00000003 +# define FP_H_SYNC_WID_SHIFT 0x00000010 +# define FP_V_SYNC_STRT_SHIFT 0x00000000 +# define FP_V_SYNC_WID_SHIFT 0x00000010 +#define CRT_CRTC_H_SYNC_STRT_WID 0x0258 +#define CRT_CRTC_V_SYNC_STRT_WID 0x025C +#define CUR_OFFSET 0x0260 +#define CUR_HORZ_VERT_POSN 0x0264 +#define CUR_HORZ_VERT_OFF 0x0268 +/* CUR_OFFSET, CUR_HORZ_VERT_POSN, CUR_HORZ_VERT_OFF bit constants */ +# define CUR_LOCK 0x80000000 +#define CUR_CLR0 0x026C +#define CUR_CLR1 0x0270 +#define CUR2_OFFSET 0x0360 +#define CUR2_HORZ_VERT_POSN 0x0364 +#define CUR2_HORZ_VERT_OFF 0x0368 +# define CUR2_LOCK (1 << 31) +#define CUR2_CLR0 0x036c +#define CUR2_CLR1 0x0370 +#define FP_HORZ_VERT_ACTIVE 0x0278 +#define CRTC_MORE_CNTL 0x027C +#define DAC_EXT_CNTL 0x0280 +#define FP_GEN_CNTL 0x0284 +/* FP_GEN_CNTL bit constants */ +# define FP_FPON (1 << 0) +# define FP_TMDS_EN (1 << 2) +# define FP_EN_TMDS (1 << 7) +# define FP_DETECT_SENSE (1 << 8) +# define FP_SEL_CRTC2 (1 << 13) +# define FP_CRTC_DONT_SHADOW_HPAR (1 << 15) +# define FP_CRTC_DONT_SHADOW_VPAR (1 << 16) +# define FP_CRTC_DONT_SHADOW_HEND (1 << 17) +# define FP_CRTC_USE_SHADOW_VEND (1 << 18) +# define FP_RMX_HVSYNC_CONTROL_EN (1 << 20) +# define FP_DFP_SYNC_SEL (1 << 21) +# define FP_CRTC_LOCK_8DOT (1 << 22) +# define FP_CRT_SYNC_SEL (1 << 23) +# define FP_USE_SHADOW_EN (1 << 24) +# define FP_CRT_SYNC_ALT (1 << 26) +#define FP2_GEN_CNTL 0x0288 +/* FP2_GEN_CNTL bit constants */ +# define FP2_FPON (1 << 0) +# define FP2_TMDS_EN (1 << 2) +# define FP2_EN_TMDS (1 << 7) +# define FP2_DETECT_SENSE (1 << 8) +# define FP2_SEL_CRTC2 (1 << 13) +# define FP2_FP_POL (1 << 16) +# define FP2_LP_POL (1 << 17) +# define FP2_SCK_POL (1 << 18) +# define FP2_LCD_CNTL_MASK (7 << 19) +# define FP2_PAD_FLOP_EN (1 << 22) +# define FP2_CRC_EN (1 << 23) +# define FP2_CRC_READ_EN (1 << 24) +#define FP_HORZ_STRETCH 0x028C +#define FP_HORZ2_STRETCH 0x038C +# define HORZ_STRETCH_RATIO_MASK 0xffff +# define HORZ_STRETCH_RATIO_MAX 4096 +# define HORZ_PANEL_SIZE (0x1ff << 16) +# define HORZ_PANEL_SHIFT 16 +# define HORZ_STRETCH_PIXREP (0 << 25) +# define HORZ_STRETCH_BLEND (1 << 26) +# define HORZ_STRETCH_ENABLE (1 << 25) +# define HORZ_AUTO_RATIO (1 << 27) +# define HORZ_FP_LOOP_STRETCH (0x7 << 28) +# define HORZ_AUTO_RATIO_INC (1 << 31) +#define FP_VERT_STRETCH 0x0290 +#define FP_VERT2_STRETCH 0x0390 +# define VERT_PANEL_SIZE (0xfff << 12) +# define VERT_PANEL_SHIFT 12 +# define VERT_STRETCH_RATIO_MASK 0xfff +# define VERT_STRETCH_RATIO_SHIFT 0 +# define VERT_STRETCH_RATIO_MAX 4096 +# define VERT_STRETCH_ENABLE (1 << 25) +# define VERT_STRETCH_LINEREP (0 << 26) +# define VERT_STRETCH_BLEND (1 << 26) +# define VERT_AUTO_RATIO_EN (1 << 27) +# define VERT_STRETCH_RESERVED 0xf1000000 +#define FP_H_SYNC_STRT_WID 0x02C4 +#define FP_H2_SYNC_STRT_WID 0x03C4 +#define FP_V_SYNC_STRT_WID 0x02C8 +#define FP_V2_SYNC_STRT_WID 0x03C8 +#define LVDS_GEN_CNTL 0x02d0 +# define LVDS_ON (1 << 0) +# define LVDS_DISPLAY_DIS (1 << 1) +# define LVDS_PANEL_TYPE (1 << 2) +# define LVDS_PANEL_FORMAT (1 << 3) +# define LVDS_EN (1 << 7) +# define LVDS_DIGON (1 << 18) +# define LVDS_BLON (1 << 19) +# define LVDS_SEL_CRTC2 (1 << 23) +#define LVDS_PLL_CNTL 0x02d4 +# define HSYNC_DELAY_SHIFT 28 +# define HSYNC_DELAY_MASK (0xf << 28) +#define AUX_WINDOW_HORZ_CNTL 0x02D8 +#define AUX_WINDOW_VERT_CNTL 0x02DC +#define DDA_CONFIG 0x02e0 +#define DDA_ON_OFF 0x02e4 + +#define GRPH_BUFFER_CNTL 0x02F0 +#define VGA_BUFFER_CNTL 0x02F4 + +/* first overlay unit (there is only one) */ + +#define OV0_Y_X_START 0x0400 +#define OV0_Y_X_END 0x0404 +#define OV0_PIPELINE_CNTL 0x0408 +#define OV0_EXCLUSIVE_HORZ 0x0408 +# define EXCL_HORZ_START_MASK 0x000000ff +# define EXCL_HORZ_END_MASK 0x0000ff00 +# define EXCL_HORZ_BACK_PORCH_MASK 0x00ff0000 +# define EXCL_HORZ_EXCLUSIVE_EN 0x80000000 +#define OV0_EXCLUSIVE_VERT 0x040C +# define EXCL_VERT_START_MASK 0x000003ff +# define EXCL_VERT_END_MASK 0x03ff0000 +#define OV0_REG_LOAD_CNTL 0x0410 +# define REG_LD_CTL_LOCK 0x00000001L +# define REG_LD_CTL_VBLANK_DURING_LOCK 0x00000002L +# define REG_LD_CTL_STALL_GUI_UNTIL_FLIP 0x00000004L +# define REG_LD_CTL_LOCK_READBACK 0x00000008L +#define OV0_SCALE_CNTL 0x0420 +# define SCALER_PIX_EXPAND 0x00000001L +# define SCALER_Y2R_TEMP 0x00000002L +#ifdef RAGE128 +# define SCALER_HORZ_PICK_NEAREST 0x00000003L +# define SCALER_VERT_PICK_NEAREST 0x00000004L +#else +# define SCALER_HORZ_PICK_NEAREST 0x00000004L +# define SCALER_VERT_PICK_NEAREST 0x00000008L +#endif +# define SCALER_SIGNED_UV 0x00000010L +# define SCALER_GAMMA_SEL_MASK 0x00000060L +# define SCALER_GAMMA_SEL_BRIGHT 0x00000000L +# define SCALER_GAMMA_SEL_G22 0x00000020L +# define SCALER_GAMMA_SEL_G18 0x00000040L +# define SCALER_GAMMA_SEL_G14 0x00000060L +# define SCALER_COMCORE_SHIFT_UP_ONE 0x00000080L +# define SCALER_SURFAC_FORMAT 0x00000f00L +# define SCALER_SOURCE_UNK0 0x00000000L /* 2 bpp ??? */ +# define SCALER_SOURCE_UNK1 0x00000100L /* 4 bpp ??? */ +# define SCALER_SOURCE_UNK2 0x00000200L /* 8 bpp ??? */ +# define SCALER_SOURCE_15BPP 0x00000300L +# define SCALER_SOURCE_16BPP 0x00000400L +/*# define SCALER_SOURCE_24BPP 0x00000500L*/ +# define SCALER_SOURCE_32BPP 0x00000600L +# define SCALER_SOURCE_UNK3 0x00000700L /* 8BPP_RGB332 ??? */ +# define SCALER_SOURCE_UNK4 0x00000800L /* 8BPP_Y8 ??? */ +# define SCALER_SOURCE_YUV9 0x00000900L /* 8BPP_RGB8 */ +# define SCALER_SOURCE_YUV12 0x00000A00L +# define SCALER_SOURCE_VYUY422 0x00000B00L +# define SCALER_SOURCE_YVYU422 0x00000C00L +# define SCALER_SOURCE_UNK5 0x00000D00L /* ??? */ +# define SCALER_SOURCE_UNK6 0x00000E00L /* 32BPP_AYUV444 */ +# define SCALER_SOURCE_UNK7 0x00000F00L /* 16BPP_ARGB4444 */ +# define SCALER_ADAPTIVE_DEINT 0x00001000L +# define R200_SCALER_TEMPORAL_DEINT 0x00002000L +# define SCALER_UNKNOWN_FLAG1 0x00004000L /* ??? */ +# define SCALER_SMART_SWITCH 0x00008000L +#ifdef RAGE128 +# define SCALER_BURST_PER_PLANE 0x00ff0000L +#else +# define SCALER_BURST_PER_PLANE 0x007f0000L +#endif +# define SCALER_DOUBLE_BUFFER 0x01000000L +# define SCALER_UNKNOWN_FLAG3 0x02000000L /* ??? */ +# define SCALER_UNKNOWN_FLAG4 0x04000000L /* ??? */ +# define SCALER_DIS_LIMIT 0x08000000L +#ifdef RAGE128 +# define SCALER_PRG_LOAD_START 0x10000000L +#endif +# define SCALER_INT_EMU 0x20000000L +# define SCALER_ENABLE 0x40000000L +# define SCALER_SOFT_RESET 0x80000000L +#define OV0_V_INC 0x0424 +#define OV0_P1_V_ACCUM_INIT 0x0428 +# define OV0_P1_MAX_LN_IN_PER_LN_OUT 0x00000003L +# define OV0_P1_V_ACCUM_INIT_MASK 0x01ff8000L +#define OV0_P23_V_ACCUM_INIT 0x042C +# define OV0_P23_MAX_LN_IN_PER_LN_OUT 0x00000003L +# define OV0_P23_V_ACCUM_INIT_MASK 0x01ff8000L +#define OV0_P1_BLANK_LINES_AT_TOP 0x0430 +# define P1_BLNK_LN_AT_TOP_M1_MASK 0x00000fffL +# define P1_ACTIVE_LINES_M1 0x0fff0000L +#define OV0_P23_BLANK_LINES_AT_TOP 0x0434 +# define P23_BLNK_LN_AT_TOP_M1_MASK 0x000007ffL +# define P23_ACTIVE_LINES_M1 0x07ff0000L +#ifndef RAGE128 +#define OV0_BASE_ADDR 0x043C +#endif +#define OV0_VID_BUF0_BASE_ADRS 0x0440 +# define VIF_BUF0_PITCH_SEL 0x00000001L +# define VIF_BUF0_TILE_ADRS 0x00000002L +# define VIF_BUF0_BASE_ADRS_MASK 0x03fffff0L +# define VIF_BUF0_1ST_LINE_LSBS_MASK 0x48000000L +#define OV0_VID_BUF1_BASE_ADRS 0x0444 +# define VIF_BUF1_PITCH_SEL 0x00000001L +# define VIF_BUF1_TILE_ADRS 0x00000002L +# define VIF_BUF1_BASE_ADRS_MASK 0x03fffff0L +# define VIF_BUF1_1ST_LINE_LSBS_MASK 0x48000000L +#define OV0_VID_BUF2_BASE_ADRS 0x0448 +# define VIF_BUF2_PITCH_SEL 0x00000001L +# define VIF_BUF2_TILE_ADRS 0x00000002L +# define VIF_BUF2_BASE_ADRS_MASK 0x03fffff0L +# define VIF_BUF2_1ST_LINE_LSBS_MASK 0x48000000L +#define OV0_VID_BUF3_BASE_ADRS 0x044C +# define VIF_BUF3_PITCH_SEL 0x00000001L +# define VIF_BUF3_TILE_ADRS 0x00000002L +# define VIF_BUF3_BASE_ADRS_MASK 0x03fffff0L +# define VIF_BUF3_1ST_LINE_LSBS_MASK 0x48000000L +#define OV0_VID_BUF4_BASE_ADRS 0x0450 +# define VIF_BUF4_PITCH_SEL 0x00000001L +# define VIF_BUF4_TILE_ADRS 0x00000002L +# define VIF_BUF4_BASE_ADRS_MASK 0x03fffff0L +# define VIF_BUF4_1ST_LINE_LSBS_MASK 0x48000000L +#define OV0_VID_BUF5_BASE_ADRS 0x0454 +# define VIF_BUF5_PITCH_SEL 0x00000001L +# define VIF_BUF5_TILE_ADRS 0x00000002L +# define VIF_BUF5_BASE_ADRS_MASK 0x03fffff0L +# define VIF_BUF5_1ST_LINE_LSBS_MASK 0x48000000L +#define OV0_VID_BUF_PITCH0_VALUE 0x0460 +#define OV0_VID_BUF_PITCH1_VALUE 0x0464 +#define OV0_AUTO_FLIP_CNTL 0x0470 +# define OV0_AUTO_FLIP_CNTL_SOFT_BUF_NUM 0x00000007 +# define OV0_AUTO_FLIP_CNTL_SOFT_REPEAT_FIELD 0x00000008 +# define OV0_AUTO_FLIP_CNTL_SOFT_BUF_ODD 0x00000010 +# define OV0_AUTO_FLIP_CNTL_IGNORE_REPEAT_FIELD 0x00000020 +# define OV0_AUTO_FLIP_CNTL_SOFT_EOF_TOGGLE 0x00000040 +# define OV0_AUTO_FLIP_CNTL_VID_PORT_SELECT 0x00000300 +# define OV0_AUTO_FLIP_CNTL_P1_FIRST_LINE_EVEN 0x00010000 +# define OV0_AUTO_FLIP_CNTL_SHIFT_EVEN_DOWN 0x00040000 +# define OV0_AUTO_FLIP_CNTL_SHIFT_ODD_DOWN 0x00080000 +# define OV0_AUTO_FLIP_CNTL_FIELD_POL_SOURCE 0x00800000 +#define OV0_DEINTERLACE_PATTERN 0x0474 +#define OV0_SUBMIT_HISTORY 0x0478 +#define OV0_H_INC 0x0480 +#define OV0_STEP_BY 0x0484 +#define OV0_P1_H_ACCUM_INIT 0x0488 +#define OV0_P23_H_ACCUM_INIT 0x048C +#define OV0_P1_X_START_END 0x0494 +#define OV0_P2_X_START_END 0x0498 +#define OV0_P3_X_START_END 0x049C +#define OV0_FILTER_CNTL 0x04A0 +# define FILTER_PROGRAMMABLE_COEF 0x00000000 +# define FILTER_HARD_SCALE_HORZ_Y 0x00000001 +# define FILTER_HARD_SCALE_HORZ_UV 0x00000002 +# define FILTER_HARD_SCALE_VERT_Y 0x00000004 +# define FILTER_HARD_SCALE_VERT_UV 0x00000008 +# define FILTER_HARDCODED_COEF 0x0000000F +# define FILTER_COEF_MASK 0x0000000F +/* When bit is set hard coded coefficients are used. */ + +/* + Top quality 4x4-tap filtered vertical and horizontal scaler. + It allows up to 64:1 upscaling and downscaling without + performance or quality degradation. +*/ +#define OV0_FOUR_TAP_COEF_0 0x04B0 +# define OV0_FOUR_TAP_PHASE_0_TAP_0 0x0000000F +# define OV0_FOUR_TAP_PHASE_0_TAP_1 0x00007F00 +# define OV0_FOUR_TAP_PHASE_0_TAP_2 0x007F0000 +# define OV0_FOUR_TAP_PHASE_0_TAP_3 0x0F000000 +#define OV0_FOUR_TAP_COEF_1 0x04B4 +# define OV0_FOUR_TAP_PHASE_1_5_TAP_0 0x0000000F +# define OV0_FOUR_TAP_PHASE_1_5_TAP_1 0x00007F00 +# define OV0_FOUR_TAP_PHASE_1_5_TAP_2 0x007F0000 +# define OV0_FOUR_TAP_PHASE_1_5_TAP_3 0x0F000000 +#define OV0_FOUR_TAP_COEF_2 0x04B8 +# define OV0_FOUR_TAP_PHASE_2_6_TAP_0 0x0000000F +# define OV0_FOUR_TAP_PHASE_2_6_TAP_1 0x00007F00 +# define OV0_FOUR_TAP_PHASE_2_6_TAP_2 0x007F0000 +# define OV0_FOUR_TAP_PHASE_2_6_TAP_3 0x0F000000 +#define OV0_FOUR_TAP_COEF_3 0x04BC +# define OV0_FOUR_TAP_PHASE_3_7_TAP_0 0x0000000F +# define OV0_FOUR_TAP_PHASE_3_7_TAP_1 0x00007F00 +# define OV0_FOUR_TAP_PHASE_3_7_TAP_2 0x007F0000 +# define OV0_FOUR_TAP_PHASE_3_7_TAP_3 0x0F000000 +#define OV0_FOUR_TAP_COEF_4 0x04C0 +# define OV0_FOUR_TAP_PHASE_4_TAP_0 0x0000000F +# define OV0_FOUR_TAP_PHASE_4_TAP_1 0x00007F00 +# define OV0_FOUR_TAP_PHASE_4_TAP_2 0x007F0000 +# define OV0_FOUR_TAP_PHASE_4_TAP_3 0x0F000000 +/* 0th_tap means that the left most of top most pixel in a set of four will + be multiplied by this coefficient. */ + +#define OV0_FLAG_CNTL 0x04DC +#ifdef RAGE128 +#define OV0_COLOUR_CNTL 0x04E0 +# define COLOUR_CNTL_BRIGHTNESS 0x0000007F +# define COLOUR_CNTL_SATURATION 0x001F1F00 +#else +/* NB: radeons have no COLOUR_CNTL register */ +#define OV0_SLICE_CNTL 0x04E0 +# define SLICE_CNTL_DISABLE 0x40000000 +#endif +/* Video and graphics keys allow alpha blending, color correction + and many other video effects */ +#define OV0_VID_KEY_CLR 0x04E4 +#define OV0_VID_KEY_MSK 0x04E8 +#define OV0_GRAPHICS_KEY_CLR 0x04EC +#define OV0_GRAPHICS_KEY_MSK 0x04F0 +#define OV0_KEY_CNTL 0x04F4 +#ifdef RAGE128 +# define VIDEO_KEY_FN_MASK 0x00000007L +# define VIDEO_KEY_FN_FALSE 0x00000000L +# define VIDEO_KEY_FN_TRUE 0x00000001L +# define VIDEO_KEY_FN_EQ 0x00000004L +# define VIDEO_KEY_FN_NE 0x00000005L +# define GRAPHIC_KEY_FN_MASK 0x00000070L +# define GRAPHIC_KEY_FN_FALSE 0x00000000L +# define GRAPHIC_KEY_FN_TRUE 0x00000010L +# define GRAPHIC_KEY_FN_EQ 0x00000040L +# define GRAPHIC_KEY_FN_NE 0x00000050L +#else +# define VIDEO_KEY_FN_MASK 0x00000003L +# define VIDEO_KEY_FN_FALSE 0x00000000L +# define VIDEO_KEY_FN_TRUE 0x00000001L +# define VIDEO_KEY_FN_EQ 0x00000002L +# define VIDEO_KEY_FN_NE 0x00000003L +# define GRAPHIC_KEY_FN_MASK 0x00000030L +# define GRAPHIC_KEY_FN_FALSE 0x00000000L +# define GRAPHIC_KEY_FN_TRUE 0x00000010L +# define GRAPHIC_KEY_FN_EQ 0x00000020L +# define GRAPHIC_KEY_FN_NE 0x00000030L +#endif +# define CMP_MIX_MASK 0x00000100L +# define CMP_MIX_OR 0x00000000L +# define CMP_MIX_AND 0x00000100L +#define OV0_TEST 0x04F8 +#define OV0_LIN_TRANS_A 0x0D20 +#define OV0_LIN_TRANS_B 0x0D24 +#define OV0_LIN_TRANS_C 0x0D28 +#define OV0_LIN_TRANS_D 0x0D2C +#define OV0_LIN_TRANS_E 0x0D30 +#define OV0_LIN_TRANS_F 0x0D34 +#define OV0_GAMMA_0_F 0x0D40 +#define OV0_GAMMA_10_1F 0x0D44 +#define OV0_GAMMA_20_3F 0x0D48 +#define OV0_GAMMA_40_7F 0x0D4C +/* These registers exist on R200 only */ +#define OV0_GAMMA_80_BF 0x0E00 +#define OV0_GAMMA_C0_FF 0x0E04 +#define OV0_GAMMA_100_13F 0x0E08 +#define OV0_GAMMA_140_17F 0x0E0C +#define OV0_GAMMA_180_1BF 0x0E10 +#define OV0_GAMMA_1C0_1FF 0x0E14 +#define OV0_GAMMA_200_23F 0x0E18 +#define OV0_GAMMA_240_27F 0x0E1C +#define OV0_GAMMA_280_2BF 0x0E20 +#define OV0_GAMMA_2C0_2FF 0x0E24 +#define OV0_GAMMA_300_33F 0x0E28 +#define OV0_GAMMA_340_37F 0x0E2C +/* End of R200 specific definitions */ +#define OV0_GAMMA_380_3BF 0x0D50 +#define OV0_GAMMA_3C0_3FF 0x0D54 + +/* + IDCT ENGINE: + It's MPEG-2 hardware decoder which incorporates run-level decode, de-zigzag + and IDCT into an IDCT engine to complement the motion compensation engine. +*/ +#define IDCT_RUNS 0x1F80 +#define IDCT_LEVELS 0x1F84 +#define IDCT_AUTH_CONTROL 0x1F88 +#define IDCT_AUTH 0x1F8C +#define IDCT_CONTROL 0x1FBC + +#define SE_MC_SRC2_CNTL 0x19D4 +#define SE_MC_SRC1_CNTL 0x19D8 +#define SE_MC_DST_CNTL 0x19DC +#define SE_MC_CNTL_START 0x19E0 +#ifndef RAGE128 +#define SE_MC_BUF_BASE 0x19E4 +#define PP_MC_CONTEXT 0x19E8 +#define PP_MISC 0x1C14 +#endif +/* + SUBPICTURE UNIT: + Decompressing, scaling and alpha blending the compressed bitmap on the fly. + Provide optimal DVD subpicture qualtity. +*/ +#define SUBPIC_CNTL 0x0540 +#define SUBPIC_DEFCOLCON 0x0544 +#define SUBPIC_Y_X_START 0x054C +#define SUBPIC_Y_X_END 0x0550 +#define SUBPIC_V_INC 0x0554 +#define SUBPIC_H_INC 0x0558 +#define SUBPIC_BUF0_OFFSET 0x055C +#define SUBPIC_BUF1_OFFSET 0x0560 +#define SUBPIC_LC0_OFFSET 0x0564 +#define SUBPIC_LC1_OFFSET 0x0568 +#define SUBPIC_PITCH 0x056C +#define SUBPIC_BTN_HLI_COLCON 0x0570 +#define SUBPIC_BTN_HLI_Y_X_START 0x0574 +#define SUBPIC_BTN_HLI_Y_X_END 0x0578 +#define SUBPIC_PALETTE_INDEX 0x057C +#define SUBPIC_PALETTE_DATA 0x0580 +#define SUBPIC_H_ACCUM_INIT 0x0584 +#define SUBPIC_V_ACCUM_INIT 0x0588 + +#define CP_RB_BASE 0x0700 +#define CP_RB_CNTL 0x0704 +#define CP_RB_RPTR_ADDR 0x070C +#define CP_RB_RPTR 0x0710 +#define CP_RB_WPTR 0x0714 +#define CP_RB_WPTR_DELAY 0x0718 +#define CP_IB_BASE 0x0738 +#define CP_IB_BUFSZ 0x073C +#define CP_CSQ_CNTL 0x0740 +#define SCRATCH_UMSK 0x0770 +#define SCRATCH_ADDR 0x0774 +#define DMA_GUI_TABLE_ADDR 0x0780 +# define DMA_GUI_COMMAND__BYTE_COUNT_MASK 0x001fffff +# define DMA_GUI_COMMAND__INTDIS 0x40000000 +# define DMA_GUI_COMMAND__EOL 0x80000000 +#define DMA_GUI_SRC_ADDR 0x0784 +#define DMA_GUI_DST_ADDR 0x0788 +#define DMA_GUI_COMMAND 0x078C +#define DMA_GUI_STATUS 0x0790 +#define DMA_GUI_ACT_DSCRPTR 0x0794 +#define DMA_VID_TABLE_ADDR 0x07A0 +#define DMA_VID_SRC_ADDR 0x07A4 +#define DMA_VID_DST_ADDR 0x07A8 +#define DMA_VID_COMMAND 0x07AC +#define DMA_VID_STATUS 0x07B0 +#define DMA_VID_ACT_DSCRPTR 0x07B4 +#define CP_ME_CNTL 0x07D0 +#define CP_ME_RAM_ADDR 0x07D4 +#define CP_ME_RAM_RADDR 0x07D8 +#define CP_ME_RAM_DATAH 0x07DC +#define CP_ME_RAM_DATAL 0x07E0 +#define CP_CSQ_ADDR 0x07F0 +#define CP_CSQ_DATA 0x07F4 +#define CP_CSQ_STAT 0x07F8 + +#define DISP_MISC_CNTL 0x0D00 +# define SOFT_RESET_GRPH_PP (1 << 0) +#define DAC_MACRO_CNTL 0x0D04 +#define DISP_PWR_MAN 0x0D08 +#define DISP_TEST_DEBUG_CNTL 0x0D10 +#define DISP_HW_DEBUG 0x0D14 +#define DAC_CRC_SIG1 0x0D18 +#define DAC_CRC_SIG2 0x0D1C + +/* first capture unit */ + +#define VID_BUFFER_CONTROL 0x0900 +#define CAP_INT_CNTL 0x0908 +#define CAP_INT_STATUS 0x090C +#define FCP_CNTL 0x0910 +# define FCP_CNTL__PCICLK 0 +# define FCP_CNTL__PCLK 1 +# define FCP_CNTL__PCLKb 2 +# define FCP_CNTL__HREF 3 +# define FCP_CNTL__GND 4 +# define FCP_CNTL__HREFb 5 + +#define CAP0_BUF0_OFFSET 0x0920 +#define CAP0_BUF1_OFFSET 0x0924 +#define CAP0_BUF0_EVEN_OFFSET 0x0928 +#define CAP0_BUF1_EVEN_OFFSET 0x092C +#define CAP0_BUF_PITCH 0x0930 +#define CAP0_V_WINDOW 0x0934 +#define CAP0_H_WINDOW 0x0938 +#define CAP0_VBI0_OFFSET 0x093C +#define CAP0_VBI1_OFFSET 0x0940 +#define CAP0_VBI_V_WINDOW 0x0944 +#define CAP0_VBI_H_WINDOW 0x0948 +#define CAP0_PORT_MODE_CNTL 0x094C +#define CAP0_TRIG_CNTL 0x0950 +#define CAP0_DEBUG 0x0954 +#define CAP0_CONFIG 0x0958 +# define CAP0_CONFIG_CONTINUOS 0x00000001 +# define CAP0_CONFIG_START_FIELD_EVEN 0x00000002 +# define CAP0_CONFIG_START_BUF_GET 0x00000004 +# define CAP0_CONFIG_START_BUF_SET 0x00000008 +# define CAP0_CONFIG_BUF_TYPE_ALT 0x00000010 +# define CAP0_CONFIG_BUF_TYPE_FRAME 0x00000020 +# define CAP0_CONFIG_ONESHOT_MODE_FRAME 0x00000040 +# define CAP0_CONFIG_BUF_MODE_DOUBLE 0x00000080 +# define CAP0_CONFIG_BUF_MODE_TRIPLE 0x00000100 +# define CAP0_CONFIG_MIRROR_EN 0x00000200 +# define CAP0_CONFIG_ONESHOT_MIRROR_EN 0x00000400 +# define CAP0_CONFIG_VIDEO_SIGNED_UV 0x00000800 +# define CAP0_CONFIG_ANC_DECODE_EN 0x00001000 +# define CAP0_CONFIG_VBI_EN 0x00002000 +# define CAP0_CONFIG_SOFT_PULL_DOWN_EN 0x00004000 +# define CAP0_CONFIG_VIP_EXTEND_FLAG_EN 0x00008000 +# define CAP0_CONFIG_FAKE_FIELD_EN 0x00010000 +# define CAP0_CONFIG_ODD_ONE_MORE_LINE 0x00020000 +# define CAP0_CONFIG_EVEN_ONE_MORE_LINE 0x00040000 +# define CAP0_CONFIG_HORZ_DIVIDE_2 0x00080000 +# define CAP0_CONFIG_HORZ_DIVIDE_4 0x00100000 +# define CAP0_CONFIG_VERT_DIVIDE_2 0x00200000 +# define CAP0_CONFIG_VERT_DIVIDE_4 0x00400000 +# define CAP0_CONFIG_FORMAT_BROOKTREE 0x00000000 +# define CAP0_CONFIG_FORMAT_CCIR656 0x00800000 +# define CAP0_CONFIG_FORMAT_ZV 0x01000000 +# define CAP0_CONFIG_FORMAT_VIP 0x01800000 +# define CAP0_CONFIG_FORMAT_TRANSPORT 0x02000000 +# define CAP0_CONFIG_HORZ_DECIMATOR 0x04000000 +# define CAP0_CONFIG_VIDEO_IN_YVYU422 0x00000000 +# define CAP0_CONFIG_VIDEO_IN_VYUY422 0x20000000 +# define CAP0_CONFIG_VBI_DIVIDE_2 0x40000000 +# define CAP0_CONFIG_VBI_DIVIDE_4 0x80000000 +#define CAP0_ANC_ODD_OFFSET 0x095C +#define CAP0_ANC_EVEN_OFFSET 0x0960 +#define CAP0_ANC_H_WINDOW 0x0964 +#define CAP0_VIDEO_SYNC_TEST 0x0968 +#define CAP0_ONESHOT_BUF_OFFSET 0x096C +#define CAP0_BUF_STATUS 0x0970 +#ifdef RAGE128 +#define CAP0_DWNSC_XRATIO 0x0978 +#define CAP0_XSHARPNESS 0x097C +#else +/* #define CAP0_DWNSC_XRATIO 0x0978 */ +/* #define CAP0_XSHARPNESS 0x097C */ +#endif +#define CAP0_VBI2_OFFSET 0x0980 +#define CAP0_VBI3_OFFSET 0x0984 +#define CAP0_ANC2_OFFSET 0x0988 +#define CAP0_ANC3_OFFSET 0x098C + +/* second capture unit */ + +#define CAP1_BUF0_OFFSET 0x0990 +#define CAP1_BUF1_OFFSET 0x0994 +#define CAP1_BUF0_EVEN_OFFSET 0x0998 +#define CAP1_BUF1_EVEN_OFFSET 0x099C + +#define CAP1_BUF_PITCH 0x09A0 +#define CAP1_V_WINDOW 0x09A4 +#define CAP1_H_WINDOW 0x09A8 +#define CAP1_VBI_ODD_OFFSET 0x09AC +#define CAP1_VBI_EVEN_OFFSET 0x09B0 +#define CAP1_VBI_V_WINDOW 0x09B4 +#define CAP1_VBI_H_WINDOW 0x09B8 +#define CAP1_PORT_MODE_CNTL 0x09BC +#define CAP1_TRIG_CNTL 0x09C0 +#define CAP1_DEBUG 0x09C4 +#define CAP1_CONFIG 0x09C8 +#define CAP1_ANC_ODD_OFFSET 0x09CC +#define CAP1_ANC_EVEN_OFFSET 0x09D0 +#define CAP1_ANC_H_WINDOW 0x09D4 +#define CAP1_VIDEO_SYNC_TEST 0x09D8 +#define CAP1_ONESHOT_BUF_OFFSET 0x09DC +#define CAP1_BUF_STATUS 0x09E0 +#define CAP1_DWNSC_XRATIO 0x09E8 +#define CAP1_XSHARPNESS 0x09EC + +#define DISP_MERGE_CNTL 0x0D60 +#define DISP_OUTPUT_CNTL 0x0D64 +# define DISP_DAC_SOURCE_MASK 0x03 +# define DISP_DAC_SOURCE_CRTC2 0x01 +#define DISP_LIN_TRANS_GRPH_A 0x0D80 +#define DISP_LIN_TRANS_GRPH_B 0x0D84 +#define DISP_LIN_TRANS_GRPH_C 0x0D88 +#define DISP_LIN_TRANS_GRPH_D 0x0D8C +#define DISP_LIN_TRANS_GRPH_E 0x0D90 +#define DISP_LIN_TRANS_GRPH_F 0x0D94 +#define DISP_LIN_TRANS_VID_A 0x0D98 +#define DISP_LIN_TRANS_VID_B 0x0D9C +#define DISP_LIN_TRANS_VID_C 0x0DA0 +#define DISP_LIN_TRANS_VID_D 0x0DA4 +#define DISP_LIN_TRANS_VID_E 0x0DA8 +#define DISP_LIN_TRANS_VID_F 0x0DAC +#define RMX_HORZ_FILTER_0TAP_COEF 0x0DB0 +#define RMX_HORZ_FILTER_1TAP_COEF 0x0DB4 +#define RMX_HORZ_FILTER_2TAP_COEF 0x0DB8 +#define RMX_HORZ_PHASE 0x0DBC +#define DAC_EMBEDDED_SYNC_CNTL 0x0DC0 +#define DAC_BROAD_PULSE 0x0DC4 +#define DAC_SKEW_CLKS 0x0DC8 +#define DAC_INCR 0x0DCC +#define DAC_NEG_SYNC_LEVEL 0x0DD0 +#define DAC_POS_SYNC_LEVEL 0x0DD4 +#define DAC_BLANK_LEVEL 0x0DD8 +#define CLOCK_CNTL_INDEX 0x0008 +/* CLOCK_CNTL_INDEX bit constants */ +# define PLL_WR_EN 0x00000080 +# define PLL_DIV_SEL (3 << 8) +# define PLL2_DIV_SEL_MASK ~(3 << 8) +#define CLOCK_CNTL_DATA 0x000C +#define CP_RB_CNTL 0x0704 +#define CP_RB_BASE 0x0700 +#define CP_RB_RPTR_ADDR 0x070C +#define CP_RB_RPTR 0x0710 +#define CP_RB_WPTR 0x0714 +#define CP_RB_WPTR_DELAY 0x0718 +#define CP_IB_BASE 0x0738 +#define CP_IB_BUFSZ 0x073C +#define SCRATCH_REG0 0x15E0 +#define GUI_SCRATCH_REG0 0x15E0 +#define SCRATCH_REG1 0x15E4 +#define GUI_SCRATCH_REG1 0x15E4 +#define SCRATCH_REG2 0x15E8 +#define GUI_SCRATCH_REG2 0x15E8 +#define SCRATCH_REG3 0x15EC +#define GUI_SCRATCH_REG3 0x15EC +#define SCRATCH_REG4 0x15F0 +#define GUI_SCRATCH_REG4 0x15F0 +#define SCRATCH_REG5 0x15F4 +#define GUI_SCRATCH_REG5 0x15F4 +#define SCRATCH_UMSK 0x0770 +#define SCRATCH_ADDR 0x0774 +#define DP_BRUSH_FRGD_CLR 0x147C +#define DP_BRUSH_BKGD_CLR 0x1478 +#define DST_LINE_START 0x1600 +#define DST_LINE_END 0x1604 +#define SRC_OFFSET 0x15AC +#define SRC_PITCH 0x15B0 +#define SRC_TILE 0x1704 +#define SRC_PITCH_OFFSET 0x1428 +#define SRC_X 0x1414 +#define SRC_Y 0x1418 +#define DST_WIDTH_X 0x1588 +#define DST_HEIGHT_WIDTH_8 0x158C +#define SRC_X_Y 0x1590 +#define SRC_Y_X 0x1434 +#define DST_Y_X 0x1438 +#define DST_WIDTH_HEIGHT 0x1598 +#define DST_HEIGHT_WIDTH 0x143c +#ifdef RAGE128 +#define GUI_STAT 0x1740 +# define GUI_FIFOCNT_MASK 0x0fff +# define GUI_ACTIVE (1 << 31) +#endif +#define SRC_CLUT_ADDRESS 0x1780 +#define SRC_CLUT_DATA 0x1784 +#define SRC_CLUT_DATA_RD 0x1788 +#define HOST_DATA0 0x17C0 +#define HOST_DATA1 0x17C4 +#define HOST_DATA2 0x17C8 +#define HOST_DATA3 0x17CC +#define HOST_DATA4 0x17D0 +#define HOST_DATA5 0x17D4 +#define HOST_DATA6 0x17D8 +#define HOST_DATA7 0x17DC +#define HOST_DATA_LAST 0x17E0 +#define DP_SRC_ENDIAN 0x15D4 +#define DP_SRC_FRGD_CLR 0x15D8 +#define DP_SRC_BKGD_CLR 0x15DC +#define DP_WRITE_MASK 0x16cc +#define SC_LEFT 0x1640 +#define SC_RIGHT 0x1644 +#define SC_TOP 0x1648 +#define SC_BOTTOM 0x164C +#define SRC_SC_RIGHT 0x1654 +#define SRC_SC_BOTTOM 0x165C +#define DP_CNTL 0x16C0 +/* DP_CNTL bit constants */ +# define DST_X_RIGHT_TO_LEFT 0x00000000 +# define DST_X_LEFT_TO_RIGHT 0x00000001 +# define DST_Y_BOTTOM_TO_TOP 0x00000000 +# define DST_Y_TOP_TO_BOTTOM 0x00000002 +# define DST_X_MAJOR 0x00000000 +# define DST_Y_MAJOR 0x00000004 +# define DST_X_TILE 0x00000008 +# define DST_Y_TILE 0x00000010 +# define DST_LAST_PEL 0x00000020 +# define DST_TRAIL_X_RIGHT_TO_LEFT 0x00000000 +# define DST_TRAIL_X_LEFT_TO_RIGHT 0x00000040 +# define DST_TRAP_FILL_RIGHT_TO_LEFT 0x00000000 +# define DST_TRAP_FILL_LEFT_TO_RIGHT 0x00000080 +# define DST_BRES_SIGN 0x00000100 +# define DST_HOST_BIG_ENDIAN_EN 0x00000200 +# define DST_POLYLINE_NONLAST 0x00008000 +# define DST_RASTER_STALL 0x00010000 +# define DST_POLY_EDGE 0x00040000 +#define DP_CNTL_XDIR_YDIR_YMAJOR 0x16D0 +/* DP_CNTL_XDIR_YDIR_YMAJOR bit constants (short version of DP_CNTL) */ +# define DST_X_MAJOR_S 0x00000000 +# define DST_Y_MAJOR_S 0x00000001 +# define DST_Y_BOTTOM_TO_TOP_S 0x00000000 +# define DST_Y_TOP_TO_BOTTOM_S 0x00008000 +# define DST_X_RIGHT_TO_LEFT_S 0x00000000 +# define DST_X_LEFT_TO_RIGHT_S 0x80000000 +#define DP_DATATYPE 0x16C4 +/* DP_DATATYPE bit constants */ +# define DST_8BPP 0x00000002 +# define DST_15BPP 0x00000003 +# define DST_16BPP 0x00000004 +# define DST_24BPP 0x00000005 +# define DST_32BPP 0x00000006 +# define DST_8BPP_RGB332 0x00000007 +# define DST_8BPP_Y8 0x00000008 +# define DST_8BPP_RGB8 0x00000009 +# define DST_16BPP_VYUY422 0x0000000b +# define DST_16BPP_YVYU422 0x0000000c +# define DST_32BPP_AYUV444 0x0000000e +# define DST_16BPP_ARGB4444 0x0000000f +# define BRUSH_SOLIDCOLOR 0x00000d00 +# define SRC_MONO 0x00000000 +# define SRC_MONO_LBKGD 0x00010000 +# define SRC_DSTCOLOR 0x00030000 +# define BYTE_ORDER_MSB_TO_LSB 0x00000000 +# define BYTE_ORDER_LSB_TO_MSB 0x40000000 +# define DP_CONVERSION_TEMP 0x80000000 +# define HOST_BIG_ENDIAN_EN (1 << 29) +#define DP_MIX 0x16C8 +/* DP_MIX bit constants */ +# define DP_SRC_RECT 0x00000200 +# define DP_SRC_HOST 0x00000300 +# define DP_SRC_HOST_BYTEALIGN 0x00000400 +#define DP_WRITE_MSK 0x16CC +#define DP_XOP 0x17F8 +#define CLR_CMP_CLR_SRC 0x15C4 +#define CLR_CMP_CLR_DST 0x15C8 +#define CLR_CMP_CNTL 0x15C0 +/* CLR_CMP_CNTL bit constants */ +# define COMPARE_SRC_FALSE 0x00000000 +# define COMPARE_SRC_TRUE 0x00000001 +# define COMPARE_SRC_NOT_EQUAL 0x00000004 +# define COMPARE_SRC_EQUAL 0x00000005 +# define COMPARE_SRC_EQUAL_FLIP 0x00000007 +# define COMPARE_DST_FALSE 0x00000000 +# define COMPARE_DST_TRUE 0x00000100 +# define COMPARE_DST_NOT_EQUAL 0x00000400 +# define COMPARE_DST_EQUAL 0x00000500 +# define COMPARE_DESTINATION 0x00000000 +# define COMPARE_SOURCE 0x01000000 +# define COMPARE_SRC_AND_DST 0x02000000 +#define CLR_CMP_MSK 0x15CC +#define DSTCACHE_MODE 0x1710 +#define DSTCACHE_CTLSTAT 0x1714 +/* DSTCACHE_CTLSTAT bit constants */ +# define RB2D_DC_FLUSH (3 << 0) +# define RB2D_DC_FLUSH_ALL 0xf +# define RB2D_DC_BUSY (1 << 31) +#define DEFAULT_OFFSET 0x16e0 +#define DEFAULT_PITCH_OFFSET 0x16E0 +#define DEFAULT_SC_BOTTOM_RIGHT 0x16E8 +/* DEFAULT_SC_BOTTOM_RIGHT bit constants */ +# define DEFAULT_SC_RIGHT_MAX (0x1fff << 0) +# define DEFAULT_SC_BOTTOM_MAX (0x1fff << 16) +#define DP_GUI_MASTER_CNTL 0x146C +/* DP_GUI_MASTER_CNTL bit constants */ +# define GMC_SRC_PITCH_OFFSET_DEFAULT 0x00000000 +# define GMC_SRC_PITCH_OFFSET_LEAVE 0x00000001 +# define GMC_DST_PITCH_OFFSET_DEFAULT 0x00000000 +# define GMC_DST_PITCH_OFFSET_LEAVE 0x00000002 +# define GMC_SRC_CLIP_DEFAULT 0x00000000 +# define GMC_SRC_CLIP_LEAVE 0x00000004 +# define GMC_DST_CLIP_DEFAULT 0x00000000 +# define GMC_DST_CLIP_LEAVE 0x00000008 +# define GMC_BRUSH_8x8MONO 0x00000000 +# define GMC_BRUSH_8x8MONO_LBKGD 0x00000010 +# define GMC_BRUSH_8x1MONO 0x00000020 +# define GMC_BRUSH_8x1MONO_LBKGD 0x00000030 +# define GMC_BRUSH_1x8MONO 0x00000040 +# define GMC_BRUSH_1x8MONO_LBKGD 0x00000050 +# define GMC_BRUSH_32x1MONO 0x00000060 +# define GMC_BRUSH_32x1MONO_LBKGD 0x00000070 +# define GMC_BRUSH_32x32MONO 0x00000080 +# define GMC_BRUSH_32x32MONO_LBKGD 0x00000090 +# define GMC_BRUSH_8x8COLOR 0x000000a0 +# define GMC_BRUSH_8x1COLOR 0x000000b0 +# define GMC_BRUSH_1x8COLOR 0x000000c0 +# define GMC_BRUSH_SOLID_COLOR 0x000000d0 +# define GMC_DST_8BPP 0x00000200 +# define GMC_DST_15BPP 0x00000300 +# define GMC_DST_16BPP 0x00000400 +# define GMC_DST_24BPP 0x00000500 +# define GMC_DST_32BPP 0x00000600 +# define GMC_DST_8BPP_RGB332 0x00000700 +# define GMC_DST_8BPP_Y8 0x00000800 +# define GMC_DST_8BPP_RGB8 0x00000900 +# define GMC_DST_16BPP_VYUY422 0x00000b00 +# define GMC_DST_16BPP_YVYU422 0x00000c00 +# define GMC_DST_32BPP_AYUV444 0x00000e00 +# define GMC_DST_16BPP_ARGB4444 0x00000f00 +# define GMC_SRC_MONO 0x00000000 +# define GMC_SRC_MONO_LBKGD 0x00001000 +# define GMC_SRC_DSTCOLOR 0x00003000 +# define GMC_BYTE_ORDER_MSB_TO_LSB 0x00000000 +# define GMC_BYTE_ORDER_LSB_TO_MSB 0x00004000 +# define GMC_DP_CONVERSION_TEMP_9300 0x00008000 +# define GMC_DP_CONVERSION_TEMP_6500 0x00000000 +# define GMC_DP_SRC_RECT 0x02000000 +# define GMC_DP_SRC_HOST 0x03000000 +# define GMC_DP_SRC_HOST_BYTEALIGN 0x04000000 +# define GMC_3D_FCN_EN_CLR 0x00000000 +# define GMC_3D_FCN_EN_SET 0x08000000 +# define GMC_DST_CLR_CMP_FCN_LEAVE 0x00000000 +# define GMC_DST_CLR_CMP_FCN_CLEAR 0x10000000 +# define GMC_AUX_CLIP_LEAVE 0x00000000 +# define GMC_AUX_CLIP_CLEAR 0x20000000 +# define GMC_WRITE_MASK_LEAVE 0x00000000 +# define GMC_WRITE_MASK_SET 0x40000000 +# define GMC_CLR_CMP_CNTL_DIS (1 << 28) +# define GMC_SRC_DATATYPE_COLOR (3 << 12) +# define ROP3_S 0x00cc0000 +# define ROP3_SRCCOPY 0x00cc0000 +# define ROP3_P 0x00f00000 +# define ROP3_PATCOPY 0x00f00000 +# define DP_SRC_SOURCE_MASK (7 << 24) +# define GMC_BRUSH_NONE (15 << 4) +# define DP_SRC_SOURCE_MEMORY (2 << 24) +# define GMC_BRUSH_SOLIDCOLOR 0x000000d0 +#define SC_TOP_LEFT 0x16EC +#define SC_BOTTOM_RIGHT 0x16F0 +#define SRC_SC_BOTTOM_RIGHT 0x16F4 +#define RB2D_DSTCACHE_CTLSTAT 0x342C +#define RB2D_DSTCACHE_MODE 0x3428 + +#define BASE_CODE 0x0f0b +#define RADEON_BIOS_0_SCRATCH 0x0010 +#define RADEON_BIOS_1_SCRATCH 0x0014 +#define RADEON_BIOS_2_SCRATCH 0x0018 +#define RADEON_BIOS_3_SCRATCH 0x001c +#define RADEON_BIOS_4_SCRATCH 0x0020 +#define RADEON_BIOS_5_SCRATCH 0x0024 +#define RADEON_BIOS_6_SCRATCH 0x0028 +#define RADEON_BIOS_7_SCRATCH 0x002c + + +#define CLK_PIN_CNTL 0x0001 +#define PPLL_CNTL 0x0002 +# define PPLL_RESET (1 << 0) +# define PPLL_SLEEP (1 << 1) +# define PPLL_ATOMIC_UPDATE_EN (1 << 16) +# define PPLL_VGA_ATOMIC_UPDATE_EN (1 << 17) +# define PPLL_ATOMIC_UPDATE_VSYNC (1 << 18) +#define PPLL_REF_DIV 0x0003 +# define PPLL_REF_DIV_MASK 0x03ff +# define PPLL_ATOMIC_UPDATE_R (1 << 15) /* same as _W */ +# define PPLL_ATOMIC_UPDATE_W (1 << 15) /* same as _R */ +#define PPLL_DIV_0 0x0004 +#define PPLL_DIV_1 0x0005 +#define PPLL_DIV_2 0x0006 +#define PPLL_DIV_3 0x0007 +#define VCLK_ECP_CNTL 0x0008 +# define VCLK_SRC_SEL_MASK 0x03 +# define VCLK_SRC_SEL_CPUCLK 0x00 +# define VCLK_SRC_SEL_PSCANCLK 0x01 +# define VCLK_SRC_SEL_BYTECLK 0x02 +# define VCLK_SRC_SEL_PPLLCLK 0x03 +#define HTOTAL_CNTL 0x0009 +#define HTOTAL2_CNTL 0x002e /* PLL */ +#define M_SPLL_REF_FB_DIV 0x000a +#define AGP_PLL_CNTL 0x000b +#define SPLL_CNTL 0x000c +#define SCLK_CNTL 0x000d +# define DYN_STOP_LAT_MASK 0x00007ff8 +# define CP_MAX_DYN_STOP_LAT 0x0008 +# define SCLK_FORCEON_MASK 0xffff8000 +#define SCLK_MORE_CNTL 0x0035 /* PLL */ +# define SCLK_MORE_FORCEON 0x0700 +#define MPLL_CNTL 0x000e +#ifdef RAGE128 +#define MCLK_CNTL 0x000f /* PLL */ +# define FORCE_GCP (1 << 16) +# define FORCE_PIPE3D_CP (1 << 17) +# define FORCE_RCP (1 << 18) +#else +#define MCLK_CNTL 0x0012 +/* MCLK_CNTL bit constants */ +# define FORCEON_MCLKA (1 << 16) +# define FORCEON_MCLKB (1 << 17) +# define FORCEON_YCLKA (1 << 18) +# define FORCEON_YCLKB (1 << 19) +# define FORCEON_MC (1 << 20) +# define FORCEON_AIC (1 << 21) +#endif +#define PLL_TEST_CNTL 0x0013 +#define P2PLL_CNTL 0x002a /* P2PLL */ +# define P2PLL_RESET (1 << 0) +# define P2PLL_SLEEP (1 << 1) +# define P2PLL_ATOMIC_UPDATE_EN (1 << 16) +# define P2PLL_VGA_ATOMIC_UPDATE_EN (1 << 17) +# define P2PLL_ATOMIC_UPDATE_VSYNC (1 << 18) +#define P2PLL_DIV_0 0x002c +# define P2PLL_FB0_DIV_MASK 0x07ff +# define P2PLL_POST0_DIV_MASK 0x00070000 +#define P2PLL_REF_DIV 0x002B /* PLL */ +# define P2PLL_REF_DIV_MASK 0x03ff +# define P2PLL_ATOMIC_UPDATE_R (1 << 15) /* same as _W */ +# define P2PLL_ATOMIC_UPDATE_W (1 << 15) /* same as _R */ +#define PIXCLKS_CNTL 0x002d +# define PIX2CLK_SRC_SEL_MASK 0x03 +# define PIX2CLK_SRC_SEL_CPUCLK 0x00 +# define PIX2CLK_SRC_SEL_PSCANCLK 0x01 +# define PIX2CLK_SRC_SEL_BYTECLK 0x02 +# define PIX2CLK_SRC_SEL_P2PLLCLK 0x03 + +/* masks */ + +#define CONFIG_MEMSIZE_MASK 0x1f000000 +#define MEM_CFG_TYPE 0x40000000 +#define DST_OFFSET_MASK 0x003fffff +#define DST_PITCH_MASK 0x3fc00000 +#define DEFAULT_TILE_MASK 0xc0000000 +#define PPLL_DIV_SEL_MASK 0x00000300 +#define PPLL_FB3_DIV_MASK 0x000007ff +#define PPLL_POST3_DIV_MASK 0x00070000 + +/* BUS MASTERING */ +#define BM_FRAME_BUF_OFFSET 0xA00 +#define BM_SYSTEM_MEM_ADDR 0xA04 +#define BM_COMMAND 0xA08 +# define BM_INTERRUPT_DIS 0x08000000 +# define BM_TRANSFER_DEST_REG 0x10000000 +# define BM_FORCE_TO_PCI 0x20000000 +# define BM_FRAME_OFFSET_HOLD 0x40000000 +# define BM_END_OF_LIST 0x80000000 +#define BM_STATUS 0xA0c +#define BM_QUEUE_STATUS 0xA10 +#define BM_QUEUE_FREE_STATUS 0xA14 +#define BM_CHUNK_0_VAL 0xA18 +# define BM_PTR_FORCE_TO_PCI 0x00200000 +# define BM_PM4_RD_FORCE_TO_PCI 0x00400000 +# define BM_GLOBAL_FORCE_TO_PCI 0x00800000 +# define BM_VIP3_NOCHUNK 0x10000000 +# define BM_VIP2_NOCHUNK 0x20000000 +# define BM_VIP1_NOCHUNK 0x40000000 +# define BM_VIP0_NOCHUNK 0x80000000 +#define BM_CHUNK_1_VAL 0xA1C +#define BM_VIP0_BUF 0xA20 +# define SYSTEM_TRIGGER_SYSTEM_TO_VIDEO 0x0 +# define SYSTEM_TRIGGER_VIDEO_TO_SYSTEM 0x1 +#define BM_VIP0_ACTIVE 0xA24 +#define BM_VIP1_BUF 0xA30 +#define BM_VIP1_ACTIVE 0xA34 +#define BM_VIP2_BUF 0xA40 +#define BM_VIP2_ACTIVE 0xA44 +#define BM_VIP3_BUF 0xA50 +#define BM_VIP3_ACTIVE 0xA54 +#define BM_VIDCAP_BUF0 0xA60 +#define BM_VIDCAP_BUF1 0xA64 +#define BM_VIDCAP_BUF2 0xA68 +#define BM_VIDCAP_ACTIVE 0xA6c +#define BM_GUI 0xA80 + +/* RAGE THEATER REGISTERS */ + +#define DMA_VIPH0_COMMAND 0x0A00 +#define DMA_VIPH1_COMMAND 0x0A04 +#define DMA_VIPH2_COMMAND 0x0A08 +#define DMA_VIPH3_COMMAND 0x0A0C +#define DMA_VIPH_STATUS 0x0A10 +#define DMA_VIPH_CHUNK_0 0x0A18 +#define DMA_VIPH_CHUNK_1_VAL 0x0A1C +#define DMA_VIP0_TABLE_ADDR 0x0A20 +#define DMA_VIPH0_ACTIVE 0x0A24 +#define DMA_VIP1_TABLE_ADDR 0x0A30 +#define DMA_VIPH1_ACTIVE 0x0A34 +#define DMA_VIP2_TABLE_ADDR 0x0A40 +#define DMA_VIPH2_ACTIVE 0x0A44 +#define DMA_VIP3_TABLE_ADDR 0x0A50 +#define DMA_VIPH3_ACTIVE 0x0A54 +#define DMA_VIPH_ABORT 0x0A88 + +#define VIPH_CH0_DATA 0x0c00 +#define VIPH_CH1_DATA 0x0c04 +#define VIPH_CH2_DATA 0x0c08 +#define VIPH_CH3_DATA 0x0c0c +#define VIPH_CH0_ADDR 0x0c10 +#define VIPH_CH1_ADDR 0x0c14 +#define VIPH_CH2_ADDR 0x0c18 +#define VIPH_CH3_ADDR 0x0c1c +#define VIPH_CH0_SBCNT 0x0c20 +#define VIPH_CH1_SBCNT 0x0c24 +#define VIPH_CH2_SBCNT 0x0c28 +#define VIPH_CH3_SBCNT 0x0c2c +#define VIPH_CH0_ABCNT 0x0c30 +#define VIPH_CH1_ABCNT 0x0c34 +#define VIPH_CH2_ABCNT 0x0c38 +#define VIPH_CH3_ABCNT 0x0c3c +#define VIPH_CONTROL 0x0c40 +#define VIPH_DV_LAT 0x0c44 +#define VIPH_BM_CHUNK 0x0c48 +#define VIPH_DV_INT 0x0c4c +#define VIPH_TIMEOUT_STAT 0x0c50 + +#define VIPH_REG_DATA 0x0084 +#define VIPH_REG_ADDR 0x0080 + +/* Address Space Rage Theatre Registers (VIP Access) */ +#define VIP_VIP_VENDOR_DEVICE_ID 0x0000 +#define VIP_VIP_SUB_VENDOR_DEVICE_ID 0x0004 +#define VIP_VIP_COMMAND_STATUS 0x0008 +#define VIP_VIP_REVISION_ID 0x000c +#define VIP_HW_DEBUG 0x0010 +#define VIP_SW_SCRATCH 0x0014 +#define VIP_I2C_CNTL_0 0x0020 +#define VIP_I2C_CNTL_1 0x0024 +#define VIP_I2C_DATA 0x0028 +#define VIP_INT_CNTL 0x002c +#define VIP_GPIO_INOUT 0x0030 +#define VIP_GPIO_CNTL 0x0034 +#define VIP_CLKOUT_GPIO_CNTL 0x0038 +#define VIP_RIPINTF_PORT_CNTL 0x003c +#define VIP_ADC_CNTL 0x0400 +#define VIP_ADC_DEBUG 0x0404 +#define VIP_STANDARD_SELECT 0x0408 +#define VIP_THERMO2BIN_STATUS 0x040c +#define VIP_COMB_CNTL0 0x0440 +#define VIP_COMB_CNTL1 0x0444 +#define VIP_COMB_CNTL2 0x0448 +#define VIP_COMB_LINE_LENGTH 0x044c +#define VIP_NOISE_CNTL0 0x0450 +#define VIP_HS_PLINE 0x0480 +#define VIP_HS_DTOINC 0x0484 +#define VIP_HS_PLLGAIN 0x0488 +#define VIP_HS_MINMAXWIDTH 0x048c +#define VIP_HS_GENLOCKDELAY 0x0490 +#define VIP_HS_WINDOW_LIMIT 0x0494 +#define VIP_HS_WINDOW_OC_SPEED 0x0498 +#define VIP_HS_PULSE_WIDTH 0x049c +#define VIP_HS_PLL_ERROR 0x04a0 +#define VIP_HS_PLL_FS_PATH 0x04a4 +#define VIP_SG_BLACK_GATE 0x04c0 +#define VIP_SG_SYNCTIP_GATE 0x04c4 +#define VIP_SG_UVGATE_GATE 0x04c8 +#define VIP_LP_AGC_CLAMP_CNTL0 0x0500 +#define VIP_LP_AGC_CLAMP_CNTL1 0x0504 +#define VIP_LP_BRIGHTNESS 0x0508 +#define VIP_LP_CONTRAST 0x050c +#define VIP_LP_SLICE_LIMIT 0x0510 +#define VIP_LP_WPA_CNTL0 0x0514 +#define VIP_LP_WPA_CNTL1 0x0518 +#define VIP_LP_BLACK_LEVEL 0x051c +#define VIP_LP_SLICE_LEVEL 0x0520 +#define VIP_LP_SYNCTIP_LEVEL 0x0524 +#define VIP_LP_VERT_LOCKOUT 0x0528 +#define VIP_VS_DETECTOR_CNTL 0x0540 +#define VIP_VS_BLANKING_CNTL 0x0544 +#define VIP_VS_FIELD_ID_CNTL 0x0548 +#define VIP_VS_COUNTER_CNTL 0x054c +#define VIP_VS_FRAME_TOTAL 0x0550 +#define VIP_VS_LINE_COUNT 0x0554 +#define VIP_CP_PLL_CNTL0 0x0580 +#define VIP_CP_PLL_CNTL1 0x0584 +#define VIP_CP_HUE_CNTL 0x0588 +#define VIP_CP_BURST_GAIN 0x058c +#define VIP_CP_AGC_CNTL 0x0590 +#define VIP_CP_ACTIVE_GAIN 0x0594 +#define VIP_CP_PLL_STATUS0 0x0598 +#define VIP_CP_PLL_STATUS1 0x059c +#define VIP_CP_PLL_STATUS2 0x05a0 +#define VIP_CP_PLL_STATUS3 0x05a4 +#define VIP_CP_PLL_STATUS4 0x05a8 +#define VIP_CP_PLL_STATUS5 0x05ac +#define VIP_CP_PLL_STATUS6 0x05b0 +#define VIP_CP_PLL_STATUS7 0x05b4 +#define VIP_CP_DEBUG_FORCE 0x05b8 +#define VIP_CP_VERT_LOCKOUT 0x05bc +#define VIP_H_ACTIVE_WINDOW 0x05c0 +#define VIP_V_ACTIVE_WINDOW 0x05c4 +#define VIP_H_VBI_WINDOW 0x05c8 +#define VIP_V_VBI_WINDOW 0x05cc +#define VIP_VBI_CONTROL 0x05d0 +#define VIP_DECODER_DEBUG_CNTL 0x05d4 +#define VIP_SINGLE_STEP_DATA 0x05d8 +#define VIP_MASTER_CNTL 0x0040 +#define VIP_RGB_CNTL 0x0048 +#define VIP_CLKOUT_CNTL 0x004c +#define VIP_SYNC_CNTL 0x0050 +#define VIP_I2C_CNTL 0x0054 +#define VIP_HTOTAL 0x0080 +#define VIP_HDISP 0x0084 +#define VIP_HSIZE 0x0088 +#define VIP_HSTART 0x008c +#define VIP_HCOUNT 0x0090 +#define VIP_VTOTAL 0x0094 +#define VIP_VDISP 0x0098 +#define VIP_VCOUNT 0x009c +#define VIP_VFTOTAL 0x00a0 +#define VIP_DFCOUNT 0x00a4 +#define VIP_DFRESTART 0x00a8 +#define VIP_DHRESTART 0x00ac +#define VIP_DVRESTART 0x00b0 +#define VIP_SYNC_SIZE 0x00b4 +#define VIP_TV_PLL_FINE_CNTL 0x00b8 +#define VIP_CRT_PLL_FINE_CNTL 0x00bc +#define VIP_TV_PLL_CNTL 0x00c0 +#define VIP_CRT_PLL_CNTL 0x00c4 +#define VIP_PLL_CNTL0 0x00c8 +#define VIP_PLL_TEST_CNTL 0x00cc +#define VIP_CLOCK_SEL_CNTL 0x00d0 +#define VIP_VIN_PLL_CNTL 0x00d4 +#define VIP_VIN_PLL_FINE_CNTL 0x00d8 +#define VIP_AUD_PLL_CNTL 0x00e0 +#define VIP_AUD_PLL_FINE_CNTL 0x00e4 +#define VIP_AUD_CLK_DIVIDERS 0x00e8 +#define VIP_AUD_DTO_INCREMENTS 0x00ec +#define VIP_L54_PLL_CNTL 0x00f0 +#define VIP_L54_PLL_FINE_CNTL 0x00f4 +#define VIP_L54_DTO_INCREMENTS 0x00f8 +#define VIP_PLL_CNTL1 0x00fc +#define VIP_FRAME_LOCK_CNTL 0x0100 +#define VIP_SYNC_LOCK_CNTL 0x0104 +#define VIP_TVO_SYNC_PAT_ACCUM 0x0108 +#define VIP_TVO_SYNC_THRESHOLD 0x010c +#define VIP_TVO_SYNC_PAT_EXPECT 0x0110 +#define VIP_DELAY_ONE_MAP_A 0x0114 +#define VIP_DELAY_ONE_MAP_B 0x0118 +#define VIP_DELAY_ZERO_MAP_A 0x011c +#define VIP_DELAY_ZERO_MAP_B 0x0120 +#define VIP_TVO_DATA_DELAY_A 0x0140 +#define VIP_TVO_DATA_DELAY_B 0x0144 +#define VIP_HOST_READ_DATA 0x0180 +#define VIP_HOST_WRITE_DATA 0x0184 +#define VIP_HOST_RD_WT_CNTL 0x0188 +#define VIP_VSCALER_CNTL1 0x01c0 +#define VIP_TIMING_CNTL 0x01c4 +#define VIP_VSCALER_CNTL2 0x01c8 +#define VIP_Y_FALL_CNTL 0x01cc +#define VIP_Y_RISE_CNTL 0x01d0 +#define VIP_Y_SAW_TOOTH_CNTL 0x01d4 +#define VIP_UPSAMP_AND_GAIN_CNTL 0x01e0 +#define VIP_GAIN_LIMIT_SETTINGS 0x01e4 +#define VIP_LINEAR_GAIN_SETTINGS 0x01e8 +#define VIP_MODULATOR_CNTL1 0x0200 +#define VIP_MODULATOR_CNTL2 0x0204 +#define VIP_MV_MODE_CNTL 0x0208 +#define VIP_MV_STRIPE_CNTL 0x020c +#define VIP_MV_LEVEL_CNTL1 0x0210 +#define VIP_MV_LEVEL_CNTL2 0x0214 +#define VIP_PRE_DAC_MUX_CNTL 0x0240 +#define VIP_TV_DAC_CNTL 0x0280 +#define VIP_CRC_CNTL 0x02c0 +#define VIP_VIDEO_PORT_SIG 0x02c4 +#define VIP_VBI_CC_CNTL 0x02c8 +#define VIP_VBI_EDS_CNTL 0x02cc +#define VIP_VBI_20BIT_CNTL 0x02d0 +#define VIP_VBI_DTO_CNTL 0x02d4 +#define VIP_VBI_LEVEL_CNTL 0x02d8 +#define VIP_UV_ADR 0x0300 +#define VIP_MV_STATUS 0x0330 +#define VIP_UPSAMP_COEFF0_0 0x0340 +#define VIP_UPSAMP_COEFF0_1 0x0344 +#define VIP_UPSAMP_COEFF0_2 0x0348 +#define VIP_UPSAMP_COEFF1_0 0x034c +#define VIP_UPSAMP_COEFF1_1 0x0350 +#define VIP_UPSAMP_COEFF1_2 0x0354 +#define VIP_UPSAMP_COEFF2_0 0x0358 +#define VIP_UPSAMP_COEFF2_1 0x035c +#define VIP_UPSAMP_COEFF2_2 0x0360 +#define VIP_UPSAMP_COEFF3_0 0x0364 +#define VIP_UPSAMP_COEFF3_1 0x0368 +#define VIP_UPSAMP_COEFF3_2 0x036c +#define VIP_UPSAMP_COEFF4_0 0x0370 +#define VIP_UPSAMP_COEFF4_1 0x0374 +#define VIP_UPSAMP_COEFF4_2 0x0378 +#define VIP_TV_DTO_INCREMENTS 0x0390 +#define VIP_CRT_DTO_INCREMENTS 0x0394 +#define VIP_VSYNC_DIFF_CNTL 0x03a0 +#define VIP_VSYNC_DIFF_LIMITS 0x03a4 +#define VIP_VSYNC_DIFF_RD_DATA 0x03a8 +#define VIP_SCALER_IN_WINDOW 0x0618 +#define VIP_SCALER_OUT_WINDOW 0x061c +#define VIP_H_SCALER_CONTROL 0x0600 +#define VIP_V_SCALER_CONTROL 0x0604 +#define VIP_V_DEINTERLACE_CONTROL 0x0608 +#define VIP_VBI_SCALER_CONTROL 0x060c +#define VIP_DVS_PORT_CTRL 0x0610 +#define VIP_DVS_PORT_READBACK 0x0614 +#define VIP_FIFOA_CONFIG 0x0800 +#define VIP_FIFOB_CONFIG 0x0804 +#define VIP_FIFOC_CONFIG 0x0808 +#define VIP_SPDIF_PORT_CNTL 0x080c +#define VIP_SPDIF_CHANNEL_STAT 0x0810 +#define VIP_SPDIF_AC3_PREAMBLE 0x0814 +#define VIP_I2S_TRANSMIT_CNTL 0x0818 +#define VIP_I2S_RECEIVE_CNTL 0x081c +#define VIP_SPDIF_TX_CNT_REG 0x0820 +#define VIP_IIS_TX_CNT_REG 0x0824 + +/* Status defines */ +#define VIP_BUSY 0 +#define VIP_IDLE 1 +#define VIP_RESET 2 + +#define VIPH_TIMEOUT_STAT__VIPH_REG_STAT 0x00000010 +#define VIPH_TIMEOUT_STAT__VIPH_REG_AK 0x00000010 +#define VIPH_TIMEOUT_STAT__VIPH_REGR_DIS 0x01000000 +#define TEST_DEBUG_CNTL__TEST_DEBUG_OUT_EN 0x00000001 + +#define RT_ATI_ID 0x4D541002 + +/* Register/Field values: */ +#define RT_COMP0 0x0 +#define RT_COMP1 0x1 +#define RT_COMP2 0x2 +#define RT_YF_COMP3 0x3 +#define RT_YR_COMP3 0x4 +#define RT_YCF_COMP4 0x5 +#define RT_YCR_COMP4 0x6 + +/* Video standard defines */ +#define RT_NTSC 0x0 +#define RT_PAL 0x1 +#define RT_SECAM 0x2 +#define extNONE 0x0000 +#define extNTSC 0x0100 +#define extRsvd 0x0200 +#define extPAL 0x0300 +#define extPAL_M 0x0400 +#define extPAL_N 0x0500 +#define extSECAM 0x0600 +#define extPAL_NCOMB 0x0700 +#define extNTSC_J 0x0800 +#define extNTSC_443 0x0900 +#define extPAL_BGHI 0x0A00 +#define extPAL_60 0x0B00 + /* these are used in MSP3430 */ +#define extPAL_DK1 0x0C00 +#define extPAL_AUTO 0x0D00 + +#define RT_FREF_2700 6 +#define RT_FREF_2950 5 + +#define RT_COMPOSITE 0x0 +#define RT_SVIDEO 0x1 + +#define RT_NORM_SHARPNESS 0x03 +#define RT_HIGH_SHARPNESS 0x0F + +#define RT_HUE_PAL_DEF 0x00 + +#define RT_DECINTERLACED 0x1 +#define RT_DECNONINTERLACED 0x0 + +#define NTSC_LINES 525 +#define PAL_SECAM_LINES 625 + +#define RT_ASYNC_ENABLE 0x0 +#define RT_ASYNC_DISABLE 0x1 +#define RT_ASYNC_RESET 0x1 + +#define RT_VINRST_ACTIVE 0x0 +#define RT_VINRST_RESET 0x1 +#define RT_L54RST_RESET 0x1 + +#define RT_REF_CLK 0x0 +#define RT_PLL_VIN_CLK 0x1 + +#define RT_VIN_ASYNC_RST 0x20 +#define RT_DVS_ASYNC_RST 0x80 + +#define RT_ADC_ENABLE 0x0 +#define RT_ADC_DISABLE 0x1 + +#define RT_DVSDIR_IN 0x0 +#define RT_DVSDIR_OUT 0x1 + +#define RT_DVSCLK_HIGH 0x0 +#define RT_DVSCLK_LOW 0x1 + +#define RT_DVSCLK_SEL_8FS 0x0 +#define RT_DVSCLK_SEL_27MHZ 0x1 + +#define RT_DVS_CONTSTREAM 0x1 +#define RT_DVS_NONCONTSTREAM 0x0 + +#define RT_DVSDAT_HIGH 0x0 +#define RT_DVSDAT_LOW 0x1 + +#define RT_ADC_CNTL_DEFAULT 0x03252338 + +/* COMB_CNTL0 FILTER SETTINGS FOR DIFFERENT STANDARDS: */ +#define RT_NTSCM_COMB_CNTL0_COMPOSITE 0x09438090 +#define RT_NTSCM_COMB_CNTL0_SVIDEO 0x48540000 + +#define RT_PAL_COMB_CNTL0_COMPOSITE 0x09438090 +#define RT_PAL_COMB_CNTL0_SVIDEO 0x40348090 + +#define RT_SECAM_COMB_CNTL0_COMPOSITE 0xD0108090 /* instead of orig 0xD0088090 - eric*/ +#define RT_SECAM_COMB_CNTL0_SVIDEO 0x50148090 + +#define RT_PALN_COMB_CNTL0_COMPOSITE 0x09438090 +#define RT_PALN_COMB_CNTL0_SVIDEO 0x40348090 + +#define RT_PALM_COMB_CNTL0_COMPOSITE 0x09438090 +#define RT_PALM_COMB_CNTL0_SVIDEO 0x40348090 +/* End of filter settings. */ + +/* COMB_CNTL1 FILTER SETTINGS FOR DIFFERENT STANDARDS: */ +#define RT_NTSCM_COMB_CNTL1_COMPOSITE 0x00000010 +#define RT_NTSCM_COMB_CNTL1_SVIDEO 0x00000081 + +#define RT_PAL_COMB_CNTL1_COMPOSITE 0x00000010 +#define RT_PAL_COMB_CNTL1_SVIDEO 0x000000A1 + +#define RT_SECAM_COMB_CNTL1_COMPOSITE 0x00000091 +#define RT_SECAM_COMB_CNTL1_SVIDEO 0x00000081 + +#define RT_PALN_COMB_CNTL1_COMPOSITE 0x00000010 +#define RT_PALN_COMB_CNTL1_SVIDEO 0x000000A1 + +#define RT_PALM_COMB_CNTL1_COMPOSITE 0x00000010 +#define RT_PALM_COMB_CNTL1_SVIDEO 0x000000A1 +/* End of filter settings. */ + +/* COMB_CNTL2 FILTER SETTINGS FOR DIFFERENT STANDARDS: */ +#define RT_NTSCM_COMB_CNTL2_COMPOSITE 0x16161010 +#define RT_NTSCM_COMB_CNTL2_SVIDEO 0xFFFFFFFF + +#define RT_PAL_COMB_CNTL2_COMPOSITE 0x06080102 /* instead of 0x16161010 - Ivo */ +#define RT_PAL_COMB_CNTL2_SVIDEO 0x06080102 + +#define RT_SECAM_COMB_CNTL2_COMPOSITE 0xffffffff /* instead of 0x06080102 - eric */ +#define RT_SECAM_COMB_CNTL2_SVIDEO 0x06080102 + +#define RT_PALN_COMB_CNTL2_COMPOSITE 0x06080102 +#define RT_PALN_COMB_CNTL2_SVIDEO 0x06080102 + +#define RT_PALM_COMB_CNTL2_COMPOSITE 0x06080102 +#define RT_PALM_COMB_CNTL2_SVIDEO 0x06080102 +/* End of filter settings. */ + +/* COMB_LINE_LENGTH FILTER SETTINGS FOR DIFFERENT STANDARDS: */ +#define RT_NTSCM_COMB_LENGTH_COMPOSITE 0x0718038A +#define RT_NTSCM_COMB_LENGTH_SVIDEO 0x0718038A + +#define RT_PAL_COMB_LENGTH_COMPOSITE 0x08DA046B +#define RT_PAL_COMB_LENGTH_SVIDEO 0x08DA046B + +#define RT_SECAM_COMB_LENGTH_COMPOSITE 0x08DA046A +#define RT_SECAM_COMB_LENGTH_SVIDEO 0x08DA046A + +#define RT_PALN_COMB_LENGTH_COMPOSITE 0x07260391 +#define RT_PALN_COMB_LENGTH_SVIDEO 0x07260391 + +#define RT_PALM_COMB_LENGTH_COMPOSITE 0x07160389 +#define RT_PALM_COMB_LENGTH_SVIDEO 0x07160389 +/* End of filter settings. */ + +/* LP_AGC_CLAMP_CNTL0 */ +#define RT_NTSCM_SYNCTIP_REF0 0x00000037 +#define RT_NTSCM_SYNCTIP_REF1 0x00000029 +#define RT_NTSCM_CLAMP_REF 0x0000003B +#define RT_NTSCM_PEAKWHITE 0x000000FF +#define RT_NTSCM_VBI_PEAKWHITE 0x000000C2 + +#define RT_NTSCM_WPA_THRESHOLD 0x00000406 +#define RT_NTSCM_WPA_TRIGGER_LO 0x000000B3 + +#define RT_NTSCM_WPA_TRIGGER_HIGH 0x0000021B + +#define RT_NTSCM_LP_LOCKOUT_START 0x00000206 +#define RT_NTSCM_LP_LOCKOUT_END 0x00000021 +#define RT_NTSCM_CH_DTO_INC 0x00400000 +#define RT_NTSCM_CH_PLL_SGAIN 0x00000001 +#define RT_NTSCM_CH_PLL_FGAIN 0x00000002 + +#define RT_NTSCM_CR_BURST_GAIN 0x0000007A +#define RT_NTSCM_CB_BURST_GAIN 0x000000AC + +#define RT_NTSCM_CH_HEIGHT 0x000000CD +#define RT_NTSCM_CH_KILL_LEVEL 0x000000C0 +#define RT_NTSCM_CH_AGC_ERROR_LIM 0x00000002 +#define RT_NTSCM_CH_AGC_FILTER_EN 0x00000000 +#define RT_NTSCM_CH_AGC_LOOP_SPEED 0x00000000 + +#define RT_NTSCM_CRDR_ACTIVE_GAIN 0x0000007A +#define RT_NTSCM_CBDB_ACTIVE_GAIN 0x000000AC + +#define RT_NTSCM_VERT_LOCKOUT_START 0x00000207 +#define RT_NTSCM_VERT_LOCKOUT_END 0x0000000E + +#define RT_NTSCJ_SYNCTIP_REF0 0x00000004 +#define RT_NTSCJ_SYNCTIP_REF1 0x00000012 +#define RT_NTSCJ_CLAMP_REF 0x0000003B +#define RT_NTSCJ_PEAKWHITE 0x000000CB +#define RT_NTSCJ_VBI_PEAKWHITE 0x000000C2 +#define RT_NTSCJ_WPA_THRESHOLD 0x000004B0 +#define RT_NTSCJ_WPA_TRIGGER_LO 0x000000B4 +#define RT_NTSCJ_WPA_TRIGGER_HIGH 0x0000021C +#define RT_NTSCJ_LP_LOCKOUT_START 0x00000206 +#define RT_NTSCJ_LP_LOCKOUT_END 0x00000021 + +#define RT_NTSCJ_CR_BURST_GAIN 0x00000071 +#define RT_NTSCJ_CB_BURST_GAIN 0x0000009F +#define RT_NTSCJ_CH_HEIGHT 0x000000CD +#define RT_NTSCJ_CH_KILL_LEVEL 0x000000C0 +#define RT_NTSCJ_CH_AGC_ERROR_LIM 0x00000002 +#define RT_NTSCJ_CH_AGC_FILTER_EN 0x00000000 +#define RT_NTSCJ_CH_AGC_LOOP_SPEED 0x00000000 + +#define RT_NTSCJ_CRDR_ACTIVE_GAIN 0x00000071 +#define RT_NTSCJ_CBDB_ACTIVE_GAIN 0x0000009F +#define RT_NTSCJ_VERT_LOCKOUT_START 0x00000207 +#define RT_NTSCJ_VERT_LOCKOUT_END 0x0000000E + +#define RT_PAL_SYNCTIP_REF0 0x37 /* instead of 0x00000004 - Ivo */ +#define RT_PAL_SYNCTIP_REF1 0x26 /* instead of 0x0000000F - Ivo */ +#define RT_PAL_CLAMP_REF 0x0000003B +#define RT_PAL_PEAKWHITE 0xFF /* instead of 0x000000C1 - Ivo */ +#define RT_PAL_VBI_PEAKWHITE 0xC6 /* instead of 0x000000C7 - Ivo */ +#define RT_PAL_WPA_THRESHOLD 0x59C /* instead of 0x000006A4 - Ivo */ + +#define RT_PAL_WPA_TRIGGER_LO 0x00000096 +#define RT_PAL_WPA_TRIGGER_HIGH 0x000001C2 +#define RT_PAL_LP_LOCKOUT_START 0x00000263 +#define RT_PAL_LP_LOCKOUT_END 0x0000002C + +#define RT_PAL_CH_DTO_INC 0x00400000 +#define RT_PAL_CH_PLL_SGAIN 1 /* instead of 0x00000002 - Ivo */ +#define RT_PAL_CH_PLL_FGAIN 2 /* instead of 0x00000001 - Ivo */ +#define RT_PAL_CR_BURST_GAIN 0x0000007A +#define RT_PAL_CB_BURST_GAIN 0x000000AB +#define RT_PAL_CH_HEIGHT 0x0000009C +#define RT_PAL_CH_KILL_LEVEL 4 /* instead of 0x00000090 - Ivo */ +#define RT_PAL_CH_AGC_ERROR_LIM 1 /* instead of 0x00000002 - Ivo */ +#define RT_PAL_CH_AGC_FILTER_EN 1 /* instead of 0x00000000 - Ivo */ +#define RT_PAL_CH_AGC_LOOP_SPEED 0x00000000 + +#define RT_PAL_CRDR_ACTIVE_GAIN 0x9E /* instead of 0x0000007A - Ivo */ +#define RT_PAL_CBDB_ACTIVE_GAIN 0xDF /* instead of 0x000000AB - Ivo */ +#define RT_PAL_VERT_LOCKOUT_START 0x00000269 +#define RT_PAL_VERT_LOCKOUT_END 0x00000012 + +#define RT_SECAM_SYNCTIP_REF0 0x37 /* instead of 0x00000004 - Ivo */ +#define RT_SECAM_SYNCTIP_REF1 0x26 /* instead of 0x0000000F - Ivo */ +#define RT_SECAM_CLAMP_REF 0x0000003B +#define RT_SECAM_PEAKWHITE 0xFF /* instead of 0x000000C1 - Ivo */ +#define RT_SECAM_VBI_PEAKWHITE 0xC6 /* instead of 0x000000C7 - Ivo */ +#define RT_SECAM_WPA_THRESHOLD 0x57A /* instead of 0x6A4, instead of 0x0000059C is Ivo's value , -eric*/ + +#define RT_SECAM_WPA_TRIGGER_LO 0x96 /* instead of 0x0000026B - eric */ +#define RT_SECAM_WPA_TRIGGER_HIGH 0x000001C2 +#define RT_SECAM_LP_LOCKOUT_START 0x263 /* instead of 0x0000026B - eric */ +#define RT_SECAM_LP_LOCKOUT_END 0x2b /* instead of 0x0000002C -eric */ + +#define RT_SECAM_CH_DTO_INC 0x003E7A28 +#define RT_SECAM_CH_PLL_SGAIN 0x4 /* instead of 0x00000006 -Volodya */ +#define RT_SECAM_CH_PLL_FGAIN 0x7 /* instead of 0x00000006 -Volodya */ + +#define RT_SECAM_CR_BURST_GAIN 0x1FF /* instead of 0x00000200 -Volodya */ +#define RT_SECAM_CB_BURST_GAIN 0x1FF /* instead of 0x00000200 -Volodya */ +#define RT_SECAM_CH_HEIGHT 0x00000066 +#define RT_SECAM_CH_KILL_LEVEL 0x00000060 +#define RT_SECAM_CH_AGC_ERROR_LIM 0x00000003 +#define RT_SECAM_CH_AGC_FILTER_EN 0x00000000 +#define RT_SECAM_CH_AGC_LOOP_SPEED 0x00000000 + +#define RT_SECAM_CRDR_ACTIVE_GAIN 0x11B /* instead of 0x00000200 - eric */ +#define RT_SECAM_CBDB_ACTIVE_GAIN 0x15A /* instead of 0x00000200 - eric */ +#define RT_SECAM_VERT_LOCKOUT_START 0x00000269 +#define RT_SECAM_VERT_LOCKOUT_END 0x00000012 + +#define RT_PAL_VS_FIELD_BLANK_END 0x2A /* instead of 0x0000002C - Ivo*/ +#define RT_NTSCM_VS_FIELD_BLANK_END 0x0000000A + +#define RT_NTSCM_FIELD_IDLOCATION 0x00000105 +#define RT_PAL_FIELD_IDLOCATION 0x00000137 + +#define RT_NTSCM_H_ACTIVE_START 0x00000070 +#define RT_NTSCM_H_ACTIVE_END 0x00000363 + +#define RT_PAL_H_ACTIVE_START 0x0000009A +#define RT_PAL_H_ACTIVE_END 0x00000439 + +#define RT_NTSCM_V_ACTIVE_START ((22-4)*2+1) +#define RT_NTSCM_V_ACTIVE_END ((22+240-4)*2+1) + +#define RT_PAL_V_ACTIVE_START 0x2E /* instead of 0x00000023 (Same as SECAM) - Ivo */ +#define RT_PAL_V_ACTIVE_END 0x269 /* instead of 0x00000262 - Ivo */ + +/* VBI */ +#define RT_NTSCM_H_VBI_WIND_START 0x00000049 +#define RT_NTSCM_H_VBI_WIND_END 0x00000366 + +#define RT_PAL_H_VBI_WIND_START 0x00000084 +#define RT_PAL_H_VBI_WIND_END 0x0000041F + +#define RT_NTSCM_V_VBI_WIND_START fld_V_VBI_WIND_START_def +#define RT_NTSCM_V_VBI_WIND_END fld_V_VBI_WIND_END_def + +#define RT_PAL_V_VBI_WIND_START 0x8 /* instead of 0x0000000B - Ivo */ +#define RT_PAL_V_VBI_WIND_END 0x2D /* instead of 0x00000022 - Ivo */ + +#define RT_VBI_CAPTURE_EN 0x00000001 /* Enable */ +#define RT_VBI_CAPTURE_DIS 0x00000000 /* Disable */ +#define RT_RAW_CAPTURE 0x00000002 /* Use raw Video Capture. */ + +#define RT_NTSCM_VSYNC_INT_TRIGGER 0x2AA +#define RT_PALSEM_VSYNC_INT_TRIGGER 0x353 + +#define RT_NTSCM_VSYNC_INT_HOLD 0x17 +#define RT_PALSEM_VSYNC_INT_HOLD 0x1C + +#define RT_NTSCM_VS_FIELD_BLANK_START 0x206 +#define RT_PALSEM_VS_FIELD_BLANK_START 0x26D /* instead of 0x26C - Ivo */ + +#define RT_FIELD_FLIP_EN 0x4 +#define RT_V_FIELD_FLIP_INVERTED 0x2000 + +#define RT_NTSCM_H_IN_START 0x70 +#define RT_PAL_H_IN_START 154 /* instead of 144 - Ivo */ +#define RT_SECAM_H_IN_START 0x91 /* instead of 0x9A, Ivo value is 154, instead of 144 - Volodya, - eric */ +#define RT_NTSC_H_ACTIVE_SIZE 744 +#define RT_PAL_H_ACTIVE_SIZE 928 /* instead of 927 - Ivo */ +#define RT_SECAM_H_ACTIVE_SIZE 932 /* instead of 928, instead of 927 - Ivo, - eric */ +#define RT_NTSCM_V_IN_START (0x23) +#define RT_PAL_V_IN_START 44 /* instead of (45-6) - Ivo */ +#define RT_SECAM_V_IN_START 0x2C /* instead of (45-6) - Volodya */ +#define RT_NTSCM_V_ACTIVE_SIZE 480 +#define RT_PAL_V_ACTIVE_SIZE 572 /* instead of 575 - Ivo */ +#define RT_SECAM_V_ACTIVE_SIZE 570 /* instead of 572, instead of 575 - Ivo, - eric */ + +#define RT_NTSCM_WIN_CLOSE_LIMIT 0x4D +#define RT_NTSCJ_WIN_CLOSE_LIMIT 0x4D +#define RT_NTSC443_WIN_CLOSE_LIMIT 0x5F +#define RT_PALM_WIN_CLOSE_LIMIT 0x4D +#define RT_PALN_WIN_CLOSE_LIMIT 0x5F +#define RT_SECAM_WIN_CLOSE_LIMIT 0xC7 /* instead of 0x5F - eric */ + +#define RT_NTSCM_VS_FIELD_BLANK_START 0x206 + +#define RT_NTSCM_HS_PLL_SGAIN 0x5 +#define RT_NTSCM_HS_PLL_FGAIN 0x7 + +#define RT_NTSCM_H_OUT_WIND_WIDTH 0x2F4 +#define RT_NTSCM_V_OUT_WIND_HEIGHT 0xF0 + +#define TV 0x1 +#define LINEIN 0x2 +#define MUTE 0x3 + +#define DEC_COMPOSITE 0 +#define DEC_SVIDEO 1 +#define DEC_TUNER 2 + +#define DEC_NTSC 0 +#define DEC_PAL 1 +#define DEC_SECAM 2 +#define DEC_NTSC_J 8 + +#define DEC_SMOOTH 0 +#define DEC_SHARP 1 + +/* RT Register Field Defaults: */ +#define fld_tmpReg1_def 0x00000000 +#define fld_tmpReg2_def 0x00000001 +#define fld_tmpReg3_def 0x00000002 + +#define fld_LP_CONTRAST_def 0x0000006e +#define fld_LP_BRIGHTNESS_def 0x00003ff0 +#define fld_CP_HUE_CNTL_def 0x00000000 +#define fld_LUMA_FILTER_def 0x00000001 +#define fld_H_SCALE_RATIO_def 0x00010000 +#define fld_H_SHARPNESS_def 0x00000000 + +#define fld_V_SCALE_RATIO_def 0x00000800 +#define fld_V_DEINTERLACE_ON_def 0x00000001 +#define fld_V_BYPSS_def 0x00000000 +#define fld_V_DITHER_ON_def 0x00000001 +#define fld_EVENF_OFFSET_def 0x00000000 +#define fld_ODDF_OFFSET_def 0x00000000 + +#define fld_INTERLACE_DETECTED_def 0x00000000 + +#define fld_VS_LINE_COUNT_def 0x00000000 +#define fld_VS_DETECTED_LINES_def 0x00000000 +#define fld_VS_ITU656_VB_def 0x00000000 + +#define fld_VBI_CC_DATA_def 0x00000000 +#define fld_VBI_CC_WT_def 0x00000000 +#define fld_VBI_CC_WT_ACK_def 0x00000000 +#define fld_VBI_CC_HOLD_def 0x00000000 +#define fld_VBI_DECODE_EN_def 0x00000000 + +#define fld_VBI_CC_DTO_P_def 0x00001802 +#define fld_VBI_20BIT_DTO_P_def 0x0000155c + +#define fld_VBI_CC_LEVEL_def 0x0000003f +#define fld_VBI_20BIT_LEVEL_def 0x00000059 +#define fld_VBI_CLK_RUNIN_GAIN_def 0x0000010f + +#define fld_H_VBI_WIND_START_def 0x00000041 +#define fld_H_VBI_WIND_END_def 0x00000366 + +#define fld_V_VBI_WIND_START_def 0x0D +#define fld_V_VBI_WIND_END_def 0x24 + +#define fld_VBI_20BIT_DATA0_def 0x00000000 +#define fld_VBI_20BIT_DATA1_def 0x00000000 +#define fld_VBI_20BIT_WT_def 0x00000000 +#define fld_VBI_20BIT_WT_ACK_def 0x00000000 +#define fld_VBI_20BIT_HOLD_def 0x00000000 + +#define fld_VBI_CAPTURE_ENABLE_def 0x00000000 + +#define fld_VBI_EDS_DATA_def 0x00000000 +#define fld_VBI_EDS_WT_def 0x00000000 +#define fld_VBI_EDS_WT_ACK_def 0x00000000 +#define fld_VBI_EDS_HOLD_def 0x00000000 + +#define fld_VBI_SCALING_RATIO_def 0x00010000 +#define fld_VBI_ALIGNER_ENABLE_def 0x00000000 + +#define fld_H_ACTIVE_START_def 0x00000070 +#define fld_H_ACTIVE_END_def 0x000002f0 + +#define fld_V_ACTIVE_START_def ((22-4)*2+1) +#define fld_V_ACTIVE_END_def ((22+240-4)*2+2) + +#define fld_CH_HEIGHT_def 0x000000CD +#define fld_CH_KILL_LEVEL_def 0x000000C0 +#define fld_CH_AGC_ERROR_LIM_def 0x00000002 +#define fld_CH_AGC_FILTER_EN_def 0x00000000 +#define fld_CH_AGC_LOOP_SPEED_def 0x00000000 + +#define fld_HUE_ADJ_def 0x00000000 + +#define fld_STANDARD_SEL_def 0x00000000 +#define fld_STANDARD_YC_def 0x00000000 + +#define fld_ADC_PDWN_def 0x00000001 +#define fld_INPUT_SELECT_def 0x00000000 + +#define fld_ADC_PREFLO_def 0x00000003 +#define fld_H_SYNC_PULSE_WIDTH_def 0x00000000 +#define fld_HS_GENLOCKED_def 0x00000000 +#define fld_HS_SYNC_IN_WIN_def 0x00000000 + +#define fld_VIN_ASYNC_RST_def 0x00000001 +#define fld_DVS_ASYNC_RST_def 0x00000001 + +/* Vendor IDs: */ +#define fld_VIP_VENDOR_ID_def 0x00001002 +#define fld_VIP_DEVICE_ID_def 0x00004d54 +#define fld_VIP_REVISION_ID_def 0x00000001 + +/* AGC Delay Register */ +#define fld_BLACK_INT_START_def 0x00000031 +#define fld_BLACK_INT_LENGTH_def 0x0000000f + +#define fld_UV_INT_START_def 0x0000003b +#define fld_U_INT_LENGTH_def 0x0000000f +#define fld_V_INT_LENGTH_def 0x0000000f +#define fld_CRDR_ACTIVE_GAIN_def 0x0000007a +#define fld_CBDB_ACTIVE_GAIN_def 0x000000ac + +#define fld_DVS_DIRECTION_def 0x00000000 +#define fld_DVS_VBI_CARD8_SWAP_def 0x00000000 +#define fld_DVS_CLK_SELECT_def 0x00000000 +#define fld_CONTINUOUS_STREAM_def 0x00000000 +#define fld_DVSOUT_CLK_DRV_def 0x00000001 +#define fld_DVSOUT_DATA_DRV_def 0x00000001 + +#define fld_COMB_CNTL0_def 0x09438090 +#define fld_COMB_CNTL1_def 0x00000010 + +#define fld_COMB_CNTL2_def 0x16161010 +#define fld_COMB_LENGTH_def 0x0718038A + +#define fld_SYNCTIP_REF0_def 0x00000037 +#define fld_SYNCTIP_REF1_def 0x00000029 +#define fld_CLAMP_REF_def 0x0000003B +#define fld_AGC_PEAKWHITE_def 0x000000FF +#define fld_VBI_PEAKWHITE_def 0x000000D2 + +#define fld_WPA_THRESHOLD_def 0x000003B0 + +#define fld_WPA_TRIGGER_LO_def 0x000000B4 +#define fld_WPA_TRIGGER_HIGH_def 0x0000021C + +#define fld_LOCKOUT_START_def 0x00000206 +#define fld_LOCKOUT_END_def 0x00000021 + +#define fld_CH_DTO_INC_def 0x00400000 +#define fld_PLL_SGAIN_def 0x00000001 +#define fld_PLL_FGAIN_def 0x00000002 + +#define fld_CR_BURST_GAIN_def 0x0000007a +#define fld_CB_BURST_GAIN_def 0x000000ac + +#define fld_VERT_LOCKOUT_START_def 0x00000207 +#define fld_VERT_LOCKOUT_END_def 0x0000000E + +#define fld_H_IN_WIND_START_def 0x00000070 +#define fld_V_IN_WIND_START_def 0x00000027 + +#define fld_H_OUT_WIND_WIDTH_def 0x000002f4 + +#define fld_V_OUT_WIND_WIDTH_def 0x000000f0 + +#define fld_HS_LINE_TOTAL_def 0x0000038E + +#define fld_MIN_PULSE_WIDTH_def 0x0000002F +#define fld_MAX_PULSE_WIDTH_def 0x00000046 + +#define fld_WIN_CLOSE_LIMIT_def 0x0000004D +#define fld_WIN_OPEN_LIMIT_def 0x000001B7 + +#define fld_VSYNC_INT_TRIGGER_def 0x000002AA + +#define fld_VSYNC_INT_HOLD_def 0x0000001D + +#define fld_VIN_M0_def 0x00000039 +#define fld_VIN_N0_def 0x0000014c +#define fld_MNFLIP_EN_def 0x00000000 +#define fld_VIN_P_def 0x00000006 +#define fld_REG_CLK_SEL_def 0x00000000 + +#define fld_VIN_M1_def 0x00000000 +#define fld_VIN_N1_def 0x00000000 +#define fld_VIN_DRIVER_SEL_def 0x00000000 +#define fld_VIN_MNFLIP_REQ_def 0x00000000 +#define fld_VIN_MNFLIP_DONE_def 0x00000000 +#define fld_TV_LOCK_TO_VIN_def 0x00000000 +#define fld_TV_P_FOR_WINCLK_def 0x00000004 + +#define fld_VINRST_def 0x00000001 +#define fld_VIN_CLK_SEL_def 0x00000000 + +#define fld_VS_FIELD_BLANK_START_def 0x00000206 + +#define fld_VS_FIELD_BLANK_END_def 0x0000000A + +/*#define fld_VS_FIELD_IDLOCATION_def 0x00000105 */ +#define fld_VS_FIELD_IDLOCATION_def 0x00000001 +#define fld_VS_FRAME_TOTAL_def 0x00000217 + +#define fld_SYNC_TIP_START_def 0x00000372 +#define fld_SYNC_TIP_LENGTH_def 0x0000000F + +#define fld_GAIN_FORCE_DATA_def 0x00000000 +#define fld_GAIN_FORCE_EN_def 0x00000000 +#define fld_I_CLAMP_SEL_def 0x00000003 +#define fld_I_AGC_SEL_def 0x00000001 +#define fld_EXT_CLAMP_CAP_def 0x00000001 +#define fld_EXT_AGC_CAP_def 0x00000001 +#define fld_DECI_DITHER_EN_def 0x00000001 +#define fld_ADC_PREFHI_def 0x00000000 +#define fld_ADC_CH_GAIN_SEL_def 0x00000001 + +#define fld_HS_PLL_SGAIN_def 0x00000003 + +#define fld_NREn_def 0x00000000 +#define fld_NRGainCntl_def 0x00000000 +#define fld_NRBWTresh_def 0x00000000 +#define fld_NRGCTresh_def 0x00000000 +#define fld_NRCoefDespeclMode_def 0x00000000 + +#define fld_GPIO_5_OE_def 0x00000000 +#define fld_GPIO_6_OE_def 0x00000000 + +#define fld_GPIO_5_OUT_def 0x00000000 +#define fld_GPIO_6_OUT_def 0x00000000 + +/* End of field default values. */ + +#endif /* RADEON_H */ diff --git a/src/video_out/vidix/drivers/radeon_vid.c b/src/video_out/vidix/drivers/radeon_vid.c new file mode 100644 index 000000000..91d961a73 --- /dev/null +++ b/src/video_out/vidix/drivers/radeon_vid.c @@ -0,0 +1,1610 @@ +/* + radeon_vid - VIDIX based video driver for Radeon and Rage128 chips + Copyrights 2002 Nick Kurshev. This file is based on sources from + GATOS (gatos.sf.net) and X11 (www.xfree86.org) + Licence: GPL +*/ + +#include +#include +#include +#include +#include +#include +#include "../../libdha/pci_ids.h" +#include "../../libdha/pci_names.h" +#include "../vidix.h" +#include "../fourcc.h" +#include "../../libdha/libdha.h" +#include "radeon.h" + +#ifdef RAGE128 +#define RADEON_MSG "Rage128_vid:" +#define X_ADJUST 0 +#else +#define RADEON_MSG "Radeon_vid:" +#define X_ADJUST 8 +#ifndef RADEON +#define RADEON +#endif +#endif + +static int __verbose = 0; + +typedef struct bes_registers_s +{ + /* base address of yuv framebuffer */ + uint32_t yuv_base; + uint32_t fourcc; + uint32_t dest_bpp; + /* YUV BES registers */ + uint32_t reg_load_cntl; + uint32_t h_inc; + uint32_t step_by; + uint32_t y_x_start; + uint32_t y_x_end; + uint32_t v_inc; + uint32_t p1_blank_lines_at_top; + uint32_t p23_blank_lines_at_top; + uint32_t vid_buf_pitch0_value; + uint32_t vid_buf_pitch1_value; + uint32_t p1_x_start_end; + uint32_t p2_x_start_end; + uint32_t p3_x_start_end; + uint32_t base_addr; + uint32_t vid_buf_base_adrs_y[VID_PLAY_MAXFRAMES]; + uint32_t vid_buf_base_adrs_u[VID_PLAY_MAXFRAMES]; + uint32_t vid_buf_base_adrs_v[VID_PLAY_MAXFRAMES]; + uint32_t vid_nbufs; + + uint32_t p1_v_accum_init; + uint32_t p1_h_accum_init; + uint32_t p23_v_accum_init; + uint32_t p23_h_accum_init; + uint32_t scale_cntl; + uint32_t exclusive_horz; + uint32_t auto_flip_cntl; + uint32_t filter_cntl; + uint32_t key_cntl; + uint32_t test; + /* Configurable stuff */ + int double_buff; + + int brightness; + int saturation; + + int ckey_on; + uint32_t graphics_key_clr; + uint32_t graphics_key_msk; + uint32_t ckey_cntl; + + int deinterlace_on; + uint32_t deinterlace_pattern; + +} bes_registers_t; + +typedef struct video_registers_s +{ + const char * sname; + uint32_t name; + uint32_t value; +}video_registers_t; + +static bes_registers_t besr; +#ifndef RAGE128 +static int IsR200=0; +#endif +#define DECLARE_VREG(name) { #name, name, 0 } +static video_registers_t vregs[] = +{ + DECLARE_VREG(VIDEOMUX_CNTL), + DECLARE_VREG(VIPPAD_MASK), + DECLARE_VREG(VIPPAD1_A), + DECLARE_VREG(VIPPAD1_EN), + DECLARE_VREG(VIPPAD1_Y), + DECLARE_VREG(OV0_Y_X_START), + DECLARE_VREG(OV0_Y_X_END), + DECLARE_VREG(OV0_PIPELINE_CNTL), + DECLARE_VREG(OV0_EXCLUSIVE_HORZ), + DECLARE_VREG(OV0_EXCLUSIVE_VERT), + DECLARE_VREG(OV0_REG_LOAD_CNTL), + DECLARE_VREG(OV0_SCALE_CNTL), + DECLARE_VREG(OV0_V_INC), + DECLARE_VREG(OV0_P1_V_ACCUM_INIT), + DECLARE_VREG(OV0_P23_V_ACCUM_INIT), + DECLARE_VREG(OV0_P1_BLANK_LINES_AT_TOP), + DECLARE_VREG(OV0_P23_BLANK_LINES_AT_TOP), +#ifdef RADEON + DECLARE_VREG(OV0_BASE_ADDR), +#endif + DECLARE_VREG(OV0_VID_BUF0_BASE_ADRS), + DECLARE_VREG(OV0_VID_BUF1_BASE_ADRS), + DECLARE_VREG(OV0_VID_BUF2_BASE_ADRS), + DECLARE_VREG(OV0_VID_BUF3_BASE_ADRS), + DECLARE_VREG(OV0_VID_BUF4_BASE_ADRS), + DECLARE_VREG(OV0_VID_BUF5_BASE_ADRS), + DECLARE_VREG(OV0_VID_BUF_PITCH0_VALUE), + DECLARE_VREG(OV0_VID_BUF_PITCH1_VALUE), + DECLARE_VREG(OV0_AUTO_FLIP_CNTL), + DECLARE_VREG(OV0_DEINTERLACE_PATTERN), + DECLARE_VREG(OV0_SUBMIT_HISTORY), + DECLARE_VREG(OV0_H_INC), + DECLARE_VREG(OV0_STEP_BY), + DECLARE_VREG(OV0_P1_H_ACCUM_INIT), + DECLARE_VREG(OV0_P23_H_ACCUM_INIT), + DECLARE_VREG(OV0_P1_X_START_END), + DECLARE_VREG(OV0_P2_X_START_END), + DECLARE_VREG(OV0_P3_X_START_END), + DECLARE_VREG(OV0_FILTER_CNTL), + DECLARE_VREG(OV0_FOUR_TAP_COEF_0), + DECLARE_VREG(OV0_FOUR_TAP_COEF_1), + DECLARE_VREG(OV0_FOUR_TAP_COEF_2), + DECLARE_VREG(OV0_FOUR_TAP_COEF_3), + DECLARE_VREG(OV0_FOUR_TAP_COEF_4), + DECLARE_VREG(OV0_FLAG_CNTL), +#ifdef RAGE128 + DECLARE_VREG(OV0_COLOUR_CNTL), +#else + DECLARE_VREG(OV0_SLICE_CNTL), +#endif + DECLARE_VREG(OV0_VID_KEY_CLR), + DECLARE_VREG(OV0_VID_KEY_MSK), + DECLARE_VREG(OV0_GRAPHICS_KEY_CLR), + DECLARE_VREG(OV0_GRAPHICS_KEY_MSK), + DECLARE_VREG(OV0_KEY_CNTL), + DECLARE_VREG(OV0_TEST), + DECLARE_VREG(OV0_LIN_TRANS_A), + DECLARE_VREG(OV0_LIN_TRANS_B), + DECLARE_VREG(OV0_LIN_TRANS_C), + DECLARE_VREG(OV0_LIN_TRANS_D), + DECLARE_VREG(OV0_LIN_TRANS_E), + DECLARE_VREG(OV0_LIN_TRANS_F), + DECLARE_VREG(OV0_GAMMA_0_F), + DECLARE_VREG(OV0_GAMMA_10_1F), + DECLARE_VREG(OV0_GAMMA_20_3F), + DECLARE_VREG(OV0_GAMMA_40_7F), + DECLARE_VREG(OV0_GAMMA_380_3BF), + DECLARE_VREG(OV0_GAMMA_3C0_3FF), + DECLARE_VREG(SUBPIC_CNTL), + DECLARE_VREG(SUBPIC_DEFCOLCON), + DECLARE_VREG(SUBPIC_Y_X_START), + DECLARE_VREG(SUBPIC_Y_X_END), + DECLARE_VREG(SUBPIC_V_INC), + DECLARE_VREG(SUBPIC_H_INC), + DECLARE_VREG(SUBPIC_BUF0_OFFSET), + DECLARE_VREG(SUBPIC_BUF1_OFFSET), + DECLARE_VREG(SUBPIC_LC0_OFFSET), + DECLARE_VREG(SUBPIC_LC1_OFFSET), + DECLARE_VREG(SUBPIC_PITCH), + DECLARE_VREG(SUBPIC_BTN_HLI_COLCON), + DECLARE_VREG(SUBPIC_BTN_HLI_Y_X_START), + DECLARE_VREG(SUBPIC_BTN_HLI_Y_X_END), + DECLARE_VREG(SUBPIC_PALETTE_INDEX), + DECLARE_VREG(SUBPIC_PALETTE_DATA), + DECLARE_VREG(SUBPIC_H_ACCUM_INIT), + DECLARE_VREG(SUBPIC_V_ACCUM_INIT), + DECLARE_VREG(IDCT_RUNS), + DECLARE_VREG(IDCT_LEVELS), + DECLARE_VREG(IDCT_AUTH_CONTROL), + DECLARE_VREG(IDCT_AUTH), + DECLARE_VREG(IDCT_CONTROL) +}; + +static void * radeon_mmio_base = 0; +static void * radeon_mem_base = 0; +static int32_t radeon_overlay_off = 0; +static uint32_t radeon_ram_size = 0; + +#define GETREG(TYPE,PTR,OFFZ) (*((volatile TYPE*)((PTR)+(OFFZ)))) +#define SETREG(TYPE,PTR,OFFZ,VAL) (*((volatile TYPE*)((PTR)+(OFFZ))))=VAL + +#define INREG8(addr) GETREG(uint8_t,(uint32_t)(radeon_mmio_base),addr) +#define OUTREG8(addr,val) SETREG(uint8_t,(uint32_t)(radeon_mmio_base),addr,val) +#define INREG(addr) GETREG(uint32_t,(uint32_t)(radeon_mmio_base),addr) +#define OUTREG(addr,val) SETREG(uint32_t,(uint32_t)(radeon_mmio_base),addr,val) +#define OUTREGP(addr,val,mask) \ + do { \ + unsigned int _tmp = INREG(addr); \ + _tmp &= (mask); \ + _tmp |= (val); \ + OUTREG(addr, _tmp); \ + } while (0) + +static __inline__ uint32_t INPLL(uint32_t addr) +{ + OUTREG8(CLOCK_CNTL_INDEX, addr & 0x0000001f); + return (INREG(CLOCK_CNTL_DATA)); +} + +#define OUTPLL(addr,val) OUTREG8(CLOCK_CNTL_INDEX, (addr & 0x0000001f) | 0x00000080); \ + OUTREG(CLOCK_CNTL_DATA, val) +#define OUTPLLP(addr,val,mask) \ + do { \ + unsigned int _tmp = INPLL(addr); \ + _tmp &= (mask); \ + _tmp |= (val); \ + OUTPLL(addr, _tmp); \ + } while (0) + +static uint32_t radeon_vid_get_dbpp( void ) +{ + uint32_t dbpp,retval; + dbpp = (INREG(CRTC_GEN_CNTL)>>8)& 0xF; + switch(dbpp) + { + case DST_8BPP: retval = 8; break; + case DST_15BPP: retval = 15; break; + case DST_16BPP: retval = 16; break; + case DST_24BPP: retval = 24; break; + default: retval=32; break; + } + return retval; +} + +static int radeon_is_dbl_scan( void ) +{ + return (INREG(CRTC_GEN_CNTL))&CRTC_DBL_SCAN_EN; +} + +static int radeon_is_interlace( void ) +{ + return (INREG(CRTC_GEN_CNTL))&CRTC_INTERLACE_EN; +} + +static uint32_t radeon_get_xres( void ) +{ + /* FIXME: currently we extract that from CRTC!!!*/ + uint32_t xres,h_total; + h_total = INREG(CRTC_H_TOTAL_DISP); + xres = (h_total >> 16) & 0xffff; + return (xres + 1)*8; +} + +static uint32_t radeon_get_yres( void ) +{ + /* FIXME: currently we extract that from CRTC!!!*/ + uint32_t yres,v_total; + v_total = INREG(CRTC_V_TOTAL_DISP); + yres = (v_total >> 16) & 0xffff; + return yres + 1; +} + +static void radeon_wait_vsync(void) +{ + int i; + + OUTREG(GEN_INT_STATUS, VSYNC_INT_AK); + for (i = 0; i < 2000000; i++) + { + if (INREG(GEN_INT_STATUS) & VSYNC_INT) break; + } +} + +#ifdef RAGE128 +static void _radeon_engine_idle(void); +static void _radeon_fifo_wait(unsigned); +#define radeon_engine_idle() _radeon_engine_idle() +#define radeon_fifo_wait(entries) _radeon_fifo_wait(entries) +/* Flush all dirty data in the Pixel Cache to memory. */ +static __inline__ void radeon_engine_flush ( void ) +{ + unsigned i; + + OUTREGP(PC_NGUI_CTLSTAT, PC_FLUSH_ALL, ~PC_FLUSH_ALL); + for (i = 0; i < 2000000; i++) { + if (!(INREG(PC_NGUI_CTLSTAT) & PC_BUSY)) break; + } +} + +/* Reset graphics card to known state. */ +static void radeon_engine_reset( void ) +{ + uint32_t clock_cntl_index; + uint32_t mclk_cntl; + uint32_t gen_reset_cntl; + + radeon_engine_flush(); + + clock_cntl_index = INREG(CLOCK_CNTL_INDEX); + mclk_cntl = INPLL(MCLK_CNTL); + + OUTPLL(MCLK_CNTL, mclk_cntl | FORCE_GCP | FORCE_PIPE3D_CP); + + gen_reset_cntl = INREG(GEN_RESET_CNTL); + + OUTREG(GEN_RESET_CNTL, gen_reset_cntl | SOFT_RESET_GUI); + INREG(GEN_RESET_CNTL); + OUTREG(GEN_RESET_CNTL, + gen_reset_cntl & (uint32_t)(~SOFT_RESET_GUI)); + INREG(GEN_RESET_CNTL); + + OUTPLL(MCLK_CNTL, mclk_cntl); + OUTREG(CLOCK_CNTL_INDEX, clock_cntl_index); + OUTREG(GEN_RESET_CNTL, gen_reset_cntl); +} +#else + +static __inline__ void radeon_engine_flush ( void ) +{ + int i; + + /* initiate flush */ + OUTREGP(RB2D_DSTCACHE_CTLSTAT, RB2D_DC_FLUSH_ALL, + ~RB2D_DC_FLUSH_ALL); + + for (i=0; i < 2000000; i++) { + if (!(INREG(RB2D_DSTCACHE_CTLSTAT) & RB2D_DC_BUSY)) + break; + } +} + +static void _radeon_engine_idle(void); +static void _radeon_fifo_wait(unsigned); +#define radeon_engine_idle() _radeon_engine_idle() +#define radeon_fifo_wait(entries) _radeon_fifo_wait(entries) + +static void radeon_engine_reset( void ) +{ + uint32_t clock_cntl_index, mclk_cntl, rbbm_soft_reset; + + radeon_engine_flush (); + + clock_cntl_index = INREG(CLOCK_CNTL_INDEX); + mclk_cntl = INPLL(MCLK_CNTL); + + OUTPLL(MCLK_CNTL, (mclk_cntl | + FORCEON_MCLKA | + FORCEON_MCLKB | + FORCEON_YCLKA | + FORCEON_YCLKB | + FORCEON_MC | + FORCEON_AIC)); + rbbm_soft_reset = INREG(RBBM_SOFT_RESET); + + OUTREG(RBBM_SOFT_RESET, rbbm_soft_reset | + SOFT_RESET_CP | + SOFT_RESET_HI | + SOFT_RESET_SE | + SOFT_RESET_RE | + SOFT_RESET_PP | + SOFT_RESET_E2 | + SOFT_RESET_RB | + SOFT_RESET_HDP); + INREG(RBBM_SOFT_RESET); + OUTREG(RBBM_SOFT_RESET, rbbm_soft_reset & (uint32_t) + ~(SOFT_RESET_CP | + SOFT_RESET_HI | + SOFT_RESET_SE | + SOFT_RESET_RE | + SOFT_RESET_PP | + SOFT_RESET_E2 | + SOFT_RESET_RB | + SOFT_RESET_HDP)); + INREG(RBBM_SOFT_RESET); + + OUTPLL(MCLK_CNTL, mclk_cntl); + OUTREG(CLOCK_CNTL_INDEX, clock_cntl_index); + OUTREG(RBBM_SOFT_RESET, rbbm_soft_reset); + + return; +} +#endif +static void radeon_engine_restore( void ) +{ +#ifndef RAGE128 + int pitch64; + uint32_t xres,yres,bpp; + radeon_fifo_wait(1); + xres = radeon_get_xres(); + yres = radeon_get_yres(); + bpp = radeon_vid_get_dbpp(); + /* turn of all automatic flushing - we'll do it all */ + OUTREG(RB2D_DSTCACHE_MODE, 0); + + pitch64 = ((xres * (bpp / 8) + 0x3f)) >> 6; + + radeon_fifo_wait(1); + OUTREG(DEFAULT_OFFSET, (INREG(DEFAULT_OFFSET) & 0xC0000000) | + (pitch64 << 22)); + + radeon_fifo_wait(1); +#if defined(__BIG_ENDIAN) + OUTREGP(DP_DATATYPE, + HOST_BIG_ENDIAN_EN, ~HOST_BIG_ENDIAN_EN); +#else + OUTREGP(DP_DATATYPE, 0, ~HOST_BIG_ENDIAN_EN); +#endif + + radeon_fifo_wait(1); + OUTREG(DEFAULT_SC_BOTTOM_RIGHT, (DEFAULT_SC_RIGHT_MAX + | DEFAULT_SC_BOTTOM_MAX)); + radeon_fifo_wait(1); + OUTREG(DP_GUI_MASTER_CNTL, (INREG(DP_GUI_MASTER_CNTL) + | GMC_BRUSH_SOLID_COLOR + | GMC_SRC_DATATYPE_COLOR)); + + radeon_fifo_wait(7); + OUTREG(DST_LINE_START, 0); + OUTREG(DST_LINE_END, 0); + OUTREG(DP_BRUSH_FRGD_CLR, 0xffffffff); + OUTREG(DP_BRUSH_BKGD_CLR, 0x00000000); + OUTREG(DP_SRC_FRGD_CLR, 0xffffffff); + OUTREG(DP_SRC_BKGD_CLR, 0x00000000); + OUTREG(DP_WRITE_MASK, 0xffffffff); + + radeon_engine_idle(); +#endif +} +#ifdef RAGE128 +static void _radeon_fifo_wait (unsigned entries) +{ + unsigned i; + + for(;;) + { + for (i=0; i<2000000; i++) + if ((INREG(GUI_STAT) & GUI_FIFOCNT_MASK) >= entries) + return; + radeon_engine_reset(); + radeon_engine_restore(); + } +} + +static void _radeon_engine_idle ( void ) +{ + unsigned i; + + /* ensure FIFO is empty before waiting for idle */ + radeon_fifo_wait (64); + for(;;) + { + for (i=0; i<2000000; i++) { + if ((INREG(GUI_STAT) & GUI_ACTIVE) == 0) { + radeon_engine_flush (); + return; + } + } + radeon_engine_reset(); + radeon_engine_restore(); + } +} +#else +static void _radeon_fifo_wait (unsigned entries) +{ + unsigned i; + + for(;;) + { + for (i=0; i<2000000; i++) + if ((INREG(RBBM_STATUS) & RBBM_FIFOCNT_MASK) >= entries) + return; + radeon_engine_reset(); + radeon_engine_restore(); + } +} +static void _radeon_engine_idle ( void ) +{ + int i; + + /* ensure FIFO is empty before waiting for idle */ + radeon_fifo_wait (64); + for(;;) + { + for (i=0; i<2000000; i++) { + if (((INREG(RBBM_STATUS) & RBBM_ACTIVE)) == 0) { + radeon_engine_flush (); + return; + } + } + radeon_engine_reset(); + radeon_engine_restore(); + } +} +#endif + +#ifndef RAGE128 +/* Reference color space transform data */ +typedef struct tagREF_TRANSFORM +{ + float RefLuma; + float RefRCb; + float RefRCr; + float RefGCb; + float RefGCr; + float RefBCb; + float RefBCr; +} REF_TRANSFORM; + +/* Parameters for ITU-R BT.601 and ITU-R BT.709 colour spaces */ +REF_TRANSFORM trans[2] = +{ + {1.1678, 0.0, 1.6007, -0.3929, -0.8154, 2.0232, 0.0}, /* BT.601 */ + {1.1678, 0.0, 1.7980, -0.2139, -0.5345, 2.1186, 0.0} /* BT.709 */ +}; +/**************************************************************************** + * SetTransform * + * Function: Calculates and sets color space transform from supplied * + * reference transform, gamma, brightness, contrast, hue and * + * saturation. * + * Inputs: bright - brightness * + * cont - contrast * + * sat - saturation * + * hue - hue * + * red_intensity - intense of red component * + * green_intensity - intense of green component * + * blue_intensity - intense of blue component * + * ref - index to the table of refernce transforms * + * Outputs: NONE * + ****************************************************************************/ + +static void radeon_set_transform(float bright, float cont, float sat, + float hue, float red_intensity, + float green_intensity,float blue_intensity, + unsigned ref) +{ + float OvHueSin, OvHueCos; + float CAdjLuma, CAdjOff; + float RedAdj,GreenAdj,BlueAdj; + float CAdjRCb, CAdjRCr; + float CAdjGCb, CAdjGCr; + float CAdjBCb, CAdjBCr; + float OvLuma, OvROff, OvGOff, OvBOff; + float OvRCb, OvRCr; + float OvGCb, OvGCr; + float OvBCb, OvBCr; + float Loff = 64.0; + float Coff = 512.0f; + + uint32_t dwOvLuma, dwOvROff, dwOvGOff, dwOvBOff; + uint32_t dwOvRCb, dwOvRCr; + uint32_t dwOvGCb, dwOvGCr; + uint32_t dwOvBCb, dwOvBCr; + + if (ref >= 2) return; + + OvHueSin = sin((double)hue); + OvHueCos = cos((double)hue); + + CAdjLuma = cont * trans[ref].RefLuma; + CAdjOff = cont * trans[ref].RefLuma * bright * 1023.0; + RedAdj = cont * trans[ref].RefLuma * red_intensity * 1023.0; + GreenAdj = cont * trans[ref].RefLuma * green_intensity * 1023.0; + BlueAdj = cont * trans[ref].RefLuma * blue_intensity * 1023.0; + + CAdjRCb = sat * -OvHueSin * trans[ref].RefRCr; + CAdjRCr = sat * OvHueCos * trans[ref].RefRCr; + CAdjGCb = sat * (OvHueCos * trans[ref].RefGCb - OvHueSin * trans[ref].RefGCr); + CAdjGCr = sat * (OvHueSin * trans[ref].RefGCb + OvHueCos * trans[ref].RefGCr); + CAdjBCb = sat * OvHueCos * trans[ref].RefBCb; + CAdjBCr = sat * OvHueSin * trans[ref].RefBCb; + +#if 0 /* default constants */ + CAdjLuma = 1.16455078125; + + CAdjRCb = 0.0; + CAdjRCr = 1.59619140625; + CAdjGCb = -0.39111328125; + CAdjGCr = -0.8125; + CAdjBCb = 2.01708984375; + CAdjBCr = 0; +#endif + OvLuma = CAdjLuma; + OvRCb = CAdjRCb; + OvRCr = CAdjRCr; + OvGCb = CAdjGCb; + OvGCr = CAdjGCr; + OvBCb = CAdjBCb; + OvBCr = CAdjBCr; + OvROff = RedAdj + CAdjOff - + OvLuma * Loff - (OvRCb + OvRCr) * Coff; + OvGOff = GreenAdj + CAdjOff - + OvLuma * Loff - (OvGCb + OvGCr) * Coff; + OvBOff = BlueAdj + CAdjOff - + OvLuma * Loff - (OvBCb + OvBCr) * Coff; +#if 0 /* default constants */ + OvROff = -888.5; + OvGOff = 545; + OvBOff = -1104; +#endif + + dwOvROff = ((int)(OvROff * 2.0)) & 0x1fff; + dwOvGOff = (int)(OvGOff * 2.0) & 0x1fff; + dwOvBOff = (int)(OvBOff * 2.0) & 0x1fff; + /* Whatever docs say about R200 having 3.8 format instead of 3.11 + as in Radeon is a lie */ +#if 0 + if(!IsR200) + { +#endif + dwOvLuma =(((int)(OvLuma * 2048.0))&0x7fff)<<17; + dwOvRCb = (((int)(OvRCb * 2048.0))&0x7fff)<<1; + dwOvRCr = (((int)(OvRCr * 2048.0))&0x7fff)<<17; + dwOvGCb = (((int)(OvGCb * 2048.0))&0x7fff)<<1; + dwOvGCr = (((int)(OvGCr * 2048.0))&0x7fff)<<17; + dwOvBCb = (((int)(OvBCb * 2048.0))&0x7fff)<<1; + dwOvBCr = (((int)(OvBCr * 2048.0))&0x7fff)<<17; +#if 0 + } + else + { + dwOvLuma = (((int)(OvLuma * 256.0))&0x7ff)<<20; + dwOvRCb = (((int)(OvRCb * 256.0))&0x7ff)<<4; + dwOvRCr = (((int)(OvRCr * 256.0))&0x7ff)<<20; + dwOvGCb = (((int)(OvGCb * 256.0))&0x7ff)<<4; + dwOvGCr = (((int)(OvGCr * 256.0))&0x7ff)<<20; + dwOvBCb = (((int)(OvBCb * 256.0))&0x7ff)<<4; + dwOvBCr = (((int)(OvBCr * 256.0))&0x7ff)<<20; + } +#endif + OUTREG(OV0_LIN_TRANS_A, dwOvRCb | dwOvLuma); + OUTREG(OV0_LIN_TRANS_B, dwOvROff | dwOvRCr); + OUTREG(OV0_LIN_TRANS_C, dwOvGCb | dwOvLuma); + OUTREG(OV0_LIN_TRANS_D, dwOvGOff | dwOvGCr); + OUTREG(OV0_LIN_TRANS_E, dwOvBCb | dwOvLuma); + OUTREG(OV0_LIN_TRANS_F, dwOvBOff | dwOvBCr); +} + +/* Gamma curve definition */ +typedef struct +{ + unsigned int gammaReg; + unsigned int gammaSlope; + unsigned int gammaOffset; +}GAMMA_SETTINGS; + +/* Recommended gamma curve parameters */ +GAMMA_SETTINGS r200_def_gamma[18] = +{ + {OV0_GAMMA_0_F, 0x100, 0x0000}, + {OV0_GAMMA_10_1F, 0x100, 0x0020}, + {OV0_GAMMA_20_3F, 0x100, 0x0040}, + {OV0_GAMMA_40_7F, 0x100, 0x0080}, + {OV0_GAMMA_80_BF, 0x100, 0x0100}, + {OV0_GAMMA_C0_FF, 0x100, 0x0100}, + {OV0_GAMMA_100_13F, 0x100, 0x0200}, + {OV0_GAMMA_140_17F, 0x100, 0x0200}, + {OV0_GAMMA_180_1BF, 0x100, 0x0300}, + {OV0_GAMMA_1C0_1FF, 0x100, 0x0300}, + {OV0_GAMMA_200_23F, 0x100, 0x0400}, + {OV0_GAMMA_240_27F, 0x100, 0x0400}, + {OV0_GAMMA_280_2BF, 0x100, 0x0500}, + {OV0_GAMMA_2C0_2FF, 0x100, 0x0500}, + {OV0_GAMMA_300_33F, 0x100, 0x0600}, + {OV0_GAMMA_340_37F, 0x100, 0x0600}, + {OV0_GAMMA_380_3BF, 0x100, 0x0700}, + {OV0_GAMMA_3C0_3FF, 0x100, 0x0700} +}; + +GAMMA_SETTINGS r100_def_gamma[6] = +{ + {OV0_GAMMA_0_F, 0x100, 0x0000}, + {OV0_GAMMA_10_1F, 0x100, 0x0020}, + {OV0_GAMMA_20_3F, 0x100, 0x0040}, + {OV0_GAMMA_40_7F, 0x100, 0x0080}, + {OV0_GAMMA_380_3BF, 0x100, 0x0100}, + {OV0_GAMMA_3C0_3FF, 0x100, 0x0100} +}; + +static void make_default_gamma_correction( void ) +{ + size_t i; + if(!IsR200){ + OUTREG(OV0_LIN_TRANS_A, 0x12A00000); + OUTREG(OV0_LIN_TRANS_B, 0x199018FE); + OUTREG(OV0_LIN_TRANS_C, 0x12A0F9B0); + OUTREG(OV0_LIN_TRANS_D, 0xF2F0043B); + OUTREG(OV0_LIN_TRANS_E, 0x12A02050); + OUTREG(OV0_LIN_TRANS_F, 0x0000174E); + for(i=0; i<6; i++){ + OUTREG(r100_def_gamma[i].gammaReg, + (r100_def_gamma[i].gammaSlope<<16) | + r100_def_gamma[i].gammaOffset); + } + } + else{ + OUTREG(OV0_LIN_TRANS_A, 0x12a00000); + OUTREG(OV0_LIN_TRANS_B, 0x1990190e); + OUTREG(OV0_LIN_TRANS_C, 0x12a0f9c0); + OUTREG(OV0_LIN_TRANS_D, 0xf3000442); + OUTREG(OV0_LIN_TRANS_E, 0x12a02040); + OUTREG(OV0_LIN_TRANS_F, 0x175f); + + /* Default Gamma, + Of 18 segments for gamma cure, all segments in R200 are programmable, + while only lower 4 and upper 2 segments are programmable in Radeon*/ + for(i=0; i<18; i++){ + OUTREG(r200_def_gamma[i].gammaReg, + (r200_def_gamma[i].gammaSlope<<16) | + r200_def_gamma[i].gammaOffset); + } + } +} +#endif + +static void radeon_vid_make_default(void) +{ +#ifdef RAGE128 + OUTREG(OV0_COLOUR_CNTL,0x00101000UL); /* Default brihgtness and saturation for Rage128 */ +#else + make_default_gamma_correction(); +#endif + besr.deinterlace_pattern = 0x900AAAAA; + OUTREG(OV0_DEINTERLACE_PATTERN,besr.deinterlace_pattern); + besr.deinterlace_on=1; + besr.double_buff=1; + besr.ckey_on=0; + besr.graphics_key_msk=0; + besr.graphics_key_clr=0; + besr.ckey_cntl = VIDEO_KEY_FN_TRUE|GRAPHIC_KEY_FN_TRUE|CMP_MIX_AND; +} + + +unsigned vixGetVersion( void ) { return VIDIX_VERSION; } + +static unsigned short ati_card_ids[] = +{ +#ifdef RAGE128 + /* + This driver should be compatible with Rage128 (pro) chips. + (include adaptive deinterlacing!!!). + Moreover: the same logic can be used with Mach64 chips. + (I mean: mach64xx, 3d rage, 3d rage IIc, 3D rage pro, 3d rage mobility). + but they are incompatible by i/o ports. So if enthusiasts will want + then they can redefine OUTREG and INREG macros and redefine OV0_* + constants. Also it seems that mach64 chips supports only: YUY2, YV12, UYVY + fourccs (422 and 420 formats only). + */ +/* Rage128 Pro GL */ + DEVICE_ATI_RAGE_128_PA_PRO, + DEVICE_ATI_RAGE_128_PB_PRO, + DEVICE_ATI_RAGE_128_PC_PRO, + DEVICE_ATI_RAGE_128_PD_PRO, + DEVICE_ATI_RAGE_128_PE_PRO, + DEVICE_ATI_RAGE_128_PF_PRO, +/* Rage128 Pro VR */ + DEVICE_ATI_RAGE_128_PG_PRO, + DEVICE_ATI_RAGE_128_PH_PRO, + DEVICE_ATI_RAGE_128_PI_PRO, + DEVICE_ATI_RAGE_128_PJ_PRO, + DEVICE_ATI_RAGE_128_PK_PRO, + DEVICE_ATI_RAGE_128_PL_PRO, + DEVICE_ATI_RAGE_128_PM_PRO, + DEVICE_ATI_RAGE_128_PN_PRO, + DEVICE_ATI_RAGE_128_PO_PRO, + DEVICE_ATI_RAGE_128_PP_PRO, + DEVICE_ATI_RAGE_128_PQ_PRO, + DEVICE_ATI_RAGE_128_PR_PRO, + DEVICE_ATI_RAGE_128_PS_PRO, + DEVICE_ATI_RAGE_128_PT_PRO, + DEVICE_ATI_RAGE_128_PU_PRO, + DEVICE_ATI_RAGE_128_PV_PRO, + DEVICE_ATI_RAGE_128_PW_PRO, + DEVICE_ATI_RAGE_128_PX_PRO, +/* Rage128 GL */ + DEVICE_ATI_RAGE_128_RE_SG, + DEVICE_ATI_RAGE_128_RF_SG, + DEVICE_ATI_RAGE_128_RG, + DEVICE_ATI_RAGE_128_RK_VR, + DEVICE_ATI_RAGE_128_RL_VR, + DEVICE_ATI_RAGE_128_SE_4X, + DEVICE_ATI_RAGE_128_SF_4X, + DEVICE_ATI_RAGE_128_SG_4X, + DEVICE_ATI_RAGE_128_4X, + DEVICE_ATI_RAGE_128_SK_4X, + DEVICE_ATI_RAGE_128_SL_4X, + DEVICE_ATI_RAGE_128_SM_4X, + DEVICE_ATI_RAGE_128_4X2, + DEVICE_ATI_RAGE_128_PRO, + DEVICE_ATI_RAGE_128_PRO2, + DEVICE_ATI_RAGE_128_PRO3, +/* these seem to be based on rage 128 instead of mach64 */ + DEVICE_ATI_RAGE_MOBILITY_M3, + DEVICE_ATI_RAGE_MOBILITY_M32 +#else +/* Radeons (indeed: Rage 256 Pro ;) */ + DEVICE_ATI_RADEON_8500_DV, + DEVICE_ATI_RADEON_MOBILITY_M6, + DEVICE_ATI_RADEON_MOBILITY_M62, + DEVICE_ATI_RADEON_MOBILITY_M63, + DEVICE_ATI_RADEON_QD, + DEVICE_ATI_RADEON_QE, + DEVICE_ATI_RADEON_QF, + DEVICE_ATI_RADEON_QG, + DEVICE_ATI_RADEON_QL, + DEVICE_ATI_RADEON_QW, + DEVICE_ATI_RADEON_VE_QY, + DEVICE_ATI_RADEON_VE_QZ +#endif +}; + +static int find_chip(unsigned chip_id) +{ + unsigned i; + for(i = 0;i < sizeof(ati_card_ids)/sizeof(unsigned short);i++) + { + if(chip_id == ati_card_ids[i]) return i; + } + return -1; +} + +pciinfo_t pci_info; +static int probed=0; + +vidix_capability_t def_cap = +{ +#ifdef RAGE128 + "BES driver for rage128 cards", +#else + "BES driver for radeon cards", +#endif + "Nick Kurshev", + TYPE_OUTPUT | TYPE_FX, + { 0, 0, 0, 0 }, + 2048, + 2048, + 4, + 4, + -1, + FLAG_UPSCALER | FLAG_DOWNSCALER | FLAG_EQUALIZER, + VENDOR_ATI, + 0, + { 0, 0, 0, 0} +}; + + +int vixProbe( int verbose,int force ) +{ + pciinfo_t lst[MAX_PCI_DEVICES]; + unsigned i,num_pci; + int err; + __verbose = verbose; + err = pci_scan(lst,&num_pci); + if(err) + { + printf(RADEON_MSG" Error occured during pci scan: %s\n",strerror(err)); + return err; + } + else + { + err = ENXIO; + for(i=0;i PROBE_NORMAL) + { + printf(RADEON_MSG" Driver was forced. Was found %sknown chip\n",idx == -1 ? "un" : ""); + if(idx == -1) +#ifdef RAGE128 + printf(RADEON_MSG" Assuming it as Rage128\n"); +#else + printf(RADEON_MSG" Assuming it as Radeon1\n"); +#endif + } + def_cap.device_id = lst[i].device; + err = 0; + memcpy(&pci_info,&lst[i],sizeof(pciinfo_t)); + probed=1; + break; + } + } + } + if(err && verbose) printf(RADEON_MSG" Can't find chip\n"); + return err; +} + +int vixInit( void ) +{ + int err; + if(!probed) + { + printf(RADEON_MSG" Driver was not probed but is being initializing\n"); + return EINTR; + } + if((radeon_mmio_base = map_phys_mem(pci_info.base2,0xFFFF))==(void *)-1) return ENOMEM; + radeon_ram_size = INREG(CONFIG_MEMSIZE); + /* mem size is bits [28:0], mask off the rest. Range: from 1Mb up to 512 Mb */ + radeon_ram_size &= CONFIG_MEMSIZE_MASK; + if((radeon_mem_base = map_phys_mem(pci_info.base0,radeon_ram_size))==(void *)-1) return ENOMEM; + memset(&besr,0,sizeof(bes_registers_t)); + radeon_vid_make_default(); + printf(RADEON_MSG" Video memory = %uMb\n",radeon_ram_size/0x100000); + err = mtrr_set_type(pci_info.base0,radeon_ram_size,MTRR_TYPE_WRCOMB); + if(!err) printf(RADEON_MSG" Set write-combining type of video memory\n"); + if(bm_open() == 0) def_cap.flags |= FLAG_DMA | FLAG_EQ_DMA; + else + if(__verbose) printf(RADEON_MSG" Can't initialize busmastering: %s\n",strerror(errno)); + return 0; +} + +void vixDestroy( void ) +{ + unmap_phys_mem(radeon_mem_base,radeon_ram_size); + unmap_phys_mem(radeon_mmio_base,0xFFFF); + bm_close(); +} + +int vixGetCapability(vidix_capability_t *to) +{ + memcpy(to,&def_cap,sizeof(vidix_capability_t)); + return 0; +} + +uint32_t supported_fourcc[] = +{ + IMGFMT_YV12, IMGFMT_I420, IMGFMT_IYUV, + IMGFMT_UYVY, IMGFMT_YUY2, IMGFMT_YVYU, + IMGFMT_RGB15, IMGFMT_BGR15, + IMGFMT_RGB16, IMGFMT_BGR16, + IMGFMT_RGB32, IMGFMT_BGR32 +}; + +__inline__ static int is_supported_fourcc(uint32_t fourcc) +{ + unsigned i; + for(i=0;ifourcc)) + { + to->depth = VID_DEPTH_1BPP | VID_DEPTH_2BPP | + VID_DEPTH_4BPP | VID_DEPTH_8BPP | + VID_DEPTH_12BPP| VID_DEPTH_15BPP| + VID_DEPTH_16BPP| VID_DEPTH_24BPP| + VID_DEPTH_32BPP; + to->flags = VID_CAP_EXPAND | VID_CAP_SHRINK | VID_CAP_COLORKEY; + return 0; + } + else to->depth = to->flags = 0; + return ENOSYS; +} + +static void radeon_vid_dump_regs( void ) +{ + size_t i; + printf(RADEON_MSG"*** Begin of DRIVER variables dump ***\n"); + printf(RADEON_MSG"radeon_mmio_base=%p\n",radeon_mmio_base); + printf(RADEON_MSG"radeon_mem_base=%p\n",radeon_mem_base); + printf(RADEON_MSG"radeon_overlay_off=%08X\n",radeon_overlay_off); + printf(RADEON_MSG"radeon_ram_size=%08X\n",radeon_ram_size); + printf(RADEON_MSG"video mode: %ux%u@%u\n",radeon_get_xres(),radeon_get_yres(),radeon_vid_get_dbpp()); + printf(RADEON_MSG"*** Begin of OV0 registers dump ***\n"); + for(i=0;i 1) printf(RADEON_MSG"we wanted: scaler=%08X\n",bes_flags); + if(__verbose > 1) radeon_vid_dump_regs(); +} + +static unsigned radeon_query_pitch(unsigned fourcc,const vidix_yuv_t *spitch) +{ + unsigned pitch,spy,spv,spu; + spy = spv = spu = 0; + switch(spitch->y) + { + case 16: + case 32: + case 64: + case 128: + case 256: spy = spitch->y; break; + default: break; + } + switch(spitch->u) + { + case 16: + case 32: + case 64: + case 128: + case 256: spu = spitch->u; break; + default: break; + } + switch(spitch->v) + { + case 16: + case 32: + case 64: + case 128: + case 256: spv = spitch->v; break; + default: break; + } + switch(fourcc) + { + /* 4:2:0 */ + case IMGFMT_IYUV: + case IMGFMT_YV12: + case IMGFMT_I420: + if(spy > 16 && spu == spy/2 && spv == spy/2) pitch = spy; + else pitch = 32; + break; + case IMGFMT_YVU9: + if(spy > 32 && spu == spy/4 && spv == spy/4) pitch = spy; + else pitch = 64; + break; + default: + if(spy >= 16) pitch = spy; + else pitch = 16; + break; + } + return pitch; +} + +static int radeon_vid_init_video( vidix_playback_t *config ) +{ + uint32_t i,tmp,src_w,src_h,dest_w,dest_h,pitch,h_inc,step_by,left,leftUV,top; + int is_420,is_rgb32,is_rgb,best_pitch,mpitch; + radeon_vid_stop_video(); + left = config->src.x << 16; + top = config->src.y << 16; + src_h = config->src.h; + src_w = config->src.w; + is_420 = is_rgb32 = is_rgb = 0; + if(config->fourcc == IMGFMT_YV12 || + config->fourcc == IMGFMT_I420 || + config->fourcc == IMGFMT_IYUV) is_420 = 1; + if(config->fourcc == IMGFMT_RGB32 || + config->fourcc == IMGFMT_BGR32) is_rgb32 = 1; + if(config->fourcc == IMGFMT_RGB32 || + config->fourcc == IMGFMT_BGR32 || + config->fourcc == IMGFMT_RGB24 || + config->fourcc == IMGFMT_BGR24 || + config->fourcc == IMGFMT_RGB16 || + config->fourcc == IMGFMT_BGR16 || + config->fourcc == IMGFMT_RGB15 || + config->fourcc == IMGFMT_BGR15) is_rgb = 1; + best_pitch = radeon_query_pitch(config->fourcc,&config->src.pitch); + mpitch = best_pitch-1; + switch(config->fourcc) + { + case IMGFMT_YVU9: + /* 4:2:0 */ + case IMGFMT_IYUV: + case IMGFMT_YV12: + case IMGFMT_I420: pitch = (src_w + mpitch) & ~mpitch; + config->dest.pitch.y = + config->dest.pitch.u = + config->dest.pitch.v = best_pitch; + break; + /* RGB 4:4:4:4 */ + case IMGFMT_RGB32: + case IMGFMT_BGR32: pitch = (src_w*4 + mpitch) & ~mpitch; + config->dest.pitch.y = + config->dest.pitch.u = + config->dest.pitch.v = best_pitch; + break; + /* 4:2:2 */ + default: /* RGB15, RGB16, YVYU, UYVY, YUY2 */ + pitch = ((src_w*2) + mpitch) & ~mpitch; + config->dest.pitch.y = + config->dest.pitch.u = + config->dest.pitch.v = best_pitch; + break; + } + dest_w = config->dest.w; + dest_h = config->dest.h; + if(radeon_is_dbl_scan()) dest_h *= 2; + besr.dest_bpp = radeon_vid_get_dbpp(); + besr.fourcc = config->fourcc; + besr.v_inc = (src_h << 20) / dest_h; + if(radeon_is_interlace()) besr.v_inc *= 2; + h_inc = (src_w << 12) / dest_w; + step_by = 1; + while(h_inc >= (2 << 12)) { + step_by++; + h_inc >>= 1; + } + + /* keep everything in 16.16 */ + besr.base_addr = INREG(DISPLAY_BASE_ADDR); + config->offsets[0] = 0; + for(i=1;ioffsets[i] = config->offsets[i-1]+config->frame_size; + if(is_420) + { + uint32_t d1line,d2line,d3line; + d1line = top*pitch; + d2line = src_h*pitch+(d1line>>2); + d3line = d2line+((src_h*pitch)>>2); + d1line += (left >> 16) & ~15; + d2line += (left >> 17) & ~15; + d3line += (left >> 17) & ~15; + config->offset.y = d1line & VIF_BUF0_BASE_ADRS_MASK; + config->offset.v = d2line & VIF_BUF1_BASE_ADRS_MASK; + config->offset.u = d3line & VIF_BUF2_BASE_ADRS_MASK; + for(i=0;ioffsets[i]+config->offset.y)&VIF_BUF0_BASE_ADRS_MASK); + besr.vid_buf_base_adrs_v[i]=((radeon_overlay_off+config->offsets[i]+config->offset.v)&VIF_BUF1_BASE_ADRS_MASK)|VIF_BUF1_PITCH_SEL; + besr.vid_buf_base_adrs_u[i]=((radeon_overlay_off+config->offsets[i]+config->offset.u)&VIF_BUF2_BASE_ADRS_MASK)|VIF_BUF2_PITCH_SEL; + } + config->offset.y = ((besr.vid_buf_base_adrs_y[0])&VIF_BUF0_BASE_ADRS_MASK) - radeon_overlay_off; + config->offset.v = ((besr.vid_buf_base_adrs_v[0])&VIF_BUF1_BASE_ADRS_MASK) - radeon_overlay_off; + config->offset.u = ((besr.vid_buf_base_adrs_u[0])&VIF_BUF2_BASE_ADRS_MASK) - radeon_overlay_off; + if(besr.fourcc == IMGFMT_I420 || besr.fourcc == IMGFMT_IYUV) + { + uint32_t tmp; + tmp = config->offset.u; + config->offset.u = config->offset.v; + config->offset.v = tmp; + } + } + else + { + config->offset.y = config->offset.u = config->offset.v = ((left & ~7) << 1)&VIF_BUF0_BASE_ADRS_MASK; + for(i=0;ioffsets[i] + config->offset.y; + } + } + + tmp = (left & 0x0003ffff) + 0x00028000 + (h_inc << 3); + besr.p1_h_accum_init = ((tmp << 4) & 0x000f8000) | + ((tmp << 12) & 0xf0000000); + + tmp = ((left >> 1) & 0x0001ffff) + 0x00028000 + (h_inc << 2); + besr.p23_h_accum_init = ((tmp << 4) & 0x000f8000) | + ((tmp << 12) & 0x70000000); + tmp = (top & 0x0000ffff) + 0x00018000; + besr.p1_v_accum_init = ((tmp << 4) & OV0_P1_V_ACCUM_INIT_MASK) + |(OV0_P1_MAX_LN_IN_PER_LN_OUT & 1); + + tmp = ((top >> 1) & 0x0000ffff) + 0x00018000; + besr.p23_v_accum_init = is_420 ? ((tmp << 4) & OV0_P23_V_ACCUM_INIT_MASK) + |(OV0_P23_MAX_LN_IN_PER_LN_OUT & 1) : 0; + + leftUV = (left >> 17) & 15; + left = (left >> 16) & 15; + if(is_rgb && !is_rgb32) h_inc<<=1; + if(is_rgb32) + besr.h_inc = (h_inc >> 1) | ((h_inc >> 1) << 16); + else + besr.h_inc = h_inc | ((h_inc >> 1) << 16); + besr.step_by = step_by | (step_by << 8); + besr.y_x_start = (config->dest.x+X_ADJUST) | (config->dest.y << 16); + besr.y_x_end = (config->dest.x + dest_w+X_ADJUST) | ((config->dest.y + dest_h) << 16); + besr.p1_blank_lines_at_top = P1_BLNK_LN_AT_TOP_M1_MASK|((src_h-1)<<16); + if(is_420) + { + src_h = (src_h + 1) >> 1; + besr.p23_blank_lines_at_top = P23_BLNK_LN_AT_TOP_M1_MASK|((src_h-1)<<16); + } + else besr.p23_blank_lines_at_top = 0; + besr.vid_buf_pitch0_value = pitch; + besr.vid_buf_pitch1_value = is_420 ? pitch>>1 : pitch; + besr.p1_x_start_end = (src_w+left-1)|(left<<16); + src_w>>=1; + besr.p2_x_start_end = (src_w+left-1)|(leftUV<<16); + besr.p3_x_start_end = besr.p2_x_start_end; + + + return 0; +} + +static void radeon_compute_framesize(vidix_playback_t *info) +{ + unsigned pitch,awidth,dbpp; + pitch = radeon_query_pitch(info->fourcc,&info->src.pitch); + dbpp = radeon_vid_get_dbpp(); + switch(info->fourcc) + { + case IMGFMT_I420: + case IMGFMT_YV12: + case IMGFMT_IYUV: + awidth = (info->src.w + (pitch-1)) & ~(pitch-1); + info->frame_size = awidth*(info->src.h+info->src.h/2); + break; + case IMGFMT_RGB32: + case IMGFMT_BGR32: + awidth = (info->src.w*4 + (pitch-1)) & ~(pitch-1); + info->frame_size = awidth*info->src.h; + break; + /* YUY2 YVYU, RGB15, RGB16 */ + default: + awidth = (info->src.w*2 + (pitch-1)) & ~(pitch-1); + info->frame_size = awidth*info->src.h; + break; + } +} + +int vixConfigPlayback(vidix_playback_t *info) +{ + unsigned rgb_size,nfr; + if(!is_supported_fourcc(info->fourcc)) return ENOSYS; + if(info->num_frames>VID_PLAY_MAXFRAMES) info->num_frames=VID_PLAY_MAXFRAMES; + if(info->num_frames==1) besr.double_buff=0; + else besr.double_buff=1; + radeon_compute_framesize(info); + + rgb_size = radeon_get_xres()*radeon_get_yres()*((radeon_vid_get_dbpp()+7)/8); + nfr = info->num_frames; + for(;nfr>0; nfr--) + { + radeon_overlay_off = radeon_ram_size - info->frame_size*nfr; + radeon_overlay_off &= 0xffff0000; + if(radeon_overlay_off >= (int)rgb_size ) break; + } + if(nfr <= 3) + { + nfr = info->num_frames; + for(;nfr>0; nfr--) + { + radeon_overlay_off = radeon_ram_size - info->frame_size*nfr; + radeon_overlay_off &= 0xffff0000; + if(radeon_overlay_off > 0) break; + } + } + if(nfr <= 0) return EINVAL; + info->num_frames = nfr; + besr.vid_nbufs = info->num_frames; + info->dga_addr = (char *)radeon_mem_base + radeon_overlay_off; + radeon_vid_init_video(info); + return 0; +} + +int vixPlaybackOn( void ) +{ + radeon_vid_display_video(); + return 0; +} + +int vixPlaybackOff( void ) +{ + radeon_vid_stop_video(); + return 0; +} + +int vixPlaybackFrameSelect(unsigned frame) +{ + uint32_t off[6]; + int prev_frame= (frame-1+besr.vid_nbufs) % besr.vid_nbufs; + /* + buf3-5 always should point onto second buffer for better + deinterlacing and TV-in + */ + if(!besr.double_buff) return 0; + if(frame > besr.vid_nbufs) frame = besr.vid_nbufs-1; + if(prev_frame > (int)besr.vid_nbufs) prev_frame = besr.vid_nbufs-1; + off[0] = besr.vid_buf_base_adrs_y[frame]; + off[1] = besr.vid_buf_base_adrs_v[frame]; + off[2] = besr.vid_buf_base_adrs_u[frame]; + off[3] = besr.vid_buf_base_adrs_y[prev_frame]; + off[4] = besr.vid_buf_base_adrs_v[prev_frame]; + off[5] = besr.vid_buf_base_adrs_u[prev_frame]; + radeon_fifo_wait(8); + OUTREG(OV0_REG_LOAD_CNTL, REG_LD_CTL_LOCK); + radeon_engine_idle(); + while(!(INREG(OV0_REG_LOAD_CNTL)®_LD_CTL_LOCK_READBACK)); + OUTREG(OV0_VID_BUF0_BASE_ADRS, off[0]); + OUTREG(OV0_VID_BUF1_BASE_ADRS, off[1]); + OUTREG(OV0_VID_BUF2_BASE_ADRS, off[2]); + OUTREG(OV0_VID_BUF3_BASE_ADRS, off[3]); + OUTREG(OV0_VID_BUF4_BASE_ADRS, off[4]); + OUTREG(OV0_VID_BUF5_BASE_ADRS, off[5]); + OUTREG(OV0_REG_LOAD_CNTL, 0); + if(besr.vid_nbufs == 2) radeon_wait_vsync(); + if(__verbose > 1) radeon_vid_dump_regs(); + return 0; +} + +vidix_video_eq_t equal = +{ + VEQ_CAP_BRIGHTNESS | VEQ_CAP_SATURATION +#ifndef RAGE128 + | VEQ_CAP_CONTRAST | VEQ_CAP_HUE | VEQ_CAP_RGB_INTENSITY +#endif + , + 0, 0, 0, 0, 0, 0, 0, 0 }; + +int vixPlaybackGetEq( vidix_video_eq_t * eq) +{ + memcpy(eq,&equal,sizeof(vidix_video_eq_t)); + return 0; +} + +#ifndef RAGE128 +#define RTFSaturation(a) (1.0 + ((a)*1.0)/1000.0) +#define RTFBrightness(a) (((a)*1.0)/2000.0) +#define RTFIntensity(a) (((a)*1.0)/2000.0) +#define RTFContrast(a) (1.0 + ((a)*1.0)/1000.0) +#define RTFHue(a) (((a)*3.1416)/1000.0) +#define RTFCheckParam(a) {if((a)<-1000) (a)=-1000; if((a)>1000) (a)=1000;} +#endif + +int vixPlaybackSetEq( const vidix_video_eq_t * eq) +{ +#ifdef RAGE128 + int br,sat; +#else + int itu_space; +#endif + if(eq->cap & VEQ_CAP_BRIGHTNESS) equal.brightness = eq->brightness; + if(eq->cap & VEQ_CAP_CONTRAST) equal.contrast = eq->contrast; + if(eq->cap & VEQ_CAP_SATURATION) equal.saturation = eq->saturation; + if(eq->cap & VEQ_CAP_HUE) equal.hue = eq->hue; + if(eq->cap & VEQ_CAP_RGB_INTENSITY) + { + equal.red_intensity = eq->red_intensity; + equal.green_intensity = eq->green_intensity; + equal.blue_intensity = eq->blue_intensity; + } + equal.flags = eq->flags; +#ifdef RAGE128 + br = equal.brightness * 64 / 1000; + if(br < -64) br = -64; if(br > 63) br = 63; + sat = (equal.saturation + 1000) * 16 / 1000; + if(sat < 0) sat = 0; if(sat > 31) sat = 31; + OUTREG(OV0_COLOUR_CNTL, (br & 0x7f) | (sat << 8) | (sat << 16)); +#else + itu_space = equal.flags == VEQ_FLG_ITU_R_BT_709 ? 1 : 0; + RTFCheckParam(equal.brightness); + RTFCheckParam(equal.saturation); + RTFCheckParam(equal.contrast); + RTFCheckParam(equal.hue); + RTFCheckParam(equal.red_intensity); + RTFCheckParam(equal.green_intensity); + RTFCheckParam(equal.blue_intensity); + radeon_set_transform(RTFBrightness(equal.brightness), + RTFContrast(equal.contrast), + RTFSaturation(equal.saturation), + RTFHue(equal.hue), + RTFIntensity(equal.red_intensity), + RTFIntensity(equal.green_intensity), + RTFIntensity(equal.blue_intensity), + itu_space); +#endif + return 0; +} + +int vixPlaybackSetDeint( const vidix_deinterlace_t * info) +{ + unsigned sflg; + switch(info->flags) + { + default: + case CFG_NON_INTERLACED: + besr.deinterlace_on = 0; + break; + case CFG_EVEN_ODD_INTERLACING: + case CFG_INTERLACED: + besr.deinterlace_on = 1; + besr.deinterlace_pattern = 0x900AAAAA; + break; + case CFG_ODD_EVEN_INTERLACING: + besr.deinterlace_on = 1; + besr.deinterlace_pattern = 0x00055555; + break; + case CFG_UNIQUE_INTERLACING: + besr.deinterlace_on = 1; + besr.deinterlace_pattern = info->deinterlace_pattern; + break; + } + OUTREG(OV0_REG_LOAD_CNTL, REG_LD_CTL_LOCK); + radeon_engine_idle(); + while(!(INREG(OV0_REG_LOAD_CNTL)®_LD_CTL_LOCK_READBACK)); + radeon_fifo_wait(15); + sflg = INREG(OV0_SCALE_CNTL); + if(besr.deinterlace_on) + { + OUTREG(OV0_SCALE_CNTL,sflg | SCALER_ADAPTIVE_DEINT); + OUTREG(OV0_DEINTERLACE_PATTERN,besr.deinterlace_pattern); + } + else OUTREG(OV0_SCALE_CNTL,sflg & (~SCALER_ADAPTIVE_DEINT)); + OUTREG(OV0_REG_LOAD_CNTL, 0); + return 0; +} + +int vixPlaybackGetDeint( vidix_deinterlace_t * info) +{ + if(!besr.deinterlace_on) info->flags = CFG_NON_INTERLACED; + else + { + info->flags = CFG_UNIQUE_INTERLACING; + info->deinterlace_pattern = besr.deinterlace_pattern; + } + return 0; +} + + +/* Graphic keys */ +static vidix_grkey_t radeon_grkey; + +static void set_gr_key( void ) +{ + if(radeon_grkey.ckey.op == CKEY_TRUE) + { + int dbpp=radeon_vid_get_dbpp(); + besr.ckey_on=1; + + switch(dbpp) + { + case 15: + besr.graphics_key_clr= + ((radeon_grkey.ckey.blue &0xF8)>>3) + | ((radeon_grkey.ckey.green&0xF8)<<2) + | ((radeon_grkey.ckey.red &0xF8)<<7); + break; + case 16: + besr.graphics_key_clr= + ((radeon_grkey.ckey.blue &0xF8)>>3) + | ((radeon_grkey.ckey.green&0xFC)<<3) + | ((radeon_grkey.ckey.red &0xF8)<<8); + break; + case 24: + besr.graphics_key_clr= + ((radeon_grkey.ckey.blue &0xFF)) + | ((radeon_grkey.ckey.green&0xFF)<<8) + | ((radeon_grkey.ckey.red &0xFF)<<16); + break; + case 32: + besr.graphics_key_clr= + ((radeon_grkey.ckey.blue &0xFF)) + | ((radeon_grkey.ckey.green&0xFF)<<8) + | ((radeon_grkey.ckey.red &0xFF)<<16); + break; + default: + besr.ckey_on=0; + besr.graphics_key_msk=0; + besr.graphics_key_clr=0; + } +#ifdef RAGE128 + besr.graphics_key_msk=(1< driver: movies's fourcc */ + unsigned capability; /* app -> driver: what capability to use */ + unsigned blend_factor; /* app -> driver: blending factor */ + vidix_rect_t src; /* app -> driver: original movie size */ + vidix_rect_t dest; /* app -> driver: destinition movie size. driver->app dest_pitch */ +#define VID_PLAY_INTERLEAVED_UV 0x00000001 /* driver -> app: interleaved UV planes */ +#define INTERLEAVING_UV 0x00001000 /* UVUVUVUVUV used by Matrox G200 */ +#define INTERLEAVING_VU 0x00001001 /* VUVUVUVUVU */ + int flags; + /* memory model */ + unsigned frame_size; /* driver -> app: destinition frame size */ + unsigned num_frames; /* app -> driver: after call: driver -> app */ +#define VID_PLAY_MAXFRAMES 64 /* reasonable limitation for decoding ahead */ + unsigned offsets[VID_PLAY_MAXFRAMES]; /* driver -> app */ + vidix_yuv_t offset; /* driver -> app: relative offsets within frame for yuv planes */ + void* dga_addr; /* driver -> app: linear address */ +}vidix_playback_t; + + /* Returns 0 if ok else errno */ +extern int vixConfigPlayback(vidix_playback_t *); + + /* Returns 0 if ok else errno */ +extern int vixPlaybackOn( void ); + + /* Returns 0 if ok else errno */ +extern int vixPlaybackOff( void ); + + /* Returns 0 if ok else errno */ +extern int vixPlaybackFrameSelect( unsigned frame_idx ); + +typedef struct vidix_grkey_s +{ + vidix_ckey_t ckey; /* app -> driver: color key */ + vidix_vkey_t vkey; /* app -> driver: video key */ +#define KEYS_PUT 0 +#define KEYS_AND 1 +#define KEYS_OR 2 +#define KEYS_XOR 3 + unsigned key_op; /* app -> driver: keys operations */ +}vidix_grkey_t; + + /* Returns 0 if ok else errno */ +extern int vixGetGrKeys( vidix_grkey_t * ); + + /* Returns 0 if ok else errno */ +extern int vixSetGrKeys( const vidix_grkey_t * ); + + +typedef struct vidix_video_eq_s +{ +#define VEQ_CAP_NONE 0x00000000UL +#define VEQ_CAP_BRIGHTNESS 0x00000001UL +#define VEQ_CAP_CONTRAST 0x00000002UL +#define VEQ_CAP_SATURATION 0x00000004UL +#define VEQ_CAP_HUE 0x00000008UL +#define VEQ_CAP_RGB_INTENSITY 0x00000010UL + int cap; /* on get_eq should contain capability of equalizer + on set_eq should contain using fields */ +/* end-user app can have presets like: cold-normal-hot picture and so on */ + int brightness; /* -1000 : +1000 */ + int contrast; /* -1000 : +1000 */ + int saturation; /* -1000 : +1000 */ + int hue; /* -1000 : +1000 */ + int red_intensity; /* -1000 : +1000 */ + int green_intensity;/* -1000 : +1000 */ + int blue_intensity; /* -1000 : +1000 */ +#define VEQ_FLG_ITU_R_BT_601 0x00000000 /* ITU-R BT.601 colour space (default) */ +#define VEQ_FLG_ITU_R_BT_709 0x00000001 /* ITU-R BT.709 colour space */ +#define VEQ_FLG_ITU_MASK 0x0000000f + int flags; /* currently specifies ITU YCrCb color space to use */ +}vidix_video_eq_t; + + /* Returns 0 if ok else errno */ +extern int vixPlaybackGetEq( vidix_video_eq_t * ); + + /* Returns 0 if ok else errno */ +extern int vixPlaybackSetEq( const vidix_video_eq_t * ); + +typedef struct vidix_deinterlace_s +{ +#define CFG_NON_INTERLACED 0x00000000 /* stream is not interlaced */ +#define CFG_INTERLACED 0x00000001 /* stream is interlaced */ +#define CFG_EVEN_ODD_INTERLACING 0x00000002 /* first frame contains even fields but second - odd */ +#define CFG_ODD_EVEN_INTERLACING 0x00000004 /* first frame contains odd fields but second - even */ +#define CFG_UNIQUE_INTERLACING 0x00000008 /* field deinterlace_pattern is valid */ +#define CFG_UNKNOWN_INTERLACING 0x0000000f /* unknown deinterlacing - use adaptive if it's possible */ + unsigned flags; + unsigned deinterlace_pattern; /* app -> driver: deinterlace pattern if flag CFG_UNIQUE_INTERLACING is set */ +}vidix_deinterlace_t; + + /* Returns 0 if ok else errno */ +extern int vixPlaybackGetDeint( vidix_deinterlace_t * ); + + /* Returns 0 if ok else errno */ +extern int vixPlaybackSetDeint( const vidix_deinterlace_t * ); + +typedef struct vidix_slice_s +{ + void* address; /* app -> driver */ + unsigned size; /* app -> driver */ + vidix_rect_t slice; /* app -> driver */ +}vidix_slice_t; + +typedef struct vidix_dma_s +{ + void * src; /* app -> driver */ + unsigned dest_frame; /* app -> driver */ +#define BM_DMA_ASYNC 0 +#define BM_DMA_SYNC 1 /* means: wait dma transfer completion */ + unsigned flags; /* app -> driver */ +}vidix_dma_t; + + /* Returns 0 if ok else errno */ +extern int vixPlaybackCopyFrame( const vidix_dma_t * ); + + /* Returns 0 if DMA is available else errno (EBUSY) */ +extern int vixQueryDMAStatus( void ); +/* + This structure is introdused to support OEM effects like: + - sharpness + - exposure + - (auto)gain + - H(V)flip + - black level + - white balance + and many other +*/ +typedef struct vidix_oem_fx_s +{ +#define FX_TYPE_BOOLEAN 0x00000000 +#define FX_TYPE_INTEGER 0x00000001 + int type; /* type of effects */ + int num; /* app -> driver: effect number. From 0 to max number of effects */ + int minvalue; /* min value of effect. 0 - for boolean */ + int maxvalue; /* max value of effect. 1 - for boolean */ + int value; /* current value of effect on 'get'; required on set */ + char * name[80]; /* effect name to display */ +}vidix_oem_fx_t; + + /* Returns 0 if ok else errno */ +extern int vixQueryNumOemEffects( unsigned * number ); + + /* Returns 0 if ok else errno */ +extern int vixGetOemEffect( vidix_oem_fx_t * ); + + /* Returns 0 if ok else errno */ +extern int vixSetOemEffect( const vidix_oem_fx_t * ); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/src/video_out/vidix/vidix.txt b/src/video_out/vidix/vidix.txt new file mode 100644 index 000000000..a2eb4bc82 --- /dev/null +++ b/src/video_out/vidix/vidix.txt @@ -0,0 +1,154 @@ + VIDIX - VIDeo Interface for *niX + ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +This interface was designed and introduced as interface to userspace drivers +to provide DGA everywhere where it's possible (unline X11). +I hope that these drivers will be portable same as X11 (not only on *nix). + +What is it: +- It's portable successor of mga_vid technology which is located in user-space. +- Unlikely X11 it's provides DGA everywhere where it's possible. +- Unlikely v4l it provides interface for video playback +- Unlikely linux's drivers it uses mathematics library. + +Why it was developed: +As said Vladimir Dergachev +(http://cvs.sourceforge.net/cgi-bin/viewcvs.cgi/gatos/km/km.rfc.txt): +"0) Motivation + v4l, v4l2 and Xv are all suffering from the same problem: attempt to fit + existing multimedia devices into a fixed scheme." +Well - I tried to implement something similar by motivation. + +How it works: +~~~~~~~~~~~~~ + +This interface is almost finished. But I guess it can be expanded by developer's +requests. +So any suggestions, reports, criticism are gladly accepted. + +1) APP calls vixGetVersion to check age of driver ;) +2) APP calls vixProbe. Driver should return 0 if it can handle something in PC. +3) APP calls vixGetCapability. Driver should return filled + vidix_capability_t.type field at least. +4) If above calls were succesful then APP calls vixInit function + (Driver can have not exported this function in this case call will be + skiped). +5) After initializing of driver APP calls vixGetCapability again + (In this case driver must fill every field of struct) +6) APP calls vixQueryFourcc. Driver should answer - can it configure + video memory for given fourcc or not. +7) APP calls vixConfigPlayback. Driver should prepare BES on this call. + APP pass to driver following info: + ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + vidix_playback_t.fourcc - contains fourcc of movie + vidix_playback_t.capability - currently contsinas copy of vidix_capability_t.flags + vidix_playback_t.blend_factor- currently unused + vidix_playback_t.src - x,y,w,h fields contain original movie size + (in pixels) x and y often are nulls. + vidix_playback_t.src.pitch.y These fields contain source pitches + vidix_playback_t.src.pitch.u - for each Y,U,V plane in bytes. + vidix_playback_t.src.pitch.v (For packed fourcc only Y value is used) + They are hints for driver to use same destinition + pitches as in source memory (to speed up + memcpy process). + Note: when source pitches are unknown or + variable these field will be filled into 0. + vidix_playback_t.dest - x,y,w,h fields contains destinition rectange + on the screen in pixels. + vidix_playback_t.num_frames - maximal # of frames which can be used by APP. + (Currently 10). + Driver should fill following fields: + ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + vidix_playback_t.num_frames - real # of frames which will be used by driver. + (Should be less or equal to app's num_frames). + + vidix_playback_t.dest.pitch.y These fields should contain alignment + vidix_playback_t.dest.pitch.u - for each Y,U,V plane in bytes. + vidix_playback_t.dest.pitch.v (For packed fourcc only Y value is used) + + vidix_playback_t.frame_size - Driver should tell to app which size of + source frame (src.w and src.h) should + use APP (according to pitches and offsets) + + vidix_playback_t.offsets - offsets from begin of BES memory for each frame + + vidix_playback_t.offset.y These field should contain offset + vidix_playback_t.offset.u - for each Y,U,V plane within frame. + vidix_playback_t.offset.v (For packed fourcc only Y value is used) + + vidix_playback_t.dga_addr - Address of BES memory. + +Also see this picture: + +VIDEO MEMORY layout: + +----------- It's begin of video memory End of video memory--------------+ + | | + v v + [ RGB memory | YUV memory | UNDEF ] + ^ + | + +---- begin of BES memory + +BES MEMORY layout: + +-------- begin of BES memory + | + v + [ | | | | | + ^ ^ ^ ^ ^ + | | | | + BEGIN of second frame + | | | + BEGIN of V plane + | | + BEGIN of U plane + | +------- BEGIN of Y plane + | + +--------- BEGIN of first frame + +This means that in general case: +offset of frame != offset of BES +offset of Y plane != offset of first frame + +But often: vidix_playback_t.offsets[0] = vidix_playback_t.offset.y = 0; + +Formula: (For Y plane) copy source to: + vidix_playback_t.dga_addr + + vidix_playback_t.offsets[i] + + vidix_playback_t.offset.y + +8) APP calls vixPlaybackOn. Driver should activate BES on this call. +9) PLAYBACK. Driver should sleep here ;) + But during playback can be called: + vixFrameSelect (if this function is exported) + Driver should prepare and activate corresponded frame. + This function is used only for double and trilpe buffering and + never used for single buffering playback. + vixGet(Set)GrKeys (if this function is exported) + This interface should be tuned but intriduced for overlapped playback + and video effects (TYPE_FX) + vixPlaybackGet(Set)Eq (if this function is exported) + For color correction. +10) APP calls vixPlaybackOff. Driver should deactivate BES on this call. +11) If vixDestroy is defined APP calls this function before unloading driver + from memory. + + +What functions are mandatory: +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +vixGetVersion +vixProbe +vixGetCapability +vixQueryFourcc +vixConfigPlayback +vixPlaybackOn +vixPlaybackOff + +All other functions are optionaly. + +Useful links: +~~~~~~~~~~~~~ +Guide to DTV http://www.digitaltelevision.com/dtvbook/toc.shtml +Fourcc http://www.webartz.com/fourcc/ +MPEG http://www.mpeg.org/MPEG/index.html +Analog colors http://www.miranda.com/en/app_notes/TN/TN-05/TN-05.htm + +Please send your suggestions, reports, feedback to mplayerxp-general@lists.sourceforge.net + +Best regards! Nick Kurshev. diff --git a/src/video_out/vidix/vidixlib.c b/src/video_out/vidix/vidixlib.c new file mode 100644 index 000000000..4bc585060 --- /dev/null +++ b/src/video_out/vidix/vidixlib.c @@ -0,0 +1,337 @@ +/* + * vidixlib.c + * VIDIXLib - Library for VIDeo Interface for *niX + * This interface is introduced as universal one to MPEG decoder, + * BES == Back End Scaler and YUV2RGB hw accelerators. + * In the future it may be expanded up to capturing and audio things. + * Main goal of this this interface imlpementation is providing DGA + * everywhere where it's possible (unlike X11 and other). + * Copyright 2002 Nick Kurshev + * Licence: GPL + * This interface is based on v4l2, fbvid.h, mga_vid.h projects + * and personally my ideas. + * NOTE: This interface is introduces as APP interface. + * Don't use it for driver. + * It provides multistreaming. This mean that APP can handle + * several streams simultaneously. (Example: Video capturing and video + * playback or capturing, video playback, audio encoding and so on). +*/ +#include +#include +#include +#include +#include + +#include /* GLIBC specific. Exists under cygwin too! */ +#include + +#if defined(__OpenBSD__) && !defined(__ELF__) +#define dlsym(h,s) dlsym(h, "_" s) +#endif + +#include "vidixlib.h" +#include "bswap.h" + +static char drv_name[FILENAME_MAX]; + +typedef struct vdl_stream_s +{ + void * handle; + int (*get_caps)(vidix_capability_t *); + int (*query_fourcc)(vidix_fourcc_t *); + int (*config_playback)(vidix_playback_t *); + int (*playback_on)( void ); + int (*playback_off)( void ); + /* Functions below can be missed in driver ;) */ + int (*init)(void); + void (*destroy)(void); + int (*frame_sel)( unsigned frame_idx ); + int (*get_eq)( vidix_video_eq_t * ); + int (*set_eq)( const vidix_video_eq_t * ); + int (*get_deint)( vidix_deinterlace_t * ); + int (*set_deint)( const vidix_deinterlace_t * ); + int (*copy_frame)( const vidix_dma_t * ); + int (*query_dma)( void ); + int (*get_gkey)( vidix_grkey_t * ); + int (*set_gkey)( const vidix_grkey_t * ); + int (*get_num_fx)( unsigned * ); + int (*get_fx)( vidix_oem_fx_t * ); + int (*set_fx)( const vidix_oem_fx_t * ); +}vdl_stream_t; + +#define t_vdl(p) (((vdl_stream_t *)p)) + +extern unsigned vdlGetVersion( void ) +{ + return VIDIX_VERSION; +} + +static int vdl_fill_driver(VDL_HANDLE stream) +{ + t_vdl(stream)->init = dlsym(t_vdl(stream)->handle,"vixInit"); + t_vdl(stream)->destroy = dlsym(t_vdl(stream)->handle,"vixDestroy"); + t_vdl(stream)->get_caps = dlsym(t_vdl(stream)->handle,"vixGetCapability"); + t_vdl(stream)->query_fourcc = dlsym(t_vdl(stream)->handle,"vixQueryFourcc"); + t_vdl(stream)->config_playback= dlsym(t_vdl(stream)->handle,"vixConfigPlayback"); + t_vdl(stream)->playback_on = dlsym(t_vdl(stream)->handle,"vixPlaybackOn"); + t_vdl(stream)->playback_off = dlsym(t_vdl(stream)->handle,"vixPlaybackOff"); + t_vdl(stream)->frame_sel = dlsym(t_vdl(stream)->handle,"vixPlaybackFrameSelect"); + t_vdl(stream)->get_eq = dlsym(t_vdl(stream)->handle,"vixPlaybackGetEq"); + t_vdl(stream)->set_eq = dlsym(t_vdl(stream)->handle,"vixPlaybackSetEq"); + t_vdl(stream)->get_gkey = dlsym(t_vdl(stream)->handle,"vixGetGrKeys"); + t_vdl(stream)->set_gkey = dlsym(t_vdl(stream)->handle,"vixSetGrKeys"); + t_vdl(stream)->get_deint = dlsym(t_vdl(stream)->handle,"vixPlaybackGetDeint"); + t_vdl(stream)->set_deint = dlsym(t_vdl(stream)->handle,"vixPlaybackSetDeint"); + t_vdl(stream)->copy_frame = dlsym(t_vdl(stream)->handle,"vixPlaybackCopyFrame"); + t_vdl(stream)->query_dma = dlsym(t_vdl(stream)->handle,"vixQueryDMAStatus"); + t_vdl(stream)->get_num_fx = dlsym(t_vdl(stream)->handle,"vixQueryNumOemEffects"); + t_vdl(stream)->get_fx = dlsym(t_vdl(stream)->handle,"vixGetOemEffect"); + t_vdl(stream)->set_fx = dlsym(t_vdl(stream)->handle,"vixSetOemEffect"); + /* check driver viability */ + if(!( t_vdl(stream)->get_caps && t_vdl(stream)->query_fourcc && + t_vdl(stream)->config_playback && t_vdl(stream)->playback_on && + t_vdl(stream)->playback_off)) + { + printf("vidixlib: Incomplete driver: some of essential features are missed in it.\n"); + return 0; + } + return 1; +} + +#ifndef RTLD_GLOBAL +#define RTLD_GLOBAL RTLD_LAZY +#endif +#ifndef RTLD_NOW +#define RTLD_NOW RTLD_LAZY +#endif + +static int vdl_probe_driver(VDL_HANDLE stream,const char *path,const char *name,unsigned cap,int verbose) +{ + vidix_capability_t vid_cap; + unsigned (*_ver)(void); + int (*_probe)(int,int); + int (*_cap)(vidix_capability_t*); + strcpy(drv_name,path); + strcat(drv_name,name); + if(verbose) printf("vidixlib: PROBING: %s\n",drv_name); + if(!(t_vdl(stream)->handle = dlopen(drv_name,RTLD_LAZY|RTLD_GLOBAL))) + { + if(verbose) printf("vidixlib: %s not driver: %s\n",drv_name,dlerror()); + return 0; + } + _ver = dlsym(t_vdl(stream)->handle,"vixGetVersion"); + _probe = dlsym(t_vdl(stream)->handle,"vixProbe"); + _cap = dlsym(t_vdl(stream)->handle,"vixGetCapability"); + if(_ver) + { + if((*_ver)() != VIDIX_VERSION) + { + if(verbose) printf("vidixlib: %s has wrong version\n",drv_name); + err: + dlclose(t_vdl(stream)->handle); + t_vdl(stream)->handle = 0; + return 0; + } + } + else + { + fatal_err: + if(verbose) printf("vidixlib: %s has no function definition\n",drv_name); + goto err; + } + if(_probe) { if((*_probe)(verbose,PROBE_NORMAL) != 0) goto err; } + else goto fatal_err; + if(_cap) { if((*_cap)(&vid_cap) != 0) goto err; } + else goto fatal_err; + if((vid_cap.type & cap) != cap) + { + if(verbose) printf("vidixlib: Found %s but has no required capability\n",drv_name); + goto err; + } + if(verbose) printf("vidixlib: %s probed o'k\n",drv_name); + return 1; +} + +static int vdl_find_driver(VDL_HANDLE stream,const char *path,unsigned cap,int verbose) +{ + DIR *dstream; + struct dirent *name; + int done = 0; + if(!(dstream = opendir(path))) return 0; + while(!done) + { + name = readdir(dstream); + if(name) + { + if(name->d_name[0] != '.') + if(vdl_probe_driver(stream,path,name->d_name,cap,verbose)) break; + } + else done = 1; + } + closedir(dstream); + return done?0:1; +} + +VDL_HANDLE vdlOpen(const char *path,const char *name,unsigned cap,int verbose) +{ + vdl_stream_t *stream; + int errcode; + if(!(stream = malloc(sizeof(vdl_stream_t)))) return NULL; + memset(stream,0,sizeof(vdl_stream_t)); + if(name) + { + unsigned (*ver)(void); + int (*probe)(int,int); + unsigned version = 0; + strcpy(drv_name,path); + strcat(drv_name,name); + if(!(t_vdl(stream)->handle = dlopen(drv_name,RTLD_NOW|RTLD_GLOBAL))) + { + if (verbose) + printf("vidixlib: dlopen error: %s\n", dlerror()); + err: + free(stream); + return NULL; + } + ver = dlsym(t_vdl(stream)->handle,"vixGetVersion"); + if(ver) version = (*ver)(); + if(version != VIDIX_VERSION) + { + drv_err: + if(t_vdl(stream)->handle) dlclose(t_vdl(stream)->handle); + goto err; + } + probe = dlsym(t_vdl(stream)->handle,"vixProbe"); + if(probe) { if((*probe)(verbose,PROBE_FORCE)!=0) goto drv_err; } + else goto drv_err; + fill: + if(!vdl_fill_driver(stream)) goto drv_err; + goto ok; + } + else + if(vdl_find_driver(stream,path,cap,verbose)) + { + if(verbose) printf("vidixlib: will use %s driver\n",drv_name); + goto fill; + } + else goto err; + ok: + if(t_vdl(stream)->init) + { + if(verbose) printf("vidixlib: Attempt to initialize driver at: %p\n",t_vdl(stream)->init); + if((errcode=t_vdl(stream)->init())!=0) + { + if(verbose) printf("vidixlib: Can't init driver: %s\n",strerror(errcode)); + goto drv_err; + } + } + if(verbose) printf("vidixlib: '%s'successfully loaded\n",drv_name); + return stream; +} + +void vdlClose(VDL_HANDLE stream) +{ + if(t_vdl(stream)->destroy) t_vdl(stream)->destroy(); + dlclose(t_vdl(stream)->handle); + memset(stream,0,sizeof(vdl_stream_t)); /* <- it's not stupid */ + free(stream); +} + +int vdlGetCapability(VDL_HANDLE handle, vidix_capability_t *cap) +{ + return t_vdl(handle)->get_caps(cap); +} + +#define MPLAYER_IMGFMT_RGB (('R'<<24)|('G'<<16)|('B'<<8)) +#define MPLAYER_IMGFMT_BGR (('B'<<24)|('G'<<16)|('R'<<8)) +#define MPLAYER_IMGFMT_RGB_MASK 0xFFFFFF00 + +static uint32_t normalize_fourcc(uint32_t fourcc) +{ + if((fourcc & MPLAYER_IMGFMT_RGB_MASK) == (MPLAYER_IMGFMT_RGB|0) || + (fourcc & MPLAYER_IMGFMT_RGB_MASK) == (MPLAYER_IMGFMT_BGR|0)) + return bswap_32(fourcc); + else return fourcc; +} + +int vdlQueryFourcc(VDL_HANDLE handle,vidix_fourcc_t *f) +{ + f->fourcc = normalize_fourcc(f->fourcc); + return t_vdl(handle)->query_fourcc(f); +} + +int vdlConfigPlayback(VDL_HANDLE handle,vidix_playback_t *p) +{ + p->fourcc = normalize_fourcc(p->fourcc); + return t_vdl(handle)->config_playback(p); +} + +int vdlPlaybackOn(VDL_HANDLE handle) +{ + return t_vdl(handle)->playback_on(); +} + +int vdlPlaybackOff(VDL_HANDLE handle) +{ + return t_vdl(handle)->playback_off(); +} + +int vdlPlaybackFrameSelect(VDL_HANDLE handle, unsigned frame_idx ) +{ + return t_vdl(handle)->frame_sel ? t_vdl(handle)->frame_sel(frame_idx) : ENOSYS; +} + +int vdlPlaybackGetEq(VDL_HANDLE handle, vidix_video_eq_t * e) +{ + return t_vdl(handle)->get_eq ? t_vdl(handle)->get_eq(e) : ENOSYS; +} + +int vdlPlaybackSetEq(VDL_HANDLE handle, const vidix_video_eq_t * e) +{ + return t_vdl(handle)->set_eq ? t_vdl(handle)->set_eq(e) : ENOSYS; +} + +int vdlPlaybackCopyFrame(VDL_HANDLE handle, const vidix_dma_t * f) +{ + return t_vdl(handle)->copy_frame ? t_vdl(handle)->copy_frame(f) : ENOSYS; +} + +int vdlQueryDMAStatus(VDL_HANDLE handle ) +{ + return t_vdl(handle)->query_dma ? t_vdl(handle)->query_dma() : ENOSYS; +} + +int vdlGetGrKeys(VDL_HANDLE handle, vidix_grkey_t * k) +{ + return t_vdl(handle)->get_gkey ? t_vdl(handle)->get_gkey(k) : ENOSYS; +} + +int vdlSetGrKeys(VDL_HANDLE handle, const vidix_grkey_t * k) +{ + return t_vdl(handle)->set_gkey ? t_vdl(handle)->set_gkey(k) : ENOSYS; +} + +int vdlPlaybackGetDeint(VDL_HANDLE handle, vidix_deinterlace_t * d) +{ + return t_vdl(handle)->get_deint ? t_vdl(handle)->get_deint(d) : ENOSYS; +} + +int vdlPlaybackSetDeint(VDL_HANDLE handle, const vidix_deinterlace_t * d) +{ + return t_vdl(handle)->set_deint ? t_vdl(handle)->set_deint(d) : ENOSYS; +} + +int vdlQueryNumOemEffects(VDL_HANDLE handle, unsigned * number ) +{ + return t_vdl(handle)->get_num_fx ? t_vdl(handle)->get_num_fx(number) : ENOSYS; +} + +int vdlGetOemEffect(VDL_HANDLE handle, vidix_oem_fx_t * f) +{ + return t_vdl(handle)->get_fx ? t_vdl(handle)->get_fx(f) : ENOSYS; +} + +int vdlSetOemEffect(VDL_HANDLE handle, const vidix_oem_fx_t * f) +{ + return t_vdl(handle)->set_fx ? t_vdl(handle)->set_fx(f) : ENOSYS; +} diff --git a/src/video_out/vidix/vidixlib.h b/src/video_out/vidix/vidixlib.h new file mode 100644 index 000000000..19ab86615 --- /dev/null +++ b/src/video_out/vidix/vidixlib.h @@ -0,0 +1,101 @@ +/* + * vidixlib.h + * VIDIXLib - Library for VIDeo Interface for *niX + * This interface is introduced as universal one to MPEG decoder, + * BES == Back End Scaler and YUV2RGB hw accelerators. + * In the future it may be expanded up to capturing and audio things. + * Main goal of this this interface imlpementation is providing DGA + * everywhere where it's possible (unlike X11 and other). + * Copyright 2002 Nick Kurshev + * Licence: GPL + * This interface is based on v4l2, fbvid.h, mga_vid.h projects + * and personally my ideas. + * NOTE: This interface is introduces as APP interface. + * Don't use it for driver. + * It provides multistreaming. This mean that APP can handle + * several streams simultaneously. (Example: Video capturing and video + * playback or capturing, video playback, audio encoding and so on). +*/ +#ifndef VIDIXLIB_H +#define VIDIXLIB_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "vidix.h" + +typedef void * VDL_HANDLE; + + /* returns library version */ +extern unsigned vdlGetVersion( void ); + + /* Opens corresponded video driver and returns handle + of associated stream. + path - specifies path where drivers are located. + name - specifies prefered driver name (can be NULL). + cap - specifies driver capability (TYPE_* constants). + verbose - specifies verbose level + returns !0 if ok else NULL. + */ +extern VDL_HANDLE vdlOpen(const char *path,const char *name,unsigned cap,int verbose); + /* Closes stream and corresponded driver. */ +extern void vdlClose(VDL_HANDLE stream); + + /* Queries driver capabilities. Return 0 if ok else errno */ +extern int vdlGetCapability(VDL_HANDLE, vidix_capability_t *); + + /* Queries support for given fourcc. Returns 0 if ok else errno */ +extern int vdlQueryFourcc(VDL_HANDLE,vidix_fourcc_t *); + + /* Returns 0 if ok else errno */ +extern int vdlConfigPlayback(VDL_HANDLE, vidix_playback_t *); + + /* Returns 0 if ok else errno */ +extern int vdlPlaybackOn(VDL_HANDLE); + + /* Returns 0 if ok else errno */ +extern int vdlPlaybackOff(VDL_HANDLE); + + /* Returns 0 if ok else errno */ +extern int vdlPlaybackFrameSelect(VDL_HANDLE, unsigned frame_idx ); + + /* Returns 0 if ok else errno */ +extern int vdlGetGrKeys(VDL_HANDLE, vidix_grkey_t * ); + + /* Returns 0 if ok else errno */ +extern int vdlSetGrKeys(VDL_HANDLE, const vidix_grkey_t * ); + + /* Returns 0 if ok else errno */ +extern int vdlPlaybackGetEq(VDL_HANDLE, vidix_video_eq_t * ); + + /* Returns 0 if ok else errno */ +extern int vdlPlaybackSetEq(VDL_HANDLE, const vidix_video_eq_t * ); + + /* Returns 0 if ok else errno */ +extern int vdlPlaybackGetDeint(VDL_HANDLE, vidix_deinterlace_t * ); + + /* Returns 0 if ok else errno */ +extern int vdlPlaybackSetDeint(VDL_HANDLE, const vidix_deinterlace_t * ); + + /* Returns 0 if ok else errno */ +extern int vdlQueryNumOemEffects(VDL_HANDLE, unsigned * number ); + + /* Returns 0 if ok else errno */ +extern int vdlGetOemEffect(VDL_HANDLE, vidix_oem_fx_t * ); + + /* Returns 0 if ok else errno */ +extern int vdlSetOemEffect(VDL_HANDLE, const vidix_oem_fx_t * ); + + + /* Returns 0 if ok else errno */ +extern int vdlPlaybackCopyFrame(VDL_HANDLE, const vidix_dma_t * ); + + /* Returns 0 if DMA is available else errno (EBUSY) */ +extern int vdlQueryDMAStatus( VDL_HANDLE ); + +#ifdef __cplusplus +} +#endif + +#endif -- cgit v1.2.3