From f6aaa4c1e321c6657d20b8fe43693e451fa56d71 Mon Sep 17 00:00:00 2001 From: Alan Barrett Date: Mon, 19 May 2014 10:06:20 +0300 Subject: Require less GPRs for asm parameters. In affine_1d_MMX(), move the initialisation of %mm3 and %mm4 registers into a separate asm statement, to give the compiler more freedom for register allocation. Fixes a problem with gcc-4.5.4 on NetBSD/i386. --- src/post/planar/eq2.c | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) (limited to 'src') diff --git a/src/post/planar/eq2.c b/src/post/planar/eq2.c index 867699b3d..06d8cd3fd 100644 --- a/src/post/planar/eq2.c +++ b/src/post/planar/eq2.c @@ -126,8 +126,12 @@ void affine_1d_MMX (eq2_param_t *par, unsigned char *dst, unsigned char *src, while (h-- > 0) { asm volatile ( - "movq (%5), %%mm3 \n\t" - "movq (%6), %%mm4 \n\t" + "movq (%0), %%mm3 \n\t" + "movq (%1), %%mm4 \n\t" + : + : "r" (brvec), "r" (contvec) + ); + asm volatile ( "pxor %%mm0, %%mm0 \n\t" "movl %4, %%eax\n\t" ASMALIGN(4) @@ -149,7 +153,7 @@ void affine_1d_MMX (eq2_param_t *par, unsigned char *dst, unsigned char *src, "decl %%eax \n\t" "jnz 1b \n\t" : "=r" (src), "=r" (dst) - : "0" (src), "1" (dst), "r" (w >> 3), "r" (brvec), "r" (contvec) + : "0" (src), "1" (dst), "r" (w >> 3) : "%eax" ); -- cgit v1.2.3