- pinnacle 300i starts working a bit.

4 files changed, 127 insertions, 152 deletions

diff --git a/linux/drivers/media/video/saa7134/saa7134-dvb.c b/linux/drivers/media/video/saa7134/saa7134-dvb.c
index 968a9080c..2d336498c 100644
--- a/linux/drivers/media/video/saa7134/saa7134-dvb.c
+++ b/linux/drivers/media/video/saa7134/saa7134-dvb.c
@@ -1,5 +1,5 @@
 /*
- * $Id: saa7134-dvb.c,v 1.8 2005/01/13 17:22:33 kraxel Exp $
+ * $Id: saa7134-dvb.c,v 1.9 2005/01/14 13:29:40 kraxel Exp $
  *
  * (c) 2004 Gerd Knorr <kraxel@bytesex.org> [SuSE Labs]
  *
@@ -39,56 +39,7 @@ MODULE_LICENSE("GPL");
 
 /* ------------------------------------------------------------------ */
 
-static int mt352_pinnacle_fixup(struct dvb_frontend* fe)
-{
-	static u8 wr[][2] = {
-		{ 0x67, 0x28 },
-		{ 0x68, 0xa0 },
-		
-		{ 0x7b, 0x04 },
-		
-		{ 0x88, 0x0d },
-		{ 0x8a, 0x28 },
-		{ 0x8c, 0x0f },
-	};
-	struct saa7134_dev *dev= fe->dvb->priv;
-	int i;
-	
-	printk("%s: %s called\n",dev->name,__FUNCTION__);
-	for (i = 0; i < ARRAY_SIZE(wr); i++) {
-		mt352_write(fe, wr[i], 2);
-	}
-}
-
-static int mt352_pinnacle_init(struct dvb_frontend* fe)
-{
-	static u8 clock_config []  = { CLOCK_CTL,  0x3d, 0x39 };
-	static u8 reset []         = { RESET,      0x80 };
-	static u8 adc_ctl_1_cfg [] = { ADC_CTL_1,  0x40 };
-	static u8 agc_cfg []       = { AGC_TARGET, 0x20, 0x20 };
-	static u8 capt_range_cfg[] = { CAPT_RANGE, 0x31 };
-#if 0
-	// general purpose port pins
-	static u8 gpp_ctl_cfg []   = { GPP_CTL,    0x33 };
-#endif
-	struct saa7134_dev *dev= fe->dvb->priv;
-
-	printk("%s: %s called\n",dev->name,__FUNCTION__);
-
-	mt352_write(fe, clock_config,   sizeof(clock_config));
-	udelay(200);
-	mt352_write(fe, reset,          sizeof(reset));
-	mt352_write(fe, adc_ctl_1_cfg,  sizeof(adc_ctl_1_cfg));
-	mt352_write(fe, agc_cfg,        sizeof(agc_cfg));
-	mt352_write(fe, capt_range_cfg, sizeof(capt_range_cfg));
-
-#if 0
-	mt352_write(fe, gpp_ctl_cfg,    sizeof(gpp_ctl_cfg));
-#endif
-	return 0;
-}
-
-static int mt352_pinnacle_antenna_pwr(struct saa7134_dev *dev, int on)
+static int pinnacle_antenna_pwr(struct saa7134_dev *dev, int on)
 {
 	u32 ok;
 
@@ -116,26 +67,41 @@ static int mt352_pinnacle_antenna_pwr(struct saa7134_dev *dev, int on)
 	return ok;
 }
 
+static int mt352_pinnacle_init(struct dvb_frontend* fe)
+{
+	static u8 clock_config []  = { CLOCK_CTL,  0x3d, 0x28 };
+	static u8 reset []         = { RESET,      0x80 };
+	static u8 adc_ctl_1_cfg [] = { ADC_CTL_1,  0x40 };
+	static u8 agc_cfg []       = { AGC_TARGET, 0x28, 0xa0 };
+	static u8 capt_range_cfg[] = { CAPT_RANGE, 0x31 };
+	static u8 fsm_ctl_cfg[]    = { 0x7b,       0x04 };
+	static u8 gpp_ctl_cfg []   = { GPP_CTL,    0x0f };
+	static u8 scan_ctl_cfg []  = { SCAN_CTL,   0x0d };
+	struct saa7134_dev *dev= fe->dvb->priv;
+
+	printk("%s: %s called\n",dev->name,__FUNCTION__);
+
+	mt352_write(fe, clock_config,   sizeof(clock_config));
+	udelay(200);
+	mt352_write(fe, reset,          sizeof(reset));
+	mt352_write(fe, adc_ctl_1_cfg,  sizeof(adc_ctl_1_cfg));
+	mt352_write(fe, agc_cfg,        sizeof(agc_cfg));
+	mt352_write(fe, capt_range_cfg, sizeof(capt_range_cfg));
+	mt352_write(fe, gpp_ctl_cfg,    sizeof(gpp_ctl_cfg));
+
+	mt352_write(fe, fsm_ctl_cfg,    sizeof(fsm_ctl_cfg));
+	mt352_write(fe, scan_ctl_cfg,   sizeof(scan_ctl_cfg));
+	return 0;
+}
+
 static int mt352_pinnacle_pll_set(struct dvb_frontend* fe,
 				  struct dvb_frontend_parameters* params,
 				  u8* pllbuf)
 {
-	static u8 buf[][3] = {
-		/* set bandwidth (ADC frequency is 20.333 MHz) */
-		[ BANDWIDTH_6_MHZ ] = { TRL_NOMINAL_RATE_1, 0x56, 0x55 },
-		[ BANDWIDTH_7_MHZ ] = { TRL_NOMINAL_RATE_1, 0x64, 0xB8 },
-		[ BANDWIDTH_8_MHZ ] = { TRL_NOMINAL_RATE_1, 0x73, 0x1C },
-	};
 	static int on  = TDA9887_PRESENT | TDA9887_PORT2_INACTIVE;
 	static int off = TDA9887_PRESENT | TDA9887_PORT2_ACTIVE;
 	struct saa7134_dev *dev = fe->dvb->priv;
 	struct v4l2_frequency f;
-	int bw = params->u.ofdm.bandwidth;
-
-	printk("%s: %s called (freq=%d,bw=%d)\n",dev->name,__FUNCTION__,
-	       params->frequency,bw);
-
-	mt352_pinnacle_antenna_pwr(dev, 0);
 
 	/* set frequency (mt2050) */
 	f.tuner     = 0;
@@ -145,34 +111,23 @@ static int mt352_pinnacle_pll_set(struct dvb_frontend* fe,
 	saa7134_i2c_call_clients(dev,VIDIOC_S_FREQUENCY,&f);
 	saa7134_i2c_call_clients(dev,TDA9887_SET_CONFIG,&off);
 
+	pinnacle_antenna_pwr(dev, 0);
+
 	/* mt352 setup */
 	mt352_pinnacle_init(fe);
-	mt352_pinnacle_fixup(fe);
-	
 	pllbuf[0] = 0xc2;
 	pllbuf[1] = 0x00;
 	pllbuf[2] = 0x00;
 	pllbuf[3] = 0x80;
 	pllbuf[4] = 0x00;
-
-	if (bw < ARRAY_SIZE(buf) && NULL != buf[bw]) {
-#if 1
-		/* dirty hack time -- fixup mt352 buffer which has
-		 * adc freq 20.48 MHz values hardcoded */
-		pllbuf[-4] = buf[bw][1];
-		pllbuf[-3] = buf[bw][2];
-		pllbuf[-2] = 0x31; /* if 36.15 + adc 20.333 */
-		pllbuf[-1] = 0xB8;
-#else
-		mt352_write(fe, buf[bw], 3);
-#endif
-	}
-		
 	return 0;
 }
 
 static struct mt352_config pinnacle_300i = {
 	.demod_address = 0x3c >> 1,
+	.adc_clock     = 20333,
+	.if2           = 36150,
+	.no_tuner      = 1,
 	.demod_init    = mt352_pinnacle_init,
 	.pll_set       = mt352_pinnacle_pll_set,
 };
diff --git a/v4l/mt352.c b/v4l/mt352.c
index 7b0489dec..fe9ff3505 100644
--- a/v4l/mt352.c
+++ b/v4l/mt352.c
@@ -63,14 +63,13 @@ int mt352_write(struct dvb_frontend* fe, u8* ibuf, int ilen)
 	struct mt352_state* state = (struct mt352_state*) fe->demodulator_priv;
 	struct i2c_msg msg = { .addr = state->config->demod_address, .flags = 0,
 			       .buf = ibuf, .len = ilen };
-#if 0
-	int i;
-
-	printk("%s:",__FUNCTION__);
-	for (i = 0; i < ilen; i++)
-		printk(" %02x",ibuf[i]);
-	printk("\n");
-#endif
+	if (debug) {
+		int i;
+		printk("%s:",__FUNCTION__);
+		for (i = 0; i < ilen; i++)
+			printk(" %02x",ibuf[i]);
+		printk("\n");
+	}
 	
 	int err = i2c_transfer(state->i2c, &msg, 1);
 	if (err != 1) {
@@ -94,11 +93,13 @@ static u8 mt352_read_register(struct mt352_state* state, u8 reg)
 				    .flags = I2C_M_RD,
 				    .buf = b1, .len = 1 } };
 
-	for (i = 0; i < 3; i++) {
+	for (i = 0; i < 5; i++) {
 		ret = i2c_transfer(state->i2c, msg, 2);
 		if (2 == ret)
 			break;
-		udelay(10);
+		msleep(10);
+		dprintk("%s: readreg error #%d, retrying\n",
+			__FUNCTION__, i+1);
 	}
 
 	if (ret != 2)
@@ -108,51 +109,74 @@ static u8 mt352_read_register(struct mt352_state* state, u8 reg)
 	return b1[0];
 }
 
-static u8 mt352_register_dump(struct mt352_state* state)
+static int mt352_sleep(struct dvb_frontend* fe)
 {
-	int i,val;
+	static u8 mt352_softdown[] = { CLOCK_CTL, 0x20, 0x08 };
 
-	for (i = 0x50; i < 0x8f; i++) {
-		val = mt352_read_register(state,i);
-		printk("%s: %02x %02x\n",__FUNCTION__,i,val);
-	}
+	mt352_write(fe, mt352_softdown, sizeof(mt352_softdown));
+
+	return 0;
 }
 
-static u8 mt352_state_dump(struct mt352_state* state)
+static void mt352_calc_nominal_rate(struct mt352_state* state,
+				    enum fe_bandwidth bandwidth,
+				    unsigned char *buf)
 {
-	int i,val,agc,snr;
-
-	printk("mt352:  status:");
-	for (i = STATUS_0; i <= STATUS_4; i++) {
-		val = mt352_read_register(state,i);
-		printk(" %02x",val);
+	u32 adc_clock = 20480; /* 20.340 MHz */
+	u32 bw,value;
+
+	switch (bandwidth) {
+	case BANDWIDTH_6_MHZ:
+		bw = 6;
+		break;
+	case BANDWIDTH_7_MHZ:
+		bw = 7;
+		break;
+	case BANDWIDTH_8_MHZ:
+	default:
+		bw = 8;
+		break;
 	}
-	agc  = 0;
-	agc |= mt352_read_register(state,AGC_GAIN_3) << 24;
-	agc |= mt352_read_register(state,AGC_GAIN_2) << 16;
-	agc |= mt352_read_register(state,AGC_GAIN_1) <<  8;
-	agc |= mt352_read_register(state,AGC_GAIN_0);
-	snr  = mt352_read_register(state,SNR);
-	printk("  agc: %5d  snr: %02x\n", (~agc)>>16, snr);
+	if (state->config->adc_clock)
+		adc_clock = state->config->adc_clock;
+
+	value = 64 * bw * (1<<16) / (7 * 8);
+	value = value * 1000 / adc_clock;
+	dprintk("%s: bw %d, adc_clock %d => 0x%x\n",
+		__FUNCTION__, bw, adc_clock, value);
+	buf[0] = msb(value);
+	buf[1] = lsb(value);
 }
 
-static int mt352_sleep(struct dvb_frontend* fe)
+static void mt352_calc_input_freq(struct mt352_state* state,
+				  unsigned char *buf)
 {
-	static u8 mt352_softdown[] = { CLOCK_CTL, 0x20, 0x08 };
-
-	mt352_write(fe, mt352_softdown, sizeof(mt352_softdown));
-
-	return 0;
+	int adc_clock = 20480; /* 20.480000 MHz */
+	int if2       = 36167; /* 36.166667 MHz */
+	int ife,value;
+
+	if (state->config->adc_clock)
+		adc_clock = state->config->adc_clock;
+	if (state->config->if2)
+		if2 = state->config->if2;
+
+	ife = (2*adc_clock - if2);
+	value = -16374 * ife / adc_clock;
+	dprintk("%s: if2 %d, ife %d, adc_clock %d => %d / 0x%x\n",
+		__FUNCTION__, if2, ife, adc_clock, value, value & 0x3fff);
+	buf[0] = msb(value);
+	buf[1] = lsb(value);
 }
 
 static int mt352_set_parameters(struct dvb_frontend* fe,
 				struct dvb_frontend_parameters *param)
 {
 	struct mt352_state* state = (struct mt352_state*) fe->demodulator_priv;
-	unsigned char buf[14];
+	unsigned char buf[13];
+	static unsigned char tuner_go[] = { 0x5d, 0x01 };
+	static unsigned char fsm_go[]   = { 0x5e, 0x01 };
 	unsigned int tps = 0;
 	struct dvb_ofdm_parameters *op = &param->u.ofdm;
-	int i;
 
 	switch (op->code_rate_HP) {
 		case FEC_2_3:
@@ -263,49 +287,32 @@ static int mt352_set_parameters(struct dvb_frontend* fe,
 	buf[1] = msb(tps);      /* TPS_GIVEN_(1|0) */
 	buf[2] = lsb(tps);
 
-//	buf[3] = 0x50;
-	buf[3] = 0xf4;
-
-	/**
-	 *  these settings assume 20.48MHz f_ADC, for other tuners you might
-	 *  need other values. See p. 33 in the MT352 Design Manual.
-	 */
-	if (op->bandwidth == BANDWIDTH_8_MHZ) {
-		buf[4] = 0x72;  /* TRL_NOMINAL_RATE_(1|0) */
-		buf[5] = 0x49;
-	} else if (op->bandwidth == BANDWIDTH_7_MHZ) {
-		buf[4] = 0x64;
-		buf[5] = 0x00;
-	} else {		/* 6MHz */
-		buf[4] = 0x55;
-		buf[5] = 0xb7;
-	}
-
-	buf[6] = 0x31;  /* INPUT_FREQ_(1|0), 20.48MHz clock, 36.166667MHz IF */
-	buf[7] = 0x05;  /* see MT352 Design Manual page 32 for details */
+//	buf[3] = 0x50;  // old
+	buf[3] = 0xf4;  // pinnacle
 
+	mt352_calc_nominal_rate(state, op->bandwidth, buf+4);
+	mt352_calc_input_freq(state, buf+6);
 	state->config->pll_set(fe, param, buf+8);
 
-	buf[13] = 0x01; /* TUNER_GO!! */
-
-#if 0
+#if 0 /* FIXME: should be catched elsewhere ... */
 	/* Only send the tuning request if the tuner doesn't have the requested
 	 * parameters already set.  Enhances tuning time and prevents stream
 	 * breakup when retuning the same transponder. */
 	for (i = 1; i < 13; i++)
-		if (buf[i] != mt352_read_register(state, i + 0x50)) {
-			mt352_write(fe, buf, sizeof(buf));
+		if (buf[i] != mt352_read_register(state, i + 0x50))
 			break;
-		}
-#else
-	mt352_write(fe, buf, sizeof(buf));
+	if (13 == i)
+		/* no changes */
+		return 0;
 #endif
 
-	if (0)
-		mt352_register_dump(state);
-	for (i = 0; i < 2; i++) {
-		msleep(500);
-		mt352_state_dump(state);
+	mt352_write(fe, buf, sizeof(buf));
+	if (state->config->no_tuner) {
+		/* start decoding */
+		mt352_write(fe, fsm_go, 2);
+	} else {
+		/* start tuning */
+		mt352_write(fe, tuner_go, 2);
 	}
 	return 0;
 }
@@ -498,7 +505,7 @@ static int mt352_read_ucblocks(struct dvb_frontend* fe, u32* ucblocks)
 
 static int mt352_get_tune_settings(struct dvb_frontend* fe, struct dvb_frontend_tune_settings* fe_tune_settings)
 {
-	fe_tune_settings->min_delay_ms = 800 * 10000;
+	fe_tune_settings->min_delay_ms = 800;
 	fe_tune_settings->step_size = 0;
 	fe_tune_settings->max_drift = 0;
 
diff --git a/v4l/mt352.h b/v4l/mt352.h
index 635095b49..8bc032f7f 100644
--- a/v4l/mt352.h
+++ b/v4l/mt352.h
@@ -40,6 +40,13 @@ struct mt352_config
 	/* the demodulator's i2c address */
 	u8 demod_address;
 
+	/* frequencies in kHz */
+	int adc_clock;  // default: 20480
+	int if2;        // default: 36166
+
+	/* set if no pll is connected to the secondary i2c bus */
+	int no_tuner;
+
 	/* Initialise the demodulator and PLL. Cannot be NULL */
 	int (*demod_init)(struct dvb_frontend* fe);
 
@@ -56,3 +63,9 @@ extern struct dvb_frontend* mt352_attach(const struct mt352_config* config,
 extern int mt352_write(struct dvb_frontend* fe, u8* ibuf, int ilen);
 
 #endif // MT352_H
+
+/*
+ * Local variables:
+ * c-basic-offset: 8
+ * End:
+ */
diff --git a/v4l/scripts/update b/v4l/scripts/update
index 1a9731e47..0c2966ab5 100644
--- a/v4l/scripts/update
+++ b/v4l/scripts/update
@@ -99,5 +99,5 @@ xinsmod saa7134-empress
 xinsmod cx22702 debug=0
 xinsmod mt352	debug=1
 xinsmod video-buf-dvb
-xinsmod cx88-dvb
+#xinsmod cx88-dvb
 xinsmod saa7134-dvb