- alpha has to be 1, even when hierarchy is off

- modified the tuning auto search behaviour
- inversion is now detected automatically, too
- some cleanups, added some more debug printks

2 files changed, 287 insertions, 313 deletions

diff --git a/linux/drivers/media/dvb/frontends/dib3000mb.c b/linux/drivers/media/dvb/frontends/dib3000mb.c
index 5e2276ef2..6d0da4688 100644
--- a/linux/drivers/media/dvb/frontends/dib3000mb.c
+++ b/linux/drivers/media/dvb/frontends/dib3000mb.c
@@ -40,7 +40,7 @@ MODULE_PARM_DESC(debug, "Turn on/off debugging (default:off).");
 #define dprintk if (debug) printk
 
 /* Version information */
-#define DRIVER_VERSION "0.0"
+#define DRIVER_VERSION "0.1"
 #define DRIVER_DESC "DiBcom 3000-MB DVB-T frontend"
 #define DRIVER_AUTHOR "Patrick Boettcher, patrick.boettcher@desy.de"
 
@@ -67,8 +67,8 @@ static struct dvb_frontend_info dib3000mb_info = {
 };
 
 
-#define rd(reg) dib3000mb_read_reg(i2c,reg)
-#define wr(reg,val) if (dib3000mb_write_reg(i2c,reg,val)) \
+#define rd(reg) dib3000mb_read_reg(state->i2c,reg)
+#define wr(reg,val) if (dib3000mb_write_reg(state->i2c,reg,val)) \
 	{ err("while sending 0x%04x to 0x%04x.",val,reg); return -EREMOTEIO; }
 #define wr_foreach(a,v) { int i; \
 	dprintk("sizeof: %d %d\n",sizeof(a),sizeof(v));\
@@ -107,7 +107,6 @@ static int dib3000mb_write_reg(struct i2c_client *i2c,u16 reg, u16 val)
 static int dib3000mb_tuner_thomson_cable_eu(struct dib3000mb_state *state,
 		u32 freq)
 {
-	struct i2c_client *i2c = state->i2c;
 	u32 tfreq = (freq + 36125000) / 62500;
 	unsigned int addr;
 	int vu,p0,p1,p2;
@@ -121,188 +120,248 @@ static int dib3000mb_tuner_thomson_cable_eu(struct dib3000mb_state *state,
 	else 
 		return -EINVAL;
 	/* TODO better solution for i2c->addr handling */
-	addr = i2c->addr;
-	i2c->addr = DIB3000MB_TUNER_ADDR_DEFAULT;
+	addr = state->i2c->addr;
+	state->i2c->addr = DIB3000MB_TUNER_ADDR_DEFAULT;
 	wr(tfreq & 0x7fff,(0x8e << 8) + ((vu << 7) | (p2 << 2) | (p1 << 1) | p0) );
-	i2c->addr = addr;
+	state->i2c->addr = addr;
 	
 	return 0;
 }
 
-struct dib3000mb_fe_param {
-	u16 qam;
-	u16 fft;
-	u16 guard;
-	u16 alpha;
-	u16 hrch;
-	u16 hp;
-	u16 cr;
-	u16 inv;
-	u16 seq;
-	u8 qam_vit_manual;
-};
-
-static int dib3000mb_fe_set_parameters(struct dib3000mb_state *state,
-		struct dib3000mb_fe_param *p)
+static int dib3000mb_get_frontend(struct dib3000mb_state *state, 
+		struct dvb_frontend_parameters *fep)
 {
-	struct i2c_client *i2c = state->i2c;
-
-	wr(DIB3000MB_REG_LOCK1_MASK,DIB3000MB_LOCK1_SEARCH_4);
-	
-	dprintk("inversion: %d, seq: %d\n",p->inv,p->seq);
+	struct dvb_ofdm_parameters *ofdm = &fep->u.ofdm;
+	fe_code_rate_t *cr;
+	u16 tps_val;
+	int inv_test1,inv_test2;
+	u32 dds_val, threshold = 0x800000;
 	
-	wr(DIB3000MB_REG_FFT,p->fft);
-	wr(DIB3000MB_REG_GUARD_TIME,p->guard);
-	wr(DIB3000MB_REG_DDS_INV,p->inv);
+	if (!rd(DIB3000MB_REG_TPS_LOCK)) 
+		return -EINVAL;
+
+	dds_val = ((rd(DIB3000MB_REG_DDS_VALUE_MSB) & 0xff) << 16) + rd(DIB3000MB_REG_DDS_VALUE_LSB);
+	if (dds_val & threshold)
+		inv_test1 = 0;
+	else if (dds_val == threshold) 
+		inv_test1 = 1;
+	else 
+		inv_test1 = 2;
+
+	dds_val = ((rd(DIB3000MB_REG_DDS_FREQ_MSB) & 0xff) << 16) + rd(DIB3000MB_REG_DDS_FREQ_LSB);
+	if (dds_val & threshold)
+		inv_test2 = 0;
+	else if (dds_val == threshold) 
+		inv_test2 = 1;
+	else 
+		inv_test2 = 2;
 	
-	wr(DIB3000MB_REG_SEQ,p->seq);
+	fep->inversion = 
+		((inv_test2 == 2) && (inv_test1==1 || inv_test1==0))
+					||
+		((inv_test2 == 0) && (inv_test1==1 || inv_test1==2));
+
+	dprintk("inversion %d %d, %d\n",inv_test2,inv_test1, fep->inversion);
 	
-	wr(DIB3000MB_REG_ISI,p->seq ? DIB3000MB_ISI_INHIBIT : DIB3000MB_ISI_ACTIVATE);
+	switch ((tps_val = rd(DIB3000MB_REG_TPS_QAM))) {
+		case DIB3000MB_QAM_QPSK:
+			dprintk("QPSK ");
+			ofdm->constellation = QPSK;
+			break;
+		case DIB3000MB_QAM_QAM16:
+			dprintk("QAM16 ");
+			ofdm->constellation = QAM_16;
+			break;
+		case DIB3000MB_QAM_QAM64:
+			dprintk("QAM64 ");
+			ofdm->constellation = QAM_64;
+			break;
+		default:
+			err("Unexpected constellation returned by TPS (%d)",tps_val);
+			break;
+ 	}
+	dprintk("TPS: %d\n",tps_val);
 
-	if (p->fft == DIB3000MB_FFT_2K) {
-		if (p->guard == DIB3000MB_GUARD_TIME_1_8) {
-			wr(DIB3000MB_REG_SYNC_IMPROVEMENT,DIB3000MB_SYNC_IMPROVE_2K_1_8);
-		} else {
-			wr(DIB3000MB_REG_SYNC_IMPROVEMENT,DIB3000MB_SYNC_IMPROVE_DEFAULT);
-		}
+	if (rd(DIB3000MB_REG_TPS_HRCH)) {
+		dprintk("HRCH ON\n");
+		tps_val = rd(DIB3000MB_REG_TPS_CODE_RATE_LP);
+		cr = &ofdm->code_rate_LP;
+		ofdm->code_rate_HP = FEC_NONE;
 		
-		wr(DIB3000MB_REG_UNK_121,DIB3000MB_UNK_121_2K);
+		switch ((tps_val = rd(DIB3000MB_REG_TPS_VIT_ALPHA))) {
+			case DIB3000MB_VIT_ALPHA_OFF:
+				dprintk("HIERARCHY_NONE ");
+				ofdm->hierarchy_information = HIERARCHY_NONE;
+				break;
+			case DIB3000MB_VIT_ALPHA_1:
+				dprintk("HIERARCHY_1 ");
+				ofdm->hierarchy_information = HIERARCHY_1;
+				break;
+			case DIB3000MB_VIT_ALPHA_2:
+				dprintk("HIERARCHY_2 ");
+				ofdm->hierarchy_information = HIERARCHY_2;
+				break;
+			case DIB3000MB_VIT_ALPHA_4:
+				dprintk("HIERARCHY_4 ");
+				ofdm->hierarchy_information = HIERARCHY_4;
+				break;
+			default:
+				err("Unexpected ALPHA value returned by TPS (%d)",tps_val);
+		}	
+		dprintk("TPS: %d\n",tps_val);
 	} else {
-		wr(DIB3000MB_REG_UNK_121,DIB3000MB_UNK_121_DEFAULT);
+		dprintk("HRCH OFF\n");
+		tps_val = rd(DIB3000MB_REG_TPS_CODE_RATE_HP);
+		cr = &ofdm->code_rate_HP;
+		ofdm->code_rate_LP = FEC_NONE;
+		ofdm->hierarchy_information = HIERARCHY_NONE;
 	}
 
-	if (p->qam_vit_manual) {
-		wr(DIB3000MB_REG_QAM,p->qam);
-		wr(DIB3000MB_REG_VIT_ALPHA,p->alpha);
-		wr(DIB3000MB_REG_VIT_HRCH,p->hrch);
-		wr(DIB3000MB_REG_VIT_HP,p->hp);
-		wr(DIB3000MB_REG_VIT_CODE_RATE,p->cr);
+	switch (tps_val) {
+		case DIB3000MB_FEC_1_2:
+			dprintk("FEC_1_2 ");
+			*cr = FEC_1_2;
+			break;
+		case DIB3000MB_FEC_2_3:
+			dprintk("FEC_2_3 ");
+			*cr = FEC_2_3;
+			break;
+		case DIB3000MB_FEC_3_4:
+			dprintk("FEC_3_4 ");
+			*cr = FEC_3_4;
+			break;
+		case DIB3000MB_FEC_5_6:
+			dprintk("FEC_5_6 ");
+			*cr = FEC_4_5;
+			break;
+		case DIB3000MB_FEC_7_8:
+			dprintk("FEC_7_8 ");
+			*cr = FEC_7_8;
+			break;
+		default:
+			err("Unexpected FEC returned by TPS (%d)",tps_val);
+			break;
 	}
+	dprintk("TPS: %d\n",tps_val);
 	
-	wr(DIB3000MB_REG_MOBILE_ALGO,DIB3000MB_MOBILE_ALGO_OFF);
-	wr(DIB3000MB_REG_MOBILE_MODE_QAM,DIB3000MB_MOBILE_MODE_QAM_OFF);
-	wr(DIB3000MB_REG_MOBILE_MODE,DIB3000MB_MOBILE_MODE_OFF);
+	switch ((tps_val = rd(DIB3000MB_REG_TPS_GUARD_TIME))) {
+		case DIB3000MB_GUARD_TIME_1_32:
+			dprintk("GUARD_INTERVAL_1_32 ");
+			ofdm->guard_interval = GUARD_INTERVAL_1_32;
+			break;
+		case DIB3000MB_GUARD_TIME_1_16:
+			dprintk("GUARD_INTERVAL_1_16 ");
+			ofdm->guard_interval = GUARD_INTERVAL_1_16;
+			break;
+		case DIB3000MB_GUARD_TIME_1_8:
+			dprintk("GUARD_INTERVAL_1_8 ");
+			ofdm->guard_interval = GUARD_INTERVAL_1_8;
+			break;
+		case DIB3000MB_GUARD_TIME_1_4:
+			dprintk("GUARD_INTERVAL_1_4 ");
+			ofdm->guard_interval = GUARD_INTERVAL_1_4;
+			break;
+		default:
+			err("Unexpected Guard Time returned by TPS (%d)",tps_val);
+			break;
+	}
+	dprintk("TPS: %d\n",tps_val);
+	
+	switch ((tps_val = rd(DIB3000MB_REG_TPS_FFT))) {
+		case DIB3000MB_FFT_2K:
+			dprintk("TRANSMISSION_MODE_2K ");
+			ofdm->transmission_mode = TRANSMISSION_MODE_2K;
+			break;
+		case DIB3000MB_FFT_8K:
+			dprintk("TRANSMISSION_MODE_8K ");
+			ofdm->transmission_mode = TRANSMISSION_MODE_8K;
+			break;
+		default:
+			err("unexpected transmission mode return by TPS (%d)",tps_val);
+	}
+	dprintk("TPS: %d\n",tps_val);
 	return 0;
-}	
+}
+
+static int dib3000mb_set_frontend(struct dib3000mb_state *state,
+		struct dvb_frontend_parameters *fep, int tuner);
 
 static int dib3000mb_fe_read_search_status(struct dib3000mb_state *state) 
 {
-	struct i2c_client *i2c = state->i2c;
 	u16 irq;
-	u16 lock;
-	struct dib3000mb_fe_param p;
+	struct dvb_frontend_parameters fep;
 	
 	irq = rd(DIB3000MB_REG_AS_IRQ_PENDING);
 
 	if (irq & 0x02) {
-		dprintk("autoval: tps: %d, qam: %d, hrch: %d, alpha: %d, hp: %d, lp: %d, guard: %d, fft: %d cell: %d\n",
-			rd(DIB3000MB_REG_TPS_LOCK),
-			rd(DIB3000MB_REG_TPS_QAM), 
-			rd(DIB3000MB_REG_TPS_HRCH),
-			rd(DIB3000MB_REG_TPS_VIT_ALPHA),
-			rd(DIB3000MB_REG_TPS_CODE_RATE_HP),
-			rd(DIB3000MB_REG_TPS_CODE_RATE_LP), 
-			rd(DIB3000MB_REG_TPS_GUARD_TIME),
-			rd(DIB3000MB_REG_TPS_FFT),
-			rd(DIB3000MB_REG_TPS_CELL_ID));
-
-		if (rd(DIB3000MB_REG_TPS_LOCK) && rd(DIB3000MB_REG_LOCK2_VALUE)) {
-			int inv_test1,inv_test2;
-			u32 dds_val, threshold = 0x800000;
-			
-			p.qam = rd(DIB3000MB_REG_TPS_QAM);
-			p.hrch = rd(DIB3000MB_REG_TPS_HRCH);  
-			p.alpha = rd(DIB3000MB_REG_TPS_VIT_ALPHA); 
-			p.hp = !p.hrch;
-			p.cr = p.hp ? rd(DIB3000MB_REG_TPS_CODE_RATE_HP) : 
-				rd(DIB3000MB_REG_TPS_CODE_RATE_LP);
-			p.guard = rd(DIB3000MB_REG_TPS_GUARD_TIME);
-			p.fft = rd(DIB3000MB_REG_TPS_FFT);
-			p.seq = 0;
-			p.qam_vit_manual = 0;
-
-			dds_val = (rd(DIB3000MB_REG_DDS_VALUE_MSB & 0xff) << 16) + rd(DIB3000MB_REG_DDS_VALUE_LSB);
-			if (dds_val & threshold)
-				inv_test1 = 0;
-			else if (dds_val == threshold) 
-				inv_test1 = 1;
-			else 
-				inv_test1 = 2;
-
-			dds_val = (rd(DIB3000MB_REG_DDS_FREQ_MSB & 0xff) << 16) + rd(DIB3000MB_REG_DDS_FREQ_LSB);
-			if (dds_val & threshold)
-				inv_test2 = 0;
-			else if (dds_val == threshold) 
-				inv_test2 = 1;
-			else 
-				inv_test2 = 2;
-			
-			p.inv = ((inv_test2 == 2) && (inv_test1==1 || inv_test1==0))
-							||
-					((inv_test2 == 0) && (inv_test1==1 || inv_test1==2));
-
-			dib3000mb_fe_set_parameters(state,&p);
-			
-			wr(DIB3000MB_REG_RESTART,DIB3000MB_RESTART_CTRL);
-			wr(DIB3000MB_REG_RESTART,DIB3000MB_RESTART_OFF);
-
-			msleep(70);
-			
-			return 1;
-		} else
+		if (rd(DIB3000MB_REG_LOCK2_VALUE) & 0x01) {
+			if (dib3000mb_get_frontend(state,&fep) == 0) {
+				dprintk("reading tuning data from frontend succeeded.\n");
+				return dib3000mb_set_frontend(state,&fep,0);
+			} else {
+				dprintk("reading tuning data failed -> tuning failed.\n");
+				return 0;
+			}
+		} else {
+			dprintk("AS IRQ was pending, but LOCK2 was not & 0x01.\n");
 			return 0;
-	} else if (irq & 0x01)
+		}
+	} else if (irq & 0x01) {
+		dprintk("Autosearch failed.\n");
 		return 0;
+	}
 
 	return -1;
 }
 
 static int dib3000mb_set_frontend(struct dib3000mb_state *state,
-		struct dvb_frontend_parameters *fep)
+		struct dvb_frontend_parameters *fep, int tuner)
 {
-	struct i2c_client *i2c = state->i2c;
 	struct dvb_ofdm_parameters *ofdm = &fep->u.ofdm;
 	fe_code_rate_t fe_cr;
-	struct dib3000mb_fe_param par;
-	
-	wr(DIB3000MB_REG_TUNER,
-			DIB3000MB_ACTIVATE_TUNER_XFER( DIB3000MB_TUNER_ADDR_DEFAULT ) );
-	dib3000mb_tuner_thomson_cable_eu(state,fep->frequency);
+	int search_state,seq;
 	
-	/* wait for tuner */
-	msleep(1);
-	wr(DIB3000MB_REG_TUNER, 
-			DIB3000MB_DEACTIVATE_TUNER_XFER( DIB3000MB_TUNER_ADDR_DEFAULT ) );
+	if (tuner) {
+		wr(DIB3000MB_REG_TUNER,
+				DIB3000MB_ACTIVATE_TUNER_XFER( DIB3000MB_TUNER_ADDR_DEFAULT ) );
+		dib3000mb_tuner_thomson_cable_eu(state,fep->frequency);
+		
+		/* wait for tuner */
+		msleep(1);
+		wr(DIB3000MB_REG_TUNER, 
+				DIB3000MB_DEACTIVATE_TUNER_XFER( DIB3000MB_TUNER_ADDR_DEFAULT ) );
+
+		switch (ofdm->bandwidth) {
+			case BANDWIDTH_8_MHZ:
+			case BANDWIDTH_AUTO:
+				wr_foreach(dib3000mb_reg_timing_freq,dib3000mb_timing_freq[2]);
+				wr_foreach(dib3000mb_reg_bandwidth,dib3000mb_bandwidth_8mhz);
+				break;
+			case BANDWIDTH_7_MHZ:
+				wr_foreach(dib3000mb_reg_timing_freq,dib3000mb_timing_freq[1]);
+				wr_foreach(dib3000mb_reg_bandwidth,dib3000mb_bandwidth_7mhz);
+				break;
+			case BANDWIDTH_6_MHZ:
+				wr_foreach(dib3000mb_reg_timing_freq,dib3000mb_timing_freq[0]);
+				wr_foreach(dib3000mb_reg_bandwidth,dib3000mb_bandwidth_6mhz);
+				break;
+			default:
+				err("unkown bandwidth value.");
+				return -EINVAL;
+				break;
+		}
+	}	
+	wr(DIB3000MB_REG_LOCK1_MASK,DIB3000MB_LOCK1_SEARCH_4);
 
-	switch (ofdm->bandwidth) {
-		case BANDWIDTH_8_MHZ:
-		case BANDWIDTH_AUTO:
-			wr_foreach(dib3000mb_reg_timing_freq,dib3000mb_timing_freq[2]);
-			wr_foreach(dib3000mb_reg_bandwidth,dib3000mb_bandwidth_8mhz);
-			break;
-		case BANDWIDTH_7_MHZ:
-			wr_foreach(dib3000mb_reg_timing_freq,dib3000mb_timing_freq[1]);
-			wr_foreach(dib3000mb_reg_bandwidth,dib3000mb_bandwidth_7mhz);
-			break;
-		case BANDWIDTH_6_MHZ:
-			wr_foreach(dib3000mb_reg_timing_freq,dib3000mb_timing_freq[0]);
-			wr_foreach(dib3000mb_reg_bandwidth,dib3000mb_bandwidth_6mhz);
-			break;
-		default:
-			err("unkown bandwidth value.");
-			return -EINVAL;
-			break;
-	}
-	
 	switch (ofdm->transmission_mode) {
 		case TRANSMISSION_MODE_2K:
-			par.fft = DIB3000MB_FFT_2K;		
+			wr(DIB3000MB_REG_FFT,DIB3000MB_FFT_2K);
 			break;
 		case TRANSMISSION_MODE_8K:
-			par.fft = DIB3000MB_FFT_8K;
+			wr(DIB3000MB_REG_FFT,DIB3000MB_FFT_8K);
 			break;
 		case TRANSMISSION_MODE_AUTO:
-			par.fft = DIB3000MB_FFT_AUTO;
+			wr(DIB3000MB_REG_FFT,DIB3000MB_FFT_AUTO);
 			break;
 		default:
 			return -EINVAL;
@@ -310,19 +369,19 @@ static int dib3000mb_set_frontend(struct dib3000mb_state *state,
 	
 	switch (ofdm->guard_interval) {
 		case GUARD_INTERVAL_1_32:
-			par.guard = DIB3000MB_GUARD_TIME_1_32;
+			wr(DIB3000MB_REG_GUARD_TIME,DIB3000MB_GUARD_TIME_1_32);
 			break;
 		case GUARD_INTERVAL_1_16:
-			par.guard = DIB3000MB_GUARD_TIME_1_16;
+			wr(DIB3000MB_REG_GUARD_TIME,DIB3000MB_GUARD_TIME_1_16);
 			break;
 		case GUARD_INTERVAL_1_8:
-			par.guard = DIB3000MB_GUARD_TIME_1_8;
+			wr(DIB3000MB_REG_GUARD_TIME,DIB3000MB_GUARD_TIME_1_8);
 			break;
 		case GUARD_INTERVAL_1_4:
-			par.guard = DIB3000MB_GUARD_TIME_1_4;
+			wr(DIB3000MB_REG_GUARD_TIME,DIB3000MB_GUARD_TIME_1_4);
 			break;
 		case GUARD_INTERVAL_AUTO:
-			par.guard = DIB3000MB_GUARD_TIME_AUTO;
+			wr(DIB3000MB_REG_GUARD_TIME,DIB3000MB_GUARD_TIME_AUTO);
 			break;
 		default:
 			return -EINVAL;
@@ -330,11 +389,11 @@ static int dib3000mb_set_frontend(struct dib3000mb_state *state,
 
 	switch (fep->inversion) {
 		case INVERSION_OFF:
-			par.inv = DIB3000MB_DDS_INV_OFF;
+			wr(DIB3000MB_REG_DDS_INV,DIB3000MB_DDS_INV_OFF);
 			break;
 		case INVERSION_AUTO:
 		case INVERSION_ON:
-			par.inv = DIB3000MB_DDS_INV_ON;
+			wr(DIB3000MB_REG_DDS_INV,DIB3000MB_DDS_INV_ON);
 			break;
 		default:
 			return -EINVAL;
@@ -342,13 +401,13 @@ static int dib3000mb_set_frontend(struct dib3000mb_state *state,
 	
 	switch (ofdm->constellation) {
 		case QPSK:
-			par.qam = DIB3000MB_QAM_QPSK;
+			wr(DIB3000MB_REG_QAM,DIB3000MB_QAM_QPSK);
 			break;
 		case QAM_16:
-			par.qam = DIB3000MB_QAM_QAM16;
+			wr(DIB3000MB_REG_QAM,DIB3000MB_QAM_QAM16);
 			break;
 		case QAM_64:
-			par.qam = DIB3000MB_QAM_QAM64;
+			wr(DIB3000MB_REG_QAM,DIB3000MB_QAM_QAM64);
 			break;
 		case QAM_AUTO:
 			break;
@@ -358,49 +417,47 @@ static int dib3000mb_set_frontend(struct dib3000mb_state *state,
 	
 	switch (ofdm->hierarchy_information) {
 		case HIERARCHY_NONE:
-			par.alpha = DIB3000MB_VIT_ALPHA_OFF;
-			break;
 		case HIERARCHY_1:
-			par.alpha = DIB3000MB_VIT_ALPHA_1;
+			wr(DIB3000MB_REG_VIT_ALPHA,DIB3000MB_VIT_ALPHA_1);
 			break;
 		case HIERARCHY_2:
-			par.alpha = DIB3000MB_VIT_ALPHA_2;
+			wr(DIB3000MB_REG_VIT_ALPHA,DIB3000MB_VIT_ALPHA_2);
 			break;
 		case HIERARCHY_4:
-			par.alpha = DIB3000MB_VIT_ALPHA_4;
+			wr(DIB3000MB_REG_VIT_ALPHA,DIB3000MB_VIT_ALPHA_4);
 			break; 
 		case HIERARCHY_AUTO:
-			par.alpha = DIB3000MB_VIT_ALPHA_AUTO;
+			wr(DIB3000MB_REG_VIT_ALPHA,DIB3000MB_VIT_ALPHA_AUTO);
 			break;
 		default:
 			return -EINVAL;
 	}
 	
 	if (ofdm->hierarchy_information == HIERARCHY_NONE) {
-		par.hrch = DIB3000MB_VIT_HRCH_OFF;
-		par.hp = DIB3000MB_VIT_HP;
+		wr(DIB3000MB_REG_VIT_HRCH,DIB3000MB_VIT_HRCH_OFF);
+		wr(DIB3000MB_REG_VIT_HP,DIB3000MB_VIT_HP);
 		fe_cr = ofdm->code_rate_HP;
 	} else {
-		par.hrch = DIB3000MB_VIT_HRCH_ON;
-		par.hp = DIB3000MB_VIT_LP;
+		wr(DIB3000MB_REG_VIT_HRCH,DIB3000MB_VIT_HRCH_ON);
+		wr(DIB3000MB_REG_VIT_HP,DIB3000MB_VIT_LP);
 		fe_cr = ofdm->code_rate_LP;
 	}
 			
 	switch (fe_cr) {
 		case FEC_1_2:
-			par.cr = DIB3000MB_FEC_1_2;	
+			wr(DIB3000MB_REG_VIT_CODE_RATE,DIB3000MB_FEC_1_2);
 			break;
 		case FEC_2_3:
-			par.cr = DIB3000MB_FEC_2_3;
+			wr(DIB3000MB_REG_VIT_CODE_RATE,DIB3000MB_FEC_2_3);
 			break;
 		case FEC_3_4:
-			par.cr = DIB3000MB_FEC_3_4;
+			wr(DIB3000MB_REG_VIT_CODE_RATE,DIB3000MB_FEC_3_4);
 			break;
 		case FEC_5_6:
-			par.cr = DIB3000MB_FEC_5_6;
+			wr(DIB3000MB_REG_VIT_CODE_RATE,DIB3000MB_FEC_5_6);
 			break;
 		case FEC_7_8:
-			par.cr = DIB3000MB_FEC_7_8;
+			wr(DIB3000MB_REG_VIT_CODE_RATE,DIB3000MB_FEC_7_8);
 			break;
 		case FEC_NONE:
 		case FEC_AUTO:
@@ -409,19 +466,32 @@ static int dib3000mb_set_frontend(struct dib3000mb_state *state,
 			return -EINVAL;
 	}	
 	
-	par.seq = dib3000mb_seq
+	seq = dib3000mb_seq
 		[ofdm->transmission_mode == TRANSMISSION_MODE_AUTO]
 		[ofdm->guard_interval == GUARD_INTERVAL_AUTO]
 		[fep->inversion == INVERSION_AUTO];
 
-	par.qam_vit_manual = (ofdm->constellation != QAM_AUTO && 
-						ofdm->hierarchy_information != HIERARCHY_AUTO &&
-						ofdm->code_rate_HP != FEC_AUTO &&
-						ofdm->code_rate_LP != FEC_AUTO);
+	dprintk("seq? %d\n",seq);
 	
-	dprintk("auto search will be enabled? %d %d\n",par.seq,!par.qam_vit_manual);
+	wr(DIB3000MB_REG_SEQ,seq);
+	
+	wr(DIB3000MB_REG_ISI,seq ? DIB3000MB_ISI_INHIBIT : DIB3000MB_ISI_ACTIVATE);
+
+	if (ofdm->transmission_mode == TRANSMISSION_MODE_2K) {
+		if (ofdm->guard_interval == GUARD_INTERVAL_1_8) {
+			wr(DIB3000MB_REG_SYNC_IMPROVEMENT,DIB3000MB_SYNC_IMPROVE_2K_1_8);
+		} else {
+			wr(DIB3000MB_REG_SYNC_IMPROVEMENT,DIB3000MB_SYNC_IMPROVE_DEFAULT);
+		}
+		
+		wr(DIB3000MB_REG_UNK_121,DIB3000MB_UNK_121_2K);
+	} else {
+		wr(DIB3000MB_REG_UNK_121,DIB3000MB_UNK_121_DEFAULT);
+	}
 
-	dib3000mb_fe_set_parameters(state,&par);
+	wr(DIB3000MB_REG_MOBILE_ALGO,DIB3000MB_MOBILE_ALGO_OFF);
+	wr(DIB3000MB_REG_MOBILE_MODE_QAM,DIB3000MB_MOBILE_MODE_QAM_OFF);
+	wr(DIB3000MB_REG_MOBILE_MODE,DIB3000MB_MOBILE_MODE_OFF);
 		
 	wr_foreach(dib3000mb_reg_agc_bandwidth,dib3000mb_agc_bandwidth_high);
 	
@@ -434,139 +504,34 @@ static int dib3000mb_set_frontend(struct dib3000mb_state *state,
 	msleep(70);
 
 	wr_foreach(dib3000mb_reg_agc_bandwidth,dib3000mb_agc_bandwidth_low);
-
+	
 	/* something has to be auto searched */ 
-	if (par.seq || !par.qam_vit_manual) { 
+	if (ofdm->constellation == QAM_AUTO ||
+		ofdm->hierarchy_information == HIERARCHY_AUTO ||
+		fe_cr == FEC_AUTO || 
+		fep->inversion == INVERSION_AUTO) {
+		
+		dprintk("autosearch enabled.\n");	
+		
 		wr(DIB3000MB_REG_ISI,DIB3000MB_ISI_INHIBIT);
+		
 		wr(DIB3000MB_REG_RESTART,DIB3000MB_RESTART_AUTO_SEARCH);
 		wr(DIB3000MB_REG_RESTART,DIB3000MB_RESTART_OFF);
+		
+		while ((search_state = dib3000mb_fe_read_search_status(state)) < 0);
+		
+		return search_state ? 0 : -EINVAL;
 	} else {
 		wr(DIB3000MB_REG_RESTART,DIB3000MB_RESTART_CTRL);
 		wr(DIB3000MB_REG_RESTART,DIB3000MB_RESTART_OFF);
 	}
 
-	if (ofdm->constellation != QAM_AUTO &&
-		ofdm->transmission_mode != TRANSMISSION_MODE_AUTO &&
-		ofdm->guard_interval != GUARD_INTERVAL_AUTO &&
-		fep->inversion != INVERSION_AUTO) {
-		wr(DIB3000MB_REG_LOCK1_MASK,DIB3000MB_LOCK1_SEARCH_2048);
-	}
-	
-	while (dib3000mb_fe_read_search_status(state) < 0);
-
 	return 0;
 }
 
 
-static int dib3000mb_get_frontend(struct dib3000mb_state *state, 
-		struct dvb_frontend_parameters *fep)
-{
-	struct i2c_client *i2c = state->i2c;
-	struct dvb_ofdm_parameters *ofdm = &fep->u.ofdm;
-	fe_code_rate_t *cr;
-	u16 tps_val;
-	
-	if (!rd(DIB3000MB_REG_TPS_LOCK)) 
-		return -EINVAL;
-
-	switch ((tps_val = rd(DIB3000MB_REG_TPS_QAM))) {
-		case DIB3000MB_QAM_QPSK:
-			ofdm->constellation = QPSK;
-			break;
-		case DIB3000MB_QAM_QAM16:
-			ofdm->constellation = QAM_16;
-			break;
-		case DIB3000MB_QAM_QAM64:
-			ofdm->constellation = QAM_64;
-			break;
-		default:
-			err("Unexpected constellation returned by TPS (%d)",tps_val);
-			break;
- 	}
-
-	if (rd(DIB3000MB_REG_TPS_HRCH)) {
-		tps_val = rd(DIB3000MB_REG_TPS_CODE_RATE_LP);
-		cr = &ofdm->code_rate_LP;
-		ofdm->code_rate_HP = FEC_NONE;
-		
-		switch ((tps_val = rd(DIB3000MB_REG_TPS_VIT_ALPHA))) {
-			case DIB3000MB_VIT_ALPHA_OFF:
-				ofdm->hierarchy_information = HIERARCHY_NONE;
-				break;
-			case DIB3000MB_VIT_ALPHA_1:
-				ofdm->hierarchy_information = HIERARCHY_1;
-				break;
-			case DIB3000MB_VIT_ALPHA_2:
-				ofdm->hierarchy_information = HIERARCHY_2;
-				break;
-			case DIB3000MB_VIT_ALPHA_4:
-				ofdm->hierarchy_information = HIERARCHY_4;
-				break;
-			default:
-				err("Unexpected ALPHA value returned by TPS (%d)",tps_val);
-		}	
-	} else {
-		tps_val = rd(DIB3000MB_REG_TPS_CODE_RATE_HP);
-		cr = &ofdm->code_rate_HP;
-		ofdm->code_rate_LP = FEC_NONE;
-		ofdm->hierarchy_information = HIERARCHY_NONE;
-	}
-	switch (tps_val) {
-		case DIB3000MB_FEC_1_2:
-			*cr = FEC_1_2;
-			break;
-		case DIB3000MB_FEC_2_3:
-			*cr = FEC_2_3;
-			break;
-		case DIB3000MB_FEC_3_4:
-			*cr = FEC_3_4;
-			break;
-		case DIB3000MB_FEC_5_6:
-			*cr = FEC_4_5;
-			break;
-		case DIB3000MB_FEC_7_8:
-			*cr = FEC_7_8;
-			break;
-		default:
-			err("Unexpected FEC returned by TPS (%d)",tps_val);
-			break;
-	}
-	
-	switch ((tps_val = rd(DIB3000MB_REG_TPS_GUARD_TIME))) {
-		case DIB3000MB_GUARD_TIME_1_32:
-			ofdm->guard_interval = GUARD_INTERVAL_1_32;
-			break;
-		case DIB3000MB_GUARD_TIME_1_16:
-			ofdm->guard_interval = GUARD_INTERVAL_1_16;
-			break;
-		case DIB3000MB_GUARD_TIME_1_8:
-			ofdm->guard_interval = GUARD_INTERVAL_1_8;
-			break;
-		case DIB3000MB_GUARD_TIME_1_4:
-			ofdm->guard_interval = GUARD_INTERVAL_1_4;
-			break;
-		default:
-			err("Unexpected Guard Time returned by TPS (%d)",tps_val);
-			break;
-	}
-
-	switch ((tps_val = rd(DIB3000MB_REG_TPS_FFT))) {
-		case DIB3000MB_FFT_2K:
-			ofdm->transmission_mode = TRANSMISSION_MODE_2K;
-			break;
-		case DIB3000MB_FFT_8K:
-			ofdm->transmission_mode = TRANSMISSION_MODE_8K;
-			break;
-		default:
-			err("unexpected transmission mode return by TPS (%d)",tps_val);
-	}
-	return 0;
-}
-
 static int dib3000mb_fe_init(struct dib3000mb_state *state,int mobile_mode)
 {
-	struct i2c_client *i2c = state->i2c;
-
 	wr(DIB3000MB_REG_POWER_CONTROL,DIB3000MB_POWER_UP);
 	
 	wr(DIB3000MB_REG_RESTART, DIB3000MB_RESTART_AGC);
@@ -645,7 +610,6 @@ static int dib3000mb_fe_init(struct dib3000mb_state *state,int mobile_mode)
 
 static int dib3000mb_read_status(struct dib3000mb_state *state,fe_status_t *stat)
 {
-	struct i2c_client *i2c = state->i2c;
 	*stat = 0;
 	*stat |= rd(DIB3000MB_REG_AGC_LOCK) ? FE_HAS_SIGNAL : 0;
 	*stat |= rd(DIB3000MB_REG_CARRIER_LOCK) ? FE_HAS_CARRIER : 0;
@@ -672,7 +636,6 @@ static int dib3000mb_read_status(struct dib3000mb_state *state,fe_status_t *stat
 
 static int dib3000mb_read_ber(struct dib3000mb_state *state,u32 *ber)
 {
-	struct i2c_client *i2c = state->i2c;
 	*ber = 
 		(((rd(DIB3000MB_REG_BER_MSB) << 16) & 0x1f) | rd(DIB3000MB_REG_BER_LSB) ) /
 		 100000000;
@@ -681,14 +644,12 @@ static int dib3000mb_read_ber(struct dib3000mb_state *state,u32 *ber)
 
 static int dib3000mb_signal_strength(struct dib3000mb_state *state, u16 *strength)
 {
-	struct i2c_client *i2c = state->i2c;
 //	*stength = DIB3000MB_REG_SIGNAL_POWER 
 	return 0;
 }
 
 static int dib3000mb_sleep(struct dib3000mb_state *state)
 {
-	struct i2c_client *i2c = state->i2c;
 	wr(DIB3000MB_REG_POWER_CONTROL,DIB3000MB_POWER_DOWN);
 	return 0;
 }
@@ -728,7 +689,7 @@ static int dib3000mb_ioctl (struct dvb_frontend *fe, unsigned int cmd, void *arg
 
 		case FE_SET_FRONTEND:
 			dprintk("FE_SET_FRONTEND\n");
-			ret = dib3000mb_set_frontend(state,(struct dvb_frontend_parameters *) arg);
+			ret = dib3000mb_set_frontend(state,(struct dvb_frontend_parameters *) arg,1);
 			break;
 
 		case FE_GET_FRONTEND:
diff --git a/linux/drivers/media/dvb/frontends/dib3000mb.h b/linux/drivers/media/dvb/frontends/dib3000mb.h
index 5f81b6eb0..c191845ae 100644
--- a/linux/drivers/media/dvb/frontends/dib3000mb.h
+++ b/linux/drivers/media/dvb/frontends/dib3000mb.h
@@ -72,11 +72,11 @@
 #define DIB3000MB_DDS_FREQ_LSB				(  8990)
 
 /* timing frequency (carrier spacing) */
-#define DIB3000MB_TIMING_FREQ_MSB		(     8)
-#define DIB3000N_TIMING_FREQ_LSB		(     9)
+#define DIB3000MB_REG_TIMING_FREQ_MSB	(     8)
+#define DIB3000MB_REG_TIMING_FREQ_LSB	(     9)
 
 static u16 dib3000mb_reg_timing_freq[] = {
-	DIB3000MB_TIMING_FREQ_MSB, DIB3000N_TIMING_FREQ_LSB 
+	DIB3000MB_REG_TIMING_FREQ_MSB, DIB3000MB_REG_TIMING_FREQ_LSB 
 };
 static u16 dib3000mb_timing_freq[][2] = {
 	{ 126 , 48873 }, /* 6 MHz */
@@ -499,7 +499,7 @@ static u16 dib3000mb_filter_coeffs[] = {
 #define DIB3000MB_MULTI_DEMOD_MSB			( 32767)
 #define DIB3000MB_MULTI_DEMOD_LSB			(  4095)
 
-/* bring the device into a known state */
+/* bring the device into a known  */
 #define DIB3000MB_REG_RESET_DEVICE		(  1024)
 #define DIB3000MB_RESET_DEVICE				(0x812c)
 #define DIB3000MB_RESET_DEVICE_RST			(     0)
@@ -522,29 +522,32 @@ static u16 dib3000mb_filter_coeffs[] = {
 #define DIB3000MB_POWER_UP					(     0)
 
 /* electrical output mode */
-#define DIB3000MB_REG_ELECT_OUT_MODE		(  1029)
-#define DIB3000MB_ELECT_OUT_MODE_OFF			(     0)
-#define DIB3000MB_ELECT_OUT_MODE_ON				(     1)
+#define DIB3000MB_REG_ELECT_OUT_MODE	(  1029)
+#define DIB3000MB_ELECT_OUT_MODE_OFF		(     0)
+#define DIB3000MB_ELECT_OUT_MODE_ON			(     1)
 
 /* set the tuner i2c address */
-#define DIB3000MB_REG_TUNER					(  1089)
-#define DIB3000MB_TUNER_ADDR_DEFAULT			(   194)
-#define DIB3000MB_ACTIVATE_TUNER_XFER(a)		(0xffff & (a << 7))
-#define DIB3000MB_DEACTIVATE_TUNER_XFER(a)		(0xffff & ((a << 7) + 0x80)) 
+#define DIB3000MB_REG_TUNER				(  1089)
+#define DIB3000MB_TUNER_ADDR_DEFAULT		(   194)
+#define DIB3000MB_ACTIVATE_TUNER_XFER(a)	(0xffff & (a << 7))
+#define DIB3000MB_DEACTIVATE_TUNER_XFER(a)	(0xffff & ((a << 7) + 0x80)) 
 
 /* monitoring registers (read only) */
 
 /* agc loop locked (size: 1) */
 #define DIB3000MB_REG_AGC_LOCK			(   324)
 
+/* agc power (size: 16) */
+#define DIB3000MB_REG_AGC_POWER			(   325)
+
 /* agc1 value (16) */
-#define DIB3000MB_REG_AGC1_VALUE			(   326)
+#define DIB3000MB_REG_AGC1_VALUE		(   326)
 
 /* agc2 value (16) */
-#define DIB3000MB_REG_AGC2_VALUE			(   327)
+#define DIB3000MB_REG_AGC2_VALUE		(   327)
 
 /* total RF power (16), can be used for signal strength */
-#define DIB3000MB_REG_AGC_GLOBAL			(   328)
+#define DIB3000MB_REG_RF_POWER			(   328)
 
 /* dds_frequency with offset (24) */
 #define DIB3000MB_REG_DDS_VALUE_MSB		(   339)
@@ -555,7 +558,7 @@ static u16 dib3000mb_filter_coeffs[] = {
 #define DIB3000MB_REG_TIMING_OFFSET_LSB	(   342)
 
 /* fft start position (13) */
-#define DIB3000MB_REG_FFT_WINDOW_POS		(   353)
+#define DIB3000MB_REG_FFT_WINDOW_POS	(   353)
 
 /* carriers locked (1) */
 #define DIB3000MB_REG_CARRIER_LOCK		(   355)
@@ -564,6 +567,9 @@ static u16 dib3000mb_filter_coeffs[] = {
 #define DIB3000MB_REG_NOISE_POWER_MSB	(   372)
 #define DIB3000MB_REG_NOISE_POWER_LSB	(   373)
 
+#define DIB3000MB_REG_MOBILE_NOISE_MSB	(   374)
+#define DIB3000MB_REG_MOBILE_NOISE_LSB	(   375)
+
 /* 
  * signal power (16), this and the above can be 
  * used to calculate the signal/noise - ratio
@@ -607,6 +613,13 @@ static u16 dib3000mb_filter_coeffs[] = {
 /* cell id from TPS (16) */
 #define DIB3000MB_REG_TPS_CELL_ID		(   406)
 
+/* TPS (68) */
+#define DIB3000MB_REG_TPS_1				(   408)
+#define DIB3000MB_REG_TPS_2				(   409)
+#define DIB3000MB_REG_TPS_3				(   410)
+#define DIB3000MB_REG_TPS_4				(   411)
+#define DIB3000MB_REG_TPS_5				(   412)
+
 /* bit error rate (before RS correction) (21) */
 #define DIB3000MB_REG_BER_MSB			(   414)
 #define DIB3000MB_REG_BER_LSB			(   415)