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authorAndy Walls <awalls@radix.net>2009-01-01 09:09:24 -0500
committerAndy Walls <awalls@radix.net>2009-01-01 09:09:24 -0500
commitdb548dc0e0db38f2af004d4007368c659742b64f (patch)
treed69b6177436d6c19ce2fa1252bac79227cc84c8b /linux/drivers/media/video/cx18/cx18-av-firmware.c
parent70e0ec035b78cab8338a5b20518bfc1d1307b7ad (diff)
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cx18: Fix a PLL divisor update for the I2S master clock
From: Andy Walls <awalls@radix.net> A redundant PLL divisior update for the I2S master clock after AV core firmware load was missed in earlier PLL parameter changes. This one really doesn't matter because it's redundant and gets overwritten, but the driver should be self consistent in the values used. Priority: normal Signed-off-by: Andy Walls <awalls@radix.net>
Diffstat (limited to 'linux/drivers/media/video/cx18/cx18-av-firmware.c')
-rw-r--r--linux/drivers/media/video/cx18/cx18-av-firmware.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/linux/drivers/media/video/cx18/cx18-av-firmware.c b/linux/drivers/media/video/cx18/cx18-av-firmware.c
index c64fd0a05..d1fa0289b 100644
--- a/linux/drivers/media/video/cx18/cx18-av-firmware.c
+++ b/linux/drivers/media/video/cx18/cx18-av-firmware.c
@@ -115,9 +115,9 @@ int cx18_av_loadfw(struct cx18 *cx)
are generated) */
cx18_av_write4(cx, CXADEC_I2S_OUT_CTL, 0x000001A0);
- /* set alt I2s master clock to /16 and enable alt divider i2s
+ /* set alt I2s master clock to /0x16 and enable alt divider i2s
passthrough */
- cx18_av_write4(cx, CXADEC_PIN_CFG3, 0x5000B687);
+ cx18_av_write4(cx, CXADEC_PIN_CFG3, 0x5600B687);
cx18_av_write4_expect(cx, CXADEC_STD_DET_CTL, 0x000000F6, 0x000000F6,
0x3F00FFFF);