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| author | Andy Walls <awalls@radix.net> | 2008-11-17 20:48:46 -0500 |
|---|---|---|
| committer | Andy Walls <awalls@radix.net> | 2008-11-17 20:48:46 -0500 |
| commit | 79ee5103332e36280ca8ff8426dce1d8cb37df1c (patch) | |
| tree | ac88913cf10838abfbd51b84fb35118139f9fbad /linux/drivers/media/video/cx18/cx18-io.c | |
| parent | 41442c233ecb6016a8d6c73ff23002138488e42b (diff) | |
| download | mediapointer-dvb-s2-79ee5103332e36280ca8ff8426dce1d8cb37df1c.tar.gz mediapointer-dvb-s2-79ee5103332e36280ca8ff8426dce1d8cb37df1c.tar.bz2 | |
cx18: Remove unnecessary MMIO accesses in time critical irq handling path
From: Andy Walls <awalls@radix.net>
Remove unnecessary MMIO accesses in time critical irq handling path. Also
ensured that the mailbox ack field is read in last, so we know for sure if we
have a stale mailbox or not on receipt.
Priority: normal
Signed-off-by: Andy Walls <awalls@radix.net>
Diffstat (limited to 'linux/drivers/media/video/cx18/cx18-io.c')
| -rw-r--r-- | linux/drivers/media/video/cx18/cx18-io.c | 20 |
1 files changed, 8 insertions, 12 deletions
diff --git a/linux/drivers/media/video/cx18/cx18-io.c b/linux/drivers/media/video/cx18/cx18-io.c index a2b5e807f..c6f1d0d7f 100644 --- a/linux/drivers/media/video/cx18/cx18-io.c +++ b/linux/drivers/media/video/cx18/cx18-io.c @@ -71,32 +71,28 @@ void cx18_memset_io(struct cx18 *cx, void __iomem *addr, int val, size_t count) void cx18_sw1_irq_enable(struct cx18 *cx, u32 val) { - u32 r; cx18_write_reg_expect(cx, val, SW1_INT_STATUS, ~val, val); - r = cx18_read_reg(cx, SW1_INT_ENABLE_PCI); - cx18_write_reg(cx, r | val, SW1_INT_ENABLE_PCI); + cx->sw1_irq_mask = cx18_read_reg(cx, SW1_INT_ENABLE_PCI) | val; + cx18_write_reg(cx, cx->sw1_irq_mask, SW1_INT_ENABLE_PCI); } void cx18_sw1_irq_disable(struct cx18 *cx, u32 val) { - u32 r; - r = cx18_read_reg(cx, SW1_INT_ENABLE_PCI); - cx18_write_reg(cx, r & ~val, SW1_INT_ENABLE_PCI); + cx->sw1_irq_mask = cx18_read_reg(cx, SW1_INT_ENABLE_PCI) & ~val; + cx18_write_reg(cx, cx->sw1_irq_mask, SW1_INT_ENABLE_PCI); } void cx18_sw2_irq_enable(struct cx18 *cx, u32 val) { - u32 r; cx18_write_reg_expect(cx, val, SW2_INT_STATUS, ~val, val); - r = cx18_read_reg(cx, SW2_INT_ENABLE_PCI); - cx18_write_reg(cx, r | val, SW2_INT_ENABLE_PCI); + cx->sw2_irq_mask = cx18_read_reg(cx, SW2_INT_ENABLE_PCI) | val; + cx18_write_reg(cx, cx->sw2_irq_mask, SW2_INT_ENABLE_PCI); } void cx18_sw2_irq_disable(struct cx18 *cx, u32 val) { - u32 r; - r = cx18_read_reg(cx, SW2_INT_ENABLE_PCI); - cx18_write_reg(cx, r & ~val, SW2_INT_ENABLE_PCI); + cx->sw2_irq_mask = cx18_read_reg(cx, SW2_INT_ENABLE_PCI) & ~val; + cx18_write_reg(cx, cx->sw2_irq_mask, SW2_INT_ENABLE_PCI); } void cx18_sw2_irq_disable_cpu(struct cx18 *cx, u32 val) |