diff options
| author | Gerd Knorr <devnull@localhost> | 2005-01-04 16:31:20 +0000 |
|---|---|---|
| committer | Gerd Knorr <devnull@localhost> | 2005-01-04 16:31:20 +0000 |
| commit | d11bf9fb3ca8e03aa181518279de67fcd51ee374 (patch) | |
| tree | 4ad254e15a99aa03cfb729c21331c9da4004a45d /linux/drivers/media/video/saa7134 | |
| parent | 5bac93165c075e9bde153e2abd14d5c5a550d90a (diff) | |
| download | mediapointer-dvb-s2-d11bf9fb3ca8e03aa181518279de67fcd51ee374.tar.gz mediapointer-dvb-s2-d11bf9fb3ca8e03aa181518279de67fcd51ee374.tar.bz2 | |
- more pinnacle 300i stuff (not working yet).
Diffstat (limited to 'linux/drivers/media/video/saa7134')
| -rw-r--r-- | linux/drivers/media/video/saa7134/saa7134-dvb.c | 63 |
1 files changed, 46 insertions, 17 deletions
diff --git a/linux/drivers/media/video/saa7134/saa7134-dvb.c b/linux/drivers/media/video/saa7134/saa7134-dvb.c index b6cb37003..325631fd0 100644 --- a/linux/drivers/media/video/saa7134/saa7134-dvb.c +++ b/linux/drivers/media/video/saa7134/saa7134-dvb.c @@ -1,5 +1,5 @@ /* - * $Id: saa7134-dvb.c,v 1.6 2004/12/10 12:33:39 kraxel Exp $ + * $Id: saa7134-dvb.c,v 1.7 2005/01/04 16:31:20 kraxel Exp $ * * (c) 2004 Gerd Knorr <kraxel@bytesex.org> [SuSE Labs] * @@ -39,15 +39,16 @@ MODULE_LICENSE("GPL"); /* ------------------------------------------------------------------ */ -static int mt352_init(struct dvb_frontend* fe) +static int mt352_pinnacle_init(struct dvb_frontend* fe) { - static u8 clock_config [] = { CLOCK_CTL, 0x38, 0x39 }; // check - static u8 reset [] = { RESET, 0x80 }; // ok - static u8 adc_ctl_1_cfg [] = { ADC_CTL_1, 0x40 }; // ok + static u8 clock_config [] = { CLOCK_CTL, 0x3d, 0x39 }; + static u8 reset [] = { RESET, 0x80 }; + static u8 adc_ctl_1_cfg [] = { ADC_CTL_1, 0x40 }; + static u8 agc_cfg [] = { AGC_TARGET, 0x20, 0x20 }; + static u8 capt_range_cfg[] = { CAPT_RANGE, 0x31 }; #if 0 - static u8 agc_cfg [] = { AGC_TARGET, 0x28, 0x20 }; // check - static u8 gpp_ctl_cfg [] = { GPP_CTL, 0x33 }; // ??? - static u8 capt_range_cfg[] = { CAPT_RANGE, 0x32 }; // ??? + // general purpose port pins + static u8 gpp_ctl_cfg [] = { GPP_CTL, 0x33 }; #endif struct saa7134_dev *dev= fe->dvb->priv; @@ -57,31 +58,59 @@ static int mt352_init(struct dvb_frontend* fe) udelay(200); mt352_write(fe, reset, sizeof(reset)); mt352_write(fe, adc_ctl_1_cfg, sizeof(adc_ctl_1_cfg)); + mt352_write(fe, agc_cfg, sizeof(agc_cfg)); + mt352_write(fe, capt_range_cfg, sizeof(capt_range_cfg)); #if 0 - mt352_write(fe, agc_cfg, sizeof(agc_cfg)); mt352_write(fe, gpp_ctl_cfg, sizeof(gpp_ctl_cfg)); - mt352_write(fe, capt_range_cfg, sizeof(capt_range_cfg)); #endif return 0; } -static int mt352_pll_set(struct dvb_frontend* fe, - struct dvb_frontend_parameters* params, - u8* pllbuf) +static int mt352_pinnacle_pll_set(struct dvb_frontend* fe, + struct dvb_frontend_parameters* params, + u8* pllbuf) { + static u8 buf[][3] = { + /* set bandwidth (ADC frequency is 20.333 MHz) */ + [ BANDWIDTH_6_MHZ ] = { TRL_NOMINAL_RATE_1, 0x56, 0x55 }, + [ BANDWIDTH_7_MHZ ] = { TRL_NOMINAL_RATE_1, 0x64, 0xB8 }, + [ BANDWIDTH_8_MHZ ] = { TRL_NOMINAL_RATE_1, 0x73, 0x1C }, + }; struct saa7134_dev *dev= fe->dvb->priv; + struct v4l2_frequency f; + int bw = params->u.ofdm.bandwidth; - printk("%s: %s called\n",dev->name,__FUNCTION__); - /* FIXME */ + printk("%s: %s called (freq=%d,bw=%d)\n",dev->name,__FUNCTION__, + params->frequency,bw); + + /* set frequency */ + f.tuner = 0; + f.type = V4L2_TUNER_ANALOG_TV; /* FIXME */ + f.frequency = params->frequency / 1000 * 16 / 1000; + saa7134_i2c_call_clients(dev,VIDIOC_S_FREQUENCY,&f); memset(pllbuf,0,5); + + if (bw < ARRAY_SIZE(buf) && NULL != buf[bw]) { +#if 1 + /* dirty hack time -- fixup mt352 buffer which has + * adc freq 20.48 MHz values hardcoded */ + pllbuf[-4] = buf[bw][1]; + pllbuf[-3] = buf[bw][2]; + pllbuf[-2] = 0x31; /* if 36.1667 + adc 20.333 */ + pllbuf[-1] = 0xD9; +#else + mt352_write(fe, buf[bw], 3); +#endif + } + return 0; } static struct mt352_config pinnacle_300i = { .demod_address = 0x3c >> 1, - .demod_init = mt352_init, - .pll_set = mt352_pll_set, + .demod_init = mt352_pinnacle_init, + .pll_set = mt352_pinnacle_pll_set, }; /* ------------------------------------------------------------------ */ |