- cx88: started going over the blackbird code.

3 files changed, 81 insertions, 90 deletions

diff --git a/linux/drivers/media/video/cx88/cx88-blackbird.c b/linux/drivers/media/video/cx88/cx88-blackbird.c
index 0725ea76c..47772322b 100644
--- a/linux/drivers/media/video/cx88/cx88-blackbird.c
+++ b/linux/drivers/media/video/cx88/cx88-blackbird.c
@@ -1,5 +1,5 @@
 /*
- * $Id: cx88-blackbird.c,v 1.2 2004/07/30 13:43:39 kraxel Exp $
+ * $Id: cx88-blackbird.c,v 1.3 2004/07/30 15:26:01 kraxel Exp $
  *
  *  Support for a cx23416 mpeg encoder via cx2388x host port.
  *  "blackbird" reference design.
@@ -28,6 +28,8 @@
 #include <linux/init.h>
 #include <linux/device.h>
 #include <linux/fs.h>
+#include <linux/delay.h>
+#include <linux/firmware.h>
 
 #include "cx88.h"
 
@@ -84,13 +86,10 @@ MODULE_LICENSE("GPL");
 #define IVTV_REG_VPU (0x9058 /*| IVTV_REG_OFFSET*/)
 #define IVTV_REG_APU (0xA064 /*| IVTV_REG_OFFSET*/)
 
-#if 0
+/* ------------------------------------------------------------------ */
 
-/* initialize the dma for the mpegport, called from cx88-video.c:cx8800_initdev */
-int cx8800_mpegport_init_dma(struct cx8800_dev *dev)
+static void host_setup(struct cx88_core *core)
 {
-	dprintk(1,"cx88_mpegport_init_dma\n");
-
 	/* toggle reset of the host */	
 	cx_write(MO_GPHST_SOFT_RST, 1);
 	udelay(100);
@@ -104,59 +103,10 @@ int cx8800_mpegport_init_dma(struct cx8800_dev *dev)
 	cx_write(MO_GPHST_HDSHK, 0);
 	cx_write(MO_GPHST_MUX16, 0x44448888U);
 	cx_write(MO_GPHST_MODE, 0);
-	
-	cx_write(MO_PINMUX_IO, 0x88); /* enable MPEG parallel IO */
-	
-	cx_write(MO_DEV_CNTRL2, 0x20); /* enable the RISC controller */
-	cx_set(MO_PCI_INTMSK, 0x4); /* enable ts_int */
-	
-	cx_write(TS_F2_CMD_STAT_MM, 0x2900106); /* F2_CMD_STAT_MM defaults + master + memory space */
-	cx_write(TS_GEN_CNTRL, 0x46); /* punctured clock TS & posedge driven & software reset */	
-	cx_write(MO_TS_LNGTH, MD_TS_LNGHT_VAL);
-	
-	udelay(100);
-	INIT_LIST_HEAD(&dev->mpegq.active);
-	INIT_LIST_HEAD(&dev->mpegq.queued);
-	dev->mpegq.timeout.function = cx8800_mpegport_timeout;
-	dev->mpegq.timeout.data     = (unsigned long)dev;
-	init_timer(&dev->mpegq.timeout);
-	cx88_risc_stopper(dev->pci,&dev->mpegq.stopper,
-			  MO_TS_DMACNTRL,0x11,0x00);
-	udelay(100);
-	
-	cx_write(MO_TS_INTMSK, 0);
-	cx_set(MO_TS_INTSTAT, 0);
-	cx_write(MO_TS_INTMSK, 0x1f1101); /* all except the irq2 bit */
-	
-	cx_write(MO_TS_GPCNTRL, GP_COUNT_CONTROL_RESET); /* reset gp counter to 0 */
-	cx_write(TS_HW_SOP_CNTRL, 0x408); /* mpeg start byte */
-	//cx_write(TS_HW_SOP_CNTRL, 0x2F0BC0); /* mpeg start byte ts: 0x2F0BC0 ? */
-	cx_write(TS_VALERR_CNTRL, 0x2000);
-	
-	cx_write(TS_GEN_CNTRL, 0x06); /* punctured clock TS & posedge driven */
-	udelay(100);
-	
-	return 0;
 }
 
 /* ------------------------------------------------------------------ */
 
-int wait_ready_gpio0_bit1_high(struct cx8800_dev *dev)
-{
-	int timeout = 1000;
-	do { timeout--; udelay(1); } while (!(cx_readb(MO_GP0_IO) & 2) && (timeout >= 0));
-	if (timeout < 0) return -1;
-	return 0;
-}
-
-int wait_ready_gpio0_bit1_low(struct cx8800_dev *dev)
-{
-	int timeout = 1000;
-	do { timeout--; udelay(1); } while ((cx_readb(MO_GP0_IO) & 2) && (timeout >= 0));
-	if (timeout < 0) return -1;
-	return 0;
-}
-
 #define P1_MDATA0 0x390000
 #define P1_MDATA1 0x390001
 #define P1_MDATA2 0x390002
@@ -172,13 +122,25 @@ int wait_ready_gpio0_bit1_low(struct cx8800_dev *dev)
 #define P1_RADDR1 0x39000D
 #define P1_RRDWR  0x39000E
 
-/* Warning: address is dword address (4 bytes) */
-static int memory_write(struct cx8800_dev *dev, int address, int value)
+static int wait_ready_gpio0_bit1(struct cx88_core *core, u32 state)
 {
-	int retval;
+	unsigned long timeout = jiffies + msecs_to_jiffies(1);
+	u32 gpio0,need;
+
+	need = state ? 2 : 0;
+	for (;;) {
+		gpio0 = cx_read(MO_GP0_IO) & 2;
+		if (need == gpio0)
+			return 0;
+		if (time_after(jiffies,timeout))
+			return -1;
+		udelay(1);
+	}
+}
 
-	//retval  = wait_ready_gpio0_bit1_low(dev);
-	
+static int memory_write(struct cx88_core *core, u32 address, u32 value)
+{
+	/* Warning: address is dword address (4 bytes) */
 	cx_writeb(P1_MDATA0, (unsigned int)value);
 	cx_writeb(P1_MDATA1, (unsigned int)(value >> 8));
 	cx_writeb(P1_MDATA2, (unsigned int)(value >> 16));
@@ -186,23 +148,25 @@ static int memory_write(struct cx8800_dev *dev, int address, int value)
 	cx_writeb(P1_MADDR2, (unsigned int)(address >> 16) | 0x40);
 	cx_writeb(P1_MADDR1, (unsigned int)(address >> 8));
 	cx_writeb(P1_MADDR0, (unsigned int)address);
+	cx_read(P1_MDATA0);
+	cx_read(P1_MADDR0);
 
-	retval  = wait_ready_gpio0_bit1_high(dev);
-	return retval;
+	return wait_ready_gpio0_bit1(core,1);
 }
 
-/* Warning: address is dword address (4 bytes) */
-static int memory_read(struct cx8800_dev *dev, int address, int *value)
+static int memory_read(struct cx88_core *core, u32 address, u32 *value)
 {
-	int retval;
+        int retval;
+	u32 val;
 
+	/* Warning: address is dword address (4 bytes) */
 	cx_writeb(P1_MADDR2, (unsigned int)(address >> 16) & ~0xC0);
 	cx_writeb(P1_MADDR1, (unsigned int)(address >> 8));
 	cx_writeb(P1_MADDR0, (unsigned int)address);
+	cx_read(P1_MADDR0);
 	
-	retval  = wait_ready_gpio0_bit1_high(dev);
+	retval = wait_ready_gpio0_bit1(core,1);
 	
-	int val;
 	cx_writeb(P1_MDATA3, 0);
 	val     = (unsigned char)cx_read(P1_MDATA3) << 24;
 	cx_writeb(P1_MDATA2, 0);
@@ -211,15 +175,13 @@ static int memory_read(struct cx8800_dev *dev, int address, int *value)
 	val    |= (unsigned char)cx_read(P1_MDATA1) << 8;
 	cx_writeb(P1_MDATA0, 0);
 	val    |= (unsigned char)cx_read(P1_MDATA0);
+
 	*value  = val;
-	
 	return retval;
 }
 
-
-static int register_write(struct cx8800_dev *dev, int address, int value)
+static int register_write(struct cx88_core *core, u32 address, u32 value)
 {
-	int retval;
 	cx_writeb(P1_RDATA0, (unsigned int)value);
 	cx_writeb(P1_RDATA1, (unsigned int)(value >> 8));
 	cx_writeb(P1_RDATA2, (unsigned int)(value >> 16));
@@ -227,51 +189,60 @@ static int register_write(struct cx8800_dev *dev, int address, int value)
 	cx_writeb(P1_RADDR0, (unsigned int)address);
 	cx_writeb(P1_RADDR1, (unsigned int)(address >> 8));
 	cx_writeb(P1_RRDWR, 1);
+	cx_read(P1_RDATA0);
+	cx_read(P1_RADDR0);
 
-	retval  = wait_ready_gpio0_bit1_high(dev);
+	return wait_ready_gpio0_bit1(core,1);
+#if 0
 	udelay(1000); /* without this, things don't go right (subsequent memory_write()'s don't get through */
 	/* ? would this be safe here? set_current_state(TASK_INTERRUPTIBLE); schedule_timeout(1); */
-	return retval;
+#endif
 }
 
 
-static int register_read(struct cx8800_dev *dev, int address, int *value)
+static int register_read(struct cx88_core *core, u32 address, u32 *value)
 {
 	int retval;
+	u32 val;
+
 	cx_writeb(P1_RADDR0, (unsigned int)address);
 	cx_writeb(P1_RADDR1, (unsigned int)(address >> 8));
 	cx_writeb(P1_RRDWR, 0);
+	cx_read(P1_RADDR0);
 
-	retval  = wait_ready_gpio0_bit1_high(dev);
-	
-	int val;
+	retval  = wait_ready_gpio0_bit1(core,1);
 	val     = (unsigned char)cx_read(P1_RDATA0);
 	val    |= (unsigned char)cx_read(P1_RDATA1) << 8;
 	val    |= (unsigned char)cx_read(P1_RDATA2) << 16;
 	val    |= (unsigned char)cx_read(P1_RDATA3) << 24;
-	*value  = val;
 
+	*value  = val;
 	return retval;
 }
 
+/* ------------------------------------------------------------------ */
+
+#if 0
+
 /* We don't need to call the API often, so using just one mailbox will probably suffice */
-int mpegport_api_cmd(struct cx8800_dev *dev, u32 command, u32 inputcnt, u32 outputcnt, ...)
+int blackbird_cmd(struct cx8802_dev *dev, u32 command, u32 inputcnt, u32 outputcnt, ...)
 {
 	va_list args;
 	va_start(args, outputcnt);
 	int i;
 	u32 value;
+	u32 flag;
 	
-	dprintk(1,"API Command 0x%X\n", command);
+	dprintk(1,"%s: 0x%X\n", __FUNCTION__, command);
 
-	/* this may not be 100% safe if we can't read any memory location without side effects */
+	/* this may not be 100% safe if we can't read any memory location
+	   without side effects */
 	memory_read(dev, dev->mpegport_mailbox - 4, &value);
 	if (value != 0x12345678) {
 		dprintk(0, "Firmware and/or mailbox pointer not initialized or corrupted\n");
 		return -1;
 	}
 	
-	u32 flag;
 	memory_read(dev, dev->mpegport_mailbox, &flag);
 	if (flag) {
 		dprintk(0, "ERROR: Mailbox appears to be in use (%x)\n", flag);
diff --git a/linux/drivers/media/video/cx88/cx88-mpeg.c b/linux/drivers/media/video/cx88/cx88-mpeg.c
index d05e925c4..9d92fce36 100644
--- a/linux/drivers/media/video/cx88/cx88-mpeg.c
+++ b/linux/drivers/media/video/cx88/cx88-mpeg.c
@@ -1,5 +1,5 @@
 /*
- * $Id: cx88-mpeg.c,v 1.3 2004/07/30 13:43:39 kraxel Exp $
+ * $Id: cx88-mpeg.c,v 1.4 2004/07/30 15:26:01 kraxel Exp $
  *
  *  Support for the mpeg transport stream transfers
  *  PCI function #2 of the cx2388x.
@@ -68,7 +68,7 @@ int cx8802_start_dma(struct cx8802_dev    *dev,
 	cx88_sram_channel_setup(core, &cx88_sram_channels[SRAM_CH28],
 				PACKET_SIZE, buf->risc.dma);
 
-#if 0 /* from DVB -- for transport streams only? */
+#if 0 /* config stuff from DVB */
 	/* Setup TS portion of chip */
 	cx_write(TS_GEN_CNTRL, 0x0c);
 	
@@ -76,6 +76,24 @@ int cx8802_start_dma(struct cx8802_dev    *dev,
 	cx_write(MO_TS_LNGTH, buf->bpl);
 #endif
 
+#if 0 /* config stuff for from blackbird ... */
+	cx_write(MO_PINMUX_IO, 0x88); /* enable MPEG parallel IO */
+	
+
+	cx_write(TS_F2_CMD_STAT_MM, 0x2900106); /* F2_CMD_STAT_MM defaults + master + memory space */
+	cx_write(TS_GEN_CNTRL, 0x46); /* punctured clock TS & posedge driven & software reset */	
+	cx_write(MO_TS_LNGTH, MD_TS_LNGHT_VAL);
+	
+	udelay(100);
+
+	cx_write(TS_HW_SOP_CNTRL, 0x408); /* mpeg start byte */
+	//cx_write(TS_HW_SOP_CNTRL, 0x2F0BC0); /* mpeg start byte ts: 0x2F0BC0 ? */
+	cx_write(TS_VALERR_CNTRL, 0x2000);
+	
+	cx_write(TS_GEN_CNTRL, 0x06); /* punctured clock TS & posedge driven */
+	udelay(100);
+#endif
+
 	/* reset counter */
 	cx_write(MO_TS_GPCNTRL, GP_COUNT_CONTROL_RESET);
 	q->count = 1;
diff --git a/linux/drivers/media/video/cx88/cx88-reg.h b/linux/drivers/media/video/cx88/cx88-reg.h
index a80b7519e..b1831ce3d 100644
--- a/linux/drivers/media/video/cx88/cx88-reg.h
+++ b/linux/drivers/media/video/cx88/cx88-reg.h
@@ -502,12 +502,6 @@
 
 #define MO_GPHSTD_DMA       0x350000 // {64}RWp Host downstream
 #define MO_GPHSTU_DMA       0x350008 // {64}RWp Host upstream
-#define MO_GPHSTD_GPCNT     0x35C020 // Host down general purpose counter
-#define MO_GPHSTU_GPCNT     0x35C024 // Host up general purpose counter
-#define MO_GPHSTD_GPCNTRL   0x38C030 // Host down general purpose control
-#define MO_GPHSTU_GPCNTRL   0x38C034 // Host up general purpose control
-#define MO_GPHST_DMACNTRL   0x38C040 // Host DMA control
-#define MO_GPHST_XFR_STAT   0x38C044 // Host transfer status
 #define MO_GPHSTU_CNTRL     0x380048 // Host upstream control #1
 #define MO_GPHSTD_CNTRL     0x38004C // Host downstream control #2
 #define MO_GPHSTD_LNGTH     0x380050 // Host downstream line length
@@ -518,6 +512,14 @@
 #define MO_GPHST_MUX16      0x380064 // Host muxed 16-bit transfer parameters
 #define MO_GPHST_MODE       0x380068 // Host mode select
 
+#define MO_GPHSTD_GPCNT     0x35C020 // Host down general purpose counter
+#define MO_GPHSTU_GPCNT     0x35C024 // Host up general purpose counter
+#define MO_GPHSTD_GPCNTRL   0x38C030 // Host down general purpose control
+#define MO_GPHSTU_GPCNTRL   0x38C034 // Host up general purpose control
+#define MO_GPHST_DMACNTRL   0x38C040 // Host DMA control
+#define MO_GPHST_XFR_STAT   0x38C044 // Host transfer status
+#define MO_GPHST_SOFT_RST   0x38C06C // Host software reset
+
 
 /* ---------------------------------------------------------------------- */
 /* RISC instructions                                                      */