Renames registers to be easier to work with they

From: Mauro Carvalho Chehab <mchehab@infradead.org>

On SAA711x datasheets, registers are referenced by its numbers.
So, it is better to keep the number at register name. This way, it is
easier to seek that register at datasheet. Also, the alias helps to identify
what the meaning for each register.

Signed-off-by: Mauro Carvalho Chehab <mchehab@infradead.org>

2 files changed, 655 insertions, 651 deletions

diff --git a/linux/drivers/media/video/saa7115.c b/linux/drivers/media/video/saa7115.c
index 4b5e09adc..2db998717 100644
--- a/linux/drivers/media/video/saa7115.c
+++ b/linux/drivers/media/video/saa7115.c
@@ -123,41 +123,41 @@ static inline int saa7115_read(struct i2c_client *client, u8 reg)
 
 static const unsigned char saa7115_init_auto_input[] = {
 		/* Front-End Part */
-	INC_DELAY, 0x48,		/* white peak control disabled */
-	ANALOG_INPUT_CNTL_2, 0x20,	/* was 0x30. 0x20: long vertical blanking */
-	ANALOG_INPUT_CNTL_3, 0x90,	/* analog gain set to 0 */
-	ANALOG_INPUT_CNTL_4, 0x90,	/* analog gain set to 0 */
+	R_01_INC_DELAY, 0x48,			/* white peak control disabled */
+	R_03_INPUT_CNTL_2, 0x20,		/* was 0x30. 0x20: long vertical blanking */
+	R_04_INPUT_CNTL_3, 0x90,		/* analog gain set to 0 */
+	R_05_INPUT_CNTL_4, 0x90,		/* analog gain set to 0 */
 		/* Decoder Part */
-	HORIZ_SYNC_START, 0xeb,		/* horiz sync begin = -21 */
-	HORIZ_SYNC_STOP, 0xe0,		/* horiz sync stop = -17 */
-	LUMA_BRIGHTNESS_CNTL, 0x80,	/* was 0x88. decoder brightness, 0x80 is itu standard */
-	LUMA_CONTRAST_CNTL, 0x44,	/* was 0x48. decoder contrast, 0x44 is itu standard */
-	CHROMA_SATURATION_CNTL, 0x40,	/* was 0x47. decoder saturation, 0x40 is itu standard */
-	CHROMA_HUE_CNTL, 0x00,
-	CHROMA_GAIN_CNTL, 0x00,		/* use automatic gain  */
-	CHROMA_CNTL_2, 0x06,		/* chroma: active adaptive combfilter */
-	MODE_DELAY_CNTL, 0x00,
-	RT_SIGNAL_CNTL, 0x9d,		/* RTS0 output control: VGATE */
-	RT_X_PORT_OUTPUT_CNTL, 0x80,	/* ITU656 standard mode, RTCO output enable RTCE */
-	ANALOG_ADC_COMPAT_CNTL, 0x00,
-	RAW_DATA_GAIN_CNTL, 0x40,	/* gain 0x00 = nominal */
-	RAW_DATA_OFF_CNTL, 0x80,
-	COLOR_KILLER_LEVEL_CNTL, 0x77,	/* recommended value */
-	MISC_TVVCRDET, 0x42,		/* recommended value */
-	ENHANCED_COMB_CTRL1, 0xa9,	/* recommended value */
-	ENHANCED_COMB_CTRL2, 0x01,	/* recommended value */
+	R_06_H_SYNC_START, 0xeb,		/* horiz sync begin = -21 */
+	R_07_H_SYNC_STOP, 0xe0,			/* horiz sync stop = -17 */
+	R_0A_LUMA_BRIGHT_CNTL, 0x80,		/* was 0x88. decoder brightness, 0x80 is itu standard */
+	R_0B_LUMA_CONTRAST_CNTL, 0x44,		/* was 0x48. decoder contrast, 0x44 is itu standard */
+	R_0C_CHROMA_SAT_CNTL, 0x40,		/* was 0x47. decoder saturation, 0x40 is itu standard */
+	R_0D_CHROMA_HUE_CNTL, 0x00,
+	R_0F_CHROMA_GAIN_CNTL, 0x00,		/* use automatic gain  */
+	R_10_CHROMA_CNTL_2, 0x06,		/* chroma: active adaptive combfilter */
+	R_11_MODE_DELAY_CNTL, 0x00,
+	R_12_RT_SIGNAL_CNTL, 0x9d,		/* RTS0 output control: VGATE */
+	R_13_RT_X_PORT_OUT_CNTL, 0x80,		/* ITU656 standard mode, RTCO output enable RTCE */
+	R_14_ANAL_ADC_COMPAT_CNTL, 0x00,
+	R_18_RAW_DATA_GAIN_CNTL, 0x40,		/* gain 0x00 = nominal */
+	R_19_RAW_DATA_OFF_CNTL, 0x80,
+	R_1A_COLOR_KILL_LVL_CNTL, 0x77,		/* recommended value */
+	R_1B_MISC_TVVCRDET, 0x42,		/* recommended value */
+	R_1C_ENHAN_COMB_CTRL1, 0xa9,		/* recommended value */
+	R_1D_ENHAN_COMB_CTRL2, 0x01,		/* recommended value */
 
 		/* Power Device Control */
-	POWER_SAVE_ADC_PORT_CNTL, 0xd0,	/* reset device */
-	POWER_SAVE_ADC_PORT_CNTL, 0xf0,	/* set device programmed, all in operational mode */
+	R_88_POWER_SAVE_ADC_PORT_CNTL, 0xd0,	/* reset device */
+	R_88_POWER_SAVE_ADC_PORT_CNTL, 0xf0,	/* set device programmed, all in operational mode */
 	0x00, 0x00
 };
 
 static const unsigned char saa7115_cfg_reset_scaler[] = {
-	I_PORT_I_O_ENABLE_OUTPUT_CLOCK_AND_GATED, 0x00,	/* disable I-port output */
-	POWER_SAVE_ADC_PORT_CNTL, 0xd0,			/* reset scaler */
-	POWER_SAVE_ADC_PORT_CNTL, 0xf0,			/* activate scaler */
-	I_PORT_I_O_ENABLE_OUTPUT_CLOCK_AND_GATED, 0x01,	/* enable I-port output */
+	R_87_I_PORT_I_O_ENA_OUT_CLK_AND_GATED, 0x00,	/* disable I-port output */
+	R_88_POWER_SAVE_ADC_PORT_CNTL, 0xd0,		/* reset scaler */
+	R_88_POWER_SAVE_ADC_PORT_CNTL, 0xf0,		/* activate scaler */
+	R_87_I_PORT_I_O_ENA_OUT_CLK_AND_GATED, 0x01,	/* enable I-port output */
 	0x00, 0x00
 };
 
@@ -165,234 +165,234 @@ static const unsigned char saa7115_cfg_reset_scaler[] = {
 
 static const unsigned char saa7115_cfg_60hz_fullres_x[] = {
 	/* hsize = 0x2d0 = 720 */
-	B_HORIZ_OUTPUT_WINDOW_LENGTH, 0xd0,
-	B_HORIZ_OUTPUT_WINDOW_LENGTH_MSB, 0x02,
+	R_CC_B_HORIZ_OUTPUT_WINDOW_LENGTH, 0xd0,
+	R_CD_B_HORIZ_OUTPUT_WINDOW_LENGTH_MSB, 0x02,
 
 	/* Why not in 60hz-Land, too? */
-	B_HORIZ_PRESCALING, 0x01,		/* downscale = 1 */
+	R_D0_B_HORIZ_PRESCALING, 0x01,		/* downscale = 1 */
 	/* hor lum scaling 0x0400 = 1 */
-	B_HORIZ_LUMA_SCALING_INC, 0x00,
-	B_HORIZ_LUMA_SCALING_INC_MSB, 0x04,
+	R_D8_B_HORIZ_LUMA_SCALING_INC, 0x00,
+	R_D9_B_HORIZ_LUMA_SCALING_INC_MSB, 0x04,
 
 	/* must be hor lum scaling / 2 */
-	B_HORIZ_CHROMA_SCALING, 0x00,
-	B_HORIZ_CHROMA_SCALING_MSB, 0x02,
+	R_DC_B_HORIZ_CHROMA_SCALING, 0x00,
+	R_DD_B_HORIZ_CHROMA_SCALING_MSB, 0x02,
 
 	0x00, 0x00
 };
 
 static const unsigned char saa7115_cfg_60hz_fullres_y[] = {
 	/* output window size = 248 (but 60hz is 240?) */
-	B_VERT_OUTPUT_WINDOW_LENGTH, 0xf8,
-	B_VERT_OUTPUT_WINDOW_LENGTH_MSB, 0x00,
+	R_CE_B_VERT_OUTPUT_WINDOW_LENGTH, 0xf8,
+	R_CF_B_VERT_OUTPUT_WINDOW_LENGTH_MSB, 0x00,
 
 	/* Why not in 60hz-Land, too? */
-	B_LUMA_CONTRAST_CNTL, 0x40,		/* Lum contrast, nominal value = 0x40 */
-	B_CHROMA_SATURATION_CNTL, 0x40,		/* Chroma satur. nominal value = 0x80 */
+	R_D5_B_LUMA_CONTRAST_CNTL, 0x40,		/* Lum contrast, nominal value = 0x40 */
+	R_D6_B_CHROMA_SATURATION_CNTL, 0x40,		/* Chroma satur. nominal value = 0x80 */
 
-	B_VERT_LUMA_SCALING_INC, 0x00,
-	B_VERT_LUMA_SCALING_INC_MSB, 0x04,
+	R_E0_B_VERT_LUMA_SCALING_INC, 0x00,
+	R_E1_B_VERT_LUMA_SCALING_INC_MSB, 0x04,
 
-	B_VERT_CHROMA_SCALING_INC, 0x00,
-	B_VERT_CHROMA_SCALING_INC_MSB, 0x04,
+	R_E2_B_VERT_CHROMA_SCALING_INC, 0x00,
+	R_E3_B_VERT_CHROMA_SCALING_INC_MSB, 0x04,
 
 	0x00, 0x00
 };
 
 static const unsigned char saa7115_cfg_60hz_video[] = {
-	GLOBAL_CNTL_1, 0x00,			/* reset tasks */
-	POWER_SAVE_ADC_PORT_CNTL, 0xd0,		/* reset scaler */
+	R_80_GLOBAL_CNTL_1, 0x00,			/* reset tasks */
+	R_88_POWER_SAVE_ADC_PORT_CNTL, 0xd0,		/* reset scaler */
 
-	VGATE_START_FID_CHANGE, 0x03,
-	VGATE_STOP, 0x11,
-	MISC_VGATE_CONF_AND_MSBS, 0x9c,
+	R_15_VGATE_START_FID_CHG, 0x03,
+	R_16_VGATE_STOP, 0x11,
+	R_17_MISC_VGATE_CONF_AND_MSB, 0x9c,
 
-	SYNC_CNTL, 0x68,			/* 0xBO: auto detection, 0x68 = NTSC */
-	CHROMA_CNTL_1, 0x07,			/* video autodetection is on */
+	R_08_SYNC_CNTL, 0x68,			/* 0xBO: auto detection, 0x68 = NTSC */
+	R_0E_CHROMA_CNTL_1, 0x07,		/* video autodetection is on */
 
-	VERT_OFF_FOR_SLICER, 0x06,		/* standard 60hz value for ITU656 line counting */
+	R_5A_V_OFF_FOR_SLICER, 0x06,		/* standard 60hz value for ITU656 line counting */
 
 	/* Task A */
-	A_TASK_HANDLING_CNTL, 0x80,
-	A_X_PORT_FORMATS_AND_CONF, 0x48,
-	A_X_PORT_INPUT_REFERENCE_SIGNAL, 0x40,
-	A_I_PORT_OUTPUT_FORMATS_AND_CONF, 0x84,
+	R_90_A_TASK_HANDLING_CNTL, 0x80,
+	R_91_A_X_PORT_FORMATS_AND_CONF, 0x48,
+	R_92_A_X_PORT_INPUT_REFERENCE_SIGNAL, 0x40,
+	R_93_A_I_PORT_OUTPUT_FORMATS_AND_CONF, 0x84,
 
 	/* hoffset low (input), 0x0002 is minimum */
-	A_HORIZ_INPUT_WINDOW_START, 0x01,
-	A_HORIZ_INPUT_WINDOW_START_MSB, 0x00,
+	R_94_A_HORIZ_INPUT_WINDOW_START, 0x01,
+	R_95_A_HORIZ_INPUT_WINDOW_START_MSB, 0x00,
 
 	/* hsize low (input), 0x02d0 = 720 */
-	A_HORIZ_INPUT_WINDOW_LENGTH, 0xd0,
-	A_HORIZ_INPUT_WINDOW_LENGTH_MSB, 0x02,
+	R_96_A_HORIZ_INPUT_WINDOW_LENGTH, 0xd0,
+	R_97_A_HORIZ_INPUT_WINDOW_LENGTH_MSB, 0x02,
 
-	A_VERT_INPUT_WINDOW_START, 0x05,
-	A_VERT_INPUT_WINDOW_START_MSB, 0x00,
+	R_98_A_VERT_INPUT_WINDOW_START, 0x05,
+	R_99_A_VERT_INPUT_WINDOW_START_MSB, 0x00,
 
-	A_VERT_INPUT_WINDOW_LENGTH, 0x0c,
-	A_VERT_INPUT_WINDOW_LENGTH_MSB, 0x00,
+	R_9A_A_VERT_INPUT_WINDOW_LENGTH, 0x0c,
+	R_9B_A_VERT_INPUT_WINDOW_LENGTH_MSB, 0x00,
 
-	A_HORIZ_OUTPUT_WINDOW_LENGTH, 0xa0,
-	A_HORIZ_OUTPUT_WINDOW_LENGTH_MSB, 0x05,
+	R_9C_A_HORIZ_OUTPUT_WINDOW_LENGTH, 0xa0,
+	R_9D_A_HORIZ_OUTPUT_WINDOW_LENGTH_MSB, 0x05,
 
-	A_VERT_OUTPUT_WINDOW_LENGTH, 0x0c,
-	A_VERT_OUTPUT_WINDOW_LENGTH_MSB, 0x00,
+	R_9E_A_VERT_OUTPUT_WINDOW_LENGTH, 0x0c,
+	R_9F_A_VERT_OUTPUT_WINDOW_LENGTH_MSB, 0x00,
 
 	/* Task B */
-	B_TASK_HANDLING_CNTL, 0x00,
-	B_X_PORT_FORMATS_AND_CONF, 0x08,
-	B_INPUT_REFERENCE_SIGNAL_DEFINITION, 0x00,
-	B_I_PORT_FORMATS_AND_CONF, 0x80,
+	R_C0_B_TASK_HANDLING_CNTL, 0x00,
+	R_C1_B_X_PORT_FORMATS_AND_CONF, 0x08,
+	R_C2_B_INPUT_REFERENCE_SIGNAL_DEFINITION, 0x00,
+	R_C3_B_I_PORT_FORMATS_AND_CONF, 0x80,
 
 	/* 0x0002 is minimum */
-	B_HORIZ_INPUT_WINDOW_START, 0x02,
-	B_HORIZ_INPUT_WINDOW_START_MSB, 0x00,
+	R_C4_B_HORIZ_INPUT_WINDOW_START, 0x02,
+	R_C5_B_HORIZ_INPUT_WINDOW_START_MSB, 0x00,
 
 	/* 0x02d0 = 720 */
-	B_HORIZ_INPUT_WINDOW_LENGTH, 0xd0,
-	B_HORIZ_INPUT_WINDOW_LENGTH_MSB, 0x02,
+	R_C6_B_HORIZ_INPUT_WINDOW_LENGTH, 0xd0,
+	R_C7_B_HORIZ_INPUT_WINDOW_LENGTH_MSB, 0x02,
 
 	/* vwindow start 0x12 = 18 */
-	B_VERT_INPUT_WINDOW_START, 0x12,
-	B_VERT_INPUT_WINDOW_START_MSB, 0x00,
+	R_C8_B_VERT_INPUT_WINDOW_START, 0x12,
+	R_C9_B_VERT_INPUT_WINDOW_START_MSB, 0x00,
 
 	/* vwindow length 0xf8 = 248 */
-	B_VERT_INPUT_WINDOW_LENGTH, 0xf8,
-	B_VERT_INPUT_WINDOW_LENGTH_MSB, 0x00,
+	R_CA_B_VERT_INPUT_WINDOW_LENGTH, 0xf8,
+	R_CB_B_VERT_INPUT_WINDOW_LENGTH_MSB, 0x00,
 
 	/* hwindow 0x02d0 = 720 */
-	B_HORIZ_OUTPUT_WINDOW_LENGTH, 0xd0,
-	B_HORIZ_OUTPUT_WINDOW_LENGTH_MSB, 0x02,
-
-	LFCO_PER_LINE, 0xad,		/* Set PLL Register. 60hz 525 lines per frame, 27 MHz */
-	P_I_PARAM_SELECT, 0x05,		/* low bit with 0xF0 */
-	PULSGEN_LINE_LENGTH, 0xad,
-	PULSE_A_POS_LSB_AND_PULSEGEN_CONFIG, 0x01,
-
-	I_PORT_I_O_ENABLE_OUTPUT_CLOCK_AND_GATED, 0x00,	/* Disable I-port output */
-	POWER_SAVE_ADC_PORT_CNTL, 0xd0,			/* reset scaler */
-	GLOBAL_CNTL_1, 0x20,				/* Activate only task "B", continuous mode (was 0xA0) */
-	POWER_SAVE_ADC_PORT_CNTL, 0xf0,			/* activate scaler */
-	I_PORT_I_O_ENABLE_OUTPUT_CLOCK_AND_GATED, 0x01,	/* Enable I-port output */
+	R_CC_B_HORIZ_OUTPUT_WINDOW_LENGTH, 0xd0,
+	R_CD_B_HORIZ_OUTPUT_WINDOW_LENGTH_MSB, 0x02,
+
+	R_F0_LFCO_PER_LINE, 0xad,		/* Set PLL Register. 60hz 525 lines per frame, 27 MHz */
+	R_F1_P_I_PARAM_SELECT, 0x05,		/* low bit with 0xF0 */
+	R_F5_PULSGEN_LINE_LENGTH, 0xad,
+	R_F6_PULSE_A_POS_LSB_AND_PULSEGEN_CONFIG, 0x01,
+
+	R_87_I_PORT_I_O_ENA_OUT_CLK_AND_GATED, 0x00,	/* Disable I-port output */
+	R_88_POWER_SAVE_ADC_PORT_CNTL, 0xd0,		/* reset scaler */
+	R_80_GLOBAL_CNTL_1, 0x20,			/* Activate only task "B", continuous mode (was 0xA0) */
+	R_88_POWER_SAVE_ADC_PORT_CNTL, 0xf0,		/* activate scaler */
+	R_87_I_PORT_I_O_ENA_OUT_CLK_AND_GATED, 0x01,	/* Enable I-port output */
 	0x00, 0x00
 };
 
 static const unsigned char saa7115_cfg_50hz_fullres_x[] = {
 	/* hsize low (output), 720 same as 60hz */
-	B_HORIZ_OUTPUT_WINDOW_LENGTH, 0xd0,
-	B_HORIZ_OUTPUT_WINDOW_LENGTH_MSB, 0x02,
+	R_CC_B_HORIZ_OUTPUT_WINDOW_LENGTH, 0xd0,
+	R_CD_B_HORIZ_OUTPUT_WINDOW_LENGTH_MSB, 0x02,
 
-	B_HORIZ_PRESCALING, 0x01,		/* down scale = 1 */
-	B_HORIZ_LUMA_SCALING_INC, 0x00,		/* hor lum scaling 0x0400 = 1 */
-	B_HORIZ_LUMA_SCALING_INC_MSB, 0x04,
+	R_D0_B_HORIZ_PRESCALING, 0x01,		/* down scale = 1 */
+	R_D8_B_HORIZ_LUMA_SCALING_INC, 0x00,	/* hor lum scaling 0x0400 = 1 */
+	R_D9_B_HORIZ_LUMA_SCALING_INC_MSB, 0x04,
 
 	/* must be hor lum scaling / 2 */
-	B_HORIZ_CHROMA_SCALING, 0x00,
-	B_HORIZ_CHROMA_SCALING_MSB, 0x02,
+	R_DC_B_HORIZ_CHROMA_SCALING, 0x00,
+	R_DD_B_HORIZ_CHROMA_SCALING_MSB, 0x02,
 
 	0x00, 0x00
 };
 static const unsigned char saa7115_cfg_50hz_fullres_y[] = {
 	/* vsize low (output), 0x0120 = 288 */
-	B_VERT_OUTPUT_WINDOW_LENGTH, 0x20,
-	B_VERT_OUTPUT_WINDOW_LENGTH_MSB, 0x01,
+	R_CE_B_VERT_OUTPUT_WINDOW_LENGTH, 0x20,
+	R_CF_B_VERT_OUTPUT_WINDOW_LENGTH_MSB, 0x01,
 
-	B_LUMA_CONTRAST_CNTL, 0x40,		/* Lum contrast, nominal value = 0x40 */
-	B_CHROMA_SATURATION_CNTL, 0x40,		/* Chroma satur. nominal value = 0x80 */
+	R_D5_B_LUMA_CONTRAST_CNTL, 0x40,	/* Lum contrast, nominal value = 0x40 */
+	R_D6_B_CHROMA_SATURATION_CNTL, 0x40,	/* Chroma satur. nominal value = 0x80 */
 
-	B_VERT_LUMA_SCALING_INC, 0x00,
-	B_VERT_LUMA_SCALING_INC_MSB, 0x04,
+	R_E0_B_VERT_LUMA_SCALING_INC, 0x00,
+	R_E1_B_VERT_LUMA_SCALING_INC_MSB, 0x04,
 
-	B_VERT_CHROMA_SCALING_INC, 0x00,
-	B_VERT_CHROMA_SCALING_INC_MSB, 0x04,
+	R_E2_B_VERT_CHROMA_SCALING_INC, 0x00,
+	R_E3_B_VERT_CHROMA_SCALING_INC_MSB, 0x04,
 
 	0x00, 0x00
 };
 
 static const unsigned char saa7115_cfg_50hz_video[] = {
-	GLOBAL_CNTL_1, 0x00,
-	POWER_SAVE_ADC_PORT_CNTL, 0xd0,		/* reset scaler */
+	R_80_GLOBAL_CNTL_1, 0x00,
+	R_88_POWER_SAVE_ADC_PORT_CNTL, 0xd0,	/* reset scaler */
 
-	VGATE_START_FID_CHANGE, 0x37,		/* VGATE start */
-	VGATE_STOP, 0x16,
-	MISC_VGATE_CONF_AND_MSBS, 0x99,
+	R_15_VGATE_START_FID_CHG, 0x37,		/* VGATE start */
+	R_16_VGATE_STOP, 0x16,
+	R_17_MISC_VGATE_CONF_AND_MSB, 0x99,
 
-	SYNC_CNTL, 0x28,			/* 0x28 = PAL */
-	CHROMA_CNTL_1, 0x07,
+	R_08_SYNC_CNTL, 0x28,			/* 0x28 = PAL */
+	R_0E_CHROMA_CNTL_1, 0x07,
 
-	VERT_OFF_FOR_SLICER, 0x03,		/* standard 50hz value */
+	R_5A_V_OFF_FOR_SLICER, 0x03,		/* standard 50hz value */
 
 	/* Task A */
-	A_TASK_HANDLING_CNTL, 0x81,
-	A_X_PORT_FORMATS_AND_CONF, 0x48,
-	A_X_PORT_INPUT_REFERENCE_SIGNAL, 0x40,
-	A_I_PORT_OUTPUT_FORMATS_AND_CONF, 0x84,
+	R_90_A_TASK_HANDLING_CNTL, 0x81,
+	R_91_A_X_PORT_FORMATS_AND_CONF, 0x48,
+	R_92_A_X_PORT_INPUT_REFERENCE_SIGNAL, 0x40,
+	R_93_A_I_PORT_OUTPUT_FORMATS_AND_CONF, 0x84,
 
 	/* This is weird: the datasheet says that you should use 2 as the minimum value, */
 	/* but Hauppauge uses 0, and changing that to 2 causes indeed problems (for 50hz) */
 	/* hoffset low (input), 0x0002 is minimum */
-	A_HORIZ_INPUT_WINDOW_START, 0x00,
-	A_HORIZ_INPUT_WINDOW_START_MSB, 0x00,
+	R_94_A_HORIZ_INPUT_WINDOW_START, 0x00,
+	R_95_A_HORIZ_INPUT_WINDOW_START_MSB, 0x00,
 
 	/* hsize low (input), 0x02d0 = 720 */
-	A_HORIZ_INPUT_WINDOW_LENGTH, 0xd0,
-	A_HORIZ_INPUT_WINDOW_LENGTH_MSB, 0x02,
+	R_96_A_HORIZ_INPUT_WINDOW_LENGTH, 0xd0,
+	R_97_A_HORIZ_INPUT_WINDOW_LENGTH_MSB, 0x02,
 
-	A_VERT_INPUT_WINDOW_START, 0x03,
-	A_VERT_INPUT_WINDOW_START_MSB, 0x00,
+	R_98_A_VERT_INPUT_WINDOW_START, 0x03,
+	R_99_A_VERT_INPUT_WINDOW_START_MSB, 0x00,
 
 	/* vsize 0x12 = 18 */
-	A_VERT_INPUT_WINDOW_LENGTH, 0x12,
-	A_VERT_INPUT_WINDOW_LENGTH_MSB, 0x00,
+	R_9A_A_VERT_INPUT_WINDOW_LENGTH, 0x12,
+	R_9B_A_VERT_INPUT_WINDOW_LENGTH_MSB, 0x00,
 
 	/* hsize 0x05a0 = 1440 */
-	A_HORIZ_OUTPUT_WINDOW_LENGTH, 0xa0,
-	A_HORIZ_OUTPUT_WINDOW_LENGTH_MSB, 0x05,		/* hsize hi (output) */
-	A_VERT_OUTPUT_WINDOW_LENGTH, 0x12,		/* vsize low (output), 0x12 = 18 */
-	A_VERT_OUTPUT_WINDOW_LENGTH_MSB, 0x00,		/* vsize hi (output) */
+	R_9C_A_HORIZ_OUTPUT_WINDOW_LENGTH, 0xa0,
+	R_9D_A_HORIZ_OUTPUT_WINDOW_LENGTH_MSB, 0x05,	/* hsize hi (output) */
+	R_9E_A_VERT_OUTPUT_WINDOW_LENGTH, 0x12,		/* vsize low (output), 0x12 = 18 */
+	R_9F_A_VERT_OUTPUT_WINDOW_LENGTH_MSB, 0x00,	/* vsize hi (output) */
 
 	/* Task B */
-	B_TASK_HANDLING_CNTL, 0x00,
-	B_X_PORT_FORMATS_AND_CONF, 0x08,
-	B_INPUT_REFERENCE_SIGNAL_DEFINITION, 0x00,
-	B_I_PORT_FORMATS_AND_CONF, 0x80,
+	R_C0_B_TASK_HANDLING_CNTL, 0x00,
+	R_C1_B_X_PORT_FORMATS_AND_CONF, 0x08,
+	R_C2_B_INPUT_REFERENCE_SIGNAL_DEFINITION, 0x00,
+	R_C3_B_I_PORT_FORMATS_AND_CONF, 0x80,
 
 	/* This is weird: the datasheet says that you should use 2 as the minimum value, */
 	/* but Hauppauge uses 0, and changing that to 2 causes indeed problems (for 50hz) */
 	/* hoffset low (input), 0x0002 is minimum. See comment above. */
-	B_HORIZ_INPUT_WINDOW_START, 0x00,
-	B_HORIZ_INPUT_WINDOW_START_MSB, 0x00,
+	R_C4_B_HORIZ_INPUT_WINDOW_START, 0x00,
+	R_C5_B_HORIZ_INPUT_WINDOW_START_MSB, 0x00,
 
 	/* hsize 0x02d0 = 720 */
-	B_HORIZ_INPUT_WINDOW_LENGTH, 0xd0,
-	B_HORIZ_INPUT_WINDOW_LENGTH_MSB, 0x02,
+	R_C6_B_HORIZ_INPUT_WINDOW_LENGTH, 0xd0,
+	R_C7_B_HORIZ_INPUT_WINDOW_LENGTH_MSB, 0x02,
 
 	/* voffset 0x16 = 22 */
-	B_VERT_INPUT_WINDOW_START, 0x16,
-	B_VERT_INPUT_WINDOW_START_MSB, 0x00,
+	R_C8_B_VERT_INPUT_WINDOW_START, 0x16,
+	R_C9_B_VERT_INPUT_WINDOW_START_MSB, 0x00,
 
 	/* vsize 0x0120 = 288 */
-	B_VERT_INPUT_WINDOW_LENGTH, 0x20,
-	B_VERT_INPUT_WINDOW_LENGTH_MSB, 0x01,
+	R_CA_B_VERT_INPUT_WINDOW_LENGTH, 0x20,
+	R_CB_B_VERT_INPUT_WINDOW_LENGTH_MSB, 0x01,
 
 	/* hsize 0x02d0 = 720 */
-	B_HORIZ_OUTPUT_WINDOW_LENGTH, 0xd0,
-	B_HORIZ_OUTPUT_WINDOW_LENGTH_MSB, 0x02,
+	R_CC_B_HORIZ_OUTPUT_WINDOW_LENGTH, 0xd0,
+	R_CD_B_HORIZ_OUTPUT_WINDOW_LENGTH_MSB, 0x02,
 
 	/* vsize 0x0120 = 288 */
-	B_VERT_OUTPUT_WINDOW_LENGTH, 0x20,
-	B_VERT_OUTPUT_WINDOW_LENGTH_MSB, 0x01,
+	R_CE_B_VERT_OUTPUT_WINDOW_LENGTH, 0x20,
+	R_CF_B_VERT_OUTPUT_WINDOW_LENGTH_MSB, 0x01,
 
-	LFCO_PER_LINE, 0xb0,		/* Set PLL Register. 50hz 625 lines per frame, 27 MHz */
-	P_I_PARAM_SELECT, 0x05,		/* low bit with 0xF0, (was 0x05) */
-	PULSGEN_LINE_LENGTH, 0xb0,
-	PULSE_A_POS_LSB_AND_PULSEGEN_CONFIG, 0x01,
+	R_F0_LFCO_PER_LINE, 0xb0,		/* Set PLL Register. 50hz 625 lines per frame, 27 MHz */
+	R_F1_P_I_PARAM_SELECT, 0x05,		/* low bit with 0xF0, (was 0x05) */
+	R_F5_PULSGEN_LINE_LENGTH, 0xb0,
+	R_F6_PULSE_A_POS_LSB_AND_PULSEGEN_CONFIG, 0x01,
 
-	I_PORT_I_O_ENABLE_OUTPUT_CLOCK_AND_GATED, 0x00,	/* Disable I-port output */
-	POWER_SAVE_ADC_PORT_CNTL, 0xd0,		/* reset scaler (was 0xD0) */
-	GLOBAL_CNTL_1, 0x20,			/* Activate only task "B" */
-	POWER_SAVE_ADC_PORT_CNTL, 0xf0,		/* activate scaler */
-	I_PORT_I_O_ENABLE_OUTPUT_CLOCK_AND_GATED, 0x01,	/* Enable I-port output */
+	R_87_I_PORT_I_O_ENA_OUT_CLK_AND_GATED, 0x00,	/* Disable I-port output */
+	R_88_POWER_SAVE_ADC_PORT_CNTL, 0xd0,		/* reset scaler (was 0xD0) */
+	R_80_GLOBAL_CNTL_1, 0x20,			/* Activate only task "B" */
+	R_88_POWER_SAVE_ADC_PORT_CNTL, 0xf0,		/* activate scaler */
+	R_87_I_PORT_I_O_ENA_OUT_CLK_AND_GATED, 0x01,	/* Enable I-port output */
 
 	0x00, 0x00
 };
@@ -400,195 +400,195 @@ static const unsigned char saa7115_cfg_50hz_video[] = {
 /* ============== SAA7715 VIDEO templates (end) =======  */
 
 static const unsigned char saa7115_cfg_vbi_on[] = {
-	GLOBAL_CNTL_1, 0x00,				/* reset tasks */
-	POWER_SAVE_ADC_PORT_CNTL, 0xd0,			/* reset scaler */
-	GLOBAL_CNTL_1, 0x30,				/* Activate both tasks */
-	POWER_SAVE_ADC_PORT_CNTL, 0xf0,			/* activate scaler */
-	I_PORT_I_O_ENABLE_OUTPUT_CLOCK_AND_GATED, 0x01,	/* Enable I-port output */
+	R_80_GLOBAL_CNTL_1, 0x00,			/* reset tasks */
+	R_88_POWER_SAVE_ADC_PORT_CNTL, 0xd0,		/* reset scaler */
+	R_80_GLOBAL_CNTL_1, 0x30,			/* Activate both tasks */
+	R_88_POWER_SAVE_ADC_PORT_CNTL, 0xf0,		/* activate scaler */
+	R_87_I_PORT_I_O_ENA_OUT_CLK_AND_GATED, 0x01,	/* Enable I-port output */
 
 	0x00, 0x00
 };
 
 static const unsigned char saa7115_cfg_vbi_off[] = {
-	GLOBAL_CNTL_1, 0x00,				/* reset tasks */
-	POWER_SAVE_ADC_PORT_CNTL, 0xd0,			/* reset scaler */
-	GLOBAL_CNTL_1, 0x20,				/* Activate only task "B" */
-	POWER_SAVE_ADC_PORT_CNTL, 0xf0,			/* activate scaler */
-	I_PORT_I_O_ENABLE_OUTPUT_CLOCK_AND_GATED, 0x01,	/* Enable I-port output */
+	R_80_GLOBAL_CNTL_1, 0x00,			/* reset tasks */
+	R_88_POWER_SAVE_ADC_PORT_CNTL, 0xd0,		/* reset scaler */
+	R_80_GLOBAL_CNTL_1, 0x20,			/* Activate only task "B" */
+	R_88_POWER_SAVE_ADC_PORT_CNTL, 0xf0,		/* activate scaler */
+	R_87_I_PORT_I_O_ENA_OUT_CLK_AND_GATED, 0x01,	/* Enable I-port output */
 
 	0x00, 0x00
 };
 
 #if 1 /* saa7113 init codes */
 static const unsigned char saa7113_init_auto_input[] = {
-	INC_DELAY, 0x08,
-	ANALOG_INPUT_CNTL_1, 0xc2,
-	ANALOG_INPUT_CNTL_2, 0x30,
-	ANALOG_INPUT_CNTL_3, 0x00,
-	ANALOG_INPUT_CNTL_4, 0x00,
-	HORIZ_SYNC_START, 0x89,
-	HORIZ_SYNC_STOP, 0x0d,
-	SYNC_CNTL, 0x88,
-	LUMA_CNTL, 0x01,
-	LUMA_BRIGHTNESS_CNTL, 0x80,
-	LUMA_CONTRAST_CNTL, 0x47,
-	CHROMA_SATURATION_CNTL, 0x40,
-	CHROMA_HUE_CNTL, 0x00,
-	CHROMA_CNTL_1, 0x01,
-	CHROMA_GAIN_CNTL, 0x2a,
-	CHROMA_CNTL_2, 0x08,
-	MODE_DELAY_CNTL, 0x0c,
-	RT_SIGNAL_CNTL, 0x07,
-	RT_X_PORT_OUTPUT_CNTL, 0x00,
-	ANALOG_ADC_COMPAT_CNTL, 0x00,
-	VGATE_START_FID_CHANGE, 0x00,
-	VGATE_STOP, 0x00,
-	MISC_VGATE_CONF_AND_MSBS, 0x00,
+	R_01_INC_DELAY, 0x08,
+	R_02_INPUT_CNTL_1, 0xc2,
+	R_03_INPUT_CNTL_2, 0x30,
+	R_04_INPUT_CNTL_3, 0x00,
+	R_05_INPUT_CNTL_4, 0x00,
+	R_06_H_SYNC_START, 0x89,
+	R_07_H_SYNC_STOP, 0x0d,
+	R_08_SYNC_CNTL, 0x88,
+	R_09_LUMA_CNTL, 0x01,
+	R_0A_LUMA_BRIGHT_CNTL, 0x80,
+	R_0B_LUMA_CONTRAST_CNTL, 0x47,
+	R_0C_CHROMA_SAT_CNTL, 0x40,
+	R_0D_CHROMA_HUE_CNTL, 0x00,
+	R_0E_CHROMA_CNTL_1, 0x01,
+	R_0F_CHROMA_GAIN_CNTL, 0x2a,
+	R_10_CHROMA_CNTL_2, 0x08,
+	R_11_MODE_DELAY_CNTL, 0x0c,
+	R_12_RT_SIGNAL_CNTL, 0x07,
+	R_13_RT_X_PORT_OUT_CNTL, 0x00,
+	R_14_ANAL_ADC_COMPAT_CNTL, 0x00,
+	R_15_VGATE_START_FID_CHG, 0x00,
+	R_16_VGATE_STOP, 0x00,
+	R_17_MISC_VGATE_CONF_AND_MSB, 0x00,
 
 	0x00, 0x00
 };
 #endif
 
 static const unsigned char saa7115_init_misc[] = {
-	VERT_SYNC_FLD_ID_SRC_SEL_AND_RETIMED_V_F, 0x01,
+	R_81_V_SYNC_FLD_ID_SRC_SEL_AND_RETIMED_V_F, 0x01,
 	0x82, 0x00,		/* Reserved register - value should be zero*/
-	X_PORT_I_O_ENABLE_AND_OUTPUT_CLOCK, 0x01,
-	I_PORT_SIGNAL_DEFINITIONS, 0x20,
-	I_PORT_SIGNAL_POLARITIES, 0x21,
-	I_PORT_FIFO_FLAG_CNTL_AND_ARBITRATION, 0xc5,
-	I_PORT_I_O_ENABLE_OUTPUT_CLOCK_AND_GATED, 0x01,
+	R_83_X_PORT_I_O_ENA_AND_OUT_CLK, 0x01,
+	R_84_I_PORT_SIGNAL_DEF, 0x20,
+	R_85_I_PORT_SIGNAL_POLAR, 0x21,
+	R_86_I_PORT_FIFO_FLAG_CNTL_AND_ARBIT, 0xc5,
+	R_87_I_PORT_I_O_ENA_OUT_CLK_AND_GATED, 0x01,
 
 	/* Task A */
-	A_HORIZ_PRESCALING, 0x01,
-	A_ACCUMULATION_LENGTH, 0x00,
-	A_PRESCALER_DC_GAIN_AND_FIR_PREFILTER, 0x00,
+	R_A0_A_HORIZ_PRESCALING, 0x01,
+	R_A1_A_ACCUMULATION_LENGTH, 0x00,
+	R_A2_A_PRESCALER_DC_GAIN_AND_FIR_PREFILTER, 0x00,
 
 	/* Configure controls at nominal value*/
-	A_LUMA_BRIGHTNESS_CNTL, 0x80,
-	A_LUMA_CONTRAST_CNTL, 0x40,
-	A_CHROMA_SATURATION_CNTL, 0x40,
+	R_A4_A_LUMA_BRIGHTNESS_CNTL, 0x80,
+	R_A5_A_LUMA_CONTRAST_CNTL, 0x40,
+	R_A6_A_CHROMA_SATURATION_CNTL, 0x40,
 
 	/* note: 2 x zoom ensures that VBI lines have same length as video lines. */
-	A_HORIZ_LUMA_SCALING_INC, 0x00,
-	A_HORIZ_LUMA_SCALING_INC_MSB, 0x02,
+	R_A8_A_HORIZ_LUMA_SCALING_INC, 0x00,
+	R_A9_A_HORIZ_LUMA_SCALING_INC_MSB, 0x02,
 
-	A_HORIZ_LUMA_PHASE_OFF, 0x00,
+	R_AA_A_HORIZ_LUMA_PHASE_OFF, 0x00,
 
 	/* must be horiz lum scaling / 2 */
-	A_HORIZ_CHROMA_SCALING_INC, 0x00,
-	A_HORIZ_CHROMA_SCALING_INC_MSB, 0x01,
+	R_AC_A_HORIZ_CHROMA_SCALING_INC, 0x00,
+	R_AD_A_HORIZ_CHROMA_SCALING_INC_MSB, 0x01,
 
 	/* must be offset luma / 2 */
-	A_HORIZ_CHROMA_PHASE_OFF, 0x00,
+	R_AE_A_HORIZ_CHROMA_PHASE_OFF, 0x00,
 
-	A_VERT_LUMA_SCALING_INC, 0x00,
-	A_VERT_LUMA_SCALING_INC_MSB, 0x04,
+	R_B0_A_VERT_LUMA_SCALING_INC, 0x00,
+	R_B1_A_VERT_LUMA_SCALING_INC_MSB, 0x04,
 
-	A_VERT_CHROMA_SCALING_INC, 0x00,
-	A_VERT_CHROMA_SCALING_INC_MSB, 0x04,
+	R_B2_A_VERT_CHROMA_SCALING_INC, 0x00,
+	R_B3_A_VERT_CHROMA_SCALING_INC_MSB, 0x04,
 
-	A_VERT_SCALING_MODE_CNTL, 0x01,
+	R_B4_A_VERT_SCALING_MODE_CNTL, 0x01,
 
-	A_VERT_CHROMA_PHASE_OFF_00, 0x00,
-	A_VERT_CHROMA_PHASE_OFF_01, 0x00,
-	A_VERT_CHROMA_PHASE_OFF_10, 0x00,
-	A_VERT_CHROMA_PHASE_OFF_11, 0x00,
+	R_B8_A_VERT_CHROMA_PHASE_OFF_00, 0x00,
+	R_B9_A_VERT_CHROMA_PHASE_OFF_01, 0x00,
+	R_BA_A_VERT_CHROMA_PHASE_OFF_10, 0x00,
+	R_BB_A_VERT_CHROMA_PHASE_OFF_11, 0x00,
 
-	A_VERT_LUMA_PHASE_OFF_00, 0x00,
-	A_VERT_LUMA_PHASE_OFF_01, 0x00,
-	A_VERT_LUMA_PHASE_OFF_10, 0x00,
-	A_VERT_LUMA_PHASE_OFF_11, 0x00,
+	R_BC_A_VERT_LUMA_PHASE_OFF_00, 0x00,
+	R_BD_A_VERT_LUMA_PHASE_OFF_01, 0x00,
+	R_BE_A_VERT_LUMA_PHASE_OFF_10, 0x00,
+	R_BF_A_VERT_LUMA_PHASE_OFF_11, 0x00,
 
 	/* Task B */
-	B_HORIZ_PRESCALING, 0x01,
-	B_ACCUMULATION_LENGTH, 0x00,
-	B_PRESCALER_DC_GAIN_AND_FIR_PREFILTER, 0x00,
+	R_D0_B_HORIZ_PRESCALING, 0x01,
+	R_D1_B_ACCUMULATION_LENGTH, 0x00,
+	R_D2_B_PRESCALER_DC_GAIN_AND_FIR_PREFILTER, 0x00,
 
 	/* Configure controls at nominal value*/
-	B_LUMA_BRIGHTNESS_CNTL, 0x80,
-	B_LUMA_CONTRAST_CNTL, 0x40,
-	B_CHROMA_SATURATION_CNTL, 0x40,
+	R_D4_B_LUMA_BRIGHTNESS_CNTL, 0x80,
+	R_D5_B_LUMA_CONTRAST_CNTL, 0x40,
+	R_D6_B_CHROMA_SATURATION_CNTL, 0x40,
 
 	/* hor lum scaling 0x0400 = 1 */
-	B_HORIZ_LUMA_SCALING_INC, 0x00,
-	B_HORIZ_LUMA_SCALING_INC_MSB, 0x04,
+	R_D8_B_HORIZ_LUMA_SCALING_INC, 0x00,
+	R_D9_B_HORIZ_LUMA_SCALING_INC_MSB, 0x04,
 
-	B_HORIZ_LUMA_PHASE_OFF, 0x00,
+	R_DA_B_HORIZ_LUMA_PHASE_OFF, 0x00,
 
 	/* must be hor lum scaling / 2 */
-	B_HORIZ_CHROMA_SCALING, 0x00,
-	B_HORIZ_CHROMA_SCALING_MSB, 0x02,
+	R_DC_B_HORIZ_CHROMA_SCALING, 0x00,
+	R_DD_B_HORIZ_CHROMA_SCALING_MSB, 0x02,
 
 	/* must be offset luma / 2 */
-	B_HORIZ_PHASE_OFFSET_CRHOMA, 0x00,
+	R_DE_B_HORIZ_PHASE_OFFSET_CRHOMA, 0x00,
 
-	B_VERT_LUMA_SCALING_INC, 0x00,
-	B_VERT_LUMA_SCALING_INC_MSB, 0x04,
+	R_E0_B_VERT_LUMA_SCALING_INC, 0x00,
+	R_E1_B_VERT_LUMA_SCALING_INC_MSB, 0x04,
 
-	B_VERT_CHROMA_SCALING_INC, 0x00,
-	B_VERT_CHROMA_SCALING_INC_MSB, 0x04,
+	R_E2_B_VERT_CHROMA_SCALING_INC, 0x00,
+	R_E3_B_VERT_CHROMA_SCALING_INC_MSB, 0x04,
 
-	B_VERT_SCALING_MODE_CNTL, 0x01,
+	R_E4_B_VERT_SCALING_MODE_CNTL, 0x01,
 
-	B_VERT_CHROMA_PHASE_OFF_00, 0x00,
-	B_VERT_CHROMA_PHASE_OFF_01, 0x00,
-	B_VERT_CHROMA_PHASE_OFF_10, 0x00,
-	B_VERT_CHROMA_PHASE_OFF_11, 0x00,
+	R_E8_B_VERT_CHROMA_PHASE_OFF_00, 0x00,
+	R_E9_B_VERT_CHROMA_PHASE_OFF_01, 0x00,
+	R_EA_B_VERT_CHROMA_PHASE_OFF_10, 0x00,
+	R_EB_B_VERT_CHROMA_PHASE_OFF_11, 0x00,
 
-	B_VERT_LUMA_PHASE_OFF_00, 0x00,
-	B_VERT_LUMA_PHASE_OFF_01, 0x00,
-	B_VERT_LUMA_PHASE_OFF_10, 0x00,
-	B_VERT_LUMA_PHASE_OFF_11, 0x00,
+	R_EC_B_VERT_LUMA_PHASE_OFF_00, 0x00,
+	R_ED_B_VERT_LUMA_PHASE_OFF_01, 0x00,
+	R_EE_B_VERT_LUMA_PHASE_OFF_10, 0x00,
+	R_EF_B_VERT_LUMA_PHASE_OFF_11, 0x00,
 
-	NOMINAL_PLL2_DTO, 0x50,		/* crystal clock = 24.576 MHz, target = 27MHz */
-	PLL_INCREMENT, 0x46,
-	PLL2_STATUS, 0x00,
-	PULSE_A_POS_MSB, 0x4b,		/* not the recommended settings! */
-	PULSE_B_POS, 0x00,
-	PULSE_B_POS_MSB, 0x4b,
-	PULSE_C_POS, 0x00,
-	PULSE_C_POS_MSB, 0x4b,
+	R_F2_NOMINAL_PLL2_DTO, 0x50,		/* crystal clock = 24.576 MHz, target = 27MHz */
+	R_F3_PLL_INCREMENT, 0x46,
+	R_F4_PLL2_STATUS, 0x00,
+	R_F7_PULSE_A_POS_MSB, 0x4b,		/* not the recommended settings! */
+	R_F8_PULSE_B_POS, 0x00,
+	R_F9_PULSE_B_POS_MSB, 0x4b,
+	R_FA_PULSE_C_POS, 0x00,
+	R_FB_PULSE_C_POS_MSB, 0x4b,
 
 	/* PLL2 lock detection settings: 71 lines 50% phase error */
-	S_PLL_MAX_PHASE_ERR_THRESH_NUM_LINES, 0x88,
+	R_FF_S_PLL_MAX_PHASE_ERR_THRESH_NUM_LINES, 0x88,
 
 	/* Turn off VBI */
-	SLICER_CNTL_1, 0x20,             /* No framing code errors allowed. */
-	LCR, 0xff,
-	LCR+1, 0xff,
-	LCR+2, 0xff,
-	LCR+3, 0xff,
-	LCR+4, 0xff,
-	LCR+5, 0xff,
-	LCR+6, 0xff,
-	LCR+7, 0xff,
-	LCR+8, 0xff,
-	LCR+9, 0xff,
-	LCR+10, 0xff,
-	LCR+11, 0xff,
-	LCR+12, 0xff,
-	LCR+13, 0xff,
-	LCR+14, 0xff,
-	LCR+15, 0xff,
-	LCR+16, 0xff,
-	LCR+17, 0xff,
-	LCR+18, 0xff,
-	LCR+19, 0xff,
-	LCR+20, 0xff,
-	LCR+21, 0xff,
-	LCR+22, 0xff,
-	PROGRAMMABLE_FRAMING_CODE, 0x40,
-	HORIZ_OFF_FOR_SLICER, 0x47,
-	FIELD_OFF_AND_MSB_FOR_HORIZ_AND_VERT_OFF, 0x83,
-	DID, 0xbd,
-	SDID, 0x35,
-
-	ANALOG_INPUT_CNTL_1, 0x84,		/* input tuner -> input 4, amplifier active */
-	LUMA_CNTL, 0x53,		/* 0x53, was 0x56 for 60hz. luminance control */
-
-	GLOBAL_CNTL_1, 0x20,		/* enable task B */
-	POWER_SAVE_ADC_PORT_CNTL, 0xd0,
-	POWER_SAVE_ADC_PORT_CNTL, 0xf0,
+	R_40_SLICER_CNTL_1, 0x20,             /* No framing code errors allowed. */
+	R_41_LCR_BASE, 0xff,
+	R_41_LCR_BASE+1, 0xff,
+	R_41_LCR_BASE+2, 0xff,
+	R_41_LCR_BASE+3, 0xff,
+	R_41_LCR_BASE+4, 0xff,
+	R_41_LCR_BASE+5, 0xff,
+	R_41_LCR_BASE+6, 0xff,
+	R_41_LCR_BASE+7, 0xff,
+	R_41_LCR_BASE+8, 0xff,
+	R_41_LCR_BASE+9, 0xff,
+	R_41_LCR_BASE+10, 0xff,
+	R_41_LCR_BASE+11, 0xff,
+	R_41_LCR_BASE+12, 0xff,
+	R_41_LCR_BASE+13, 0xff,
+	R_41_LCR_BASE+14, 0xff,
+	R_41_LCR_BASE+15, 0xff,
+	R_41_LCR_BASE+16, 0xff,
+	R_41_LCR_BASE+17, 0xff,
+	R_41_LCR_BASE+18, 0xff,
+	R_41_LCR_BASE+19, 0xff,
+	R_41_LCR_BASE+20, 0xff,
+	R_41_LCR_BASE+21, 0xff,
+	R_41_LCR_BASE+22, 0xff,
+	R_58_PROGRAM_FRAMING_CODE, 0x40,
+	R_59_H_OFF_FOR_SLICER, 0x47,
+	R_5B_FLD_OFF_AND_MSB_FOR_H_AND_V_OFF, 0x83,
+	R_5D_DID, 0xbd,
+	R_5E_SDID, 0x35,
+
+	R_02_INPUT_CNTL_1, 0x84,		/* input tuner -> input 4, amplifier active */
+	R_09_LUMA_CNTL, 0x53,			/* 0x53, was 0x56 for 60hz. luminance control */
+
+	R_80_GLOBAL_CNTL_1, 0x20,		/* enable task B */
+	R_88_POWER_SAVE_ADC_PORT_CNTL, 0xd0,
+	R_88_POWER_SAVE_ADC_PORT_CNTL, 0xf0,
 	0x00, 0x00
 };
 
@@ -716,15 +716,19 @@ static int saa7115_set_audio_clock_freq(struct i2c_client *client, u32 freq)
 	if (state->apll)
 		acc |= 0x08;
 
-	saa7115_write(client, CLOCK_RATIO_AMXCLK_TO_ASCLK, 0x03);
-	saa7115_write(client, CLOCK_RATIO_ASCLK_TO_ALRCLK, 0x10);
-	saa7115_write(client, AUDIO_CLOCK_GENERATOR_BASIC_SETUP, acc);
-	saa7115_write(client, AUDIO_MASTER_CLOCK_CYCLES_PER_FIELD, acpf & 0xff);
-	saa7115_write(client, 0x31, (acpf >> 8) & 0xff);
-	saa7115_write(client, 0x32, (acpf >> 16) & 0x03);
-	saa7115_write(client, AUDIO_MASTER_CLOCK_NOMINAL_INC, acni & 0xff);
-	saa7115_write(client, 0x35, (acni >> 8) & 0xff);
-	saa7115_write(client, 0x36, (acni >> 16) & 0x3f);
+	saa7115_write(client, R_38_CLK_RATIO_AMXCLK_TO_ASCLK, 0x03);
+	saa7115_write(client, R_39_CLK_RATIO_ASCLK_TO_ALRCLK, 0x10);
+	saa7115_write(client, R_3A_AUD_CLK_GEN_BASIC_SETUP, acc);
+
+	saa7115_write(client, R_30_AUD_MAST_CLK_CYCLES_PER_FIELD, acpf & 0xff);
+	saa7115_write(client, R_30_AUD_MAST_CLK_CYCLES_PER_FIELD+1,
+							(acpf >> 8) & 0xff);
+	saa7115_write(client, R_30_AUD_MAST_CLK_CYCLES_PER_FIELD+2,
+							(acpf >> 16) & 0x03);
+
+	saa7115_write(client, R_34_AUD_MAST_CLK_NOMINAL_INC, acni & 0xff);
+	saa7115_write(client, R_34_AUD_MAST_CLK_NOMINAL_INC+1, (acni >> 8) & 0xff);
+	saa7115_write(client, R_34_AUD_MAST_CLK_NOMINAL_INC+2, (acni >> 16) & 0x3f);
 	state->audclk_freq = freq;
 	return 0;
 }
@@ -741,7 +745,7 @@ static int saa7115_set_v4lctrl(struct i2c_client *client, struct v4l2_control *c
 		}
 
 		state->bright = ctrl->value;
-		saa7115_write(client, LUMA_BRIGHTNESS_CNTL, state->bright);
+		saa7115_write(client, R_0A_LUMA_BRIGHT_CNTL, state->bright);
 		break;
 
 	case V4L2_CID_CONTRAST:
@@ -751,7 +755,7 @@ static int saa7115_set_v4lctrl(struct i2c_client *client, struct v4l2_control *c
 		}
 
 		state->contrast = ctrl->value;
-		saa7115_write(client, LUMA_CONTRAST_CNTL, state->contrast);
+		saa7115_write(client, R_0B_LUMA_CONTRAST_CNTL, state->contrast);
 		break;
 
 	case V4L2_CID_SATURATION:
@@ -761,7 +765,7 @@ static int saa7115_set_v4lctrl(struct i2c_client *client, struct v4l2_control *c
 		}
 
 		state->sat = ctrl->value;
-		saa7115_write(client, CHROMA_SATURATION_CNTL, state->sat);
+		saa7115_write(client, R_0C_CHROMA_SAT_CNTL, state->sat);
 		break;
 
 	case V4L2_CID_HUE:
@@ -771,7 +775,7 @@ static int saa7115_set_v4lctrl(struct i2c_client *client, struct v4l2_control *c
 		}
 
 		state->hue = ctrl->value;
-		saa7115_write(client, CHROMA_HUE_CNTL, state->hue);
+		saa7115_write(client, R_0D_CHROMA_HUE_CNTL, state->hue);
 		break;
 
 	default:
@@ -808,7 +812,7 @@ static int saa7115_get_v4lctrl(struct i2c_client *client, struct v4l2_control *c
 static void saa7115_set_v4lstd(struct i2c_client *client, v4l2_std_id std)
 {
 	struct saa7115_state *state = i2c_get_clientdata(client);
-	int taskb = saa7115_read(client, GLOBAL_CNTL_1) & 0x10;
+	int taskb = saa7115_read(client, R_80_GLOBAL_CNTL_1) & 0x10;
 
 	/* Prevent unnecessary standard changes. During a standard
 	   change the I-Port is temporarily disabled. Any devices
@@ -839,7 +843,7 @@ static void saa7115_set_v4lstd(struct i2c_client *client, v4l2_std_id std)
 	100 reserved                    NTSC-Japan (3.58MHz)
 	*/
 	if (state->ident == V4L2_IDENT_SAA7113) {
-		u8 reg = saa7115_read(client, CHROMA_CNTL_1) & 0x8f;
+		u8 reg = saa7115_read(client, R_0E_CHROMA_CNTL_1) & 0x8f;
 
 		if (std == V4L2_STD_PAL_M) {
 			reg |= 0x30;
@@ -850,7 +854,7 @@ static void saa7115_set_v4lstd(struct i2c_client *client, v4l2_std_id std)
 		} else if (std == V4L2_STD_NTSC_M_JP) {
 			reg |= 0x40;
 		}
-		saa7115_write(client, CHROMA_CNTL_1, reg);
+		saa7115_write(client, R_0E_CHROMA_CNTL_1, reg);
 	}
 
 
@@ -882,7 +886,7 @@ static void saa7115_log_status(struct i2c_client *client)
 	v4l_info(client, "Audio frequency: %d Hz\n", state->audclk_freq);
 	if (state->ident != V4L2_IDENT_SAA7115) {
 		/* status for the saa7114 */
-		reg1f = saa7115_read(client, STATUS_BYTE_2_VIDEO_DECODER);
+		reg1f = saa7115_read(client, R_1F_STATUS_BYTE_2_VD_DEC);
 		signalOk = (reg1f & 0xc1) == 0x81;
 		v4l_info(client, "Video signal:    %s\n", signalOk ? "ok" : "bad");
 		v4l_info(client, "Frequency:       %s\n", (reg1f & 0x20) ? "60 Hz" : "50 Hz");
@@ -890,8 +894,8 @@ static void saa7115_log_status(struct i2c_client *client)
 	}
 
 	/* status for the saa7115 */
-	reg1e = saa7115_read(client, STATUS_BYTE_1_VIDEO_DECODER);
-	reg1f = saa7115_read(client, STATUS_BYTE_2_VIDEO_DECODER);
+	reg1e = saa7115_read(client, R_1E_STATUS_BYTE_1_VD_DEC);
+	reg1f = saa7115_read(client, R_1F_STATUS_BYTE_2_VD_DEC);
 
 	signalOk = (reg1f & 0xc1) == 0x81 && (reg1e & 0xc0) == 0x80;
 	vcr = !(reg1f & 0x10);
@@ -987,7 +991,7 @@ static void saa7115_set_lcr(struct i2c_client *client, struct v4l2_sliced_vbi_fo
 
 	/* write the lcr registers */
 	for (i = 2; i <= 23; i++) {
-		saa7115_write(client, i - 2 + LCR, lcr[i]);
+		saa7115_write(client, i - 2 + R_41_LCR_BASE, lcr[i]);
 	}
 
 	/* enable/disable raw VBI capturing */
@@ -1012,10 +1016,10 @@ static int saa7115_get_v4lfmt(struct i2c_client *client, struct v4l2_format *fmt
 		return -EINVAL;
 	memset(sliced, 0, sizeof(*sliced));
 	/* done if using raw VBI */
-	if (saa7115_read(client, GLOBAL_CNTL_1) & 0x10)
+	if (saa7115_read(client, R_80_GLOBAL_CNTL_1) & 0x10)
 		return 0;
 	for (i = 2; i <= 23; i++) {
-		u8 v = saa7115_read(client, i - 2 + LCR);
+		u8 v = saa7115_read(client, i - 2 + R_41_LCR_BASE);
 
 		sliced->service_lines[0][i] = lcr2vbi[v >> 4];
 		sliced->service_lines[1][i] = lcr2vbi[v & 0xf];
@@ -1053,14 +1057,14 @@ static int saa7115_set_v4lfmt(struct i2c_client *client, struct v4l2_format *fmt
 	/* probably have a valid size, let's set it */
 	/* Set output width/height */
 	/* width */
-	saa7115_write(client, B_HORIZ_OUTPUT_WINDOW_LENGTH,
+	saa7115_write(client, R_CC_B_HORIZ_OUTPUT_WINDOW_LENGTH,
 				(u8) (pix->width & 0xff));
-	saa7115_write(client, B_HORIZ_OUTPUT_WINDOW_LENGTH_MSB,
+	saa7115_write(client, R_CD_B_HORIZ_OUTPUT_WINDOW_LENGTH_MSB,
 				(u8) ((pix->width >> 8) & 0xff));
 	/* height */
-	saa7115_write(client, B_VERT_OUTPUT_WINDOW_LENGTH,
+	saa7115_write(client, R_CE_B_VERT_OUTPUT_WINDOW_LENGTH,
 				(u8) (pix->height & 0xff));
-	saa7115_write(client, B_VERT_OUTPUT_WINDOW_LENGTH_MSB,
+	saa7115_write(client, R_CF_B_VERT_OUTPUT_WINDOW_LENGTH_MSB,
 				(u8) ((pix->height >> 8) & 0xff));
 
 	/* Scaling settings */
@@ -1075,19 +1079,19 @@ static int saa7115_set_v4lfmt(struct i2c_client *client, struct v4l2_format *fmt
 		v4l_dbg(1, debug, client, "Hpsc: 0x%05x, Hfsc: 0x%05x\n", HPSC, HFSC);
 		/* FIXME hardcodes to "Task B"
 		 * write H prescaler integer */
-		saa7115_write(client, B_HORIZ_PRESCALING,
+		saa7115_write(client, R_D0_B_HORIZ_PRESCALING,
 					(u8) (HPSC & 0x3f));
 
 		/* write H fine-scaling (luminance) */
-		saa7115_write(client, B_HORIZ_LUMA_SCALING_INC,
+		saa7115_write(client, R_D8_B_HORIZ_LUMA_SCALING_INC,
 					(u8) (HFSC & 0xff));
-		saa7115_write(client, B_HORIZ_LUMA_SCALING_INC_MSB,
+		saa7115_write(client, R_D9_B_HORIZ_LUMA_SCALING_INC_MSB,
 					(u8) ((HFSC >> 8) & 0xff));
 		/* write H fine-scaling (chrominance)
 		 * must be lum/2, so i'll just bitshift :) */
-		saa7115_write(client, B_HORIZ_CHROMA_SCALING,
+		saa7115_write(client, R_DC_B_HORIZ_CHROMA_SCALING,
 					(u8) ((HFSC >> 1) & 0xff));
-		saa7115_write(client, B_HORIZ_CHROMA_SCALING_MSB,
+		saa7115_write(client, R_DD_B_HORIZ_CHROMA_SCALING_MSB,
 					(u8) ((HFSC >> 9) & 0xff));
 	} else {
 		if (is_50hz) {
@@ -1106,20 +1110,20 @@ static int saa7115_set_v4lfmt(struct i2c_client *client, struct v4l2_format *fmt
 		v4l_dbg(1, debug, client, "Vsrc: %d, Vscy: 0x%05x\n", Vsrc, VSCY);
 
 		/* Correct Contrast and Luminance */
-		saa7115_write(client, B_LUMA_CONTRAST_CNTL,
+		saa7115_write(client, R_D5_B_LUMA_CONTRAST_CNTL,
 					(u8) (64 * 1024 / VSCY));
-		saa7115_write(client, B_CHROMA_SATURATION_CNTL,
+		saa7115_write(client, R_D6_B_CHROMA_SATURATION_CNTL,
 					(u8) (64 * 1024 / VSCY));
 
 		/* write V fine-scaling (luminance) */
-		saa7115_write(client, B_VERT_LUMA_SCALING_INC,
+		saa7115_write(client, R_E0_B_VERT_LUMA_SCALING_INC,
 					(u8) (VSCY & 0xff));
-		saa7115_write(client, B_VERT_LUMA_SCALING_INC_MSB,
+		saa7115_write(client, R_E1_B_VERT_LUMA_SCALING_INC_MSB,
 					(u8) ((VSCY >> 8) & 0xff));
 		/* write V fine-scaling (chrominance) */
-		saa7115_write(client, B_VERT_CHROMA_SCALING_INC,
+		saa7115_write(client, R_E2_B_VERT_CHROMA_SCALING_INC,
 					(u8) (VSCY & 0xff));
-		saa7115_write(client, B_VERT_CHROMA_SCALING_INC_MSB,
+		saa7115_write(client, R_E3_B_VERT_CHROMA_SCALING_INC_MSB,
 					(u8) ((VSCY >> 8) & 0xff));
 	} else {
 		if (is_50hz) {
@@ -1139,7 +1143,7 @@ static int saa7115_set_v4lfmt(struct i2c_client *client, struct v4l2_format *fmt
    The format is described in the saa7115 datasheet in Tables 25 and 26
    and in Figure 33.
    The current implementation uses SAV/EAV codes and not the ancillary data
-   headers. The vbi->p pointer points to the SDID byte right after the SAV
+   headers. The vbi->p pointer points to the R_5E_SDID byte right after the SAV
    code. */
 static void saa7115_decode_vbi_line(struct i2c_client *client,
 				    struct v4l2_decode_vbi_line *vbi)
@@ -1229,7 +1233,7 @@ static int saa7115_command(struct i2c_client *client, unsigned int cmd, void *ar
 
 		if (state->radio)
 			break;
-		status = saa7115_read(client, STATUS_BYTE_2_VIDEO_DECODER);
+		status = saa7115_read(client, R_1F_STATUS_BYTE_2_VD_DEC);
 
 		v4l_dbg(1, debug, client, "status: 0x%02x\n", status);
 		vt->signal = ((status & (1 << 6)) == 0) ? 0xffff : 0x0;
@@ -1303,13 +1307,13 @@ static int saa7115_command(struct i2c_client *client, unsigned int cmd, void *ar
 		state->input = route->input;
 
 		/* select mode */
-		saa7115_write(client, ANALOG_INPUT_CNTL_1,
-			      (saa7115_read(client, ANALOG_INPUT_CNTL_1) & 0xf0) |
+		saa7115_write(client, R_02_INPUT_CNTL_1,
+			      (saa7115_read(client, R_02_INPUT_CNTL_1) & 0xf0) |
 			       state->input);
 
 		/* bypass chrominance trap for S-Video modes */
-		saa7115_write(client, LUMA_CNTL,
-			      (saa7115_read(client, LUMA_CNTL) & 0x7f) |
+		saa7115_write(client, R_09_LUMA_CNTL,
+			      (saa7115_read(client, R_09_LUMA_CNTL) & 0x7f) |
 			       (state->input >= SAA7115_SVIDEO0 ? 0x80 : 0x0));
 		break;
 	}
@@ -1322,7 +1326,7 @@ static int saa7115_command(struct i2c_client *client, unsigned int cmd, void *ar
 		if (state->enable != (cmd == VIDIOC_STREAMON)) {
 			state->enable = (cmd == VIDIOC_STREAMON);
 			saa7115_write(client,
-				I_PORT_I_O_ENABLE_OUTPUT_CLOCK_AND_GATED,
+				R_87_I_PORT_I_O_ENA_OUT_CLK_AND_GATED,
 				state->enable);
 		}
 		break;
@@ -1518,7 +1522,7 @@ static int saa7115_attach(struct i2c_adapter *adapter, int address, int kind)
 	i2c_attach_client(client);
 
 	v4l_dbg(1, debug, client, "status: (1E) 0x%02x, (1F) 0x%02x\n",
-		saa7115_read(client, STATUS_BYTE_1_VIDEO_DECODER), saa7115_read(client, STATUS_BYTE_2_VIDEO_DECODER));
+		saa7115_read(client, R_1E_STATUS_BYTE_1_VD_DEC), saa7115_read(client, R_1F_STATUS_BYTE_2_VD_DEC));
 
 #if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0)
 	MOD_INC_USE_COUNT;
diff --git a/linux/drivers/media/video/saa711x_regs.h b/linux/drivers/media/video/saa711x_regs.h
index 5bf6b6d74..713e9056e 100644
--- a/linux/drivers/media/video/saa711x_regs.h
+++ b/linux/drivers/media/video/saa711x_regs.h
@@ -13,193 +13,193 @@
  * GNU General Public License for more details.
  */
 
-#define CHIP_VERSION                             0x00
+#define R_00_CHIP_VERSION                             0x00
 /* Video Decoder */
 	/* Video Decoder - Frontend part */
-#define INC_DELAY                                0x01
-#define ANALOG_INPUT_CNTL_1                      0x02
-#define ANALOG_INPUT_CNTL_2                      0x03
-#define ANALOG_INPUT_CNTL_3                      0x04
-#define ANALOG_INPUT_CNTL_4                      0x05
+#define R_01_INC_DELAY                                0x01
+#define R_02_INPUT_CNTL_1                             0x02
+#define R_03_INPUT_CNTL_2                             0x03
+#define R_04_INPUT_CNTL_3                             0x04
+#define R_05_INPUT_CNTL_4                             0x05
 	/* Video Decoder - Decoder part */
-#define HORIZ_SYNC_START                         0x06
-#define HORIZ_SYNC_STOP                          0x07
-#define SYNC_CNTL                                0x08
-#define LUMA_CNTL                                0x09
-#define LUMA_BRIGHTNESS_CNTL                     0x0a
-#define LUMA_CONTRAST_CNTL                       0x0b
-#define CHROMA_SATURATION_CNTL                   0x0c
-#define CHROMA_HUE_CNTL                          0x0d
-#define CHROMA_CNTL_1                            0x0e
-#define CHROMA_GAIN_CNTL                         0x0f
-#define CHROMA_CNTL_2                            0x10
-#define MODE_DELAY_CNTL                          0x11
-#define RT_SIGNAL_CNTL                           0x12
-#define RT_X_PORT_OUTPUT_CNTL                    0x13
-#define ANALOG_ADC_COMPAT_CNTL                   0x14
-#define VGATE_START_FID_CHANGE                   0x15
-#define VGATE_STOP                               0x16
-#define MISC_VGATE_CONF_AND_MSBS                 0x17
-#define RAW_DATA_GAIN_CNTL                       0x18
-#define RAW_DATA_OFF_CNTL                        0x19
-#define COLOR_KILLER_LEVEL_CNTL                  0x1a
-#define MISC_TVVCRDET                            0x1b
-#define ENHANCED_COMB_CTRL1                      0x1c
-#define ENHANCED_COMB_CTRL2                      0x1d
-#define STATUS_BYTE_1_VIDEO_DECODER              0x1e
-#define STATUS_BYTE_2_VIDEO_DECODER              0x1f
+#define R_06_H_SYNC_START                             0x06
+#define R_07_H_SYNC_STOP                              0x07
+#define R_08_SYNC_CNTL                                0x08
+#define R_09_LUMA_CNTL                                0x09
+#define R_0A_LUMA_BRIGHT_CNTL                         0x0a
+#define R_0B_LUMA_CONTRAST_CNTL                       0x0b
+#define R_0C_CHROMA_SAT_CNTL                          0x0c
+#define R_0D_CHROMA_HUE_CNTL                          0x0d
+#define R_0E_CHROMA_CNTL_1                            0x0e
+#define R_0F_CHROMA_GAIN_CNTL                         0x0f
+#define R_10_CHROMA_CNTL_2                            0x10
+#define R_11_MODE_DELAY_CNTL                          0x11
+#define R_12_RT_SIGNAL_CNTL                           0x12
+#define R_13_RT_X_PORT_OUT_CNTL                       0x13
+#define R_14_ANAL_ADC_COMPAT_CNTL                     0x14
+#define R_15_VGATE_START_FID_CHG                      0x15
+#define R_16_VGATE_STOP                               0x16
+#define R_17_MISC_VGATE_CONF_AND_MSB                  0x17
+#define R_18_RAW_DATA_GAIN_CNTL                       0x18
+#define R_19_RAW_DATA_OFF_CNTL                        0x19
+#define R_1A_COLOR_KILL_LVL_CNTL                      0x1a
+#define R_1B_MISC_TVVCRDET                            0x1b
+#define R_1C_ENHAN_COMB_CTRL1                         0x1c
+#define R_1D_ENHAN_COMB_CTRL2                         0x1d
+#define R_1E_STATUS_BYTE_1_VD_DEC                     0x1e
+#define R_1F_STATUS_BYTE_2_VD_DEC                     0x1f
 
 /* Component processing and interrupt masking part */
-#define ANALOG_INPUT_CNTL_5                      0x23
-#define ANALOG_INPUT_CNTL_6                      0x24
-#define ANALOG_INPUT_CNTL_7                      0x25
-#define COMP_DELAY                               0x29
-#define COMP_BRIGHTNESS_CNTL                     0x2a
-#define COMP_CONTRAST_CNTL                       0x2b
-#define COMP_SATURATION_CNTL                     0x2c
-#define INTERRUPT_MASK_1                         0x2d
-#define INTERRUPT_MASK_2                         0x2e
-#define INTERRUPT_MASK_3                         0x2f
+#define R_23_INPUT_CNTL_5                             0x23
+#define R_24_INPUT_CNTL_6                             0x24
+#define R_25_INPUT_CNTL_7                             0x25
+#define R_29_COMP_DELAY                               0x29
+#define R_2A_COMP_BRIGHT_CNTL                         0x2a
+#define R_2B_COMP_CONTRAST_CNTL                       0x2b
+#define R_2C_COMP_SAT_CNTL                            0x2c
+#define R_2D_INTERRUPT_MASK_1                         0x2d
+#define R_2E_INTERRUPT_MASK_2                         0x2e
+#define R_2F_INTERRUPT_MASK_3                         0x2f
 
 /* Audio clock generator part */
-#define AUDIO_MASTER_CLOCK_CYCLES_PER_FIELD      0x30
-#define AUDIO_MASTER_CLOCK_NOMINAL_INC           0x34
-#define CLOCK_RATIO_AMXCLK_TO_ASCLK              0x38
-#define CLOCK_RATIO_ASCLK_TO_ALRCLK              0x39
-#define AUDIO_CLOCK_GENERATOR_BASIC_SETUP        0x3a
+#define R_30_AUD_MAST_CLK_CYCLES_PER_FIELD            0x30
+#define R_34_AUD_MAST_CLK_NOMINAL_INC                 0x34
+#define R_38_CLK_RATIO_AMXCLK_TO_ASCLK                0x38
+#define R_39_CLK_RATIO_ASCLK_TO_ALRCLK                0x39
+#define R_3A_AUD_CLK_GEN_BASIC_SETUP                  0x3a
 
 /* General purpose VBI data slicer part */
-#define SLICER_CNTL_1                            0x40
-#define LCR                                      0x41
-#define PROGRAMMABLE_FRAMING_CODE                0x58
-#define HORIZ_OFF_FOR_SLICER                     0x59
-#define VERT_OFF_FOR_SLICER                      0x5a
-#define FIELD_OFF_AND_MSB_FOR_HORIZ_AND_VERT_OFF 0x5b
-#define DID                                      0x5d
-#define SDID                                     0x5e
-#define SLICER_STATUS_BYTE_0                     0x60
-#define SLICER_STATUS_BYTE_1                     0x61
-#define SLICER_STATUS_BYTE_2                     0x62
+#define R_40_SLICER_CNTL_1                            0x40
+#define R_41_LCR_BASE                                 0x41
+#define R_58_PROGRAM_FRAMING_CODE                     0x58
+#define R_59_H_OFF_FOR_SLICER                         0x59
+#define R_5A_V_OFF_FOR_SLICER                         0x5a
+#define R_5B_FLD_OFF_AND_MSB_FOR_H_AND_V_OFF          0x5b
+#define R_5D_DID                                      0x5d
+#define R_5E_SDID                                     0x5e
+#define R_60_SLICER_STATUS_BYTE_0                     0x60
+#define R_61_SLICER_STATUS_BYTE_1                     0x61
+#define R_62_SLICER_STATUS_BYTE_2                     0x62
 
 /* X port, I port and the scaler part */
 	/* Task independent global settings */
-#define GLOBAL_CNTL_1                            0x80
-#define VERT_SYNC_FLD_ID_SRC_SEL_AND_RETIMED_V_F 0x81
-#define X_PORT_I_O_ENABLE_AND_OUTPUT_CLOCK       0x83
-#define I_PORT_SIGNAL_DEFINITIONS                0x84
-#define I_PORT_SIGNAL_POLARITIES                 0x85
-#define I_PORT_FIFO_FLAG_CNTL_AND_ARBITRATION    0x86
-#define I_PORT_I_O_ENABLE_OUTPUT_CLOCK_AND_GATED 0x87
-#define POWER_SAVE_ADC_PORT_CNTL                 0x88
-#define STATUS_INFORMATION_SCALER_PART           0x8f
+#define R_80_GLOBAL_CNTL_1                            0x80
+#define R_81_V_SYNC_FLD_ID_SRC_SEL_AND_RETIMED_V_F    0x81
+#define R_83_X_PORT_I_O_ENA_AND_OUT_CLK               0x83
+#define R_84_I_PORT_SIGNAL_DEF                        0x84
+#define R_85_I_PORT_SIGNAL_POLAR                      0x85
+#define R_86_I_PORT_FIFO_FLAG_CNTL_AND_ARBIT          0x86
+#define R_87_I_PORT_I_O_ENA_OUT_CLK_AND_GATED         0x87
+#define R_88_POWER_SAVE_ADC_PORT_CNTL                 0x88
+#define R_8F_STATUS_INFO_SCALER                       0x8f
 	/* Task A definition */
 		/* Basic settings and acquisition window definition */
-#define A_TASK_HANDLING_CNTL                     0x90
-#define A_X_PORT_FORMATS_AND_CONF                0x91
-#define A_X_PORT_INPUT_REFERENCE_SIGNAL          0x92
-#define A_I_PORT_OUTPUT_FORMATS_AND_CONF         0x93
-#define A_HORIZ_INPUT_WINDOW_START               0x94
-#define A_HORIZ_INPUT_WINDOW_START_MSB           0x95
-#define A_HORIZ_INPUT_WINDOW_LENGTH              0x96
-#define A_HORIZ_INPUT_WINDOW_LENGTH_MSB          0x97
-#define A_VERT_INPUT_WINDOW_START                0x98
-#define A_VERT_INPUT_WINDOW_START_MSB            0x99
-#define A_VERT_INPUT_WINDOW_LENGTH               0x9a
-#define A_VERT_INPUT_WINDOW_LENGTH_MSB           0x9b
-#define A_HORIZ_OUTPUT_WINDOW_LENGTH             0x9c
-#define A_HORIZ_OUTPUT_WINDOW_LENGTH_MSB         0x9d
-#define A_VERT_OUTPUT_WINDOW_LENGTH              0x9e
-#define A_VERT_OUTPUT_WINDOW_LENGTH_MSB          0x9f
+#define R_90_A_TASK_HANDLING_CNTL                     0x90
+#define R_91_A_X_PORT_FORMATS_AND_CONF                0x91
+#define R_92_A_X_PORT_INPUT_REFERENCE_SIGNAL          0x92
+#define R_93_A_I_PORT_OUTPUT_FORMATS_AND_CONF         0x93
+#define R_94_A_HORIZ_INPUT_WINDOW_START               0x94
+#define R_95_A_HORIZ_INPUT_WINDOW_START_MSB           0x95
+#define R_96_A_HORIZ_INPUT_WINDOW_LENGTH              0x96
+#define R_97_A_HORIZ_INPUT_WINDOW_LENGTH_MSB          0x97
+#define R_98_A_VERT_INPUT_WINDOW_START                0x98
+#define R_99_A_VERT_INPUT_WINDOW_START_MSB            0x99
+#define R_9A_A_VERT_INPUT_WINDOW_LENGTH               0x9a
+#define R_9B_A_VERT_INPUT_WINDOW_LENGTH_MSB           0x9b
+#define R_9C_A_HORIZ_OUTPUT_WINDOW_LENGTH             0x9c
+#define R_9D_A_HORIZ_OUTPUT_WINDOW_LENGTH_MSB         0x9d
+#define R_9E_A_VERT_OUTPUT_WINDOW_LENGTH              0x9e
+#define R_9F_A_VERT_OUTPUT_WINDOW_LENGTH_MSB          0x9f
 		/* FIR filtering and prescaling */
-#define A_HORIZ_PRESCALING                       0xa0
-#define A_ACCUMULATION_LENGTH                    0xa1
-#define A_PRESCALER_DC_GAIN_AND_FIR_PREFILTER    0xa2
-#define A_LUMA_BRIGHTNESS_CNTL                   0xa4
-#define A_LUMA_CONTRAST_CNTL                     0xa5
-#define A_CHROMA_SATURATION_CNTL                 0xa6
+#define R_A0_A_HORIZ_PRESCALING                       0xa0
+#define R_A1_A_ACCUMULATION_LENGTH                    0xa1
+#define R_A2_A_PRESCALER_DC_GAIN_AND_FIR_PREFILTER    0xa2
+#define R_A4_A_LUMA_BRIGHTNESS_CNTL                   0xa4
+#define R_A5_A_LUMA_CONTRAST_CNTL                     0xa5
+#define R_A6_A_CHROMA_SATURATION_CNTL                 0xa6
 		/* Horizontal phase scaling */
-#define A_HORIZ_LUMA_SCALING_INC                 0xa8
-#define A_HORIZ_LUMA_SCALING_INC_MSB             0xa9
-#define A_HORIZ_LUMA_PHASE_OFF                   0xaa
-#define A_HORIZ_CHROMA_SCALING_INC               0xac
-#define A_HORIZ_CHROMA_SCALING_INC_MSB           0xad
-#define A_HORIZ_CHROMA_PHASE_OFF                 0xae
-#define A_HORIZ_CHROMA_PHASE_OFF_MSB             0xaf
+#define R_A8_A_HORIZ_LUMA_SCALING_INC                 0xa8
+#define R_A9_A_HORIZ_LUMA_SCALING_INC_MSB             0xa9
+#define R_AA_A_HORIZ_LUMA_PHASE_OFF                   0xaa
+#define R_AC_A_HORIZ_CHROMA_SCALING_INC               0xac
+#define R_AD_A_HORIZ_CHROMA_SCALING_INC_MSB           0xad
+#define R_AE_A_HORIZ_CHROMA_PHASE_OFF                 0xae
+#define R_AF_A_HORIZ_CHROMA_PHASE_OFF_MSB             0xaf
 		/* Vertical scaling */
-#define A_VERT_LUMA_SCALING_INC                  0xb0
-#define A_VERT_LUMA_SCALING_INC_MSB              0xb1
-#define A_VERT_CHROMA_SCALING_INC                0xb2
-#define A_VERT_CHROMA_SCALING_INC_MSB            0xb3
-#define A_VERT_SCALING_MODE_CNTL                 0xb4
-#define A_VERT_CHROMA_PHASE_OFF_00               0xb8
-#define A_VERT_CHROMA_PHASE_OFF_01               0xb9
-#define A_VERT_CHROMA_PHASE_OFF_10               0xba
-#define A_VERT_CHROMA_PHASE_OFF_11               0xbb
-#define A_VERT_LUMA_PHASE_OFF_00                 0xbc
-#define A_VERT_LUMA_PHASE_OFF_01                 0xbd
-#define A_VERT_LUMA_PHASE_OFF_10                 0xbe
-#define A_VERT_LUMA_PHASE_OFF_11                 0xbf
+#define R_B0_A_VERT_LUMA_SCALING_INC                  0xb0
+#define R_B1_A_VERT_LUMA_SCALING_INC_MSB              0xb1
+#define R_B2_A_VERT_CHROMA_SCALING_INC                0xb2
+#define R_B3_A_VERT_CHROMA_SCALING_INC_MSB            0xb3
+#define R_B4_A_VERT_SCALING_MODE_CNTL                 0xb4
+#define R_B8_A_VERT_CHROMA_PHASE_OFF_00               0xb8
+#define R_B9_A_VERT_CHROMA_PHASE_OFF_01               0xb9
+#define R_BA_A_VERT_CHROMA_PHASE_OFF_10               0xba
+#define R_BB_A_VERT_CHROMA_PHASE_OFF_11               0xbb
+#define R_BC_A_VERT_LUMA_PHASE_OFF_00                 0xbc
+#define R_BD_A_VERT_LUMA_PHASE_OFF_01                 0xbd
+#define R_BE_A_VERT_LUMA_PHASE_OFF_10                 0xbe
+#define R_BF_A_VERT_LUMA_PHASE_OFF_11                 0xbf
 	/* Task B definition */
 		/* Basic settings and acquisition window definition */
-#define B_TASK_HANDLING_CNTL                     0xc0
-#define B_X_PORT_FORMATS_AND_CONF                0xc1
-#define B_INPUT_REFERENCE_SIGNAL_DEFINITION      0xc2
-#define B_I_PORT_FORMATS_AND_CONF                0xc3
-#define B_HORIZ_INPUT_WINDOW_START               0xc4
-#define B_HORIZ_INPUT_WINDOW_START_MSB           0xc5
-#define B_HORIZ_INPUT_WINDOW_LENGTH              0xc6
-#define B_HORIZ_INPUT_WINDOW_LENGTH_MSB          0xc7
-#define B_VERT_INPUT_WINDOW_START                0xc8
-#define B_VERT_INPUT_WINDOW_START_MSB            0xc9
-#define B_VERT_INPUT_WINDOW_LENGTH               0xca
-#define B_VERT_INPUT_WINDOW_LENGTH_MSB           0xcb
-#define B_HORIZ_OUTPUT_WINDOW_LENGTH             0xcc
-#define B_HORIZ_OUTPUT_WINDOW_LENGTH_MSB         0xcd
-#define B_VERT_OUTPUT_WINDOW_LENGTH              0xce
-#define B_VERT_OUTPUT_WINDOW_LENGTH_MSB          0xcf
+#define R_C0_B_TASK_HANDLING_CNTL                     0xc0
+#define R_C1_B_X_PORT_FORMATS_AND_CONF                0xc1
+#define R_C2_B_INPUT_REFERENCE_SIGNAL_DEFINITION      0xc2
+#define R_C3_B_I_PORT_FORMATS_AND_CONF                0xc3
+#define R_C4_B_HORIZ_INPUT_WINDOW_START               0xc4
+#define R_C5_B_HORIZ_INPUT_WINDOW_START_MSB           0xc5
+#define R_C6_B_HORIZ_INPUT_WINDOW_LENGTH              0xc6
+#define R_C7_B_HORIZ_INPUT_WINDOW_LENGTH_MSB          0xc7
+#define R_C8_B_VERT_INPUT_WINDOW_START                0xc8
+#define R_C9_B_VERT_INPUT_WINDOW_START_MSB            0xc9
+#define R_CA_B_VERT_INPUT_WINDOW_LENGTH               0xca
+#define R_CB_B_VERT_INPUT_WINDOW_LENGTH_MSB           0xcb
+#define R_CC_B_HORIZ_OUTPUT_WINDOW_LENGTH             0xcc
+#define R_CD_B_HORIZ_OUTPUT_WINDOW_LENGTH_MSB         0xcd
+#define R_CE_B_VERT_OUTPUT_WINDOW_LENGTH              0xce
+#define R_CF_B_VERT_OUTPUT_WINDOW_LENGTH_MSB          0xcf
 		/* FIR filtering and prescaling */
-#define B_HORIZ_PRESCALING                       0xd0
-#define B_ACCUMULATION_LENGTH                    0xd1
-#define B_PRESCALER_DC_GAIN_AND_FIR_PREFILTER    0xd2
-#define B_LUMA_BRIGHTNESS_CNTL                   0xd4
-#define B_LUMA_CONTRAST_CNTL                     0xd5
-#define B_CHROMA_SATURATION_CNTL                 0xd6
+#define R_D0_B_HORIZ_PRESCALING                       0xd0
+#define R_D1_B_ACCUMULATION_LENGTH                    0xd1
+#define R_D2_B_PRESCALER_DC_GAIN_AND_FIR_PREFILTER    0xd2
+#define R_D4_B_LUMA_BRIGHTNESS_CNTL                   0xd4
+#define R_D5_B_LUMA_CONTRAST_CNTL                     0xd5
+#define R_D6_B_CHROMA_SATURATION_CNTL                 0xd6
 		/* Horizontal phase scaling */
-#define B_HORIZ_LUMA_SCALING_INC                 0xd8
-#define B_HORIZ_LUMA_SCALING_INC_MSB             0xd9
-#define B_HORIZ_LUMA_PHASE_OFF                   0xda
-#define B_HORIZ_CHROMA_SCALING                   0xdc
-#define B_HORIZ_CHROMA_SCALING_MSB               0xdd
-#define B_HORIZ_PHASE_OFFSET_CRHOMA              0xde
+#define R_D8_B_HORIZ_LUMA_SCALING_INC                 0xd8
+#define R_D9_B_HORIZ_LUMA_SCALING_INC_MSB             0xd9
+#define R_DA_B_HORIZ_LUMA_PHASE_OFF                   0xda
+#define R_DC_B_HORIZ_CHROMA_SCALING                   0xdc
+#define R_DD_B_HORIZ_CHROMA_SCALING_MSB               0xdd
+#define R_DE_B_HORIZ_PHASE_OFFSET_CRHOMA              0xde
 		/* Vertical scaling */
-#define B_VERT_LUMA_SCALING_INC                  0xe0
-#define B_VERT_LUMA_SCALING_INC_MSB              0xe1
-#define B_VERT_CHROMA_SCALING_INC                0xe2
-#define B_VERT_CHROMA_SCALING_INC_MSB            0xe3
-#define B_VERT_SCALING_MODE_CNTL                 0xe4
-#define B_VERT_CHROMA_PHASE_OFF_00               0xe8
-#define B_VERT_CHROMA_PHASE_OFF_01               0xe9
-#define B_VERT_CHROMA_PHASE_OFF_10               0xea
-#define B_VERT_CHROMA_PHASE_OFF_11               0xeb
-#define B_VERT_LUMA_PHASE_OFF_00                 0xec
-#define B_VERT_LUMA_PHASE_OFF_01                 0xed
-#define B_VERT_LUMA_PHASE_OFF_10                 0xee
-#define B_VERT_LUMA_PHASE_OFF_11                 0xef
+#define R_E0_B_VERT_LUMA_SCALING_INC                  0xe0
+#define R_E1_B_VERT_LUMA_SCALING_INC_MSB              0xe1
+#define R_E2_B_VERT_CHROMA_SCALING_INC                0xe2
+#define R_E3_B_VERT_CHROMA_SCALING_INC_MSB            0xe3
+#define R_E4_B_VERT_SCALING_MODE_CNTL                 0xe4
+#define R_E8_B_VERT_CHROMA_PHASE_OFF_00               0xe8
+#define R_E9_B_VERT_CHROMA_PHASE_OFF_01               0xe9
+#define R_EA_B_VERT_CHROMA_PHASE_OFF_10               0xea
+#define R_EB_B_VERT_CHROMA_PHASE_OFF_11               0xeb
+#define R_EC_B_VERT_LUMA_PHASE_OFF_00                 0xec
+#define R_ED_B_VERT_LUMA_PHASE_OFF_01                 0xed
+#define R_EE_B_VERT_LUMA_PHASE_OFF_10                 0xee
+#define R_EF_B_VERT_LUMA_PHASE_OFF_11                 0xef
 
 /* second PLL (PLL2) and Pulsegenerator Programming */
-#define LFCO_PER_LINE                            0xf0
-#define P_I_PARAM_SELECT                         0xf1
-#define NOMINAL_PLL2_DTO                         0xf2
-#define PLL_INCREMENT                            0xf3
-#define PLL2_STATUS                              0xf4
-#define PULSGEN_LINE_LENGTH                      0xf5
-#define PULSE_A_POS_LSB_AND_PULSEGEN_CONFIG      0xf6
-#define PULSE_A_POS_MSB                          0xf7
-#define PULSE_B_POS                              0xf8
-#define PULSE_B_POS_MSB                          0xf9
-#define PULSE_C_POS                              0xfa
-#define PULSE_C_POS_MSB                          0xfb
-#define S_PLL_MAX_PHASE_ERR_THRESH_NUM_LINES     0xff
+#define R_F0_LFCO_PER_LINE                            0xf0
+#define R_F1_P_I_PARAM_SELECT                         0xf1
+#define R_F2_NOMINAL_PLL2_DTO                         0xf2
+#define R_F3_PLL_INCREMENT                            0xf3
+#define R_F4_PLL2_STATUS                              0xf4
+#define R_F5_PULSGEN_LINE_LENGTH                      0xf5
+#define R_F6_PULSE_A_POS_LSB_AND_PULSEGEN_CONFIG      0xf6
+#define R_F7_PULSE_A_POS_MSB                          0xf7
+#define R_F8_PULSE_B_POS                              0xf8
+#define R_F9_PULSE_B_POS_MSB                          0xf9
+#define R_FA_PULSE_C_POS                              0xfa
+#define R_FB_PULSE_C_POS_MSB                          0xfb
+#define R_FF_S_PLL_MAX_PHASE_ERR_THRESH_NUM_LINES     0xff
 
 #if 0 /* keep */
 /* Those structs will be used in the future for debug purposes */
@@ -211,339 +211,339 @@ struct saa711x_reg_descr {
 
 struct saa711x_reg_descr saa711x_regs[] = {
 	/* REG COUNT NAME */
-	{CHIP_VERSION,1,
+	{R_00_CHIP_VERSION,1,
 	 "Chip version"},
 
-	/* Video Decoder: INC_DELAY to STATUS_BYTE_2_VIDEO_DECODER */
+	/* Video Decoder: R_01_INC_DELAY to R_1F_STATUS_BYTE_2_VD_DEC */
 
-	/* Video Decoder - Frontend part: INC_DELAY to ANALOG_INPUT_CNTL_4 */
-	{INC_DELAY,1,
+	/* Video Decoder - Frontend part: R_01_INC_DELAY to R_05_INPUT_CNTL_4 */
+	{R_01_INC_DELAY,1,
 	 "Increment delay"},
-	{ANALOG_INPUT_CNTL_1,1,
+	{R_02_INPUT_CNTL_1,1,
 	 "Analog input control 1"},
-	{ANALOG_INPUT_CNTL_2,1,
+	{R_03_INPUT_CNTL_2,1,
 	 "Analog input control 2"},
-	{ANALOG_INPUT_CNTL_3,1,
+	{R_04_INPUT_CNTL_3,1,
 	 "Analog input control 3"},
-	{ANALOG_INPUT_CNTL_4,1,
+	{R_05_INPUT_CNTL_4,1,
 	 "Analog input control 4"},
 
-	/* Video Decoder - Decoder part: HORIZ_SYNC_START to STATUS_BYTE_2_VIDEO_DECODER */
-	{HORIZ_SYNC_START,1,
+	/* Video Decoder - Decoder part: R_06_H_SYNC_START to R_1F_STATUS_BYTE_2_VD_DEC */
+	{R_06_H_SYNC_START,1,
 	 "Horizontal sync start"},
-	{HORIZ_SYNC_STOP,1,
+	{R_07_H_SYNC_STOP,1,
 	 "Horizontal sync stop"},
-	{SYNC_CNTL,1,
+	{R_08_SYNC_CNTL,1,
 	 "Sync control"},
-	{LUMA_CNTL,1,
+	{R_09_LUMA_CNTL,1,
 	 "Luminance control"},
-	{LUMA_BRIGHTNESS_CNTL,1,
+	{R_0A_LUMA_BRIGHT_CNTL,1,
 	 "Luminance brightness control"},
-	{LUMA_CONTRAST_CNTL,1,
+	{R_0B_LUMA_CONTRAST_CNTL,1,
 	 "Luminance contrast control"},
-	{CHROMA_SATURATION_CNTL,1,
+	{R_0C_CHROMA_SAT_CNTL,1,
 	 "Chrominance saturation control"},
-	{CHROMA_HUE_CNTL,1,
+	{R_0D_CHROMA_HUE_CNTL,1,
 	 "Chrominance hue control"},
-	{CHROMA_CNTL_1,1,
+	{R_0E_CHROMA_CNTL_1,1,
 	 "Chrominance control 1"},
-	{CHROMA_GAIN_CNTL,1,
+	{R_0F_CHROMA_GAIN_CNTL,1,
 	 "Chrominance gain control"},
-	{CHROMA_CNTL_2,1,
+	{R_10_CHROMA_CNTL_2,1,
 	 "Chrominance control 2"},
-	{MODE_DELAY_CNTL,1,
+	{R_11_MODE_DELAY_CNTL,1,
 	 "Mode/delay control"},
-	{RT_SIGNAL_CNTL,1,
+	{R_12_RT_SIGNAL_CNTL,1,
 	 "RT signal control"},
-	{RT_X_PORT_OUTPUT_CNTL,1,
+	{R_13_RT_X_PORT_OUT_CNTL,1,
 	 "RT/X port output control"},
-	{ANALOG_ADC_COMPAT_CNTL,1,
+	{R_14_ANAL_ADC_COMPAT_CNTL,1,
 	 "Analog/ADC/compatibility control"},
-	{VGATE_START_FID_CHANGE,  1,
+	{R_15_VGATE_START_FID_CHG,  1,
 	 "VGATE start FID change"},
-	{VGATE_STOP,1,
+	{R_16_VGATE_STOP,1,
 	 "VGATE stop"},
-	{MISC_VGATE_CONF_AND_MSBS,  1,
+	{R_17_MISC_VGATE_CONF_AND_MSB,  1,
 	 "Miscellaneous VGATE configuration and MSBs"},
-	{RAW_DATA_GAIN_CNTL,1,
+	{R_18_RAW_DATA_GAIN_CNTL,1,
 	 "Raw data gain control",},
-	{RAW_DATA_OFF_CNTL,1,
+	{R_19_RAW_DATA_OFF_CNTL,1,
 	 "Raw data offset control",},
-	{COLOR_KILLER_LEVEL_CNTL,1,
+	{R_1A_COLOR_KILL_LVL_CNTL,1,
 	 "Color Killer Level Control"},
-	{ MISC_TVVCRDET, 1,
+	{ R_1B_MISC_TVVCRDET, 1,
 	  "MISC /TVVCRDET"},
-	{ ENHANCED_COMB_CTRL1, 1,
+	{ R_1C_ENHAN_COMB_CTRL1, 1,
 	 "Enhanced comb ctrl1"},
-	{ ENHANCED_COMB_CTRL2, 1,
+	{ R_1D_ENHAN_COMB_CTRL2, 1,
 	 "Enhanced comb ctrl1"},
-	{STATUS_BYTE_1_VIDEO_DECODER,1,
+	{R_1E_STATUS_BYTE_1_VD_DEC,1,
 	 "Status byte 1 video decoder"},
-	{STATUS_BYTE_2_VIDEO_DECODER,1,
+	{R_1F_STATUS_BYTE_2_VD_DEC,1,
 	 "Status byte 2 video decoder"},
 
-	/* Component processing and interrupt masking part:  0x20h to INTERRUPT_MASK_3 */
+	/* Component processing and interrupt masking part:  0x20h to R_2F_INTERRUPT_MASK_3 */
 	/* 0x20 to 0x22 - Reserved */
-	{ANALOG_INPUT_CNTL_5,1,
+	{R_23_INPUT_CNTL_5,1,
 	 "Analog input control 5"},
-	{ANALOG_INPUT_CNTL_6,1,
+	{R_24_INPUT_CNTL_6,1,
 	 "Analog input control 6"},
-	{ANALOG_INPUT_CNTL_7,1,
+	{R_25_INPUT_CNTL_7,1,
 	 "Analog input control 7"},
 	/* 0x26 to 0x28 - Reserved */
-	{COMP_DELAY,1,
+	{R_29_COMP_DELAY,1,
 	 "Component delay"},
-	{COMP_BRIGHTNESS_CNTL,1,
+	{R_2A_COMP_BRIGHT_CNTL,1,
 	 "Component brightness control"},
-	{COMP_CONTRAST_CNTL,1,
+	{R_2B_COMP_CONTRAST_CNTL,1,
 	 "Component contrast control"},
-	{COMP_SATURATION_CNTL,1,
+	{R_2C_COMP_SAT_CNTL,1,
 	 "Component saturation control"},
-	{INTERRUPT_MASK_1,1,
+	{R_2D_INTERRUPT_MASK_1,1,
 	 "Interrupt mask 1"},
-	{INTERRUPT_MASK_2,1,
+	{R_2E_INTERRUPT_MASK_2,1,
 	 "Interrupt mask 2"},
-	{INTERRUPT_MASK_3,1,
+	{R_2F_INTERRUPT_MASK_3,1,
 	 "Interrupt mask 3"},
 
-	/* Audio clock generator part: AUDIO_MASTER_CLOCK_CYCLES_PER_FIELD to 0x3f */
-	{AUDIO_MASTER_CLOCK_CYCLES_PER_FIELD,3,
+	/* Audio clock generator part: R_30_AUD_MAST_CLK_CYCLES_PER_FIELD to 0x3f */
+	{R_30_AUD_MAST_CLK_CYCLES_PER_FIELD,3,
 	 "Audio master clock cycles per field"},
 	/* 0x33 - Reserved */
-	{AUDIO_MASTER_CLOCK_NOMINAL_INC,3,
+	{R_34_AUD_MAST_CLK_NOMINAL_INC,3,
 	 "Audio master clock nominal increment"},
 	/* 0x37 - Reserved */
-	{CLOCK_RATIO_AMXCLK_TO_ASCLK,1,
+	{R_38_CLK_RATIO_AMXCLK_TO_ASCLK,1,
 	 "Clock ratio AMXCLK to ASCLK"},
-	{CLOCK_RATIO_ASCLK_TO_ALRCLK,1,
+	{R_39_CLK_RATIO_ASCLK_TO_ALRCLK,1,
 	 "Clock ratio ASCLK to ALRCLK"},
-	{AUDIO_CLOCK_GENERATOR_BASIC_SETUP,1,
+	{R_3A_AUD_CLK_GEN_BASIC_SETUP,1,
 	 "Audio clock generator basic setup"},
 	/* 0x3b-0x3f - Reserved */
 
-	/* General purpose VBI data slicer part: SLICER_CNTL_1 to 0x7f */
-	{SLICER_CNTL_1,1,
+	/* General purpose VBI data slicer part: R_40_SLICER_CNTL_1 to 0x7f */
+	{R_40_SLICER_CNTL_1,1,
 	 "Slicer control 1"},
-	{LCR,23,
-	 "LCR"},
-	{PROGRAMMABLE_FRAMING_CODE,1,
+	{R_41_LCR,23,
+	 "R_41_LCR"},
+	{R_58_PROGRAM_FRAMING_CODE,1,
 	 "Programmable framing code"},
-	{HORIZ_OFF_FOR_SLICER,1,
+	{R_59_H_OFF_FOR_SLICER,1,
 	 "Horizontal offset for slicer"},
-	{VERT_OFF_FOR_SLICER,1,
+	{R_5A_V_OFF_FOR_SLICER,1,
 	 "Vertical offset for slicer"},
-	{FIELD_OFF_AND_MSB_FOR_HORIZ_AND_VERT_OFF,1,
+	{R_5B_FLD_OFF_AND_MSB_FOR_H_AND_V_OFF,1,
 	 "Field offset and MSBs for horizontal and vertical offset"},
-	{DID,1,
-	 "Header and data identification (DID)"},
-	{SDID,1,
-	 "Sliced data identification (SDID) code"},
-	{SLICER_STATUS_BYTE_0,1,
+	{R_5D_DID,1,
+	 "Header and data identification (R_5D_DID)"},
+	{R_5E_SDID,1,
+	 "Sliced data identification (R_5E_SDID) code"},
+	{R_60_SLICER_STATUS_BYTE_0,1,
 	 "Slicer status byte 0"},
-	{SLICER_STATUS_BYTE_1,1,
+	{R_61_SLICER_STATUS_BYTE_1,1,
 	 "Slicer status byte 1"},
-	{SLICER_STATUS_BYTE_2,1,
+	{R_62_SLICER_STATUS_BYTE_2,1,
 	 "Slicer status byte 2"},
 	/* 0x63-0x7f - Reserved */
 
-	/* X port, I port and the scaler part: GLOBAL_CNTL_1 to B_VERT_LUMA_PHASE_OFF_11 */
-	/* Task independent global settings: GLOBAL_CNTL_1 to STATUS_INFORMATION_SCALER_PART */
-	{GLOBAL_CNTL_1,1,
+	/* X port, I port and the scaler part: R_80_GLOBAL_CNTL_1 to R_EF_B_VERT_LUMA_PHASE_OFF_11 */
+	/* Task independent global settings: R_80_GLOBAL_CNTL_1 to R_8F_STATUS_INFO_SCALER */
+	{R_80_GLOBAL_CNTL_1,1,
 	 "Global control 1"},
-	{VERT_SYNC_FLD_ID_SRC_SEL_AND_RETIMED_V_F,1,
+	{R_81_V_SYNC_FLD_ID_SRC_SEL_AND_RETIMED_V_F,1,
 	 "Vertical sync and Field ID source selection, retimed V and F signals"},
 	/* 0x82 - Reserved */
-	{X_PORT_I_O_ENABLE_AND_OUTPUT_CLOCK,1,
+	{R_83_X_PORT_I_O_ENA_AND_OUT_CLK,1,
 	 "X port I/O enable and output clock"},
-	{I_PORT_SIGNAL_DEFINITIONS,1,
+	{R_84_I_PORT_SIGNAL_DEF,1,
 	 "I port signal definitions"},
-	{I_PORT_SIGNAL_POLARITIES,1,
+	{R_85_I_PORT_SIGNAL_POLAR,1,
 	 "I port signal polarities"},
-	{I_PORT_FIFO_FLAG_CNTL_AND_ARBITRATION,1,
+	{R_86_I_PORT_FIFO_FLAG_CNTL_AND_ARBIT,1,
 	 "I port FIFO flag control and arbitration"},
-	{I_PORT_I_O_ENABLE_OUTPUT_CLOCK_AND_GATED,  1,
+	{R_87_I_PORT_I_O_ENA_OUT_CLK_AND_GATED,  1,
 	 "I port I/O enable output clock and gated"},
-	{POWER_SAVE_ADC_PORT_CNTL,1,
+	{R_88_POWER_SAVE_ADC_PORT_CNTL,1,
 	 "Power save/ADC port control"},
 	/* 089-0x8e - Reserved */
-	{STATUS_INFORMATION_SCALER_PART,1,
+	{R_8F_STATUS_INFO_SCALER,1,
 	 "Status information scaler part"},
 
-	/* Task A definition: A_TASK_HANDLING_CNTL to A_VERT_LUMA_PHASE_OFF_11 */
+	/* Task A definition: R_90_A_TASK_HANDLING_CNTL to R_BF_A_VERT_LUMA_PHASE_OFF_11 */
 	/* Task A: Basic settings and acquisition window definition */
-	{A_TASK_HANDLING_CNTL,1,
+	{R_90_A_TASK_HANDLING_CNTL,1,
 	 "Task A: Task handling control"},
-	{A_X_PORT_FORMATS_AND_CONF,1,
+	{R_91_A_X_PORT_FORMATS_AND_CONF,1,
 	 "Task A: X port formats and configuration"},
-	{A_X_PORT_INPUT_REFERENCE_SIGNAL,1,
+	{R_92_A_X_PORT_INPUT_REFERENCE_SIGNAL,1,
 	 "Task A: X port input reference signal definition"},
-	{A_I_PORT_OUTPUT_FORMATS_AND_CONF,1,
+	{R_93_A_I_PORT_OUTPUT_FORMATS_AND_CONF,1,
 	 "Task A: I port output formats and configuration"},
-	{A_HORIZ_INPUT_WINDOW_START,2,
+	{R_94_A_HORIZ_INPUT_WINDOW_START,2,
 	 "Task A: Horizontal input window start"},
-	{A_HORIZ_INPUT_WINDOW_LENGTH,2,
+	{R_96_A_HORIZ_INPUT_WINDOW_LENGTH,2,
 	 "Task A: Horizontal input window length"},
-	{A_VERT_INPUT_WINDOW_START,2,
+	{R_98_A_VERT_INPUT_WINDOW_START,2,
 	 "Task A: Vertical input window start"},
-	{A_VERT_INPUT_WINDOW_LENGTH,2,
+	{R_9A_A_VERT_INPUT_WINDOW_LENGTH,2,
 	 "Task A: Vertical input window length"},
-	{A_HORIZ_OUTPUT_WINDOW_LENGTH,2,
+	{R_9C_A_HORIZ_OUTPUT_WINDOW_LENGTH,2,
 	 "Task A: Horizontal output window length"},
-	{A_VERT_OUTPUT_WINDOW_LENGTH,2,
+	{R_9E_A_VERT_OUTPUT_WINDOW_LENGTH,2,
 	 "Task A: Vertical output window length"},
 
 	/* Task A: FIR filtering and prescaling */
-	{A_HORIZ_PRESCALING,1,
+	{R_A0_A_HORIZ_PRESCALING,1,
 	 "Task A: Horizontal prescaling"},
-	{A_ACCUMULATION_LENGTH,1,
+	{R_A1_A_ACCUMULATION_LENGTH,1,
 	 "Task A: Accumulation length"},
-	{A_PRESCALER_DC_GAIN_AND_FIR_PREFILTER,1,
+	{R_A2_A_PRESCALER_DC_GAIN_AND_FIR_PREFILTER,1,
 	 "Task A: Prescaler DC gain and FIR prefilter"},
 	/* 0xa3 - Reserved */
-	{A_LUMA_BRIGHTNESS_CNTL,1,
+	{R_A4_A_LUMA_BRIGHTNESS_CNTL,1,
 	 "Task A: Luminance brightness control"},
-	{A_LUMA_CONTRAST_CNTL,1,
+	{R_A5_A_LUMA_CONTRAST_CNTL,1,
 	 "Task A: Luminance contrast control"},
-	{A_CHROMA_SATURATION_CNTL,1,
+	{R_A6_A_CHROMA_SATURATION_CNTL,1,
 	 "Task A: Chrominance saturation control"},
 	/* 0xa7 - Reserved */
 
 	/* Task A: Horizontal phase scaling */
-	{A_HORIZ_LUMA_SCALING_INC,2,
+	{R_A8_A_HORIZ_LUMA_SCALING_INC,2,
 	 "Task A: Horizontal luminance scaling increment"},
-	{A_HORIZ_LUMA_PHASE_OFF,1,
+	{R_AA_A_HORIZ_LUMA_PHASE_OFF,1,
 	 "Task A: Horizontal luminance phase offset"},
 	/* 0xab - Reserved */
-	{A_HORIZ_CHROMA_SCALING_INC,2,
+	{R_AC_A_HORIZ_CHROMA_SCALING_INC,2,
 	 "Task A: Horizontal chrominance scaling increment"},
-	{A_HORIZ_CHROMA_PHASE_OFF,1,
+	{R_AE_A_HORIZ_CHROMA_PHASE_OFF,1,
 	 "Task A: Horizontal chrominance phase offset"},
 	/* 0xaf - Reserved */
 
 	/* Task A: Vertical scaling */
-	{A_VERT_LUMA_SCALING_INC,2,
+	{R_B0_A_VERT_LUMA_SCALING_INC,2,
 	 "Task A: Vertical luminance scaling increment"},
-	{A_VERT_CHROMA_SCALING_INC,2,
+	{R_B2_A_VERT_CHROMA_SCALING_INC,2,
 	 "Task A: Vertical chrominance scaling increment"},
-	{A_VERT_SCALING_MODE_CNTL,1,
+	{R_B4_A_VERT_SCALING_MODE_CNTL,1,
 	 "Task A: Vertical scaling mode control"},
 	/* 0xb5-0xb7 - Reserved */
-	{A_VERT_CHROMA_PHASE_OFF_00,1,
+	{R_B8_A_VERT_CHROMA_PHASE_OFF_00,1,
 	 "Task A: Vertical chrominance phase offset '00'"},
-	{A_VERT_CHROMA_PHASE_OFF_01,1,
+	{R_B9_A_VERT_CHROMA_PHASE_OFF_01,1,
 	 "Task A: Vertical chrominance phase offset '01'"},
-	{A_VERT_CHROMA_PHASE_OFF_10,1,
+	{R_BA_A_VERT_CHROMA_PHASE_OFF_10,1,
 	 "Task A: Vertical chrominance phase offset '10'"},
-	{A_VERT_CHROMA_PHASE_OFF_11,1,
+	{R_BB_A_VERT_CHROMA_PHASE_OFF_11,1,
 	 "Task A: Vertical chrominance phase offset '11'"},
-	{A_VERT_LUMA_PHASE_OFF_00,1,
+	{R_BC_A_VERT_LUMA_PHASE_OFF_00,1,
 	 "Task A: Vertical luminance phase offset '00'"},
-	{A_VERT_LUMA_PHASE_OFF_01,1,
+	{R_BD_A_VERT_LUMA_PHASE_OFF_01,1,
 	 "Task A: Vertical luminance phase offset '01'"},
-	{A_VERT_LUMA_PHASE_OFF_10,1,
+	{R_BE_A_VERT_LUMA_PHASE_OFF_10,1,
 	 "Task A: Vertical luminance phase offset '10'"},
-	{A_VERT_LUMA_PHASE_OFF_11,1,
+	{R_BF_A_VERT_LUMA_PHASE_OFF_11,1,
 	 "Task A: Vertical luminance phase offset '11'"},
 
-	/* Task B definition: B_TASK_HANDLING_CNTL to B_VERT_LUMA_PHASE_OFF_11 */
+	/* Task B definition: R_C0_B_TASK_HANDLING_CNTL to R_EF_B_VERT_LUMA_PHASE_OFF_11 */
 	/* Task B: Basic settings and acquisition window definition */
-	{B_TASK_HANDLING_CNTL,1,
+	{R_C0_B_TASK_HANDLING_CNTL,1,
 	 "Task B: Task handling control"},
-	{B_X_PORT_FORMATS_AND_CONF,1,
+	{R_C1_B_X_PORT_FORMATS_AND_CONF,1,
 	 "Task B: X port formats and configuration"},
-	{B_INPUT_REFERENCE_SIGNAL_DEFINITION,1,
+	{R_C2_B_INPUT_REFERENCE_SIGNAL_DEFINITION,1,
 	 "Task B: Input reference signal definition"},
-	{B_I_PORT_FORMATS_AND_CONF,1,
+	{R_C3_B_I_PORT_FORMATS_AND_CONF,1,
 	 "Task B: I port formats and configuration"},
-	{B_HORIZ_INPUT_WINDOW_START,2,
+	{R_C4_B_HORIZ_INPUT_WINDOW_START,2,
 	 "Task B: Horizontal input window start"},
-	{B_HORIZ_INPUT_WINDOW_LENGTH,2,
+	{R_C6_B_HORIZ_INPUT_WINDOW_LENGTH,2,
 	 "Task B: Horizontal input window length"},
-	{B_VERT_INPUT_WINDOW_START,2,
+	{R_C8_B_VERT_INPUT_WINDOW_START,2,
 	 "Task B: Vertical input window start"},
-	{B_VERT_INPUT_WINDOW_LENGTH,2,
+	{R_CA_B_VERT_INPUT_WINDOW_LENGTH,2,
 	 "Task B: Vertical input window length"},
-	{B_HORIZ_OUTPUT_WINDOW_LENGTH,2,
+	{R_CC_B_HORIZ_OUTPUT_WINDOW_LENGTH,2,
 	 "Task B: Horizontal output window length"},
-	{B_VERT_OUTPUT_WINDOW_LENGTH,2,
+	{R_CE_B_VERT_OUTPUT_WINDOW_LENGTH,2,
 	 "Task B: Vertical output window length"},
 
 	/* Task B: FIR filtering and prescaling */
-	{B_HORIZ_PRESCALING,1,
+	{R_D0_B_HORIZ_PRESCALING,1,
 	 "Task B: Horizontal prescaling"},
-	{B_ACCUMULATION_LENGTH,1,
+	{R_D1_B_ACCUMULATION_LENGTH,1,
 	 "Task B: Accumulation length"},
-	{B_PRESCALER_DC_GAIN_AND_FIR_PREFILTER,1,
+	{R_D2_B_PRESCALER_DC_GAIN_AND_FIR_PREFILTER,1,
 	 "Task B: Prescaler DC gain and FIR prefilter"},
 	/* 0xd3 - Reserved */
-	{B_LUMA_BRIGHTNESS_CNTL,1,
+	{R_D4_B_LUMA_BRIGHTNESS_CNTL,1,
 	 "Task B: Luminance brightness control"},
-	{B_LUMA_CONTRAST_CNTL,1,
+	{R_D5_B_LUMA_CONTRAST_CNTL,1,
 	 "Task B: Luminance contrast control"},
-	{B_CHROMA_SATURATION_CNTL,1,
+	{R_D6_B_CHROMA_SATURATION_CNTL,1,
 	 "Task B: Chrominance saturation control"},
 	/* 0xd7 - Reserved */
 
 	/* Task B: Horizontal phase scaling */
-	{B_HORIZ_LUMA_SCALING_INC,2,
+	{R_D8_B_HORIZ_LUMA_SCALING_INC,2,
 	 "Task B: Horizontal luminance scaling increment"},
-	{B_HORIZ_LUMA_PHASE_OFF,1,
+	{R_DA_B_HORIZ_LUMA_PHASE_OFF,1,
 	 "Task B: Horizontal luminance phase offset"},
 	/* 0xdb - Reserved */
-	{B_HORIZ_CHROMA_SCALING,2,
+	{R_DC_B_HORIZ_CHROMA_SCALING,2,
 	 "Task B: Horizontal chrominance scaling"},
-	{B_HORIZ_PHASE_OFFSET_CRHOMA,1,
+	{R_DE_B_HORIZ_PHASE_OFFSET_CRHOMA,1,
 	 "Task B: Horizontal Phase Offset Chroma"},
 	/* 0xdf - Reserved */
 
 	/* Task B: Vertical scaling */
-	{B_VERT_LUMA_SCALING_INC,2,
+	{R_E0_B_VERT_LUMA_SCALING_INC,2,
 	 "Task B: Vertical luminance scaling increment"},
-	{B_VERT_CHROMA_SCALING_INC,2,
+	{R_E2_B_VERT_CHROMA_SCALING_INC,2,
 	 "Task B: Vertical chrominance scaling increment"},
-	{B_VERT_SCALING_MODE_CNTL,1,
+	{R_E4_B_VERT_SCALING_MODE_CNTL,1,
 	 "Task B: Vertical scaling mode control"},
 	/* 0xe5-0xe7 - Reserved */
-	{B_VERT_CHROMA_PHASE_OFF_00,1,
+	{R_E8_B_VERT_CHROMA_PHASE_OFF_00,1,
 	 "Task B: Vertical chrominance phase offset '00'"},
-	{B_VERT_CHROMA_PHASE_OFF_01,1,
+	{R_E9_B_VERT_CHROMA_PHASE_OFF_01,1,
 	 "Task B: Vertical chrominance phase offset '01'"},
-	{B_VERT_CHROMA_PHASE_OFF_10,1,
+	{R_EA_B_VERT_CHROMA_PHASE_OFF_10,1,
 	 "Task B: Vertical chrominance phase offset '10'"},
-	{B_VERT_CHROMA_PHASE_OFF_11,1,
+	{R_EB_B_VERT_CHROMA_PHASE_OFF_11,1,
 	 "Task B: Vertical chrominance phase offset '11'"},
-	{B_VERT_LUMA_PHASE_OFF_00,1,
+	{R_EC_B_VERT_LUMA_PHASE_OFF_00,1,
 	 "Task B: Vertical luminance phase offset '00'"},
-	{B_VERT_LUMA_PHASE_OFF_01,1,
+	{R_ED_B_VERT_LUMA_PHASE_OFF_01,1,
 	 "Task B: Vertical luminance phase offset '01'"},
-	{B_VERT_LUMA_PHASE_OFF_10,1,
+	{R_EE_B_VERT_LUMA_PHASE_OFF_10,1,
 	 "Task B: Vertical luminance phase offset '10'"},
-	{B_VERT_LUMA_PHASE_OFF_11,1,
+	{R_EF_B_VERT_LUMA_PHASE_OFF_11,1,
 	 "Task B: Vertical luminance phase offset '11'"},
 
 	/* second PLL (PLL2) and Pulsegenerator Programming */
-	{ LFCO_PER_LINE, 1,
+	{ R_F0_LFCO_PER_LINE, 1,
 	  "LFCO's per line"},
-	{ P_I_PARAM_SELECT,1,
+	{ R_F1_P_I_PARAM_SELECT,1,
 	  "P-/I- Param. Select., PLL Mode, PLL H-Src., LFCO's per line"},
-	{ NOMINAL_PLL2_DTO,1,
+	{ R_F2_NOMINAL_PLL2_DTO,1,
 	 "Nominal PLL2 DTO"},
-	{PLL_INCREMENT,1,
+	{R_F3_PLL_INCREMENT,1,
 	 "PLL2 Increment"},
-	{PLL2_STATUS,1,
+	{R_F4_PLL2_STATUS,1,
 	 "PLL2 Status"},
-	{PULSGEN_LINE_LENGTH,1,
+	{R_F5_PULSGEN_LINE_LENGTH,1,
 	 "Pulsgen. line length"},
-	{PULSE_A_POS_LSB_AND_PULSEGEN_CONFIG,1,
+	{R_F6_PULSE_A_POS_LSB_AND_PULSEGEN_CONFIG,1,
 	 "Pulse A Position, Pulsgen Resync., Pulsgen. H-Src., Pulsgen. line length"},
-	{PULSE_A_POS_MSB,1,
+	{R_F7_PULSE_A_POS_MSB,1,
 	 "Pulse A Position"},
-	{PULSE_B_POS,2,
+	{R_F8_PULSE_B_POS,2,
 	 "Pulse B Position"},
-	{PULSE_C_POS,2,
+	{R_FA_PULSE_C_POS,2,
 	 "Pulse C Position"},
 	/* 0xfc to 0xfe - Reserved */
-	{S_PLL_MAX_PHASE_ERR_THRESH_NUM_LINES,1,
+	{R_FF_S_PLL_MAX_PHASE_ERR_THRESH_NUM_LINES,1,
 	 "S_PLL max. phase, error threshold, PLL2 no. of lines, threshold"},
 };
 #endif