diff options
| author | Mauro Carvalho Chehab <mchehab@infradead.org> | 2008-03-27 09:22:06 -0300 |
|---|---|---|
| committer | Mauro Carvalho Chehab <mchehab@infradead.org> | 2008-03-27 09:22:06 -0300 |
| commit | 96e68dee554c5a2529bb70972c9954e62c36386d (patch) | |
| tree | 89bbf0baba6994cb2757a216d5253ec5e94e9c46 /linux/include/asm-arm/arch-pxa/pxa-regs.h | |
| parent | b551799548f9bfe9e20df63ae1263df5a367f8e3 (diff) | |
| download | mediapointer-dvb-s2-96e68dee554c5a2529bb70972c9954e62c36386d.tar.gz mediapointer-dvb-s2-96e68dee554c5a2529bb70972c9954e62c36386d.tar.bz2 | |
Update some files from mainstream
From: Mauro Carvalho Chehab <mchehab@infradead.org>
Those files are maintained on other trees. Just update them to the newest
version.
kernel-sync:
Signed-off-by: Mauro Carvalho Chehab <mchehab@infradead.org>
Diffstat (limited to 'linux/include/asm-arm/arch-pxa/pxa-regs.h')
| -rw-r--r-- | linux/include/asm-arm/arch-pxa/pxa-regs.h | 25 |
1 files changed, 23 insertions, 2 deletions
diff --git a/linux/include/asm-arm/arch-pxa/pxa-regs.h b/linux/include/asm-arm/arch-pxa/pxa-regs.h index bf4fd0b96..b65a3a789 100644 --- a/linux/include/asm-arm/arch-pxa/pxa-regs.h +++ b/linux/include/asm-arm/arch-pxa/pxa-regs.h @@ -520,6 +520,9 @@ #define MCCR_FSRIE (1 << 1) /* FIFO Service Request Interrupt Enable */ #define GCR __REG(0x4050000C) /* Global Control Register */ +#ifdef CONFIG_PXA3xx +#define GCR_CLKBPB (1 << 31) /* Internal clock enable */ +#endif #define GCR_nDMAEN (1 << 24) /* non DMA Enable */ #define GCR_CDONE_IE (1 << 19) /* Command Done Interrupt Enable */ #define GCR_SDONE_IE (1 << 18) /* Status Done Interrupt Enable */ @@ -1131,6 +1134,19 @@ * General Purpose I/O */ +#define GPIO0_BASE ((void __iomem *)io_p2v(0x40E00000)) +#define GPIO1_BASE ((void __iomem *)io_p2v(0x40E00004)) +#define GPIO2_BASE ((void __iomem *)io_p2v(0x40E00008)) +#define GPIO3_BASE ((void __iomem *)io_p2v(0x40E00100)) + +#define GPLR_OFFSET 0x00 +#define GPDR_OFFSET 0x0C +#define GPSR_OFFSET 0x18 +#define GPCR_OFFSET 0x24 +#define GRER_OFFSET 0x30 +#define GFER_OFFSET 0x3C +#define GEDR_OFFSET 0x48 + #define GPLR0 __REG(0x40E00000) /* GPIO Pin-Level Register GPIO<31:0> */ #define GPLR1 __REG(0x40E00004) /* GPIO Pin-Level Register GPIO<63:32> */ #define GPLR2 __REG(0x40E00008) /* GPIO Pin-Level Register GPIO<80:64> */ @@ -1824,6 +1840,11 @@ /* [1..256 Tpix] */ \ (((Tpix) - 1) << FShft (LCCR1_BLW)) +#if 0 +#define LCCR3_PCD (0xff) /* Pixel clock divisor */ +#define LCCR3_ACB (0xff << 8) /* AC Bias pin frequency */ +#define LCCR3_ACB_S 8 +#endif #define LCCR2_LPP Fld (10, 0) /* Line Per Panel - 1 */ #define LCCR2_DisHght(Line) /* Display Height [1..1024 lines] */ \ @@ -1847,7 +1868,7 @@ /* [0..255 Tln] */ \ ((Tln) << FShft (LCCR2_BFW)) -#if 0 +#if 0 /* keep */ #define LCCR3_PCD (0xff) /* Pixel clock divisor */ #define LCCR3_ACB (0xff << 8) /* AC Bias pin frequency */ #define LCCR3_ACB_S 8 @@ -1866,7 +1887,7 @@ #define LCCR3_OutEnH (LCCR3_OEP*0) /* Output Enable active High */ #define LCCR3_OutEnL (LCCR3_OEP*1) /* Output Enable active Low */ -#if 0 +#if 0 /* keep */ #define LCCR3_BPP (7 << 24) /* bits per pixel */ #define LCCR3_BPP_S 24 #endif |