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| author | Mauro Carvalho Chehab <mchehab@infradead.org> | 2008-02-24 00:12:57 +0000 |
|---|---|---|
| committer | Mauro Carvalho Chehab <mchehab@infradead.org> | 2008-02-24 00:12:57 +0000 |
| commit | c330ead98bf91bbd4afd6afd53e3d1c7019452f4 (patch) | |
| tree | 1d366ea03a9e91d74e7361675d5e18f1faf86cb2 /linux/include/asm-arm/arch-pxa/pxa-regs.h | |
| parent | 3d2f3f63ab5390b9c19b2a42c7f78d420ad602b3 (diff) | |
| download | mediapointer-dvb-s2-c330ead98bf91bbd4afd6afd53e3d1c7019452f4.tar.gz mediapointer-dvb-s2-c330ead98bf91bbd4afd6afd53e3d1c7019452f4.tar.bz2 | |
Clean up pxa-camera driver, remove non-functional and never tested pm-support
From: Guennadi Liakhovetski <g.liakhovetski@pengutronix.de>
This patch addresses most issues pointed out by Russell and Erik, moves
recently introduced into pxa-regs.h camera-specific defines into
pxa_camera.c, removes dummy power-management functions, improves
function-naming, etc.
Signed-off-by: Guennadi Liakhovetski <g.liakhovetski@pengutronix.de>
Acked-by: Russell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: Mauro Carvalho Chehab <mchehab@infradead.org>
Diffstat (limited to 'linux/include/asm-arm/arch-pxa/pxa-regs.h')
| -rw-r--r-- | linux/include/asm-arm/arch-pxa/pxa-regs.h | 19 |
1 files changed, 0 insertions, 19 deletions
diff --git a/linux/include/asm-arm/arch-pxa/pxa-regs.h b/linux/include/asm-arm/arch-pxa/pxa-regs.h index 2eb05e746..bf4fd0b96 100644 --- a/linux/include/asm-arm/arch-pxa/pxa-regs.h +++ b/linux/include/asm-arm/arch-pxa/pxa-regs.h @@ -2000,11 +2000,6 @@ #define CICR0_ENB (1 << 28) /* Camera interface enable */ #define CICR0_DIS (1 << 27) /* Camera interface disable */ #define CICR0_SIM (0x7 << 24) /* Sensor interface mode mask */ -#define CICR0_SIM_MP (0 << 24) -#define CICR0_SIM_SP (1 << 24) -#define CICR0_SIM_MS (2 << 24) -#define CICR0_SIM_EP (3 << 24) -#define CICR0_SIM_ES (4 << 24) #define CICR0_TOM (1 << 9) /* Time-out mask */ #define CICR0_RDAVM (1 << 8) /* Receive-data-available mask */ #define CICR0_FEM (1 << 7) /* FIFO-empty mask */ @@ -2055,20 +2050,6 @@ #define CICR4_FR_RATE (0x7 << 8) /* Frame rate mask */ #define CICR4_DIV (0xff << 0) /* Clock divisor mask */ -#define CICR1_DW_VAL(x) ((x) & CICR1_DW) /* Data bus width */ -#define CICR1_PPL_VAL(x) (((x) << 15) & CICR1_PPL) /* Pixels per line */ - -#define CICR2_BLW_VAL(x) (((x) << 24) & CICR2_BLW) /* Beginning-of-line pixel clock wait count */ -#define CICR2_ELW_VAL(x) (((x) << 16) & CICR2_ELW) /* End-of-line pixel clock wait count */ -#define CICR2_HSW_VAL(x) (((x) << 10) & CICR2_HSW) /* Horizontal sync pulse width */ -#define CICR2_BFPW_VAL(x) (((x) << 3) & CICR2_BFPW) /* Beginning-of-frame pixel clock wait count */ -#define CICR2_FSW_VAL(x) (((x) << 0) & CICR2_FSW) /* Frame stabilization wait count */ - -#define CICR3_BFW_VAL(x) (((x) << 24) & CICR3_BFW) /* Beginning-of-frame line clock wait count */ -#define CICR3_EFW_VAL(x) (((x) << 16) & CICR3_EFW) /* End-of-frame line clock wait count */ -#define CICR3_VSW_VAL(x) (((x) << 11) & CICR3_VSW) /* Vertical sync pulse width */ -#define CICR3_LPF_VAL(x) (((x) << 0) & CICR3_LPF) /* Lines per frame */ - #define CISR_FTO (1 << 15) /* FIFO time-out */ #define CISR_RDAV_2 (1 << 14) /* Channel 2 receive data available */ #define CISR_RDAV_1 (1 << 13) /* Channel 1 receive data available */ |