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| author | Hans Verkuil <hverkuil@xs4all.nl> | 2006-04-02 17:50:42 +0200 |
|---|---|---|
| committer | Hans Verkuil <hverkuil@xs4all.nl> | 2006-04-02 17:50:42 +0200 |
| commit | 7d27e5f3b2bbe8ca82a41dce5203a67d7595ab09 (patch) | |
| tree | 61df08b6032aee1f880e3a1987019b542aee8c31 /linux/include/media/saa7115.h | |
| parent | 33ba11f17dbf2c000c797475db2c6b68b7d33662 (diff) | |
| download | mediapointer-dvb-s2-7d27e5f3b2bbe8ca82a41dce5203a67d7595ab09.tar.gz mediapointer-dvb-s2-7d27e5f3b2bbe8ca82a41dce5203a67d7595ab09.tar.bz2 | |
Add support for VIDIOC_INT_S_CRYSTAL_FREQ internal command.
From: Hans Verkuil <hverkuil@xs4all.nl>
Some saa7115-based cards use a different crystal frequency and a different
audio clock generation. Add a new VIDIOC_INT_S_CRYSTAL_FREQ command to be
able to set these values.
Also change the default APLL setting to 0. It makes no sense to have the
audio clock independent from the video clock, this can lead to audio/video
synchronization problems. Setting this to 0 is also consistent with the old
saa7114.c source and the way the Hauppauge Windows driver sets it.
Signed-off-by: Hans Verkuil <hverkuil@xs4all.nl>
Diffstat (limited to 'linux/include/media/saa7115.h')
| -rw-r--r-- | linux/include/media/saa7115.h | 11 |
1 files changed, 10 insertions, 1 deletions
diff --git a/linux/include/media/saa7115.h b/linux/include/media/saa7115.h index 6b4836f3f..9f0e2285a 100644 --- a/linux/include/media/saa7115.h +++ b/linux/include/media/saa7115.h @@ -1,5 +1,5 @@ /* - saa7115.h - definition for saa7113/4/5 inputs + saa7115.h - definition for saa7113/4/5 inputs and frequency flags Copyright (C) 2006 Hans Verkuil (hverkuil@xs4all.nl) @@ -33,5 +33,14 @@ #define SAA7115_SVIDEO2 8 #define SAA7115_SVIDEO3 9 +/* SAA7115 v4l2_crystal_freq frequency values */ +#define SAA7115_FREQ_32_11_MHZ 32110000 /* 32.11 MHz crystal, SAA7114/5 only */ +#define SAA7115_FREQ_24_576_MHZ 24576000 /* 24.576 MHz crystal */ + +/* SAA7115 v4l2_crystal_freq audio clock control flags */ +#define SAA7115_FREQ_FL_UCGC (1 << 0) /* SA 3A[7], UCGC, SAA7115 only */ +#define SAA7115_FREQ_FL_CGCDIV (1 << 1) /* SA 3A[6], CGCDIV, SAA7115 only */ +#define SAA7115_FREQ_FL_APLL (1 << 2) /* SA 3A[3], APLL, SAA7114/5 only */ + #endif |