diff options
| -rw-r--r-- | linux/drivers/media/dvb/frontends/nxt6000.c | 417 | ||||
| -rw-r--r-- | linux/drivers/media/dvb/frontends/nxt6000.h | 292 |
2 files changed, 709 insertions, 0 deletions
diff --git a/linux/drivers/media/dvb/frontends/nxt6000.c b/linux/drivers/media/dvb/frontends/nxt6000.c new file mode 100644 index 000000000..984f065f7 --- /dev/null +++ b/linux/drivers/media/dvb/frontends/nxt6000.c @@ -0,0 +1,417 @@ +/* + + NxtWave Communications - NXT6000 demodulator driver + + This driver currently supports: + + Alps TDME7 (Tuner: MITEL SP5659) + Alps TDED4 (Tuner: TI ALP510, external Nxt6000) + + Copyright (C) 2002-2003 Florian Schirmer <schirmer@taytron.net> + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + +*/ + +#include <linux/module.h> +#include <linux/init.h> +#include <linux/delay.h> +#include <linux/slab.h> +#include <linux/poll.h> +#include <asm/io.h> +#include <linux/i2c.h> + +#include "dvb_frontend.h" +#include "nxt6000.h" + +MODULE_DESCRIPTION("NxtWave NXT6000 DVB demodulator driver"); +MODULE_AUTHOR("Florian Schirmer"); +MODULE_LICENSE("GPL"); + +static struct dvb_frontend_info nxt6000_info = { + + .name = "NxtWave NXT6000", + .type = FE_OFDM, + .frequency_min = 48250000, + .frequency_max = 863250000, + .frequency_stepsize = 62500, + /*.frequency_tolerance = */ /* FIXME: 12% of SR */ + .symbol_rate_min = 0, /* FIXME */ + .symbol_rate_max = 9360000, /* FIXME */ + .symbol_rate_tolerance = 4000, + .notifier_delay = 0, + .caps = FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 | + FE_CAN_FEC_4_5 | FE_CAN_FEC_5_6 | FE_CAN_FEC_6_7 | + FE_CAN_FEC_7_8 | FE_CAN_FEC_8_9 | FE_CAN_FEC_AUTO | + FE_CAN_QAM_16 | FE_CAN_QAM_64 | FE_CAN_QAM_AUTO | + FE_CAN_TRANSMISSION_MODE_AUTO | +// FE_CAN_BANDWIDTH_AUTO | + FE_CAN_GUARD_INTERVAL_AUTO | + FE_CAN_HIERARCHY_AUTO, + +}; + +static int nxt6000_writereg(struct dvb_i2c_bus *i2c, u8 reg, u8 data) +{ + + u8 buf[] = {reg, data}; + struct i2c_msg msg = {addr: 0x14 >> 1, flags: 0, buf: buf, len: 2}; + int ret; + + if ((ret = i2c->xfer(i2c, &msg, 1)) != 1) + printk("nxt6000: nxt6000_write error (reg: 0x%02X <- data: 0x%02X)\n", reg, data); + + return (ret != 1) ? -EFAULT : 0; + +} + +static u8 nxt6000_readreg(struct dvb_i2c_bus *i2c, u8 reg) +{ + int ret; + + u8 b0[] = {reg}; + u8 b1[] = {0}; + struct i2c_msg msgs[] = {{addr: 0x14 >> 1, flags: 0, buf: b0, len: 1}, + {addr: 0x14 >> 1, flags: I2C_M_RD, buf: b1, len: 1}}; + + ret = i2c->xfer(i2c, msgs, 2); + + if (ret != 2) + printk("nxt6000: nxt6000_read error (reg: 0x%02X, ret=%d)\n", reg, ret); + + return b1[0]; + +} + +static int pll_write(struct dvb_i2c_bus *i2c, u8 addr, u8 *buf, u8 len) +{ + + struct i2c_msg msg = {addr: addr >> 1, flags: 0, buf: buf, len: len}; + int ret; + + nxt6000_writereg(i2c, ENABLE_TUNER_IIC, 0x01); /* open i2c bus switch */ + ret = i2c->xfer(i2c, &msg, 1); + nxt6000_writereg(i2c, ENABLE_TUNER_IIC, 0x00); /* close i2c bus switch */ + + if (ret != 1) + printk("nxt6000: pll_write error %d\n", ret); + + return (ret != 1) ? -EFAULT : 0; + +} + +#define FREQ2DIV(freq) ((freq + 36166667) / 166667) + +static int sp5659_set_tv_freq(struct dvb_i2c_bus *i2c, u32 freq) +{ + + u8 buf[4]; + + buf[0] = (FREQ2DIV(freq) >> 8) & 0x7F; + buf[1] = FREQ2DIV(freq) & 0xFF; + buf[2] = (((FREQ2DIV(freq) >> 15) & 0x03) << 5) | 0x85; + + if ((freq >= 174000000) && (freq < 230000000)) + buf[3] = 0x82; + else if ((freq >= 470000000) && (freq < 782000000)) + buf[3] = 0x85; + else if ((freq >= 782000000) && (freq < 863000000)) + buf[3] = 0xC5; + else + return -EINVAL; + + return pll_write(i2c, 0xC2, buf, 4); + +} + +static int alp510_set_tv_freq(struct dvb_i2c_bus *i2c, u32 freq) +{ + + u8 buf[4]; + + buf[0] = (FREQ2DIV(freq) >> 8) & 0x7F; + buf[1] = FREQ2DIV(freq) & 0xFF; + buf[2] = 0x85; + + if ((freq >= 47000000) && (freq < 153000000)) + buf[3] = 0x01; + else if ((freq >= 153000000) && (freq < 430000000)) + buf[3] = 0x02; + else if ((freq >= 430000000) && (freq < 824000000)) + buf[3] = 0x08; + else if ((freq >= 824000000) && (freq < 863000000)) + buf[3] = 0x88; + else + return -EINVAL; + + // Enable 8K SAW BW mode + buf[3] |= (1 << 2); + + return pll_write(i2c, 0xC0, buf, 4); + +} + +#if 0 +static int SetInversion(struct dvb_i2c_bus *i2c, int inversion) +{ + u8 val; + + if (inversion == stv->inv) + return 0; + stv->inv=inversion; + switch (inversion) { + case INVERSION_AUTO: // Hmm, return EINVAL or leave it like this? + default: + case INVERSION_OFF: + val=0x01; + break; + case INVERSION_ON: + val=0x00; + break; + } + writereg(client, 0x0c, + (readreg(client, 0x0c)&0xfe)|val); + return 0; +} +#endif + +static void nxt6000_reset(struct dvb_i2c_bus *i2c) +{ + + nxt6000_writereg(i2c, RS_COR_SYNC_PARAM, SYNC_PARAM); + nxt6000_writereg(i2c, BER_CTRL, /*(1 << 2) |*/ (1 << 1) | 1); + nxt6000_writereg(i2c, VIT_COR_CTL, (1 << 7) | (1 << 1)); +// VIT_BER_TIMER_? + nxt6000_writereg(i2c, OFDM_COR_CTL, (1 << 5) | (nxt6000_readreg(i2c, OFDM_COR_CTL) & 0x0F)); + // Auto mode with MODE8K & 1/8 guard as default + nxt6000_writereg(i2c, OFDM_COR_MODEGUARD, (1 << 2) | 2); +// OFDM_AGC_CTL tune zap time + nxt6000_writereg(i2c, OFDM_ITB_FREQ_1, 0x06); + nxt6000_writereg(i2c, OFDM_ITB_FREQ_2, 0x31); +// CAS_FREQ + nxt6000_writereg(i2c, OFDM_SYR_CTL, 1 << 2); + nxt6000_writereg(i2c, OFDM_PPM_CTL_1, PPM256); + nxt6000_writereg(i2c, OFDM_TRL_NOMINALRATE_1, 0x49); + nxt6000_writereg(i2c, OFDM_TRL_NOMINALRATE_2, 0x72); + nxt6000_writereg(i2c, ANALOG_CONTROL_0, 1 << 5); + nxt6000_writereg(i2c, EN_DMD_RACQ, (1 << 7) | (3 << 4) | 2); + nxt6000_writereg(i2c, DIAG_CONFIG, TB_SET); + nxt6000_writereg(i2c, SUB_DIAG_MODE_SEL, 0); + nxt6000_writereg(i2c, SUB_DIAG_MODE_SEL, CLKINVERSION); + nxt6000_writereg(i2c, TS_FORMAT, 0); +// nxt6000_writereg(i2c, TS_FORMAT, GATED_CLOCK); + +} + +#if 1 +static void nxt6000_dump_status(struct dvb_i2c_bus *i2c) +{ + + printk("RS_COR_STAT: 0x%02X\n", nxt6000_readreg(i2c, RS_COR_STAT)); + printk("VIT_SYNC_STATUS: 0x%02X\n", nxt6000_readreg(i2c, VIT_SYNC_STATUS)); + printk("OFDM_COR_STAT: 0x%02X\n", nxt6000_readreg(i2c, OFDM_COR_STAT)); + printk("OFDM_SYR_STAT: 0x%02X\n", nxt6000_readreg(i2c, OFDM_SYR_STAT)); + printk("OFDM_TPS_RCVD_1: 0x%02X\n", nxt6000_readreg(i2c, OFDM_TPS_RCVD_1)); +// printk("OFDM_TPS_RCVD_2: 0x%02X\n", nxt6000_readreg(i2c, OFDM_TPS_RCVD_2)); +// printk("OFDM_TPS_RCVD_3: 0x%02X\n", nxt6000_readreg(i2c, OFDM_TPS_RCVD_3)); +// printk("OFDM_TPS_RCVD_4: 0x%02X\n", nxt6000_readreg(i2c, OFDM_TPS_RCVD_4)); +// printk("OFDM_TPS_RESERVED_1: 0x%02X\n", nxt6000_readreg(i2c, OFDM_TPS_RESERVED_1)); +// printk("OFDM_TPS_RESERVED_2: 0x%02X\n", nxt6000_readreg(i2c, OFDM_TPS_RESERVED_2)); +// printk("RF_AGC_STATUS: 0x%02X\n", nxt6000_readreg(i2c, RF_AGC_STATUS)); + +} +#endif + +static int nxt6000_ioctl(struct dvb_frontend *fe, unsigned int cmd, void *arg) +{ + + switch (cmd) { + + case FE_GET_INFO: + + memcpy(arg, &nxt6000_info, sizeof (struct dvb_frontend_info)); + + return 0; + + case FE_READ_STATUS: + { + fe_status_t *status = (fe_status_t *)arg; +#if 0 + u8 core_status; + nxt6000_dump_status(fe->i2c); + + *status = 0; + + core_status = nxt6000_readreg(fe->i2c, OFDM_COR_STAT); + + if (core_status & AGCLOCKED) + *status |= FE_HAS_SIGNAL; + + if (nxt6000_readreg(fe->i2c, OFDM_SYR_STAT) & GI14_SYR_LOCK) + *status |= FE_HAS_CARRIER; + + if (nxt6000_readreg(fe->i2c, VIT_SYNC_STATUS) & VITINSYNC) + *status |= FE_HAS_VITERBI; + + if (nxt6000_readreg(fe->i2c, RS_COR_STAT) & RSCORESTATUS) + *status |= FE_HAS_SYNC; + + if (core_status & TPSLOCKED) + *status |= FE_HAS_LOCK; +#endif + *status = FE_HAS_LOCK; + + return 0; + + } + + case FE_READ_BER: + { + u32 *ber = (u32 *)arg; + + *ber=0; + + return 0; + + } + + case FE_READ_SIGNAL_STRENGTH: + { +// s16 *signal = (s16 *)arg; + +// *signal=(((signed char)readreg(client, 0x16))+128)<<8; + + return 0; + + } + + case FE_READ_SNR: + { +// s16 *snr = (s16 *)arg; + +// *snr=readreg(client, 0x24)<<8; +// *snr|=readreg(client, 0x25); + + break; + } + + case FE_READ_UNCORRECTED_BLOCKS: + { + u32 *ublocks = (u32 *)arg; + + *ublocks = 0; + + break; + } + + case FE_INIT: + case FE_RESET: + + nxt6000_reset(fe->i2c); + + break; + + case FE_SET_FRONTEND: + { + struct dvb_frontend_parameters *param = (struct dvb_frontend_parameters *)arg; + + //SetInversion(client, param->Inversion); + //SetFEC(client, param->u.qpsk.FEC_inner); + //SetSymbolrate(client, param->u.qpsk.SymbolRate); + alp510_set_tv_freq(fe->i2c, param->frequency); + + break; + } + + default: + + return -EOPNOTSUPP; + + } + + return 0; + +} + +static int nxt6000_attach(struct dvb_i2c_bus *i2c) +{ + + u8 core_rev; + + printk("nxt6000: attach\n"); + + if ((core_rev = nxt6000_readreg(i2c, OFDM_MSC_REV)) != NXT6000ASICDEVICE) { + + printk("nxt6000: core revision is wrong (0x%02X != 0x0B)\n", core_rev); + + return -ENODEV; + + } + + if (pll_write(i2c, 0xC0, NULL, 0) == 0) { + + printk("nxt6000: detected TI ALP510 tuner\n"); + + } else if (pll_write(i2c, 0xC2, NULL, 0) == 0) { + + printk("nxt6000: detected MITEL SP5659 tuner\n"); + + } else { + + printk("nxt6000: unable to detect tuner\n"); + + return -EINVAL; + + } + + printk("nxt6000: attached at %d:%d\n", i2c->adapter->num, i2c->id); + + nxt6000_reset(i2c); + alp510_set_tv_freq(i2c, 658000000); + nxt6000_dump_status(i2c); + + return dvb_register_frontend(nxt6000_ioctl, i2c, NULL, &nxt6000_info); + +} + +static void nxt6000_detach(struct dvb_i2c_bus *i2c) +{ + + printk("nxt6000: detach\n"); + + dvb_unregister_frontend(nxt6000_ioctl, i2c); + +} + +static __init int nxt6000_init(void) +{ + + printk("nxt6000: init\n"); + + return dvb_register_i2c_device(THIS_MODULE, nxt6000_attach, nxt6000_detach); + +} + +static __exit void nxt6000_exit(void) +{ + + printk("nxt6000: cleanup\n"); + + dvb_unregister_i2c_device(nxt6000_attach); + +} + +module_init(nxt6000_init); +module_exit(nxt6000_exit); diff --git a/linux/drivers/media/dvb/frontends/nxt6000.h b/linux/drivers/media/dvb/frontends/nxt6000.h new file mode 100644 index 000000000..995bbca62 --- /dev/null +++ b/linux/drivers/media/dvb/frontends/nxt6000.h @@ -0,0 +1,292 @@ +/**********************************************************************
/ + * DRV6000reg.H
+ * Public Include File for DRV6000 users
+ *
+ * Copyright (C) 2001 NxtWave Communications, Inc.
+ *
+ * $Log: alps_tdme7.h,v $ + * Revision 1.1 2003/01/03 02:25:45 obi + * alps tdme7 driver + *
+ *
+ * Rev 1.10 Jun 12 2002 11:28:02 dkoeger
+ * Updated for SA in GUi work
+ *
+ * Rev 1.9 Apr 01 2002 10:38:46 dkoeger
+ * Updated for 1.0.31 GUI
+ *
+ * Rev 1.8 Mar 11 2002 10:04:56 dkoeger
+ * Updated for 1.0.31 GUI version
+ *
+ * Rev 1.5 Dec 07 2001 14:40:40 dkoeger
+ * Updated for 1.0.28 GUI
+ *
+ * Rev 1.4 Nov 13 2001 11:09:00 dkoeger
+ * No change.
+ *
+ * Rev 1.3 Aug 23 2001 14:21:02 dkoeger
+ * Updated for driver version 2.1.9
+ *
+ * Rev 1.2 Jul 09 2001 09:20:04 dkoeger
+ * Updated for 1.0.18
+ *
+ * Rev 1.1 Jun 13 2001 16:14:24 dkoeger
+ * Updated to reflect NXT6000 GUI BETA 1.0.11 6/13/2001
+ **********************************************************************/
+
+
+/* Nxt6000 Register Addresses and Bit Masks */
+
+/* Maximum Register Number */
+#define MAXNXT6000REG (0x9A)
+
+/* 0x1B A_VIT_BER_0 aka 0x3A */
+#define A_VIT_BER_0 (0x1B)
+
+/* 0x1D A_VIT_BER_TIMER_0 aka 0x38 */
+#define A_VIT_BER_TIMER_0 (0x1D)
+
+/* 0x21 RS_COR_STAT */
+#define RS_COR_STAT (0x21)
+#define RSCORESTATUS (0x03)
+
+/* 0x22 RS_COR_INTEN */
+#define RS_COR_INTEN (0x22)
+
+/* 0x23 RS_COR_INSTAT */
+#define RS_COR_INSTAT (0x23)
+#define INSTAT_ERROR (0x04)
+#define LOCK_LOSS_BITS (0x03)
+
+/* 0x24 RS_COR_SYNC_PARAM */
+#define RS_COR_SYNC_PARAM (0x24)
+#define SYNC_PARAM (0x03)
+
+/* 0x25 BER_CTRL */
+#define BER_CTRL (0x25)
+#define BER_ENABLE (0x02)
+#define BER_RESET (0x01)
+
+/* 0x26 BER_PAY */
+#define BER_PAY (0x26)
+
+/* 0x27 BER_PKT_L */
+#define BER_PKT_L (0x27)
+#define BER_PKTOVERFLOW (0x80)
+
+/* 0x30 VIT_COR_CTL */
+#define VIT_COR_CTL (0x30)
+#define BER_CONTROL (0x02)
+#define VIT_COR_MASK (0x82)
+#define VIT_COR_RESYNC (0x80)
+
+
+/* 0x32 VIT_SYNC_STATUS */
+#define VIT_SYNC_STATUS (0x32)
+#define VITINSYNC (0x80)
+
+/* 0x33 VIT_COR_INTEN */
+#define VIT_COR_INTEN (0x33)
+#define GLOBAL_ENABLE (0x80)
+
+/* 0x34 VIT_COR_INTSTAT */
+#define VIT_COR_INTSTAT (0x34)
+#define BER_DONE (0x08)
+#define BER_OVERFLOW (0x10)
+
+/* 0x38 OFDM_BERTimer */ /* Use the alias registers */
+#define A_VIT_BER_TIMER_0 (0x1D)
+
+/* 0x3A VIT_BER_TIMER_0 */ /* Use the alias registers */
+#define A_VIT_BER_0 (0x1B)
+
+/* 0x40 OFDM_COR_CTL */
+#define OFDM_COR_CTL (0x40)
+#define COREACT (0x20)
+#define HOLDSM (0x10)
+#define WAIT_AGC (0x02)
+#define WAIT_SYR (0x03)
+
+/* 0x41 OFDM_COR_STAT */
+#define OFDM_COR_STAT (0x41)
+#define COR_STATUS (0x0F)
+#define MONITOR_TPS (0x06)
+#define TPSLOCKED (0x40)
+#define AGCLOCKED (0x10)
+
+/* 0x42 OFDM_COR_INTEN */
+#define OFDM_COR_INTEN (0x42)
+#define TPSRCVBAD (0x04)
+#define TPSRCVCHANGED (0x02)
+#define TPSRCVUPDATE (0x01)
+
+/* 0x43 OFDM_COR_INSTAT */
+#define OFDM_COR_INSTAT (0x43)
+
+/* 0x44 OFDM_COR_MODEGUARD */
+#define OFDM_COR_MODEGUARD (0x44)
+#define FORCEMODE (0x08)
+#define FORCEMODE8K (0x04)
+
+/* 0x45 OFDM_AGC_CTL */
+#define OFDM_AGC_CTL (0x45)
+#define INITIAL_AGC_BW (0x08)
+#define AGCNEG (0x02)
+#define AGCLAST (0x10)
+
+/* 0x48 OFDM_AGC_TARGET */
+#define OFDM_AGC_TARGET (0x48)
+#define OFDM_AGC_TARGET_DEFAULT (0x28)
+#define OFDM_AGC_TARGET_IMPULSE (0x38)
+
+/* 0x49 OFDM_AGC_GAIN_1 */
+#define OFDM_AGC_GAIN_1 (0x49)
+
+/* 0x4B OFDM_ITB_CTL */
+#define OFDM_ITB_CTL (0x4B)
+#define ITBINV (0x01)
+
+/* 0x4C OFDM_ITB_FREQ_1 */
+#define OFDM_ITB_FREQ_1 (0x4C)
+
+/* 0x4D OFDM_ITB_FREQ_2 */
+#define OFDM_ITB_FREQ_2 (0x4D)
+
+/* 0x4E OFDM_CAS_CTL */
+#define OFDM_CAS_CTL (0x4E)
+#define ACSDIS (0x40)
+#define CCSEN (0x80)
+
+/* 0x4F CAS_FREQ */
+#define CAS_FREQ (0x4F)
+
+/* 0x51 OFDM_SYR_CTL */
+#define OFDM_SYR_CTL (0x51)
+#define SIXTH_ENABLE (0x80)
+#define SYR_TRACKING_DISABLE (0x01)
+
+/* 0x52 OFDM_SYR_STAT */
+#define OFDM_SYR_STAT (0x52)
+#define GI14_2K_SYR_LOCK (0x13)
+#define GI14_8K_SYR_LOCK (0x17)
+#define GI14_SYR_LOCK (0x10)
+
+/* 0x55 OFDM_SYR_OFFSET_1 */
+#define OFDM_SYR_OFFSET_1 (0x55)
+
+/* 0x56 OFDM_SYR_OFFSET_2 */
+#define OFDM_SYR_OFFSET_2 (0x56)
+
+/* 0x58 OFDM_SCR_CTL */
+#define OFDM_SCR_CTL (0x58)
+#define SYR_ADJ_DECAY_MASK (0x70)
+#define SYR_ADJ_DECAY (0x30)
+
+/* 0x59 OFDM_PPM_CTL_1 */
+#define OFDM_PPM_CTL_1 (0x59)
+#define PPMMAX_MASK (0x30)
+#define PPM256 (0x30)
+
+/* 0x5B OFDM_TRL_NOMINALRATE_1 */
+#define OFDM_TRL_NOMINALRATE_1 (0x5B)
+
+/* 0x5C OFDM_TRL_NOMINALRATE_2 */
+#define OFDM_TRL_NOMINALRATE_2 (0x5C)
+
+/* 0x5D OFDM_TRL_TIME_1 */
+#define OFDM_TRL_TIME_1 (0x5D)
+
+/* 0x60 OFDM_CRL_FREQ_1 */
+#define OFDM_CRL_FREQ_1 (0x60)
+
+/* 0x63 OFDM_CHC_CTL_1 */
+#define OFDM_CHC_CTL_1 (0x63)
+#define MANMEAN1 (0xF0);
+#define CHCFIR (0x01)
+
+/* 0x64 OFDM_CHC_SNR */
+#define OFDM_CHC_SNR (0x64)
+
+/* 0x65 OFDM_BDI_CTL */
+#define OFDM_BDI_CTL (0x65)
+#define LP_SELECT (0x02)
+
+/* 0x67 OFDM_TPS_RCVD_1 */
+#define OFDM_TPS_RCVD_1 (0x67)
+#define TPSFRAME (0x03)
+
+/* 0x68 OFDM_TPS_RCVD_2 */
+#define OFDM_TPS_RCVD_2 (0x68)
+
+/* 0x69 OFDM_TPS_RCVD_3 */
+#define OFDM_TPS_RCVD_3 (0x69)
+
+/* 0x6A OFDM_TPS_RCVD_4 */
+#define OFDM_TPS_RCVD_4 (0x6A)
+
+/* 0x6B OFDM_TPS_RESERVED_1 */
+#define OFDM_TPS_RESERVED_1 (0x6B)
+
+/* 0x6C OFDM_TPS_RESERVED_2 */
+#define OFDM_TPS_RESERVED_2 (0x6C)
+
+/* 0x73 OFDM_MSC_REV */
+#define OFDM_MSC_REV (0x73)
+
+/* 0x76 OFDM_SNR_CARRIER_2 */
+#define OFDM_SNR_CARRIER_2 (0x76)
+#define MEAN_MASK (0x80)
+#define MEANBIT (0x80)
+
+/* 0x80 ANALOG_CONTROL_0 */
+#define ANALOG_CONTROL_0 (0x80)
+#define POWER_DOWN_ADC (0x40)
+
+/* 0x81 ENABLE_TUNER_IIC */
+#define ENABLE_TUNER_IIC (0x81)
+#define ENABLE_TUNER_BIT (0x01)
+
+/* 0x82 EN_DMD_RACQ */
+#define EN_DMD_RACQ (0x82)
+#define EN_DMD_RACQ_REG_VAL (0x81)
+#define EN_DMD_RACQ_REG_VAL_14 (0x01)
+
+/* 0x84 SNR_COMMAND */
+#define SNR_COMMAND (0x84)
+#define SNRStat (0x80)
+
+/* 0x85 SNRCARRIERNUMBER_LSB */
+#define SNRCARRIERNUMBER_LSB (0x85)
+
+/* 0x87 SNRMINTHRESHOLD_LSB */
+#define SNRMINTHRESHOLD_LSB (0x87)
+
+/* 0x89 SNR_PER_CARRIER_LSB */
+#define SNR_PER_CARRIER_LSB (0x89)
+
+/* 0x8B SNRBELOWTHRESHOLD_LSB */
+#define SNRBELOWTHRESHOLD_LSB (0x8B)
+
+/* 0x91 RF_AGC_VAL_1 */
+#define RF_AGC_VAL_1 (0x91)
+
+/* 0x98 DIAG_CONFIG */
+#define DIAG_CONFIG (0x98)
+#define DIAG_MASK (0x70)
+#define TB_SET (0x10)
+#define TRAN_SELECT (0x07)
+#define SERIAL_SELECT (0x01)
+
+/* 0x99 SUB_DIAG_MODE_SEL */
+#define SUB_DIAG_MODE_SEL (0x99)
+#define CLKINVERSION (0x01)
+
+/* 0x9A TS_FORMAT */
+#define TS_FORMAT (0x9A)
+#define ERROR_SENSE (0x08)
+#define VALID_SENSE (0x04)
+#define SYNC_SENSE (0x02)
+#define GATED_CLOCK (0x01)
+
+#define NXT6000ASICDEVICE (0x0b)
+
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