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-rw-r--r--linux/arch/arm/mach-pxa/devices.c695
-rw-r--r--linux/arch/arm/mach-pxa/pcm990-baseboard.c416
2 files changed, 1111 insertions, 0 deletions
diff --git a/linux/arch/arm/mach-pxa/devices.c b/linux/arch/arm/mach-pxa/devices.c
new file mode 100644
index 000000000..3838aabdf
--- /dev/null
+++ b/linux/arch/arm/mach-pxa/devices.c
@@ -0,0 +1,695 @@
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/dma-mapping.h>
+
+#include <asm/arch/gpio.h>
+#include <asm/arch/udc.h>
+#include <asm/arch/pxafb.h>
+#include <asm/arch/mmc.h>
+#include <asm/arch/irda.h>
+#include <asm/arch/i2c.h>
+#include <asm/arch/ohci.h>
+#include <asm/arch/camera.h>
+
+#include "devices.h"
+
+void __init pxa_register_device(struct platform_device *dev, void *data)
+{
+ int ret;
+
+ dev->dev.platform_data = data;
+
+ ret = platform_device_register(dev);
+ if (ret)
+ dev_err(&dev->dev, "unable to register device: %d\n", ret);
+}
+
+static struct resource pxamci_resources[] = {
+ [0] = {
+ .start = 0x41100000,
+ .end = 0x41100fff,
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .start = IRQ_MMC,
+ .end = IRQ_MMC,
+ .flags = IORESOURCE_IRQ,
+ },
+ [2] = {
+ .start = 21,
+ .end = 21,
+ .flags = IORESOURCE_DMA,
+ },
+ [3] = {
+ .start = 22,
+ .end = 22,
+ .flags = IORESOURCE_DMA,
+ },
+};
+
+static u64 pxamci_dmamask = 0xffffffffUL;
+
+struct platform_device pxa_device_mci = {
+ .name = "pxa2xx-mci",
+ .id = 0,
+ .dev = {
+ .dma_mask = &pxamci_dmamask,
+ .coherent_dma_mask = 0xffffffff,
+ },
+ .num_resources = ARRAY_SIZE(pxamci_resources),
+ .resource = pxamci_resources,
+};
+
+void __init pxa_set_mci_info(struct pxamci_platform_data *info)
+{
+ pxa_register_device(&pxa_device_mci, info);
+}
+
+
+static struct pxa2xx_udc_mach_info pxa_udc_info;
+
+void __init pxa_set_udc_info(struct pxa2xx_udc_mach_info *info)
+{
+ memcpy(&pxa_udc_info, info, sizeof *info);
+}
+
+static struct resource pxa2xx_udc_resources[] = {
+ [0] = {
+ .start = 0x40600000,
+ .end = 0x4060ffff,
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .start = IRQ_USB,
+ .end = IRQ_USB,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+static u64 udc_dma_mask = ~(u32)0;
+
+struct platform_device pxa_device_udc = {
+ .name = "pxa2xx-udc",
+ .id = -1,
+ .resource = pxa2xx_udc_resources,
+ .num_resources = ARRAY_SIZE(pxa2xx_udc_resources),
+ .dev = {
+ .platform_data = &pxa_udc_info,
+ .dma_mask = &udc_dma_mask,
+ }
+};
+
+static struct resource pxafb_resources[] = {
+ [0] = {
+ .start = 0x44000000,
+ .end = 0x4400ffff,
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .start = IRQ_LCD,
+ .end = IRQ_LCD,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+static u64 fb_dma_mask = ~(u64)0;
+
+struct platform_device pxa_device_fb = {
+ .name = "pxa2xx-fb",
+ .id = -1,
+ .dev = {
+ .dma_mask = &fb_dma_mask,
+ .coherent_dma_mask = 0xffffffff,
+ },
+ .num_resources = ARRAY_SIZE(pxafb_resources),
+ .resource = pxafb_resources,
+};
+
+void __init set_pxa_fb_info(struct pxafb_mach_info *info)
+{
+ pxa_register_device(&pxa_device_fb, info);
+}
+
+void __init set_pxa_fb_parent(struct device *parent_dev)
+{
+ pxa_device_fb.dev.parent = parent_dev;
+}
+
+static struct resource pxa_resource_ffuart[] = {
+ {
+ .start = __PREG(FFUART),
+ .end = __PREG(FFUART) + 35,
+ .flags = IORESOURCE_MEM,
+ }, {
+ .start = IRQ_FFUART,
+ .end = IRQ_FFUART,
+ .flags = IORESOURCE_IRQ,
+ }
+};
+
+struct platform_device pxa_device_ffuart= {
+ .name = "pxa2xx-uart",
+ .id = 0,
+ .resource = pxa_resource_ffuart,
+ .num_resources = ARRAY_SIZE(pxa_resource_ffuart),
+};
+
+static struct resource pxa_resource_btuart[] = {
+ {
+ .start = __PREG(BTUART),
+ .end = __PREG(BTUART) + 35,
+ .flags = IORESOURCE_MEM,
+ }, {
+ .start = IRQ_BTUART,
+ .end = IRQ_BTUART,
+ .flags = IORESOURCE_IRQ,
+ }
+};
+
+struct platform_device pxa_device_btuart = {
+ .name = "pxa2xx-uart",
+ .id = 1,
+ .resource = pxa_resource_btuart,
+ .num_resources = ARRAY_SIZE(pxa_resource_btuart),
+};
+
+static struct resource pxa_resource_stuart[] = {
+ {
+ .start = __PREG(STUART),
+ .end = __PREG(STUART) + 35,
+ .flags = IORESOURCE_MEM,
+ }, {
+ .start = IRQ_STUART,
+ .end = IRQ_STUART,
+ .flags = IORESOURCE_IRQ,
+ }
+};
+
+struct platform_device pxa_device_stuart = {
+ .name = "pxa2xx-uart",
+ .id = 2,
+ .resource = pxa_resource_stuart,
+ .num_resources = ARRAY_SIZE(pxa_resource_stuart),
+};
+
+static struct resource pxa_resource_hwuart[] = {
+ {
+ .start = __PREG(HWUART),
+ .end = __PREG(HWUART) + 47,
+ .flags = IORESOURCE_MEM,
+ }, {
+ .start = IRQ_HWUART,
+ .end = IRQ_HWUART,
+ .flags = IORESOURCE_IRQ,
+ }
+};
+
+struct platform_device pxa_device_hwuart = {
+ .name = "pxa2xx-uart",
+ .id = 3,
+ .resource = pxa_resource_hwuart,
+ .num_resources = ARRAY_SIZE(pxa_resource_hwuart),
+};
+
+static struct resource pxai2c_resources[] = {
+ {
+ .start = 0x40301680,
+ .end = 0x403016a3,
+ .flags = IORESOURCE_MEM,
+ }, {
+ .start = IRQ_I2C,
+ .end = IRQ_I2C,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+struct platform_device pxa_device_i2c = {
+ .name = "pxa2xx-i2c",
+ .id = 0,
+ .resource = pxai2c_resources,
+ .num_resources = ARRAY_SIZE(pxai2c_resources),
+};
+
+void __init pxa_set_i2c_info(struct i2c_pxa_platform_data *info)
+{
+ pxa_register_device(&pxa_device_i2c, info);
+}
+
+static struct resource pxai2s_resources[] = {
+ {
+ .start = 0x40400000,
+ .end = 0x40400083,
+ .flags = IORESOURCE_MEM,
+ }, {
+ .start = IRQ_I2S,
+ .end = IRQ_I2S,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+struct platform_device pxa_device_i2s = {
+ .name = "pxa2xx-i2s",
+ .id = -1,
+ .resource = pxai2s_resources,
+ .num_resources = ARRAY_SIZE(pxai2s_resources),
+};
+
+static u64 pxaficp_dmamask = ~(u32)0;
+
+struct platform_device pxa_device_ficp = {
+ .name = "pxa2xx-ir",
+ .id = -1,
+ .dev = {
+ .dma_mask = &pxaficp_dmamask,
+ .coherent_dma_mask = 0xffffffff,
+ },
+};
+
+void __init pxa_set_ficp_info(struct pxaficp_platform_data *info)
+{
+ pxa_register_device(&pxa_device_ficp, info);
+}
+
+struct platform_device pxa_device_rtc = {
+ .name = "sa1100-rtc",
+ .id = -1,
+};
+
+#ifdef CONFIG_PXA25x
+
+static u64 pxa25x_ssp_dma_mask = DMA_BIT_MASK(32);
+
+static struct resource pxa25x_resource_ssp[] = {
+ [0] = {
+ .start = 0x41000000,
+ .end = 0x4100001f,
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .start = IRQ_SSP,
+ .end = IRQ_SSP,
+ .flags = IORESOURCE_IRQ,
+ },
+ [2] = {
+ /* DRCMR for RX */
+ .start = 13,
+ .end = 13,
+ .flags = IORESOURCE_DMA,
+ },
+ [3] = {
+ /* DRCMR for TX */
+ .start = 14,
+ .end = 14,
+ .flags = IORESOURCE_DMA,
+ },
+};
+
+struct platform_device pxa25x_device_ssp = {
+ .name = "pxa25x-ssp",
+ .id = 0,
+ .dev = {
+ .dma_mask = &pxa25x_ssp_dma_mask,
+ .coherent_dma_mask = DMA_BIT_MASK(32),
+ },
+ .resource = pxa25x_resource_ssp,
+ .num_resources = ARRAY_SIZE(pxa25x_resource_ssp),
+};
+
+static u64 pxa25x_nssp_dma_mask = DMA_BIT_MASK(32);
+
+static struct resource pxa25x_resource_nssp[] = {
+ [0] = {
+ .start = 0x41400000,
+ .end = 0x4140002f,
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .start = IRQ_NSSP,
+ .end = IRQ_NSSP,
+ .flags = IORESOURCE_IRQ,
+ },
+ [2] = {
+ /* DRCMR for RX */
+ .start = 15,
+ .end = 15,
+ .flags = IORESOURCE_DMA,
+ },
+ [3] = {
+ /* DRCMR for TX */
+ .start = 16,
+ .end = 16,
+ .flags = IORESOURCE_DMA,
+ },
+};
+
+struct platform_device pxa25x_device_nssp = {
+ .name = "pxa25x-nssp",
+ .id = 1,
+ .dev = {
+ .dma_mask = &pxa25x_nssp_dma_mask,
+ .coherent_dma_mask = DMA_BIT_MASK(32),
+ },
+ .resource = pxa25x_resource_nssp,
+ .num_resources = ARRAY_SIZE(pxa25x_resource_nssp),
+};
+
+static u64 pxa25x_assp_dma_mask = DMA_BIT_MASK(32);
+
+static struct resource pxa25x_resource_assp[] = {
+ [0] = {
+ .start = 0x41500000,
+ .end = 0x4150002f,
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .start = IRQ_ASSP,
+ .end = IRQ_ASSP,
+ .flags = IORESOURCE_IRQ,
+ },
+ [2] = {
+ /* DRCMR for RX */
+ .start = 23,
+ .end = 23,
+ .flags = IORESOURCE_DMA,
+ },
+ [3] = {
+ /* DRCMR for TX */
+ .start = 24,
+ .end = 24,
+ .flags = IORESOURCE_DMA,
+ },
+};
+
+struct platform_device pxa25x_device_assp = {
+ /* ASSP is basically equivalent to NSSP */
+ .name = "pxa25x-nssp",
+ .id = 2,
+ .dev = {
+ .dma_mask = &pxa25x_assp_dma_mask,
+ .coherent_dma_mask = DMA_BIT_MASK(32),
+ },
+ .resource = pxa25x_resource_assp,
+ .num_resources = ARRAY_SIZE(pxa25x_resource_assp),
+};
+#endif /* CONFIG_PXA25x */
+
+#if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
+
+static u64 pxa27x_ohci_dma_mask = DMA_BIT_MASK(32);
+
+static struct resource pxa27x_resource_ohci[] = {
+ [0] = {
+ .start = 0x4C000000,
+ .end = 0x4C00ff6f,
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .start = IRQ_USBH1,
+ .end = IRQ_USBH1,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+struct platform_device pxa27x_device_ohci = {
+ .name = "pxa27x-ohci",
+ .id = -1,
+ .dev = {
+ .dma_mask = &pxa27x_ohci_dma_mask,
+ .coherent_dma_mask = DMA_BIT_MASK(32),
+ },
+ .num_resources = ARRAY_SIZE(pxa27x_resource_ohci),
+ .resource = pxa27x_resource_ohci,
+};
+
+void __init pxa_set_ohci_info(struct pxaohci_platform_data *info)
+{
+ pxa_register_device(&pxa27x_device_ohci, info);
+}
+
+static u64 pxa27x_ssp1_dma_mask = DMA_BIT_MASK(32);
+
+static struct resource pxa27x_resource_ssp1[] = {
+ [0] = {
+ .start = 0x41000000,
+ .end = 0x4100003f,
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .start = IRQ_SSP,
+ .end = IRQ_SSP,
+ .flags = IORESOURCE_IRQ,
+ },
+ [2] = {
+ /* DRCMR for RX */
+ .start = 13,
+ .end = 13,
+ .flags = IORESOURCE_DMA,
+ },
+ [3] = {
+ /* DRCMR for TX */
+ .start = 14,
+ .end = 14,
+ .flags = IORESOURCE_DMA,
+ },
+};
+
+struct platform_device pxa27x_device_ssp1 = {
+ .name = "pxa27x-ssp",
+ .id = 0,
+ .dev = {
+ .dma_mask = &pxa27x_ssp1_dma_mask,
+ .coherent_dma_mask = DMA_BIT_MASK(32),
+ },
+ .resource = pxa27x_resource_ssp1,
+ .num_resources = ARRAY_SIZE(pxa27x_resource_ssp1),
+};
+
+static u64 pxa27x_ssp2_dma_mask = DMA_BIT_MASK(32);
+
+static struct resource pxa27x_resource_ssp2[] = {
+ [0] = {
+ .start = 0x41700000,
+ .end = 0x4170003f,
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .start = IRQ_SSP2,
+ .end = IRQ_SSP2,
+ .flags = IORESOURCE_IRQ,
+ },
+ [2] = {
+ /* DRCMR for RX */
+ .start = 15,
+ .end = 15,
+ .flags = IORESOURCE_DMA,
+ },
+ [3] = {
+ /* DRCMR for TX */
+ .start = 16,
+ .end = 16,
+ .flags = IORESOURCE_DMA,
+ },
+};
+
+struct platform_device pxa27x_device_ssp2 = {
+ .name = "pxa27x-ssp",
+ .id = 1,
+ .dev = {
+ .dma_mask = &pxa27x_ssp2_dma_mask,
+ .coherent_dma_mask = DMA_BIT_MASK(32),
+ },
+ .resource = pxa27x_resource_ssp2,
+ .num_resources = ARRAY_SIZE(pxa27x_resource_ssp2),
+};
+
+static u64 pxa27x_ssp3_dma_mask = DMA_BIT_MASK(32);
+
+static struct resource pxa27x_resource_ssp3[] = {
+ [0] = {
+ .start = 0x41900000,
+ .end = 0x4190003f,
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .start = IRQ_SSP3,
+ .end = IRQ_SSP3,
+ .flags = IORESOURCE_IRQ,
+ },
+ [2] = {
+ /* DRCMR for RX */
+ .start = 66,
+ .end = 66,
+ .flags = IORESOURCE_DMA,
+ },
+ [3] = {
+ /* DRCMR for TX */
+ .start = 67,
+ .end = 67,
+ .flags = IORESOURCE_DMA,
+ },
+};
+
+struct platform_device pxa27x_device_ssp3 = {
+ .name = "pxa27x-ssp",
+ .id = 2,
+ .dev = {
+ .dma_mask = &pxa27x_ssp3_dma_mask,
+ .coherent_dma_mask = DMA_BIT_MASK(32),
+ },
+ .resource = pxa27x_resource_ssp3,
+ .num_resources = ARRAY_SIZE(pxa27x_resource_ssp3),
+};
+
+static struct resource pxa27x_resource_camera[] = {
+ [0] = {
+ .start = 0x50000000,
+ .end = 0x50000fff,
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .start = IRQ_CAMERA,
+ .end = IRQ_CAMERA,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+static u64 pxa27x_dma_mask_camera = DMA_BIT_MASK(32);
+
+static struct platform_device pxa27x_device_camera = {
+ .name = "pxa27x-camera",
+ .id = 0, /* This is used to put cameras on this interface */
+ .dev = {
+ .dma_mask = &pxa27x_dma_mask_camera,
+ .coherent_dma_mask = 0xffffffff,
+ },
+ .num_resources = ARRAY_SIZE(pxa27x_resource_camera),
+ .resource = pxa27x_resource_camera,
+};
+
+void __init pxa_set_camera_info(struct pxacamera_platform_data *info)
+{
+ pxa_register_device(&pxa27x_device_camera, info);
+}
+#endif /* CONFIG_PXA27x || CONFIG_PXA3xx */
+
+#ifdef CONFIG_PXA3xx
+static u64 pxa3xx_ssp4_dma_mask = DMA_BIT_MASK(32);
+
+static struct resource pxa3xx_resource_ssp4[] = {
+ [0] = {
+ .start = 0x41a00000,
+ .end = 0x41a0003f,
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .start = IRQ_SSP4,
+ .end = IRQ_SSP4,
+ .flags = IORESOURCE_IRQ,
+ },
+ [2] = {
+ /* DRCMR for RX */
+ .start = 2,
+ .end = 2,
+ .flags = IORESOURCE_DMA,
+ },
+ [3] = {
+ /* DRCMR for TX */
+ .start = 3,
+ .end = 3,
+ .flags = IORESOURCE_DMA,
+ },
+};
+
+struct platform_device pxa3xx_device_ssp4 = {
+ /* PXA3xx SSP is basically equivalent to PXA27x */
+ .name = "pxa27x-ssp",
+ .id = 3,
+ .dev = {
+ .dma_mask = &pxa3xx_ssp4_dma_mask,
+ .coherent_dma_mask = DMA_BIT_MASK(32),
+ },
+ .resource = pxa3xx_resource_ssp4,
+ .num_resources = ARRAY_SIZE(pxa3xx_resource_ssp4),
+};
+
+static struct resource pxa3xx_resources_mci2[] = {
+ [0] = {
+ .start = 0x42000000,
+ .end = 0x42000fff,
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .start = IRQ_MMC2,
+ .end = IRQ_MMC2,
+ .flags = IORESOURCE_IRQ,
+ },
+ [2] = {
+ .start = 93,
+ .end = 93,
+ .flags = IORESOURCE_DMA,
+ },
+ [3] = {
+ .start = 94,
+ .end = 94,
+ .flags = IORESOURCE_DMA,
+ },
+};
+
+struct platform_device pxa3xx_device_mci2 = {
+ .name = "pxa2xx-mci",
+ .id = 1,
+ .dev = {
+ .dma_mask = &pxamci_dmamask,
+ .coherent_dma_mask = 0xffffffff,
+ },
+ .num_resources = ARRAY_SIZE(pxa3xx_resources_mci2),
+ .resource = pxa3xx_resources_mci2,
+};
+
+void __init pxa3xx_set_mci2_info(struct pxamci_platform_data *info)
+{
+ pxa_register_device(&pxa3xx_device_mci2, info);
+}
+
+static struct resource pxa3xx_resources_mci3[] = {
+ [0] = {
+ .start = 0x42500000,
+ .end = 0x42500fff,
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .start = IRQ_MMC3,
+ .end = IRQ_MMC3,
+ .flags = IORESOURCE_IRQ,
+ },
+ [2] = {
+ .start = 100,
+ .end = 100,
+ .flags = IORESOURCE_DMA,
+ },
+ [3] = {
+ .start = 101,
+ .end = 101,
+ .flags = IORESOURCE_DMA,
+ },
+};
+
+struct platform_device pxa3xx_device_mci3 = {
+ .name = "pxa2xx-mci",
+ .id = 2,
+ .dev = {
+ .dma_mask = &pxamci_dmamask,
+ .coherent_dma_mask = 0xffffffff,
+ },
+ .num_resources = ARRAY_SIZE(pxa3xx_resources_mci3),
+ .resource = pxa3xx_resources_mci3,
+};
+
+void __init pxa3xx_set_mci3_info(struct pxamci_platform_data *info)
+{
+ pxa_register_device(&pxa3xx_device_mci3, info);
+}
+
+#endif /* CONFIG_PXA3xx */
diff --git a/linux/arch/arm/mach-pxa/pcm990-baseboard.c b/linux/arch/arm/mach-pxa/pcm990-baseboard.c
new file mode 100644
index 000000000..07ac050f2
--- /dev/null
+++ b/linux/arch/arm/mach-pxa/pcm990-baseboard.c
@@ -0,0 +1,416 @@
+/*
+ * arch/arm/mach-pxa/pcm990-baseboard.c
+ * Support for the Phytec phyCORE-PXA270 Development Platform (PCM-990).
+ *
+ * Refer
+ * http://www.phytec.com/products/rdk/ARM-XScale/phyCORE-XScale-PXA270.html
+ * for additional hardware info
+ *
+ * Author: Juergen Kilb
+ * Created: April 05, 2005
+ * Copyright: Phytec Messtechnik GmbH
+ * e-Mail: armlinux@phytec.de
+ *
+ * based on Intel Mainstone Board
+ *
+ * Copyright 2007 Juergen Beisert @ Pengutronix (j.beisert@pengutronix.de)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/irq.h>
+#include <linux/platform_device.h>
+#include <linux/ide.h>
+#include <linux/i2c.h>
+
+#include <media/soc_camera.h>
+
+#include <asm/gpio.h>
+#include <asm/arch/i2c.h>
+#include <asm/arch/camera.h>
+#include <asm/mach/map.h>
+#include <asm/arch/pxa-regs.h>
+#include <asm/arch/mmc.h>
+#include <asm/arch/ohci.h>
+#include <asm/arch/pcm990_baseboard.h>
+
+/*
+ * The PCM-990 development baseboard uses PCM-027's hardeware in the
+ * following way:
+ *
+ * - LCD support is in use
+ * - GPIO16 is output for back light on/off with PWM
+ * - GPIO58 ... GPIO73 are outputs for display data
+ * - GPIO74 is output output for LCDFCLK
+ * - GPIO75 is output for LCDLCLK
+ * - GPIO76 is output for LCDPCLK
+ * - GPIO77 is output for LCDBIAS
+ * - MMC support is in use
+ * - GPIO32 is output for MMCCLK
+ * - GPIO92 is MMDAT0
+ * - GPIO109 is MMDAT1
+ * - GPIO110 is MMCS0
+ * - GPIO111 is MMCS1
+ * - GPIO112 is MMCMD
+ * - IDE/CF card is in use
+ * - GPIO48 is output /POE
+ * - GPIO49 is output /PWE
+ * - GPIO50 is output /PIOR
+ * - GPIO51 is output /PIOW
+ * - GPIO54 is output /PCE2
+ * - GPIO55 is output /PREG
+ * - GPIO56 is input /PWAIT
+ * - GPIO57 is output /PIOS16
+ * - GPIO79 is output PSKTSEL
+ * - GPIO85 is output /PCE1
+ * - FFUART is in use
+ * - GPIO34 is input FFRXD
+ * - GPIO35 is input FFCTS
+ * - GPIO36 is input FFDCD
+ * - GPIO37 is input FFDSR
+ * - GPIO38 is input FFRI
+ * - GPIO39 is output FFTXD
+ * - GPIO40 is output FFDTR
+ * - GPIO41 is output FFRTS
+ * - BTUART is in use
+ * - GPIO42 is input BTRXD
+ * - GPIO43 is output BTTXD
+ * - GPIO44 is input BTCTS
+ * - GPIO45 is output BTRTS
+ * - IRUART is in use
+ * - GPIO46 is input STDRXD
+ * - GPIO47 is output STDTXD
+ * - AC97 is in use*)
+ * - GPIO28 is input AC97CLK
+ * - GPIO29 is input AC97DatIn
+ * - GPIO30 is output AC97DatO
+ * - GPIO31 is output AC97SYNC
+ * - GPIO113 is output AC97_RESET
+ * - SSP is in use
+ * - GPIO23 is output SSPSCLK
+ * - GPIO24 is output chip select to Max7301
+ * - GPIO25 is output SSPTXD
+ * - GPIO26 is input SSPRXD
+ * - GPIO27 is input for Max7301 IRQ
+ * - GPIO53 is input SSPSYSCLK
+ * - SSP3 is in use
+ * - GPIO81 is output SSPTXD3
+ * - GPIO82 is input SSPRXD3
+ * - GPIO83 is output SSPSFRM
+ * - GPIO84 is output SSPCLK3
+ *
+ * Otherwise claimed GPIOs:
+ * GPIO1 -> IRQ from user switch
+ * GPIO9 -> IRQ from power management
+ * GPIO10 -> IRQ from WML9712 AC97 controller
+ * GPIO11 -> IRQ from IDE controller
+ * GPIO12 -> IRQ from CF controller
+ * GPIO13 -> IRQ from CF controller
+ * GPIO14 -> GPIO free
+ * GPIO15 -> /CS1 selects baseboard's Control CPLD (U7, 16 bit wide data path)
+ * GPIO19 -> GPIO free
+ * GPIO20 -> /SDCS2
+ * GPIO21 -> /CS3 PC card socket select
+ * GPIO33 -> /CS5 network controller select
+ * GPIO78 -> /CS2 (16 bit wide data path)
+ * GPIO80 -> /CS4 (16 bit wide data path)
+ * GPIO86 -> GPIO free
+ * GPIO87 -> GPIO free
+ * GPIO90 -> LED0 on CPU module
+ * GPIO91 -> LED1 on CPI module
+ * GPIO117 -> SCL
+ * GPIO118 -> SDA
+ */
+
+static unsigned long pcm990_irq_enabled;
+
+static void pcm990_mask_ack_irq(unsigned int irq)
+{
+ int pcm990_irq = (irq - PCM027_IRQ(0));
+ PCM990_INTMSKENA = (pcm990_irq_enabled &= ~(1 << pcm990_irq));
+}
+
+static void pcm990_unmask_irq(unsigned int irq)
+{
+ int pcm990_irq = (irq - PCM027_IRQ(0));
+ /* the irq can be acknowledged only if deasserted, so it's done here */
+ PCM990_INTSETCLR |= 1 << pcm990_irq;
+ PCM990_INTMSKENA = (pcm990_irq_enabled |= (1 << pcm990_irq));
+}
+
+static struct irq_chip pcm990_irq_chip = {
+ .mask_ack = pcm990_mask_ack_irq,
+ .unmask = pcm990_unmask_irq,
+};
+
+static void pcm990_irq_handler(unsigned int irq, struct irq_desc *desc)
+{
+ unsigned long pending = (~PCM990_INTSETCLR) & pcm990_irq_enabled;
+
+ do {
+ GEDR(PCM990_CTRL_INT_IRQ_GPIO) =
+ GPIO_bit(PCM990_CTRL_INT_IRQ_GPIO);
+ if (likely(pending)) {
+ irq = PCM027_IRQ(0) + __ffs(pending);
+ desc = irq_desc + irq;
+ desc_handle_irq(irq, desc);
+ }
+ pending = (~PCM990_INTSETCLR) & pcm990_irq_enabled;
+ } while (pending);
+}
+
+static void __init pcm990_init_irq(void)
+{
+ int irq;
+
+ /* setup extra PCM990 irqs */
+ for (irq = PCM027_IRQ(0); irq <= PCM027_IRQ(3); irq++) {
+ set_irq_chip(irq, &pcm990_irq_chip);
+ set_irq_handler(irq, handle_level_irq);
+ set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
+ }
+
+ PCM990_INTMSKENA = 0x00; /* disable all Interrupts */
+ PCM990_INTSETCLR = 0xFF;
+
+ set_irq_chained_handler(PCM990_CTRL_INT_IRQ, pcm990_irq_handler);
+ set_irq_type(PCM990_CTRL_INT_IRQ, PCM990_CTRL_INT_IRQ_EDGE);
+}
+
+static int pcm990_mci_init(struct device *dev, irq_handler_t mci_detect_int,
+ void *data)
+{
+ int err;
+
+ /*
+ * enable GPIO for PXA27x MMC controller
+ */
+ pxa_gpio_mode(GPIO32_MMCCLK_MD);
+ pxa_gpio_mode(GPIO112_MMCCMD_MD);
+ pxa_gpio_mode(GPIO92_MMCDAT0_MD);
+ pxa_gpio_mode(GPIO109_MMCDAT1_MD);
+ pxa_gpio_mode(GPIO110_MMCDAT2_MD);
+ pxa_gpio_mode(GPIO111_MMCDAT3_MD);
+
+ err = request_irq(PCM027_MMCDET_IRQ, mci_detect_int, IRQF_DISABLED,
+ "MMC card detect", data);
+ if (err)
+ printk(KERN_ERR "pcm990_mci_init: MMC/SD: can't request MMC "
+ "card detect IRQ\n");
+
+ return err;
+}
+
+static void pcm990_mci_setpower(struct device *dev, unsigned int vdd)
+{
+ struct pxamci_platform_data *p_d = dev->platform_data;
+
+ if ((1 << vdd) & p_d->ocr_mask)
+ __PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG5) =
+ PCM990_CTRL_MMC2PWR;
+ else
+ __PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG5) =
+ ~PCM990_CTRL_MMC2PWR;
+}
+
+static void pcm990_mci_exit(struct device *dev, void *data)
+{
+ free_irq(PCM027_MMCDET_IRQ, data);
+}
+
+#define MSECS_PER_JIFFY (1000/HZ)
+
+static struct pxamci_platform_data pcm990_mci_platform_data = {
+ .detect_delay = 250 / MSECS_PER_JIFFY,
+ .ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34,
+ .init = pcm990_mci_init,
+ .setpower = pcm990_mci_setpower,
+ .exit = pcm990_mci_exit,
+};
+
+/*
+ * init OHCI hardware to work with
+ *
+ * Note: Only USB port 1 (host only) is connected
+ *
+ * GPIO88 (USBHPWR#1): overcurrent in, overcurrent when low
+ * GPIO89 (USBHPEN#1): power-on out, on when low
+ */
+static int pcm990_ohci_init(struct device *dev)
+{
+ pxa_gpio_mode(PCM990_USB_OVERCURRENT);
+ pxa_gpio_mode(PCM990_USB_PWR_EN);
+ /*
+ * disable USB port 2 and 3
+ * power sense is active low
+ */
+ UHCHR = ((UHCHR) | UHCHR_PCPL | UHCHR_PSPL | UHCHR_SSEP2 |
+ UHCHR_SSEP3) & ~(UHCHR_SSEP1 | UHCHR_SSE);
+ /*
+ * wait 10ms after Power on
+ * overcurrent per port
+ * power switch per port
+ */
+ UHCRHDA = (5<<24) | (1<<11) | (1<<8); /* FIXME: Required? */
+
+ return 0;
+}
+
+static struct pxaohci_platform_data pcm990_ohci_platform_data = {
+ .port_mode = PMM_PERPORT_MODE,
+ .init = pcm990_ohci_init,
+ .exit = NULL,
+};
+
+/*
+ * PXA27x Camera specific stuff
+ */
+#if defined(CONFIG_VIDEO_PXA27x) || defined(CONFIG_VIDEO_PXA27x_MODULE)
+static int pcm990_pxacamera_init(struct device *dev)
+{
+ pxa_gpio_mode(GPIO98_CIF_DD0_MD);
+ pxa_gpio_mode(GPIO105_CIF_DD1_MD);
+ pxa_gpio_mode(GPIO104_CIF_DD2_MD);
+ pxa_gpio_mode(GPIO103_CIF_DD3_MD);
+ pxa_gpio_mode(GPIO95_CIF_DD4_MD);
+ pxa_gpio_mode(GPIO94_CIF_DD5_MD);
+ pxa_gpio_mode(GPIO93_CIF_DD6_MD);
+ pxa_gpio_mode(GPIO108_CIF_DD7_MD);
+ pxa_gpio_mode(GPIO107_CIF_DD8_MD);
+ pxa_gpio_mode(GPIO106_CIF_DD9_MD);
+ pxa_gpio_mode(GPIO42_CIF_MCLK_MD);
+ pxa_gpio_mode(GPIO45_CIF_PCLK_MD);
+ pxa_gpio_mode(GPIO43_CIF_FV_MD);
+ pxa_gpio_mode(GPIO44_CIF_LV_MD);
+
+ return 0;
+}
+
+/*
+ * CICR4: PCLK_EN: Pixel clock is supplied by the sensor
+ * MCLK_EN: Master clock is generated by PXA
+ * PCP: Data sampled on the falling edge of pixel clock
+ */
+struct pxacamera_platform_data pcm990_pxacamera_platform_data = {
+ .init = pcm990_pxacamera_init,
+ .flags = PXA_CAMERA_MASTER | PXA_CAMERA_DATAWIDTH_8 | PXA_CAMERA_DATAWIDTH_10 |
+ PXA_CAMERA_PCLK_EN | PXA_CAMERA_MCLK_EN/* | PXA_CAMERA_PCP*/,
+ .mclk_10khz = 1000,
+};
+
+#include <linux/i2c/pca953x.h>
+
+static struct pca953x_platform_data pca9536_data = {
+ .gpio_base = NR_BUILTIN_GPIO + 1,
+};
+
+static struct soc_camera_link iclink[] = {
+ {
+ .bus_id = 0, /* Must match with the camera ID above */
+ .gpio = NR_BUILTIN_GPIO + 1,
+ }, {
+ .bus_id = 0, /* Must match with the camera ID above */
+ }
+};
+
+/* Board I2C devices. */
+static struct i2c_board_info __initdata pcm990_i2c_devices[] = {
+ {
+ /* Must initialize before the camera(s) */
+ I2C_BOARD_INFO("pca953x", 0x41),
+ .type = "pca9536",
+ .platform_data = &pca9536_data,
+ }, {
+ I2C_BOARD_INFO("mt9v022", 0x48),
+ .type = "mt9v022",
+ .platform_data = &iclink[0], /* With extender */
+ }, {
+ I2C_BOARD_INFO("mt9m001", 0x5d),
+ .type = "mt9m001",
+ .platform_data = &iclink[0], /* With extender */
+ },
+};
+#endif /* CONFIG_VIDEO_PXA27x ||CONFIG_VIDEO_PXA27x_MODULE */
+
+/*
+ * AC97 support
+ * Note: The connected AC97 mixer also reports interrupts at PCM990_AC97_IRQ
+ */
+static struct resource pxa27x_ac97_resources[] = {
+ [0] = {
+ .start = 0x40500000,
+ .end = 0x40500000 + 0xfff,
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .start = IRQ_AC97,
+ .end = IRQ_AC97,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+static u64 pxa_ac97_dmamask = 0xffffffffUL;
+
+static struct platform_device pxa27x_device_ac97 = {
+ .name = "pxa2xx-ac97",
+ .id = -1,
+ .dev = {
+ .dma_mask = &pxa_ac97_dmamask,
+ .coherent_dma_mask = 0xffffffff,
+ },
+ .num_resources = ARRAY_SIZE(pxa27x_ac97_resources),
+ .resource = pxa27x_ac97_resources,
+};
+
+/*
+ * enable generic access to the base board control CPLDs U6 and U7
+ */
+static struct map_desc pcm990_io_desc[] __initdata = {
+ {
+ .virtual = PCM990_CTRL_BASE,
+ .pfn = __phys_to_pfn(PCM990_CTRL_PHYS),
+ .length = PCM990_CTRL_SIZE,
+ .type = MT_DEVICE /* CPLD */
+ }, {
+ .virtual = PCM990_CF_PLD_BASE,
+ .pfn = __phys_to_pfn(PCM990_CF_PLD_PHYS),
+ .length = PCM990_CF_PLD_SIZE,
+ .type = MT_DEVICE /* CPLD */
+ }
+};
+
+/*
+ * system init for baseboard usage. Will be called by pcm027 init.
+ *
+ * Add platform devices present on this baseboard and init
+ * them from CPU side as far as required to use them later on
+ */
+void __init pcm990_baseboard_init(void)
+{
+ /* register CPLD access */
+ iotable_init(pcm990_io_desc, ARRAY_SIZE(pcm990_io_desc));
+
+ /* register CPLD's IRQ controller */
+ pcm990_init_irq();
+
+ platform_device_register(&pxa27x_device_ac97);
+
+ /* MMC */
+ pxa_set_mci_info(&pcm990_mci_platform_data);
+
+ /* USB host */
+ pxa_set_ohci_info(&pcm990_ohci_platform_data);
+
+ pxa_set_i2c_info(NULL);
+
+#if defined(CONFIG_VIDEO_PXA27x) || defined(CONFIG_VIDEO_PXA27x_MODULE)
+ pxa_set_camera_info(&pcm990_pxacamera_platform_data);
+
+ i2c_register_board_info(0, pcm990_i2c_devices,
+ ARRAY_SIZE(pcm990_i2c_devices));
+#endif
+
+ printk(KERN_INFO"PCM-990 Evaluation baseboard initialized\n");
+}
generated by cgit v1.2.3 (git 2.25.1) at 2025-01-10 21:02:36 +0000