diff options
Diffstat (limited to 'linux/drivers/media/video/em28xx/em28xx-reg.h')
| -rw-r--r-- | linux/drivers/media/video/em28xx/em28xx-reg.h | 37 |
1 files changed, 36 insertions, 1 deletions
diff --git a/linux/drivers/media/video/em28xx/em28xx-reg.h b/linux/drivers/media/video/em28xx/em28xx-reg.h index 491d66abe..98e95054e 100644 --- a/linux/drivers/media/video/em28xx/em28xx-reg.h +++ b/linux/drivers/media/video/em28xx/em28xx-reg.h @@ -17,11 +17,34 @@ /* em28xx registers */ +#define EM28XX_R00_CHIPCFG 0x00 + +/* em28xx Chip Configuration 0x00 */ +#define EM28XX_CHIPCFG_VENDOR_AUDIO 0x80 +#define EM28XX_CHIPCFG_I2S_VOLUME_CAPABLE 0x40 +#define EM28XX_CHIPCFG_I2S_3_SAMPRATES 0x30 +#define EM28XX_CHIPCFG_I2S_5_SAMPRATES 0x20 +#define EM28XX_CHIPCFG_AC97 0x10 +#define EM28XX_CHIPCFG_AUDIOMASK 0x30 + /* GPIO/GPO registers */ #define EM2880_R04_GPO 0x04 /* em2880-em2883 only */ #define EM28XX_R08_GPIO 0x08 /* em2820 or upper */ #define EM28XX_R06_I2C_CLK 0x06 + +/* em28xx I2C Clock Register (0x06) */ +#define EM28XX_I2C_CLK_ACK_LAST_READ 0x80 +#define EM28XX_I2C_CLK_WAIT_ENABLE 0x40 +#define EM28XX_I2C_EEPROM_ON_BOARD 0x08 +#define EM28XX_I2C_EEPROM_KEY_VALID 0x04 +#define EM2874_I2C_SECONDARY_BUS_SELECT 0x04 /* em2874 has two i2c busses */ +#define EM28XX_I2C_FREQ_1_5_MHZ 0x03 /* bus frequency (bits [1-0]) */ +#define EM28XX_I2C_FREQ_25_KHZ 0x02 +#define EM28XX_I2C_FREQ_400_KHZ 0x01 +#define EM28XX_I2C_FREQ_100_KHZ 0x00 + + #define EM28XX_R0A_CHIPID 0x0a #define EM28XX_R0C_USBSUSP 0x0c /* */ @@ -120,10 +143,13 @@ enum em28xx_chip_id { /* Standard AC97 registers */ #define AC97_RESET 0x00 + + /* Output volumes */ #define AC97_MASTER_VOL 0x02 -#define AC97_LINE_LEVEL_VOL 0x04 +#define AC97_LINE_LEVEL_VOL 0x04 /* Some devices use for headphones */ #define AC97_MASTER_MONO_VOL 0x06 + /* Input volumes */ #define AC97_PC_BEEP_VOL 0x0a #define AC97_PHONE_VOL 0x0c #define AC97_MIC_VOL 0x0e @@ -132,8 +158,12 @@ enum em28xx_chip_id { #define AC97_VIDEO_VOL 0x14 #define AC97_AUX_VOL 0x16 #define AC97_PCM_OUT_VOL 0x18 + + /* capture registers */ #define AC97_RECORD_SELECT 0x1a #define AC97_RECORD_GAIN 0x1c + + /* control registers */ #define AC97_GENERAL_PURPOSE 0x20 #define AC97_3D_CTRL 0x22 #define AC97_AUD_INT_AND_PAG 0x24 @@ -148,10 +178,15 @@ enum em28xx_chip_id { #define AC97_PCM_OUT_SURR_SRATE 0x2e #define AC97_PCM_OUT_LFE_SRATE 0x30 #define AC97_PCM_IN_SRATE 0x32 + + /* For devices with more than 2 channels, extra output volumes */ #define AC97_LFE_MASTER_VOL 0x36 #define AC97_SURR_MASTER_VOL 0x38 + + /* Digital SPDIF output control */ #define AC97_SPDIF_OUT_CTRL 0x3a + /* Vendor ID identifier */ #define AC97_VENDOR_ID1 0x7c #define AC97_VENDOR_ID2 0x7e |