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| author | Alex Deucher <alexdeucher@gmail.com> | 2008-07-21 10:36:48 -0400 |
|---|---|---|
| committer | Brice Goglin <bgoglin@debian.org> | 2008-08-02 18:47:30 +0200 |
| commit | 1574d11f66b1f5479b8b2fe6919f7f5a0c3e6cf7 (patch) | |
| tree | 9bcd126f81975928696871ff2f012dbed2511714 | |
| parent | 1e99aaf7033e76c157572da23c31030aba0d5ce3 (diff) | |
| download | xf86-video-ati-frc-1574d11f66b1f5479b8b2fe6919f7f5a0c3e6cf7.tar.gz xf86-video-ati-frc-1574d11f66b1f5479b8b2fe6919f7f5a0c3e6cf7.tar.bz2 | |
Clear display priority bits before resetting them
(cherry picked from commit c18fad622a3c4f9572051120d83af68b625b5686)
| -rw-r--r-- | src/legacy_crtc.c | 3 | ||||
| -rw-r--r-- | src/radeon_reg.h | 2 |
2 files changed, 4 insertions, 1 deletions
diff --git a/src/legacy_crtc.c b/src/legacy_crtc.c index e5561e8..f7216f9 100644 --- a/src/legacy_crtc.c +++ b/src/legacy_crtc.c @@ -1369,6 +1369,8 @@ RADEONInitDispBandwidthLegacy(ScrnInfoPtr pScrn, */ if ((info->DispPriority == 2) && IS_R300_VARIANT) { uint32_t mc_init_misc_lat_timer = INREG(R300_MC_INIT_MISC_LAT_TIMER); + mc_init_misc_lat_timer &= ~(R300_MC_DISP1R_INIT_LAT_MASK << R300_MC_DISP1R_INIT_LAT_SHIFT); + mc_init_misc_lat_timer &= ~(R300_MC_DISP0R_INIT_LAT_MASK << R300_MC_DISP0R_INIT_LAT_SHIFT); if (pRADEONEnt->pCrtc[1]->enabled) mc_init_misc_lat_timer |= (1 << R300_MC_DISP1R_INIT_LAT_SHIFT); /* display 1 */ if (pRADEONEnt->pCrtc[0]->enabled) @@ -1376,7 +1378,6 @@ RADEONInitDispBandwidthLegacy(ScrnInfoPtr pScrn, OUTREG(R300_MC_INIT_MISC_LAT_TIMER, mc_init_misc_lat_timer); } - /* R420 and RV410 family not supported yet */ if (info->ChipFamily == CHIP_FAMILY_R420 || info->ChipFamily == CHIP_FAMILY_RV410) return; diff --git a/src/radeon_reg.h b/src/radeon_reg.h index 3967f95..dd47dc4 100644 --- a/src/radeon_reg.h +++ b/src/radeon_reg.h @@ -1033,7 +1033,9 @@ #define RADEON_NB_TOM 0x15c #define R300_MC_INIT_MISC_LAT_TIMER 0x180 # define R300_MC_DISP0R_INIT_LAT_SHIFT 8 +# define R300_MC_DISP0R_INIT_LAT_MASK 0xf # define R300_MC_DISP1R_INIT_LAT_SHIFT 12 +# define R300_MC_DISP1R_INIT_LAT_MASK 0xf #define RADEON_MCLK_CNTL 0x0012 /* PLL */ # define RADEON_FORCEON_MCLKA (1 << 16) # define RADEON_FORCEON_MCLKB (1 << 17) |