Merge branch 'master' of git://git.freedesktop.org/git/xorg/driver/xf86-video-ati into debian-experimental

20 files changed, 1535 insertions, 866 deletions

diff --git a/src/AtomBios/includes/CD_Common_Types.h b/src/AtomBios/includes/CD_Common_Types.h
index 44a0b35..bc18c42 100644
--- a/src/AtomBios/includes/CD_Common_Types.h
+++ b/src/AtomBios/includes/CD_Common_Types.h
@@ -37,6 +37,10 @@ Revision History:
 #ifndef _COMMON_TYPES_H_
 	#define _COMMON_TYPES_H_
 
+#ifdef HAVE_CONFIG_H
+#include "config.h"
+#endif
+
     #ifndef LINUX
 	#if _MSC_EXTENSIONS 
     
diff --git a/src/atombios_crtc.c b/src/atombios_crtc.c
index 6fbf7ed..51981a7 100644
--- a/src/atombios_crtc.c
+++ b/src/atombios_crtc.c
@@ -403,6 +403,9 @@ atombios_crtc_mode_set(xf86CrtcPtr crtc,
     ErrorF("Mode %dx%d - %d %d %d\n", adjusted_mode->CrtcHDisplay, adjusted_mode->CrtcVDisplay,
 	   adjusted_mode->CrtcHTotal, adjusted_mode->CrtcVTotal, adjusted_mode->Flags);
 
+    RADEONInitMemMapRegisters(pScrn, info->ModeReg, info);
+    RADEONRestoreMemMapRegisters(pScrn, info->ModeReg);
+
     if (IS_AVIVO_VARIANT) {
 	CARD32 fb_format;
 
@@ -448,12 +451,10 @@ atombios_crtc_mode_set(xf86CrtcPtr crtc,
 
 	OUTREG(AVIVO_D1GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0);
 	OUTREG(AVIVO_D1GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0);
-	OUTREG(AVIVO_D1GRPH_X_START + radeon_crtc->crtc_offset, 0);
-	OUTREG(AVIVO_D1GRPH_Y_START + radeon_crtc->crtc_offset, 0);
-	OUTREG(AVIVO_D1GRPH_X_END + radeon_crtc->crtc_offset,
-	       crtc->scrn->virtualX);
-	OUTREG(AVIVO_D1GRPH_Y_END + radeon_crtc->crtc_offset,
-	       crtc->scrn->virtualY);
+	OUTREG(AVIVO_D1GRPH_X_START + radeon_crtc->crtc_offset, x);
+	OUTREG(AVIVO_D1GRPH_Y_START + radeon_crtc->crtc_offset, y);
+	OUTREG(AVIVO_D1GRPH_X_END + radeon_crtc->crtc_offset, x + mode->HDisplay);
+	OUTREG(AVIVO_D1GRPH_Y_END + radeon_crtc->crtc_offset, y + mode->VDisplay);
 	OUTREG(AVIVO_D1GRPH_PITCH + radeon_crtc->crtc_offset,
 	       crtc->scrn->displayWidth);
 	OUTREG(AVIVO_D1GRPH_ENABLE + radeon_crtc->crtc_offset, 1);
@@ -465,7 +466,7 @@ atombios_crtc_mode_set(xf86CrtcPtr crtc,
 	OUTREG(AVIVO_D1SCL_UPDATE + radeon_crtc->crtc_offset, AVIVO_D1SCL_UPDATE_LOCK);
 
 	OUTREG(AVIVO_D1MODE_DESKTOP_HEIGHT + radeon_crtc->crtc_offset,
-	       crtc->scrn->virtualY);
+	       		mode->VDisplay);
 	OUTREG(AVIVO_D1MODE_VIEWPORT_START + radeon_crtc->crtc_offset, (x << 16) | y);
 	OUTREG(AVIVO_D1MODE_VIEWPORT_SIZE + radeon_crtc->crtc_offset,
 	       (mode->HDisplay << 16) | mode->VDisplay);
diff --git a/src/legacy_crtc.c b/src/legacy_crtc.c
index 0689114..5ef86ce 100644
--- a/src/legacy_crtc.c
+++ b/src/legacy_crtc.c
@@ -78,6 +78,13 @@ RADEONRestoreCommonRegisters(ScrnInfoPtr pScrn,
     OUTREG(RADEON_BUS_CNTL,           restore->bus_cntl);
     OUTREG(RADEON_SURFACE_CNTL,       restore->surface_cntl);
 
+    if (info->ChipFamily == CHIP_FAMILY_RS400) {
+	OUTREG(RS400_DISP2_REQ_CNTL1, restore->disp2_req_cntl1);
+	OUTREG(RS400_DISP2_REQ_CNTL2, restore->disp2_req_cntl2);
+	OUTREG(RS400_DMIF_MEM_CNTL1,  restore->dmif_mem_cntl1);
+	OUTREG(RS400_DISP1_REQ_CNTL1, restore->disp1_req_cntl1);
+    }
+
     /* Workaround for the VT switching problem in dual-head mode.  This
      * problem only occurs on RV style chips, typically when a FP and
      * CRT are connected.
@@ -178,12 +185,6 @@ RADEONRestoreCrtc2Registers(ScrnInfoPtr pScrn,
     OUTREG(RADEON_CRTC2_PITCH,           restore->crtc2_pitch);
     OUTREG(RADEON_DISP2_MERGE_CNTL,      restore->disp2_merge_cntl);
 
-    if (info->ChipFamily == CHIP_FAMILY_RS400) {
-	OUTREG(RADEON_RS480_UNK_e30, restore->rs480_unk_e30);
-	OUTREG(RADEON_RS480_UNK_e34, restore->rs480_unk_e34);
-	OUTREG(RADEON_RS480_UNK_e38, restore->rs480_unk_e38);
-	OUTREG(RADEON_RS480_UNK_e3c, restore->rs480_unk_e3c);
-    }
     OUTREG(RADEON_CRTC2_GEN_CNTL, restore->crtc2_gen_cntl);
 
 }
@@ -489,6 +490,13 @@ RADEONSaveCommonRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save)
     save->surface_cntl	     = INREG(RADEON_SURFACE_CNTL);
     save->grph_buffer_cntl   = INREG(RADEON_GRPH_BUFFER_CNTL);
     save->grph2_buffer_cntl  = INREG(RADEON_GRPH2_BUFFER_CNTL);
+
+    if (info->ChipFamily == CHIP_FAMILY_RS400) {
+	save->disp2_req_cntl1 = INREG(RS400_DISP2_REQ_CNTL1);
+	save->disp2_req_cntl2 = INREG(RS400_DISP2_REQ_CNTL2);
+	save->dmif_mem_cntl1  = INREG(RS400_DMIF_MEM_CNTL1);
+	save->disp1_req_cntl1 = INREG(RS400_DISP1_REQ_CNTL1);
+    }
 }
 
 /* Read CRTC registers */
@@ -550,13 +558,6 @@ RADEONSaveCrtc2Registers(ScrnInfoPtr pScrn, RADEONSavePtr save)
     save->fp_h2_sync_strt_wid   = INREG (RADEON_FP_H2_SYNC_STRT_WID);
     save->fp_v2_sync_strt_wid   = INREG (RADEON_FP_V2_SYNC_STRT_WID);
 
-    if (info->ChipFamily == CHIP_FAMILY_RS400) {
-	save->rs480_unk_e30 = INREG(RADEON_RS480_UNK_e30);
-	save->rs480_unk_e34 = INREG(RADEON_RS480_UNK_e34);
-	save->rs480_unk_e38 = INREG(RADEON_RS480_UNK_e38);
-	save->rs480_unk_e3c = INREG(RADEON_RS480_UNK_e3c);
-    }
-    
     save->disp2_merge_cntl      = INREG(RADEON_DISP2_MERGE_CNTL);
 
     /* track if the crtc is enabled for text restore */
@@ -677,6 +678,14 @@ RADEONInitCommonRegisters(RADEONSavePtr save, RADEONInfoPtr info)
     save->cap0_trig_cntl     = 0;
     save->cap1_trig_cntl     = 0;
     save->bus_cntl           = info->BusCntl;
+
+    if (info->ChipFamily == CHIP_FAMILY_RS400) {
+	save->disp2_req_cntl1 = info->SavedReg->disp2_req_cntl1;
+	save->disp2_req_cntl2 = info->SavedReg->disp2_req_cntl2;
+	save->dmif_mem_cntl1  = info->SavedReg->dmif_mem_cntl1;
+	save->disp1_req_cntl1 = info->SavedReg->disp1_req_cntl1;
+    }
+
     /*
      * If bursts are enabled, turn on discards
      * Radeon doesn't have write bursts
@@ -1125,13 +1134,6 @@ RADEONInitCrtc2Registers(xf86CrtcPtr crtc, RADEONSavePtr save,
     save->fp_h2_sync_strt_wid = save->crtc2_h_sync_strt_wid;
     save->fp_v2_sync_strt_wid = save->crtc2_v_sync_strt_wid;
 
-    if (info->ChipFamily == CHIP_FAMILY_RS400) {
-	save->rs480_unk_e30 = 0x105DC1CC; /* because I'm worth it */
-	save->rs480_unk_e34 = 0x2749D000; /* AMD really should */
-	save->rs480_unk_e38 = 0x29ca71dc; /* release docs */
-	save->rs480_unk_e3c = 0x28FBC3AC; /* this is so a trade secret */
-    }
-
     return TRUE;
 }
 
@@ -1554,6 +1556,24 @@ RADEONInitDispBandwidth2(ScrnInfoPtr pScrn, RADEONInfoPtr info, int pixel_bytes2
     OUTREG(RADEON_GRPH_BUFFER_CNTL, ((temp & ~RADEON_GRPH_CRITICAL_POINT_MASK) |
 				     (critical_point << RADEON_GRPH_CRITICAL_POINT_SHIFT)));
 
+#if 0
+    if (info->ChipFamily == CHIP_FAMILY_RS400) {
+	/* attempt to program RS400 disp regs correctly ??? */
+	temp = info->SavedReg->disp1_req_cntl1;
+	temp &= ~(RS400_DISP1_START_REQ_LEVEL_MASK |
+		  RS400_DISP1_STOP_REQ_LEVEL_MASK);
+	OUTREG(RS400_DISP1_REQ_CNTL1, (temp |
+				       (critical_point << RS400_DISP1_START_REQ_LEVEL_SHIFT) |
+				       (critical_point << RS400_DISP1_STOP_REQ_LEVEL_SHIFT)));
+	temp = info->SavedReg->dmif_mem_cntl1;
+	temp &= ~(RS400_DISP1_CRITICAL_POINT_START_MASK |
+		  RS400_DISP1_CRITICAL_POINT_STOP_MASK);
+	OUTREG(RS400_DMIF_MEM_CNTL1, (temp |
+				      (critical_point << RS400_DISP1_CRITICAL_POINT_START_SHIFT) |
+				      (critical_point << RS400_DISP1_CRITICAL_POINT_STOP_SHIFT)));
+    }
+#endif
+
     xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
 		   "GRPH_BUFFER_CNTL from %x to %x\n",
 		   (unsigned int)info->SavedReg->grph_buffer_cntl,
@@ -1604,6 +1624,28 @@ RADEONInitDispBandwidth2(ScrnInfoPtr pScrn, RADEONInfoPtr info, int pixel_bytes2
 	OUTREG(RADEON_GRPH2_BUFFER_CNTL, ((temp & ~RADEON_GRPH_CRITICAL_POINT_MASK) |
 					  (critical_point2 << RADEON_GRPH_CRITICAL_POINT_SHIFT)));
 
+	if (info->ChipFamily == CHIP_FAMILY_RS400) {
+#if 0
+	    /* attempt to program RS400 disp2 regs correctly ??? */
+	    temp = info->SavedReg->disp2_req_cntl1;
+	    temp &= ~(RS400_DISP2_START_REQ_LEVEL_MASK |
+		      RS400_DISP2_STOP_REQ_LEVEL_MASK);
+	    OUTREG(RS400_DISP2_REQ_CNTL1, (temp |
+					   (critical_point2 << RS400_DISP1_START_REQ_LEVEL_SHIFT) |
+					   (critical_point2 << RS400_DISP1_STOP_REQ_LEVEL_SHIFT)));
+	    temp = info->SavedReg->disp2_req_cntl2;
+	    temp &= ~(RS400_DISP2_CRITICAL_POINT_START_MASK |
+		      RS400_DISP2_CRITICAL_POINT_STOP_MASK);
+	    OUTREG(RS400_DISP2_REQ_CNTL2, (temp |
+					   (critical_point2 << RS400_DISP2_CRITICAL_POINT_START_SHIFT) |
+					   (critical_point2 << RS400_DISP2_CRITICAL_POINT_STOP_SHIFT)));
+#endif
+	    OUTREG(RS400_DISP2_REQ_CNTL1, 0x105DC1CC);
+	    OUTREG(RS400_DISP2_REQ_CNTL2, 0x2749D000);
+	    OUTREG(RS400_DMIF_MEM_CNTL1,  0x29CA71DC);
+	    OUTREG(RS400_DISP1_REQ_CNTL1, 0x28FBC3AC);
+	}
+
 	xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
 		       "GRPH2_BUFFER_CNTL from %x to %x\n",
 		       (unsigned int)info->SavedReg->grph2_buffer_cntl,
@@ -1682,6 +1724,8 @@ legacy_crtc_mode_set(xf86CrtcPtr crtc, DisplayModePtr mode,
     }
 
 
+    ErrorF("init memmap\n");
+    RADEONInitMemMapRegisters(pScrn, info->ModeReg, info);
     ErrorF("init common\n");
     RADEONInitCommonRegisters(info->ModeReg, info);
 
@@ -1735,6 +1779,8 @@ legacy_crtc_mode_set(xf86CrtcPtr crtc, DisplayModePtr mode,
 	}
     }
 
+    ErrorF("restore memmap\n");
+    RADEONRestoreMemMapRegisters(pScrn, info->ModeReg);
     ErrorF("restore common\n");
     RADEONRestoreCommonRegisters(pScrn, info->ModeReg);
 
@@ -1758,7 +1804,7 @@ legacy_crtc_mode_set(xf86CrtcPtr crtc, DisplayModePtr mode,
 	radeon_update_tv_routing(pScrn, info->ModeReg);
 
     if (info->DispPriority)
-	RADEONInitDispBandwidth(pScrn);
+        RADEONInitDispBandwidth(pScrn);
 
     if (tilingChanged) {
 	/* need to redraw front buffer, I guess this can be considered a hack ? */
diff --git a/src/legacy_output.c b/src/legacy_output.c
index 9dc7286..0d6e4f1 100644
--- a/src/legacy_output.c
+++ b/src/legacy_output.c
@@ -103,6 +103,12 @@ RADEONRestoreFPRegisters(ScrnInfoPtr pScrn, RADEONSavePtr restore)
     OUTREG(RADEON_TMDS_TRANSMITTER_CNTL,restore->tmds_transmitter_cntl);
     OUTREG(RADEON_FP_GEN_CNTL,          restore->fp_gen_cntl);
 
+    if (info->ChipFamily == CHIP_FAMILY_RS400) {
+	OUTREG(RS400_FP_2ND_GEN_CNTL, restore->fp_2nd_gen_cntl);
+	/*OUTREG(RS400_TMDS2_CNTL, restore->tmds2_cntl);*/
+	OUTREG(RS400_TMDS2_TRANSMITTER_CNTL, restore->tmds2_transmitter_cntl);
+    }
+
     /* old AIW Radeon has some BIOS initialization problem
      * with display buffer underflow, only occurs to DFP
      */
@@ -121,6 +127,8 @@ RADEONRestoreFP2Registers(ScrnInfoPtr pScrn, RADEONSavePtr restore)
 
     OUTREG(RADEON_FP2_GEN_CNTL,         restore->fp2_gen_cntl);
 
+    if (info->ChipFamily == CHIP_FAMILY_RS400)
+	OUTREG(RS400_FP2_2_GEN_CNTL, restore->fp2_2_gen_cntl);
 }
 
 /* Write RMX registers */
@@ -203,6 +211,14 @@ RADEONSaveFPRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save)
 	/* bit 22 of TMDS_PLL_CNTL is read-back inverted */
 	save->tmds_pll_cntl ^= (1 << 22);
     }
+
+    if (info->ChipFamily == CHIP_FAMILY_RS400) {
+	save->fp_2nd_gen_cntl         = INREG(RS400_FP_2ND_GEN_CNTL);
+	save->fp2_2_gen_cntl          = INREG(RS400_FP2_2_GEN_CNTL);
+	save->tmds2_cntl              = INREG(RS400_TMDS2_CNTL);
+	save->tmds2_transmitter_cntl  = INREG(RS400_TMDS2_TRANSMITTER_CNTL);
+    }
+
 }
 
 Bool
@@ -716,6 +732,13 @@ RADEONEnableDisplay(xf86OutputPtr output, BOOL bEnable)
 		tmp |= (RADEON_FP_FPON | RADEON_FP_TMDS_EN);
 		OUTREG(RADEON_FP_GEN_CNTL, tmp);
 		save->fp_gen_cntl |= (RADEON_FP_FPON | RADEON_FP_TMDS_EN);
+		if (info->ChipFamily == CHIP_FAMILY_RS400) {
+		    tmp = INREG(RS400_FP_2ND_GEN_CNTL);
+		    tmp |= (RS400_FP_2ND_ON | RS400_TMDS_2ND_EN);
+		    OUTREG(RS400_FP_2ND_GEN_CNTL, tmp);
+		    save->fp_2nd_gen_cntl |= (RS400_FP_2ND_ON |
+					      RS400_TMDS_2ND_EN);
+		}
 	    } else if (radeon_output->TMDSType == TMDS_EXT) {
 		info->output_dfp2 |= (1 << o);
 		tmp = INREG(RADEON_FP2_GEN_CNTL);
@@ -724,6 +747,14 @@ RADEONEnableDisplay(xf86OutputPtr output, BOOL bEnable)
 		OUTREG(RADEON_FP2_GEN_CNTL, tmp);
 		save->fp2_gen_cntl |= (RADEON_FP2_ON | RADEON_FP2_DVO_EN);
 		save->fp2_gen_cntl &= ~RADEON_FP2_BLANK_EN;
+		if (info->ChipFamily == CHIP_FAMILY_RS400) {
+		    tmp = INREG(RS400_FP2_2_GEN_CNTL);
+		    tmp &= ~RS400_FP2_2_BLANK_EN;
+		    tmp |= (RS400_FP2_2_ON | RS400_FP2_2_DVO2_EN);
+		    OUTREG(RS400_FP2_2_GEN_CNTL, tmp);
+		    save->fp2_2_gen_cntl |= (RS400_FP2_2_ON | RS400_FP2_2_DVO2_EN);
+		    save->fp2_2_gen_cntl &= ~RS400_FP2_2_BLANK_EN;
+		}
 	    }
 	} else if (radeon_output->MonType == MT_LCD) {
 	    info->output_lcd1 |= (1 << o);
@@ -780,6 +811,13 @@ RADEONEnableDisplay(xf86OutputPtr output, BOOL bEnable)
 		    tmp &= ~(RADEON_FP_FPON | RADEON_FP_TMDS_EN);
 		    OUTREG(RADEON_FP_GEN_CNTL, tmp);
 		    save->fp_gen_cntl &= ~(RADEON_FP_FPON | RADEON_FP_TMDS_EN);
+		    if (info->ChipFamily == CHIP_FAMILY_RS400) {
+			tmp = INREG(RS400_FP_2ND_GEN_CNTL);
+			tmp &= ~(RS400_FP_2ND_ON | RS400_TMDS_2ND_EN);
+			OUTREG(RS400_FP_2ND_GEN_CNTL, tmp);
+			save->fp_2nd_gen_cntl &= ~(RS400_FP_2ND_ON |
+						   RS400_TMDS_2ND_EN);
+		    }
 		}
 	    } else if (radeon_output->TMDSType == TMDS_EXT) {
 		info->output_dfp2 &= ~(1 << o);
@@ -790,6 +828,14 @@ RADEONEnableDisplay(xf86OutputPtr output, BOOL bEnable)
 		    OUTREG(RADEON_FP2_GEN_CNTL, tmp);
 		    save->fp2_gen_cntl &= ~(RADEON_FP2_ON | RADEON_FP2_DVO_EN);
 		    save->fp2_gen_cntl |= RADEON_FP2_BLANK_EN;
+		    if (info->ChipFamily == CHIP_FAMILY_RS400) {
+			tmp = INREG(RS400_FP2_2_GEN_CNTL);
+			tmp |= RS400_FP2_2_BLANK_EN;
+			tmp &= ~(RS400_FP2_2_ON | RS400_FP2_2_DVO2_EN);
+			OUTREG(RS400_FP2_2_GEN_CNTL, tmp);
+			save->fp2_2_gen_cntl &= ~(RS400_FP2_2_ON | RS400_FP2_2_DVO2_EN);
+			save->fp2_2_gen_cntl |= RS400_FP2_2_BLANK_EN;
+		    }
 		}
 	    }
 	} else if (radeon_output->MonType == MT_LCD) {
@@ -918,6 +964,29 @@ RADEONInitFPRegisters(xf86OutputPtr output, RADEONSavePtr save,
 	    save->fp_gen_cntl |= RADEON_FP_SEL_CRTC2;
     }
 
+    if (info->ChipFamily == CHIP_FAMILY_RS400) {
+	save->tmds2_transmitter_cntl = info->SavedReg->tmds2_transmitter_cntl &
+	    ~(RS400_TMDS2_PLLRST);
+	save->tmds2_transmitter_cntl &= ~(RS400_TMDS2_PLLEN);
+
+	save->fp_2nd_gen_cntl = info->SavedReg->fp_2nd_gen_cntl;
+
+	if (pScrn->rgbBits == 8)
+	    save->fp_2nd_gen_cntl |= RS400_PANEL_FORMAT_2ND;  /* 24 bit format */
+	else
+	    save->fp_2nd_gen_cntl &= ~RS400_PANEL_FORMAT_2ND;/* 18 bit format */
+
+	save->fp_2nd_gen_cntl &= ~RS400_FP_2ND_SOURCE_SEL_MASK;
+
+	if (IsPrimary) {
+	    if (radeon_output->Flags & RADEON_USE_RMX)
+		save->fp_2nd_gen_cntl |= RS400_FP_2ND_SOURCE_SEL_RMX;
+	    else
+		save->fp_2nd_gen_cntl |= RS400_FP_2ND_SOURCE_SEL_CRTC1;
+	} else
+	    save->fp_2nd_gen_cntl |= RS400_FP_2ND_SOURCE_SEL_CRTC2;
+    }
+
 }
 
 static void
@@ -954,6 +1023,8 @@ RADEONInitFP2Registers(xf86OutputPtr output, RADEONSavePtr save,
 	    save->fp2_gen_cntl &= ~R200_FP2_SOURCE_SEL_MASK;
 	    if (radeon_output->Flags & RADEON_USE_RMX)
 		save->fp2_gen_cntl |= R200_FP2_SOURCE_SEL_RMX;
+	    else
+		save->fp2_gen_cntl |= R200_FP2_SOURCE_SEL_CRTC1;
 	} else {
 	    save->fp2_gen_cntl &= ~RADEON_FP2_SRC_SEL_CRTC2;
 	}
@@ -966,6 +1037,27 @@ RADEONInitFP2Registers(xf86OutputPtr output, RADEONSavePtr save,
 	}
     }
 
+    if (info->ChipFamily == CHIP_FAMILY_RS400) {
+	if (pScrn->rgbBits == 8)
+	    save->fp2_2_gen_cntl = info->SavedReg->fp2_2_gen_cntl |
+		RS400_FP2_2_PANEL_FORMAT; /* 24 bit format, */
+	else
+	    save->fp2_2_gen_cntl = info->SavedReg->fp2_2_gen_cntl &
+		~RS400_FP2_2_PANEL_FORMAT;/* 18 bit format, */
+
+	save->fp2_2_gen_cntl &= ~(RS400_FP2_2_ON |
+				  RS400_FP2_2_DVO2_EN |
+				  RS400_FP2_2_SOURCE_SEL_MASK);
+
+	if (IsPrimary) {
+	    if (radeon_output->Flags & RADEON_USE_RMX)
+		save->fp2_2_gen_cntl |= RS400_FP2_2_SOURCE_SEL_RMX;
+	    else
+		save->fp2_2_gen_cntl |= RS400_FP2_2_SOURCE_SEL_CRTC1;
+	} else
+	    save->fp2_2_gen_cntl |= RS400_FP2_2_SOURCE_SEL_CRTC2;
+    }
+
 }
 
 static void
diff --git a/src/radeon.h b/src/radeon.h
index f3db451..feff48f 100644
--- a/src/radeon.h
+++ b/src/radeon.h
@@ -379,6 +379,9 @@ typedef struct {
     unsigned long     BIOSAddr;         /* BIOS physical address             */
     CARD32            fbLocation;
     CARD32            gartLocation;
+    CARD32            mc_fb_location;
+    CARD32            mc_agp_location;
+    CARD32            mc_agp_location_hi;
 
     void              *MMIO;            /* Map of MMIO region                */
     void              *FB;              /* Map of frame buffer               */
@@ -757,6 +760,9 @@ typedef struct {
 
     Bool              r600_shadow_fb;
     void *fb_shadow;
+
+    int num_gb_pipes;
+    Bool has_tcl;
 } RADEONInfoRec, *RADEONInfoPtr;
 
 #define RADEONWaitForFifo(pScrn, entries)				\
@@ -915,6 +921,10 @@ extern void RADEONPllErrataAfterData(RADEONInfoPtr info);
 extern void RADEONPllErrataAfterIndex(RADEONInfoPtr info);
 extern void RADEONWaitForVerticalSync(ScrnInfoPtr pScrn);
 extern void RADEONWaitForVerticalSync2(ScrnInfoPtr pScrn);
+extern void RADEONInitMemMapRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save,
+				      RADEONInfoPtr info);
+extern void RADEONRestoreMemMapRegisters(ScrnInfoPtr pScrn,
+					 RADEONSavePtr restore);
 
 #ifdef USE_EXA
 /* radeon_exa.c */
@@ -1181,15 +1191,27 @@ do {									\
 #define RADEON_PURGE_CACHE()						\
 do {									\
     BEGIN_RING(2);							\
-    OUT_RING(CP_PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0));		\
-    OUT_RING(RADEON_RB3D_DC_FLUSH_ALL);					\
+    if (info->ChipFamily <= CHIP_FAMILY_RV280) {                        \
+        OUT_RING(CP_PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0));		\
+        OUT_RING(RADEON_RB3D_DC_FLUSH_ALL);				\
+    } else {                                                            \
+        OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));		\
+        OUT_RING(R300_RB3D_DC_FLUSH_ALL);				\
+    }                                                                   \
     ADVANCE_RING();							\
 } while (0)
 
 #define RADEON_PURGE_ZCACHE()						\
 do {									\
-    OUT_RING(CP_PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0));		\
-    OUT_RING(RADEON_RB3D_ZC_FLUSH_ALL);					\
+    BEGIN_RING(2);							\
+    if (info->ChipFamily <= CHIP_FAMILY_RV280) {                        \
+        OUT_RING(CP_PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0));		\
+        OUT_RING(RADEON_RB3D_ZC_FLUSH_ALL);				\
+    } else {                                                            \
+        OUT_RING(CP_PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0));		\
+        OUT_RING(R300_ZC_FLUSH_ALL);					\
+    }                                                                   \
+    ADVANCE_RING();							\
 } while (0)
 
 #endif /* XF86DRI */
diff --git a/src/radeon_accel.c b/src/radeon_accel.c
index 015d176..9fecce6 100644
--- a/src/radeon_accel.c
+++ b/src/radeon_accel.c
@@ -158,17 +158,32 @@ void RADEONEngineFlush(ScrnInfoPtr pScrn)
     unsigned char *RADEONMMIO = info->MMIO;
     int            i;
 
-    OUTREGP(RADEON_RB3D_DSTCACHE_CTLSTAT,
-	    RADEON_RB3D_DC_FLUSH_ALL,
-	    ~RADEON_RB3D_DC_FLUSH_ALL);
-    for (i = 0; i < RADEON_TIMEOUT; i++) {
-	if (!(INREG(RADEON_RB3D_DSTCACHE_CTLSTAT) & RADEON_RB3D_DC_BUSY))
-	    break;
-    }
-    if (i == RADEON_TIMEOUT) {
-	xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
-		       "DC flush timeout: %x\n",
-		       (unsigned int)INREG(RADEON_RB3D_DSTCACHE_CTLSTAT));
+    if (info->ChipFamily <= CHIP_FAMILY_RV280) {
+	OUTREGP(RADEON_RB3D_DSTCACHE_CTLSTAT,
+		RADEON_RB3D_DC_FLUSH_ALL,
+		~RADEON_RB3D_DC_FLUSH_ALL);
+	for (i = 0; i < RADEON_TIMEOUT; i++) {
+	    if (!(INREG(RADEON_RB3D_DSTCACHE_CTLSTAT) & RADEON_RB3D_DC_BUSY))
+		break;
+	}
+	if (i == RADEON_TIMEOUT) {
+	    xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
+			   "DC flush timeout: %x\n",
+			   (unsigned int)INREG(RADEON_RB3D_DSTCACHE_CTLSTAT));
+	}
+    } else {
+	OUTREGP(R300_RB2D_DSTCACHE_CTLSTAT,
+		R300_RB2D_DC_FLUSH_ALL,
+		~R300_RB2D_DC_FLUSH_ALL);
+	for (i = 0; i < RADEON_TIMEOUT; i++) {
+	    if (!(INREG(R300_RB2D_DSTCACHE_CTLSTAT) & R300_RB2D_DC_BUSY))
+		break;
+	}
+	if (i == RADEON_TIMEOUT) {
+	    xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
+			   "DC flush timeout: %x\n",
+			   (unsigned int)INREG(R300_RB2D_DSTCACHE_CTLSTAT));
+	}
     }
 }
 
@@ -355,7 +370,52 @@ void RADEONEngineInit(ScrnInfoPtr pScrn)
 		   info->CurrentLayout.pixel_code,
 		   info->CurrentLayout.bitsPerPixel);
 
-    OUTREG(RADEON_RB3D_CNTL, 0);
+    if ((info->ChipFamily == CHIP_FAMILY_RV410) ||
+	(info->ChipFamily == CHIP_FAMILY_R420)  ||
+	(info->ChipFamily == CHIP_FAMILY_RS690) ||
+	(info->ChipFamily == CHIP_FAMILY_RS740) ||
+	(info->ChipFamily == CHIP_FAMILY_RS400) ||
+	IS_R500_3D) {
+	uint32_t gb_pipe_sel = INREG(R400_GB_PIPE_SELECT);
+	if (info->num_gb_pipes == 0) {
+	    info->num_gb_pipes = ((gb_pipe_sel >> 12) & 0x3) + 1;
+	    xf86DrvMsg(pScrn->scrnIndex, X_INFO,
+		       "%s: num pipes is %d\n", __FUNCTION__, info->num_gb_pipes);
+	}
+	if (IS_R500_3D)
+	    OUTPLL(pScrn, R500_DYN_SCLK_PWMEM_PIPE, (1 | ((gb_pipe_sel >> 8) & 0xf) << 4));
+    } else {
+	if (info->num_gb_pipes == 0) {
+	    if ((info->ChipFamily == CHIP_FAMILY_R300) ||
+		(info->ChipFamily == CHIP_FAMILY_R350)) {
+		/* R3xx chips */
+		info->num_gb_pipes = 2;
+	    } else {
+		/* RV3xx chips */
+		info->num_gb_pipes = 1;
+	    }
+	}
+    }
+
+    if (IS_R300_3D | IS_R500_3D) {
+	CARD32 gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16 | R300_SUBPIXEL_1_16);
+
+	switch(info->num_gb_pipes) {
+	case 2: gb_tile_config |= R300_PIPE_COUNT_R300; break;
+	case 3: gb_tile_config |= R300_PIPE_COUNT_R420_3P; break;
+	case 4: gb_tile_config |= R300_PIPE_COUNT_R420; break;
+	default:
+	case 1: gb_tile_config |= R300_PIPE_COUNT_RV350; break;
+	}
+
+	OUTREG(R300_GB_TILE_CONFIG, gb_tile_config);
+	OUTREG(R300_WAIT_UNTIL, R300_WAIT_2D_IDLECLEAN | R300_WAIT_3D_IDLECLEAN);
+	OUTREG(R300_DST_PIPE_CONFIG, INREG(R300_DST_PIPE_CONFIG) | R300_PIPE_AUTO_CONFIG);
+	OUTREG(R300_RB2D_DSTCACHE_MODE, (INREG(R300_RB2D_DSTCACHE_MODE) |
+					 R300_DC_AUTOFLUSH_ENABLE |
+					 R300_DC_DC_DISABLE_IGNORE_PE));
+    } else
+	OUTREG(RADEON_RB3D_CNTL, 0);
 
     RADEONEngineReset(pScrn);
 
diff --git a/src/radeon_accelfuncs.c b/src/radeon_accelfuncs.c
index e3b37c1..bda15ff 100644
--- a/src/radeon_accelfuncs.c
+++ b/src/radeon_accelfuncs.c
@@ -1302,15 +1302,16 @@ FUNC_NAME(RADEONAccelInit)(ScreenPtr pScreen, XAAInfoRecPtr a)
 	a->CPUToScreenTextureDstFormats = RADEONDstFormats;
 
 	if (IS_R300_VARIANT || IS_AVIVO_VARIANT) {
-	    xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Render acceleration "
-		       "unsupported on Radeon 9500/9700 and newer.\n");
+	    xf86DrvMsg(pScrn->scrnIndex, X_INFO, "XAA Render acceleration "
+		       "unsupported on Radeon 9500/9700 and newer. "
+		       "Please use EXA instead.\n");
 	} else if ((info->ChipFamily == CHIP_FAMILY_RV250) || 
 		   (info->ChipFamily == CHIP_FAMILY_RV280) || 
 		   (info->ChipFamily == CHIP_FAMILY_RS300) || 
 		   (info->ChipFamily == CHIP_FAMILY_R200)) {
 	    a->SetupForCPUToScreenAlphaTexture2 =
 		FUNC_NAME(R200SetupForCPUToScreenAlphaTexture);
-	    a->SubsequentCPUToScreenAlphaTexture = 
+	    a->SubsequentCPUToScreenAlphaTexture =
 		FUNC_NAME(R200SubsequentCPUToScreenTexture);
 
 	    a->SetupForCPUToScreenTexture2 =
diff --git a/src/radeon_atombios.c b/src/radeon_atombios.c
index 85a2e71..224aae3 100644
--- a/src/radeon_atombios.c
+++ b/src/radeon_atombios.c
@@ -35,6 +35,8 @@
 #include "radeon_probe.h"
 #include "radeon_macros.h"
 
+#include "ati_pciids_gen.h"
+
 #include "xorg-server.h"
 
 /* only for testing now */
@@ -517,25 +519,52 @@ rhdAtomASICInit(atomBiosHandlePtr handle)
     return FALSE;
 }
 
-Bool
-rhdAtomSetScaler(atomBiosHandlePtr handle, unsigned char scalerID, int setting)
+int
+atombios_dyn_clk_setup(ScrnInfoPtr pScrn, int enable)
 {
-    ENABLE_SCALER_PARAMETERS scaler;
+    RADEONInfoPtr info       = RADEONPTR(pScrn);
+    DYNAMIC_CLOCK_GATING_PS_ALLOCATION dynclk_data;
     AtomBiosArgRec data;
+    unsigned char *space;
 
-    scaler.ucScaler = scalerID;
-    scaler.ucEnable = setting;
-    data.exec.dataSpace = NULL;
-    data.exec.index = 0x21;
-    data.exec.pspace = &scaler;
-    xf86DrvMsg(handle->scrnIndex, X_INFO, "Calling EnableScaler\n");
-    if (RHDAtomBiosFunc(handle->scrnIndex, handle,
-			ATOMBIOS_EXEC, &data) == ATOM_SUCCESS) {
-	xf86DrvMsg(handle->scrnIndex, X_INFO, "EnableScaler Successful\n");
-	return TRUE;
+    dynclk_data.ucEnable = enable;
+
+    data.exec.index = GetIndexIntoMasterTable(COMMAND, DynamicClockGating);
+    data.exec.dataSpace = (void *)&space;
+    data.exec.pspace = &dynclk_data;
+
+    if (RHDAtomBiosFunc(info->atomBIOS->scrnIndex, info->atomBIOS, ATOMBIOS_EXEC, &data) == ATOM_SUCCESS) {
+	ErrorF("Dynamic clock gating %s success\n", enable? "enable" : "disable");
+	return ATOM_SUCCESS;
     }
-    xf86DrvMsg(handle->scrnIndex, X_INFO, "EableScaler Failed\n");
-    return FALSE;
+
+    ErrorF("Dynamic clock gating %s failure\n", enable? "enable" : "disable");
+    return ATOM_NOT_IMPLEMENTED;
+
+}
+
+int
+atombios_static_pwrmgt_setup(ScrnInfoPtr pScrn, int enable)
+{
+    RADEONInfoPtr info       = RADEONPTR(pScrn);
+    ENABLE_ASIC_STATIC_PWR_MGT_PS_ALLOCATION pwrmgt_data;
+    AtomBiosArgRec data;
+    unsigned char *space;
+
+    pwrmgt_data.ucEnable = enable;
+
+    data.exec.index = GetIndexIntoMasterTable(COMMAND, EnableASIC_StaticPwrMgt);
+    data.exec.dataSpace = (void *)&space;
+    data.exec.pspace = &pwrmgt_data;
+
+    if (RHDAtomBiosFunc(info->atomBIOS->scrnIndex, info->atomBIOS, ATOMBIOS_EXEC, &data) == ATOM_SUCCESS) {
+	ErrorF("Static power management %s success\n", enable? "enable" : "disable");
+	return ATOM_SUCCESS;
+    }
+
+    ErrorF("Static power management %s failure\n", enable? "enable" : "disable");
+    return ATOM_NOT_IMPLEMENTED;
+
 }
 
 # endif
@@ -1747,6 +1776,22 @@ RADEONATOMGetTVTimings(ScrnInfoPtr pScrn, int index, SET_CRTC_TIMING_PARAMETERS_
     return TRUE;
 }
 
+static void RADEONApplyATOMQuirks(ScrnInfoPtr pScrn, int index)
+{
+    RADEONInfoPtr info = RADEONPTR (pScrn);
+
+    /* Asus M2A-VM HDMI board lists the DVI port as HDMI */
+    if ((info->Chipset == PCI_CHIP_RS690_791E) &&
+	(PCI_SUB_VENDOR_ID(info->PciInfo) == 0x1043) &&
+	(PCI_SUB_DEVICE_ID(info->PciInfo) == 0x826d)) {
+	if ((info->BiosConnector[index].ConnectorType == CONNECTOR_HDMI_TYPE_A) &&
+	    (info->BiosConnector[index].TMDSType == TMDS_LVTMA)) {
+	    info->BiosConnector[index].ConnectorType = CONNECTOR_DVI_D;
+	}
+    }
+
+}
+
 Bool
 RADEONGetATOMConnectorInfoFromBIOSConnectorTable (ScrnInfoPtr pScrn)
 {
@@ -1849,6 +1894,9 @@ RADEONGetATOMConnectorInfoFromBIOSConnectorTable (ScrnInfoPtr pScrn)
 	} else {
 	    info->BiosConnector[i].hpd_mask = 0;
 	}
+
+	RADEONApplyATOMQuirks(pScrn, i);
+
     }
 
     /* CRTs/DFPs may share a port */
diff --git a/src/radeon_atombios.h b/src/radeon_atombios.h
index 9cb279e..955f2e4 100644
--- a/src/radeon_atombios.h
+++ b/src/radeon_atombios.h
@@ -116,6 +116,12 @@ RADEONGetATOMConnectorInfoFromBIOSObject (ScrnInfoPtr pScrn);
 extern Bool
 RADEONGetATOMConnectorInfoFromBIOSConnectorTable (ScrnInfoPtr pScrn);
 
+extern int
+atombios_dyn_clk_setup(ScrnInfoPtr pScrn, int enable);
+
+extern int
+atombios_static_pwrmgt_setup(ScrnInfoPtr pScrn, int enable);
+
 extern Bool
 RADEONGetATOMTVInfo(xf86OutputPtr output);
 
diff --git a/src/radeon_bios.c b/src/radeon_bios.c
index a32188d..6be3528 100644
--- a/src/radeon_bios.c
+++ b/src/radeon_bios.c
@@ -75,7 +75,8 @@ Bool RADEONGetBIOSInfo(ScrnInfoPtr pScrn, xf86Int10InfoPtr  pInt10)
 
 #ifdef XSERVER_LIBPCIACCESS
     //info->VBIOS = xalloc(info->PciInfo->rom_size);
-    info->VBIOS = xalloc(RADEON_VBIOS_SIZE);
+    int size = info->PciInfo->rom_size > RADEON_VBIOS_SIZE ? info->PciInfo->rom_size : RADEON_VBIOS_SIZE;
+    info->VBIOS = xalloc(size);
 #else
     info->VBIOS = xalloc(RADEON_VBIOS_SIZE);
 #endif
@@ -216,6 +217,54 @@ static Bool RADEONGetATOMConnectorInfoFromBIOS (ScrnInfoPtr pScrn)
     return FALSE;
 }
 
+static void RADEONApplyLegacyQuirks(ScrnInfoPtr pScrn, int index)
+{
+    RADEONInfoPtr info = RADEONPTR (pScrn);
+
+    /* most XPRESS chips seem to specify DDC_CRT2 for their 
+     * VGA DDC port, however DDC never seems to work on that
+     * port.  Some have reported success on DDC_MONID, so 
+     * lets see what happens with that.
+     */
+    if (info->ChipFamily == CHIP_FAMILY_RS400 &&
+	info->BiosConnector[index].ConnectorType == CONNECTOR_VGA &&
+	info->BiosConnector[index].ddc_i2c.mask_clk_reg == RADEON_GPIO_CRT2_DDC) {
+	info->BiosConnector[index].ddc_i2c = legacy_setup_i2c_bus(RADEON_GPIO_MONID);
+    }
+    
+    /* XPRESS desktop chips seem to have a proprietary connector listed for
+     * DVI-D, try and do the right thing here.
+     */
+    if ((!info->IsMobility) &&
+	(info->BiosConnector[index].ConnectorType == CONNECTOR_LVDS)) {
+	xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
+		   "Proprietary connector found, assuming DVI-D\n");
+	info->BiosConnector[index].DACType = DAC_NONE;
+	info->BiosConnector[index].TMDSType = TMDS_EXT;
+	info->BiosConnector[index].ConnectorType = CONNECTOR_DVI_D;
+    }
+
+    /* Certain IBM chipset RN50s have a BIOS reporting two VGAs,
+       one with VGA DDC and one with CRT2 DDC. - kill the CRT2 DDC one */
+    if (info->Chipset == PCI_CHIP_RN50_515E &&
+	PCI_SUB_VENDOR_ID(info->PciInfo) == 0x1014) {
+	if (info->BiosConnector[index].ConnectorType == CONNECTOR_VGA &&
+	    info->BiosConnector[index].ddc_i2c.mask_clk_reg == RADEON_GPIO_CRT2_DDC) {
+	    info->BiosConnector[index].valid = FALSE;
+	}
+    }
+
+    /* Some RV100 cards with 2 VGA ports show up with DVI+VGA */
+    if (info->Chipset == PCI_CHIP_RV100_QY &&
+	PCI_SUB_VENDOR_ID(info->PciInfo) == 0x1002 &&
+	PCI_SUB_DEVICE_ID(info->PciInfo) == 0x013a) {
+	if (info->BiosConnector[index].ConnectorType == CONNECTOR_DVI_I) {
+	    info->BiosConnector[index].ConnectorType = CONNECTOR_VGA;
+	}
+    }
+
+}
+
 static Bool RADEONGetLegacyConnectorInfoFromBIOS (ScrnInfoPtr pScrn)
 {
     RADEONInfoPtr info = RADEONPTR (pScrn);
@@ -297,28 +346,8 @@ static Bool RADEONGetLegacyConnectorInfoFromBIOS (ScrnInfoPtr pScrn)
 	    else
 		info->BiosConnector[i].TMDSType = TMDS_INT;
 
-	    /* most XPRESS chips seem to specify DDC_CRT2 for their 
-	     * VGA DDC port, however DDC never seems to work on that
-	     * port.  Some have reported success on DDC_MONID, so 
-	     * lets see what happens with that.
-	     */
-	    if (info->ChipFamily == CHIP_FAMILY_RS400 &&
-		info->BiosConnector[i].ConnectorType == CONNECTOR_VGA &&
-		info->BiosConnector[i].ddc_i2c.mask_clk_reg == RADEON_GPIO_CRT2_DDC) {
-		info->BiosConnector[i].ddc_i2c = legacy_setup_i2c_bus(RADEON_GPIO_MONID);
-	    }
+	    RADEONApplyLegacyQuirks(pScrn, i);
 
-	    /* XPRESS desktop chips seem to have a proprietary connector listed for
-	     * DVI-D, try and do the right thing here.
-	    */
-	    if ((!info->IsMobility) &&
-		(info->BiosConnector[i].ConnectorType == CONNECTOR_LVDS)) {
-		xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
-			   "Proprietary connector found, assuming DVI-D\n");
-		info->BiosConnector[i].DACType = DAC_NONE;
-		info->BiosConnector[i].TMDSType = TMDS_EXT;
-		info->BiosConnector[i].ConnectorType = CONNECTOR_DVI_D;
-	    }
 	}
     } else {
 	xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "No Connector Info Table found!\n");
diff --git a/src/radeon_commonfuncs.c b/src/radeon_commonfuncs.c
index 45dc14b..c249c43 100644
--- a/src/radeon_commonfuncs.c
+++ b/src/radeon_commonfuncs.c
@@ -55,14 +55,12 @@
 static void FUNC_NAME(RADEONInit3DEngine)(ScrnInfoPtr pScrn)
 {
     RADEONInfoPtr  info       = RADEONPTR(pScrn);
-    CARD32 gb_tile_config;
+    CARD32 gb_tile_config, su_reg_dest, vap_cntl;
     ACCEL_PREAMBLE();
 
     info->texW[0] = info->texH[0] = info->texW[1] = info->texH[1] = 1;
 
-    if (IS_R300_VARIANT || IS_AVIVO_VARIANT ||
-	(info->ChipFamily == CHIP_FAMILY_RS690) ||
-	(info->ChipFamily == CHIP_FAMILY_RS740)) {
+    if (IS_R300_3D || IS_R500_3D) {
 
 	BEGIN_ACCEL(3);
 	OUT_ACCEL_REG(R300_RB3D_DSTCACHE_CTLSTAT, R300_DC_FLUSH_3D | R300_DC_FREE_3D);
@@ -72,35 +70,30 @@ static void FUNC_NAME(RADEONInit3DEngine)(ScrnInfoPtr pScrn)
 
 	gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16 | R300_SUBPIXEL_1_16);
 
-	if ((info->Chipset == PCI_CHIP_RV410_5E4C) ||
-	    (info->Chipset == PCI_CHIP_RV410_5E4F)) {
-	    /* RV410 SE chips */
-	    gb_tile_config |= R300_PIPE_COUNT_RV350;
-	} else if ((info->ChipFamily == CHIP_FAMILY_RV350) ||
-		   (info->ChipFamily == CHIP_FAMILY_RV380) ||
-		   (info->ChipFamily == CHIP_FAMILY_RS400)) {
-	    /* RV3xx, RS4xx chips */
-	    gb_tile_config |= R300_PIPE_COUNT_RV350;
-	} else if ((info->ChipFamily == CHIP_FAMILY_R300) ||
-		   (info->ChipFamily == CHIP_FAMILY_R350)) {
-	    /* R3xx chips */
-	    gb_tile_config |= R300_PIPE_COUNT_R300;
-	} else if ((info->ChipFamily == CHIP_FAMILY_RV410) ||
-		   (info->ChipFamily == CHIP_FAMILY_RS690) ||
-		   (info->ChipFamily == CHIP_FAMILY_RS740)) {
-	    /* RV4xx, RS6xx chips */
-	    gb_tile_config |= R300_PIPE_COUNT_R420_3P;
-	} else {
-	    /* R4xx, R5xx chips */
-	    gb_tile_config |= R300_PIPE_COUNT_R420;
+	switch(info->num_gb_pipes) {
+	case 2: gb_tile_config |= R300_PIPE_COUNT_R300; break;
+	case 3: gb_tile_config |= R300_PIPE_COUNT_R420_3P; break;
+	case 4: gb_tile_config |= R300_PIPE_COUNT_R420; break;
+	default:
+	case 1: gb_tile_config |= R300_PIPE_COUNT_RV350; break;
 	}
 
-	BEGIN_ACCEL(3);
+	BEGIN_ACCEL(5);
 	OUT_ACCEL_REG(R300_GB_TILE_CONFIG, gb_tile_config);
+	OUT_ACCEL_REG(R300_WAIT_UNTIL, R300_WAIT_2D_IDLECLEAN | R300_WAIT_3D_IDLECLEAN);
+	OUT_ACCEL_REG(R300_DST_PIPE_CONFIG, R300_PIPE_AUTO_CONFIG);
 	OUT_ACCEL_REG(R300_GB_SELECT, 0);
 	OUT_ACCEL_REG(R300_GB_ENABLE, 0);
 	FINISH_ACCEL();
 
+	if (IS_R500_3D) {
+	    su_reg_dest = ((1 << info->num_gb_pipes) - 1);
+	    BEGIN_ACCEL(2);
+	    OUT_ACCEL_REG(R500_SU_REG_DEST, su_reg_dest);
+	    OUT_ACCEL_REG(R500_VAP_INDEX_OFFSET, 0);
+	    FINISH_ACCEL();
+	}
+
 	BEGIN_ACCEL(3);
 	OUT_ACCEL_REG(R300_RB3D_DSTCACHE_CTLSTAT, R300_DC_FLUSH_3D | R300_DC_FREE_3D);
 	OUT_ACCEL_REG(R300_RB3D_ZCACHE_CTLSTAT, R300_ZC_FLUSH | R300_ZC_FREE);
@@ -128,7 +121,8 @@ static void FUNC_NAME(RADEONInit3DEngine)(ScrnInfoPtr pScrn)
 				       (8 << R300_MSBD1_SHIFT)));
 	FINISH_ACCEL();
 
-	BEGIN_ACCEL(4);
+	BEGIN_ACCEL(5);
+	OUT_ACCEL_REG(R300_GA_ENHANCE, R300_GA_DEADLOCK_CNTL | R300_GA_FASTSYNC_CNTL);
 	OUT_ACCEL_REG(R300_GA_POLY_MODE, R300_FRONT_PTYPE_TRIANGE | R300_BACK_PTYPE_TRIANGE);
 	OUT_ACCEL_REG(R300_GA_ROUND_MODE, (R300_GEOMETRY_ROUND_NEAREST |
 					   R300_COLOR_ROUND_NEAREST));
@@ -151,7 +145,394 @@ static void FUNC_NAME(RADEONInit3DEngine)(ScrnInfoPtr pScrn)
 	OUT_ACCEL_REG(R300_SU_DEPTH_OFFSET, 0);
 	FINISH_ACCEL();
 
-	BEGIN_ACCEL(5);
+	/* setup the VAP */
+	vap_cntl = ((5 << R300_PVS_NUM_SLOTS_SHIFT) |
+		    (5 << R300_PVS_NUM_CNTLRS_SHIFT) |
+		    (9/*12*/ << R300_VF_MAX_VTX_NUM_SHIFT));
+
+	if (info->ChipFamily == CHIP_FAMILY_RV515)
+	    vap_cntl |= (2 << R300_PVS_NUM_FPUS_SHIFT);
+	else if ((info->ChipFamily == CHIP_FAMILY_RV530) ||
+		 (info->ChipFamily == CHIP_FAMILY_RV560))
+	    vap_cntl |= (5 << R300_PVS_NUM_FPUS_SHIFT);
+	else if (info->ChipFamily == CHIP_FAMILY_R420)
+	    vap_cntl |= (6 << R300_PVS_NUM_FPUS_SHIFT);
+	else if ((info->ChipFamily == CHIP_FAMILY_R520) ||
+		 (info->ChipFamily == CHIP_FAMILY_R580) ||
+		 (info->ChipFamily == CHIP_FAMILY_RV570))
+	    vap_cntl |= (8 << R300_PVS_NUM_FPUS_SHIFT);
+	else
+	    vap_cntl |= (4 << R300_PVS_NUM_FPUS_SHIFT);
+
+	if (info->has_tcl)
+	    BEGIN_ACCEL(15);
+	else
+	    BEGIN_ACCEL(8);
+	OUT_ACCEL_REG(R300_VAP_VTX_STATE_CNTL, 0);
+	OUT_ACCEL_REG(R300_VAP_PVS_STATE_FLUSH_REG, 0);
+
+	if (info->has_tcl) {
+	    OUT_ACCEL_REG(R300_VAP_CNTL_STATUS, 0);
+	    OUT_ACCEL_REG(R300_VAP_CNTL, vap_cntl);
+	}else
+	    OUT_ACCEL_REG(R300_VAP_CNTL_STATUS, R300_PVS_BYPASS);
+	OUT_ACCEL_REG(R300_VAP_PVS_STATE_FLUSH_REG, 0);
+	OUT_ACCEL_REG(R300_VAP_VTE_CNTL, R300_VTX_XY_FMT | R300_VTX_Z_FMT);
+	OUT_ACCEL_REG(R300_VAP_PSC_SGN_NORM_CNTL, 0);
+
+	OUT_ACCEL_REG(R300_VAP_PROG_STREAM_CNTL_EXT_0,
+		      ((R300_SWIZZLE_SELECT_X << R300_SWIZZLE_SELECT_X_0_SHIFT) |
+		       (R300_SWIZZLE_SELECT_Y << R300_SWIZZLE_SELECT_Y_0_SHIFT) |
+		       (R300_SWIZZLE_SELECT_Z << R300_SWIZZLE_SELECT_Z_0_SHIFT) |
+		       (R300_SWIZZLE_SELECT_W << R300_SWIZZLE_SELECT_W_0_SHIFT) |
+		       ((R300_WRITE_ENA_X | R300_WRITE_ENA_Y | R300_WRITE_ENA_Z | R300_WRITE_ENA_W)
+			<< R300_WRITE_ENA_0_SHIFT) |
+		       (R300_SWIZZLE_SELECT_X << R300_SWIZZLE_SELECT_X_1_SHIFT) |
+		       (R300_SWIZZLE_SELECT_Y << R300_SWIZZLE_SELECT_Y_1_SHIFT) |
+		       (R300_SWIZZLE_SELECT_Z << R300_SWIZZLE_SELECT_Z_1_SHIFT) |
+		       (R300_SWIZZLE_SELECT_W << R300_SWIZZLE_SELECT_W_1_SHIFT) |
+		       ((R300_WRITE_ENA_X | R300_WRITE_ENA_Y | R300_WRITE_ENA_Z | R300_WRITE_ENA_W)
+			<< R300_WRITE_ENA_1_SHIFT)));
+	OUT_ACCEL_REG(R300_VAP_PROG_STREAM_CNTL_EXT_1,
+		      ((R300_SWIZZLE_SELECT_X << R300_SWIZZLE_SELECT_X_2_SHIFT) |
+		       (R300_SWIZZLE_SELECT_Y << R300_SWIZZLE_SELECT_Y_2_SHIFT) |
+		       (R300_SWIZZLE_SELECT_Z << R300_SWIZZLE_SELECT_Z_2_SHIFT) |
+		       (R300_SWIZZLE_SELECT_W << R300_SWIZZLE_SELECT_W_2_SHIFT) |
+		       ((R300_WRITE_ENA_X | R300_WRITE_ENA_Y | R300_WRITE_ENA_Z | R300_WRITE_ENA_W)
+			<< R300_WRITE_ENA_2_SHIFT)));
+
+	if (info->has_tcl) {
+	    OUT_ACCEL_REG(R300_VAP_PVS_FLOW_CNTL_OPC, 0);
+	    OUT_ACCEL_REG(R300_VAP_GB_VERT_CLIP_ADJ, 0x3f800000);
+	    OUT_ACCEL_REG(R300_VAP_GB_VERT_DISC_ADJ, 0x3f800000);
+	    OUT_ACCEL_REG(R300_VAP_GB_HORZ_CLIP_ADJ, 0x3f800000);
+	    OUT_ACCEL_REG(R300_VAP_GB_HORZ_DISC_ADJ, 0x3f800000);
+	    OUT_ACCEL_REG(R300_VAP_CLIP_CNTL, R300_CLIP_DISABLE);
+	}
+	FINISH_ACCEL();
+
+	/* pre-load the vertex shaders */
+	if (info->has_tcl) {
+	    /* exa mask shader program */
+	    BEGIN_ACCEL(13);
+	    OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_INDX_REG, 0);
+	    /* PVS inst 0 */
+	    OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
+			  (R300_PVS_DST_OPCODE(R300_VE_ADD) |
+			   R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_OUT) |
+			   R300_PVS_DST_OFFSET(0) |
+			   R300_PVS_DST_WE_X | R300_PVS_DST_WE_Y |
+			   R300_PVS_DST_WE_Z | R300_PVS_DST_WE_W));
+	    OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
+			  (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
+			   R300_PVS_SRC_OFFSET(0) |
+			   R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) |
+			   R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) |
+			   R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_Z) |
+			   R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_W)));
+	    OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
+			  (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
+			   R300_PVS_SRC_OFFSET(0) |
+			   R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) |
+			   R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) |
+			   R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
+			   R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
+	    OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
+			  (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
+			   R300_PVS_SRC_OFFSET(0) |
+			   R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) |
+			   R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) |
+			   R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
+			   R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
+
+	    /* PVS inst 1 */
+	    OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
+			  (R300_PVS_DST_OPCODE(R300_VE_ADD) |
+			   R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_OUT) |
+			   R300_PVS_DST_OFFSET(1) |
+			   R300_PVS_DST_WE_X | R300_PVS_DST_WE_Y |
+			   R300_PVS_DST_WE_Z | R300_PVS_DST_WE_W));
+	    OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
+			  (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
+			   R300_PVS_SRC_OFFSET(6) |
+			   R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) |
+			   R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) |
+			   R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_Z) |
+			   R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_W)));
+	    OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
+			  (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
+			   R300_PVS_SRC_OFFSET(6) |
+			   R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) |
+			   R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) |
+			   R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
+			   R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
+	    OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
+			  (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
+			   R300_PVS_SRC_OFFSET(6) |
+			   R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) |
+			   R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) |
+			   R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
+			   R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
+
+	    /* PVS inst 2 */
+	    OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
+			  (R300_PVS_DST_OPCODE(R300_VE_ADD) |
+			   R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_OUT) |
+			   R300_PVS_DST_OFFSET(2) |
+			   R300_PVS_DST_WE_X | R300_PVS_DST_WE_Y |
+			   R300_PVS_DST_WE_Z | R300_PVS_DST_WE_W));
+	    OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
+			  (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
+			   R300_PVS_SRC_OFFSET(7) |
+			   R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) |
+			   R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) |
+			   R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_Z) |
+			   R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_W)));
+	    OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
+			  (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
+			   R300_PVS_SRC_OFFSET(7) |
+			   R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) |
+			   R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) |
+			   R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
+			   R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
+	    OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
+			  (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
+			   R300_PVS_SRC_OFFSET(7) |
+			   R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) |
+			   R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) |
+			   R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
+			   R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
+	    FINISH_ACCEL();
+
+	    BEGIN_ACCEL(9);
+	    /* exa no mask instruction */
+	    OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_INDX_REG, 3);
+	    /* PVS inst 0 */
+	    OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
+			  (R300_PVS_DST_OPCODE(R300_VE_ADD) |
+			   R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_OUT) |
+			   R300_PVS_DST_OFFSET(0) |
+			   R300_PVS_DST_WE_X | R300_PVS_DST_WE_Y |
+			   R300_PVS_DST_WE_Z | R300_PVS_DST_WE_W));
+	    OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
+			  (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
+			   R300_PVS_SRC_OFFSET(0) |
+			   R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) |
+			   R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) |
+			   R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_Z) |
+			   R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_W)));
+	    OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
+			  (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
+			   R300_PVS_SRC_OFFSET(0) |
+			   R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) |
+			   R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) |
+			   R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
+			   R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
+	    OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
+			  (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
+			   R300_PVS_SRC_OFFSET(0) |
+			   R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) |
+			   R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) |
+			   R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
+			   R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
+
+	    /* PVS inst 1 */
+	    OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
+			  (R300_PVS_DST_OPCODE(R300_VE_ADD) |
+			   R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_OUT) |
+			   R300_PVS_DST_OFFSET(1) |
+			   R300_PVS_DST_WE_X | R300_PVS_DST_WE_Y |
+			   R300_PVS_DST_WE_Z | R300_PVS_DST_WE_W));
+	    OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
+			  (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
+			   R300_PVS_SRC_OFFSET(6) |
+			   R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) |
+			   R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) |
+			   R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_Z) |
+			   R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_W)));
+	    OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
+			  (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
+			   R300_PVS_SRC_OFFSET(6) |
+			   R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) |
+			   R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) |
+			   R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
+			   R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
+	    OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
+			  (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
+			   R300_PVS_SRC_OFFSET(6) |
+			   R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) |
+			   R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) |
+			   R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
+			   R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
+	    FINISH_ACCEL();
+
+	    /* Xv shader program */
+	    BEGIN_ACCEL(9);
+	    OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_INDX_REG, 5);
+
+	    OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
+			  (R300_PVS_DST_OPCODE(R300_VE_ADD) |
+			   R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_OUT) |
+			   R300_PVS_DST_OFFSET(0) |
+			   R300_PVS_DST_WE_X | R300_PVS_DST_WE_Y |
+			   R300_PVS_DST_WE_Z | R300_PVS_DST_WE_W));
+	    OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
+			  (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
+			   R300_PVS_SRC_OFFSET(0) |
+			   R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) |
+			   R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) |
+			   R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_Z) |
+			   R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_W)));
+	    OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
+			  (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
+			   R300_PVS_SRC_OFFSET(0) |
+			   R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) |
+			   R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) |
+			   R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
+			   R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
+	    OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
+			  (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
+			   R300_PVS_SRC_OFFSET(0) |
+			   R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) |
+			   R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) |
+			   R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
+			   R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
+
+	    OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
+			  (R300_PVS_DST_OPCODE(R300_VE_ADD) |
+			   R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_OUT) |
+			   R300_PVS_DST_OFFSET(1) |
+			   R300_PVS_DST_WE_X | R300_PVS_DST_WE_Y |
+			   R300_PVS_DST_WE_Z | R300_PVS_DST_WE_W));
+	    OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
+			  (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
+			   R300_PVS_SRC_OFFSET(6) |
+			   R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) |
+			   R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) |
+			   R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_Z) |
+			   R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_W)));
+	    OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
+			  (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
+			   R300_PVS_SRC_OFFSET(6) |
+			   R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) |
+			   R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) |
+			   R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
+			   R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
+	    OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
+			  (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
+			   R300_PVS_SRC_OFFSET(6) |
+			   R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) |
+			   R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) |
+			   R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
+			   R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
+	    FINISH_ACCEL();
+	}
+
+	/* pre-load the RS instructions */
+	BEGIN_ACCEL(4);
+	if (IS_R300_3D) {
+	    /* rasterizer source table
+	     * R300_RS_TEX_PTR is the offset into the input RS stream
+	     * 0,1 are tex0
+	     * 2,3 are tex1
+	     */
+	    OUT_ACCEL_REG(R300_RS_IP_0,
+			  (R300_RS_TEX_PTR(0) |
+			   R300_RS_SEL_S(R300_RS_SEL_C0) |
+			   R300_RS_SEL_T(R300_RS_SEL_C1) |
+			   R300_RS_SEL_R(R300_RS_SEL_K0) |
+			   R300_RS_SEL_Q(R300_RS_SEL_K1)));
+	    OUT_ACCEL_REG(R300_RS_IP_1,
+			  (R300_RS_TEX_PTR(2) |
+			   R300_RS_SEL_S(R300_RS_SEL_C0) |
+			   R300_RS_SEL_T(R300_RS_SEL_C1) |
+			   R300_RS_SEL_R(R300_RS_SEL_K0) |
+			   R300_RS_SEL_Q(R300_RS_SEL_K1)));
+	    /* src tex */
+	    /* R300_INST_TEX_ID - select the RS source table entry
+	     * R300_INST_TEX_ADDR - the FS temp register for the texture data
+	     */
+	    OUT_ACCEL_REG(R300_RS_INST_0, (R300_INST_TEX_ID(0) |
+					   R300_RS_INST_TEX_CN_WRITE |
+					   R300_INST_TEX_ADDR(0)));
+	    /* mask tex */
+	    OUT_ACCEL_REG(R300_RS_INST_1, (R300_INST_TEX_ID(1) |
+					   R300_RS_INST_TEX_CN_WRITE |
+					   R300_INST_TEX_ADDR(1)));
+
+	} else {
+	    /* rasterizer source table
+	     * R300_RS_TEX_PTR is the offset into the input RS stream
+	     * 0,1 are tex0
+	     * 2,3 are tex1
+	     */
+	    OUT_ACCEL_REG(R500_RS_IP_0, ((0 << R500_RS_IP_TEX_PTR_S_SHIFT) |
+					 (1 << R500_RS_IP_TEX_PTR_T_SHIFT) |
+					 (R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_R_SHIFT) |
+					 (R500_RS_IP_PTR_K1 << R500_RS_IP_TEX_PTR_Q_SHIFT)));
+
+	    OUT_ACCEL_REG(R500_RS_IP_1, ((2 << R500_RS_IP_TEX_PTR_S_SHIFT) |
+					 (3 << R500_RS_IP_TEX_PTR_T_SHIFT) |
+					 (R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_R_SHIFT) |
+					 (R500_RS_IP_PTR_K1 << R500_RS_IP_TEX_PTR_Q_SHIFT)));
+	    /* src tex */
+	    /* R500_RS_INST_TEX_ID_SHIFT - select the RS source table entry
+	     * R500_RS_INST_TEX_ADDR_SHIFT - the FS temp register for the texture data
+	     */
+	    OUT_ACCEL_REG(R500_RS_INST_0, ((0 << R500_RS_INST_TEX_ID_SHIFT) |
+					   R500_RS_INST_TEX_CN_WRITE |
+					   (0 << R500_RS_INST_TEX_ADDR_SHIFT)));
+	    /* mask tex */
+	    OUT_ACCEL_REG(R500_RS_INST_1, ((1 << R500_RS_INST_TEX_ID_SHIFT) |
+					   R500_RS_INST_TEX_CN_WRITE |
+					   (1 << R500_RS_INST_TEX_ADDR_SHIFT)));
+	}
+	FINISH_ACCEL();
+
+	/* pre-load FS tex instructions */
+	if (IS_R300_3D) {
+	    BEGIN_ACCEL(2);
+	    /* tex inst for src texture */
+	    OUT_ACCEL_REG(R300_US_TEX_INST_0,
+			  (R300_TEX_SRC_ADDR(0) |
+			   R300_TEX_DST_ADDR(0) |
+			   R300_TEX_ID(0) |
+			   R300_TEX_INST(R300_TEX_INST_LD)));
+
+	    /* tex inst for mask texture */
+	    OUT_ACCEL_REG(R300_US_TEX_INST_1,
+			  (R300_TEX_SRC_ADDR(1) |
+			   R300_TEX_DST_ADDR(1) |
+			   R300_TEX_ID(1) |
+			   R300_TEX_INST(R300_TEX_INST_LD)));
+	    FINISH_ACCEL();
+	}
+
+	if (IS_R300_3D) {
+	    BEGIN_ACCEL(9);
+	    OUT_ACCEL_REG(R300_US_CONFIG, (0 << R300_NLEVEL_SHIFT) | R300_FIRST_TEX);
+	    OUT_ACCEL_REG(R300_US_PIXSIZE, 1); /* highest temp used */
+	    OUT_ACCEL_REG(R300_US_CODE_ADDR_0,
+			  (R300_ALU_START(0) |
+			   R300_ALU_SIZE(0) |
+			   R300_TEX_START(0) |
+			   R300_TEX_SIZE(0)));
+	    OUT_ACCEL_REG(R300_US_CODE_ADDR_1,
+			  (R300_ALU_START(0) |
+			   R300_ALU_SIZE(0) |
+			   R300_TEX_START(0) |
+			   R300_TEX_SIZE(0)));
+	    OUT_ACCEL_REG(R300_US_CODE_ADDR_2,
+			  (R300_ALU_START(0) |
+			   R300_ALU_SIZE(0) |
+			   R300_TEX_START(0) |
+			   R300_TEX_SIZE(0)));
+	} else {
+	    BEGIN_ACCEL(7);
+	    OUT_ACCEL_REG(R300_US_CONFIG, R500_ZERO_TIMES_ANYTHING_EQUALS_ZERO);
+	    OUT_ACCEL_REG(R300_US_PIXSIZE, 1); /* highest temp used */
+	    OUT_ACCEL_REG(R500_US_FC_CTRL, 0);
+	}
 	OUT_ACCEL_REG(R300_US_W_FMT, 0);
 	OUT_ACCEL_REG(R300_US_OUT_FMT_1, (R300_OUT_FMT_UNUSED |
 					  R300_OUT_FMT_C0_SEL_BLUE |
@@ -168,11 +549,6 @@ static void FUNC_NAME(RADEONInit3DEngine)(ScrnInfoPtr pScrn)
 					  R300_OUT_FMT_C1_SEL_GREEN |
 					  R300_OUT_FMT_C2_SEL_RED |
 					  R300_OUT_FMT_C3_SEL_ALPHA));
-	OUT_ACCEL_REG(R300_US_OUT_FMT_0, (R300_OUT_FMT_C4_10 |
-					  R300_OUT_FMT_C0_SEL_BLUE |
-					  R300_OUT_FMT_C1_SEL_GREEN |
-					  R300_OUT_FMT_C2_SEL_RED |
-					  R300_OUT_FMT_C3_SEL_ALPHA));
 	FINISH_ACCEL();
 
 
@@ -182,7 +558,8 @@ static void FUNC_NAME(RADEONInit3DEngine)(ScrnInfoPtr pScrn)
 	OUT_ACCEL_REG(R300_FG_ALPHA_FUNC, 0);
 	FINISH_ACCEL();
 
-	BEGIN_ACCEL(12);
+	BEGIN_ACCEL(13);
+	OUT_ACCEL_REG(R300_RB3D_ABLENDCNTL, 0);
 	OUT_ACCEL_REG(R300_RB3D_ZSTENCILCNTL, 0);
 	OUT_ACCEL_REG(R300_RB3D_ZCACHE_CTLSTAT, R300_ZC_FLUSH | R300_ZC_FREE);
 	OUT_ACCEL_REG(R300_RB3D_BW_CNTL, 0);
diff --git a/src/radeon_dri.h b/src/radeon_dri.h
index 3b54626..67892a6 100644
--- a/src/radeon_dri.h
+++ b/src/radeon_dri.h
@@ -46,7 +46,7 @@
 #define RADEON_DEFAULT_BUFFER_SIZE    2 /* MB (must be page aligned) */
 #define RADEON_DEFAULT_GART_TEX_SIZE  1 /* MB (must be page aligned) */
 
-#define RADEON_DEFAULT_CP_TIMEOUT     10000  /* usecs */
+#define RADEON_DEFAULT_CP_TIMEOUT     100000  /* usecs */
 
 #define RADEON_DEFAULT_PCI_APER_SIZE 32 /* in MB */
 
diff --git a/src/radeon_driver.c b/src/radeon_driver.c
index 3d33d47..e77ea16 100644
--- a/src/radeon_driver.c
+++ b/src/radeon_driver.c
@@ -125,8 +125,6 @@ static void RADEONSaveMemMapRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save);
 #ifdef XF86DRI
 static void RADEONAdjustMemMapRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save);
 #endif
-static void
-RADEONRestoreMemMapRegisters(ScrnInfoPtr pScrn, RADEONSavePtr restore);
 
 static const OptionInfoRec RADEONOptions[] = {
     { OPTION_NOACCEL,        "NoAccel",          OPTV_BOOLEAN, {0}, FALSE },
@@ -1185,15 +1183,30 @@ static Bool RADEONPreInitWeight(ScrnInfoPtr pScrn)
     return TRUE;
 }
 
-static void RADEONInitMemoryMap(ScrnInfoPtr pScrn, RADEONSavePtr save)
+void RADEONInitMemMapRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save,
+				      RADEONInfoPtr info)
+{
+    save->mc_fb_location = info->mc_fb_location;
+    save->mc_agp_location = info->mc_agp_location;
+
+    if (IS_AVIVO_VARIANT) {
+	save->mc_agp_location_hi = info->mc_agp_location_hi;
+    } else {
+	save->display_base_addr = info->fbLocation;
+	save->display2_base_addr = info->fbLocation;
+	save->ov0_base_addr = info->fbLocation;
+    }
+}
+
+static void RADEONInitMemoryMap(ScrnInfoPtr pScrn)
 {
     RADEONInfoPtr  info   = RADEONPTR(pScrn);
     unsigned char *RADEONMMIO = info->MMIO;
     CARD32 mem_size;
     CARD32 aper_size;
 
-    radeon_read_mc_fb_agp_location(pScrn, LOC_FB | LOC_AGP, &save->mc_fb_location,
-				   &save->mc_agp_location, &save->mc_agp_location_hi);
+    radeon_read_mc_fb_agp_location(pScrn, LOC_FB | LOC_AGP, &info->mc_fb_location,
+				   &info->mc_agp_location, &info->mc_agp_location_hi);
 
     /* We shouldn't use info->videoRam here which might have been clipped
      * but the real video RAM instead
@@ -1225,13 +1238,13 @@ static void RADEONInitMemoryMap(ScrnInfoPtr pScrn, RADEONSavePtr save)
     if ((info->ChipFamily != CHIP_FAMILY_RS690) &&
 	(info->ChipFamily != CHIP_FAMILY_RS740)) {
 	if (info->IsIGP)
-	    save->mc_fb_location = INREG(RADEON_NB_TOM);
+	    info->mc_fb_location = INREG(RADEON_NB_TOM);
 	else
 #ifdef XF86DRI
 	/* Old DRI has restrictions on the memory map */
 	if ( info->directRenderingEnabled &&
 	     info->pKernelDRMVersion->version_minor < 10 )
-	    save->mc_fb_location = (mem_size - 1) & 0xffff0000U;
+	    info->mc_fb_location = (mem_size - 1) & 0xffff0000U;
 	else
 #endif
 	{
@@ -1259,19 +1272,19 @@ static void RADEONInitMemoryMap(ScrnInfoPtr pScrn, RADEONSavePtr save)
 		    aper0_base &= ~(mem_size - 1);
 
 	    if (info->ChipFamily >= CHIP_FAMILY_R600) {
-		save->mc_fb_location = (aper0_base >> 24) |
+		info->mc_fb_location = (aper0_base >> 24) |
 		    (((aper0_base + mem_size - 1) & 0xff000000U) >> 8);
-		ErrorF("mc fb loc is %08x\n", (unsigned int)save->mc_fb_location);
+		ErrorF("mc fb loc is %08x\n", (unsigned int)info->mc_fb_location);
 	    } else {
-		save->mc_fb_location = (aper0_base >> 16) |
+		info->mc_fb_location = (aper0_base >> 16) |
 		    ((aper0_base + mem_size - 1) & 0xffff0000U);
 	    }
 	}
     }
     if (info->ChipFamily >= CHIP_FAMILY_R600) {
-	info->fbLocation = (save->mc_fb_location & 0xffff) << 24;
+	info->fbLocation = (info->mc_fb_location & 0xffff) << 24;
     } else {
-	info->fbLocation = (save->mc_fb_location & 0xffff) << 16;
+   	info->fbLocation = (info->mc_fb_location & 0xffff) << 16;
     }
     /* Just disable the damn AGP apertures for now, it may be
      * re-enabled later by the DRM
@@ -1279,27 +1292,22 @@ static void RADEONInitMemoryMap(ScrnInfoPtr pScrn, RADEONSavePtr save)
 
     if (IS_AVIVO_VARIANT) {
 	if (info->ChipFamily >= CHIP_FAMILY_R600) {
-	    OUTREG(R600_HDP_NONSURFACE_BASE, (save->mc_fb_location << 16) & 0xff0000);
+	    OUTREG(R600_HDP_NONSURFACE_BASE, (info->mc_fb_location << 16) & 0xff0000);
 	} else {
-	    OUTREG(AVIVO_HDP_FB_LOCATION, save->mc_fb_location);
+	    OUTREG(AVIVO_HDP_FB_LOCATION, info->mc_fb_location);
 	}
-	save->mc_agp_location = 0x003f0000;
-    } else {
-	save->mc_agp_location = 0xffffffc0;
-	save->display_base_addr = info->fbLocation;
-	save->display2_base_addr = info->fbLocation;
-	save->ov0_base_addr = info->fbLocation;
-    }
-
+    	info->mc_agp_location = 0x003f0000;
+    } else
+    	info->mc_agp_location = 0xffffffc0;
     xf86DrvMsg(pScrn->scrnIndex, X_INFO,
 	       "RADEONInitMemoryMap() : \n");
     xf86DrvMsg(pScrn->scrnIndex, X_INFO,
 	       "  mem_size         : 0x%08x\n", (unsigned)mem_size);
     xf86DrvMsg(pScrn->scrnIndex, X_INFO,
-	       "  MC_FB_LOCATION   : 0x%08x\n", (unsigned)save->mc_fb_location);
+	       "  MC_FB_LOCATION   : 0x%08x\n", (unsigned)info->mc_fb_location);
     xf86DrvMsg(pScrn->scrnIndex, X_INFO,
 	       "  MC_AGP_LOCATION  : 0x%08x\n",
-	       (unsigned)save->mc_agp_location);
+	       (unsigned)info->mc_agp_location);
 }
 
 static void RADEONGetVRamType(ScrnInfoPtr pScrn)
@@ -1308,7 +1316,7 @@ static void RADEONGetVRamType(ScrnInfoPtr pScrn)
     RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn);
     unsigned char *RADEONMMIO = info->MMIO;
     CARD32 tmp;
-
+ 
     if (info->IsIGP || (info->ChipFamily >= CHIP_FAMILY_R300) ||
 	(INREG(RADEON_MEM_SDRAM_MODE_REG) & (1<<30))) 
 	info->IsDDR = TRUE;
@@ -1777,6 +1785,19 @@ static Bool RADEONPreInitChipType(ScrnInfoPtr pScrn)
         if (!xf86LoadSubModule(pScrn, "shadow"))
             return FALSE;
     }
+
+
+    if ((info->ChipFamily == CHIP_FAMILY_RS100) ||
+	(info->ChipFamily == CHIP_FAMILY_RS200) ||
+	(info->ChipFamily == CHIP_FAMILY_RS300) ||
+	(info->ChipFamily == CHIP_FAMILY_RS400) ||
+	(info->ChipFamily == CHIP_FAMILY_RS690) ||
+	(info->ChipFamily == CHIP_FAMILY_RS740))
+	info->has_tcl = FALSE;
+    else {
+	info->has_tcl = TRUE;
+    }
+
     return TRUE;
 }
 
@@ -2339,7 +2360,7 @@ static Bool RADEONPreInitXv(ScrnInfoPtr pScrn)
        }
 
     bios_header=info->VBIOS[0x48];
-    bios_header+=(((int)info->VBIOS[0x49]+0)<<8);           
+    bios_header+=(((int)info->VBIOS[0x49]+0)<<8);
         
     mm_table=info->VBIOS[bios_header+0x38];
     if(mm_table==0)
@@ -2770,14 +2791,16 @@ Bool RADEONPreInit(ScrnInfoPtr pScrn, int flags)
 
     if (!RADEONPreInitAccel(pScrn))              goto fail;
 
-    if (!RADEONPreInitXv(pScrn))                 goto fail;
+    if (!IS_AVIVO_VARIANT) {
+	if (!RADEONPreInitXv(pScrn))                 goto fail;
+    }
 
     if (!xf86RandR12PreInit (pScrn))
     {
       xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "RandR initialization failure\n");
       goto fail;
-    }	
-    
+    }
+
     if (pScrn->modes == NULL) {
       xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "No modes.\n");
       goto fail;
@@ -2978,7 +3001,8 @@ RADEONInitBIOSRegisters(ScrnInfoPtr pScrn)
 	/* let the bios control the backlight */
 	save->bios_2_scratch &= ~ATOM_S2_VRI_BRIGHT_ENABLE;
 	/* tell the bios not to handle mode switching */
-	save->bios_6_scratch |= ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH;
+	save->bios_6_scratch |= (ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH |
+				 ATOM_S6_ACC_MODE);
 
 	if (info->ChipFamily >= CHIP_FAMILY_R600) {
 	    OUTREG(R600_BIOS_2_SCRATCH, save->bios_2_scratch);
@@ -2991,7 +3015,8 @@ RADEONInitBIOSRegisters(ScrnInfoPtr pScrn)
 	/* let the bios control the backlight */
 	save->bios_0_scratch &= ~RADEON_DRIVER_BRIGHTNESS_EN;
 	/* tell the bios not to handle mode switching */
-	save->bios_6_scratch |= RADEON_DISPLAY_SWITCHING_DIS;
+	save->bios_6_scratch |= (RADEON_DISPLAY_SWITCHING_DIS |
+				 RADEON_ACC_MODE_CHANGE);
 	/* tell the bios a driver is loaded */
 	save->bios_7_scratch |= RADEON_DRV_LOADED;
 
@@ -3055,11 +3080,16 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen,
     RADEONBlank(pScrn);
 
     if (info->IsMobility && !IS_AVIVO_VARIANT) {
-        if (xf86ReturnOptValBool(info->Options, OPTION_DYNAMIC_CLOCKS, FALSE)) {
+	if (xf86ReturnOptValBool(info->Options, OPTION_DYNAMIC_CLOCKS, FALSE)) {
 	    RADEONSetDynamicClock(pScrn, 1);
-        } else {
+	} else {
 	    RADEONSetDynamicClock(pScrn, 0);
-        }
+	}
+    } else if (IS_AVIVO_VARIANT) {
+	if (xf86ReturnOptValBool(info->Options, OPTION_DYNAMIC_CLOCKS, FALSE)) {
+	    atombios_static_pwrmgt_setup(pScrn, 1);
+	    atombios_dyn_clk_setup(pScrn, 1);
+	}
     }
 
     if (IS_R300_VARIANT || IS_RV100_VARIANT)
@@ -3111,10 +3141,7 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen,
     /* Initialize the memory map, this basically calculates the values
      * we'll use later on for MC_FB_LOCATION & MC_AGP_LOCATION
      */
-    RADEONInitMemoryMap(pScrn, info->ModeReg);
-
-    /* write any changes we made */
-    RADEONRestoreMemMapRegisters(pScrn, info->ModeReg);
+    RADEONInitMemoryMap(pScrn);
 
     /* empty the surfaces */
     {
@@ -3252,7 +3279,7 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen,
 		xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
 			   "[drm] failed to enable new memory map\n");
 		RADEONDRICloseScreen(pScreen);
-		info->directRenderingEnabled = FALSE;
+		info->directRenderingEnabled = FALSE;		
 	}
     }
 #endif
@@ -3312,7 +3339,7 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen,
 	else if (strcmp(s, "BGR") == 0) subPixelOrder = SubPixelHorizontalBGR;
 	else if (strcmp(s, "NONE") == 0) subPixelOrder = SubPixelNone;
 	PictureSetSubpixelOrder (pScreen, subPixelOrder);
-    }
+    } 
 #endif
 
     pScrn->vtSema = TRUE;
@@ -3359,7 +3386,7 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen,
 	RADEONAdjustMemMapRegisters(pScrn, info->ModeReg);
 
 	if ((info->DispPriority == 1) && (info->cardType==CARD_AGP)) {
-	    /* we need to re-calculate bandwidth because of AGPMode difference. */
+	    /* we need to re-calculate bandwidth because of AGPMode difference. */ 
 	    RADEONInitDispBandwidth(pScrn);
 	}
 	xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Direct rendering enabled\n");
@@ -3497,9 +3524,8 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen,
 }
 
 /* Write memory mapping registers */
-static void
-RADEONRestoreMemMapRegisters(ScrnInfoPtr pScrn,
-			     RADEONSavePtr restore)
+void RADEONRestoreMemMapRegisters(ScrnInfoPtr pScrn,
+					 RADEONSavePtr restore)
 {
     RADEONInfoPtr  info       = RADEONPTR(pScrn);
     RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn);
@@ -3569,7 +3595,7 @@ RADEONRestoreMemMapRegisters(ScrnInfoPtr pScrn,
 	    } else {
 		OUTREG(R600_HDP_NONSURFACE_BASE, (restore->mc_fb_location << 16) & 0xff0000);
 	    }
-
+	    
 	    /* Reset the engine and HDP */
 	    RADEONEngineReset(pScrn);
 	}
@@ -3619,7 +3645,7 @@ RADEONRestoreMemMapRegisters(ScrnInfoPtr pScrn,
 		       | RADEON_CRTC2_DISP_REQ_EN_B);
 	    }
 
-	    /* Make sure the chip settles down (paranoid !) */
+	    /* Make sure the chip settles down (paranoid !) */ 
 	    usleep(100000);
 
 	    /* Wait for MC idle */
@@ -3737,28 +3763,21 @@ static void RADEONAdjustMemMapRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save)
 		   "DRI init changed memory map, adjusting ...\n");
 	xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
 		   "  MC_FB_LOCATION  was: 0x%08lx is: 0x%08lx\n",
-		   (long unsigned int)save->mc_fb_location, (long unsigned int)fb);
+		   (long unsigned int)info->mc_fb_location, (long unsigned int)fb);
 	xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
 		   "  MC_AGP_LOCATION was: 0x%08lx is: 0x%08lx\n",
-		   (long unsigned int)save->mc_agp_location, (long unsigned int)agp);
-	save->mc_fb_location = fb;
-	save->mc_agp_location = agp;
-	save->mc_agp_location_hi = agp_hi;
+		   (long unsigned int)info->mc_agp_location, (long unsigned int)agp);
+	info->mc_fb_location = fb;
+	info->mc_agp_location = agp;
 	if (info->ChipFamily >= CHIP_FAMILY_R600)
-	    info->fbLocation = (save->mc_fb_location & 0xffff) << 24;
+	    info->fbLocation = (info->mc_fb_location & 0xffff) << 24;
 	else
-	    info->fbLocation = (save->mc_fb_location & 0xffff) << 16;
-
-	if (!IS_AVIVO_VARIANT) {
-	    save->display_base_addr = info->fbLocation;
-	    save->display2_base_addr = info->fbLocation;
-	    save->ov0_base_addr = info->fbLocation;
-	}
+	    info->fbLocation = (info->mc_fb_location & 0xffff) << 16;
 
 	info->dst_pitch_offset =
 	    (((pScrn->displayWidth * info->CurrentLayout.pixel_bytes / 64)
 	      << 22) | ((info->fbLocation + pScrn->fbOffset) >> 10));
-
+	RADEONInitMemMapRegisters(pScrn, save, info);
 	RADEONRestoreMemMapRegisters(pScrn, save);
     }
 
@@ -3792,7 +3811,7 @@ static void RADEONRestoreSurfaces(ScrnInfoPtr pScrn, RADEONSavePtr restore)
     RADEONInfoPtr      info = RADEONPTR(pScrn);
     unsigned char *RADEONMMIO = info->MMIO;
     unsigned int surfnr;
-
+    
     for ( surfnr = 0; surfnr < 8; surfnr++ ) {
 	OUTREG(RADEON_SURFACE0_INFO + 16 * surfnr, restore->surfaces[surfnr][0]);
 	OUTREG(RADEON_SURFACE0_LOWER_BOUND + 16 * surfnr, restore->surfaces[surfnr][1]);
@@ -3853,7 +3872,7 @@ void RADEONChangeSurfaces(ScrnInfoPtr pScrn)
        color_pattern = R300_SURF_TILE_COLOR_MACRO;
     } else {
 	color_pattern = R200_SURF_TILE_COLOR_MACRO;
-    }
+    }   
 #ifdef XF86DRI
     if (info->directRenderingInited) {
 	drmRadeonSurfaceFree drmsurffree;
@@ -3898,7 +3917,7 @@ void RADEONChangeSurfaces(ScrnInfoPtr pScrn)
 	if (retvalue < 0)
 	    xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
 		       "drm: could not allocate surface for front buffer!\n");
-
+	
 	if ((info->have3DWindows) && (!info->noBackBuffer)) {
 	    drmsurfalloc.address = info->backOffset;
 	    retvalue = drmCommandWrite(info->drmFD, DRM_RADEON_SURF_ALLOC,
@@ -4828,7 +4847,7 @@ static void RADEONRestore(ScrnInfoPtr pScrn)
 #endif
 
     /* to restore console mode, DAC registers should be set after every other registers are set,
-     * otherwise,we may get blank screen
+     * otherwise,we may get blank screen 
      */
     if (IS_AVIVO_VARIANT)
 	avivo_restore_vga_regs(pScrn, restore);
@@ -4891,7 +4910,7 @@ Bool RADEONSwitchMode(int scrnIndex, DisplayModePtr mode, int flags)
 
     if (info->allowColorTiling) {
         info->tilingEnabled = (mode->Flags & (V_DBLSCAN | V_INTERLACE)) ? FALSE : TRUE;
-#ifdef XF86DRI
+#ifdef XF86DRI	
 	if (info->directRenderingEnabled && (info->tilingEnabled != tilingOld)) {
 	    RADEONSAREAPrivPtr pSAREAPriv;
 	  if (RADEONDRISetParam(pScrn, RADEON_SETPARAM_SWITCH_TILING, (info->tilingEnabled ? 1 : 0)) < 0)
@@ -5177,6 +5196,11 @@ Bool RADEONEnterVT(int scrnIndex, int flags)
 	} else {
 	    RADEONSetDynamicClock(pScrn, 0);
 	}
+    } else if (IS_AVIVO_VARIANT) {
+	if (xf86ReturnOptValBool(info->Options, OPTION_DYNAMIC_CLOCKS, FALSE)) {
+	    atombios_static_pwrmgt_setup(pScrn, 1);
+	    atombios_dyn_clk_setup(pScrn, 1);
+	}
     }
 
     if (IS_R300_VARIANT || IS_RV100_VARIANT)
@@ -5184,20 +5208,18 @@ Bool RADEONEnterVT(int scrnIndex, int flags)
 
     pScrn->vtSema = TRUE;
 
-    RADEONRestoreMemMapRegisters(pScrn, info->ModeReg);
-    RADEONRestoreSurfaces(pScrn, info->ModeReg);
-
     if (!xf86SetDesiredModes(pScrn))
 	return FALSE;
 
+    RADEONRestoreSurfaces(pScrn, info->ModeReg);
 #ifdef XF86DRI
     if (info->directRenderingEnabled) {
-	if (info->cardType == CARD_PCIE &&
+    	if (info->cardType == CARD_PCIE &&
 	    info->pKernelDRMVersion->version_minor >= 19 &&
 	    info->FbSecureSize) {
 	    /* we need to backup the PCIE GART TABLE from fb memory */
 	    memcpy(info->FB + info->pciGartOffset, info->pciGartBackup, info->pciGartSize);
-	}
+    	}
 
 	/* get the DRI back into shape after resume */
 	RADEONDRISetVBlankInterrupt (pScrn, TRUE);
@@ -5206,7 +5228,6 @@ Bool RADEONEnterVT(int scrnIndex, int flags)
 
     }
 #endif
-
     /* this will get XVideo going again, but only if XVideo was initialised
        during server startup (hence the info->adaptor if). */
     if (info->adaptor)
@@ -5222,7 +5243,6 @@ Bool RADEONEnterVT(int scrnIndex, int flags)
     }
 #endif
 
-
     return TRUE;
 }
 
@@ -5243,12 +5263,12 @@ void RADEONLeaveVT(int scrnIndex, int flags)
 	DRILock(pScrn->pScreen, 0);
 	RADEONCP_STOP(pScrn, info);
 
-	if (info->cardType == CARD_PCIE &&
+        if (info->cardType == CARD_PCIE &&
 	    info->pKernelDRMVersion->version_minor >= 19 &&
 	    info->FbSecureSize) {
-	    /* we need to backup the PCIE GART TABLE from fb memory */
-	    memcpy(info->pciGartBackup, (info->FB + info->pciGartOffset), info->pciGartSize);
-	}
+            /* we need to backup the PCIE GART TABLE from fb memory */
+            memcpy(info->pciGartBackup, (info->FB + info->pciGartOffset), info->pciGartSize);
+        }
 
 	/* Make sure 3D clients will re-upload textures to video RAM */
 	if (info->textureSize) {
diff --git a/src/radeon_exa_funcs.c b/src/radeon_exa_funcs.c
index d5ee5a6..272ffa9 100644
--- a/src/radeon_exa_funcs.c
+++ b/src/radeon_exa_funcs.c
@@ -543,7 +543,7 @@ Bool FUNC_NAME(RADEONDrawInit)(ScreenPtr pScreen)
 		info->exa->PrepareComposite =
 		    FUNC_NAME(R300PrepareComposite);
 		info->exa->Composite = FUNC_NAME(RadeonComposite);
-		info->exa->DoneComposite = RadeonDoneComposite;
+		info->exa->DoneComposite = FUNC_NAME(RadeonDoneComposite);
 	} else if ((info->ChipFamily == CHIP_FAMILY_RV250) || 
 		   (info->ChipFamily == CHIP_FAMILY_RV280) || 
 		   (info->ChipFamily == CHIP_FAMILY_RS300) || 
@@ -554,7 +554,7 @@ Bool FUNC_NAME(RADEONDrawInit)(ScreenPtr pScreen)
 		info->exa->PrepareComposite =
 		    FUNC_NAME(R200PrepareComposite);
 		info->exa->Composite = FUNC_NAME(RadeonComposite);
-		info->exa->DoneComposite = RadeonDoneComposite;
+		info->exa->DoneComposite = FUNC_NAME(RadeonDoneComposite);
 	} else {
 		xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Render acceleration "
 			       "enabled for R100 type cards.\n");
@@ -562,7 +562,7 @@ Bool FUNC_NAME(RADEONDrawInit)(ScreenPtr pScreen)
 		info->exa->PrepareComposite =
 		    FUNC_NAME(R100PrepareComposite);
 		info->exa->Composite = FUNC_NAME(RadeonComposite);
-		info->exa->DoneComposite = RadeonDoneComposite;
+		info->exa->DoneComposite = FUNC_NAME(RadeonDoneComposite);
 	}
     }
 #endif
diff --git a/src/radeon_exa_render.c b/src/radeon_exa_render.c
index 707e9fc..138216f 100644
--- a/src/radeon_exa_render.c
+++ b/src/radeon_exa_render.c
@@ -26,6 +26,7 @@
  *    Eric Anholt <anholt@FreeBSD.org>
  *    Zack Rusin <zrusin@trolltech.com>
  *    Benjamin Herrenschmidt <benh@kernel.crashing.org>
+ *    Alex Deucher <alexander.deucher@amd.com>
  *
  */
 
@@ -57,6 +58,13 @@
 #ifdef ONLY_ONCE
 static Bool is_transform[2];
 static PictTransform *transform[2];
+static Bool has_mask;
+/* Whether we are tiling horizontally and vertically */
+static Bool need_src_tile_x;
+static Bool need_src_tile_y;
+/* Size of tiles ... set to 65536x65536 if not tiling in that direction */
+static Bool src_tile_width;
+static Bool src_tile_height;
 
 struct blendinfo {
     Bool dst_alpha;
@@ -220,6 +228,95 @@ union intfloat {
     CARD32 i;
 };
 
+/* Check if we need a software-fallback because of a repeating
+ *   non-power-of-two texture.
+ *
+ * canTile: whether we can emulate a repeat by drawing in tiles:
+ *   possible for the source, but not for the mask. (Actually
+ *   we could do tiling for the mask too, but dealing with the
+ *   combination of a tiled mask and a tiled source would be
+ *   a lot of complexity, so we handle only the most common
+ *   case of a repeating mask.)
+ */
+static Bool RADEONCheckTexturePOT(PicturePtr pPict, Bool canTile)
+{
+    int w = pPict->pDrawable->width;
+    int h = pPict->pDrawable->height;
+
+    if (pPict->repeat && ((w & (w - 1)) != 0 || (h & (h - 1)) != 0) &&
+	!(!pPict->transform && canTile))
+	RADEON_FALLBACK(("NPOT repeating %s unsupported (%dx%d), transform=%d\n",
+			 canTile ? "source" : "mask", w, h, pPict->transform != 0));
+
+    return TRUE;
+}
+
+/* Determine if the pitch of the pixmap meets the criteria for being
+ * used as a repeating texture: no padding or only a single line texture.
+ */
+static Bool RADEONPitchMatches(PixmapPtr pPix)
+{
+    int w = pPix->drawable.width;
+    int h = pPix->drawable.height;
+    CARD32 txpitch = exaGetPixmapPitch(pPix);
+
+    if (h > 1 && ((w * pPix->drawable.bitsPerPixel / 8 + 31) & ~31) != txpitch)
+	return FALSE;
+
+    return TRUE;
+}
+
+/* We can't turn on repeats normally for a non-power-of-two dimension,
+ * but if the source isn't transformed, we can get the same effect
+ * by drawing the image in multiple tiles. (A common case that it's
+ * important to get right is drawing a strip of a NPOTxPOT texture
+ * repeating in the POT direction. With tiling, this ends up as a
+ * a single tile on R300 and newer, which is perfect.)
+ *
+ * canTile1d: On R300 and newer, we can repeat a texture that is NPOT in
+ *   one direction and POT in the other in the POT direction; on
+ *   older chips we can only repeat at all if the texture is POT in
+ *   both directions.
+ *
+ * needMatchingPitch: On R100/R200, we can only repeat horizontally if
+ *   there is no padding in the texture. Textures with small POT widths
+ *   (1,2,4,8) thus can't be tiled.
+ */
+static Bool RADEONSetupSourceTile(PicturePtr pPict,
+				  PixmapPtr pPix,
+				  Bool canTile1d,
+				  Bool needMatchingPitch)
+{
+    need_src_tile_x = need_src_tile_y = FALSE;
+    src_tile_width = src_tile_height = 65536; /* "infinite" */
+	    
+    if (pPict->repeat) {
+	Bool badPitch = needMatchingPitch && !RADEONPitchMatches(pPix);
+	
+	int w = pPict->pDrawable->width;
+	int h = pPict->pDrawable->height;
+	
+	if (pPict->transform) {
+	    if (badPitch)
+		RADEON_FALLBACK(("Width %d and pitch %u not compatible for repeat\n",
+				 w, (unsigned)exaGetPixmapPitch(pPix)));
+	} else {
+	    need_src_tile_x = (w & (w - 1)) != 0 || badPitch;
+	    need_src_tile_y = (h & (h - 1)) != 0;
+	    
+	    if (!canTile1d)
+		need_src_tile_x = need_src_tile_y = need_src_tile_x || need_src_tile_y;
+	}
+
+	if (need_src_tile_x)
+	  src_tile_width = w;
+	if (need_src_tile_y)
+	  src_tile_height = h;
+    }
+
+    return TRUE;
+}
+
 /* R100-specific code */
 
 static Bool R100CheckCompositeTexture(PicturePtr pPict, int unit)
@@ -239,8 +336,8 @@ static Bool R100CheckCompositeTexture(PicturePtr pPict, int unit)
 	RADEON_FALLBACK(("Unsupported picture format 0x%x\n",
 			(int)pPict->format));
 
-    if (pPict->repeat && ((w & (w - 1)) != 0 || (h & (h - 1)) != 0))
-	RADEON_FALLBACK(("NPOT repeat unsupported (%dx%d)\n", w, h));
+    if (!RADEONCheckTexturePOT(pPict, unit == 0))
+	return FALSE;
 
     if (pPict->filter != PictFilterNearest &&
 	pPict->filter != PictFilterBilinear)
@@ -260,6 +357,7 @@ static Bool FUNC_NAME(R100TextureSetup)(PicturePtr pPict, PixmapPtr pPix,
     CARD32 txfilter, txformat, txoffset, txpitch;
     int w = pPict->pDrawable->width;
     int h = pPict->pDrawable->height;
+    Bool repeat = pPict->repeat && !(unit == 0 && (need_src_tile_x || need_src_tile_y));
     int i;
     ACCEL_PREAMBLE();
 
@@ -280,9 +378,8 @@ static Bool FUNC_NAME(R100TextureSetup)(PicturePtr pPict, PixmapPtr pPix,
     if (RADEONPixmapIsColortiled(pPix))
 	txoffset |= RADEON_TXO_MACRO_TILE;
 
-    if (pPict->repeat) {
-	if ((h != 1) &&
-	    (((w * pPix->drawable.bitsPerPixel / 8 + 31) & ~31) != txpitch))
+    if (repeat) {
+	if (!RADEONPitchMatches(pPix))
 	    RADEON_FALLBACK(("Width %d and pitch %u not compatible for repeat\n",
 			     w, (unsigned)txpitch));
 
@@ -306,6 +403,9 @@ static Bool FUNC_NAME(R100TextureSetup)(PicturePtr pPict, PixmapPtr pPix,
 	RADEON_FALLBACK(("Bad filter 0x%x\n", pPict->filter));
     }
 
+    if (repeat)
+      txfilter |= RADEON_CLAMP_S_WRAP | RADEON_CLAMP_T_WRAP;
+
     BEGIN_ACCEL(5);
     if (unit == 0) {
 	OUT_ACCEL_REG(RADEON_PP_TXFILTER_0, txfilter);
@@ -437,6 +537,11 @@ static Bool FUNC_NAME(R100PrepareComposite)(int op,
     if (!RADEONGetDestFormat(pDstPicture, &dst_format))
 	return FALSE;
 
+    if (pMask)
+	has_mask = TRUE;
+    else
+	has_mask = FALSE;
+
     pixel_shift = pDst->drawable.bitsPerPixel >> 4;
 
     dst_offset = exaGetPixmapOffset(pDst) + info->fbLocation;
@@ -452,6 +557,9 @@ static Bool FUNC_NAME(R100PrepareComposite)(int op,
     if (((dst_pitch >> pixel_shift) & 0x7) != 0)
 	RADEON_FALLBACK(("Bad destination pitch 0x%x\n", (int)dst_pitch));
 
+    if (!RADEONSetupSourceTile(pSrcPicture, pSrc, FALSE, TRUE))
+	return FALSE;
+
     if (!FUNC_NAME(R100TextureSetup)(pSrcPicture, pSrc, 0))
 	return FALSE;
     pp_cntl = RADEON_TEX_0_ENABLE | RADEON_TEX_BLEND_0_ENABLE;
@@ -507,9 +615,13 @@ static Bool FUNC_NAME(R100PrepareComposite)(int op,
 
     OUT_ACCEL_REG(RADEON_PP_TXCBLEND_0, cblend);
     OUT_ACCEL_REG(RADEON_PP_TXABLEND_0, ablend);
-    OUT_ACCEL_REG(RADEON_SE_VTX_FMT, RADEON_SE_VTX_FMT_XY |
-				     RADEON_SE_VTX_FMT_ST0 |
-				     RADEON_SE_VTX_FMT_ST1);
+    if (pMask)
+	OUT_ACCEL_REG(RADEON_SE_VTX_FMT, (RADEON_SE_VTX_FMT_XY |
+					  RADEON_SE_VTX_FMT_ST0 |
+					  RADEON_SE_VTX_FMT_ST1));
+    else
+	OUT_ACCEL_REG(RADEON_SE_VTX_FMT, (RADEON_SE_VTX_FMT_XY |
+					  RADEON_SE_VTX_FMT_ST0));
     /* Op operator. */
     blendcntl = RADEONGetBlendCntl(op, pMaskPicture, pDstPicture->format);
 
@@ -539,8 +651,8 @@ static Bool R200CheckCompositeTexture(PicturePtr pPict, int unit)
 	RADEON_FALLBACK(("Unsupported picture format 0x%x\n",
 			 (int)pPict->format));
 
-    if (pPict->repeat && ((w & (w - 1)) != 0 || (h & (h - 1)) != 0))
-	RADEON_FALLBACK(("NPOT repeat unsupported (%dx%d)\n", w, h));
+    if (!RADEONCheckTexturePOT(pPict, unit == 0))
+	return FALSE;
 
     if (pPict->filter != PictFilterNearest &&
 	pPict->filter != PictFilterBilinear)
@@ -558,6 +670,7 @@ static Bool FUNC_NAME(R200TextureSetup)(PicturePtr pPict, PixmapPtr pPix,
     CARD32 txfilter, txformat, txoffset, txpitch;
     int w = pPict->pDrawable->width;
     int h = pPict->pDrawable->height;
+    Bool repeat = pPict->repeat && !(unit == 0 && (need_src_tile_x || need_src_tile_y));
     int i;
     ACCEL_PREAMBLE();
 
@@ -578,9 +691,8 @@ static Bool FUNC_NAME(R200TextureSetup)(PicturePtr pPict, PixmapPtr pPix,
     if (RADEONPixmapIsColortiled(pPix))
 	txoffset |= R200_TXO_MACRO_TILE;
 
-    if (pPict->repeat) {
-	if ((h != 1) &&
-	    (((w * pPix->drawable.bitsPerPixel / 8 + 31) & ~31) != txpitch))
+    if (repeat) {
+	if (!RADEONPitchMatches(pPix))
 	    RADEON_FALLBACK(("Width %d and pitch %u not compatible for repeat\n",
 			     w, (unsigned)txpitch));
 
@@ -606,6 +718,9 @@ static Bool FUNC_NAME(R200TextureSetup)(PicturePtr pPict, PixmapPtr pPix,
 	RADEON_FALLBACK(("Bad filter 0x%x\n", pPict->filter));
     }
 
+    if (repeat)
+      txfilter |= R200_CLAMP_S_WRAP | R200_CLAMP_T_WRAP;
+
     BEGIN_ACCEL(6);
     if (unit == 0) {
 	OUT_ACCEL_REG(R200_PP_TXFILTER_0, txfilter);
@@ -721,6 +836,11 @@ static Bool FUNC_NAME(R200PrepareComposite)(int op, PicturePtr pSrcPicture,
     if (!RADEONGetDestFormat(pDstPicture, &dst_format))
 	return FALSE;
 
+    if (pMask)
+	has_mask = TRUE;
+    else
+	has_mask = FALSE;
+
     pixel_shift = pDst->drawable.bitsPerPixel >> 4;
 
     dst_offset = exaGetPixmapOffset(pDst) + info->fbLocation;
@@ -734,6 +854,9 @@ static Bool FUNC_NAME(R200PrepareComposite)(int op, PicturePtr pSrcPicture,
     if (((dst_pitch >> pixel_shift) & 0x7) != 0)
 	RADEON_FALLBACK(("Bad destination pitch 0x%x\n", (int)dst_pitch));
 
+    if (!RADEONSetupSourceTile(pSrcPicture, pSrc, FALSE, TRUE))
+	return FALSE;
+
     if (!FUNC_NAME(R200TextureSetup)(pSrcPicture, pSrc, 0))
 	return FALSE;
     pp_cntl = RADEON_TEX_0_ENABLE | RADEON_TEX_BLEND_0_ENABLE;
@@ -755,9 +878,13 @@ static Bool FUNC_NAME(R200PrepareComposite)(int op, PicturePtr pSrcPicture,
     OUT_ACCEL_REG(RADEON_RB3D_COLOROFFSET, dst_offset);
 
     OUT_ACCEL_REG(R200_SE_VTX_FMT_0, R200_VTX_XY);
-    OUT_ACCEL_REG(R200_SE_VTX_FMT_1,
-		 (2 << R200_VTX_TEX0_COMP_CNT_SHIFT) |
-		 (2 << R200_VTX_TEX1_COMP_CNT_SHIFT));
+    if (pMask)
+	OUT_ACCEL_REG(R200_SE_VTX_FMT_1,
+		      (2 << R200_VTX_TEX0_COMP_CNT_SHIFT) |
+		      (2 << R200_VTX_TEX1_COMP_CNT_SHIFT));
+    else
+	OUT_ACCEL_REG(R200_SE_VTX_FMT_1,
+		      (2 << R200_VTX_TEX0_COMP_CNT_SHIFT));
 
     OUT_ACCEL_REG(RADEON_RB3D_COLORPITCH, colorpitch);
 
@@ -838,13 +965,24 @@ static Bool R300CheckCompositeTexture(PicturePtr pPict, int unit, Bool is_r500)
 	RADEON_FALLBACK(("Unsupported picture format 0x%x\n",
 			 (int)pPict->format));
 
-    if (pPict->repeat && ((w & (w - 1)) != 0 || (h & (h - 1)) != 0))
-	RADEON_FALLBACK(("NPOT repeat unsupported (%dx%d)\n", w, h));
+    if (!RADEONCheckTexturePOT(pPict, unit == 0))
+	return FALSE;
 
     if (pPict->filter != PictFilterNearest &&
 	pPict->filter != PictFilterBilinear)
 	RADEON_FALLBACK(("Unsupported filter 0x%x\n", pPict->filter));
 
+    /* for REPEAT_NONE, Render semantics are that sampling outside the source
+     * picture results in alpha=0 pixels. We can implement this with a border color
+     * *if* our source texture has an alpha channel, otherwise we need to fall
+     * back. If we're not transformed then we hope that upper layers have clipped
+     * rendering to the bounds of the source drawable, in which case it doesn't
+     * matter. I have not, however, verified that the X server always does such
+     * clipping.
+     */
+    if (pPict->transform != 0 && !pPict->repeat && PICT_FORMAT_A(pPict->format) == 0)
+	RADEON_FALLBACK(("REPEAT_NONE unsupported for transformed xRGB source\n"));
+
     return TRUE;
 }
 
@@ -870,6 +1008,7 @@ static Bool FUNC_NAME(R300TextureSetup)(PicturePtr pPict, PixmapPtr pPix,
     if ((txpitch & 0x1f) != 0)
 	RADEON_FALLBACK(("Bad texture pitch 0x%x\n", (int)txpitch));
 
+    /* TXPITCH = pixels (texels) per line - 1 */
     pixel_shift = pPix->drawable.bitsPerPixel >> 4;
     txpitch >>= pixel_shift;
     txpitch -= 1;
@@ -894,21 +1033,25 @@ static Bool FUNC_NAME(R300TextureSetup)(PicturePtr pPict, PixmapPtr pPix,
     if (IS_R500_3D && ((h - 1) & 0x800))
 	txpitch |= R500_TXHEIGHT_11;
 
-    if (pPict->repeat) {
-	if ((h != 1) &&
-	    (((w * pPix->drawable.bitsPerPixel / 8 + 31) & ~31) != txpitch))
-	    RADEON_FALLBACK(("Width %d and pitch %u not compatible for repeat\n",
-			     w, (unsigned)txpitch));
-    } else
-	txformat0 |= R300_TXPITCH_EN;
-
+    /* Use TXPITCH instead of TXWIDTH for address computations: we could
+     * omit this if there is no padding, but there is no apparent advantage
+     * in doing so.
+     */
+    txformat0 |= R300_TXPITCH_EN;
 
     info->texW[unit] = w;
     info->texH[unit] = h;
 
-    txfilter = (R300_TX_CLAMP_S(R300_TX_CLAMP_CLAMP_LAST) |
-		R300_TX_CLAMP_T(R300_TX_CLAMP_CLAMP_LAST));
+    if (pPict->repeat && !(unit == 0 && need_src_tile_x))
+      txfilter = R300_TX_CLAMP_S(R300_TX_CLAMP_WRAP);
+    else
+      txfilter = R300_TX_CLAMP_S(R300_TX_CLAMP_CLAMP_GL);
 
+    if (pPict->repeat && !(unit == 0 && need_src_tile_y))
+      txfilter |= R300_TX_CLAMP_T(R300_TX_CLAMP_WRAP);
+    else
+      txfilter |= R300_TX_CLAMP_T(R300_TX_CLAMP_CLAMP_GL);
+		   
     txfilter |= (unit << R300_TX_ID_SHIFT);
 
     switch (pPict->filter) {
@@ -922,13 +1065,15 @@ static Bool FUNC_NAME(R300TextureSetup)(PicturePtr pPict, PixmapPtr pPix,
 	RADEON_FALLBACK(("Bad filter 0x%x\n", pPict->filter));
     }
 
-    BEGIN_ACCEL(6);
+    BEGIN_ACCEL(pPict->repeat ? 6 : 7);
     OUT_ACCEL_REG(R300_TX_FILTER0_0 + (unit * 4), txfilter);
     OUT_ACCEL_REG(R300_TX_FILTER1_0 + (unit * 4), 0);
     OUT_ACCEL_REG(R300_TX_FORMAT0_0 + (unit * 4), txformat0);
     OUT_ACCEL_REG(R300_TX_FORMAT1_0 + (unit * 4), txformat1);
     OUT_ACCEL_REG(R300_TX_FORMAT2_0 + (unit * 4), txpitch);
     OUT_ACCEL_REG(R300_TX_OFFSET_0 + (unit * 4), txoffset);
+    if (!pPict->repeat)
+	OUT_ACCEL_REG(R300_TX_BORDER_COLOR_0 + (unit * 4), 0);
     FINISH_ACCEL();
 
     if (pPict->transform != 0) {
@@ -1036,10 +1181,6 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture,
     CARD32 txenable, colorpitch;
     CARD32 blendcntl;
     int pixel_shift;
-    int has_tcl = ((info->ChipFamily != CHIP_FAMILY_RS690) &&
-		   (info->ChipFamily != CHIP_FAMILY_RS740) &&
-		   (info->ChipFamily != CHIP_FAMILY_RS400) &&
-		   (info->ChipFamily != CHIP_FAMILY_RV515));
     ACCEL_PREAMBLE();
 
     TRACE;
@@ -1050,6 +1191,11 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture,
     if (!R300GetDestFormat(pDstPicture, &dst_format))
 	return FALSE;
 
+    if (pMask)
+	has_mask = TRUE;
+    else
+	has_mask = FALSE;
+
     pixel_shift = pDst->drawable.bitsPerPixel >> 4;
 
     dst_offset = exaGetPixmapOffset(pDst) + info->fbLocation;
@@ -1066,6 +1212,9 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture,
     if (((dst_pitch >> pixel_shift) & 0x7) != 0)
 	RADEON_FALLBACK(("Bad destination pitch 0x%x\n", (int)dst_pitch));
 
+    if (!RADEONSetupSourceTile(pSrcPicture, pSrc, TRUE, FALSE))
+	return FALSE;
+
     if (!FUNC_NAME(R300TextureSetup)(pSrcPicture, pSrc, 0))
 	return FALSE;
     txenable = R300_TEX_0_ENABLE;
@@ -1081,27 +1230,32 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture,
     RADEON_SWITCH_TO_3D();
 
     /* setup the VAP */
-    if (has_tcl) {
-	BEGIN_ACCEL(9);
-	OUT_ACCEL_REG(R300_VAP_CNTL_STATUS, 0);
-	OUT_ACCEL_REG(R300_VAP_PVS_STATE_FLUSH_REG, 0);
-	OUT_ACCEL_REG(R300_VAP_CNTL, ((6 << R300_PVS_NUM_SLOTS_SHIFT) |
-				      (5 << R300_PVS_NUM_CNTLRS_SHIFT) |
-				      (4 << R300_PVS_NUM_FPUS_SHIFT) |
-				      (12 << R300_VF_MAX_VTX_NUM_SHIFT)));
+    if (info->has_tcl) {
+	if (pMask)
+	    BEGIN_ACCEL(8);
+	else
+	    BEGIN_ACCEL(7);
     } else {
-	BEGIN_ACCEL(8);
-	OUT_ACCEL_REG(R300_VAP_CNTL_STATUS, R300_PVS_BYPASS);
-	OUT_ACCEL_REG(R300_VAP_CNTL, ((10 << R300_PVS_NUM_SLOTS_SHIFT) |
-				      (5 << R300_PVS_NUM_CNTLRS_SHIFT) |
-				      (4 << R300_PVS_NUM_FPUS_SHIFT) |
-				      (5 << R300_VF_MAX_VTX_NUM_SHIFT)));
+	if (pMask)
+	    BEGIN_ACCEL(6);
+	else
+	    BEGIN_ACCEL(5);
     }
 
-    OUT_ACCEL_REG(R300_VAP_VTE_CNTL, R300_VTX_XY_FMT | R300_VTX_Z_FMT);
-    OUT_ACCEL_REG(R300_VAP_PSC_SGN_NORM_CNTL, 0);
-
-    if (has_tcl) {
+    /* These registers define the number, type, and location of data submitted
+     * to the PVS unit of GA input (when PVS is disabled)
+     * DST_VEC_LOC is the slot in the PVS input vector memory when PVS/TCL is
+     * enabled.  This memory provides the imputs to the vertex shader program
+     * and ordering is not important.  When PVS/TCL is disabled, this field maps
+     * directly to the GA input memory and the order is signifigant.  In
+     * PVS_BYPASS mode the order is as follows:
+     * Position
+     * Point Size
+     * Color 0-3
+     * Textures 0-7
+     * Fog
+     */
+    if (pMask) {
 	OUT_ACCEL_REG(R300_VAP_PROG_STREAM_CNTL_0,
 		      ((R300_DATA_TYPE_FLOAT_2 << R300_DATA_TYPE_0_SHIFT) |
 		       (0 << R300_SKIP_DWORDS_0_SHIFT) |
@@ -1109,35 +1263,15 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture,
 		       R300_SIGNED_0 |
 		       (R300_DATA_TYPE_FLOAT_2 << R300_DATA_TYPE_1_SHIFT) |
 		       (0 << R300_SKIP_DWORDS_1_SHIFT) |
-		       (1 << R300_DST_VEC_LOC_1_SHIFT) |
+		       (6 << R300_DST_VEC_LOC_1_SHIFT) |
 		       R300_SIGNED_1));
 	OUT_ACCEL_REG(R300_VAP_PROG_STREAM_CNTL_1,
 		      ((R300_DATA_TYPE_FLOAT_2 << R300_DATA_TYPE_2_SHIFT) |
 		       (0 << R300_SKIP_DWORDS_2_SHIFT) |
-		       (2 << R300_DST_VEC_LOC_2_SHIFT) |
+		       (7 << R300_DST_VEC_LOC_2_SHIFT) |
 		       R300_LAST_VEC_2 |
 		       R300_SIGNED_2));
-	OUT_ACCEL_REG(R300_VAP_PROG_STREAM_CNTL_EXT_0,
-		      ((R300_SWIZZLE_SELECT_X << R300_SWIZZLE_SELECT_X_0_SHIFT) |
-		       (R300_SWIZZLE_SELECT_Y << R300_SWIZZLE_SELECT_Y_0_SHIFT) |
-		       (R300_SWIZZLE_SELECT_FP_ZERO << R300_SWIZZLE_SELECT_Z_0_SHIFT) |
-		       (R300_SWIZZLE_SELECT_FP_ONE << R300_SWIZZLE_SELECT_W_0_SHIFT) |
-		       ((R300_WRITE_ENA_X | R300_WRITE_ENA_Y | R300_WRITE_ENA_Z | R300_WRITE_ENA_W)
-			<< R300_WRITE_ENA_0_SHIFT) |
-		       (R300_SWIZZLE_SELECT_X << R300_SWIZZLE_SELECT_X_1_SHIFT) |
-		       (R300_SWIZZLE_SELECT_Y << R300_SWIZZLE_SELECT_Y_1_SHIFT) |
-		       (R300_SWIZZLE_SELECT_FP_ZERO << R300_SWIZZLE_SELECT_Z_1_SHIFT) |
-		       (R300_SWIZZLE_SELECT_FP_ONE << R300_SWIZZLE_SELECT_W_1_SHIFT) |
-		       ((R300_WRITE_ENA_X | R300_WRITE_ENA_Y | R300_WRITE_ENA_Z | R300_WRITE_ENA_W)
-			<< R300_WRITE_ENA_1_SHIFT)));
-	OUT_ACCEL_REG(R300_VAP_PROG_STREAM_CNTL_EXT_1,
-		      ((R300_SWIZZLE_SELECT_X << R300_SWIZZLE_SELECT_X_2_SHIFT) |
-		       (R300_SWIZZLE_SELECT_Y << R300_SWIZZLE_SELECT_Y_2_SHIFT) |
-		       (R300_SWIZZLE_SELECT_FP_ZERO << R300_SWIZZLE_SELECT_Z_2_SHIFT) |
-		       (R300_SWIZZLE_SELECT_FP_ONE << R300_SWIZZLE_SELECT_W_2_SHIFT) |
-		       ((R300_WRITE_ENA_X | R300_WRITE_ENA_Y | R300_WRITE_ENA_Z | R300_WRITE_ENA_W)
-			<< R300_WRITE_ENA_2_SHIFT)));
-    } else {
+    } else
 	OUT_ACCEL_REG(R300_VAP_PROG_STREAM_CNTL_0,
 		      ((R300_DATA_TYPE_FLOAT_2 << R300_DATA_TYPE_0_SHIFT) |
 		       (0 << R300_SKIP_DWORDS_0_SHIFT) |
@@ -1146,43 +1280,18 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture,
 		       (R300_DATA_TYPE_FLOAT_2 << R300_DATA_TYPE_1_SHIFT) |
 		       (0 << R300_SKIP_DWORDS_1_SHIFT) |
 		       (6 << R300_DST_VEC_LOC_1_SHIFT) |
+		       R300_LAST_VEC_1 |
 		       R300_SIGNED_1));
-	OUT_ACCEL_REG(R300_VAP_PROG_STREAM_CNTL_1,
-		      ((R300_DATA_TYPE_FLOAT_2 << R300_DATA_TYPE_2_SHIFT) |
-		       (0 << R300_SKIP_DWORDS_2_SHIFT) |
-		       (7 << R300_DST_VEC_LOC_2_SHIFT) |
-		       R300_LAST_VEC_2 |
-		       R300_SIGNED_2));
-	OUT_ACCEL_REG(R300_VAP_PROG_STREAM_CNTL_EXT_0,
-		      ((R300_SWIZZLE_SELECT_X << R300_SWIZZLE_SELECT_X_0_SHIFT) |
-		       (R300_SWIZZLE_SELECT_Y << R300_SWIZZLE_SELECT_Y_0_SHIFT) |
-		       (R300_SWIZZLE_SELECT_FP_ZERO << R300_SWIZZLE_SELECT_Z_0_SHIFT) |
-		       (R300_SWIZZLE_SELECT_FP_ONE << R300_SWIZZLE_SELECT_W_0_SHIFT) |
-		       ((R300_WRITE_ENA_X | R300_WRITE_ENA_Y | R300_WRITE_ENA_Z | R300_WRITE_ENA_W)
-			<< R300_WRITE_ENA_0_SHIFT) |
-		       (R300_SWIZZLE_SELECT_X << R300_SWIZZLE_SELECT_X_1_SHIFT) |
-		       (R300_SWIZZLE_SELECT_Y << R300_SWIZZLE_SELECT_Y_1_SHIFT) |
-		       (R300_SWIZZLE_SELECT_FP_ZERO << R300_SWIZZLE_SELECT_Z_1_SHIFT) |
-		       (R300_SWIZZLE_SELECT_FP_ONE << R300_SWIZZLE_SELECT_W_1_SHIFT) |
-		       ((R300_WRITE_ENA_X | R300_WRITE_ENA_Y | R300_WRITE_ENA_Z | R300_WRITE_ENA_W)
-			<< R300_WRITE_ENA_1_SHIFT)));
-	OUT_ACCEL_REG(R300_VAP_PROG_STREAM_CNTL_EXT_1,
-		      ((R300_SWIZZLE_SELECT_X << R300_SWIZZLE_SELECT_X_2_SHIFT) |
-		       (R300_SWIZZLE_SELECT_Y << R300_SWIZZLE_SELECT_Y_2_SHIFT) |
-		       (R300_SWIZZLE_SELECT_FP_ZERO << R300_SWIZZLE_SELECT_Z_2_SHIFT) |
-		       (R300_SWIZZLE_SELECT_FP_ONE << R300_SWIZZLE_SELECT_W_2_SHIFT) |
-		       ((R300_WRITE_ENA_X | R300_WRITE_ENA_Y | R300_WRITE_ENA_Z | R300_WRITE_ENA_W)
-			<< R300_WRITE_ENA_2_SHIFT)));
-    }
-    FINISH_ACCEL();
 
-    /* setup the vertex shader */
-    if (has_tcl) {
+    /* load the vertex shader
+     * We pre-load vertex programs in RADEONInit3DEngine():
+     * - exa no mask
+     * - exa mask
+     * - Xv
+     * Here we select the offset of the vertex program we want to use
+     */
+    if (info->has_tcl) {
 	if (pMask) {
-	    BEGIN_ACCEL(22);
-	    /* flush the PVS before updating??? */
-	    OUT_ACCEL_REG(R300_VAP_PVS_STATE_FLUSH_REG, 0);
-
 	    OUT_ACCEL_REG(R300_VAP_PVS_CODE_CNTL_0,
 			  ((0 << R300_PVS_FIRST_INST_SHIFT) |
 			   (2 << R300_PVS_XYZW_VALID_INST_SHIFT) |
@@ -1190,122 +1299,24 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture,
 	    OUT_ACCEL_REG(R300_VAP_PVS_CODE_CNTL_1,
 			  (2 << R300_PVS_LAST_VTX_SRC_INST_SHIFT));
 	} else {
-	    BEGIN_ACCEL(18);
-	    /* flush the PVS before updating??? */
-	    OUT_ACCEL_REG(R300_VAP_PVS_STATE_FLUSH_REG, 0);
-
 	    OUT_ACCEL_REG(R300_VAP_PVS_CODE_CNTL_0,
-			  ((0 << R300_PVS_FIRST_INST_SHIFT) |
-			   (1 << R300_PVS_XYZW_VALID_INST_SHIFT) |
-			   (1 << R300_PVS_LAST_INST_SHIFT)));
+			  ((3 << R300_PVS_FIRST_INST_SHIFT) |
+			   (4 << R300_PVS_XYZW_VALID_INST_SHIFT) |
+			   (4 << R300_PVS_LAST_INST_SHIFT)));
 	    OUT_ACCEL_REG(R300_VAP_PVS_CODE_CNTL_1,
-			  (1 << R300_PVS_LAST_VTX_SRC_INST_SHIFT));
-	}
-	OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_INDX_REG, 0);
-	/* PVS inst 0 */
-	OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
-		      (R300_PVS_DST_OPCODE(R300_VE_ADD) |
-		       R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_OUT) |
-		       R300_PVS_DST_OFFSET(0) |
-		       R300_PVS_DST_WE_X | R300_PVS_DST_WE_Y |
-		       R300_PVS_DST_WE_Z | R300_PVS_DST_WE_W));
-	OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
-		      (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
-		       R300_PVS_SRC_OFFSET(0) |
-		       R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) |
-		       R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) |
-		       R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_Z) |
-		       R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_W)));
-	OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
-		      (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
-		       R300_PVS_SRC_OFFSET(0) |
-		       R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) |
-		       R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) |
-		       R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
-		       R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
-	OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
-		      (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
-		       R300_PVS_SRC_OFFSET(0) |
-		       R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) |
-		       R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) |
-		       R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
-		       R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
-
-	/* PVS inst 1 */
-	OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
-		      (R300_PVS_DST_OPCODE(R300_VE_ADD) |
-		       R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_OUT) |
-		       R300_PVS_DST_OFFSET(1) |
-		       R300_PVS_DST_WE_X | R300_PVS_DST_WE_Y |
-		       R300_PVS_DST_WE_Z | R300_PVS_DST_WE_W));
-	OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
-		      (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
-		       R300_PVS_SRC_OFFSET(1) |
-		       R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) |
-		       R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) |
-		       R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_Z) |
-		       R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_W)));
-	OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
-		      (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
-		       R300_PVS_SRC_OFFSET(1) |
-		       R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) |
-		       R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) |
-		       R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
-		       R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
-	OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
-		      (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
-		       R300_PVS_SRC_OFFSET(1) |
-		       R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) |
-		       R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) |
-		       R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
-		       R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
-
-	if (pMask) {
-	    /* PVS inst 2 */
-	    OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
-			  (R300_PVS_DST_OPCODE(R300_VE_ADD) |
-			   R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_OUT) |
-			   R300_PVS_DST_OFFSET(2) |
-			   R300_PVS_DST_WE_X | R300_PVS_DST_WE_Y |
-			   R300_PVS_DST_WE_Z | R300_PVS_DST_WE_W));
-	    OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
-			  (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
-			   R300_PVS_SRC_OFFSET(2) |
-			   R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) |
-			   R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) |
-			   R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_Z) |
-			   R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_W)));
-	    OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
-			  (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
-			   R300_PVS_SRC_OFFSET(2) |
-			   R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) |
-			   R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) |
-			   R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
-			   R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
-	    OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
-			  (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
-			   R300_PVS_SRC_OFFSET(2) |
-			   R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) |
-			   R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) |
-			   R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
-			   R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
+			  (4 << R300_PVS_LAST_VTX_SRC_INST_SHIFT));
 	}
-
-	OUT_ACCEL_REG(R300_VAP_PVS_FLOW_CNTL_OPC, 0);
-
-	OUT_ACCEL_REG(R300_VAP_GB_VERT_CLIP_ADJ, 0x3f800000);
-	OUT_ACCEL_REG(R300_VAP_GB_VERT_DISC_ADJ, 0x3f800000);
-	OUT_ACCEL_REG(R300_VAP_GB_HORZ_CLIP_ADJ, 0x3f800000);
-	OUT_ACCEL_REG(R300_VAP_GB_HORZ_DISC_ADJ, 0x3f800000);
-	OUT_ACCEL_REG(R300_VAP_CLIP_CNTL, R300_CLIP_DISABLE);
-	FINISH_ACCEL();
     }
 
-    BEGIN_ACCEL(4);
+    /* Position and one or two sets of 2 texture coordinates */
     OUT_ACCEL_REG(R300_VAP_OUT_VTX_FMT_0, R300_VTX_POS_PRESENT);
-    OUT_ACCEL_REG(R300_VAP_OUT_VTX_FMT_1,
-		  ((2 << R300_TEX_0_COMP_CNT_SHIFT) |
-		   (2 << R300_TEX_1_COMP_CNT_SHIFT)));
+    if (pMask)
+	OUT_ACCEL_REG(R300_VAP_OUT_VTX_FMT_1,
+		      ((2 << R300_TEX_0_COMP_CNT_SHIFT) |
+		       (2 << R300_TEX_1_COMP_CNT_SHIFT)));
+    else
+	OUT_ACCEL_REG(R300_VAP_OUT_VTX_FMT_1,
+		      (2 << R300_TEX_0_COMP_CNT_SHIFT));
 
     OUT_ACCEL_REG(R300_TX_INVALTAGS, 0x0);
     OUT_ACCEL_REG(R300_TX_ENABLE, txenable);
@@ -1394,15 +1405,6 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture,
 			  R300_OUT_FMT_C2_SEL_BLUE |
 			  R300_OUT_FMT_C3_SEL_ALPHA);
 	    break;
-	case PICT_r5g6b5:
-	case PICT_a1r5g5b5:
-	case PICT_x1r5g5b5:
-	    output_fmt = (R300_OUT_FMT_C_5_6_5 |
-			  R300_OUT_FMT_C0_SEL_BLUE |
-			  R300_OUT_FMT_C1_SEL_GREEN |
-			  R300_OUT_FMT_C2_SEL_RED |
-			  R300_OUT_FMT_C3_SEL_ALPHA);
-	    break;
 	case PICT_a8:
 	    output_fmt = (R300_OUT_FMT_C4_8 |
 			  R300_OUT_FMT_C0_SEL_ALPHA);
@@ -1410,95 +1412,41 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture,
 	}
 
 
-	/* setup the rasterizer */
+	/* setup the rasterizer, load FS */
+	BEGIN_ACCEL(9);
 	if (pMask) {
-	    BEGIN_ACCEL(20);
 	    /* 4 components: 2 for tex0, 2 for tex1 */
 	    OUT_ACCEL_REG(R300_RS_COUNT,
 			  ((4 << R300_RS_COUNT_IT_COUNT_SHIFT) |
 			   R300_RS_COUNT_HIRES_EN));
-	    /* rasterizer source table */
-	    OUT_ACCEL_REG(R300_RS_IP_0,
-			  (R300_RS_TEX_PTR(0) |
-			   R300_RS_SEL_S(R300_RS_SEL_C0) |
-			   R300_RS_SEL_T(R300_RS_SEL_C1) |
-			   R300_RS_SEL_R(R300_RS_SEL_K0) |
-			   R300_RS_SEL_Q(R300_RS_SEL_K1)));
-	    OUT_ACCEL_REG(R300_RS_IP_1,
-			  (R300_RS_TEX_PTR(2) |
-			   R300_RS_SEL_S(R300_RS_SEL_C0) |
-			   R300_RS_SEL_T(R300_RS_SEL_C1) |
-			   R300_RS_SEL_R(R300_RS_SEL_K0) |
-			   R300_RS_SEL_Q(R300_RS_SEL_K1)));
 
+	    /* R300_INST_COUNT_RS - highest RS instruction used */
 	    OUT_ACCEL_REG(R300_RS_INST_COUNT, R300_INST_COUNT_RS(1) | R300_TX_OFFSET_RS(6));
-	    /* src tex */
-	    OUT_ACCEL_REG(R300_RS_INST_0, (R300_INST_TEX_ID(0) |
-					   R300_RS_INST_TEX_CN_WRITE |
-					   R300_INST_TEX_ADDR(0)));
-	    /* mask tex */
-	    OUT_ACCEL_REG(R300_RS_INST_1, (R300_INST_TEX_ID(1) |
-					   R300_RS_INST_TEX_CN_WRITE |
-					   R300_INST_TEX_ADDR(1)));
-
-	    OUT_ACCEL_REG(R300_US_CONFIG, (0 << R300_NLEVEL_SHIFT) | R300_FIRST_TEX);
-	    OUT_ACCEL_REG(R300_US_PIXSIZE, 1); /* max num of temps used */
+
 	    OUT_ACCEL_REG(R300_US_CODE_OFFSET, (R300_ALU_CODE_OFFSET(0) |
 						R300_ALU_CODE_SIZE(0) |
 						R300_TEX_CODE_OFFSET(0) |
 						R300_TEX_CODE_SIZE(1)));
 
+	    OUT_ACCEL_REG(R300_US_CODE_ADDR_3,
+			  (R300_ALU_START(0) |
+			   R300_ALU_SIZE(0) |
+			   R300_TEX_START(0) |
+			   R300_TEX_SIZE(1) |
+			   R300_RGBA_OUT));
 	} else {
-	    BEGIN_ACCEL(17);
 	    /* 2 components: 2 for tex0 */
 	    OUT_ACCEL_REG(R300_RS_COUNT,
 			  ((2 << R300_RS_COUNT_IT_COUNT_SHIFT) |
 			   R300_RS_COUNT_HIRES_EN));
-	    OUT_ACCEL_REG(R300_RS_IP_0,
-			  (R300_RS_TEX_PTR(0) |
-			   R300_RS_SEL_S(R300_RS_SEL_C0) |
-			   R300_RS_SEL_T(R300_RS_SEL_C1) |
-			   R300_RS_SEL_R(R300_RS_SEL_K0) |
-			   R300_RS_SEL_Q(R300_RS_SEL_K1)));
+
 	    OUT_ACCEL_REG(R300_RS_INST_COUNT, R300_INST_COUNT_RS(0) | R300_TX_OFFSET_RS(6));
-	    /* src tex */
-	    OUT_ACCEL_REG(R300_RS_INST_0, (R300_INST_TEX_ID(0) |
-					   R300_RS_INST_TEX_CN_WRITE |
-					   R300_INST_TEX_ADDR(0)));
 
-	    OUT_ACCEL_REG(R300_US_CONFIG, (0 << R300_NLEVEL_SHIFT) | R300_FIRST_TEX);
-	    OUT_ACCEL_REG(R300_US_PIXSIZE, 1); /* max num of temps used */
 	    OUT_ACCEL_REG(R300_US_CODE_OFFSET, (R300_ALU_CODE_OFFSET(0) |
 						R300_ALU_CODE_SIZE(0) |
 						R300_TEX_CODE_OFFSET(0) |
 						R300_TEX_CODE_SIZE(0)));
 
-	}
-
-	OUT_ACCEL_REG(R300_US_CODE_ADDR_0,
-		      (R300_ALU_START(0) |
-		       R300_ALU_SIZE(0) |
-		       R300_TEX_START(0) |
-		       R300_TEX_SIZE(0)));
-	OUT_ACCEL_REG(R300_US_CODE_ADDR_1,
-		      (R300_ALU_START(0) |
-		       R300_ALU_SIZE(0) |
-		       R300_TEX_START(0) |
-		       R300_TEX_SIZE(0)));
-	OUT_ACCEL_REG(R300_US_CODE_ADDR_2,
-		      (R300_ALU_START(0) |
-		       R300_ALU_SIZE(0) |
-		       R300_TEX_START(0) |
-		       R300_TEX_SIZE(0)));
-
-	if (pMask) {
-	    OUT_ACCEL_REG(R300_US_CODE_ADDR_3,
-			  (R300_ALU_START(0) |
-			   R300_ALU_SIZE(0) |
-			   R300_TEX_START(0) |
-			   R300_TEX_SIZE(1) |
-			   R300_RGBA_OUT));
-	} else {
 	    OUT_ACCEL_REG(R300_US_CODE_ADDR_3,
 			  (R300_ALU_START(0) |
 			   R300_ALU_SIZE(0) |
@@ -1507,22 +1455,19 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture,
 			   R300_RGBA_OUT));
 	}
 
+	/* shader output swizzling */
 	OUT_ACCEL_REG(R300_US_OUT_FMT_0, output_fmt);
 
-	OUT_ACCEL_REG(R300_US_TEX_INST_0,
-		      (R300_TEX_SRC_ADDR(0) |
-		       R300_TEX_DST_ADDR(0) |
-		       R300_TEX_ID(0) |
-		       R300_TEX_INST(R300_TEX_INST_LD)));
-
-	if (pMask) {
-	    OUT_ACCEL_REG(R300_US_TEX_INST_1,
-			  (R300_TEX_SRC_ADDR(1) |
-			   R300_TEX_DST_ADDR(1) |
-			   R300_TEX_ID(1) |
-			   R300_TEX_INST(R300_TEX_INST_LD)));
-	}
+	/* tex inst for src texture is pre-loaded in RADEONInit3DEngine() */
+	/* tex inst for mask texture is pre-loaded in RADEONInit3DEngine() */
 
+	/* RGB inst
+	 * temp addresses for texture inputs
+	 * ALU_RGB_ADDR0 is src tex (temp 0)
+	 * ALU_RGB_ADDR1 is mask tex (temp 1)
+	 * R300_ALU_RGB_OMASK - output components to write
+	 * R300_ALU_RGB_TARGET_A - render target
+	 */
 	OUT_ACCEL_REG(R300_US_ALU_RGB_ADDR_0,
 		      (R300_ALU_RGB_ADDR0(0) |
 		       R300_ALU_RGB_ADDR1(1) |
@@ -1532,6 +1477,9 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture,
 					   R300_ALU_RGB_MASK_G |
 					   R300_ALU_RGB_MASK_B)) |
 		       R300_ALU_RGB_TARGET_A));
+	/* RGB inst
+	 * ALU operation
+	 */
 	OUT_ACCEL_REG(R300_US_ALU_RGB_INST_0,
 		      (R300_ALU_RGB_SEL_A(src_color) |
 		       R300_ALU_RGB_MOD_A(R300_ALU_RGB_MOD_NOP) |
@@ -1542,6 +1490,13 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture,
 		       R300_ALU_RGB_OP(R300_ALU_RGB_OP_MAD) |
 		       R300_ALU_RGB_OMOD(R300_ALU_RGB_OMOD_NONE) |
 		       R300_ALU_RGB_CLAMP));
+	/* Alpha inst
+	 * temp addresses for texture inputs
+	 * ALU_ALPHA_ADDR0 is src tex (0)
+	 * ALU_ALPHA_ADDR1 is mask tex (1)
+	 * R300_ALU_ALPHA_OMASK - output components to write
+	 * R300_ALU_ALPHA_TARGET_A - render target
+	 */
 	OUT_ACCEL_REG(R300_US_ALU_ALPHA_ADDR_0,
 		      (R300_ALU_ALPHA_ADDR0(0) |
 		       R300_ALU_ALPHA_ADDR1(1) |
@@ -1550,6 +1505,9 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture,
 		       R300_ALU_ALPHA_OMASK(R300_ALU_ALPHA_MASK_A) |
 		       R300_ALU_ALPHA_TARGET_A |
 		       R300_ALU_ALPHA_OMASK_W(R300_ALU_ALPHA_MASK_NONE)));
+	/* Alpha inst
+	 * ALU operation
+	 */
 	OUT_ACCEL_REG(R300_US_ALU_ALPHA_INST_0,
 		      (R300_ALU_ALPHA_SEL_A(src_alpha) |
 		       R300_ALU_ALPHA_MOD_A(R300_ALU_ALPHA_MOD_NOP) |
@@ -1567,103 +1525,80 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture,
 	CARD32 mask_color, mask_alpha;
 
 	if (PICT_FORMAT_RGB(pSrcPicture->format) == 0)
-	    //src_color = R300_ALU_RGB_0_0;
 	    src_color = (R500_ALU_RGB_R_SWIZ_A_0 |
 			 R500_ALU_RGB_G_SWIZ_A_0 |
 			 R500_ALU_RGB_B_SWIZ_A_0);
 	else
-	    //src_color = R300_ALU_RGB_SRC0_RGB;
 	    src_color = (R500_ALU_RGB_R_SWIZ_A_R |
 			 R500_ALU_RGB_G_SWIZ_A_G |
 			 R500_ALU_RGB_B_SWIZ_A_B);
 
 	if (PICT_FORMAT_A(pSrcPicture->format) == 0)
-	    //src_alpha = R300_ALU_ALPHA_1_0;
 	    src_alpha = R500_ALPHA_SWIZ_A_1;
 	else
-	    //src_alpha = R300_ALU_ALPHA_SRC0_A;
 	    src_alpha = R500_ALPHA_SWIZ_A_A;
 
 	if (pMask && pMaskPicture->componentAlpha) {
 	    if (RadeonBlendOp[op].src_alpha) {
 		if (PICT_FORMAT_A(pSrcPicture->format) == 0) {
-		    //src_color = R300_ALU_RGB_1_0;
-		    //src_alpha = R300_ALU_ALPHA_1_0;
 		    src_color = (R500_ALU_RGB_R_SWIZ_A_1 |
 				 R500_ALU_RGB_G_SWIZ_A_1 |
 				 R500_ALU_RGB_B_SWIZ_A_1);
 		    src_alpha = R500_ALPHA_SWIZ_A_1;
 		} else {
-		    //src_color = R300_ALU_RGB_SRC0_AAA;
-		    //src_alpha = R300_ALU_ALPHA_SRC0_A;
 		    src_color = (R500_ALU_RGB_R_SWIZ_A_A |
 				 R500_ALU_RGB_G_SWIZ_A_A |
 				 R500_ALU_RGB_B_SWIZ_A_A);
 		    src_alpha = R500_ALPHA_SWIZ_A_A;
 		}
 
-		//mask_color = R300_ALU_RGB_SRC1_RGB;
 		mask_color = (R500_ALU_RGB_R_SWIZ_B_R |
 			      R500_ALU_RGB_G_SWIZ_B_G |
 			      R500_ALU_RGB_B_SWIZ_B_B);
 
 		if (PICT_FORMAT_A(pMaskPicture->format) == 0)
-		    //mask_alpha = R300_ALU_ALPHA_1_0;
 		    mask_alpha = R500_ALPHA_SWIZ_B_1;
 		else
-		    //mask_alpha = R300_ALU_ALPHA_SRC1_A;
 		    mask_alpha = R500_ALPHA_SWIZ_B_A;
 
 	    } else {
-		//src_color = R300_ALU_RGB_SRC0_RGB;
 		src_color = (R500_ALU_RGB_R_SWIZ_A_R |
 			     R500_ALU_RGB_G_SWIZ_A_G |
 			     R500_ALU_RGB_B_SWIZ_A_B);
 
 		if (PICT_FORMAT_A(pSrcPicture->format) == 0)
-		    //src_alpha = R300_ALU_ALPHA_1_0;
 		    src_alpha = R500_ALPHA_SWIZ_A_1;
 		else
-		    //src_alpha = R300_ALU_ALPHA_SRC0_A;
 		    src_alpha = R500_ALPHA_SWIZ_A_A;
 
-		//mask_color = R300_ALU_RGB_SRC1_RGB;
 		mask_color = (R500_ALU_RGB_R_SWIZ_B_R |
 			      R500_ALU_RGB_G_SWIZ_B_G |
 			      R500_ALU_RGB_B_SWIZ_B_B);
 
 		if (PICT_FORMAT_A(pMaskPicture->format) == 0)
-		    //mask_alpha = R300_ALU_ALPHA_1_0;
 		    mask_alpha = R500_ALPHA_SWIZ_B_1;
 		else
-		    //mask_alpha = R300_ALU_ALPHA_SRC1_A;
 		    mask_alpha = R500_ALPHA_SWIZ_B_A;
 
 	    }
 	} else if (pMask) {
 	    if (PICT_FORMAT_A(pMaskPicture->format) == 0)
-		//mask_color = R300_ALU_RGB_1_0;
 		mask_color = (R500_ALU_RGB_R_SWIZ_B_1 |
 			      R500_ALU_RGB_G_SWIZ_B_1 |
 			      R500_ALU_RGB_B_SWIZ_B_1);
 	    else
-		//mask_color = R300_ALU_RGB_SRC1_AAA;
 		mask_color = (R500_ALU_RGB_R_SWIZ_B_A |
 			      R500_ALU_RGB_G_SWIZ_B_A |
 			      R500_ALU_RGB_B_SWIZ_B_A);
 
 	    if (PICT_FORMAT_A(pMaskPicture->format) == 0)
-		//mask_alpha = R300_ALU_ALPHA_1_0;
 		mask_alpha = R500_ALPHA_SWIZ_B_1;
 	    else
-		//mask_alpha = R300_ALU_ALPHA_SRC1_A;
 		mask_alpha = R500_ALPHA_SWIZ_B_A;
 	} else {
-	    //mask_color = R300_ALU_RGB_1_0;
 	    mask_color = (R500_ALU_RGB_R_SWIZ_B_1 |
 			  R500_ALU_RGB_G_SWIZ_B_1 |
 			  R500_ALU_RGB_B_SWIZ_B_1);
-	    //mask_alpha = R300_ALU_ALPHA_1_0;
 	    mask_alpha = R500_ALPHA_SWIZ_B_1;
 	}
 
@@ -1686,76 +1621,34 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture,
 			  R300_OUT_FMT_C2_SEL_BLUE |
 			  R300_OUT_FMT_C3_SEL_ALPHA);
 	    break;
-	case PICT_r5g6b5:
-	case PICT_a1r5g5b5:
-	case PICT_x1r5g5b5:
-	    output_fmt = (R300_OUT_FMT_C_5_6_5 |
-			  R300_OUT_FMT_C0_SEL_BLUE |
-			  R300_OUT_FMT_C1_SEL_GREEN |
-			  R300_OUT_FMT_C2_SEL_RED |
-			  R300_OUT_FMT_C3_SEL_ALPHA);
-	    break;
 	case PICT_a8:
 	    output_fmt = (R300_OUT_FMT_C4_8 |
 			  R300_OUT_FMT_C0_SEL_ALPHA);
 	    break;
 	}
 
+	BEGIN_ACCEL(6);
 	if (pMask) {
-	    BEGIN_ACCEL(13);
+	    /* 4 components: 2 for tex0, 2 for tex1 */
 	    OUT_ACCEL_REG(R300_RS_COUNT,
 			  ((4 << R300_RS_COUNT_IT_COUNT_SHIFT) |
 			   R300_RS_COUNT_HIRES_EN));
-	    OUT_ACCEL_REG(R500_RS_IP_0, ((0 << R500_RS_IP_TEX_PTR_S_SHIFT) |
-					 (1 << R500_RS_IP_TEX_PTR_T_SHIFT) |
-					 (R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_R_SHIFT) |
-					 (R500_RS_IP_PTR_K1 << R500_RS_IP_TEX_PTR_Q_SHIFT)));
-
-	    OUT_ACCEL_REG(R500_RS_IP_1, ((2 << R500_RS_IP_TEX_PTR_S_SHIFT) |
-					 (3 << R500_RS_IP_TEX_PTR_T_SHIFT) |
-					 (R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_R_SHIFT) |
-					 (R500_RS_IP_PTR_K1 << R500_RS_IP_TEX_PTR_Q_SHIFT)));
 
+	    /* 2 RS instructions: 1 for tex0 (src), 1 for tex1 (mask) */
 	    OUT_ACCEL_REG(R300_RS_INST_COUNT, R300_INST_COUNT_RS(1) | R300_TX_OFFSET_RS(6));
 
-	    /* src tex */
-	    OUT_ACCEL_REG(R500_RS_INST_0, ((0 << R500_RS_INST_TEX_ID_SHIFT) |
-					   R500_RS_INST_TEX_CN_WRITE |
-					   (0 << R500_RS_INST_TEX_ADDR_SHIFT)));
-	    /* mask tex */
-	    OUT_ACCEL_REG(R500_RS_INST_1, ((1 << R500_RS_INST_TEX_ID_SHIFT) |
-					   R500_RS_INST_TEX_CN_WRITE |
-					   (1 << R500_RS_INST_TEX_ADDR_SHIFT)));
-
-	    OUT_ACCEL_REG(R300_US_CONFIG, R500_ZERO_TIMES_ANYTHING_EQUALS_ZERO);
-	    OUT_ACCEL_REG(R300_US_PIXSIZE, 1);
-	    OUT_ACCEL_REG(R500_US_FC_CTRL, 0);
 	    OUT_ACCEL_REG(R500_US_CODE_ADDR, (R500_US_CODE_START_ADDR(0) |
 					      R500_US_CODE_END_ADDR(2)));
 	    OUT_ACCEL_REG(R500_US_CODE_RANGE, (R500_US_CODE_RANGE_ADDR(0) |
 					       R500_US_CODE_RANGE_SIZE(2)));
 	    OUT_ACCEL_REG(R500_US_CODE_OFFSET, 0);
 	} else {
-	    BEGIN_ACCEL(11);
 	    OUT_ACCEL_REG(R300_RS_COUNT,
 			  ((2 << R300_RS_COUNT_IT_COUNT_SHIFT) |
 			   R300_RS_COUNT_HIRES_EN));
 
-	    OUT_ACCEL_REG(R500_RS_IP_0, ((0 << R500_RS_IP_TEX_PTR_S_SHIFT) |
-					 (1 << R500_RS_IP_TEX_PTR_T_SHIFT) |
-					 (R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_R_SHIFT) |
-					 (R500_RS_IP_PTR_K1 << R500_RS_IP_TEX_PTR_Q_SHIFT)));
-
-	    OUT_ACCEL_REG(R300_RS_INST_COUNT, R300_INST_COUNT_RS(1) | R300_TX_OFFSET_RS(6));
-
-	    /* src tex */
-	    OUT_ACCEL_REG(R500_RS_INST_0, ((0 << R500_RS_INST_TEX_ID_SHIFT) |
-					   R500_RS_INST_TEX_CN_WRITE |
-					   (0 << R500_RS_INST_TEX_ADDR_SHIFT)));
+	    OUT_ACCEL_REG(R300_RS_INST_COUNT, R300_INST_COUNT_RS(0) | R300_TX_OFFSET_RS(6));
 
-	    OUT_ACCEL_REG(R300_US_CONFIG, R500_ZERO_TIMES_ANYTHING_EQUALS_ZERO);
-	    OUT_ACCEL_REG(R300_US_PIXSIZE, 1);
-	    OUT_ACCEL_REG(R500_US_FC_CTRL, 0);
 	    OUT_ACCEL_REG(R500_US_CODE_ADDR, (R500_US_CODE_START_ADDR(0) |
 					      R500_US_CODE_END_ADDR(1)));
 	    OUT_ACCEL_REG(R500_US_CODE_RANGE, (R500_US_CODE_RANGE_ADDR(0) |
@@ -1769,6 +1662,7 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture,
 	if (pMask) {
 	    BEGIN_ACCEL(19);
 	    OUT_ACCEL_REG(R500_GA_US_VECTOR_INDEX, 0);
+	    /* tex inst for src texture */
 	    OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_TEX |
 						   R500_INST_RGB_WMASK_R |
 						   R500_INST_RGB_WMASK_G |
@@ -1798,10 +1692,11 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture,
 						   R500_DY_S_SWIZ_R |
 						   R500_DY_T_SWIZ_R |
 						   R500_DY_R_SWIZ_R |
-						   R500_DY_Q_SWIZ_R)); // TEX_ADDR_DXDY
-	    OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, 0x00000000); // mbz
-	    OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, 0x00000000); // mbz
+						   R500_DY_Q_SWIZ_R));
+	    OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, 0x00000000);
+	    OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, 0x00000000);
 
+	    /* tex inst for mask texture */
 	    OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_TEX |
 						   R500_INST_TEX_SEM_WAIT |
 						   R500_INST_RGB_WMASK_R |
@@ -1833,12 +1728,13 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture,
 						   R500_DY_S_SWIZ_R |
 						   R500_DY_T_SWIZ_R |
 						   R500_DY_R_SWIZ_R |
-						   R500_DY_Q_SWIZ_R)); // TEX_ADDR_DXDY
-	    OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, 0x00000000); // mbz
-	    OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, 0x00000000); // mbz
+						   R500_DY_Q_SWIZ_R));
+	    OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, 0x00000000);
+	    OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, 0x00000000);
 	} else {
 	    BEGIN_ACCEL(13);
 	    OUT_ACCEL_REG(R500_GA_US_VECTOR_INDEX, 0);
+	    /* tex inst for src texture */
 	    OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_TEX |
 						   R500_INST_TEX_SEM_WAIT |
 						   R500_INST_RGB_WMASK_R |
@@ -1870,11 +1766,13 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture,
 						   R500_DY_S_SWIZ_R |
 						   R500_DY_T_SWIZ_R |
 						   R500_DY_R_SWIZ_R |
-						   R500_DY_Q_SWIZ_R)); // TEX_ADDR_DXDY
-	    OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, 0x00000000); // mbz
-	    OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, 0x00000000); // mbz
+						   R500_DY_Q_SWIZ_R));
+	    OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, 0x00000000);
+	    OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, 0x00000000);
 	}
 
+	/* ALU inst */
+	/* *_OMASK* - output component write mask */
 	OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_OUT |
 					       R500_INST_TEX_SEM_WAIT |
 					       R500_INST_LAST |
@@ -1884,21 +1782,31 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture,
 					       R500_INST_ALPHA_OMASK |
 					       R500_INST_RGB_CLAMP |
 					       R500_INST_ALPHA_CLAMP));
-
+	/* ALU inst
+	 * temp addresses for texture inputs
+	 * RGB_ADDR0 is src tex (temp 0)
+	 * RGB_ADDR1 is mask tex (temp 1)
+	 */
 	OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_RGB_ADDR0(0) |
 					       R500_RGB_ADDR1(1) |
 					       R500_RGB_ADDR2(0)));
-
+	/* ALU inst
+	 * temp addresses for texture inputs
+	 * ALPHA_ADDR0 is src tex (temp 0)
+	 * ALPHA_ADDR1 is mask tex (temp 1)
+	 */
 	OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDR0(0) |
 					       R500_ALPHA_ADDR1(1) |
 					       R500_ALPHA_ADDR2(0)));
 
+	/* R500_ALU_RGB_TARGET - RGB render target */
 	OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGB_SEL_A_SRC0 |
 					       src_color |
 					       R500_ALU_RGB_SEL_B_SRC1 |
 					       mask_color |
 					       R500_ALU_RGB_TARGET(0)));
 
+	/* R500_ALPHA_RGB_TARGET - alpha render target */
 	OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_OP_MAD |
 					       R500_ALPHA_ADDRD(0) |
 					       R500_ALPHA_SEL_A_SRC0 |
@@ -1916,25 +1824,25 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture,
 	FINISH_ACCEL();
     }
 
-    BEGIN_ACCEL(4);
+    BEGIN_ACCEL(3);
 
     OUT_ACCEL_REG(R300_RB3D_COLOROFFSET0, dst_offset);
     OUT_ACCEL_REG(R300_RB3D_COLORPITCH0, colorpitch);
 
     blendcntl = RADEONGetBlendCntl(op, pMaskPicture, pDstPicture->format);
     OUT_ACCEL_REG(R300_RB3D_BLENDCNTL, blendcntl | R300_ALPHA_BLEND_ENABLE | R300_READ_ENABLE);
-    OUT_ACCEL_REG(R300_RB3D_ABLENDCNTL, 0);
 
     FINISH_ACCEL();
 
     return TRUE;
 }
 
-#define VTX_COUNT 6
+#define VTX_COUNT_MASK 6
+#define VTX_COUNT 4
 
 #ifdef ACCEL_CP
 
-#define VTX_OUT(_dstX, _dstY, _srcX, _srcY, _maskX, _maskY)	\
+#define VTX_OUT_MASK(_dstX, _dstY, _srcX, _srcY, _maskX, _maskY)	\
 do {								\
     OUT_RING_F(_dstX);						\
     OUT_RING_F(_dstY);						\
@@ -1944,9 +1852,17 @@ do {								\
     OUT_RING_F(_maskY);						\
 } while (0)
 
+#define VTX_OUT(_dstX, _dstY, _srcX, _srcY)	\
+do {								\
+    OUT_RING_F(_dstX);						\
+    OUT_RING_F(_dstY);						\
+    OUT_RING_F(_srcX);						\
+    OUT_RING_F(_srcY);						\
+} while (0)
+
 #else /* ACCEL_CP */
 
-#define VTX_OUT(_dstX, _dstY, _srcX, _srcY, _maskX, _maskY)	\
+#define VTX_OUT_MASK(_dstX, _dstY, _srcX, _srcY, _maskX, _maskY)	\
 do {								\
     OUT_ACCEL_REG_F(RADEON_SE_PORT_DATA0, _dstX);		\
     OUT_ACCEL_REG_F(RADEON_SE_PORT_DATA0, _dstY);		\
@@ -1956,6 +1872,14 @@ do {								\
     OUT_ACCEL_REG_F(RADEON_SE_PORT_DATA0, _maskY);		\
 } while (0)
 
+#define VTX_OUT(_dstX, _dstY, _srcX, _srcY)	\
+do {								\
+    OUT_ACCEL_REG_F(RADEON_SE_PORT_DATA0, _dstX);		\
+    OUT_ACCEL_REG_F(RADEON_SE_PORT_DATA0, _dstY);		\
+    OUT_ACCEL_REG_F(RADEON_SE_PORT_DATA0, _srcX);		\
+    OUT_ACCEL_REG_F(RADEON_SE_PORT_DATA0, _srcY);		\
+} while (0)
+
 #endif /* !ACCEL_CP */
 
 #ifdef ONLY_ONCE
@@ -1971,11 +1895,11 @@ static inline void transformPoint(PictTransform *transform, xPointFixed *point)
 }
 #endif
 
-static void FUNC_NAME(RadeonComposite)(PixmapPtr pDst,
-				     int srcX, int srcY,
-				     int maskX, int maskY,
-				     int dstX, int dstY,
-				     int w, int h)
+static void FUNC_NAME(RadeonCompositeTile)(PixmapPtr pDst,
+					   int srcX, int srcY,
+					   int maskX, int maskY,
+					   int dstX, int dstY,
+					   int w, int h)
 {
     RINFO_FROM_SCREEN(pDst->drawable.pScreen);
     int vtx_count;
@@ -2019,9 +1943,12 @@ static void FUNC_NAME(RadeonComposite)(PixmapPtr pDst,
 	transformPoint(transform[1], &maskBottomRight);
     }
 
-    vtx_count = VTX_COUNT;
+    if (has_mask)
+	vtx_count = VTX_COUNT_MASK;
+    else
+	vtx_count = VTX_COUNT;
 
-    if (IS_R300_VARIANT || IS_AVIVO_VARIANT) {
+    if (IS_R300_3D || IS_R500_3D) {
 	BEGIN_ACCEL(1);
 	OUT_ACCEL_REG(R300_VAP_VTX_SIZE, vtx_count);
 	FINISH_ACCEL();
@@ -2032,17 +1959,21 @@ static void FUNC_NAME(RadeonComposite)(PixmapPtr pDst,
 	BEGIN_RING(4 * vtx_count + 3);
 	OUT_RING(CP_PACKET3(RADEON_CP_PACKET3_3D_DRAW_IMMD,
 			    4 * vtx_count + 1));
-	OUT_RING(RADEON_CP_VC_FRMT_XY |
-		 RADEON_CP_VC_FRMT_ST0 |
-		 RADEON_CP_VC_FRMT_ST1);
+	if (has_mask)
+	    OUT_RING(RADEON_CP_VC_FRMT_XY |
+		     RADEON_CP_VC_FRMT_ST0 |
+		     RADEON_CP_VC_FRMT_ST1);
+	else
+	    OUT_RING(RADEON_CP_VC_FRMT_XY |
+		     RADEON_CP_VC_FRMT_ST0);
 	OUT_RING(RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_FAN |
 		 RADEON_CP_VC_CNTL_PRIM_WALK_RING |
 		 RADEON_CP_VC_CNTL_MAOS_ENABLE |
 		 RADEON_CP_VC_CNTL_VTX_FMT_RADEON_MODE |
 		 (4 << RADEON_CP_VC_CNTL_NUM_SHIFT));
     } else {
-	if (IS_R300_VARIANT || IS_AVIVO_VARIANT)
-	    BEGIN_RING(4 * vtx_count + 6);
+	if (IS_R300_3D | IS_R500_3D)
+	    BEGIN_RING(4 * vtx_count + 4);
 	else
 	    BEGIN_RING(4 * vtx_count + 2);
 
@@ -2054,8 +1985,8 @@ static void FUNC_NAME(RadeonComposite)(PixmapPtr pDst,
     }
 
 #else /* ACCEL_CP */
-    if (IS_R300_VARIANT || IS_AVIVO_VARIANT)
-	BEGIN_ACCEL(3 + vtx_count * 4);
+    if (IS_R300_3D | IS_R500_3D)
+	BEGIN_ACCEL(2 + vtx_count * 4);
     else
 	BEGIN_ACCEL(1 + vtx_count * 4);
 
@@ -2071,24 +2002,34 @@ static void FUNC_NAME(RadeonComposite)(PixmapPtr pDst,
     }
 #endif
 
-    VTX_OUT((float)dstX,                                      (float)dstY,
-	    xFixedToFloat(srcTopLeft.x) / info->texW[0],      xFixedToFloat(srcTopLeft.y) / info->texH[0],
-	    xFixedToFloat(maskTopLeft.x) / info->texW[1],     xFixedToFloat(maskTopLeft.y) / info->texH[1]);
-    VTX_OUT((float)dstX,                                      (float)(dstY + h),
-	    xFixedToFloat(srcBottomLeft.x) / info->texW[0],   xFixedToFloat(srcBottomLeft.y) / info->texH[0],
-	    xFixedToFloat(maskBottomLeft.x) / info->texW[1],  xFixedToFloat(maskBottomLeft.y) / info->texH[1]);
-    VTX_OUT((float)(dstX + w),                                (float)(dstY + h),
-	    xFixedToFloat(srcBottomRight.x) / info->texW[0],  xFixedToFloat(srcBottomRight.y) / info->texH[0],
-	    xFixedToFloat(maskBottomRight.x) / info->texW[1], xFixedToFloat(maskBottomRight.y) / info->texH[1]);
-    VTX_OUT((float)(dstX + w),                                (float)dstY,
-	    xFixedToFloat(srcTopRight.x) / info->texW[0],     xFixedToFloat(srcTopRight.y) / info->texH[0],
-	    xFixedToFloat(maskTopRight.x) / info->texW[1],    xFixedToFloat(maskTopRight.y) / info->texH[1]);
-
-    if (IS_R300_VARIANT || IS_AVIVO_VARIANT) {
-	OUT_ACCEL_REG(R300_RB3D_DSTCACHE_CTLSTAT, R300_DC_FLUSH_3D | R300_DC_FREE_3D);
-	OUT_ACCEL_REG(RADEON_WAIT_UNTIL, RADEON_WAIT_3D_IDLECLEAN);
+    if (has_mask) {
+	VTX_OUT_MASK((float)dstX,                                      (float)dstY,
+		xFixedToFloat(srcTopLeft.x) / info->texW[0],      xFixedToFloat(srcTopLeft.y) / info->texH[0],
+		xFixedToFloat(maskTopLeft.x) / info->texW[1],     xFixedToFloat(maskTopLeft.y) / info->texH[1]);
+	VTX_OUT_MASK((float)dstX,                                      (float)(dstY + h),
+		xFixedToFloat(srcBottomLeft.x) / info->texW[0],   xFixedToFloat(srcBottomLeft.y) / info->texH[0],
+		xFixedToFloat(maskBottomLeft.x) / info->texW[1],  xFixedToFloat(maskBottomLeft.y) / info->texH[1]);
+	VTX_OUT_MASK((float)(dstX + w),                                (float)(dstY + h),
+		xFixedToFloat(srcBottomRight.x) / info->texW[0],  xFixedToFloat(srcBottomRight.y) / info->texH[0],
+		xFixedToFloat(maskBottomRight.x) / info->texW[1], xFixedToFloat(maskBottomRight.y) / info->texH[1]);
+	VTX_OUT_MASK((float)(dstX + w),                                (float)dstY,
+		xFixedToFloat(srcTopRight.x) / info->texW[0],     xFixedToFloat(srcTopRight.y) / info->texH[0],
+		xFixedToFloat(maskTopRight.x) / info->texW[1],    xFixedToFloat(maskTopRight.y) / info->texH[1]);
+    } else {
+	VTX_OUT((float)dstX,                                      (float)dstY,
+		xFixedToFloat(srcTopLeft.x) / info->texW[0],      xFixedToFloat(srcTopLeft.y) / info->texH[0]);
+	VTX_OUT((float)dstX,                                      (float)(dstY + h),
+		xFixedToFloat(srcBottomLeft.x) / info->texW[0],   xFixedToFloat(srcBottomLeft.y) / info->texH[0]);
+	VTX_OUT((float)(dstX + w),                                (float)(dstY + h),
+		xFixedToFloat(srcBottomRight.x) / info->texW[0],  xFixedToFloat(srcBottomRight.y) / info->texH[0]);
+	VTX_OUT((float)(dstX + w),                                (float)dstY,
+		xFixedToFloat(srcTopRight.x) / info->texW[0],     xFixedToFloat(srcTopRight.y) / info->texH[0]);
     }
 
+    if (IS_R300_3D | IS_R500_3D)
+	/* flushing is pipelined, free/finish is not */
+	OUT_ACCEL_REG(R300_RB3D_DSTCACHE_CTLSTAT, R300_DC_FLUSH_3D);
+
 #ifdef ACCEL_CP
     ADVANCE_RING();
 #else
@@ -2098,14 +2039,84 @@ static void FUNC_NAME(RadeonComposite)(PixmapPtr pDst,
     LEAVE_DRAW(0);
 }
 #undef VTX_OUT
+#undef VTX_OUT_MASK
 
-#ifdef ONLY_ONCE
-static void RadeonDoneComposite(PixmapPtr pDst)
+static void FUNC_NAME(RadeonComposite)(PixmapPtr pDst,
+				       int srcX, int srcY,
+				       int maskX, int maskY,
+				       int dstX, int dstY,
+				       int width, int height)
+{
+    int tileSrcY, tileMaskY, tileDstY;
+    int remainingHeight;
+    
+    if (!need_src_tile_x && !need_src_tile_y) {
+	FUNC_NAME(RadeonCompositeTile)(pDst,
+				       srcX, srcY,
+				       maskX, maskY,
+				       dstX, dstY,
+				       width, height);
+	return;
+    }
+
+    /* Tiling logic borrowed from exaFillRegionTiled */
+
+    modulus(srcY, src_tile_height, tileSrcY);
+    tileMaskY = maskY;
+    tileDstY = dstY;
+
+    remainingHeight = height;
+    while (remainingHeight > 0) {
+	int remainingWidth = width;
+	int tileSrcX, tileMaskX, tileDstX;
+	int h = src_tile_height - tileSrcY;
+	
+	if (h > remainingHeight)
+	    h = remainingHeight;
+	remainingHeight -= h;
+
+	modulus(srcX, src_tile_width, tileSrcX);
+	tileMaskX = maskX;
+	tileDstX = dstX;
+	
+	while (remainingWidth > 0) {
+	    int w = src_tile_width - tileSrcX;
+	    if (w > remainingWidth)
+		w = remainingWidth;
+	    remainingWidth -= w;
+	    
+	    FUNC_NAME(RadeonCompositeTile)(pDst,
+					   tileSrcX, tileSrcY,
+					   tileMaskX, tileMaskY,
+					   tileDstX, tileDstY,
+					   w, h);
+	    
+	    tileSrcX = 0;
+	    tileMaskX += w;
+	    tileDstX += w;
+	}
+	tileSrcY = 0;
+	tileMaskY += h;
+	tileDstY += h;
+    }
+}
+
+static void FUNC_NAME(RadeonDoneComposite)(PixmapPtr pDst)
 {
+    RINFO_FROM_SCREEN(pDst->drawable.pScreen);
+    ACCEL_PREAMBLE();
+
     ENTER_DRAW(0);
+
+    if (IS_R500_3D) {
+	/* r500 shows corruption on small things like glyphs without a 3D idle */
+	BEGIN_ACCEL(1);
+	OUT_ACCEL_REG(RADEON_WAIT_UNTIL, RADEON_WAIT_3D_IDLECLEAN);
+	FINISH_ACCEL();
+    }
+
     LEAVE_DRAW(0);
 }
-#endif /* ONLY_ONCE */
 
 #undef ONLY_ONCE
 #undef FUNC_NAME
diff --git a/src/radeon_output.c b/src/radeon_output.c
index 19ce36d..28539d4 100644
--- a/src/radeon_output.c
+++ b/src/radeon_output.c
@@ -297,7 +297,7 @@ RADEONDisplayDDCConnected(ScrnInfoPtr pScrn, xf86OutputPtr output)
 		   INREG(DDCReg) & ~(RADEON_GPIO_EN_0));
 	    usleep(15000);
 
-	    MonInfo = xf86DoEDID_DDC2(pScrn->scrnIndex, radeon_output->pI2CBus);
+	    MonInfo = xf86OutputGetEDID(output, radeon_output->pI2CBus);
 
 	    OUTREG(DDCReg, INREG(DDCReg) | RADEON_GPIO_EN_1);
 	    OUTREG(DDCReg, INREG(DDCReg) | RADEON_GPIO_EN_0);
@@ -320,7 +320,7 @@ RADEONDisplayDDCConnected(ScrnInfoPtr pScrn, xf86OutputPtr output)
 	    if (MonInfo)  break;
 	}
     } else if (radeon_output->pI2CBus && info->ddc2 && ((DDCReg == RADEON_LCD_GPIO_MASK) || (DDCReg == RADEON_MDGPIO_EN_REG))) {
-         MonInfo = xf86DoEDID_DDC2(pScrn->scrnIndex, radeon_output->pI2CBus);
+	MonInfo = xf86OutputGetEDID(output, radeon_output->pI2CBus);
     } else {
 	xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "DDC2/I2C is not properly initialized\n");
 	MonType = MT_NONE;
@@ -669,15 +669,15 @@ radeon_bios_output_lock(xf86OutputPtr output, Bool lock)
 
     if (info->IsAtomBios) {
 	if (lock) {
-	    save->bios_6_scratch |= (ATOM_S6_CRITICAL_STATE | ATOM_S6_ACC_MODE);
+	    save->bios_6_scratch |= ATOM_S6_CRITICAL_STATE;
 	} else {
-	    save->bios_6_scratch &= ~(ATOM_S6_CRITICAL_STATE | ATOM_S6_ACC_MODE);
+	    save->bios_6_scratch &= ~ATOM_S6_CRITICAL_STATE;
 	}
     } else {
 	if (lock) {
-	    save->bios_6_scratch |= (RADEON_DRIVER_CRITICAL | RADEON_ACC_MODE_CHANGE);
+	    save->bios_6_scratch |= RADEON_DRIVER_CRITICAL;
 	} else {
-	    save->bios_6_scratch &= ~(RADEON_DRIVER_CRITICAL | RADEON_ACC_MODE_CHANGE);
+	    save->bios_6_scratch &= ~RADEON_DRIVER_CRITICAL;
 	}
     }
     if (info->ChipFamily >= CHIP_FAMILY_R600)
diff --git a/src/radeon_probe.h b/src/radeon_probe.h
index 7dfce68..0096ce0 100644
--- a/src/radeon_probe.h
+++ b/src/radeon_probe.h
@@ -505,10 +505,16 @@ typedef struct {
     CARD32            palette[256];
     CARD32            palette2[256];
 
-    CARD32            rs480_unk_e30;
-    CARD32            rs480_unk_e34;
-    CARD32            rs480_unk_e38;
-    CARD32            rs480_unk_e3c;
+    CARD32            disp2_req_cntl1;
+    CARD32            disp2_req_cntl2;
+    CARD32            dmif_mem_cntl1;
+    CARD32            disp1_req_cntl1;
+
+    CARD32            fp_2nd_gen_cntl;
+    CARD32            fp2_2_gen_cntl;
+    CARD32            tmds2_cntl;
+    CARD32            tmds2_transmitter_cntl;
+
 
     /* TV out registers */
     CARD32 	      tv_master_cntl;
diff --git a/src/radeon_reg.h b/src/radeon_reg.h
index 6245403..5112872 100644
--- a/src/radeon_reg.h
+++ b/src/radeon_reg.h
@@ -887,6 +887,33 @@
 #       define RADEON_VERT_STRETCH_BLEND       (1     << 26)
 #       define RADEON_VERT_AUTO_RATIO_EN       (1     << 27)
 #       define RADEON_VERT_STRETCH_RESERVED    0xf1000000
+#define RS400_FP_2ND_GEN_CNTL               0x0384
+#       define RS400_FP_2ND_ON              (1 << 0)
+#       define RS400_FP_2ND_BLANK_EN        (1 << 1)
+#       define RS400_TMDS_2ND_EN            (1 << 2)
+#       define RS400_PANEL_FORMAT_2ND       (1 << 3)
+#       define RS400_FP_2ND_EN_TMDS         (1 << 7)
+#       define RS400_FP_2ND_DETECT_SENSE    (1 << 8)
+#       define RS400_FP_2ND_SOURCE_SEL_MASK        (3 << 10)
+#       define RS400_FP_2ND_SOURCE_SEL_CRTC1       (0 << 10)
+#       define RS400_FP_2ND_SOURCE_SEL_CRTC2       (1 << 10)
+#       define RS400_FP_2ND_SOURCE_SEL_RMX         (2 << 10)
+#       define RS400_FP_2ND_DETECT_EN       (1 << 12)
+#       define RS400_HPD_2ND_SEL            (1 << 13)
+#define RS400_FP2_2_GEN_CNTL                0x0388
+#       define RS400_FP2_2_BLANK_EN         (1 << 1)
+#       define RS400_FP2_2_ON               (1 << 2)
+#       define RS400_FP2_2_PANEL_FORMAT     (1 << 3)
+#       define RS400_FP2_2_DETECT_SENSE     (1 << 8)
+#       define RS400_FP2_2_SOURCE_SEL_MASK        (3 << 10)
+#       define RS400_FP2_2_SOURCE_SEL_CRTC1       (0 << 10)
+#       define RS400_FP2_2_SOURCE_SEL_CRTC2       (1 << 10)
+#       define RS400_FP2_2_SOURCE_SEL_RMX         (2 << 10)
+#       define RS400_FP2_2_DVO2_EN          (1 << 25)
+#define RS400_TMDS2_CNTL                    0x0394
+#define RS400_TMDS2_TRANSMITTER_CNTL        0x03a4
+#       define RS400_TMDS2_PLLEN            (1 << 0)
+#       define RS400_TMDS2_PLLRST           (1 << 1)
 
 #define RADEON_GEN_INT_CNTL                 0x0040
 #define RADEON_GEN_INT_STATUS               0x0044
@@ -3328,10 +3355,32 @@
 #       define RADEON_TVPLL_TEST_DIS             (1 << 31)
 #       define RADEON_TVCLK_SRC_SEL_TVPLL        (1 << 30)
 
-#define RADEON_RS480_UNK_e30			0xe30
-#define RADEON_RS480_UNK_e34			0xe34
-#define RADEON_RS480_UNK_e38			0xe38
-#define RADEON_RS480_UNK_e3c			0xe3c
+#define RS400_DISP2_REQ_CNTL1			0xe30
+#       define RS400_DISP2_START_REQ_LEVEL_SHIFT   0
+#       define RS400_DISP2_START_REQ_LEVEL_MASK    0x3ff
+#       define RS400_DISP2_STOP_REQ_LEVEL_SHIFT    12
+#       define RS400_DISP2_STOP_REQ_LEVEL_MASK     0x3ff
+#       define RS400_DISP2_ALLOW_FID_LEVEL_SHIFT   22
+#       define RS400_DISP2_ALLOW_FID_LEVEL_MASK    0x3ff
+#define RS400_DISP2_REQ_CNTL2			0xe34
+#       define RS400_DISP2_CRITICAL_POINT_START_SHIFT    12
+#       define RS400_DISP2_CRITICAL_POINT_START_MASK     0x3ff
+#       define RS400_DISP2_CRITICAL_POINT_STOP_SHIFT     22
+#       define RS400_DISP2_CRITICAL_POINT_STOP_MASK      0x3ff
+#define RS400_DMIF_MEM_CNTL1			0xe38
+#       define RS400_DISP2_START_ADR_SHIFT      0
+#       define RS400_DISP2_START_ADR_MASK       0x3ff
+#       define RS400_DISP1_CRITICAL_POINT_START_SHIFT    12
+#       define RS400_DISP1_CRITICAL_POINT_START_MASK     0x3ff
+#       define RS400_DISP1_CRITICAL_POINT_STOP_SHIFT     22
+#       define RS400_DISP1_CRITICAL_POINT_STOP_MASK      0x3ff
+#define RS400_DISP1_REQ_CNTL1			0xe3c
+#       define RS400_DISP1_START_REQ_LEVEL_SHIFT   0
+#       define RS400_DISP1_START_REQ_LEVEL_MASK    0x3ff
+#       define RS400_DISP1_STOP_REQ_LEVEL_SHIFT    12
+#       define RS400_DISP1_STOP_REQ_LEVEL_MASK     0x3ff
+#       define RS400_DISP1_ALLOW_FID_LEVEL_SHIFT   22
+#       define RS400_DISP1_ALLOW_FID_LEVEL_MASK    0x3ff
 
 #define RS690_MC_INDEX				0x78
 #	define RS690_MC_INDEX_MASK		0x1ff
@@ -3836,6 +3885,7 @@
 #define R300_GB_SELECT				        0x401c
 #define R300_GB_ENABLE				        0x4008
 #define R300_GB_AA_CONFIG				0x4020
+#define R400_GB_PIPE_SELECT                             0x402c
 #define R300_GB_MSPOS0				        0x4010
 #       define R300_MS_X0_SHIFT                         0
 #       define R300_MS_Y0_SHIFT                         4
@@ -3854,6 +3904,10 @@
 #       define R300_MS_Y5_SHIFT                         20
 #       define R300_MSBD1_SHIFT                         24
 
+#define R300_GA_ENHANCE				        0x4274
+#       define R300_GA_DEADLOCK_CNTL                    (1 << 0)
+#       define R300_GA_FASTSYNC_CNTL                    (1 << 1)
+
 #define R300_GA_POLY_MODE				0x4288
 #       define R300_FRONT_PTYPE_POINT                   (0 << 4)
 #       define R300_FRONT_PTYPE_LINE                    (1 << 4)
@@ -3893,6 +3947,8 @@
 #       define R300_ALPHA3_SHADING_GOURAUD              (2 << 14)
 #define R300_GA_OFFSET				        0x4290
 
+#define R500_SU_REG_DEST                                0x42c8
+
 #define R300_VAP_CNTL_STATUS				0x2140
 #       define R300_PVS_BYPASS                          (1 << 8)
 #define R300_VAP_PVS_STATE_FLUSH_REG		        0x2284
@@ -3903,6 +3959,7 @@
 #       define R300_VF_MAX_VTX_NUM_SHIFT                18
 #       define R300_GL_CLIP_SPACE_DEF                   (0 << 22)
 #       define R300_DX_CLIP_SPACE_DEF                   (1 << 22)
+#       define R500_TCL_STATE_OPTIMIZATION              (1 << 23)
 #define R300_VAP_VTE_CNTL				0x20B0
 #       define R300_VPORT_X_SCALE_ENA                   (1 << 0)
 #       define R300_VPORT_X_OFFSET_ENA                  (1 << 1)
@@ -3913,6 +3970,7 @@
 #       define R300_VTX_XY_FMT                          (1 << 8)
 #       define R300_VTX_Z_FMT                           (1 << 9)
 #       define R300_VTX_W0_FMT                          (1 << 10)
+#define R300_VAP_VTX_STATE_CNTL		                0x2180
 #define R300_VAP_PSC_SGN_NORM_CNTL		        0x21DC
 #define R300_VAP_PROG_STREAM_CNTL_0		        0x2150
 #       define R300_DATA_TYPE_0_SHIFT                   0
@@ -4142,6 +4200,8 @@
 #       define R300_BOUNDARY_EDGE_FLAG_ENA              (1 << 18)
 #define R300_VAP_PVS_STATE_FLUSH_REG			0x2284
 
+#define R500_VAP_INDEX_OFFSET			        0x208c
+
 #define R300_SU_TEX_WRAP				0x42a0
 #define R300_SU_POLY_OFFSET_ENABLE		        0x42b4
 #define R300_SU_CULL_MODE				0x42b8
@@ -4300,6 +4360,8 @@
 #       define R300_ENDIAN_SWAP_HALF_DWORD              (3 << 0)
 #       define R300_MACRO_TILE                          (1 << 2)
 
+#define R300_TX_BORDER_COLOR_0			        0x45c0
+
 #define R300_TX_ENABLE				        0x4104
 #       define R300_TEX_0_ENABLE                        (1 << 0)
 #       define R300_TEX_1_ENABLE                        (1 << 1)
@@ -4553,12 +4615,25 @@
 #define R300_FG_FOG_BLEND				0x4bc0
 #define R300_FG_ALPHA_FUNC				0x4bd4
 
+#define R300_DST_PIPE_CONFIG		                0x170c
+#       define R300_PIPE_AUTO_CONFIG                    (1 << 31)
+#define R300_RB2D_DSTCACHE_MODE		                0x3428
+#       define R300_DC_AUTOFLUSH_ENABLE                 (1 << 8)
+#       define R300_DC_DC_DISABLE_IGNORE_PE             (1 << 17)
+#define R300_RB2D_DSTCACHE_CTLSTAT		        0x342c
+#       define R300_DC_FLUSH_2D                         (1 << 0)
+#       define R300_DC_FREE_2D                          (1 << 2)
+#       define R300_RB2D_DC_FLUSH_ALL                   (R300_DC_FLUSH_2D | R300_DC_FREE_2D)
+#       define R300_RB2D_DC_BUSY                        (1 << 31)
 #define R300_RB3D_DSTCACHE_CTLSTAT		        0x4e4c
 #       define R300_DC_FLUSH_3D                         (2 << 0)
 #       define R300_DC_FREE_3D                          (2 << 2)
+#       define R300_RB3D_DC_FLUSH_ALL                   (R300_DC_FLUSH_3D | R300_DC_FREE_3D)
+#       define R300_DC_FINISH_3D                        (1 << 4)
 #define R300_RB3D_ZCACHE_CTLSTAT			0x4f18
 #       define R300_ZC_FLUSH                            (1 << 0)
 #       define R300_ZC_FREE                             (1 << 1)
+#       define R300_ZC_FLUSH_ALL                        0x3
 #define R300_WAIT_UNTIL				        0x1720
 #       define R300_WAIT_2D_IDLECLEAN                   (1 << 16)
 #       define R300_WAIT_3D_IDLECLEAN                   (1 << 17)
@@ -5126,5 +5201,6 @@
 #   define R500_RS_IP_COL_FMT_RGBA			(0 << 27)
 #   define R500_RS_IP_OFFSET_EN 			(1 << 31)
 
+#define R500_DYN_SCLK_PWMEM_PIPE                        0x000d /* PLL */
 
 #endif
diff --git a/src/radeon_textured_videofuncs.c b/src/radeon_textured_videofuncs.c
index d4a3343..f7069f0 100644
--- a/src/radeon_textured_videofuncs.c
+++ b/src/radeon_textured_videofuncs.c
@@ -106,31 +106,22 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
     dstyoff = 0;
 #endif
 
-#if 0
-    ErrorF("dst_offset: 0x%x\n", dst_offset);
-    ErrorF("dst_pitch: 0x%x\n", dst_pitch);
-    ErrorF("dstxoff: 0x%x\n", dstxoff);
-    ErrorF("dstyoff: 0x%x\n", dstyoff);
-    ErrorF("src_offset: 0x%x\n", pPriv->src_offset);
-    ErrorF("src_pitch: 0x%x\n", pPriv->src_pitch);
-#endif
-
     if (!info->XInited3D)
 	RADEONInit3DEngine(pScrn);
 
     /* we can probably improve this */
     BEGIN_VIDEO(2);
-    OUT_VIDEO_REG(RADEON_RB3D_DSTCACHE_CTLSTAT, RADEON_RB3D_DC_FLUSH);
+    if (IS_R300_3D || IS_R500_3D)
+	OUT_VIDEO_REG(R300_RB3D_DSTCACHE_CTLSTAT, R300_DC_FLUSH_3D);
+    else
+	OUT_VIDEO_REG(RADEON_RB3D_DSTCACHE_CTLSTAT, RADEON_RB3D_DC_FLUSH);
     /* We must wait for 3d to idle, in case source was just written as a dest. */
     OUT_VIDEO_REG(RADEON_WAIT_UNTIL,
 		RADEON_WAIT_HOST_IDLECLEAN | RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN);
     FINISH_VIDEO();
 
-    if (IS_R300_VARIANT || IS_AVIVO_VARIANT) {
-	int has_tcl = ((info->ChipFamily != CHIP_FAMILY_RS690) &&
-		       (info->ChipFamily != CHIP_FAMILY_RS740) &&
-		       (info->ChipFamily != CHIP_FAMILY_RS400) &&
-		       (info->ChipFamily != CHIP_FAMILY_RV515));
+    if (IS_R300_3D || IS_R500_3D) {
+	CARD32 output_fmt;
 
 	switch (pPixmap->drawable.bitsPerPixel) {
 	case 16:
@@ -146,6 +137,12 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
 	    return;
 	}
 
+	output_fmt = (R300_OUT_FMT_C4_8 |
+		      R300_OUT_FMT_C0_SEL_BLUE |
+		      R300_OUT_FMT_C1_SEL_GREEN |
+		      R300_OUT_FMT_C2_SEL_RED |
+		      R300_OUT_FMT_C3_SEL_ALPHA);
+
 	colorpitch = dst_pitch >> pixel_shift;
 	colorpitch |= dst_format;
 
@@ -195,212 +192,89 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
 	txenable = R300_TEX_0_ENABLE;
 
 	/* setup the VAP */
-	if (has_tcl) {
-	    BEGIN_VIDEO(26);
-	    OUT_VIDEO_REG(R300_VAP_CNTL_STATUS, 0);
-	    OUT_VIDEO_REG(R300_VAP_PVS_STATE_FLUSH_REG, 0);
-	    OUT_VIDEO_REG(R300_VAP_CNTL, ((6 << R300_PVS_NUM_SLOTS_SHIFT) |
-					  (5 << R300_PVS_NUM_CNTLRS_SHIFT) |
-					  (4 << R300_PVS_NUM_FPUS_SHIFT) |
-					  (12 << R300_VF_MAX_VTX_NUM_SHIFT)));
-	} else {
-	    BEGIN_VIDEO(8);
-	    OUT_VIDEO_REG(R300_VAP_CNTL_STATUS, R300_PVS_BYPASS);
-	    OUT_VIDEO_REG(R300_VAP_CNTL, ((10 << R300_PVS_NUM_SLOTS_SHIFT) |
-					  (5 << R300_PVS_NUM_CNTLRS_SHIFT) |
-					  (4 << R300_PVS_NUM_FPUS_SHIFT) |
-					  (5 << R300_VF_MAX_VTX_NUM_SHIFT)));
-	}
-
-	OUT_VIDEO_REG(R300_VAP_VTE_CNTL, R300_VTX_XY_FMT | R300_VTX_Z_FMT);
-	OUT_VIDEO_REG(R300_VAP_PSC_SGN_NORM_CNTL, 0);
-
-	if (has_tcl) {
-	    OUT_VIDEO_REG(R300_VAP_PROG_STREAM_CNTL_0,
-			  ((R300_DATA_TYPE_FLOAT_2 << R300_DATA_TYPE_0_SHIFT) |
-			   (0 << R300_SKIP_DWORDS_0_SHIFT) |
-			   (0 << R300_DST_VEC_LOC_0_SHIFT) |
-			   R300_SIGNED_0 |
-			   (R300_DATA_TYPE_FLOAT_2 << R300_DATA_TYPE_1_SHIFT) |
-			   (0 << R300_SKIP_DWORDS_1_SHIFT) |
-			   (10 << R300_DST_VEC_LOC_1_SHIFT) |
-			   R300_LAST_VEC_1 |
-			   R300_SIGNED_1));
-	    OUT_VIDEO_REG(R300_VAP_PROG_STREAM_CNTL_EXT_0,
-			  ((R300_SWIZZLE_SELECT_X << R300_SWIZZLE_SELECT_X_0_SHIFT) |
-			   (R300_SWIZZLE_SELECT_Y << R300_SWIZZLE_SELECT_Y_0_SHIFT) |
-			   (R300_SWIZZLE_SELECT_Z << R300_SWIZZLE_SELECT_Z_0_SHIFT) |
-			   (R300_SWIZZLE_SELECT_W << R300_SWIZZLE_SELECT_W_0_SHIFT) |
-			   ((R300_WRITE_ENA_X | R300_WRITE_ENA_Y | R300_WRITE_ENA_Z | R300_WRITE_ENA_W)
-			    << R300_WRITE_ENA_0_SHIFT) |
-			   (R300_SWIZZLE_SELECT_X << R300_SWIZZLE_SELECT_X_1_SHIFT) |
-			   (R300_SWIZZLE_SELECT_Y << R300_SWIZZLE_SELECT_Y_1_SHIFT) |
-			   (R300_SWIZZLE_SELECT_Z << R300_SWIZZLE_SELECT_Z_1_SHIFT) |
-			   (R300_SWIZZLE_SELECT_W << R300_SWIZZLE_SELECT_W_1_SHIFT) |
-			   ((R300_WRITE_ENA_X | R300_WRITE_ENA_Y | R300_WRITE_ENA_Z | R300_WRITE_ENA_W)
-			    << R300_WRITE_ENA_1_SHIFT)));
-	} else {
-	    OUT_VIDEO_REG(R300_VAP_PROG_STREAM_CNTL_0,
-			  ((R300_DATA_TYPE_FLOAT_2 << R300_DATA_TYPE_0_SHIFT) |
-			   (0 << R300_SKIP_DWORDS_0_SHIFT) |
-			   (0 << R300_DST_VEC_LOC_0_SHIFT) |
-			   R300_SIGNED_0 |
-			   (R300_DATA_TYPE_FLOAT_2 << R300_DATA_TYPE_1_SHIFT) |
-			   (0 << R300_SKIP_DWORDS_1_SHIFT) |
-			   (6 << R300_DST_VEC_LOC_1_SHIFT) |
-			   R300_LAST_VEC_1 |
-			   R300_SIGNED_1));
-	    OUT_VIDEO_REG(R300_VAP_PROG_STREAM_CNTL_EXT_0,
-			  ((R300_SWIZZLE_SELECT_X << R300_SWIZZLE_SELECT_X_0_SHIFT) |
-			   (R300_SWIZZLE_SELECT_Y << R300_SWIZZLE_SELECT_Y_0_SHIFT) |
-			   (R300_SWIZZLE_SELECT_FP_ZERO << R300_SWIZZLE_SELECT_Z_0_SHIFT) |
-			   (R300_SWIZZLE_SELECT_FP_ONE << R300_SWIZZLE_SELECT_W_0_SHIFT) |
-			   ((R300_WRITE_ENA_X | R300_WRITE_ENA_Y)
-			    << R300_WRITE_ENA_0_SHIFT) |
-			   (R300_SWIZZLE_SELECT_X << R300_SWIZZLE_SELECT_X_1_SHIFT) |
-			   (R300_SWIZZLE_SELECT_Y << R300_SWIZZLE_SELECT_Y_1_SHIFT) |
-			   (R300_SWIZZLE_SELECT_FP_ZERO << R300_SWIZZLE_SELECT_Z_1_SHIFT) |
-			   (R300_SWIZZLE_SELECT_FP_ONE << R300_SWIZZLE_SELECT_W_1_SHIFT) |
-			   ((R300_WRITE_ENA_X | R300_WRITE_ENA_Y)
-			    << R300_WRITE_ENA_1_SHIFT)));
-	}
-
-	/* setup vertex shader */
-	if (has_tcl) {
+	if (info->has_tcl)
+	    BEGIN_VIDEO(6);
+	else
+	    BEGIN_VIDEO(4);
+
+	/* These registers define the number, type, and location of data submitted
+	 * to the PVS unit of GA input (when PVS is disabled)
+	 * DST_VEC_LOC is the slot in the PVS input vector memory when PVS/TCL is
+	 * enabled.  This memory provides the imputs to the vertex shader program
+	 * and ordering is not important.  When PVS/TCL is disabled, this field maps
+	 * directly to the GA input memory and the order is signifigant.  In
+	 * PVS_BYPASS mode the order is as follows:
+	 * Position
+	 * Point Size
+	 * Color 0-3
+	 * Textures 0-7
+	 * Fog
+	 */
+	OUT_VIDEO_REG(R300_VAP_PROG_STREAM_CNTL_0,
+		      ((R300_DATA_TYPE_FLOAT_2 << R300_DATA_TYPE_0_SHIFT) |
+		       (0 << R300_SKIP_DWORDS_0_SHIFT) |
+		       (0 << R300_DST_VEC_LOC_0_SHIFT) |
+		       R300_SIGNED_0 |
+		       (R300_DATA_TYPE_FLOAT_2 << R300_DATA_TYPE_1_SHIFT) |
+		       (0 << R300_SKIP_DWORDS_1_SHIFT) |
+		       (6 << R300_DST_VEC_LOC_1_SHIFT) |
+		       R300_LAST_VEC_1 |
+		       R300_SIGNED_1));
+
+	/* load the vertex shader
+	 * We pre-load vertex programs in RADEONInit3DEngine():
+	 * - exa no mask
+	 * - exa mask
+	 * - Xv
+	 * Here we select the offset of the vertex program we want to use
+	 */
+	if (info->has_tcl) {
 	    OUT_VIDEO_REG(R300_VAP_PVS_CODE_CNTL_0,
-			  ((0 << R300_PVS_FIRST_INST_SHIFT) |
-			   (1 << R300_PVS_XYZW_VALID_INST_SHIFT) |
-			   (1 << R300_PVS_LAST_INST_SHIFT)));
+			  ((5 << R300_PVS_FIRST_INST_SHIFT) |
+			   (6 << R300_PVS_XYZW_VALID_INST_SHIFT) |
+			   (6 << R300_PVS_LAST_INST_SHIFT)));
 	    OUT_VIDEO_REG(R300_VAP_PVS_CODE_CNTL_1,
-			  (1 << R300_PVS_LAST_VTX_SRC_INST_SHIFT));
-	    OUT_VIDEO_REG(R300_VAP_PVS_VECTOR_INDX_REG, 0);
-
-	    OUT_VIDEO_REG(R300_VAP_PVS_VECTOR_DATA_REG,
-			  (R300_PVS_DST_OPCODE(R300_VE_ADD) |
-			   R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_OUT) |
-			   R300_PVS_DST_OFFSET(0) |
-			   R300_PVS_DST_WE_X | R300_PVS_DST_WE_Y |
-			   R300_PVS_DST_WE_Z | R300_PVS_DST_WE_W));
-	    OUT_VIDEO_REG(R300_VAP_PVS_VECTOR_DATA_REG,
-			  (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
-			   R300_PVS_SRC_OFFSET(0) |
-			   R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) |
-			   R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) |
-			   R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_Z) |
-			   R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_W)));
-	    OUT_VIDEO_REG(R300_VAP_PVS_VECTOR_DATA_REG,
-			  (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
-			   R300_PVS_SRC_OFFSET(0) |
-			   R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) |
-			   R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) |
-			   R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
-			   R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
-	    OUT_VIDEO_REG(R300_VAP_PVS_VECTOR_DATA_REG,
-			  (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
-			   R300_PVS_SRC_OFFSET(0) |
-			   R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) |
-			   R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) |
-			   R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
-			   R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
-
-	    OUT_VIDEO_REG(R300_VAP_PVS_VECTOR_DATA_REG,
-			  (R300_PVS_DST_OPCODE(R300_VE_ADD) |
-			   R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_OUT) |
-			   R300_PVS_DST_OFFSET(1) |
-			   R300_PVS_DST_WE_X | R300_PVS_DST_WE_Y |
-			   R300_PVS_DST_WE_Z | R300_PVS_DST_WE_W));
-	    OUT_VIDEO_REG(R300_VAP_PVS_VECTOR_DATA_REG,
-			  (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
-			   R300_PVS_SRC_OFFSET(10) |
-			   R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) |
-			   R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) |
-			   R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_Z) |
-			   R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_W)));
-	    OUT_VIDEO_REG(R300_VAP_PVS_VECTOR_DATA_REG,
-			  (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
-			   R300_PVS_SRC_OFFSET(10) |
-			   R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) |
-			   R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) |
-			   R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
-			   R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
-	    OUT_VIDEO_REG(R300_VAP_PVS_VECTOR_DATA_REG,
-			  (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
-			   R300_PVS_SRC_OFFSET(10) |
-			   R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) |
-			   R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) |
-			   R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
-			   R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
-
-	    OUT_VIDEO_REG(R300_VAP_PVS_FLOW_CNTL_OPC, 0);
-
-	    OUT_VIDEO_REG(R300_VAP_GB_VERT_CLIP_ADJ, 0x3f800000);
-	    OUT_VIDEO_REG(R300_VAP_GB_VERT_DISC_ADJ, 0x3f800000);
-	    OUT_VIDEO_REG(R300_VAP_GB_HORZ_CLIP_ADJ, 0x3f800000);
-	    OUT_VIDEO_REG(R300_VAP_GB_HORZ_DISC_ADJ, 0x3f800000);
-	    OUT_VIDEO_REG(R300_VAP_CLIP_CNTL, R300_CLIP_DISABLE);
+			  (6 << R300_PVS_LAST_VTX_SRC_INST_SHIFT));
 	}
 
+	/* Position and one set of 2 texture coordinates */
 	OUT_VIDEO_REG(R300_VAP_OUT_VTX_FMT_0, R300_VTX_POS_PRESENT);
 	OUT_VIDEO_REG(R300_VAP_OUT_VTX_FMT_1, (2 << R300_TEX_0_COMP_CNT_SHIFT));
+	OUT_VIDEO_REG(R300_US_OUT_FMT_0, output_fmt);
 	FINISH_VIDEO();
 
 	/* setup pixel shader */
 	if (IS_R300_3D) {
-	    BEGIN_VIDEO(16);
+	    BEGIN_VIDEO(8);
+	    /* 2 components: 2 for tex0 */
 	    OUT_VIDEO_REG(R300_RS_COUNT,
 			  ((2 << R300_RS_COUNT_IT_COUNT_SHIFT) |
 			   R300_RS_COUNT_HIRES_EN));
-	    OUT_VIDEO_REG(R300_RS_IP_0,
-			  (R300_RS_TEX_PTR(0) |
-			   R300_RS_COL_PTR(0) |
-			   R300_RS_COL_FMT(R300_RS_COL_FMT_RGBA) |
-			   R300_RS_SEL_S(R300_RS_SEL_C0) |
-			   R300_RS_SEL_T(R300_RS_SEL_C1) |
-			   R300_RS_SEL_R(R300_RS_SEL_K0) |
-			   R300_RS_SEL_Q(R300_RS_SEL_K1)));
-	    OUT_VIDEO_REG(R300_RS_INST_COUNT, R300_TX_OFFSET_RS(6));
-	    OUT_VIDEO_REG(R300_RS_INST_0, R300_RS_INST_TEX_CN_WRITE);
-	    OUT_VIDEO_REG(R300_US_CONFIG, (0 << R300_NLEVEL_SHIFT) | R300_FIRST_TEX);
-	    OUT_VIDEO_REG(R300_US_PIXSIZE, 0);
+	    /* R300_INST_COUNT_RS - highest RS instruction used */
+	    OUT_VIDEO_REG(R300_RS_INST_COUNT, R300_INST_COUNT_RS(0) | R300_TX_OFFSET_RS(6));
+
 	    OUT_VIDEO_REG(R300_US_CODE_OFFSET,
 			  (R300_ALU_CODE_OFFSET(0) |
 			   R300_ALU_CODE_SIZE(1) |
 			   R300_TEX_CODE_OFFSET(0) |
 			   R300_TEX_CODE_SIZE(1)));
-	    OUT_VIDEO_REG(R300_US_CODE_ADDR_0,
-			  (R300_ALU_START(0) |
-			   R300_ALU_SIZE(0) |
-			   R300_TEX_START(0) |
-			   R300_TEX_SIZE(0)));
-	    OUT_VIDEO_REG(R300_US_CODE_ADDR_1,
-			  (R300_ALU_START(0) |
-			   R300_ALU_SIZE(0) |
-			   R300_TEX_START(0) |
-			   R300_TEX_SIZE(0)));
-	    OUT_VIDEO_REG(R300_US_CODE_ADDR_2,
-			  (R300_ALU_START(0) |
-			   R300_ALU_SIZE(0) |
-			   R300_TEX_START(0) |
-			   R300_TEX_SIZE(0)));
+
 	    OUT_VIDEO_REG(R300_US_CODE_ADDR_3,
 			  (R300_ALU_START(0) |
 			   R300_ALU_SIZE(0) |
 			   R300_TEX_START(0) |
 			   R300_TEX_SIZE(0) |
 			   R300_RGBA_OUT));
-	    OUT_VIDEO_REG(R300_US_TEX_INST_0,
-			  (R300_TEX_SRC_ADDR(0) |
-			   R300_TEX_DST_ADDR(0) |
-			   R300_TEX_ID(0) |
-			   R300_TEX_INST(R300_TEX_INST_LD)));
+
+	    /* tex inst is preloaded in RADEONInit3DEngine() */
+
+	    /* ALU inst */
+	    /* RGB */
 	    OUT_VIDEO_REG(R300_US_ALU_RGB_ADDR_0,
 			  (R300_ALU_RGB_ADDR0(0) |
 			   R300_ALU_RGB_ADDR1(0) |
 			   R300_ALU_RGB_ADDR2(0) |
 			   R300_ALU_RGB_ADDRD(0) |
-			   R300_ALU_RGB_WMASK((R300_ALU_RGB_MASK_R |
-					       R300_ALU_RGB_MASK_G |
-					       R300_ALU_RGB_MASK_B)) |
 			   R300_ALU_RGB_OMASK((R300_ALU_RGB_MASK_R |
 					       R300_ALU_RGB_MASK_G |
 					       R300_ALU_RGB_MASK_B)) |
@@ -415,12 +289,12 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
 			   R300_ALU_RGB_OP(R300_ALU_RGB_OP_MAD) |
 			   R300_ALU_RGB_OMOD(R300_ALU_RGB_OMOD_NONE) |
 			   R300_ALU_RGB_CLAMP));
+	    /* Alpha */
 	    OUT_VIDEO_REG(R300_US_ALU_ALPHA_ADDR_0,
 			  (R300_ALU_ALPHA_ADDR0(0) |
 			   R300_ALU_ALPHA_ADDR1(0) |
 			   R300_ALU_ALPHA_ADDR2(0) |
 			   R300_ALU_ALPHA_ADDRD(0) |
-			   R300_ALU_ALPHA_WMASK(R300_ALU_ALPHA_MASK_A) |
 			   R300_ALU_ALPHA_OMASK(R300_ALU_ALPHA_MASK_A) |
 			   R300_ALU_ALPHA_TARGET_A |
 			   R300_ALU_ALPHA_OMASK_W(R300_ALU_ALPHA_MASK_NONE)));
@@ -436,27 +310,23 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
 			   R300_ALU_ALPHA_CLAMP));
 	    FINISH_VIDEO();
 	} else {
-	    BEGIN_VIDEO(23);
+	    BEGIN_VIDEO(18);
+	    /* 2 components: 2 for tex0 */
 	    OUT_VIDEO_REG(R300_RS_COUNT,
 			  ((2 << R300_RS_COUNT_IT_COUNT_SHIFT) |
 			   R300_RS_COUNT_HIRES_EN));
-	    OUT_VIDEO_REG(R500_RS_IP_0, ((0 << R500_RS_IP_TEX_PTR_S_SHIFT) |
-					 (1 << R500_RS_IP_TEX_PTR_T_SHIFT) |
-					 (R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_R_SHIFT) |
-					 (R500_RS_IP_PTR_K1 << R500_RS_IP_TEX_PTR_Q_SHIFT)));
-
-	    OUT_VIDEO_REG(R300_RS_INST_COUNT, 0);
-	    OUT_VIDEO_REG(R500_RS_INST_0, R500_RS_INST_TEX_CN_WRITE);
-	    OUT_VIDEO_REG(R300_US_CONFIG, R500_ZERO_TIMES_ANYTHING_EQUALS_ZERO);
-	    OUT_VIDEO_REG(R300_US_PIXSIZE, 0);
-	    OUT_VIDEO_REG(R500_US_FC_CTRL, 0);
+
+	    /* R300_INST_COUNT_RS - highest RS instruction used */
+	    OUT_VIDEO_REG(R300_RS_INST_COUNT, R300_INST_COUNT_RS(0) | R300_TX_OFFSET_RS(6));
+
 	    OUT_VIDEO_REG(R500_US_CODE_ADDR, (R500_US_CODE_START_ADDR(0) |
 					      R500_US_CODE_END_ADDR(1)));
 	    OUT_VIDEO_REG(R500_US_CODE_RANGE, (R500_US_CODE_RANGE_ADDR(0) |
 					       R500_US_CODE_RANGE_SIZE(1)));
 	    OUT_VIDEO_REG(R500_US_CODE_OFFSET, 0);
 	    OUT_VIDEO_REG(R500_GA_US_VECTOR_INDEX, 0);
-	    // 7807
+
+	    /* tex inst */
 	    OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_TEX |
 						   R500_INST_TEX_SEM_WAIT |
 						   R500_INST_RGB_WMASK_R |
@@ -488,11 +358,11 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
 						   R500_DY_S_SWIZ_R |
 						   R500_DY_T_SWIZ_R |
 						   R500_DY_R_SWIZ_R |
-						   R500_DY_Q_SWIZ_R)); // TEX_ADDR_DXDY
-	    OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x00000000); // mbz
-	    OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x00000000); // mbz
+						   R500_DY_Q_SWIZ_R));
+	    OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x00000000);
+	    OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, 0x00000000);
 
-	    // 0x78105
+	    /* ALU inst */
 	    OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_OUT |
 						   R500_INST_TEX_SEM_WAIT |
 						   R500_INST_LAST |
@@ -507,14 +377,12 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
 						   R500_RGB_ADDR1(0) |
 						   R500_RGB_ADDR1_CONST |
 						   R500_RGB_ADDR2(0) |
-						   R500_RGB_ADDR2_CONST |
-						   R500_RGB_SRCP_OP_1_MINUS_2RGB0)); //0x10040000
+						   R500_RGB_ADDR2_CONST));
 	    OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDR0(0) |
 						   R500_ALPHA_ADDR1(0) |
 						   R500_ALPHA_ADDR1_CONST |
 						   R500_ALPHA_ADDR2(0) |
-						   R500_ALPHA_ADDR2_CONST |
-						   R500_ALPHA_SRCP_OP_1_MINUS_2A0)); //0x10040000
+						   R500_ALPHA_ADDR2_CONST));
 
 	    OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGB_SEL_A_SRC0 |
 						   R500_ALU_RGB_R_SWIZ_A_R |
@@ -523,21 +391,21 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
 						   R500_ALU_RGB_SEL_B_SRC0 |
 						   R500_ALU_RGB_R_SWIZ_B_1 |
 						   R500_ALU_RGB_B_SWIZ_B_1 |
-						   R500_ALU_RGB_G_SWIZ_B_1));//0x00db0220
+						   R500_ALU_RGB_G_SWIZ_B_1));
 
 	    OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_OP_MAD |
 						   R500_ALPHA_SWIZ_A_A |
-						   R500_ALPHA_SWIZ_B_1));//0x00c0c000)
+						   R500_ALPHA_SWIZ_B_1));
 
 	    OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGBA_OP_MAD |
 						   R500_ALU_RGBA_R_SWIZ_0 |
 						   R500_ALU_RGBA_G_SWIZ_0 |
 						   R500_ALU_RGBA_B_SWIZ_0 |
-						   R500_ALU_RGBA_A_SWIZ_0));//0x20490000
+						   R500_ALU_RGBA_A_SWIZ_0));
 	    FINISH_VIDEO();
 	}
 
-	BEGIN_VIDEO(6);
+	BEGIN_VIDEO(5);
 	OUT_VIDEO_REG(R300_TX_INVALTAGS, 0);
 	OUT_VIDEO_REG(R300_TX_ENABLE, txenable);
 
@@ -545,8 +413,8 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
 	OUT_VIDEO_REG(R300_RB3D_COLORPITCH0, colorpitch);
 
 	blendcntl = RADEON_SRC_BLEND_GL_ONE | RADEON_DST_BLEND_GL_ZERO;
+	/* no need to enable blending */
 	OUT_VIDEO_REG(R300_RB3D_BLENDCNTL, blendcntl);
-	OUT_VIDEO_REG(R300_RB3D_ABLENDCNTL, 0);
 	FINISH_VIDEO();
 
 	BEGIN_VIDEO(1);
@@ -722,8 +590,8 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
 		     RADEON_CP_VC_CNTL_VTX_FMT_RADEON_MODE |
 		     (4 << RADEON_CP_VC_CNTL_NUM_SHIFT));
 	} else {
-	    if (IS_R300_VARIANT || IS_AVIVO_VARIANT)
-		BEGIN_RING(4 * VTX_DWORD_COUNT + 6);
+	    if (IS_R300_3D || IS_R500_3D)
+		BEGIN_RING(4 * VTX_DWORD_COUNT + 4);
 	    else
 		BEGIN_RING(4 * VTX_DWORD_COUNT + 2);
 	    OUT_RING(CP_PACKET3(R200_CP_PACKET3_3D_DRAW_IMMD_2,
@@ -733,8 +601,8 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
 		     (4 << RADEON_CP_VC_CNTL_NUM_SHIFT));
 	}
 #else /* ACCEL_CP */
-	if (IS_R300_VARIANT || IS_AVIVO_VARIANT)
-	    BEGIN_VIDEO(3 + VTX_DWORD_COUNT * 4);
+	if (IS_R300_3D || IS_R500_3D)
+	    BEGIN_VIDEO(2 + VTX_DWORD_COUNT * 4);
 	else
 	    BEGIN_VIDEO(1 + VTX_DWORD_COUNT * 4);
 
@@ -759,10 +627,9 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
 	VTX_OUT((float)(dstX + dstw),                                (float)dstY,
 		xFixedToFloat(srcTopRight.x) / info->texW[0],     xFixedToFloat(srcTopRight.y) / info->texH[0]);
 
-	if (IS_R300_VARIANT || IS_AVIVO_VARIANT) {
-	    OUT_VIDEO_REG(R300_RB3D_DSTCACHE_CTLSTAT, R300_DC_FLUSH_3D | R300_DC_FREE_3D);
-	    OUT_VIDEO_REG(RADEON_WAIT_UNTIL, RADEON_WAIT_3D_IDLECLEAN);
-	}
+	if (IS_R300_3D || IS_R500_3D)
+	    /* flushing is pipelined, free/finish is not */
+	    OUT_VIDEO_REG(R300_RB3D_DSTCACHE_CTLSTAT, R300_DC_FLUSH_3D);
 
 #ifdef ACCEL_CP
 	ADVANCE_RING();
diff --git a/src/radeon_video.c b/src/radeon_video.c
index 555186a..216cd65 100644
--- a/src/radeon_video.c
+++ b/src/radeon_video.c
@@ -285,12 +285,15 @@ void RADEONInitVideo(ScreenPtr pScreen)
 	RADEONInitOffscreenImages(pScreen);
     }
 
-    texturedAdaptor = RADEONSetupImageTexturedVideo(pScreen);
-    if (texturedAdaptor != NULL) {
-	adaptors[num_adaptors++] = texturedAdaptor;
-	xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Set up textured video\n");
+    if (info->ChipFamily != CHIP_FAMILY_RV250) {
+	texturedAdaptor = RADEONSetupImageTexturedVideo(pScreen);
+	if (texturedAdaptor != NULL) {
+	    adaptors[num_adaptors++] = texturedAdaptor;
+	    xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Set up textured video\n");
+	} else
+	    xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Failed to set up textured video\n");
     } else
-	xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Failed to set up textured video\n");
+	xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Textured video disabled on RV250 due to HW bug\n");
 
     if(num_adaptors)
 	xf86XVScreenInit(pScreen, adaptors, num_adaptors);