New options for xorg.conf, bug fix in radeon DRM.

- made 'git clone git://anongit.freedesktop.org/git/mesa/drm' obsolete
- introduced new xorg.conf options for both intel and radeon FRC patches
  - FRC (aka sync_fields) switch (default on)
  - process priority (default 0)
  - FRC debug output (default off)
- fixed a driver bug in radeon DRM with possible cause of crash
- removed code looking for lost VBLANK interrupt in radeon DRM. This issue
  has been fixed by standard lenny kernel.

Signed-off-by: Thomas Hilber <sparkie@lowbyte.de>
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>

4 files changed, 83 insertions, 24 deletions

diff --git a/src/radeon.h b/src/radeon.h
index 5191808..2f4bc95 100644
--- a/src/radeon.h
+++ b/src/radeon.h
@@ -204,7 +204,10 @@ typedef enum {
     OPTION_TVSTD,
     OPTION_IGNORE_LID_STATUS,
     OPTION_DEFAULT_TVDAC_ADJ,
-    OPTION_INT10
+    OPTION_INT10,
+    OPTION_SYNC_FIELDS,
+    OPTION_SCHED_PRIO,
+    OPTION_SYF_DEBUG,
 } RADEONOpts;
 
 
@@ -802,6 +805,10 @@ typedef struct {
     Bool              r600_shadow_fb;
     void *fb_shadow;
 
+    Bool sync_fields;
+    int SchedPrio;
+    Bool SYF_debug;
+
     int num_gb_pipes;
     Bool has_tcl;
 } RADEONInfoRec, *RADEONInfoPtr;
diff --git a/src/radeon_driver.c b/src/radeon_driver.c
index b6e1990..0bba6f9 100644
--- a/src/radeon_driver.c
+++ b/src/radeon_driver.c
@@ -111,6 +111,8 @@
 #include "radeon_chipset_gen.h"
 
 
+#include <errno.h>
+#include "sys/resource.h"
 #include "radeon_chipinfo_gen.h"
 
 				/* Forward definitions for driver functions */
@@ -192,7 +194,10 @@ static const OptionInfoRec RADEONOptions[] = {
     { OPTION_IGNORE_LID_STATUS, "IgnoreLidStatus", OPTV_BOOLEAN, {0}, FALSE },
     { OPTION_DEFAULT_TVDAC_ADJ, "DefaultTVDACAdj", OPTV_BOOLEAN, {0}, FALSE },
     { OPTION_INT10,             "Int10",           OPTV_BOOLEAN, {0}, FALSE },
-    { -1,                    NULL,               OPTV_NONE,    {0}, FALSE }
+    { OPTION_SYNC_FIELDS,    "SyncFields",         OPTV_BOOLEAN, {0}, FALSE },
+    { OPTION_SCHED_PRIO,     "SF_SchedPrio",       OPTV_INTEGER, {0}, FALSE },
+    { OPTION_SYF_DEBUG,      "SF_Debug",           OPTV_BOOLEAN, {0}, FALSE },
+    { -1,                    NULL,                 OPTV_NONE,    {0}, FALSE }
 };
 
 const OptionInfoRec *RADEONOptionsWeak(void) { return RADEONOptions; }
@@ -2663,6 +2668,7 @@ Bool RADEONPreInit(ScrnInfoPtr pScrn, int flags)
     int crtc_max_X, crtc_max_Y;
     RADEONEntPtr pRADEONEnt;
     DevUnion* pPriv;
+    MessageType from = X_PROBED;
 
     xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
 		   "RADEONPreInit\n");
@@ -2941,6 +2947,61 @@ Bool RADEONPreInit(ScrnInfoPtr pScrn, int flags)
       goto fail;
    }
 
+    /* read sync fields options */
+    if (xf86GetOptValBool(info->Options, OPTION_SYNC_FIELDS, &info->sync_fields)) {
+      from = X_CONFIG;
+    } else {
+      info->sync_fields = TRUE;
+      from = X_DEFAULT;
+    }
+    xf86DrvMsg(pScrn->scrnIndex, from, "sync fields %sactivated\n",
+		info->sync_fields ? "" : "de");
+    if (xf86GetOptValInteger(info->Options, OPTION_SCHED_PRIO, &info->SchedPrio)) {
+      from = X_CONFIG;
+    } else {
+      info->SchedPrio = 0;
+      from = X_DEFAULT;
+    }
+    xf86DrvMsg(pScrn->scrnIndex, from, "scheduling priority requested %d\n",
+                 info->SchedPrio);
+    if (xf86GetOptValBool(info->Options, OPTION_SYF_DEBUG, &info->SYF_debug)) {
+      from = X_CONFIG;
+    } else {
+      info->SYF_debug = FALSE;
+      from = X_DEFAULT;
+    }
+    xf86DrvMsg(pScrn->scrnIndex, from, "sync fields debug %sactivated\n",
+		info->SYF_debug ? "" : "de");
+
+    /* control sync fields options consistency */
+    if (!(pScrn->currentMode->Flags & V_INTERLACE)
+     && info->sync_fields) {
+      xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Cannot support sync fields on non interlaced displays, disabled\n");
+      info->sync_fields = 0;
+    }
+
+    /*
+     * sync_fields only works with
+     * Modeline  "720x576_50i"      13.875   720  744  808  888   576  580  585  625  -hsync -vsync interlace
+     */
+    if ((pScrn->currentMode->Clock != 13875
+     ||  pScrn->currentMode->HDisplay != 720
+     ||  pScrn->currentMode->VDisplay != 576)
+     &&  info->sync_fields) {
+       xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Cannot support sync fields with current timing, disabled\n");
+       info->sync_fields = 0;
+    }
+    if (info->sync_fields) {
+      if (info->SchedPrio) {
+          if (setpriority(PRIO_PROCESS, 0, info->SchedPrio)) {
+            xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
+                "failed to setpriority as requested: %s\n", strerror(errno));
+          } else {
+            xf86DrvMsg(pScrn->scrnIndex, X_INFO,
+                "set scheduling priority to %d\n", getpriority(PRIO_PROCESS, 0));
+          }
+      }
+    }
 
 				/* Free int10 info */
     if (pInt10)
diff --git a/src/radeon_reg.h b/src/radeon_reg.h
index 524806f..1971a02 100644
--- a/src/radeon_reg.h
+++ b/src/radeon_reg.h
@@ -470,9 +470,7 @@
 
 #define RADEON_CRTC2_PITCH                  0x032c
 #define RADEON_CRTC_STATUS                  0x005c
-#ifdef VGA_SYNC_FIELDS
 #       define RADEON_CRTC_CURRENT_FIELD    (1 << 3)
-#endif
 #       define RADEON_CRTC_VBLANK_SAVE      (1 <<  1)
 #       define RADEON_CRTC_VBLANK_SAVE_CLEAR  (1 <<  1)
 #define RADEON_CRTC2_STATUS                  0x03fc
@@ -502,9 +500,7 @@
 #       define RADEON_CRTC2_V_DISP_SHIFT    16
 #define RADEON_CRTC_VLINE_CRNT_VLINE        0x0210
 #       define RADEON_CRTC_CRNT_VLINE_MASK  (0x7ff << 16)
-#ifdef VGA_SYNC_FIELDS
 #	define RADEON_CRTC_CRNT_VLINE_SHIFT 16
-#endif
 #define RADEON_CRTC2_CRNT_FRAME             0x0314
 #define RADEON_CRTC2_GUI_TRIG_VLINE         0x0318
 #define RADEON_CRTC2_STATUS                 0x03fc
diff --git a/src/radeon_video.c b/src/radeon_video.c
index 3953859..487b44f 100644
--- a/src/radeon_video.c
+++ b/src/radeon_video.c
@@ -8,16 +8,12 @@
 #include <stdio.h>
 #include <math.h>
 
-#define VGA_SYNC_FIELDS
-
-#ifdef VGA_SYNC_FIELDS
 #define _RADEON_COMMON_H_
 #include <errno.h>
 #include <sys/ioctl.h>
 #include <xf86drm.h>
 #include <drm/radeon_drm.h>
 extern void vga_sync_fields();
-#endif
 
 #include "radeon.h"
 #include "radeon_reg.h"
@@ -2870,8 +2866,11 @@ RADEONDisplayVideo(
     OUTREG(RADEON_OV0_P23_V_ACCUM_INIT, p23_v_accum_init);
     OUTREG(RADEON_OV0_P23_H_ACCUM_INIT, p23_h_accum_init);
 
-   scale_cntl = RADEON_SCALER_VERT_PICK_NEAREST | RADEON_SCALER_ADAPTIVE_DEINT | RADEON_SCALER_DOUBLE_BUFFER 
+   scale_cntl = RADEON_SCALER_ADAPTIVE_DEINT | RADEON_SCALER_DOUBLE_BUFFER 
         | RADEON_SCALER_ENABLE | RADEON_SCALER_SMART_SWITCH | (0x7f<<16) | scaler_src;
+   if (info->sync_fields) {
+       scale_cntl |= RADEON_SCALER_VERT_PICK_NEAREST;
+   }
    switch(id){
         case FOURCC_UYVY:
 		scale_cntl |= RADEON_SCALER_SOURCE_YVYU422;
@@ -2944,9 +2943,9 @@ RADEONPutImage(
    uint32_t tmp;
    xf86CrtcPtr crtc;
 
-#ifdef VGA_SYNC_FIELDS
-    vga_sync_fields(info->drmFD, info->MMIO);
-#endif
+   if (info->sync_fields) {
+	vga_sync_fields(info->drmFD, info->MMIO);
+   }
 
    /*
     * s2offset, s3offset - byte offsets into U and V plane of the
@@ -4023,8 +4022,6 @@ switch(pPriv->encoding){
         }       
 }
 
-#ifdef VGA_SYNC_FIELDS
-
 /* --- 8< --- */
 /*
  * field cycle duration in usecs for PAL
@@ -4164,14 +4161,14 @@ vga_sync_fields(fd, RADEONMMIO)
     struct timeval skew2vbl;
     struct timeval tv_usecs;
     int usecs;
-    struct drm_modeset_ctl vbl_activate;
+    drm_radeon_setparam_t vbl_activate;
 
     if (!vbl_refcnt) {
-	vbl_activate.crtc = VSF_CRTC;
-	vbl_activate.cmd = _DRM_PRE_MODESET;
-	if (ioctl(fd, DRM_IOCTL_MODESET_CTL, &vbl_activate)) {
-	    ErrorF("DRM_IOCTL_MODESET_CTL: %s\n", strerror(errno)); exit(-1);
-	}
+        vbl_activate.param = RADEON_SETPARAM_VBLANK_CRTC;
+        vbl_activate.value = DRM_RADEON_VBLANK_CRTC1;
+        if (ioctl(fd, DRM_IOCTL_RADEON_SETPARAM, &vbl_activate)) {
+            ErrorF("DRM_IOCTL_RADEON_SETPARAM: %s\n", strerror(errno));
+        }
 	++vbl_refcnt;
     }
 
@@ -4265,5 +4262,3 @@ vga_sync_fields(fd, RADEONMMIO)
 /* --- 8< --- */
 
 }
-#endif
-