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authorBrice Goglin <bgoglin@debian.org>2008-03-20 09:00:20 +0100
committerBrice Goglin <bgoglin@debian.org>2008-03-20 09:00:20 +0100
commitd7bc06b02231f576e150d3a8a43b0d21e02f278d (patch)
tree242c3a9b4b74a2e7c2181c15de9e0e8116595421
parent494b2d0a0cc1426283fa259b75a1d4edeff20d09 (diff)
parent5e3b21284482df9974c9a58f248f0100def2bb0c (diff)
downloadxf86-video-ati-frc-d7bc06b02231f576e150d3a8a43b0d21e02f278d.tar.gz
xf86-video-ati-frc-d7bc06b02231f576e150d3a8a43b0d21e02f278d.tar.bz2
Merge branch 'master' of git://git.freedesktop.org/git/xorg/driver/xf86-video-ati into debian-experimental
Diffstat
-rw-r--r--src/ati.c2
-rw-r--r--src/ati.h2
-rw-r--r--src/ati_pciids_gen.h6
-rw-r--r--src/atimodule.c2
-rw-r--r--src/atombios_crtc.c13
-rw-r--r--src/atombios_output.c101
-rw-r--r--src/legacy_output.c2
-rw-r--r--src/pcidb/ati_pciids.csv8
-rw-r--r--src/radeon.h380
-rw-r--r--src/radeon_atombios.c725
-rw-r--r--src/radeon_atomwrapper.c2
-rw-r--r--src/radeon_chipinfo_gen.h8
-rw-r--r--src/radeon_chipset_gen.h6
-rw-r--r--src/radeon_crtc.c11
-rw-r--r--src/radeon_cursor.c8
-rw-r--r--src/radeon_driver.c80
-rw-r--r--src/radeon_exa.c9
-rw-r--r--src/radeon_exa_funcs.c4
-rw-r--r--src/radeon_exa_render.c1103
-rw-r--r--src/radeon_output.c142
-rw-r--r--src/radeon_pci_chipset_gen.h6
-rw-r--r--src/radeon_pci_device_match_gen.h6
-rw-r--r--src/radeon_probe.h6
-rw-r--r--src/radeon_reg.h187
-rw-r--r--src/radeon_render.c9
-rw-r--r--src/radeon_textured_video.c22
-rw-r--r--src/radeon_textured_videofuncs.c100
-rw-r--r--src/theatre_detect.c1
28 files changed, 1577 insertions, 1374 deletions
diff --git a/src/ati.c b/src/ati.c
index b3f07ca..85da389 100644
--- a/src/ati.c
+++ b/src/ati.c
@@ -102,7 +102,7 @@ ati_device_get_from_busid(int bus, int dev, int func)
}
static struct pci_device*
-ati_device_get_primary()
+ati_device_get_primary(void)
{
struct pci_device *device = NULL;
struct pci_device_iterator *device_iter;
diff --git a/src/ati.h b/src/ati.h
index 828aae1..fa2e45e 100644
--- a/src/ati.h
+++ b/src/ati.h
@@ -31,4 +31,6 @@
#include "xf86_OSproc.h"
+extern void ati_gdev_subdriver(pointer options);
+
#endif /* ___ATI_H___ */
diff --git a/src/ati_pciids_gen.h b/src/ati_pciids_gen.h
index b6b79c1..b5e000c 100644
--- a/src/ati_pciids_gen.h
+++ b/src/ati_pciids_gen.h
@@ -281,9 +281,9 @@
#define PCI_CHIP_RV530_71D6 0x71D6
#define PCI_CHIP_RV530_71DA 0x71DA
#define PCI_CHIP_RV530_71DE 0x71DE
-#define PCI_CHIP_RV530_7200 0x7200
-#define PCI_CHIP_RV530_7210 0x7210
-#define PCI_CHIP_RV530_7211 0x7211
+#define PCI_CHIP_RV515_7200 0x7200
+#define PCI_CHIP_RV515_7210 0x7210
+#define PCI_CHIP_RV515_7211 0x7211
#define PCI_CHIP_R580_7240 0x7240
#define PCI_CHIP_R580_7243 0x7243
#define PCI_CHIP_R580_7244 0x7244
diff --git a/src/atimodule.c b/src/atimodule.c
index c249333..f0eb147 100644
--- a/src/atimodule.c
+++ b/src/atimodule.c
@@ -27,8 +27,6 @@
#include "ati.h"
#include "ativersion.h"
-extern void ati_gdev_subdriver(pointer options);
-
/* Module loader interface */
static XF86ModuleVersionInfo ATIVersionRec =
diff --git a/src/atombios_crtc.c b/src/atombios_crtc.c
index 7c628bf..6fbf7ed 100644
--- a/src/atombios_crtc.c
+++ b/src/atombios_crtc.c
@@ -174,6 +174,7 @@ atombios_crtc_set_pll(xf86CrtcPtr crtc, DisplayModePtr mode)
SET_PIXEL_CLOCK_PS_ALLOCATION spc_param;
PIXEL_CLOCK_PARAMETERS_V2 *spc2_ptr;
PIXEL_CLOCK_PARAMETERS_V3 *spc3_ptr;
+ int pll_flags = 0;
xf86OutputPtr output;
RADEONOutputPrivatePtr radeon_output = NULL;
@@ -185,7 +186,11 @@ atombios_crtc_set_pll(xf86CrtcPtr crtc, DisplayModePtr mode)
if (IS_AVIVO_VARIANT) {
CARD32 temp;
- RADEONComputePLL(&info->pll, mode->Clock, &temp, &fb_div, &ref_div, &post_div, 0);
+
+ if (IS_DCE3_VARIANT)
+ pll_flags |= RADEON_PLL_DCE3;
+
+ RADEONComputePLL(&info->pll, mode->Clock, &temp, &fb_div, &ref_div, &post_div, pll_flags);
sclock = temp;
/* disable spread spectrum clocking for now -- thanks Hedy Lamarr */
@@ -232,7 +237,7 @@ atombios_crtc_set_pll(xf86CrtcPtr crtc, DisplayModePtr mode)
switch(minor) {
case 1:
case 2:
- spc2_ptr = &spc_param.sPCLKInput;
+ spc2_ptr = (PIXEL_CLOCK_PARAMETERS_V2*)&spc_param.sPCLKInput;
spc2_ptr->usPixelClock = sclock;
spc2_ptr->usRefDiv = ref_div;
spc2_ptr->usFbDiv = fb_div;
@@ -243,8 +248,7 @@ atombios_crtc_set_pll(xf86CrtcPtr crtc, DisplayModePtr mode)
ptr = &spc_param;
break;
case 3:
- spc3_ptr = &spc_param.sPCLKInput;
-
+ spc3_ptr = (PIXEL_CLOCK_PARAMETERS_V3*)&spc_param.sPCLKInput;
spc3_ptr->usPixelClock = sclock;
spc3_ptr->usRefDiv = ref_div;
spc3_ptr->usFbDiv = fb_div;
@@ -326,7 +330,6 @@ atombios_crtc_mode_set(xf86CrtcPtr crtc,
xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
unsigned char *RADEONMMIO = info->MMIO;
unsigned long fb_location = crtc->scrn->fbOffset + info->fbLocation;
- Bool tilingOld = info->tilingEnabled;
int need_tv_timings = 0;
int i, ret;
SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION crtc_timing;
diff --git a/src/atombios_output.c b/src/atombios_output.c
index 7ae004c..a00d87f 100644
--- a/src/atombios_output.c
+++ b/src/atombios_output.c
@@ -356,11 +356,20 @@ atombios_output_dig1_setup(xf86OutputPtr output, DisplayModePtr mode)
disp_data.ucAction = 1;
disp_data.usPixelClock = mode->Clock / 10;
+ disp_data.ucConfig = ATOM_ENCODER_CONFIG_TRANSMITTER1;
+ if (OUTPUT_IS_DVI || (radeon_output->type == OUTPUT_HDMI)) {
+ if (radeon_output->coherent_mode) {
+ disp_data.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
+ xf86DrvMsg(output->scrn->scrnIndex, X_INFO, "DIG1: Coherent Mode enabled\n");
+ } else
+ xf86DrvMsg(output->scrn->scrnIndex, X_INFO, "DIG1: Coherent Mode disabled\n");
+ }
+
if (mode->Clock > 165000) {
- disp_data.ucConfig = ATOM_ENCODER_CONFIG_LINKA_B | ATOM_ENCODER_CONFIG_TRANSMITTER1;
+ disp_data.ucConfig |= ATOM_ENCODER_CONFIG_LINKA_B;
disp_data.ucLaneNum = 8;
} else {
- disp_data.ucConfig = ATOM_ENCODER_CONFIG_LINKA | ATOM_ENCODER_CONFIG_TRANSMITTER1;
+ disp_data.ucConfig |= ATOM_ENCODER_CONFIG_LINKA;
disp_data.ucLaneNum = 4;
}
@@ -399,12 +408,35 @@ atombios_output_dig1_transmitter_setup(xf86OutputPtr output, DisplayModePtr mode
disp_data.ucAction = ATOM_TRANSMITTER_ACTION_ENABLE;
disp_data.usPixelClock = mode->Clock / 10;
disp_data.ucConfig = ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER | ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL;
- if (mode->Clock > 165000)
- disp_data.ucConfig |= (ATOM_TRANSMITTER_CONFIG_8LANE_LINK |
- ATOM_TRANSMITTER_CONFIG_LINKA_B |
- ATOM_TRANSMITTER_CONFIG_LANE_0_7);
- else
- disp_data.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKA | ATOM_TRANSMITTER_CONFIG_LANE_0_3;
+
+ if (info->IsIGP && (radeon_output->TMDSType == TMDS_UNIPHY)) {
+ if (mode->Clock > 165000) {
+ disp_data.ucConfig |= (ATOM_TRANSMITTER_CONFIG_8LANE_LINK |
+ ATOM_TRANSMITTER_CONFIG_LINKA_B);
+ /* guess */
+ if (radeon_output->igp_lane_info & 0x3)
+ disp_data.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_7;
+ else if (radeon_output->igp_lane_info & 0xc)
+ disp_data.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_15;
+ } else {
+ disp_data.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKA;
+ if (radeon_output->igp_lane_info & 0x1)
+ disp_data.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_3;
+ else if (radeon_output->igp_lane_info & 0x2)
+ disp_data.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_4_7;
+ else if (radeon_output->igp_lane_info & 0x4)
+ disp_data.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_11;
+ else if (radeon_output->igp_lane_info & 0x8)
+ disp_data.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_12_15;
+ }
+ } else {
+ if (mode->Clock > 165000)
+ disp_data.ucConfig |= (ATOM_TRANSMITTER_CONFIG_8LANE_LINK |
+ ATOM_TRANSMITTER_CONFIG_LINKA_B |
+ ATOM_TRANSMITTER_CONFIG_LANE_0_7);
+ else
+ disp_data.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKA | ATOM_TRANSMITTER_CONFIG_LANE_0_3;
+ }
radeon_output->transmitter_config = disp_data.ucConfig;
@@ -433,11 +465,20 @@ atombios_output_dig2_setup(xf86OutputPtr output, DisplayModePtr mode)
disp_data.ucAction = 1;
disp_data.usPixelClock = mode->Clock / 10;
+ disp_data.ucConfig = ATOM_ENCODER_CONFIG_TRANSMITTER2;
+ if (OUTPUT_IS_DVI || (radeon_output->type == OUTPUT_HDMI)) {
+ if (radeon_output->coherent_mode) {
+ disp_data.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
+ xf86DrvMsg(output->scrn->scrnIndex, X_INFO, "DIG2: Coherent Mode enabled\n");
+ } else
+ xf86DrvMsg(output->scrn->scrnIndex, X_INFO, "DIG2: Coherent Mode disabled\n");
+ }
+
if (mode->Clock > 165000) {
- disp_data.ucConfig = ATOM_ENCODER_CONFIG_LINKA_B | ATOM_ENCODER_CONFIG_TRANSMITTER2;
+ disp_data.ucConfig |= ATOM_ENCODER_CONFIG_LINKA_B;
disp_data.ucLaneNum = 8;
} else {
- disp_data.ucConfig = ATOM_ENCODER_CONFIG_LINKA | ATOM_ENCODER_CONFIG_TRANSMITTER2;
+ disp_data.ucConfig |= ATOM_ENCODER_CONFIG_LINKA;
disp_data.ucLaneNum = 4;
}
@@ -476,12 +517,35 @@ atombios_output_dig2_transmitter_setup(xf86OutputPtr output, DisplayModePtr mode
disp_data.ucAction = ATOM_TRANSMITTER_ACTION_ENABLE;
disp_data.usPixelClock = mode->Clock / 10;
disp_data.ucConfig = ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER | ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL;
- if (mode->Clock > 165000)
- disp_data.ucConfig |= (ATOM_TRANSMITTER_CONFIG_8LANE_LINK |
- ATOM_TRANSMITTER_CONFIG_LINKA_B |
- ATOM_TRANSMITTER_CONFIG_LANE_0_7);
- else
- disp_data.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKA | ATOM_TRANSMITTER_CONFIG_LANE_0_3;
+
+ if (info->IsIGP && (radeon_output->TMDSType == TMDS_UNIPHY)) {
+ if (mode->Clock > 165000) {
+ disp_data.ucConfig |= (ATOM_TRANSMITTER_CONFIG_8LANE_LINK |
+ ATOM_TRANSMITTER_CONFIG_LINKA_B);
+ /* guess */
+ if (radeon_output->igp_lane_info & 0x3)
+ disp_data.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_7;
+ else if (radeon_output->igp_lane_info & 0xc)
+ disp_data.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_15;
+ } else {
+ disp_data.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKA;
+ if (radeon_output->igp_lane_info & 0x1)
+ disp_data.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_3;
+ else if (radeon_output->igp_lane_info & 0x2)
+ disp_data.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_4_7;
+ else if (radeon_output->igp_lane_info & 0x4)
+ disp_data.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_11;
+ else if (radeon_output->igp_lane_info & 0x8)
+ disp_data.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_12_15;
+ }
+ } else {
+ if (mode->Clock > 165000)
+ disp_data.ucConfig |= (ATOM_TRANSMITTER_CONFIG_8LANE_LINK |
+ ATOM_TRANSMITTER_CONFIG_LINKA_B |
+ ATOM_TRANSMITTER_CONFIG_LANE_0_7);
+ else
+ disp_data.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKA | ATOM_TRANSMITTER_CONFIG_LANE_0_3;
+ }
radeon_output->transmitter_config = disp_data.ucConfig;
@@ -642,11 +706,6 @@ atombios_output_dig_dpms(xf86OutputPtr output, int mode, int block)
AtomBiosArgRec data;
unsigned char *space;
- /* this tends to cause problems
- * just turning off the crtc seems to be adequte for now
- */
- return ATOM_NOT_IMPLEMENTED;
-
switch (mode) {
case DPMSModeOn:
disp_data.ucAction = ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT;
diff --git a/src/legacy_output.c b/src/legacy_output.c
index 0de13df..9dc7286 100644
--- a/src/legacy_output.c
+++ b/src/legacy_output.c
@@ -675,9 +675,9 @@ RADEONEnableDisplay(xf86OutputPtr output, BOOL bEnable)
unsigned long tmp;
RADEONOutputPrivatePtr radeon_output;
int tv_dac_change = 0, o;
- radeon_output = output->driver_private;
xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
+ radeon_output = output->driver_private;
for (o = 0; o < xf86_config->num_output; o++) {
if (output == xf86_config->output[o]) {
break;
diff --git a/src/pcidb/ati_pciids.csv b/src/pcidb/ati_pciids.csv
index 8851e60..fc340e7 100644
--- a/src/pcidb/ati_pciids.csv
+++ b/src/pcidb/ati_pciids.csv
@@ -187,7 +187,7 @@
"0x5964","RV280_5964","RV280",,,,,,"ATI Radeon 9200SE 5964 (AGP)"
"0x5965","RV280_5965","RV280",,,,,,"ATI FireMV 2200 (PCI)"
"0x5969","RN50_5969","RV100",,,1,,,"ATI ES1000 5969 (PCI)"
-"0x5974","RS482_5974","RS400",,1,,,1,"ATI Radeon XPRESS 200 5974 (PCIE)"
+"0x5974","RS482_5974","RS400",1,1,,,1,"ATI Radeon XPRESS 200 5974 (PCIE)"
"0x5975","RS485_5975","RS400",1,1,,,1,"ATI Radeon XPRESS 200M 5975 (PCIE)"
"0x5A41","RS400_5A41","RS400",,1,,,1,"ATI Radeon XPRESS 200 5A41 (PCIE)"
"0x5A42","RS400_5A42","RS400",1,1,,,1,"ATI Radeon XPRESS 200M 5A42 (PCIE)"
@@ -282,9 +282,9 @@
"0x71D6","RV530_71D6","RV530",1,,,,,"ATI Mobility Radeon X1700 XT"
"0x71DA","RV530_71DA","RV530",,,,,,"ATI FireGL V5200"
"0x71DE","RV530_71DE","RV530",1,,,,,"ATI Mobility Radeon X1700"
-"0x7200","RV530_7200","RV530",,,,,,"ATI Radeon X2300HD"
-"0x7210","RV530_7210","RV530",1,,,,,"ATI Mobility Radeon HD 2300"
-"0x7211","RV530_7211","RV530",1,,,,,"ATI Mobility Radeon HD 2300"
+"0x7200","RV515_7200","RV515",,,,,,"ATI Radeon X2300HD"
+"0x7210","RV515_7210","RV515",1,,,,,"ATI Mobility Radeon HD 2300"
+"0x7211","RV515_7211","RV515",1,,,,,"ATI Mobility Radeon HD 2300"
"0x7240","R580_7240","R580",,,,,,"ATI Radeon X1950"
"0x7243","R580_7243","R580",,,,,,"ATI Radeon X1900"
"0x7244","R580_7244","R580",,,,,,"ATI Radeon X1950"
diff --git a/src/radeon.h b/src/radeon.h
index fe45428..f3db451 100644
--- a/src/radeon.h
+++ b/src/radeon.h
@@ -214,6 +214,7 @@ typedef struct {
#define RADEON_PLL_NO_ODD_POST_DIV (1 << 1)
#define RADEON_PLL_USE_REF_DIV (1 << 2)
#define RADEON_PLL_LEGACY (1 << 3)
+#define RADEON_PLL_DCE3 (1 << 4)
typedef struct {
CARD16 reference_freq;
@@ -270,7 +271,7 @@ typedef enum {
CHIP_FAMILY_RV570, /* rv570 */
CHIP_FAMILY_RS690,
CHIP_FAMILY_RS740,
- CHIP_FAMILY_R600, /* r60 */
+ CHIP_FAMILY_R600, /* r600 */
CHIP_FAMILY_R630,
CHIP_FAMILY_RV610,
CHIP_FAMILY_RV630,
@@ -302,6 +303,23 @@ typedef enum {
#define IS_DCE3_VARIANT ((info->ChipFamily >= CHIP_FAMILY_RV620))
+#define IS_R500_3D ((info->ChipFamily == CHIP_FAMILY_RV515) || \
+ (info->ChipFamily == CHIP_FAMILY_R520) || \
+ (info->ChipFamily == CHIP_FAMILY_RV530) || \
+ (info->ChipFamily == CHIP_FAMILY_R580) || \
+ (info->ChipFamily == CHIP_FAMILY_RV560) || \
+ (info->ChipFamily == CHIP_FAMILY_RV570))
+
+#define IS_R300_3D ((info->ChipFamily == CHIP_FAMILY_R300) || \
+ (info->ChipFamily == CHIP_FAMILY_RV350) || \
+ (info->ChipFamily == CHIP_FAMILY_R350) || \
+ (info->ChipFamily == CHIP_FAMILY_RV380) || \
+ (info->ChipFamily == CHIP_FAMILY_R420) || \
+ (info->ChipFamily == CHIP_FAMILY_RV410) || \
+ (info->ChipFamily == CHIP_FAMILY_RS690) || \
+ (info->ChipFamily == CHIP_FAMILY_RS740) || \
+ (info->ChipFamily == CHIP_FAMILY_RS400))
+
/*
* Errata workarounds
*/
@@ -748,147 +766,204 @@ do { \
info->fifo_slots -= entries; \
} while (0)
-extern RADEONEntPtr RADEONEntPriv(ScrnInfoPtr pScrn);
-extern void RADEONWaitForFifoFunction(ScrnInfoPtr pScrn, int entries);
-extern void RADEONWaitForIdleMMIO(ScrnInfoPtr pScrn);
+/* legacy_crtc.c */
+extern void legacy_crtc_dpms(xf86CrtcPtr crtc, int mode);
+extern void legacy_crtc_mode_set(xf86CrtcPtr crtc, DisplayModePtr mode,
+ DisplayModePtr adjusted_mode, int x, int y);
+extern void RADEONInitDispBandwidth(ScrnInfoPtr pScrn);
+extern void RADEONRestoreCommonRegisters(ScrnInfoPtr pScrn,
+ RADEONSavePtr restore);
+extern void RADEONRestoreCrtcRegisters(ScrnInfoPtr pScrn,
+ RADEONSavePtr restore);
+extern void RADEONRestoreCrtc2Registers(ScrnInfoPtr pScrn,
+ RADEONSavePtr restore);
+extern void RADEONRestorePLLRegisters(ScrnInfoPtr pScrn,
+ RADEONSavePtr restore);
+extern void RADEONRestorePLL2Registers(ScrnInfoPtr pScrn,
+ RADEONSavePtr restore);
+extern void RADEONSaveCommonRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save);
+extern void RADEONSaveCrtcRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save);
+extern void RADEONSaveCrtc2Registers(ScrnInfoPtr pScrn, RADEONSavePtr save);
+extern void RADEONSavePLLRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save);
+extern void RADEONSavePLL2Registers(ScrnInfoPtr pScrn, RADEONSavePtr save);
+
+/* legacy_output.c */
+extern RADEONMonitorType legacy_dac_detect(ScrnInfoPtr pScrn,
+ xf86OutputPtr output);
+extern void legacy_output_dpms(xf86OutputPtr output, int mode);
+extern void legacy_output_mode_set(xf86OutputPtr output, DisplayModePtr mode,
+ DisplayModePtr adjusted_mode);
+extern I2CDevPtr RADEONDVODeviceInit(I2CBusPtr b, I2CSlaveAddr addr);
+extern Bool RADEONDVOReadByte(I2CDevPtr dvo, int addr, CARD8 *ch);
+extern Bool RADEONDVOWriteByte(I2CDevPtr dvo, int addr, CARD8 ch);
+extern void RADEONRestoreDACRegisters(ScrnInfoPtr pScrn, RADEONSavePtr restore);
+extern void RADEONRestoreFPRegisters(ScrnInfoPtr pScrn, RADEONSavePtr restore);
+extern void RADEONRestoreFP2Registers(ScrnInfoPtr pScrn, RADEONSavePtr restore);
+extern void RADEONRestoreLVDSRegisters(ScrnInfoPtr pScrn, RADEONSavePtr restore);
+extern void RADEONRestoreRMXRegisters(ScrnInfoPtr pScrn, RADEONSavePtr restore);
+extern void RADEONSaveDACRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save);
+extern void RADEONSaveFPRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save);
+
+/* radeon_accel.c */
+extern Bool RADEONAccelInit(ScreenPtr pScreen);
+extern void RADEONEngineFlush(ScrnInfoPtr pScrn);
+extern void RADEONEngineInit(ScrnInfoPtr pScrn);
+extern void RADEONEngineReset(ScrnInfoPtr pScrn);
+extern void RADEONEngineRestore(ScrnInfoPtr pScrn);
+extern CARD8 *RADEONHostDataBlit(ScrnInfoPtr pScrn, unsigned int cpp,
+ unsigned int w, CARD32 dstPitchOff,
+ CARD32 *bufPitch, int x, int *y,
+ unsigned int *h, unsigned int *hpass);
+extern void RADEONHostDataBlitCopyPass(ScrnInfoPtr pScrn,
+ unsigned int bpp,
+ CARD8 *dst, CARD8 *src,
+ unsigned int hpass,
+ unsigned int dstPitch,
+ unsigned int srcPitch);
+extern void RADEONCopySwap(CARD8 *dst, CARD8 *src, unsigned int size, int swap);
+extern void RADEONHostDataParams(ScrnInfoPtr pScrn, CARD8 *dst,
+ CARD32 pitch, int cpp,
+ CARD32 *dstPitchOffset, int *x, int *y);
+extern void RADEONInit3DEngine(ScrnInfoPtr pScrn);
+extern void RADEONWaitForFifoFunction(ScrnInfoPtr pScrn, int entries);
#ifdef XF86DRI
-extern int RADEONDRISetParam(ScrnInfoPtr pScrn, unsigned int param, int64_t value);
-extern void RADEONWaitForIdleCP(ScrnInfoPtr pScrn);
+extern drmBufPtr RADEONCPGetBuffer(ScrnInfoPtr pScrn);
+extern void RADEONCPFlushIndirect(ScrnInfoPtr pScrn, int discard);
+extern void RADEONCPReleaseIndirect(ScrnInfoPtr pScrn);
+extern int RADEONCPStop(ScrnInfoPtr pScrn, RADEONInfoPtr info);
+# ifdef USE_XAA
+extern Bool RADEONSetupMemXAA_DRI(int scrnIndex, ScreenPtr pScreen);
+# endif
#endif
-extern void RADEONDoAdjustFrame(ScrnInfoPtr pScrn, int x, int y,
- Bool clone);
-
-extern void RADEONEngineReset(ScrnInfoPtr pScrn);
-extern void RADEONEngineFlush(ScrnInfoPtr pScrn);
-extern void RADEONEngineRestore(ScrnInfoPtr pScrn);
+#ifdef USE_XAA
+/* radeon_accelfuncs.c */
+extern void RADEONAccelInitMMIO(ScreenPtr pScreen, XAAInfoRecPtr a);
+extern Bool RADEONSetupMemXAA(int scrnIndex, ScreenPtr pScreen);
+#endif
-extern unsigned RADEONINPLL(ScrnInfoPtr pScrn, int addr);
-extern void RADEONOUTPLL(ScrnInfoPtr pScrn, int addr, CARD32 data);
+/* radeon_bios.c */
+extern Bool RADEONGetBIOSInfo(ScrnInfoPtr pScrn, xf86Int10InfoPtr pInt10);
+extern Bool RADEONGetClockInfoFromBIOS(ScrnInfoPtr pScrn);
+extern Bool RADEONGetConnectorInfoFromBIOS(ScrnInfoPtr pScrn);
+extern Bool RADEONGetDAC2InfoFromBIOS(xf86OutputPtr output);
+extern Bool RADEONGetExtTMDSInfoFromBIOS(xf86OutputPtr output);
+extern Bool RADEONGetHardCodedEDIDFromBIOS(xf86OutputPtr output);
+extern Bool RADEONGetBIOSInitTableOffsets(ScrnInfoPtr pScrn);
+extern Bool RADEONGetLVDSInfoFromBIOS(xf86OutputPtr output);
+extern Bool RADEONGetTMDSInfoFromBIOS(xf86OutputPtr output);
+extern Bool RADEONGetTVInfoFromBIOS(xf86OutputPtr output);
+extern Bool RADEONInitExtTMDSInfoFromBIOS (xf86OutputPtr output);
+extern Bool RADEONPostCardFromBIOSTables(ScrnInfoPtr pScrn);
+
+/* radeon_commonfuncs.c */
+#ifdef XF86DRI
+extern void RADEONWaitForIdleCP(ScrnInfoPtr pScrn);
+#endif
+extern void RADEONWaitForIdleMMIO(ScrnInfoPtr pScrn);
-extern unsigned RADEONINMC(ScrnInfoPtr pScrn, int addr);
-extern void RADEONOUTMC(ScrnInfoPtr pScrn, int addr, CARD32 data);
+/* radeon_crtc.c */
+extern void radeon_crtc_load_lut(xf86CrtcPtr crtc);
+extern Bool RADEONAllocateControllers(ScrnInfoPtr pScrn, int mask);
+extern void RADEONBlank(ScrnInfoPtr pScrn);
+extern void RADEONComputePLL(RADEONPLLPtr pll, unsigned long freq,
+ CARD32 *chosen_dot_clock_freq,
+ CARD32 *chosen_feedback_div,
+ CARD32 *chosen_reference_div,
+ CARD32 *chosen_post_div, int flags);
+extern DisplayModePtr RADEONCrtcFindClosestMode(xf86CrtcPtr crtc,
+ DisplayModePtr pMode);
+extern void RADEONUnblank(ScrnInfoPtr pScrn);
+extern Bool RADEONSetTiling(ScrnInfoPtr pScrn);
+
+/* radeon_cursor.c */
+extern Bool RADEONCursorInit(ScreenPtr pScreen);
+extern void radeon_crtc_hide_cursor(xf86CrtcPtr crtc);
+extern void radeon_crtc_load_cursor_argb(xf86CrtcPtr crtc, CARD32 *image);
+extern void radeon_crtc_set_cursor_colors(xf86CrtcPtr crtc, int bg, int fg);
+extern void radeon_crtc_set_cursor_position(xf86CrtcPtr crtc, int x, int y);
+extern void radeon_crtc_show_cursor(xf86CrtcPtr crtc);
+
+/* radeon_dga.c */
+extern Bool RADEONDGAInit(ScreenPtr pScreen);
-extern void RADEONWaitForVerticalSync(ScrnInfoPtr pScrn);
-extern void RADEONWaitForVerticalSync2(ScrnInfoPtr pScrn);
+#ifdef XF86DRI
+/* radeon_dri.c */
+extern void RADEONDRIAllocatePCIGARTTable(ScreenPtr pScreen);
+extern void RADEONDRICloseScreen(ScreenPtr pScreen);
+extern Bool RADEONDRIFinishScreenInit(ScreenPtr pScreen);
+extern int RADEONDRIGetPciAperTableSize(ScrnInfoPtr pScrn);
+extern Bool RADEONDRIGetVersion(ScrnInfoPtr pScrn);
+extern void RADEONDRIResume(ScreenPtr pScreen);
+extern Bool RADEONDRIScreenInit(ScreenPtr pScreen);
+extern int RADEONDRISetParam(ScrnInfoPtr pScrn,
+ unsigned int param, int64_t value);
+extern Bool RADEONDRISetVBlankInterrupt(ScrnInfoPtr pScrn, Bool on);
+extern void RADEONDRIStop(ScreenPtr pScreen);
+#endif
-extern void RADEONChangeSurfaces(ScrnInfoPtr pScrn);
+/* radeon_driver.c */
+extern void RADEONDoAdjustFrame(ScrnInfoPtr pScrn, int x, int y, Bool clone);
+extern void RADEONChangeSurfaces(ScrnInfoPtr pScrn);
+extern RADEONEntPtr RADEONEntPriv(ScrnInfoPtr pScrn);
+extern int RADEONMinBits(int val);
+extern unsigned RADEONINMC(ScrnInfoPtr pScrn, int addr);
+extern unsigned RADEONINPLL(ScrnInfoPtr pScrn, int addr);
+extern void RADEONOUTMC(ScrnInfoPtr pScrn, int addr, CARD32 data);
+extern void RADEONOUTPLL(ScrnInfoPtr pScrn, int addr, CARD32 data);
+extern void RADEONPllErrataAfterData(RADEONInfoPtr info);
+extern void RADEONPllErrataAfterIndex(RADEONInfoPtr info);
+extern void RADEONWaitForVerticalSync(ScrnInfoPtr pScrn);
+extern void RADEONWaitForVerticalSync2(ScrnInfoPtr pScrn);
-extern Bool RADEONAccelInit(ScreenPtr pScreen);
#ifdef USE_EXA
-extern Bool RADEONSetupMemEXA (ScreenPtr pScreen);
-extern Bool RADEONDrawInitMMIO(ScreenPtr pScreen);
-#ifdef XF86DRI
-extern unsigned long long RADEONTexOffsetStart(PixmapPtr pPix);
-extern Bool RADEONGetDatatypeBpp(int bpp, CARD32 *type);
-extern Bool RADEONGetPixmapOffsetPitch(PixmapPtr pPix,
- CARD32 *pitch_offset);
-extern Bool RADEONDrawInitCP(ScreenPtr pScreen);
-extern void RADEONDoPrepareCopyCP(ScrnInfoPtr pScrn,
- CARD32 src_pitch_offset,
- CARD32 dst_pitch_offset,
- CARD32 datatype, int rop,
- Pixel planemask);
-extern void RADEONCopyCP(PixmapPtr pDst, int srcX, int srcY, int dstX,
- int dstY, int w, int h);
+/* radeon_exa.c */
+extern Bool RADEONSetupMemEXA(ScreenPtr pScreen);
+
+/* radeon_exa_funcs.c */
+extern void RADEONCopyCP(PixmapPtr pDst, int srcX, int srcY, int dstX,
+ int dstY, int w, int h);
+extern void RADEONCopyMMIO(PixmapPtr pDst, int srcX, int srcY, int dstX,
+ int dstY, int w, int h);
+extern Bool RADEONDrawInitCP(ScreenPtr pScreen);
+extern Bool RADEONDrawInitMMIO(ScreenPtr pScreen);
+extern void RADEONDoPrepareCopyCP(ScrnInfoPtr pScrn,
+ CARD32 src_pitch_offset,
+ CARD32 dst_pitch_offset,
+ CARD32 datatype, int rop,
+ Pixel planemask);
+extern void RADEONDoPrepareCopyMMIO(ScrnInfoPtr pScrn,
+ CARD32 src_pitch_offset,
+ CARD32 dst_pitch_offset,
+ CARD32 datatype, int rop,
+ Pixel planemask);
#endif
-#endif
-#ifdef USE_XAA
-extern void RADEONAccelInitMMIO(ScreenPtr pScreen, XAAInfoRecPtr a);
-#endif
-extern void RADEONEngineInit(ScrnInfoPtr pScrn);
-extern Bool RADEONCursorInit(ScreenPtr pScreen);
-extern Bool RADEONDGAInit(ScreenPtr pScreen);
-
-extern void RADEONInit3DEngine(ScrnInfoPtr pScrn);
-
-extern int RADEONMinBits(int val);
-
-extern void RADEONInitVideo(ScreenPtr pScreen);
-extern void RADEONResetVideo(ScrnInfoPtr pScrn);
-extern void R300CGWorkaround(ScrnInfoPtr pScrn);
-
-extern void RADEONPllErrataAfterIndex(RADEONInfoPtr info);
-extern void RADEONPllErrataAfterData(RADEONInfoPtr info);
-
-extern Bool RADEONGetBIOSInfo(ScrnInfoPtr pScrn, xf86Int10InfoPtr pInt10);
-extern Bool RADEONGetConnectorInfoFromBIOS (ScrnInfoPtr pScrn);
-extern Bool RADEONGetClockInfoFromBIOS (ScrnInfoPtr pScrn);
-extern Bool RADEONGetLVDSInfoFromBIOS (xf86OutputPtr output);
-extern Bool RADEONGetTMDSInfoFromBIOS (xf86OutputPtr output);
-extern Bool RADEONGetTVInfoFromBIOS (xf86OutputPtr output);
-extern Bool RADEONGetDAC2InfoFromBIOS (xf86OutputPtr output);
-extern Bool RADEONGetHardCodedEDIDFromBIOS (xf86OutputPtr output);
-
-extern void RADEONRestoreCommonRegisters(ScrnInfoPtr pScrn,
- RADEONSavePtr restore);
-extern void RADEONRestoreCrtcRegisters(ScrnInfoPtr pScrn,
- RADEONSavePtr restore);
-extern void RADEONRestoreDACRegisters(ScrnInfoPtr pScrn,
- RADEONSavePtr restore);
-extern void RADEONRestoreFPRegisters(ScrnInfoPtr pScrn,
- RADEONSavePtr restore);
-extern void RADEONRestoreFP2Registers(ScrnInfoPtr pScrn,
- RADEONSavePtr restore);
-extern void RADEONRestoreLVDSRegisters(ScrnInfoPtr pScrn,
- RADEONSavePtr restore);
-extern void RADEONRestoreRMXRegisters(ScrnInfoPtr pScrn,
- RADEONSavePtr restore);
-extern void RADEONRestorePLLRegisters(ScrnInfoPtr pScrn,
- RADEONSavePtr restore);
-extern void RADEONRestoreCrtc2Registers(ScrnInfoPtr pScrn,
- RADEONSavePtr restore);
-extern void RADEONRestorePLL2Registers(ScrnInfoPtr pScrn,
- RADEONSavePtr restore);
-
-extern void RADEONInitDispBandwidth(ScrnInfoPtr pScrn);
-extern Bool RADEONI2cInit(ScrnInfoPtr pScrn);
-extern Bool RADEONSetupConnectors(ScrnInfoPtr pScrn);
-extern void RADEONPrintPortMap(ScrnInfoPtr pScrn);
-extern void RADEONDisableDisplays(ScrnInfoPtr pScrn);
-extern void RADEONGetPanelInfo(ScrnInfoPtr pScrn);
-extern void RADEONUnblank(ScrnInfoPtr pScrn);
-extern void RADEONUnblank(ScrnInfoPtr pScrn);
-extern void RADEONBlank(ScrnInfoPtr pScrn);
-extern Bool RADEONSetTiling(ScrnInfoPtr pScrn);
-extern Bool RADEONAllocateControllers(ScrnInfoPtr pScrn, int mask);
-extern Bool RADEONAllocateConnectors(ScrnInfoPtr pScrn);
-extern void RADEONSetPitch (ScrnInfoPtr pScrn);
-extern void RADEONUpdateHVPosition(xf86OutputPtr output, DisplayModePtr mode);
-
-extern DisplayModePtr
-RADEONProbeOutputModes(xf86OutputPtr output);
-
-extern Bool
-RADEONDVOReadByte(I2CDevPtr dvo, int addr, CARD8 *ch);
-extern Bool
-RADEONDVOWriteByte(I2CDevPtr dvo, int addr, CARD8 ch);
-extern Bool
-RADEONGetExtTMDSInfoFromBIOS (xf86OutputPtr output);
-extern Bool
-RADEONInitExtTMDSInfoFromBIOS (xf86OutputPtr output);
-
-extern RADEONI2CBusRec
-legacy_setup_i2c_bus(int ddc_line);
-extern RADEONI2CBusRec
-atom_setup_i2c_bus(int ddc_line);
-
-extern void
-radeon_crtc_set_cursor_position (xf86CrtcPtr crtc, int x, int y);
-extern void
-radeon_crtc_show_cursor (xf86CrtcPtr crtc);
-extern void
-radeon_crtc_hide_cursor (xf86CrtcPtr crtc);
-extern void
-radeon_crtc_set_cursor_position (xf86CrtcPtr crtc, int x, int y);
-extern void
-radeon_crtc_set_cursor_colors (xf86CrtcPtr crtc, int bg, int fg);
-extern void
-radeon_crtc_load_cursor_argb (xf86CrtcPtr crtc, CARD32 *image);
-extern void
-radeon_crtc_load_lut(xf86CrtcPtr crtc);
+#if defined(XF86DRI) && defined(USE_EXA)
+/* radeon_exa.c */
+extern Bool RADEONGetDatatypeBpp(int bpp, CARD32 *type);
+extern Bool RADEONGetPixmapOffsetPitch(PixmapPtr pPix,
+ CARD32 *pitch_offset);
+extern unsigned long long RADEONTexOffsetStart(PixmapPtr pPix);
+#endif
+/* radeon_modes.c */
+extern void RADEONSetPitch(ScrnInfoPtr pScrn);
+extern DisplayModePtr RADEONProbeOutputModes(xf86OutputPtr output);
+
+/* radeon_output.c */
+extern RADEONI2CBusRec atom_setup_i2c_bus(int ddc_line);
+extern RADEONI2CBusRec legacy_setup_i2c_bus(int ddc_line);
+extern void RADEONConnectorFindMonitor(ScrnInfoPtr pScrn, xf86OutputPtr output);
+extern void RADEONGetPanelInfo(ScrnInfoPtr pScrn);
+extern void RADEONInitConnector(xf86OutputPtr output);
+extern void RADEONPrintPortMap(ScrnInfoPtr pScrn);
+extern void RADEONSetOutputType(ScrnInfoPtr pScrn,
+ RADEONOutputPrivatePtr radeon_output);
+extern Bool RADEONSetupConnectors(ScrnInfoPtr pScrn);
+
+/* radeon_tv.c */
+extern void RADEONSaveTVRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save);
extern void RADEONAdjustCrtcRegistersForTV(ScrnInfoPtr pScrn, RADEONSavePtr save,
DisplayModePtr mode, xf86OutputPtr output);
extern void RADEONAdjustPLLRegistersForTV(ScrnInfoPtr pScrn, RADEONSavePtr save,
@@ -899,47 +974,18 @@ extern void RADEONAdjustPLL2RegistersForTV(ScrnInfoPtr pScrn, RADEONSavePtr save
DisplayModePtr mode, xf86OutputPtr output);
extern void RADEONInitTVRegisters(xf86OutputPtr output, RADEONSavePtr save,
DisplayModePtr mode, BOOL IsPrimary);
-
extern void RADEONRestoreTVRegisters(ScrnInfoPtr pScrn, RADEONSavePtr restore);
+extern void RADEONUpdateHVPosition(xf86OutputPtr output, DisplayModePtr mode);
-extern void RADEONComputePLL(RADEONPLLPtr pll, unsigned long freq, CARD32 *chosen_dot_clock_freq,
- CARD32 *chosen_feedback_div, CARD32 *chosen_reference_div,
- CARD32 *chosen_post_div, int flags);
+/* radeon_video.c */
+extern void RADEONInitVideo(ScreenPtr pScreen);
+extern void RADEONResetVideo(ScrnInfoPtr pScrn);
#ifdef XF86DRI
-#ifdef USE_XAA
-extern void RADEONAccelInitCP(ScreenPtr pScreen, XAAInfoRecPtr a);
-#endif
-extern Bool RADEONDRIGetVersion(ScrnInfoPtr pScrn);
-extern Bool RADEONDRIScreenInit(ScreenPtr pScreen);
-extern void RADEONDRICloseScreen(ScreenPtr pScreen);
-extern void RADEONDRIResume(ScreenPtr pScreen);
-extern Bool RADEONDRIFinishScreenInit(ScreenPtr pScreen);
-extern void RADEONDRIAllocatePCIGARTTable(ScreenPtr pScreen);
-extern int RADEONDRIGetPciAperTableSize(ScrnInfoPtr pScrn);
-extern void RADEONDRIStop(ScreenPtr pScreen);
-
-extern drmBufPtr RADEONCPGetBuffer(ScrnInfoPtr pScrn);
-extern void RADEONCPFlushIndirect(ScrnInfoPtr pScrn, int discard);
-extern void RADEONCPReleaseIndirect(ScrnInfoPtr pScrn);
-extern int RADEONCPStop(ScrnInfoPtr pScrn, RADEONInfoPtr info);
-extern Bool RADEONDRISetVBlankInterrupt(ScrnInfoPtr pScrn, Bool on);
-
-extern void RADEONHostDataParams(ScrnInfoPtr pScrn, CARD8 *dst,
- CARD32 pitch, int cpp,
- CARD32 *dstPitchOffset, int *x, int *y);
-extern CARD8* RADEONHostDataBlit(ScrnInfoPtr pScrn, unsigned int cpp,
- unsigned int w, CARD32 dstPitchOff,
- CARD32 *bufPitch, int x, int *y,
- unsigned int *h, unsigned int *hpass);
-extern void RADEONHostDataBlitCopyPass(ScrnInfoPtr pScrn,
- unsigned int bpp,
- CARD8 *dst, CARD8 *src,
- unsigned int hpass,
- unsigned int dstPitch,
- unsigned int srcPitch);
-extern void RADEONCopySwap(CARD8 *dst, CARD8 *src, unsigned int size,
- int swap);
+# ifdef USE_XAA
+/* radeon_accelfuncs.c */
+extern void RADEONAccelInitCP(ScreenPtr pScreen, XAAInfoRecPtr a);
+# endif
#define RADEONCP_START(pScrn, info) \
do { \
diff --git a/src/radeon_atombios.c b/src/radeon_atombios.c
index 4494775..85a2e71 100644
--- a/src/radeon_atombios.c
+++ b/src/radeon_atombios.c
@@ -1399,7 +1399,7 @@ const int object_connector_convert[] =
CONNECTOR_NONE,
CONNECTOR_NONE,
CONNECTOR_NONE,
- CONNECTOR_NONE,
+ CONNECTOR_DISPLAY_PORT,
};
static void
@@ -1499,6 +1499,7 @@ RADEONGetATOMConnectorInfoFromBIOSObject (ScrnInfoPtr pScrn)
unsigned short size;
atomDataTablesPtr atomDataPtr;
ATOM_CONNECTOR_OBJECT_TABLE *con_obj;
+ ATOM_INTEGRATED_SYSTEM_INFO_V2 *igp_obj = NULL;
int i, j, ddc_line = 0;
atomDataPtr = info->atomBIOS->atomDataPtr;
@@ -1507,7 +1508,7 @@ RADEONGetATOMConnectorInfoFromBIOSObject (ScrnInfoPtr pScrn)
if (crev < 2)
return FALSE;
-
+
con_obj = (ATOM_CONNECTOR_OBJECT_TABLE *)
((char *)&atomDataPtr->Object_Header->sHeader +
atomDataPtr->Object_Header->usConnectorObjectTableOffset);
@@ -1527,9 +1528,30 @@ RADEONGetATOMConnectorInfoFromBIOSObject (ScrnInfoPtr pScrn)
SrcDstTable = (ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *)
((char *)&atomDataPtr->Object_Header->sHeader
+ con_obj->asObjects[i].usSrcDstTableOffset);
-
+
ErrorF("object id %04x %02x\n", obj_id, SrcDstTable->ucNumberOfSrc);
- info->BiosConnector[i].ConnectorType = object_connector_convert[obj_id];
+
+ if ((info->ChipFamily == CHIP_FAMILY_RS780) &&
+ (obj_id == CONNECTOR_OBJECT_ID_PCIE_CONNECTOR)) {
+ CARD32 slot_config, ct;
+
+ igp_obj = info->atomBIOS->atomDataPtr->IntegratedSystemInfo.IntegratedSystemInfo_v2;
+
+ if (!igp_obj)
+ info->BiosConnector[i].ConnectorType = object_connector_convert[obj_id];
+ else {
+ if (num == 1)
+ slot_config = igp_obj->ulDDISlot1Config;
+ else
+ slot_config = igp_obj->ulDDISlot2Config;
+
+ ct = (slot_config >> 16) & 0xff;
+ info->BiosConnector[i].ConnectorType = object_connector_convert[ct];
+ info->BiosConnector[i].igp_lane_info = slot_config & 0xffff;
+ }
+ } else
+ info->BiosConnector[i].ConnectorType = object_connector_convert[obj_id];
+
if (info->BiosConnector[i].ConnectorType == CONNECTOR_NONE)
info->BiosConnector[i].valid = FALSE;
else
@@ -1541,17 +1563,23 @@ RADEONGetATOMConnectorInfoFromBIOSObject (ScrnInfoPtr pScrn)
sobj_id = (SrcDstTable->usSrcObjectID[j] & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
ErrorF("src object id %04x %d\n", SrcDstTable->usSrcObjectID[j], sobj_id);
-
+
switch(sobj_id) {
case ENCODER_OBJECT_ID_INTERNAL_LVDS:
info->BiosConnector[i].devices |= (1 << ATOM_DEVICE_LCD1_INDEX);
break;
case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
- case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
info->BiosConnector[i].devices |= (1 << ATOM_DEVICE_DFP1_INDEX);
info->BiosConnector[i].TMDSType = TMDS_INT;
break;
+ case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
+ if (num == 1)
+ info->BiosConnector[i].devices |= (1 << ATOM_DEVICE_DFP1_INDEX);
+ else
+ info->BiosConnector[i].devices |= (1 << ATOM_DEVICE_DFP2_INDEX);
+ info->BiosConnector[i].TMDSType = TMDS_UNIPHY;
+ break;
case ENCODER_OBJECT_ID_INTERNAL_TMDS2:
case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
info->BiosConnector[i].devices |= (1 << ATOM_DEVICE_DFP2_INDEX);
@@ -1599,7 +1627,7 @@ RADEONGetATOMConnectorInfoFromBIOSObject (ScrnInfoPtr pScrn)
ErrorF("record type %d\n", Record->ucRecordType);
switch (Record->ucRecordType) {
case ATOM_I2C_RECORD_TYPE:
- rhdAtomParseI2CRecord(info->atomBIOS,
+ rhdAtomParseI2CRecord(info->atomBIOS,
(ATOM_I2C_RECORD *)Record,
&ddc_line);
info->BiosConnector[i].ddc_i2c = atom_setup_i2c_bus(ddc_line);
@@ -1864,689 +1892,6 @@ RADEONGetATOMConnectorInfoFromBIOSConnectorTable (ScrnInfoPtr pScrn)
return TRUE;
}
-#if 0
-#define RHD_CONNECTORS_MAX 4
-#define MAX_OUTPUTS_PER_CONNECTOR 2
-
-#define Limit(n,max,name) ((n >= max) ? ( \
- xf86DrvMsg(handle->scrnIndex,X_ERROR,"%s: %s %i exceeds maximum %i\n", \
- __func__,name,n,max), TRUE) : FALSE)
-
-static const struct _rhd_connector_objs
-{
- char *name;
- RADEONConnectorTypeATOM con;
-} rhd_connector_objs[] = {
- { "NONE", CONNECTOR_NONE_ATOM },
- { "SINGLE_LINK_DVI_I", CONNECTOR_DVI_I_ATOM },
- { "DUAL_LINK_DVI_I", CONNECTOR_DVI_I_ATOM },
- { "SINGLE_LINK_DVI_D", CONNECTOR_DVI_D_ATOM },
- { "DUAL_LINK_DVI_D", CONNECTOR_DVI_D_ATOM },
- { "VGA", CONNECTOR_VGA_ATOM },
- { "COMPOSITE", CONNECTOR_CTV_ATOM },
- { "SVIDEO", CONNECTOR_STV_ATOM },
- { "D_CONNECTOR", CONNECTOR_NONE_ATOM },
- { "9PIN_DIN", CONNECTOR_NONE_ATOM },
- { "SCART", CONNECTOR_SCART_ATOM },
- { "HDMI_TYPE_A", CONNECTOR_HDMI_TYPE_A_ATOM },
- { "HDMI_TYPE_B", CONNECTOR_HDMI_TYPE_B_ATOM },
- { "HDMI_TYPE_B", CONNECTOR_HDMI_TYPE_B_ATOM },
- { "LVDS", CONNECTOR_LVDS_ATOM },
- { "7PIN_DIN", CONNECTOR_STV_ATOM },
- { "PCIE_CONNECTOR", CONNECTOR_NONE_ATOM },
- { "CROSSFIRE", CONNECTOR_NONE_ATOM },
- { "HARDCODE_DVI", CONNECTOR_NONE_ATOM },
- { "DISPLAYPORT", CONNECTOR_DISPLAY_PORT_ATOM }
-};
-static const int n_rhd_connector_objs = sizeof (rhd_connector_objs) / sizeof(struct _rhd_connector_objs);
-
-static const struct _rhd_encoders
-{
- char *name;
- RADEONOutputTypeATOM ot;
-} rhd_encoders[] = {
- { "NONE", OUTPUT_NONE_ATOM },
- { "INTERNAL_LVDS", OUTPUT_LVDS_ATOM },
- { "INTERNAL_TMDS1", OUTPUT_TMDSA_ATOM },
- { "INTERNAL_TMDS2", OUTPUT_TMDSB_ATOM },
- { "INTERNAL_DAC1", OUTPUT_DACA_ATOM },
- { "INTERNAL_DAC2", OUTPUT_DACB_ATOM },
- { "INTERNAL_SDVOA", OUTPUT_NONE_ATOM },
- { "INTERNAL_SDVOB", OUTPUT_NONE_ATOM },
- { "SI170B", OUTPUT_NONE_ATOM },
- { "CH7303", OUTPUT_NONE_ATOM },
- { "CH7301", OUTPUT_NONE_ATOM },
- { "INTERNAL_DVO1", OUTPUT_NONE_ATOM },
- { "EXTERNAL_SDVOA", OUTPUT_NONE_ATOM },
- { "EXTERNAL_SDVOB", OUTPUT_NONE_ATOM },
- { "TITFP513", OUTPUT_NONE_ATOM },
- { "INTERNAL_LVTM1", OUTPUT_LVTMA_ATOM },
- { "VT1623", OUTPUT_NONE_ATOM },
- { "HDMI_SI1930", OUTPUT_NONE_ATOM },
- { "HDMI_INTERNAL", OUTPUT_NONE_ATOM },
- { "INTERNAL_KLDSCP_TMDS1", OUTPUT_TMDSA_ATOM },
- { "INTERNAL_KLSCP_DVO1", OUTPUT_NONE_ATOM },
- { "INTERNAL_KLDSCP_DAC1", OUTPUT_DACA_ATOM },
- { "INTERNAL_KLDSCP_DAC2", OUTPUT_DACB_ATOM },
- { "SI178", OUTPUT_NONE_ATOM },
- { "MVPU_FPGA", OUTPUT_NONE_ATOM },
- { "INTERNAL_DDI", OUTPUT_NONE_ATOM },
- { "VT1625", OUTPUT_NONE_ATOM },
- { "HDMI_SI1932", OUTPUT_NONE_ATOM },
- { "AN9801", OUTPUT_NONE_ATOM },
- { "DP501", OUTPUT_NONE_ATOM },
-};
-static const int n_rhd_encoders = sizeof (rhd_encoders) / sizeof(struct _rhd_encoders);
-
-static const struct _rhd_connectors
-{
- char *name;
- RADEONConnectorTypeATOM con;
- Bool dual;
-} rhd_connectors[] = {
- {"NONE", CONNECTOR_NONE_ATOM, FALSE },
- {"VGA", CONNECTOR_VGA_ATOM, FALSE },
- {"DVI-I", CONNECTOR_DVI_I_ATOM, TRUE },
- {"DVI-D", CONNECTOR_DVI_D_ATOM, FALSE },
- {"DVI-A", CONNECTOR_DVI_A_ATOM, FALSE },
- {"SVIDEO", CONNECTOR_STV_ATOM, FALSE },
- {"COMPOSITE", CONNECTOR_CTV_ATOM, FALSE },
- {"PANEL", CONNECTOR_LVDS_ATOM, FALSE },
- {"DIGITAL_LINK", CONNECTOR_DIGITAL_ATOM, FALSE },
- {"SCART", CONNECTOR_SCART_ATOM, FALSE },
- {"HDMI Type A", CONNECTOR_HDMI_TYPE_A_ATOM, FALSE },
- {"HDMI Type B", CONNECTOR_HDMI_TYPE_B_ATOM, FALSE },
- {"UNKNOWN", CONNECTOR_NONE_ATOM, FALSE },
- {"UNKNOWN", CONNECTOR_NONE_ATOM, FALSE },
- {"DVI+DIN", CONNECTOR_NONE_ATOM, FALSE }
-};
-static const int n_rhd_connectors = sizeof(rhd_connectors) / sizeof(struct _rhd_connectors);
-
-static const struct _rhd_devices
-{
- char *name;
- RADEONOutputTypeATOM ot;
-} rhd_devices[] = {
- {" CRT1", OUTPUT_NONE_ATOM },
- {" LCD1", OUTPUT_LVTMA_ATOM },
- {" TV1", OUTPUT_NONE_ATOM },
- {" DFP1", OUTPUT_TMDSA_ATOM },
- {" CRT2", OUTPUT_NONE_ATOM },
- {" LCD2", OUTPUT_LVTMA_ATOM },
- {" TV2", OUTPUT_NONE_ATOM },
- {" DFP2", OUTPUT_LVTMA_ATOM },
- {" CV", OUTPUT_NONE_ATOM },
- {" DFP3", OUTPUT_LVTMA_ATOM }
-};
-static const int n_rhd_devices = sizeof(rhd_devices) / sizeof(struct _rhd_devices);
-
-static const rhdDDC hwddc[] = { RHD_DDC_0, RHD_DDC_1, RHD_DDC_2, RHD_DDC_3 };
-static const int n_hwddc = sizeof(hwddc) / sizeof(rhdDDC);
-
-static const rhdOutputType acc_dac[] = { OUTPUT_NONE_ATOM,
- OUTPUT_DACA_ATOM,
- OUTPUT_DACB_ATOM,
- OUTPUT_DAC_EXTERNAL_ATOM };
-static const int n_acc_dac = sizeof(acc_dac) / sizeof (rhdOutputType);
-
-/*
- *
- */
-static Bool
-rhdAtomInterpretObjectID(atomBiosHandlePtr handle,
- CARD16 id, CARD8 *obj_type, CARD8 *obj_id,
- CARD8 *num, char **name)
-{
- *obj_id = (id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
- *num = (id & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
- *obj_type = (id & OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
-
- *name = NULL;
-
- switch (*obj_type) {
- case GRAPH_OBJECT_TYPE_CONNECTOR:
- if (!Limit(*obj_id, n_rhd_connector_objs, "obj_id"))
- *name = rhd_connector_objs[*obj_id].name;
- break;
- case GRAPH_OBJECT_TYPE_ENCODER:
- if (!Limit(*obj_id, n_rhd_encoders, "obj_id"))
- *name = rhd_encoders[*obj_id].name;
- break;
- default:
- break;
- }
- return TRUE;
-}
-
-/*
- *
- */
-static void
-rhdAtomDDCFromI2CRecord(atomBiosHandlePtr handle,
- ATOM_I2C_RECORD *Record, rhdDDC *DDC)
-{
- RHDDebug(handle->scrnIndex,
- " %s: I2C Record: %s[%x] EngineID: %x I2CAddr: %x\n",
- __func__,
- Record->sucI2cId.bfHW_Capable ? "HW_Line" : "GPIO_ID",
- Record->sucI2cId.bfI2C_LineMux,
- Record->sucI2cId.bfHW_EngineID,
- Record->ucI2CAddr);
-
- if (!*(unsigned char *)&(Record->sucI2cId))
- *DDC = RHD_DDC_NONE;
- else {
-
- if (Record->ucI2CAddr != 0)
- return;
-
- if (Record->sucI2cId.bfHW_Capable) {
-
- *DDC = (rhdDDC)Record->sucI2cId.bfI2C_LineMux;
- if (*DDC >= RHD_DDC_MAX)
- *DDC = RHD_DDC_NONE;
-
- } else {
- *DDC = RHD_DDC_GPIO;
- /* add GPIO pin parsing */
- }
- }
-}
-
-/*
- *
- */
-static void
-rhdAtomParseGPIOLutForHPD(atomBiosHandlePtr handle,
- CARD8 pinID, rhdHPD *HPD)
-{
- atomDataTablesPtr atomDataPtr;
- ATOM_GPIO_PIN_LUT *gpio_pin_lut;
- unsigned short size;
- int i = 0;
-
- //RHDFUNC(handle);
-
- atomDataPtr = handle->atomDataPtr;
-
- *HPD = RHD_HPD_NONE;
-
- if (!rhdAtomGetTableRevisionAndSize(
- &atomDataPtr->GPIO_Pin_LUT->sHeader, NULL, NULL, &size)) {
- xf86DrvMsg(handle->scrnIndex, X_ERROR,
- "%s: No valid GPIO pin LUT in AtomBIOS\n",__func__);
- return;
- }
- gpio_pin_lut = atomDataPtr->GPIO_Pin_LUT;
-
- while (1) {
- if (gpio_pin_lut->asGPIO_Pin[i].ucGPIO_ID == pinID) {
-
- if ((sizeof(ATOM_COMMON_TABLE_HEADER)
- + (i * sizeof(ATOM_GPIO_PIN_ASSIGNMENT))) > size)
- return;
-
- RHDDebug(handle->scrnIndex,
- " %s: GPIO PinID: %i Index: %x Shift: %i\n",
- __func__,
- pinID,
- gpio_pin_lut->asGPIO_Pin[i].usGpioPin_AIndex,
- gpio_pin_lut->asGPIO_Pin[i].ucGpioPinBitShift);
-
- /* grr... map backwards: register indices -> line numbers */
- if (gpio_pin_lut->asGPIO_Pin[i].usGpioPin_AIndex
- == (DC_GPIO_HPD_A >> 2)) {
- switch (gpio_pin_lut->asGPIO_Pin[i].ucGpioPinBitShift) {
- case 0:
- *HPD = RHD_HPD_0;
- return;
- case 8:
- *HPD = RHD_HPD_1;
- return;
- case 16:
- *HPD = RHD_HPD_2;
- return;
- }
- }
- }
- i++;
- }
-}
-
-/*
- *
- */
-static void
-rhdAtomHPDFromRecord(atomBiosHandlePtr handle,
- ATOM_HPD_INT_RECORD *Record, rhdHPD *HPD)
-{
- RHDDebug(handle->scrnIndex,
- " %s: HPD Record: GPIO ID: %x Plugged_PinState: %x\n",
- __func__,
- Record->ucHPDIntGPIOID,
- Record->ucPluggged_PinState);
- rhdAtomParseGPIOLutForHPD(handle, Record->ucHPDIntGPIOID, HPD);
-}
-
-/*
- *
- */
-static char *
-rhdAtomDeviceTagsFromRecord(atomBiosHandlePtr handle,
- ATOM_CONNECTOR_DEVICE_TAG_RECORD *Record)
-{
- int i, j, k;
- char *devices;
-
- //RHDFUNC(handle);
-
- RHDDebug(handle->scrnIndex," NumberOfDevice: %i\n",
- Record->ucNumberOfDevice);
-
- if (!Record->ucNumberOfDevice) return NULL;
-
- devices = (char *)xcalloc(Record->ucNumberOfDevice * 4 + 1,1);
-
- for (i = 0; i < Record->ucNumberOfDevice; i++) {
- k = 0;
- j = Record->asDeviceTag[i].usDeviceID;
-
- while (!(j & 0x1)) { j >>= 1; k++; };
-
- if (!Limit(k,n_rhd_devices,"usDeviceID"))
- strcat(devices, rhd_devices[k].name);
- }
-
- RHDDebug(handle->scrnIndex," Devices:%s\n",devices);
-
- return devices;
-}
-
-/*
- *
- */
-static AtomBiosResult
-rhdAtomConnectorInfoFromObjectHeader(atomBiosHandlePtr handle,
- rhdConnectorInfoPtr *ptr)
-{
- atomDataTablesPtr atomDataPtr;
- CARD8 crev, frev;
- ATOM_CONNECTOR_OBJECT_TABLE *con_obj;
- rhdConnectorInfoPtr cp;
- unsigned long object_header_end;
- int ncon = 0;
- int i,j;
- unsigned short object_header_size;
-
- //RHDFUNC(handle);
-
- atomDataPtr = handle->atomDataPtr;
-
- if (!rhdAtomGetTableRevisionAndSize(
- &atomDataPtr->Object_Header->sHeader,
- &crev,&frev,&object_header_size)) {
- return ATOM_NOT_IMPLEMENTED;
- }
-
- if (crev < 2) /* don't bother with anything below rev 2 */
- return ATOM_NOT_IMPLEMENTED;
-
- if (!(cp = (rhdConnectorInfoPtr)xcalloc(sizeof(struct rhdConnectorInfo),
- RHD_CONNECTORS_MAX)))
- return ATOM_FAILED;
-
- object_header_end =
- atomDataPtr->Object_Header->usConnectorObjectTableOffset
- + object_header_size;
-
- RHDDebug(handle->scrnIndex,"ObjectTable - size: %u, BIOS - size: %u "
- "TableOffset: %u object_header_end: %u\n",
- object_header_size, handle->BIOSImageSize,
- atomDataPtr->Object_Header->usConnectorObjectTableOffset,
- object_header_end);
-
- if ((object_header_size > handle->BIOSImageSize)
- || (atomDataPtr->Object_Header->usConnectorObjectTableOffset
- > handle->BIOSImageSize)
- || object_header_end > handle->BIOSImageSize) {
- xf86DrvMsg(handle->scrnIndex, X_ERROR,
- "%s: Object table information is bogus\n",__func__);
- return ATOM_FAILED;
- }
-
- if (((unsigned long)&atomDataPtr->Object_Header->sHeader
- + object_header_end) > ((unsigned long)handle->BIOSBase
- + handle->BIOSImageSize)) {
- xf86DrvMsg(handle->scrnIndex, X_ERROR,
- "%s: Object table extends beyond BIOS Image\n",__func__);
- return ATOM_FAILED;
- }
-
- con_obj = (ATOM_CONNECTOR_OBJECT_TABLE *)
- ((char *)&atomDataPtr->Object_Header->sHeader +
- atomDataPtr->Object_Header->usConnectorObjectTableOffset);
-
- for (i = 0; i < con_obj->ucNumberOfObjects; i++) {
- ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *SrcDstTable;
- ATOM_COMMON_RECORD_HEADER *Record;
- int record_base;
- CARD8 obj_type, obj_id, num;
- char *name;
- int nout = 0;
-
- rhdAtomInterpretObjectID(handle, con_obj->asObjects[i].usObjectID,
- &obj_type, &obj_id, &num, &name);
-
- RHDDebug(handle->scrnIndex, "Object: ID: %x name: %s type: %x id: %x\n",
- con_obj->asObjects[i].usObjectID, name ? name : "",
- obj_type, obj_id);
-
-
- if (obj_type != GRAPH_OBJECT_TYPE_CONNECTOR)
- continue;
-
- SrcDstTable = (ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *)
- ((char *)&atomDataPtr->Object_Header->sHeader
- + con_obj->asObjects[i].usSrcDstTableOffset);
-
- if (con_obj->asObjects[i].usSrcDstTableOffset
- + (SrcDstTable->ucNumberOfSrc
- * sizeof(ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT))
- > handle->BIOSImageSize) {
- xf86DrvMsg(handle->scrnIndex, X_ERROR, "%s: SrcDstTable[%i] extends "
- "beyond Object_Header table\n",__func__,i);
- continue;
- }
-
- cp[ncon].Type = rhd_connector_objs[obj_id].con;
- cp[ncon].Name = RhdAppendString(cp[ncon].Name,name);
-
- for (j = 0; j < SrcDstTable->ucNumberOfSrc; j++) {
- CARD8 stype, sobj_id, snum;
- char *sname;
-
- rhdAtomInterpretObjectID(handle, SrcDstTable->usSrcObjectID[j],
- &stype, &sobj_id, &snum, &sname);
-
- RHDDebug(handle->scrnIndex, " * SrcObject: ID: %x name: %s\n",
- SrcDstTable->usSrcObjectID[j], sname);
-
- cp[ncon].Output[nout] = rhd_encoders[sobj_id].ot;
- if (++nout >= MAX_OUTPUTS_PER_CONNECTOR)
- break;
- }
-
- Record = (ATOM_COMMON_RECORD_HEADER *)
- ((char *)&atomDataPtr->Object_Header->sHeader
- + con_obj->asObjects[i].usRecordOffset);
-
- record_base = con_obj->asObjects[i].usRecordOffset;
-
- while (Record->ucRecordType > 0
- && Record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER ) {
- char *taglist;
-
- if ((record_base += Record->ucRecordSize)
- > object_header_size) {
- xf86DrvMsg(handle->scrnIndex, X_ERROR,
- "%s: Object Records extend beyond Object Table\n",
- __func__);
- break;
- }
-
- RHDDebug(handle->scrnIndex, " - Record Type: %x\n",
- Record->ucRecordType);
-
- switch (Record->ucRecordType) {
-
- case ATOM_I2C_RECORD_TYPE:
- rhdAtomDDCFromI2CRecord(handle,
- (ATOM_I2C_RECORD *)Record,
- &cp[ncon].DDC);
- break;
-
- case ATOM_HPD_INT_RECORD_TYPE:
- rhdAtomHPDFromRecord(handle,
- (ATOM_HPD_INT_RECORD *)Record,
- &cp[ncon].HPD);
- break;
-
- case ATOM_CONNECTOR_DEVICE_TAG_RECORD_TYPE:
- taglist = rhdAtomDeviceTagsFromRecord(handle,
- (ATOM_CONNECTOR_DEVICE_TAG_RECORD *)Record);
- if (taglist) {
- cp[ncon].Name = RhdAppendString(cp[ncon].Name,taglist);
- xfree(taglist);
- }
- break;
-
- default:
- break;
- }
-
- Record = (ATOM_COMMON_RECORD_HEADER*)
- ((char *)Record + Record->ucRecordSize);
-
- }
-
- if ((++ncon) == RHD_CONNECTORS_MAX)
- break;
- }
- *ptr = cp;
-
- RhdPrintConnectorInfo(handle->scrnIndex, cp);
-
- return ATOM_SUCCESS;
-}
-
-/*
- *
- */
-static AtomBiosResult
-rhdAtomConnectorInfoFromSupportedDevices(atomBiosHandlePtr handle,
- rhdConnectorInfoPtr *ptr)
-{
- atomDataTablesPtr atomDataPtr;
- CARD8 crev, frev;
- rhdConnectorInfoPtr cp;
- struct {
- rhdOutputType ot;
- rhdConnectorType con;
- rhdDDC ddc;
- rhdHPD hpd;
- Bool dual;
- char *name;
- char *outputName;
- } devices[ATOM_MAX_SUPPORTED_DEVICE];
- int ncon = 0;
- int n;
-
- //RHDFUNC(handle);
-
- atomDataPtr = handle->atomDataPtr;
-
- if (!rhdAtomGetTableRevisionAndSize(
- &(atomDataPtr->SupportedDevicesInfo.SupportedDevicesInfo->sHeader),
- &crev,&frev,NULL)) {
- return ATOM_NOT_IMPLEMENTED;
- }
-
- if (!(cp = (rhdConnectorInfoPtr)xcalloc(RHD_CONNECTORS_MAX,
- sizeof(struct rhdConnectorInfo))))
- return ATOM_FAILED;
-
- for (n = 0; n < ATOM_MAX_SUPPORTED_DEVICE; n++) {
- ATOM_CONNECTOR_INFO_I2C ci
- = atomDataPtr->SupportedDevicesInfo.SupportedDevicesInfo->asConnInfo[n];
-
- devices[n].ot = OUTPUT_NONE_ATOM;
-
- if (!(atomDataPtr->SupportedDevicesInfo
- .SupportedDevicesInfo->usDeviceSupport & (1 << n)))
- continue;
-
- if (Limit(ci.sucConnectorInfo.sbfAccess.bfConnectorType,
- n_rhd_connectors, "bfConnectorType"))
- continue;
-
- devices[n].con
- = rhd_connectors[ci.sucConnectorInfo.sbfAccess.bfConnectorType].con;
- if (devices[n].con == RHD_CONNECTOR_NONE)
- continue;
-
- devices[n].dual
- = rhd_connectors[ci.sucConnectorInfo.sbfAccess.bfConnectorType].dual;
- devices[n].name
- = rhd_connectors[ci.sucConnectorInfo.sbfAccess.bfConnectorType].name;
-
- RHDDebug(handle->scrnIndex,"AtomBIOS Connector[%i]: %s Device:%s ",n,
- rhd_connectors[ci.sucConnectorInfo
- .sbfAccess.bfConnectorType].name,
- rhd_devices[n].name);
-
- devices[n].outputName = rhd_devices[n].name;
-
- if (!Limit(ci.sucConnectorInfo.sbfAccess.bfAssociatedDAC,
- n_acc_dac, "bfAssociatedDAC")) {
- if ((devices[n].ot
- = acc_dac[ci.sucConnectorInfo.sbfAccess.bfAssociatedDAC])
- == OUTPUT_NONE_ATOM) {
- devices[n].ot = rhd_devices[n].ot;
- }
- } else
- devices[n].ot = OUTPUT_NONE_ATOM;
-
- RHDDebugCont("Output: %x ",devices[n].ot);
-
- if (ci.sucI2cId.sbfAccess.bfHW_Capable) {
-
- RHDDebugCont("HW DDC %i ",
- ci.sucI2cId.sbfAccess.bfI2C_LineMux);
-
- if (Limit(ci.sucI2cId.sbfAccess.bfI2C_LineMux,
- n_hwddc, "bfI2C_LineMux"))
- devices[n].ddc = RHD_DDC_NONE;
- else
- devices[n].ddc = hwddc[ci.sucI2cId.sbfAccess.bfI2C_LineMux];
-
- } else if (ci.sucI2cId.sbfAccess.bfI2C_LineMux) {
-
- RHDDebugCont("GPIO DDC ");
- devices[n].ddc = RHD_DDC_GPIO;
-
- /* add support for GPIO line */
- } else {
-
- RHDDebugCont("NO DDC ");
- devices[n].ddc = RHD_DDC_NONE;
-
- }
-
- if (crev > 1) {
- ATOM_CONNECTOR_INC_SRC_BITMAP isb
- = atomDataPtr->SupportedDevicesInfo
- .SupportedDevicesInfo_HD->asIntSrcInfo[n];
-
- switch (isb.ucIntSrcBitmap) {
- case 0x4:
- RHDDebugCont("HPD 0\n");
- devices[n].hpd = RHD_HPD_0;
- break;
- case 0xa:
- RHDDebugCont("HPD 1\n");
- devices[n].hpd = RHD_HPD_1;
- break;
- default:
- RHDDebugCont("NO HPD\n");
- devices[n].hpd = RHD_HPD_NONE;
- break;
- }
- } else {
- RHDDebugCont("NO HPD\n");
- devices[n].hpd = RHD_HPD_NONE;
- }
- }
- /* sort devices for connectors */
- for (n = 0; n < ATOM_MAX_SUPPORTED_DEVICE; n++) {
- int i;
-
- if (devices[n].ot == OUTPUT_NONE_ATOM)
- continue;
- if (devices[n].con == CONNECTOR_NONE_ATOM)
- continue;
-
- cp[ncon].DDC = devices[n].ddc;
- cp[ncon].HPD = devices[n].hpd;
- cp[ncon].Output[0] = devices[n].ot;
- cp[ncon].Output[1] = OUTPUT_NONE_ATOM;
- cp[ncon].Type = devices[n].con;
- cp[ncon].Name = xf86strdup(devices[n].name);
- cp[ncon].Name = RhdAppendString(cp[ncon].Name, devices[n].outputName);
-
- if (devices[n].dual) {
- if (devices[n].ddc == RHD_DDC_NONE)
- xf86DrvMsg(handle->scrnIndex, X_ERROR,
- "No DDC channel for device %s found."
- " Cannot find matching device.\n",devices[n].name);
- else {
- for (i = n + 1; i < ATOM_MAX_SUPPORTED_DEVICE; i++) {
-
- if (!devices[i].dual)
- continue;
-
- if (devices[n].ddc != devices[i].ddc)
- continue;
-
- if (((devices[n].ot == OUTPUT_DACA_ATOM
- || devices[n].ot == OUTPUT_DACB_ATOM)
- && (devices[i].ot == OUTPUT_LVTMA_ATOM
- || devices[i].ot == OUTPUT_TMDSA_ATOM))
- || ((devices[i].ot == OUTPUT_DACA_ATOM
- || devices[i].ot == OUTPUT_DACB_ATOM)
- && (devices[n].ot == OUTPUT_LVTMA_ATOM
- || devices[n].ot == OUTPUT_TMDSA_ATOM))) {
-
- cp[ncon].Output[1] = devices[i].ot;
-
- if (cp[ncon].HPD == RHD_HPD_NONE)
- cp[ncon].HPD = devices[i].hpd;
-
- cp[ncon].Name = RhdAppendString(cp[ncon].Name,
- devices[i].outputName);
- devices[i].ot = OUTPUT_NONE_ATOM; /* zero the device */
- }
- }
- }
- }
-
- if ((++ncon) == RHD_CONNECTORS_MAX)
- break;
- }
- *ptr = cp;
-
- RhdPrintConnectorInfo(handle->scrnIndex, cp);
-
- return ATOM_SUCCESS;
-}
-
-/*
- *
- */
-static AtomBiosResult
-rhdAtomConnectorInfo(atomBiosHandlePtr handle,
- AtomBiosRequestID unused, AtomBiosArgPtr data)
-{
- data->connectorInfo = NULL;
-
- if (rhdAtomConnectorInfoFromObjectHeader(handle,&data->connectorInfo)
- == ATOM_SUCCESS)
- return ATOM_SUCCESS;
- else
- return rhdAtomConnectorInfoFromSupportedDevices(handle,
- &data->connectorInfo);
-}
-#endif
-
# ifdef ATOM_BIOS_PARSER
static AtomBiosResult
rhdAtomExec (atomBiosHandlePtr handle,
diff --git a/src/radeon_atomwrapper.c b/src/radeon_atomwrapper.c
index 259366c..3e7ae01 100644
--- a/src/radeon_atomwrapper.c
+++ b/src/radeon_atomwrapper.c
@@ -27,7 +27,7 @@
# include "config.h"
#endif
-//#include "radeon_atomwrapper.h"
+#include "radeon_atomwrapper.h"
#define INT32 INT32
#include "CD_Common_Types.h"
diff --git a/src/radeon_chipinfo_gen.h b/src/radeon_chipinfo_gen.h
index c80802a..de1d109 100644
--- a/src/radeon_chipinfo_gen.h
+++ b/src/radeon_chipinfo_gen.h
@@ -106,7 +106,7 @@ RADEONCardInfo RADEONCards[] = {
{ 0x5964, CHIP_FAMILY_RV280, 0, 0, 0, 0, 0 },
{ 0x5965, CHIP_FAMILY_RV280, 0, 0, 0, 0, 0 },
{ 0x5969, CHIP_FAMILY_RV100, 0, 0, 1, 0, 0 },
- { 0x5974, CHIP_FAMILY_RS400, 0, 1, 0, 0, 1 },
+ { 0x5974, CHIP_FAMILY_RS400, 1, 1, 0, 0, 1 },
{ 0x5975, CHIP_FAMILY_RS400, 1, 1, 0, 0, 1 },
{ 0x5A41, CHIP_FAMILY_RS400, 0, 1, 0, 0, 1 },
{ 0x5A42, CHIP_FAMILY_RS400, 1, 1, 0, 0, 1 },
@@ -201,9 +201,9 @@ RADEONCardInfo RADEONCards[] = {
{ 0x71D6, CHIP_FAMILY_RV530, 1, 0, 0, 0, 0 },
{ 0x71DA, CHIP_FAMILY_RV530, 0, 0, 0, 0, 0 },
{ 0x71DE, CHIP_FAMILY_RV530, 1, 0, 0, 0, 0 },
- { 0x7200, CHIP_FAMILY_RV530, 0, 0, 0, 0, 0 },
- { 0x7210, CHIP_FAMILY_RV530, 1, 0, 0, 0, 0 },
- { 0x7211, CHIP_FAMILY_RV530, 1, 0, 0, 0, 0 },
+ { 0x7200, CHIP_FAMILY_RV515, 0, 0, 0, 0, 0 },
+ { 0x7210, CHIP_FAMILY_RV515, 1, 0, 0, 0, 0 },
+ { 0x7211, CHIP_FAMILY_RV515, 1, 0, 0, 0, 0 },
{ 0x7240, CHIP_FAMILY_R580, 0, 0, 0, 0, 0 },
{ 0x7243, CHIP_FAMILY_R580, 0, 0, 0, 0, 0 },
{ 0x7244, CHIP_FAMILY_R580, 0, 0, 0, 0, 0 },
diff --git a/src/radeon_chipset_gen.h b/src/radeon_chipset_gen.h
index 61f8da7..b668823 100644
--- a/src/radeon_chipset_gen.h
+++ b/src/radeon_chipset_gen.h
@@ -201,9 +201,9 @@ static SymTabRec RADEONChipsets[] = {
{ PCI_CHIP_RV530_71D6, "ATI Mobility Radeon X1700 XT" },
{ PCI_CHIP_RV530_71DA, "ATI FireGL V5200" },
{ PCI_CHIP_RV530_71DE, "ATI Mobility Radeon X1700" },
- { PCI_CHIP_RV530_7200, "ATI Radeon X2300HD" },
- { PCI_CHIP_RV530_7210, "ATI Mobility Radeon HD 2300" },
- { PCI_CHIP_RV530_7211, "ATI Mobility Radeon HD 2300" },
+ { PCI_CHIP_RV515_7200, "ATI Radeon X2300HD" },
+ { PCI_CHIP_RV515_7210, "ATI Mobility Radeon HD 2300" },
+ { PCI_CHIP_RV515_7211, "ATI Mobility Radeon HD 2300" },
{ PCI_CHIP_R580_7240, "ATI Radeon X1950" },
{ PCI_CHIP_R580_7243, "ATI Radeon X1900" },
{ PCI_CHIP_R580_7244, "ATI Radeon X1950" },
diff --git a/src/radeon_crtc.c b/src/radeon_crtc.c
index 87514b0..e2d31eb 100644
--- a/src/radeon_crtc.c
+++ b/src/radeon_crtc.c
@@ -57,12 +57,7 @@ extern void atombios_crtc_mode_set(xf86CrtcPtr crtc,
DisplayModePtr mode,
DisplayModePtr adjusted_mode,
int x, int y);
-extern void legacy_crtc_mode_set(xf86CrtcPtr crtc,
- DisplayModePtr mode,
- DisplayModePtr adjusted_mode,
- int x, int y);
extern void atombios_crtc_dpms(xf86CrtcPtr crtc, int mode);
-extern void legacy_crtc_dpms(xf86CrtcPtr crtc, int mode);
static void
radeon_crtc_dpms(xf86CrtcPtr crtc, int mode)
@@ -190,8 +185,10 @@ RADEONComputePLL(RADEONPLLPtr pll,
best_vco_diff = vco_diff;
}
}
- if (best_freq == freq)
- break;
+ if (!(flags & RADEON_PLL_DCE3)) {
+ if (best_freq == freq)
+ break;
+ }
}
ErrorF("best_freq: %u\n", (unsigned int)best_freq);
diff --git a/src/radeon_cursor.c b/src/radeon_cursor.c
index 0f7e668..de64dee 100644
--- a/src/radeon_cursor.c
+++ b/src/radeon_cursor.c
@@ -346,14 +346,6 @@ Bool RADEONCursorInit(ScreenPtr pScreen)
return xf86_cursors_init (pScreen, CURSOR_WIDTH, CURSOR_HEIGHT,
(HARDWARE_CURSOR_TRUECOLOR_AT_8BPP |
-#if X_BYTE_ORDER == X_BIG_ENDIAN
- /* this is a lie --
- * HARDWARE_CURSOR_BIT_ORDER_MSBFIRST
- * actually inverts the bit order, so
- * this switches to LSBFIRST
- */
- HARDWARE_CURSOR_BIT_ORDER_MSBFIRST |
-#endif
HARDWARE_CURSOR_AND_SOURCE_WITH_MASK |
HARDWARE_CURSOR_SOURCE_MASK_INTERLEAVE_1 |
HARDWARE_CURSOR_ARGB));
diff --git a/src/radeon_driver.c b/src/radeon_driver.c
index de81b2d..3d33d47 100644
--- a/src/radeon_driver.c
+++ b/src/radeon_driver.c
@@ -128,35 +128,6 @@ static void RADEONAdjustMemMapRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save);
static void
RADEONRestoreMemMapRegisters(ScrnInfoPtr pScrn, RADEONSavePtr restore);
-extern DisplayModePtr
-RADEONCrtcFindClosestMode(xf86CrtcPtr crtc, DisplayModePtr pMode);
-
-extern void
-RADEONSaveCommonRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save);
-extern void
-RADEONSaveCrtcRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save);
-extern void
-RADEONSaveCrtc2Registers(ScrnInfoPtr pScrn, RADEONSavePtr save);
-extern void
-RADEONSavePLLRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save);
-extern void
-RADEONSavePLL2Registers(ScrnInfoPtr pScrn, RADEONSavePtr save);
-extern void
-RADEONSaveFPRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save);
-extern void
-RADEONSaveDACRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save);
-extern void
-RADEONSaveTVRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save);
-
-#ifdef USE_XAA
-#ifdef XF86DRI
-extern Bool
-RADEONSetupMemXAA_DRI(int scrnIndex, ScreenPtr pScreen);
-#endif /* XF86DRI */
-extern Bool
-RADEONSetupMemXAA(int scrnIndex, ScreenPtr pScreen);
-#endif /* USE_XAA */
-
static const OptionInfoRec RADEONOptions[] = {
{ OPTION_NOACCEL, "NoAccel", OPTV_BOOLEAN, {0}, FALSE },
{ OPTION_SW_CURSOR, "SWcursor", OPTV_BOOLEAN, {0}, FALSE },
@@ -440,6 +411,9 @@ static Bool RADEONUnmapMMIO(ScrnInfoPtr pScrn)
/* Memory map the frame buffer. Used by RADEONMapMem, below. */
static Bool RADEONMapFB(ScrnInfoPtr pScrn)
{
+#ifdef XSERVER_LIBPCIACCESS
+ int err;
+#endif
RADEONInfoPtr info = RADEONPTR(pScrn);
xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
@@ -457,7 +431,7 @@ static Bool RADEONMapFB(ScrnInfoPtr pScrn)
#else
- int err = pci_device_map_range(info->PciInfo,
+ err = pci_device_map_range(info->PciInfo,
info->LinearAddr,
info->FbMapSize,
PCI_DEV_MAP_FLAG_WRITABLE |
@@ -637,7 +611,7 @@ void RADEONOUTMC(ScrnInfoPtr pScrn, int addr, CARD32 data)
}
}
-Bool avivo_get_mc_idle(ScrnInfoPtr pScrn)
+static Bool avivo_get_mc_idle(ScrnInfoPtr pScrn)
{
RADEONInfoPtr info = RADEONPTR(pScrn);
@@ -665,7 +639,7 @@ Bool avivo_get_mc_idle(ScrnInfoPtr pScrn)
#define LOC_FB 0x1
#define LOC_AGP 0x2
-void radeon_write_mc_fb_agp_location(ScrnInfoPtr pScrn, int mask, CARD32 fb_loc, CARD32 agp_loc, CARD32 agp_loc_hi)
+static void radeon_write_mc_fb_agp_location(ScrnInfoPtr pScrn, int mask, CARD32 fb_loc, CARD32 agp_loc, CARD32 agp_loc_hi)
{
RADEONInfoPtr info = RADEONPTR(pScrn);
unsigned char *RADEONMMIO = info->MMIO;
@@ -703,7 +677,7 @@ void radeon_write_mc_fb_agp_location(ScrnInfoPtr pScrn, int mask, CARD32 fb_loc,
}
}
-void radeon_read_mc_fb_agp_location(ScrnInfoPtr pScrn, int mask, CARD32 *fb_loc, CARD32 *agp_loc, CARD32 *agp_loc_hi)
+static void radeon_read_mc_fb_agp_location(ScrnInfoPtr pScrn, int mask, CARD32 *fb_loc, CARD32 *agp_loc, CARD32 *agp_loc_hi)
{
RADEONInfoPtr info = RADEONPTR(pScrn);
unsigned char *RADEONMMIO = info->MMIO;
@@ -3143,12 +3117,14 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen,
RADEONRestoreMemMapRegisters(pScrn, info->ModeReg);
/* empty the surfaces */
- unsigned char *RADEONMMIO = info->MMIO;
- unsigned int j;
- for (j = 0; j < 8; j++) {
- OUTREG(RADEON_SURFACE0_INFO + 16 * j, 0);
- OUTREG(RADEON_SURFACE0_LOWER_BOUND + 16 * j, 0);
- OUTREG(RADEON_SURFACE0_UPPER_BOUND + 16 * j, 0);
+ {
+ unsigned char *RADEONMMIO = info->MMIO;
+ unsigned int j;
+ for (j = 0; j < 8; j++) {
+ OUTREG(RADEON_SURFACE0_INFO + 16 * j, 0);
+ OUTREG(RADEON_SURFACE0_LOWER_BOUND + 16 * j, 0);
+ OUTREG(RADEON_SURFACE0_UPPER_BOUND + 16 * j, 0);
+ }
}
#ifdef XF86DRI
@@ -3745,7 +3721,7 @@ static void RADEONAdjustMemMapRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save)
{
RADEONInfoPtr info = RADEONPTR(pScrn);
CARD32 fb, agp, agp_hi;
- int changed;
+ int changed = 0;
if (info->IsSecondary)
return;
@@ -3753,7 +3729,7 @@ static void RADEONAdjustMemMapRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save)
radeon_read_mc_fb_agp_location(pScrn, LOC_FB | LOC_AGP, &fb, &agp, &agp_hi);
if (fb != save->mc_fb_location || agp != save->mc_agp_location ||
- agp_hi || save->mc_agp_location_hi)
+ agp_hi != save->mc_agp_location_hi)
changed = 1;
if (changed) {
@@ -4031,7 +4007,7 @@ static void RADEONSavePalette(ScrnInfoPtr pScrn, RADEONSavePtr save)
}
#endif
-void
+static void
avivo_save(ScrnInfoPtr pScrn, RADEONSavePtr save)
{
RADEONInfoPtr info = RADEONPTR(pScrn);
@@ -4336,7 +4312,7 @@ avivo_save(ScrnInfoPtr pScrn, RADEONSavePtr save)
}
-void
+static void
avivo_restore(ScrnInfoPtr pScrn, RADEONSavePtr restore)
{
RADEONInfoPtr info = RADEONPTR(pScrn);
@@ -4636,7 +4612,7 @@ avivo_restore(ScrnInfoPtr pScrn, RADEONSavePtr restore)
OUTREG(AVIVO_D2VGA_CONTROL, state->vga2_cntl);
}
-void avivo_restore_vga_regs(ScrnInfoPtr pScrn, RADEONSavePtr restore)
+static void avivo_restore_vga_regs(ScrnInfoPtr pScrn, RADEONSavePtr restore)
{
RADEONInfoPtr info = RADEONPTR(pScrn);
unsigned char *RADEONMMIO = info->MMIO;
@@ -4760,7 +4736,7 @@ static void RADEONSave(ScrnInfoPtr pScrn)
}
/* Restore the original (text) mode */
-void RADEONRestore(ScrnInfoPtr pScrn)
+static void RADEONRestore(ScrnInfoPtr pScrn)
{
RADEONInfoPtr info = RADEONPTR(pScrn);
RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn);
@@ -5208,6 +5184,12 @@ Bool RADEONEnterVT(int scrnIndex, int flags)
pScrn->vtSema = TRUE;
+ RADEONRestoreMemMapRegisters(pScrn, info->ModeReg);
+ RADEONRestoreSurfaces(pScrn, info->ModeReg);
+
+ if (!xf86SetDesiredModes(pScrn))
+ return FALSE;
+
#ifdef XF86DRI
if (info->directRenderingEnabled) {
if (info->cardType == CARD_PCIE &&
@@ -5222,14 +5204,8 @@ Bool RADEONEnterVT(int scrnIndex, int flags)
RADEONDRIResume(pScrn->pScreen);
RADEONAdjustMemMapRegisters(pScrn, info->ModeReg);
- } else
+ }
#endif
- RADEONRestoreMemMapRegisters(pScrn, info->ModeReg);
-
- RADEONRestoreSurfaces(pScrn, info->ModeReg);
-
- if (!xf86SetDesiredModes(pScrn))
- return FALSE;
/* this will get XVideo going again, but only if XVideo was initialised
during server startup (hence the info->adaptor if). */
diff --git a/src/radeon_exa.c b/src/radeon_exa.c
index 4da4841..a6ededa 100644
--- a/src/radeon_exa.c
+++ b/src/radeon_exa.c
@@ -99,10 +99,17 @@ static __inline__ int
RADEONLog2(int val)
{
int bits;
-
+#if (defined __i386__ || defined __x86_64__) && (defined __GNUC__)
+ __asm volatile("bsrl %1, %0"
+ : "=r" (bits)
+ : "c" (val)
+ );
+ return bits;
+#else
for (bits = 0; val != 0; val >>= 1, ++bits)
;
return bits - 1;
+#endif
}
static __inline__ CARD32 F_TO_DW(float val)
diff --git a/src/radeon_exa_funcs.c b/src/radeon_exa_funcs.c
index 84beec3..d5ee5a6 100644
--- a/src/radeon_exa_funcs.c
+++ b/src/radeon_exa_funcs.c
@@ -536,9 +536,9 @@ Bool FUNC_NAME(RADEONDrawInit)(ScreenPtr pScreen)
if (info->ChipFamily >= CHIP_FAMILY_R600)
xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Render acceleration "
"unsupported on R600 and newer cards.\n");
- else if (IS_R300_VARIANT || (IS_AVIVO_VARIANT && info->ChipFamily <= CHIP_FAMILY_RS740)) {
+ else if (IS_R300_3D || IS_R500_3D) {
xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Render acceleration "
- "enabled for R300 type cards.\n");
+ "enabled for R300/R400/R500 type cards.\n");
info->exa->CheckComposite = R300CheckComposite;
info->exa->PrepareComposite =
FUNC_NAME(R300PrepareComposite);
diff --git a/src/radeon_exa_render.c b/src/radeon_exa_render.c
index 4410cf5..707e9fc 100644
--- a/src/radeon_exa_render.c
+++ b/src/radeon_exa_render.c
@@ -177,9 +177,8 @@ static Bool R300GetDestFormat(PicturePtr pDstPicture, CARD32 *dst_format)
*dst_format = R300_COLORFORMAT_I8;
break;
default:
- ErrorF("Unsupported dest format 0x%x\n",
- (int)pDstPicture->format);
- return FALSE;
+ RADEON_FALLBACK(("Unsupported dest format 0x%x\n",
+ (int)pDstPicture->format));
}
return TRUE;
}
@@ -346,7 +345,7 @@ RADEONGetDrawablePixmap(DrawablePtr pDrawable)
return pDrawable->pScreen->GetWindowPixmap((WindowPtr)pDrawable);
else
return (PixmapPtr)pDrawable;
-}
+}
static Bool R100CheckComposite(int op, PicturePtr pSrcPicture,
PicturePtr pMaskPicture, PicturePtr pDstPicture)
@@ -435,7 +434,9 @@ static Bool FUNC_NAME(R100PrepareComposite)(int op,
if (!info->XInited3D)
RADEONInit3DEngine(pScrn);
- RADEONGetDestFormat(pDstPicture, &dst_format);
+ if (!RADEONGetDestFormat(pDstPicture, &dst_format))
+ return FALSE;
+
pixel_shift = pDst->drawable.bitsPerPixel >> 4;
dst_offset = exaGetPixmapOffset(pDst) + info->fbLocation;
@@ -567,7 +568,7 @@ static Bool FUNC_NAME(R200TextureSetup)(PicturePtr pPict, PixmapPtr pPix,
RADEON_FALLBACK(("Bad texture offset 0x%x\n", (int)txoffset));
if ((txpitch & 0x1f) != 0)
RADEON_FALLBACK(("Bad texture pitch 0x%x\n", (int)txpitch));
-
+
for (i = 0; i < sizeof(R200TexFormats) / sizeof(R200TexFormats[0]); i++)
{
if (R200TexFormats[i].fmt == pPict->format)
@@ -717,7 +718,9 @@ static Bool FUNC_NAME(R200PrepareComposite)(int op, PicturePtr pSrcPicture,
if (!info->XInited3D)
RADEONInit3DEngine(pScrn);
- RADEONGetDestFormat(pDstPicture, &dst_format);
+ if (!RADEONGetDestFormat(pDstPicture, &dst_format))
+ return FALSE;
+
pixel_shift = pDst->drawable.bitsPerPixel >> 4;
dst_offset = exaGetPixmapOffset(pDst) + info->fbLocation;
@@ -808,13 +811,22 @@ static Bool FUNC_NAME(R200PrepareComposite)(int op, PicturePtr pSrcPicture,
#ifdef ONLY_ONCE
-static Bool R300CheckCompositeTexture(PicturePtr pPict, int unit)
+static Bool R300CheckCompositeTexture(PicturePtr pPict, int unit, Bool is_r500)
{
int w = pPict->pDrawable->width;
int h = pPict->pDrawable->height;
int i;
+ int max_tex_w, max_tex_h;
- if ((w > 0x7ff) || (h > 0x7ff))
+ if (is_r500) {
+ max_tex_w = 4096;
+ max_tex_h = 4096;
+ } else {
+ max_tex_w = 2048;
+ max_tex_h = 2048;
+ }
+
+ if ((w > max_tex_w) || (h > max_tex_h))
RADEON_FALLBACK(("Picture w/h too large (%dx%d)\n", w, h));
for (i = 0; i < sizeof(R300TexFormats) / sizeof(R300TexFormats[0]); i++)
@@ -873,11 +885,16 @@ static Bool FUNC_NAME(R300TextureSetup)(PicturePtr pPict, PixmapPtr pPix,
txformat1 = R300TexFormats[i].card_fmt;
- txformat0 = (((w - 1) << R300_TXWIDTH_SHIFT) |
- ((h - 1) << R300_TXHEIGHT_SHIFT));
+ txformat0 = ((((w - 1) & 0x7ff) << R300_TXWIDTH_SHIFT) |
+ (((h - 1) & 0x7ff) << R300_TXHEIGHT_SHIFT));
+
+ if (IS_R500_3D && ((w - 1) & 0x800))
+ txpitch |= R500_TXWIDTH_11;
+
+ if (IS_R500_3D && ((h - 1) & 0x800))
+ txpitch |= R500_TXHEIGHT_11;
if (pPict->repeat) {
- ErrorF("repeat\n");
if ((h != 1) &&
(((w * pPix->drawable.bitsPerPixel / 8 + 31) & ~31) != txpitch))
RADEON_FALLBACK(("Width %d and pitch %u not compatible for repeat\n",
@@ -892,6 +909,8 @@ static Bool FUNC_NAME(R300TextureSetup)(PicturePtr pPict, PixmapPtr pPix,
txfilter = (R300_TX_CLAMP_S(R300_TX_CLAMP_CLAMP_LAST) |
R300_TX_CLAMP_T(R300_TX_CLAMP_CLAMP_LAST));
+ txfilter |= (unit << R300_TX_ID_SHIFT);
+
switch (pPict->filter) {
case PictFilterNearest:
txfilter |= (R300_TX_MAG_FILTER_NEAREST | R300_TX_MIN_FILTER_NEAREST);
@@ -905,7 +924,7 @@ static Bool FUNC_NAME(R300TextureSetup)(PicturePtr pPict, PixmapPtr pPix,
BEGIN_ACCEL(6);
OUT_ACCEL_REG(R300_TX_FILTER0_0 + (unit * 4), txfilter);
- OUT_ACCEL_REG(R300_TX_FILTER1_0 + (unit * 4), 0x0);
+ OUT_ACCEL_REG(R300_TX_FILTER1_0 + (unit * 4), 0);
OUT_ACCEL_REG(R300_TX_FORMAT0_0 + (unit * 4), txformat0);
OUT_ACCEL_REG(R300_TX_FORMAT1_0 + (unit * 4), txformat1);
OUT_ACCEL_REG(R300_TX_FORMAT2_0 + (unit * 4), txpitch);
@@ -931,8 +950,8 @@ static Bool R300CheckComposite(int op, PicturePtr pSrcPicture, PicturePtr pMaskP
ScreenPtr pScreen = pDstPicture->pDrawable->pScreen;
PixmapPtr pSrcPixmap, pDstPixmap;
ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum];
- xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
- int i;
+ RADEONInfoPtr info = RADEONPTR(pScrn);
+ int max_tex_w, max_tex_h, max_dst_w, max_dst_h;
TRACE;
@@ -940,39 +959,22 @@ static Bool R300CheckComposite(int op, PicturePtr pSrcPicture, PicturePtr pMaskP
if (op >= sizeof(RadeonBlendOp) / sizeof(RadeonBlendOp[0]))
RADEON_FALLBACK(("Unsupported Composite op 0x%x\n", op));
-#if 1
- /* Throw out cases that aren't going to be our rotation first */
- if (pMaskPicture != NULL || op != PictOpSrc || pSrcPicture->pDrawable == NULL)
- RADEON_FALLBACK(("Junk driver\n"));
-
- if (pSrcPicture->pDrawable->type != DRAWABLE_WINDOW ||
- pDstPicture->pDrawable->type != DRAWABLE_PIXMAP) {
- RADEON_FALLBACK(("bad drawable\n"));
- }
-
- pSrcPixmap = (*pScreen->GetWindowPixmap) ((WindowPtr) pSrcPicture->pDrawable);
- pDstPixmap = (PixmapPtr)pDstPicture->pDrawable;
-
- /* Check if the dest is one of our shadow pixmaps */
- for (i = 0; i < xf86_config->num_crtc; i++) {
- xf86CrtcPtr crtc = xf86_config->crtc[i];
+ pSrcPixmap = RADEONGetDrawablePixmap(pSrcPicture->pDrawable);
- if (crtc->rotatedPixmap == pDstPixmap)
- break;
+ if (IS_R500_3D) {
+ max_tex_w = 4096;
+ max_tex_h = 4096;
+ max_dst_w = 4096;
+ max_dst_h = 4096;
+ } else {
+ max_tex_w = 2048;
+ max_tex_h = 2048;
+ max_dst_w = 2560;
+ max_dst_h = 2560;
}
- if (i == xf86_config->num_crtc)
- RADEON_FALLBACK(("no rotated pixmap\n"));
-
- if (pSrcPixmap != pScreen->GetScreenPixmap(pScreen))
- RADEON_FALLBACK(("src not screen\n"));
-#endif
-
- pSrcPixmap = RADEONGetDrawablePixmap(pSrcPicture->pDrawable);
- /* XXX: R(V)5xx may have higher limits
- */
- if (pSrcPixmap->drawable.width >= 2048 ||
- pSrcPixmap->drawable.height >= 2048) {
+ if (pSrcPixmap->drawable.width >= max_tex_w ||
+ pSrcPixmap->drawable.height >= max_tex_h) {
RADEON_FALLBACK(("Source w/h too large (%d,%d).\n",
pSrcPixmap->drawable.width,
pSrcPixmap->drawable.height));
@@ -980,8 +982,8 @@ static Bool R300CheckComposite(int op, PicturePtr pSrcPicture, PicturePtr pMaskP
pDstPixmap = RADEONGetDrawablePixmap(pDstPicture->pDrawable);
- if (pDstPixmap->drawable.width >= 2560 ||
- pDstPixmap->drawable.height >= 2560) {
+ if (pDstPixmap->drawable.width >= max_dst_w ||
+ pDstPixmap->drawable.height >= max_dst_h) {
RADEON_FALLBACK(("Dest w/h too large (%d,%d).\n",
pDstPixmap->drawable.width,
pDstPixmap->drawable.height));
@@ -990,8 +992,8 @@ static Bool R300CheckComposite(int op, PicturePtr pSrcPicture, PicturePtr pMaskP
if (pMaskPicture) {
PixmapPtr pMaskPixmap = RADEONGetDrawablePixmap(pMaskPicture->pDrawable);
- if (pMaskPixmap->drawable.width >= 2048 ||
- pMaskPixmap->drawable.height >= 2048) {
+ if (pMaskPixmap->drawable.width >= max_tex_w ||
+ pMaskPixmap->drawable.height >= max_tex_h) {
RADEON_FALLBACK(("Mask w/h too large (%d,%d).\n",
pMaskPixmap->drawable.width,
pMaskPixmap->drawable.height));
@@ -1010,11 +1012,11 @@ static Bool R300CheckComposite(int op, PicturePtr pSrcPicture, PicturePtr pMaskP
}
}
- if (!R300CheckCompositeTexture(pMaskPicture, 1))
+ if (!R300CheckCompositeTexture(pMaskPicture, 1, IS_R500_3D))
return FALSE;
}
- if (!R300CheckCompositeTexture(pSrcPicture, 0))
+ if (!R300CheckCompositeTexture(pSrcPicture, 0, IS_R500_3D))
return FALSE;
if (!R300GetDestFormat(pDstPicture, &tmp1))
@@ -1036,7 +1038,8 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture,
int pixel_shift;
int has_tcl = ((info->ChipFamily != CHIP_FAMILY_RS690) &&
(info->ChipFamily != CHIP_FAMILY_RS740) &&
- (info->ChipFamily != CHIP_FAMILY_RS400));
+ (info->ChipFamily != CHIP_FAMILY_RS400) &&
+ (info->ChipFamily != CHIP_FAMILY_RV515));
ACCEL_PREAMBLE();
TRACE;
@@ -1044,7 +1047,9 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture,
if (!info->XInited3D)
RADEONInit3DEngine(pScrn);
- R300GetDestFormat(pDstPicture, &dst_format);
+ if (!R300GetDestFormat(pDstPicture, &dst_format))
+ return FALSE;
+
pixel_shift = pDst->drawable.bitsPerPixel >> 4;
dst_offset = exaGetPixmapOffset(pDst) + info->fbLocation;
@@ -1076,9 +1081,8 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture,
RADEON_SWITCH_TO_3D();
/* setup the VAP */
-
if (has_tcl) {
- BEGIN_ACCEL(28);
+ BEGIN_ACCEL(9);
OUT_ACCEL_REG(R300_VAP_CNTL_STATUS, 0);
OUT_ACCEL_REG(R300_VAP_PVS_STATE_FLUSH_REG, 0);
OUT_ACCEL_REG(R300_VAP_CNTL, ((6 << R300_PVS_NUM_SLOTS_SHIFT) |
@@ -1086,7 +1090,7 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture,
(4 << R300_PVS_NUM_FPUS_SHIFT) |
(12 << R300_VF_MAX_VTX_NUM_SHIFT)));
} else {
- BEGIN_ACCEL(10);
+ BEGIN_ACCEL(8);
OUT_ACCEL_REG(R300_VAP_CNTL_STATUS, R300_PVS_BYPASS);
OUT_ACCEL_REG(R300_VAP_CNTL, ((10 << R300_PVS_NUM_SLOTS_SHIFT) |
(5 << R300_PVS_NUM_CNTLRS_SHIFT) |
@@ -1105,32 +1109,32 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture,
R300_SIGNED_0 |
(R300_DATA_TYPE_FLOAT_2 << R300_DATA_TYPE_1_SHIFT) |
(0 << R300_SKIP_DWORDS_1_SHIFT) |
- (10 << R300_DST_VEC_LOC_1_SHIFT) |
+ (1 << R300_DST_VEC_LOC_1_SHIFT) |
R300_SIGNED_1));
OUT_ACCEL_REG(R300_VAP_PROG_STREAM_CNTL_1,
((R300_DATA_TYPE_FLOAT_2 << R300_DATA_TYPE_2_SHIFT) |
(0 << R300_SKIP_DWORDS_2_SHIFT) |
- (11 << R300_DST_VEC_LOC_2_SHIFT) |
+ (2 << R300_DST_VEC_LOC_2_SHIFT) |
R300_LAST_VEC_2 |
R300_SIGNED_2));
OUT_ACCEL_REG(R300_VAP_PROG_STREAM_CNTL_EXT_0,
((R300_SWIZZLE_SELECT_X << R300_SWIZZLE_SELECT_X_0_SHIFT) |
(R300_SWIZZLE_SELECT_Y << R300_SWIZZLE_SELECT_Y_0_SHIFT) |
- (R300_SWIZZLE_SELECT_Z << R300_SWIZZLE_SELECT_Z_0_SHIFT) |
- (R300_SWIZZLE_SELECT_W << R300_SWIZZLE_SELECT_W_0_SHIFT) |
+ (R300_SWIZZLE_SELECT_FP_ZERO << R300_SWIZZLE_SELECT_Z_0_SHIFT) |
+ (R300_SWIZZLE_SELECT_FP_ONE << R300_SWIZZLE_SELECT_W_0_SHIFT) |
((R300_WRITE_ENA_X | R300_WRITE_ENA_Y | R300_WRITE_ENA_Z | R300_WRITE_ENA_W)
<< R300_WRITE_ENA_0_SHIFT) |
(R300_SWIZZLE_SELECT_X << R300_SWIZZLE_SELECT_X_1_SHIFT) |
(R300_SWIZZLE_SELECT_Y << R300_SWIZZLE_SELECT_Y_1_SHIFT) |
- (R300_SWIZZLE_SELECT_Z << R300_SWIZZLE_SELECT_Z_1_SHIFT) |
- (R300_SWIZZLE_SELECT_W << R300_SWIZZLE_SELECT_W_1_SHIFT) |
+ (R300_SWIZZLE_SELECT_FP_ZERO << R300_SWIZZLE_SELECT_Z_1_SHIFT) |
+ (R300_SWIZZLE_SELECT_FP_ONE << R300_SWIZZLE_SELECT_W_1_SHIFT) |
((R300_WRITE_ENA_X | R300_WRITE_ENA_Y | R300_WRITE_ENA_Z | R300_WRITE_ENA_W)
<< R300_WRITE_ENA_1_SHIFT)));
OUT_ACCEL_REG(R300_VAP_PROG_STREAM_CNTL_EXT_1,
((R300_SWIZZLE_SELECT_X << R300_SWIZZLE_SELECT_X_2_SHIFT) |
(R300_SWIZZLE_SELECT_Y << R300_SWIZZLE_SELECT_Y_2_SHIFT) |
- (R300_SWIZZLE_SELECT_Z << R300_SWIZZLE_SELECT_Z_2_SHIFT) |
- (R300_SWIZZLE_SELECT_W << R300_SWIZZLE_SELECT_W_2_SHIFT) |
+ (R300_SWIZZLE_SELECT_FP_ZERO << R300_SWIZZLE_SELECT_Z_2_SHIFT) |
+ (R300_SWIZZLE_SELECT_FP_ONE << R300_SWIZZLE_SELECT_W_2_SHIFT) |
((R300_WRITE_ENA_X | R300_WRITE_ENA_Y | R300_WRITE_ENA_Z | R300_WRITE_ENA_W)
<< R300_WRITE_ENA_2_SHIFT)));
} else {
@@ -1154,40 +1158,138 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture,
(R300_SWIZZLE_SELECT_Y << R300_SWIZZLE_SELECT_Y_0_SHIFT) |
(R300_SWIZZLE_SELECT_FP_ZERO << R300_SWIZZLE_SELECT_Z_0_SHIFT) |
(R300_SWIZZLE_SELECT_FP_ONE << R300_SWIZZLE_SELECT_W_0_SHIFT) |
- ((R300_WRITE_ENA_X | R300_WRITE_ENA_Y)
+ ((R300_WRITE_ENA_X | R300_WRITE_ENA_Y | R300_WRITE_ENA_Z | R300_WRITE_ENA_W)
<< R300_WRITE_ENA_0_SHIFT) |
(R300_SWIZZLE_SELECT_X << R300_SWIZZLE_SELECT_X_1_SHIFT) |
(R300_SWIZZLE_SELECT_Y << R300_SWIZZLE_SELECT_Y_1_SHIFT) |
(R300_SWIZZLE_SELECT_FP_ZERO << R300_SWIZZLE_SELECT_Z_1_SHIFT) |
(R300_SWIZZLE_SELECT_FP_ONE << R300_SWIZZLE_SELECT_W_1_SHIFT) |
- ((R300_WRITE_ENA_X | R300_WRITE_ENA_Y)
+ ((R300_WRITE_ENA_X | R300_WRITE_ENA_Y | R300_WRITE_ENA_Z | R300_WRITE_ENA_W)
<< R300_WRITE_ENA_1_SHIFT)));
OUT_ACCEL_REG(R300_VAP_PROG_STREAM_CNTL_EXT_1,
((R300_SWIZZLE_SELECT_X << R300_SWIZZLE_SELECT_X_2_SHIFT) |
(R300_SWIZZLE_SELECT_Y << R300_SWIZZLE_SELECT_Y_2_SHIFT) |
(R300_SWIZZLE_SELECT_FP_ZERO << R300_SWIZZLE_SELECT_Z_2_SHIFT) |
(R300_SWIZZLE_SELECT_FP_ONE << R300_SWIZZLE_SELECT_W_2_SHIFT) |
- ((R300_WRITE_ENA_X | R300_WRITE_ENA_Y)
+ ((R300_WRITE_ENA_X | R300_WRITE_ENA_Y | R300_WRITE_ENA_Z | R300_WRITE_ENA_W)
<< R300_WRITE_ENA_2_SHIFT)));
}
+ FINISH_ACCEL();
/* setup the vertex shader */
if (has_tcl) {
- OUT_ACCEL_REG(R300_VAP_PVS_CODE_CNTL_0,
- ((0 << R300_PVS_FIRST_INST_SHIFT) |
- (1 << R300_PVS_XYZW_VALID_INST_SHIFT) |
- (1 << R300_PVS_LAST_INST_SHIFT)));
- OUT_ACCEL_REG(R300_VAP_PVS_CODE_CNTL_1,
- (1 << R300_PVS_LAST_VTX_SRC_INST_SHIFT));
+ if (pMask) {
+ BEGIN_ACCEL(22);
+ /* flush the PVS before updating??? */
+ OUT_ACCEL_REG(R300_VAP_PVS_STATE_FLUSH_REG, 0);
+
+ OUT_ACCEL_REG(R300_VAP_PVS_CODE_CNTL_0,
+ ((0 << R300_PVS_FIRST_INST_SHIFT) |
+ (2 << R300_PVS_XYZW_VALID_INST_SHIFT) |
+ (2 << R300_PVS_LAST_INST_SHIFT)));
+ OUT_ACCEL_REG(R300_VAP_PVS_CODE_CNTL_1,
+ (2 << R300_PVS_LAST_VTX_SRC_INST_SHIFT));
+ } else {
+ BEGIN_ACCEL(18);
+ /* flush the PVS before updating??? */
+ OUT_ACCEL_REG(R300_VAP_PVS_STATE_FLUSH_REG, 0);
+
+ OUT_ACCEL_REG(R300_VAP_PVS_CODE_CNTL_0,
+ ((0 << R300_PVS_FIRST_INST_SHIFT) |
+ (1 << R300_PVS_XYZW_VALID_INST_SHIFT) |
+ (1 << R300_PVS_LAST_INST_SHIFT)));
+ OUT_ACCEL_REG(R300_VAP_PVS_CODE_CNTL_1,
+ (1 << R300_PVS_LAST_VTX_SRC_INST_SHIFT));
+ }
OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_INDX_REG, 0);
- OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,0x00f00203);
- OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,0x00d10001);
- OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,0x01248001);
- OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,0x01248001);
- OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,0x00f02203);
- OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,0x00d10141);
- OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,0x01248141);
- OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,0x01248141);
+ /* PVS inst 0 */
+ OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
+ (R300_PVS_DST_OPCODE(R300_VE_ADD) |
+ R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_OUT) |
+ R300_PVS_DST_OFFSET(0) |
+ R300_PVS_DST_WE_X | R300_PVS_DST_WE_Y |
+ R300_PVS_DST_WE_Z | R300_PVS_DST_WE_W));
+ OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
+ (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
+ R300_PVS_SRC_OFFSET(0) |
+ R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) |
+ R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) |
+ R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_Z) |
+ R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_W)));
+ OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
+ (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
+ R300_PVS_SRC_OFFSET(0) |
+ R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) |
+ R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) |
+ R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
+ R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
+ OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
+ (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
+ R300_PVS_SRC_OFFSET(0) |
+ R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) |
+ R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) |
+ R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
+ R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
+
+ /* PVS inst 1 */
+ OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
+ (R300_PVS_DST_OPCODE(R300_VE_ADD) |
+ R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_OUT) |
+ R300_PVS_DST_OFFSET(1) |
+ R300_PVS_DST_WE_X | R300_PVS_DST_WE_Y |
+ R300_PVS_DST_WE_Z | R300_PVS_DST_WE_W));
+ OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
+ (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
+ R300_PVS_SRC_OFFSET(1) |
+ R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) |
+ R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) |
+ R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_Z) |
+ R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_W)));
+ OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
+ (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
+ R300_PVS_SRC_OFFSET(1) |
+ R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) |
+ R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) |
+ R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
+ R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
+ OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
+ (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
+ R300_PVS_SRC_OFFSET(1) |
+ R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) |
+ R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) |
+ R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
+ R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
+
+ if (pMask) {
+ /* PVS inst 2 */
+ OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
+ (R300_PVS_DST_OPCODE(R300_VE_ADD) |
+ R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_OUT) |
+ R300_PVS_DST_OFFSET(2) |
+ R300_PVS_DST_WE_X | R300_PVS_DST_WE_Y |
+ R300_PVS_DST_WE_Z | R300_PVS_DST_WE_W));
+ OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
+ (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
+ R300_PVS_SRC_OFFSET(2) |
+ R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) |
+ R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) |
+ R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_Z) |
+ R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_W)));
+ OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
+ (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
+ R300_PVS_SRC_OFFSET(2) |
+ R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) |
+ R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) |
+ R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
+ R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
+ OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG,
+ (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
+ R300_PVS_SRC_OFFSET(2) |
+ R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) |
+ R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) |
+ R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
+ R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
+ }
OUT_ACCEL_REG(R300_VAP_PVS_FLOW_CNTL_OPC, 0);
@@ -1196,259 +1298,632 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op, PicturePtr pSrcPicture,
OUT_ACCEL_REG(R300_VAP_GB_HORZ_CLIP_ADJ, 0x3f800000);
OUT_ACCEL_REG(R300_VAP_GB_HORZ_DISC_ADJ, 0x3f800000);
OUT_ACCEL_REG(R300_VAP_CLIP_CNTL, R300_CLIP_DISABLE);
+ FINISH_ACCEL();
}
+
+ BEGIN_ACCEL(4);
OUT_ACCEL_REG(R300_VAP_OUT_VTX_FMT_0, R300_VTX_POS_PRESENT);
OUT_ACCEL_REG(R300_VAP_OUT_VTX_FMT_1,
((2 << R300_TEX_0_COMP_CNT_SHIFT) |
(2 << R300_TEX_1_COMP_CNT_SHIFT)));
+ OUT_ACCEL_REG(R300_TX_INVALTAGS, 0x0);
+ OUT_ACCEL_REG(R300_TX_ENABLE, txenable);
FINISH_ACCEL();
/* setup pixel shader */
- if (IS_R300_VARIANT ||
- (info->ChipFamily == CHIP_FAMILY_RS690) ||
- (info->ChipFamily == CHIP_FAMILY_RS740)) {
- BEGIN_ACCEL(16);
- OUT_ACCEL_REG(R300_RS_COUNT,
- ((2 << R300_RS_COUNT_IT_COUNT_SHIFT) |
- R300_RS_COUNT_HIRES_EN));
- OUT_ACCEL_REG(R300_RS_IP_0,
- (R300_RS_TEX_PTR(0) |
- R300_RS_COL_PTR(0) |
- R300_RS_COL_FMT(R300_RS_COL_FMT_RGBA) |
- R300_RS_SEL_S(R300_RS_SEL_C0) |
- R300_RS_SEL_T(R300_RS_SEL_C1) |
- R300_RS_SEL_R(R300_RS_SEL_K0) |
- R300_RS_SEL_Q(R300_RS_SEL_K1)));
- OUT_ACCEL_REG(R300_RS_INST_COUNT, R300_TX_OFFSET_RS(6));
- OUT_ACCEL_REG(R300_RS_INST_0, R300_RS_INST_TEX_CN_WRITE);
- OUT_ACCEL_REG(R300_US_CONFIG, (0 << R300_NLEVEL_SHIFT) | R300_FIRST_TEX);
- OUT_ACCEL_REG(R300_US_PIXSIZE, 0);
- OUT_ACCEL_REG(R300_US_CODE_OFFSET,
- (R300_ALU_CODE_OFFSET(0) |
- R300_ALU_CODE_SIZE(1) |
- R300_TEX_CODE_OFFSET(0) |
- R300_TEX_CODE_SIZE(1)));
- OUT_ACCEL_REG(R300_US_CODE_ADDR_0,
- (R300_ALU_START(0) |
- R300_ALU_SIZE(0) |
- R300_TEX_START(0) |
- R300_TEX_SIZE(0)));
- OUT_ACCEL_REG(R300_US_CODE_ADDR_1,
- (R300_ALU_START(0) |
- R300_ALU_SIZE(0) |
- R300_TEX_START(0) |
- R300_TEX_SIZE(0)));
- OUT_ACCEL_REG(R300_US_CODE_ADDR_2,
- (R300_ALU_START(0) |
- R300_ALU_SIZE(0) |
- R300_TEX_START(0) |
- R300_TEX_SIZE(0)));
- OUT_ACCEL_REG(R300_US_CODE_ADDR_3,
- (R300_ALU_START(0) |
- R300_ALU_SIZE(0) |
- R300_TEX_START(0) |
- R300_TEX_SIZE(0) |
- R300_RGBA_OUT));
- OUT_ACCEL_REG(R300_US_TEX_INST_0,
- (R300_TEX_SRC_ADDR(0) |
- R300_TEX_DST_ADDR(0) |
- R300_TEX_ID(0) |
- R300_TEX_INST(R300_TEX_INST_LD)));
- OUT_ACCEL_REG(R300_US_ALU_RGB_ADDR_0,
- (R300_ALU_RGB_ADDR0(0) |
- R300_ALU_RGB_ADDR1(0) |
- R300_ALU_RGB_ADDR2(0) |
- R300_ALU_RGB_ADDRD(0) |
- R300_ALU_RGB_WMASK((R300_ALU_RGB_MASK_R |
- R300_ALU_RGB_MASK_G |
- R300_ALU_RGB_MASK_B)) |
- R300_ALU_RGB_OMASK((R300_ALU_RGB_MASK_R |
- R300_ALU_RGB_MASK_G |
- R300_ALU_RGB_MASK_B)) |
- R300_ALU_RGB_TARGET_A));
- OUT_ACCEL_REG(R300_US_ALU_RGB_INST_0,
- (R300_ALU_RGB_SEL_A(R300_ALU_RGB_SRC0_RGB) |
- R300_ALU_RGB_MOD_A(R300_ALU_RGB_MOD_NOP) |
- R300_ALU_RGB_SEL_B(R300_ALU_RGB_1_0) |
- R300_ALU_RGB_MOD_B(R300_ALU_RGB_MOD_NOP) |
- R300_ALU_RGB_SEL_C(R300_ALU_RGB_0_0) |
- R300_ALU_RGB_MOD_C(R300_ALU_RGB_MOD_NOP) |
- R300_ALU_RGB_OP(R300_ALU_RGB_OP_MAD) |
- R300_ALU_RGB_OMOD(R300_ALU_RGB_OMOD_NONE)));
- OUT_ACCEL_REG(R300_US_ALU_ALPHA_ADDR_0,
- (R300_ALU_ALPHA_ADDR0(0) |
- R300_ALU_ALPHA_ADDR1(0) |
- R300_ALU_ALPHA_ADDR2(0) |
- R300_ALU_ALPHA_ADDRD(0) |
- R300_ALU_ALPHA_WMASK(R300_ALU_ALPHA_MASK_A) |
- R300_ALU_ALPHA_OMASK(R300_ALU_ALPHA_MASK_A) |
- R300_ALU_ALPHA_TARGET_A |
- R300_ALU_ALPHA_OMASK_W(R300_ALU_ALPHA_MASK_NONE)));
- OUT_ACCEL_REG(R300_US_ALU_ALPHA_INST_0,
- (R300_ALU_ALPHA_SEL_A(R300_ALU_ALPHA_SRC0_A) |
- R300_ALU_ALPHA_MOD_A(R300_ALU_ALPHA_MOD_NOP) |
- R300_ALU_ALPHA_SEL_B(R300_ALU_ALPHA_1_0) |
- R300_ALU_ALPHA_MOD_B(R300_ALU_ALPHA_MOD_NOP) |
- R300_ALU_ALPHA_SEL_C(R300_ALU_ALPHA_0_0) |
- R300_ALU_ALPHA_MOD_C(R300_ALU_ALPHA_MOD_NOP) |
- R300_ALU_ALPHA_OP(R300_ALU_ALPHA_OP_MAD) |
- R300_ALU_ALPHA_OMOD(R300_ALU_ALPHA_OMOD_NONE)));
- FINISH_ACCEL();
- } else {
- BEGIN_ACCEL(23);
- OUT_ACCEL_REG(R300_RS_COUNT,
- ((2 << R300_RS_COUNT_IT_COUNT_SHIFT) |
- R300_RS_COUNT_HIRES_EN));
- OUT_ACCEL_REG(R500_RS_IP_0, ((0 << R500_RS_IP_TEX_PTR_S_SHIFT) |
- (1 << R500_RS_IP_TEX_PTR_T_SHIFT) |
- (R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_R_SHIFT) |
- (R500_RS_IP_PTR_K1 << R500_RS_IP_TEX_PTR_Q_SHIFT)));
-
- OUT_ACCEL_REG(R300_RS_INST_COUNT, 0);
- OUT_ACCEL_REG(R500_RS_INST_0, R500_RS_INST_TEX_CN_WRITE);
- OUT_ACCEL_REG(R300_US_CONFIG, R500_ZERO_TIMES_ANYTHING_EQUALS_ZERO);
- OUT_ACCEL_REG(R300_US_PIXSIZE, 0);
- OUT_ACCEL_REG(R500_US_FC_CTRL, 0);
- OUT_ACCEL_REG(R500_US_CODE_ADDR, (R500_US_CODE_START_ADDR(0) |
- R500_US_CODE_END_ADDR(1)));
- OUT_ACCEL_REG(R500_US_CODE_RANGE, (R500_US_CODE_RANGE_ADDR(0) |
- R500_US_CODE_RANGE_SIZE(1)));
- OUT_ACCEL_REG(R500_US_CODE_OFFSET, 0);
- OUT_ACCEL_REG(R500_GA_US_VECTOR_INDEX, 0);
- // 7807
- OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_TEX |
- R500_INST_TEX_SEM_WAIT |
- R500_INST_RGB_WMASK_R |
- R500_INST_RGB_WMASK_G |
- R500_INST_RGB_WMASK_B |
- R500_INST_ALPHA_WMASK));
-
- OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_ID(0) |
- R500_TEX_INST_LD |
- R500_TEX_SEM_ACQUIRE |
- R500_TEX_IGNORE_UNCOVERED));
-
- OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_SRC_ADDR(0) |
- R500_TEX_SRC_S_SWIZ_R |
- R500_TEX_SRC_T_SWIZ_G |
- R500_TEX_DST_ADDR(0) |
- R500_TEX_DST_R_SWIZ_R |
- R500_TEX_DST_G_SWIZ_G |
- R500_TEX_DST_B_SWIZ_B |
- R500_TEX_DST_A_SWIZ_A));
- OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_DX_ADDR(0) |
- R500_DX_S_SWIZ_R |
- R500_DX_T_SWIZ_R |
- R500_DX_R_SWIZ_R |
- R500_DX_Q_SWIZ_R |
- R500_DY_ADDR(0) |
- R500_DY_S_SWIZ_R |
- R500_DY_T_SWIZ_R |
- R500_DY_R_SWIZ_R |
- R500_DY_Q_SWIZ_R)); // TEX_ADDR_DXDY
- OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, 0x00000000); // mbz
- OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, 0x00000000); // mbz
-
- // 0x78105
- OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_OUT |
- R500_INST_TEX_SEM_WAIT |
- R500_INST_LAST |
- R500_INST_RGB_OMASK_R |
- R500_INST_RGB_OMASK_G |
- R500_INST_RGB_OMASK_B |
- R500_INST_ALPHA_OMASK));
-
- OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_RGB_ADDR0(0) |
- R500_RGB_ADDR1(0) |
- R500_RGB_ADDR1_CONST |
- R500_RGB_ADDR2(0) |
- R500_RGB_ADDR2_CONST |
- R500_RGB_SRCP_OP_1_MINUS_2RGB0)); //0x10040000
- OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDR0(0) |
- R500_ALPHA_ADDR1(0) |
- R500_ALPHA_ADDR1_CONST |
- R500_ALPHA_ADDR2(0) |
- R500_ALPHA_ADDR2_CONST |
- R500_ALPHA_SRCP_OP_1_MINUS_2A0)); //0x10040000
-
- OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGB_SEL_A_SRC0 |
- R500_ALU_RGB_R_SWIZ_A_R |
- R500_ALU_RGB_G_SWIZ_A_G |
- R500_ALU_RGB_B_SWIZ_A_B |
- R500_ALU_RGB_SEL_B_SRC0 |
- R500_ALU_RGB_R_SWIZ_B_1 |
- R500_ALU_RGB_B_SWIZ_B_1 |
- R500_ALU_RGB_G_SWIZ_B_1));//0x00db0220
-
- OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_OP_MAD |
- R500_ALPHA_SWIZ_A_A |
- R500_ALPHA_SWIZ_B_1));//0x00c0c000)
-
- OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGBA_OP_MAD |
- R500_ALU_RGBA_R_SWIZ_0 |
- R500_ALU_RGBA_G_SWIZ_0 |
- R500_ALU_RGBA_B_SWIZ_0 |
- R500_ALU_RGBA_A_SWIZ_0));//0x20490000
- FINISH_ACCEL();
- }
+ if (IS_R300_3D) {
+ CARD32 output_fmt;
+ int src_color, src_alpha;
+ int mask_color, mask_alpha;
- BEGIN_ACCEL(6);
- OUT_ACCEL_REG(R300_TX_INVALTAGS, 0x0);
- OUT_ACCEL_REG(R300_TX_ENABLE, txenable);
+ if (PICT_FORMAT_RGB(pSrcPicture->format) == 0)
+ src_color = R300_ALU_RGB_0_0;
+ else
+ src_color = R300_ALU_RGB_SRC0_RGB;
- OUT_ACCEL_REG(R300_RB3D_COLOROFFSET0, dst_offset);
- OUT_ACCEL_REG(R300_RB3D_COLORPITCH0, colorpitch);
+ if (PICT_FORMAT_A(pSrcPicture->format) == 0)
+ src_alpha = R300_ALU_ALPHA_1_0;
+ else
+ src_alpha = R300_ALU_ALPHA_SRC0_A;
- blendcntl = RADEONGetBlendCntl(op, pMaskPicture, pDstPicture->format);
- OUT_ACCEL_REG(R300_RB3D_BLENDCNTL, blendcntl);
- OUT_ACCEL_REG(R300_RB3D_ABLENDCNTL, 0);
+ if (pMask && pMaskPicture->componentAlpha) {
+ if (RadeonBlendOp[op].src_alpha) {
+ if (PICT_FORMAT_A(pSrcPicture->format) == 0) {
+ src_color = R300_ALU_RGB_1_0;
+ src_alpha = R300_ALU_ALPHA_1_0;
+ } else {
+ src_color = R300_ALU_RGB_SRC0_AAA;
+ src_alpha = R300_ALU_ALPHA_SRC0_A;
+ }
-#if 0
- /* IN operator: Multiply src by mask components or mask alpha.
- * BLEND_CTL_ADD is A * B + C.
- * If a picture is a8, we have to explicitly zero its color values.
- * If the destination is a8, we have to route the alpha to red, I think.
- * If we're doing component alpha where the source for blending is going to
- * be the source alpha (and there's no source value used), we have to zero
- * the source's color values.
- */
- cblend = R200_TXC_OP_MADD | R200_TXC_ARG_C_ZERO;
- ablend = R200_TXA_OP_MADD | R200_TXA_ARG_C_ZERO;
+ mask_color = R300_ALU_RGB_SRC1_RGB;
- if (pDstPicture->format == PICT_a8 ||
- (pMask && pMaskPicture->componentAlpha && RadeonBlendOp[op].src_alpha))
- {
- cblend |= R200_TXC_ARG_A_R0_ALPHA;
- } else if (pSrcPicture->format == PICT_a8)
- cblend |= R200_TXC_ARG_A_ZERO;
- else
- cblend |= R200_TXC_ARG_A_R0_COLOR;
- ablend |= R200_TXA_ARG_A_R0_ALPHA;
+ if (PICT_FORMAT_A(pMaskPicture->format) == 0)
+ mask_alpha = R300_ALU_ALPHA_1_0;
+ else
+ mask_alpha = R300_ALU_ALPHA_SRC1_A;
- if (pMask) {
- if (pMaskPicture->componentAlpha &&
- pDstPicture->format != PICT_a8)
- cblend |= R200_TXC_ARG_B_R1_COLOR;
- else
- cblend |= R200_TXC_ARG_B_R1_ALPHA;
- ablend |= R200_TXA_ARG_B_R1_ALPHA;
+ } else {
+ src_color = R300_ALU_RGB_SRC0_RGB;
+
+ if (PICT_FORMAT_A(pSrcPicture->format) == 0)
+ src_alpha = R300_ALU_ALPHA_1_0;
+ else
+ src_alpha = R300_ALU_ALPHA_SRC0_A;
+
+ mask_color = R300_ALU_RGB_SRC1_RGB;
+
+ if (PICT_FORMAT_A(pMaskPicture->format) == 0)
+ mask_alpha = R300_ALU_ALPHA_1_0;
+ else
+ mask_alpha = R300_ALU_ALPHA_SRC1_A;
+
+ }
+ } else if (pMask) {
+ if (PICT_FORMAT_A(pMaskPicture->format) == 0)
+ mask_color = R300_ALU_RGB_1_0;
+ else
+ mask_color = R300_ALU_RGB_SRC1_AAA;
+
+ if (PICT_FORMAT_A(pMaskPicture->format) == 0)
+ mask_alpha = R300_ALU_ALPHA_1_0;
+ else
+ mask_alpha = R300_ALU_ALPHA_SRC1_A;
+ } else {
+ mask_color = R300_ALU_RGB_1_0;
+ mask_alpha = R300_ALU_ALPHA_1_0;
+ }
+
+ /* shader output swizzling */
+ switch (pDstPicture->format) {
+ case PICT_a8r8g8b8:
+ case PICT_x8r8g8b8:
+ default:
+ output_fmt = (R300_OUT_FMT_C4_8 |
+ R300_OUT_FMT_C0_SEL_BLUE |
+ R300_OUT_FMT_C1_SEL_GREEN |
+ R300_OUT_FMT_C2_SEL_RED |
+ R300_OUT_FMT_C3_SEL_ALPHA);
+ break;
+ case PICT_a8b8g8r8:
+ case PICT_x8b8g8r8:
+ output_fmt = (R300_OUT_FMT_C4_8 |
+ R300_OUT_FMT_C0_SEL_RED |
+ R300_OUT_FMT_C1_SEL_GREEN |
+ R300_OUT_FMT_C2_SEL_BLUE |
+ R300_OUT_FMT_C3_SEL_ALPHA);
+ break;
+ case PICT_r5g6b5:
+ case PICT_a1r5g5b5:
+ case PICT_x1r5g5b5:
+ output_fmt = (R300_OUT_FMT_C_5_6_5 |
+ R300_OUT_FMT_C0_SEL_BLUE |
+ R300_OUT_FMT_C1_SEL_GREEN |
+ R300_OUT_FMT_C2_SEL_RED |
+ R300_OUT_FMT_C3_SEL_ALPHA);
+ break;
+ case PICT_a8:
+ output_fmt = (R300_OUT_FMT_C4_8 |
+ R300_OUT_FMT_C0_SEL_ALPHA);
+ break;
+ }
+
+
+ /* setup the rasterizer */
+ if (pMask) {
+ BEGIN_ACCEL(20);
+ /* 4 components: 2 for tex0, 2 for tex1 */
+ OUT_ACCEL_REG(R300_RS_COUNT,
+ ((4 << R300_RS_COUNT_IT_COUNT_SHIFT) |
+ R300_RS_COUNT_HIRES_EN));
+ /* rasterizer source table */
+ OUT_ACCEL_REG(R300_RS_IP_0,
+ (R300_RS_TEX_PTR(0) |
+ R300_RS_SEL_S(R300_RS_SEL_C0) |
+ R300_RS_SEL_T(R300_RS_SEL_C1) |
+ R300_RS_SEL_R(R300_RS_SEL_K0) |
+ R300_RS_SEL_Q(R300_RS_SEL_K1)));
+ OUT_ACCEL_REG(R300_RS_IP_1,
+ (R300_RS_TEX_PTR(2) |
+ R300_RS_SEL_S(R300_RS_SEL_C0) |
+ R300_RS_SEL_T(R300_RS_SEL_C1) |
+ R300_RS_SEL_R(R300_RS_SEL_K0) |
+ R300_RS_SEL_Q(R300_RS_SEL_K1)));
+
+ OUT_ACCEL_REG(R300_RS_INST_COUNT, R300_INST_COUNT_RS(1) | R300_TX_OFFSET_RS(6));
+ /* src tex */
+ OUT_ACCEL_REG(R300_RS_INST_0, (R300_INST_TEX_ID(0) |
+ R300_RS_INST_TEX_CN_WRITE |
+ R300_INST_TEX_ADDR(0)));
+ /* mask tex */
+ OUT_ACCEL_REG(R300_RS_INST_1, (R300_INST_TEX_ID(1) |
+ R300_RS_INST_TEX_CN_WRITE |
+ R300_INST_TEX_ADDR(1)));
+
+ OUT_ACCEL_REG(R300_US_CONFIG, (0 << R300_NLEVEL_SHIFT) | R300_FIRST_TEX);
+ OUT_ACCEL_REG(R300_US_PIXSIZE, 1); /* max num of temps used */
+ OUT_ACCEL_REG(R300_US_CODE_OFFSET, (R300_ALU_CODE_OFFSET(0) |
+ R300_ALU_CODE_SIZE(0) |
+ R300_TEX_CODE_OFFSET(0) |
+ R300_TEX_CODE_SIZE(1)));
+
+ } else {
+ BEGIN_ACCEL(17);
+ /* 2 components: 2 for tex0 */
+ OUT_ACCEL_REG(R300_RS_COUNT,
+ ((2 << R300_RS_COUNT_IT_COUNT_SHIFT) |
+ R300_RS_COUNT_HIRES_EN));
+ OUT_ACCEL_REG(R300_RS_IP_0,
+ (R300_RS_TEX_PTR(0) |
+ R300_RS_SEL_S(R300_RS_SEL_C0) |
+ R300_RS_SEL_T(R300_RS_SEL_C1) |
+ R300_RS_SEL_R(R300_RS_SEL_K0) |
+ R300_RS_SEL_Q(R300_RS_SEL_K1)));
+ OUT_ACCEL_REG(R300_RS_INST_COUNT, R300_INST_COUNT_RS(0) | R300_TX_OFFSET_RS(6));
+ /* src tex */
+ OUT_ACCEL_REG(R300_RS_INST_0, (R300_INST_TEX_ID(0) |
+ R300_RS_INST_TEX_CN_WRITE |
+ R300_INST_TEX_ADDR(0)));
+
+ OUT_ACCEL_REG(R300_US_CONFIG, (0 << R300_NLEVEL_SHIFT) | R300_FIRST_TEX);
+ OUT_ACCEL_REG(R300_US_PIXSIZE, 1); /* max num of temps used */
+ OUT_ACCEL_REG(R300_US_CODE_OFFSET, (R300_ALU_CODE_OFFSET(0) |
+ R300_ALU_CODE_SIZE(0) |
+ R300_TEX_CODE_OFFSET(0) |
+ R300_TEX_CODE_SIZE(0)));
+
+ }
+
+ OUT_ACCEL_REG(R300_US_CODE_ADDR_0,
+ (R300_ALU_START(0) |
+ R300_ALU_SIZE(0) |
+ R300_TEX_START(0) |
+ R300_TEX_SIZE(0)));
+ OUT_ACCEL_REG(R300_US_CODE_ADDR_1,
+ (R300_ALU_START(0) |
+ R300_ALU_SIZE(0) |
+ R300_TEX_START(0) |
+ R300_TEX_SIZE(0)));
+ OUT_ACCEL_REG(R300_US_CODE_ADDR_2,
+ (R300_ALU_START(0) |
+ R300_ALU_SIZE(0) |
+ R300_TEX_START(0) |
+ R300_TEX_SIZE(0)));
+
+ if (pMask) {
+ OUT_ACCEL_REG(R300_US_CODE_ADDR_3,
+ (R300_ALU_START(0) |
+ R300_ALU_SIZE(0) |
+ R300_TEX_START(0) |
+ R300_TEX_SIZE(1) |
+ R300_RGBA_OUT));
+ } else {
+ OUT_ACCEL_REG(R300_US_CODE_ADDR_3,
+ (R300_ALU_START(0) |
+ R300_ALU_SIZE(0) |
+ R300_TEX_START(0) |
+ R300_TEX_SIZE(0) |
+ R300_RGBA_OUT));
+ }
+
+ OUT_ACCEL_REG(R300_US_OUT_FMT_0, output_fmt);
+
+ OUT_ACCEL_REG(R300_US_TEX_INST_0,
+ (R300_TEX_SRC_ADDR(0) |
+ R300_TEX_DST_ADDR(0) |
+ R300_TEX_ID(0) |
+ R300_TEX_INST(R300_TEX_INST_LD)));
+
+ if (pMask) {
+ OUT_ACCEL_REG(R300_US_TEX_INST_1,
+ (R300_TEX_SRC_ADDR(1) |
+ R300_TEX_DST_ADDR(1) |
+ R300_TEX_ID(1) |
+ R300_TEX_INST(R300_TEX_INST_LD)));
+ }
+
+ OUT_ACCEL_REG(R300_US_ALU_RGB_ADDR_0,
+ (R300_ALU_RGB_ADDR0(0) |
+ R300_ALU_RGB_ADDR1(1) |
+ R300_ALU_RGB_ADDR2(0) |
+ R300_ALU_RGB_ADDRD(0) |
+ R300_ALU_RGB_OMASK((R300_ALU_RGB_MASK_R |
+ R300_ALU_RGB_MASK_G |
+ R300_ALU_RGB_MASK_B)) |
+ R300_ALU_RGB_TARGET_A));
+ OUT_ACCEL_REG(R300_US_ALU_RGB_INST_0,
+ (R300_ALU_RGB_SEL_A(src_color) |
+ R300_ALU_RGB_MOD_A(R300_ALU_RGB_MOD_NOP) |
+ R300_ALU_RGB_SEL_B(mask_color) |
+ R300_ALU_RGB_MOD_B(R300_ALU_RGB_MOD_NOP) |
+ R300_ALU_RGB_SEL_C(R300_ALU_RGB_0_0) |
+ R300_ALU_RGB_MOD_C(R300_ALU_RGB_MOD_NOP) |
+ R300_ALU_RGB_OP(R300_ALU_RGB_OP_MAD) |
+ R300_ALU_RGB_OMOD(R300_ALU_RGB_OMOD_NONE) |
+ R300_ALU_RGB_CLAMP));
+ OUT_ACCEL_REG(R300_US_ALU_ALPHA_ADDR_0,
+ (R300_ALU_ALPHA_ADDR0(0) |
+ R300_ALU_ALPHA_ADDR1(1) |
+ R300_ALU_ALPHA_ADDR2(0) |
+ R300_ALU_ALPHA_ADDRD(0) |
+ R300_ALU_ALPHA_OMASK(R300_ALU_ALPHA_MASK_A) |
+ R300_ALU_ALPHA_TARGET_A |
+ R300_ALU_ALPHA_OMASK_W(R300_ALU_ALPHA_MASK_NONE)));
+ OUT_ACCEL_REG(R300_US_ALU_ALPHA_INST_0,
+ (R300_ALU_ALPHA_SEL_A(src_alpha) |
+ R300_ALU_ALPHA_MOD_A(R300_ALU_ALPHA_MOD_NOP) |
+ R300_ALU_ALPHA_SEL_B(mask_alpha) |
+ R300_ALU_ALPHA_MOD_B(R300_ALU_ALPHA_MOD_NOP) |
+ R300_ALU_ALPHA_SEL_C(R300_ALU_ALPHA_0_0) |
+ R300_ALU_ALPHA_MOD_C(R300_ALU_ALPHA_MOD_NOP) |
+ R300_ALU_ALPHA_OP(R300_ALU_ALPHA_OP_MAD) |
+ R300_ALU_ALPHA_OMOD(R300_ALU_ALPHA_OMOD_NONE) |
+ R300_ALU_ALPHA_CLAMP));
+ FINISH_ACCEL();
} else {
- cblend |= R200_TXC_ARG_B_ZERO | R200_TXC_COMP_ARG_B;
- ablend |= R200_TXA_ARG_B_ZERO | R200_TXA_COMP_ARG_B;
+ CARD32 output_fmt;
+ CARD32 src_color, src_alpha;
+ CARD32 mask_color, mask_alpha;
+
+ if (PICT_FORMAT_RGB(pSrcPicture->format) == 0)
+ //src_color = R300_ALU_RGB_0_0;
+ src_color = (R500_ALU_RGB_R_SWIZ_A_0 |
+ R500_ALU_RGB_G_SWIZ_A_0 |
+ R500_ALU_RGB_B_SWIZ_A_0);
+ else
+ //src_color = R300_ALU_RGB_SRC0_RGB;
+ src_color = (R500_ALU_RGB_R_SWIZ_A_R |
+ R500_ALU_RGB_G_SWIZ_A_G |
+ R500_ALU_RGB_B_SWIZ_A_B);
+
+ if (PICT_FORMAT_A(pSrcPicture->format) == 0)
+ //src_alpha = R300_ALU_ALPHA_1_0;
+ src_alpha = R500_ALPHA_SWIZ_A_1;
+ else
+ //src_alpha = R300_ALU_ALPHA_SRC0_A;
+ src_alpha = R500_ALPHA_SWIZ_A_A;
+
+ if (pMask && pMaskPicture->componentAlpha) {
+ if (RadeonBlendOp[op].src_alpha) {
+ if (PICT_FORMAT_A(pSrcPicture->format) == 0) {
+ //src_color = R300_ALU_RGB_1_0;
+ //src_alpha = R300_ALU_ALPHA_1_0;
+ src_color = (R500_ALU_RGB_R_SWIZ_A_1 |
+ R500_ALU_RGB_G_SWIZ_A_1 |
+ R500_ALU_RGB_B_SWIZ_A_1);
+ src_alpha = R500_ALPHA_SWIZ_A_1;
+ } else {
+ //src_color = R300_ALU_RGB_SRC0_AAA;
+ //src_alpha = R300_ALU_ALPHA_SRC0_A;
+ src_color = (R500_ALU_RGB_R_SWIZ_A_A |
+ R500_ALU_RGB_G_SWIZ_A_A |
+ R500_ALU_RGB_B_SWIZ_A_A);
+ src_alpha = R500_ALPHA_SWIZ_A_A;
+ }
+
+ //mask_color = R300_ALU_RGB_SRC1_RGB;
+ mask_color = (R500_ALU_RGB_R_SWIZ_B_R |
+ R500_ALU_RGB_G_SWIZ_B_G |
+ R500_ALU_RGB_B_SWIZ_B_B);
+
+ if (PICT_FORMAT_A(pMaskPicture->format) == 0)
+ //mask_alpha = R300_ALU_ALPHA_1_0;
+ mask_alpha = R500_ALPHA_SWIZ_B_1;
+ else
+ //mask_alpha = R300_ALU_ALPHA_SRC1_A;
+ mask_alpha = R500_ALPHA_SWIZ_B_A;
+
+ } else {
+ //src_color = R300_ALU_RGB_SRC0_RGB;
+ src_color = (R500_ALU_RGB_R_SWIZ_A_R |
+ R500_ALU_RGB_G_SWIZ_A_G |
+ R500_ALU_RGB_B_SWIZ_A_B);
+
+ if (PICT_FORMAT_A(pSrcPicture->format) == 0)
+ //src_alpha = R300_ALU_ALPHA_1_0;
+ src_alpha = R500_ALPHA_SWIZ_A_1;
+ else
+ //src_alpha = R300_ALU_ALPHA_SRC0_A;
+ src_alpha = R500_ALPHA_SWIZ_A_A;
+
+ //mask_color = R300_ALU_RGB_SRC1_RGB;
+ mask_color = (R500_ALU_RGB_R_SWIZ_B_R |
+ R500_ALU_RGB_G_SWIZ_B_G |
+ R500_ALU_RGB_B_SWIZ_B_B);
+
+ if (PICT_FORMAT_A(pMaskPicture->format) == 0)
+ //mask_alpha = R300_ALU_ALPHA_1_0;
+ mask_alpha = R500_ALPHA_SWIZ_B_1;
+ else
+ //mask_alpha = R300_ALU_ALPHA_SRC1_A;
+ mask_alpha = R500_ALPHA_SWIZ_B_A;
+
+ }
+ } else if (pMask) {
+ if (PICT_FORMAT_A(pMaskPicture->format) == 0)
+ //mask_color = R300_ALU_RGB_1_0;
+ mask_color = (R500_ALU_RGB_R_SWIZ_B_1 |
+ R500_ALU_RGB_G_SWIZ_B_1 |
+ R500_ALU_RGB_B_SWIZ_B_1);
+ else
+ //mask_color = R300_ALU_RGB_SRC1_AAA;
+ mask_color = (R500_ALU_RGB_R_SWIZ_B_A |
+ R500_ALU_RGB_G_SWIZ_B_A |
+ R500_ALU_RGB_B_SWIZ_B_A);
+
+ if (PICT_FORMAT_A(pMaskPicture->format) == 0)
+ //mask_alpha = R300_ALU_ALPHA_1_0;
+ mask_alpha = R500_ALPHA_SWIZ_B_1;
+ else
+ //mask_alpha = R300_ALU_ALPHA_SRC1_A;
+ mask_alpha = R500_ALPHA_SWIZ_B_A;
+ } else {
+ //mask_color = R300_ALU_RGB_1_0;
+ mask_color = (R500_ALU_RGB_R_SWIZ_B_1 |
+ R500_ALU_RGB_G_SWIZ_B_1 |
+ R500_ALU_RGB_B_SWIZ_B_1);
+ //mask_alpha = R300_ALU_ALPHA_1_0;
+ mask_alpha = R500_ALPHA_SWIZ_B_1;
+ }
+
+ /* shader output swizzling */
+ switch (pDstPicture->format) {
+ case PICT_a8r8g8b8:
+ case PICT_x8r8g8b8:
+ default:
+ output_fmt = (R300_OUT_FMT_C4_8 |
+ R300_OUT_FMT_C0_SEL_BLUE |
+ R300_OUT_FMT_C1_SEL_GREEN |
+ R300_OUT_FMT_C2_SEL_RED |
+ R300_OUT_FMT_C3_SEL_ALPHA);
+ break;
+ case PICT_a8b8g8r8:
+ case PICT_x8b8g8r8:
+ output_fmt = (R300_OUT_FMT_C4_8 |
+ R300_OUT_FMT_C0_SEL_RED |
+ R300_OUT_FMT_C1_SEL_GREEN |
+ R300_OUT_FMT_C2_SEL_BLUE |
+ R300_OUT_FMT_C3_SEL_ALPHA);
+ break;
+ case PICT_r5g6b5:
+ case PICT_a1r5g5b5:
+ case PICT_x1r5g5b5:
+ output_fmt = (R300_OUT_FMT_C_5_6_5 |
+ R300_OUT_FMT_C0_SEL_BLUE |
+ R300_OUT_FMT_C1_SEL_GREEN |
+ R300_OUT_FMT_C2_SEL_RED |
+ R300_OUT_FMT_C3_SEL_ALPHA);
+ break;
+ case PICT_a8:
+ output_fmt = (R300_OUT_FMT_C4_8 |
+ R300_OUT_FMT_C0_SEL_ALPHA);
+ break;
+ }
+
+ if (pMask) {
+ BEGIN_ACCEL(13);
+ OUT_ACCEL_REG(R300_RS_COUNT,
+ ((4 << R300_RS_COUNT_IT_COUNT_SHIFT) |
+ R300_RS_COUNT_HIRES_EN));
+ OUT_ACCEL_REG(R500_RS_IP_0, ((0 << R500_RS_IP_TEX_PTR_S_SHIFT) |
+ (1 << R500_RS_IP_TEX_PTR_T_SHIFT) |
+ (R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_R_SHIFT) |
+ (R500_RS_IP_PTR_K1 << R500_RS_IP_TEX_PTR_Q_SHIFT)));
+
+ OUT_ACCEL_REG(R500_RS_IP_1, ((2 << R500_RS_IP_TEX_PTR_S_SHIFT) |
+ (3 << R500_RS_IP_TEX_PTR_T_SHIFT) |
+ (R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_R_SHIFT) |
+ (R500_RS_IP_PTR_K1 << R500_RS_IP_TEX_PTR_Q_SHIFT)));
+
+ OUT_ACCEL_REG(R300_RS_INST_COUNT, R300_INST_COUNT_RS(1) | R300_TX_OFFSET_RS(6));
+
+ /* src tex */
+ OUT_ACCEL_REG(R500_RS_INST_0, ((0 << R500_RS_INST_TEX_ID_SHIFT) |
+ R500_RS_INST_TEX_CN_WRITE |
+ (0 << R500_RS_INST_TEX_ADDR_SHIFT)));
+ /* mask tex */
+ OUT_ACCEL_REG(R500_RS_INST_1, ((1 << R500_RS_INST_TEX_ID_SHIFT) |
+ R500_RS_INST_TEX_CN_WRITE |
+ (1 << R500_RS_INST_TEX_ADDR_SHIFT)));
+
+ OUT_ACCEL_REG(R300_US_CONFIG, R500_ZERO_TIMES_ANYTHING_EQUALS_ZERO);
+ OUT_ACCEL_REG(R300_US_PIXSIZE, 1);
+ OUT_ACCEL_REG(R500_US_FC_CTRL, 0);
+ OUT_ACCEL_REG(R500_US_CODE_ADDR, (R500_US_CODE_START_ADDR(0) |
+ R500_US_CODE_END_ADDR(2)));
+ OUT_ACCEL_REG(R500_US_CODE_RANGE, (R500_US_CODE_RANGE_ADDR(0) |
+ R500_US_CODE_RANGE_SIZE(2)));
+ OUT_ACCEL_REG(R500_US_CODE_OFFSET, 0);
+ } else {
+ BEGIN_ACCEL(11);
+ OUT_ACCEL_REG(R300_RS_COUNT,
+ ((2 << R300_RS_COUNT_IT_COUNT_SHIFT) |
+ R300_RS_COUNT_HIRES_EN));
+
+ OUT_ACCEL_REG(R500_RS_IP_0, ((0 << R500_RS_IP_TEX_PTR_S_SHIFT) |
+ (1 << R500_RS_IP_TEX_PTR_T_SHIFT) |
+ (R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_R_SHIFT) |
+ (R500_RS_IP_PTR_K1 << R500_RS_IP_TEX_PTR_Q_SHIFT)));
+
+ OUT_ACCEL_REG(R300_RS_INST_COUNT, R300_INST_COUNT_RS(1) | R300_TX_OFFSET_RS(6));
+
+ /* src tex */
+ OUT_ACCEL_REG(R500_RS_INST_0, ((0 << R500_RS_INST_TEX_ID_SHIFT) |
+ R500_RS_INST_TEX_CN_WRITE |
+ (0 << R500_RS_INST_TEX_ADDR_SHIFT)));
+
+ OUT_ACCEL_REG(R300_US_CONFIG, R500_ZERO_TIMES_ANYTHING_EQUALS_ZERO);
+ OUT_ACCEL_REG(R300_US_PIXSIZE, 1);
+ OUT_ACCEL_REG(R500_US_FC_CTRL, 0);
+ OUT_ACCEL_REG(R500_US_CODE_ADDR, (R500_US_CODE_START_ADDR(0) |
+ R500_US_CODE_END_ADDR(1)));
+ OUT_ACCEL_REG(R500_US_CODE_RANGE, (R500_US_CODE_RANGE_ADDR(0) |
+ R500_US_CODE_RANGE_SIZE(1)));
+ OUT_ACCEL_REG(R500_US_CODE_OFFSET, 0);
+ }
+
+ OUT_ACCEL_REG(R300_US_OUT_FMT_0, output_fmt);
+ FINISH_ACCEL();
+
+ if (pMask) {
+ BEGIN_ACCEL(19);
+ OUT_ACCEL_REG(R500_GA_US_VECTOR_INDEX, 0);
+ OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_TEX |
+ R500_INST_RGB_WMASK_R |
+ R500_INST_RGB_WMASK_G |
+ R500_INST_RGB_WMASK_B |
+ R500_INST_ALPHA_WMASK |
+ R500_INST_RGB_CLAMP |
+ R500_INST_ALPHA_CLAMP));
+
+ OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_ID(0) |
+ R500_TEX_INST_LD |
+ R500_TEX_IGNORE_UNCOVERED));
+
+ OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_SRC_ADDR(0) |
+ R500_TEX_SRC_S_SWIZ_R |
+ R500_TEX_SRC_T_SWIZ_G |
+ R500_TEX_DST_ADDR(0) |
+ R500_TEX_DST_R_SWIZ_R |
+ R500_TEX_DST_G_SWIZ_G |
+ R500_TEX_DST_B_SWIZ_B |
+ R500_TEX_DST_A_SWIZ_A));
+ OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_DX_ADDR(0) |
+ R500_DX_S_SWIZ_R |
+ R500_DX_T_SWIZ_R |
+ R500_DX_R_SWIZ_R |
+ R500_DX_Q_SWIZ_R |
+ R500_DY_ADDR(0) |
+ R500_DY_S_SWIZ_R |
+ R500_DY_T_SWIZ_R |
+ R500_DY_R_SWIZ_R |
+ R500_DY_Q_SWIZ_R)); // TEX_ADDR_DXDY
+ OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, 0x00000000); // mbz
+ OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, 0x00000000); // mbz
+
+ OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_TEX |
+ R500_INST_TEX_SEM_WAIT |
+ R500_INST_RGB_WMASK_R |
+ R500_INST_RGB_WMASK_G |
+ R500_INST_RGB_WMASK_B |
+ R500_INST_ALPHA_WMASK |
+ R500_INST_RGB_CLAMP |
+ R500_INST_ALPHA_CLAMP));
+
+ OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_ID(1) |
+ R500_TEX_INST_LD |
+ R500_TEX_SEM_ACQUIRE |
+ R500_TEX_IGNORE_UNCOVERED));
+
+ OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_SRC_ADDR(1) |
+ R500_TEX_SRC_S_SWIZ_R |
+ R500_TEX_SRC_T_SWIZ_G |
+ R500_TEX_DST_ADDR(1) |
+ R500_TEX_DST_R_SWIZ_R |
+ R500_TEX_DST_G_SWIZ_G |
+ R500_TEX_DST_B_SWIZ_B |
+ R500_TEX_DST_A_SWIZ_A));
+ OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_DX_ADDR(1) |
+ R500_DX_S_SWIZ_R |
+ R500_DX_T_SWIZ_R |
+ R500_DX_R_SWIZ_R |
+ R500_DX_Q_SWIZ_R |
+ R500_DY_ADDR(1) |
+ R500_DY_S_SWIZ_R |
+ R500_DY_T_SWIZ_R |
+ R500_DY_R_SWIZ_R |
+ R500_DY_Q_SWIZ_R)); // TEX_ADDR_DXDY
+ OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, 0x00000000); // mbz
+ OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, 0x00000000); // mbz
+ } else {
+ BEGIN_ACCEL(13);
+ OUT_ACCEL_REG(R500_GA_US_VECTOR_INDEX, 0);
+ OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_TEX |
+ R500_INST_TEX_SEM_WAIT |
+ R500_INST_RGB_WMASK_R |
+ R500_INST_RGB_WMASK_G |
+ R500_INST_RGB_WMASK_B |
+ R500_INST_ALPHA_WMASK |
+ R500_INST_RGB_CLAMP |
+ R500_INST_ALPHA_CLAMP));
+
+ OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_ID(0) |
+ R500_TEX_INST_LD |
+ R500_TEX_SEM_ACQUIRE |
+ R500_TEX_IGNORE_UNCOVERED));
+
+ OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_SRC_ADDR(0) |
+ R500_TEX_SRC_S_SWIZ_R |
+ R500_TEX_SRC_T_SWIZ_G |
+ R500_TEX_DST_ADDR(0) |
+ R500_TEX_DST_R_SWIZ_R |
+ R500_TEX_DST_G_SWIZ_G |
+ R500_TEX_DST_B_SWIZ_B |
+ R500_TEX_DST_A_SWIZ_A));
+ OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_DX_ADDR(0) |
+ R500_DX_S_SWIZ_R |
+ R500_DX_T_SWIZ_R |
+ R500_DX_R_SWIZ_R |
+ R500_DX_Q_SWIZ_R |
+ R500_DY_ADDR(0) |
+ R500_DY_S_SWIZ_R |
+ R500_DY_T_SWIZ_R |
+ R500_DY_R_SWIZ_R |
+ R500_DY_Q_SWIZ_R)); // TEX_ADDR_DXDY
+ OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, 0x00000000); // mbz
+ OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, 0x00000000); // mbz
+ }
+
+ OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_OUT |
+ R500_INST_TEX_SEM_WAIT |
+ R500_INST_LAST |
+ R500_INST_RGB_OMASK_R |
+ R500_INST_RGB_OMASK_G |
+ R500_INST_RGB_OMASK_B |
+ R500_INST_ALPHA_OMASK |
+ R500_INST_RGB_CLAMP |
+ R500_INST_ALPHA_CLAMP));
+
+ OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_RGB_ADDR0(0) |
+ R500_RGB_ADDR1(1) |
+ R500_RGB_ADDR2(0)));
+
+ OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDR0(0) |
+ R500_ALPHA_ADDR1(1) |
+ R500_ALPHA_ADDR2(0)));
+
+ OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGB_SEL_A_SRC0 |
+ src_color |
+ R500_ALU_RGB_SEL_B_SRC1 |
+ mask_color |
+ R500_ALU_RGB_TARGET(0)));
+
+ OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_OP_MAD |
+ R500_ALPHA_ADDRD(0) |
+ R500_ALPHA_SEL_A_SRC0 |
+ src_alpha |
+ R500_ALPHA_SEL_B_SRC1 |
+ mask_alpha |
+ R500_ALPHA_TARGET(0)));
+
+ OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGBA_OP_MAD |
+ R500_ALU_RGBA_ADDRD(0) |
+ R500_ALU_RGBA_R_SWIZ_0 |
+ R500_ALU_RGBA_G_SWIZ_0 |
+ R500_ALU_RGBA_B_SWIZ_0 |
+ R500_ALU_RGBA_A_SWIZ_0));
+ FINISH_ACCEL();
}
- OUT_ACCEL_REG(R200_PP_TXCBLEND_0, cblend);
- OUT_ACCEL_REG(R200_PP_TXCBLEND2_0,
- R200_TXC_CLAMP_0_1 | R200_TXC_OUTPUT_REG_R0);
- OUT_ACCEL_REG(R200_PP_TXABLEND_0, ablend);
- OUT_ACCEL_REG(R200_PP_TXABLEND2_0,
- R200_TXA_CLAMP_0_1 | R200_TXA_OUTPUT_REG_R0);
+ BEGIN_ACCEL(4);
+
+ OUT_ACCEL_REG(R300_RB3D_COLOROFFSET0, dst_offset);
+ OUT_ACCEL_REG(R300_RB3D_COLORPITCH0, colorpitch);
- /* Op operator. */
blendcntl = RADEONGetBlendCntl(op, pMaskPicture, pDstPicture->format);
- OUT_ACCEL_REG(RADEON_RB3D_BLENDCNTL, blendcntl);
-#endif
+ OUT_ACCEL_REG(R300_RB3D_BLENDCNTL, blendcntl | R300_ALPHA_BLEND_ENABLE | R300_READ_ENABLE);
+ OUT_ACCEL_REG(R300_RB3D_ABLENDCNTL, 0);
FINISH_ACCEL();
diff --git a/src/radeon_output.c b/src/radeon_output.c
index 62cc5d4..19ce36d 100644
--- a/src/radeon_output.c
+++ b/src/radeon_output.c
@@ -178,15 +178,9 @@ static Bool AVIVOI2CDoLock(xf86OutputPtr output, int lock_state);
extern void atombios_output_mode_set(xf86OutputPtr output,
DisplayModePtr mode,
DisplayModePtr adjusted_mode);
-extern void legacy_output_mode_set(xf86OutputPtr output,
- DisplayModePtr mode,
- DisplayModePtr adjusted_mode);
extern void atombios_output_dpms(xf86OutputPtr output, int mode);
-extern void legacy_output_dpms(xf86OutputPtr output, int mode);
extern RADEONMonitorType atombios_dac_detect(ScrnInfoPtr pScrn, xf86OutputPtr output);
-extern RADEONMonitorType legacy_dac_detect(ScrnInfoPtr pScrn, xf86OutputPtr output);
extern int atombios_external_tmds_setup(xf86OutputPtr output, DisplayModePtr mode);
-extern I2CDevPtr RADEONDVODeviceInit(I2CBusPtr b, I2CSlaveAddr addr);
static void
radeon_bios_output_dpms(xf86OutputPtr output, int mode);
static void
@@ -239,6 +233,8 @@ avivo_display_ddc_connected(ScrnInfoPtr pScrn, xf86OutputPtr output)
MonType = MT_DFP;
else if (radeon_output->type == OUTPUT_HDMI)
MonType = MT_DFP;
+ else if (radeon_output->type == OUTPUT_DP)
+ MonType = MT_DFP;
else if (radeon_output->type == OUTPUT_DVI_I && (MonInfo->rawData[0x14] & 0x80)) /* if it's digital and DVI */
MonType = MT_DFP;
else
@@ -1168,6 +1164,7 @@ static Atom tmds_pll_atom;
static Atom rmx_atom;
static Atom monitor_type_atom;
static Atom load_detection_atom;
+static Atom coherent_mode_atom;
static Atom tv_hsize_atom;
static Atom tv_hpos_atom;
static Atom tv_vpos_atom;
@@ -1235,6 +1232,30 @@ radeon_create_resources(xf86OutputPtr output)
}
}
+ if (IS_DCE3_VARIANT &&
+ (OUTPUT_IS_DVI || (radeon_output->type == OUTPUT_HDMI))) {
+ coherent_mode_atom = MAKE_ATOM("coherent_mode");
+
+ range[0] = 0; /* off */
+ range[1] = 1; /* on */
+ err = RRConfigureOutputProperty(output->randr_output, coherent_mode_atom,
+ FALSE, TRUE, FALSE, 2, range);
+ if (err != 0) {
+ xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
+ "RRConfigureOutputProperty error, %d\n", err);
+ }
+
+ data = 1; /* use coherent mode by default */
+
+ err = RRChangeOutputProperty(output->randr_output, coherent_mode_atom,
+ XA_INTEGER, 32, PropModeReplace, 1, &data,
+ FALSE, TRUE);
+ if (err != 0) {
+ xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
+ "RRChangeOutputProperty error, %d\n", err);
+ }
+ }
+
if (OUTPUT_IS_DVI && radeon_output->TMDSType == TMDS_INT) {
tmds_pll_atom = MAKE_ATOM("tmds_pll");
@@ -1413,6 +1434,26 @@ radeon_create_resources(xf86OutputPtr output)
}
static Bool
+radeon_set_mode_for_property(xf86OutputPtr output)
+{
+ ScrnInfoPtr pScrn = output->scrn;
+
+ if (output->crtc) {
+ xf86CrtcPtr crtc = output->crtc;
+
+ if (crtc->enabled) {
+ if (!xf86CrtcSetMode(crtc, &crtc->desiredMode, crtc->desiredRotation,
+ crtc->desiredX, crtc->desiredY)) {
+ xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
+ "Failed to set mode after propery change!\n");
+ return FALSE;
+ }
+ }
+ }
+ return TRUE;
+}
+
+static Bool
radeon_set_property(xf86OutputPtr output, Atom property,
RRPropertyValuePtr value)
{
@@ -1451,22 +1492,47 @@ radeon_set_property(xf86OutputPtr output, Atom property,
radeon_output->load_detection = val;
+ } else if (property == coherent_mode_atom) {
+ Bool coherent_mode = radeon_output->coherent_mode;
+
+ if (value->type != XA_INTEGER ||
+ value->format != 32 ||
+ value->size != 1) {
+ return FALSE;
+ }
+
+ val = *(INT32 *)value->data;
+ if (val < 0 || val > 1)
+ return FALSE;
+
+ radeon_output->coherent_mode = val;
+ if (!radeon_set_mode_for_property(output)) {
+ radeon_output->coherent_mode = coherent_mode;
+ (void)radeon_set_mode_for_property(output);
+ return FALSE;
+ }
+
} else if (property == rmx_atom) {
const char *s;
+ RADEONRMXType rmx = radeon_output->rmx_type;
+
if (value->type != XA_STRING || value->format != 8)
return FALSE;
s = (char*)value->data;
if (value->size == strlen("full") && !strncmp("full", s, strlen("full"))) {
radeon_output->rmx_type = RMX_FULL;
- return TRUE;
} else if (value->size == strlen("center") && !strncmp("center", s, strlen("center"))) {
radeon_output->rmx_type = RMX_CENTER;
- return TRUE;
} else if (value->size == strlen("off") && !strncmp("off", s, strlen("off"))) {
radeon_output->rmx_type = RMX_OFF;
- return TRUE;
+ } else
+ return FALSE;
+
+ if (!radeon_set_mode_for_property(output)) {
+ radeon_output->rmx_type = rmx;
+ (void)radeon_set_mode_for_property(output);
+ return FALSE;
}
- return FALSE;
} else if (property == tmds_pll_atom) {
const char *s;
if (value->type != XA_STRING || value->format != 8)
@@ -1475,12 +1541,12 @@ radeon_set_property(xf86OutputPtr output, Atom property,
if (value->size == strlen("bios") && !strncmp("bios", s, strlen("bios"))) {
if (!RADEONGetTMDSInfoFromBIOS(output))
RADEONGetTMDSInfoFromTable(output);
- return TRUE;
} else if (value->size == strlen("driver") && !strncmp("driver", s, strlen("driver"))) {
RADEONGetTMDSInfoFromTable(output);
- return TRUE;
- }
- return FALSE;
+ } else
+ return FALSE;
+
+ return radeon_set_mode_for_property(output);
} else if (property == monitor_type_atom) {
const char *s;
if (value->type != XA_STRING || value->format != 8)
@@ -1495,8 +1561,8 @@ radeon_set_property(xf86OutputPtr output, Atom property,
} else if (value->size == strlen("digital") && !strncmp("digital", s, strlen("digital"))) {
radeon_output->DVIType = DVI_DIGITAL;
return TRUE;
- }
- return FALSE;
+ } else
+ return FALSE;
} else if (property == tv_hsize_atom) {
if (value->type != XA_INTEGER ||
value->format != 32 ||
@@ -1511,7 +1577,7 @@ radeon_set_property(xf86OutputPtr output, Atom property,
radeon_output->hSize = val;
if (radeon_output->tv_on && !IS_AVIVO_VARIANT)
RADEONUpdateHVPosition(output, &output->crtc->mode);
- return TRUE;
+
} else if (property == tv_hpos_atom) {
if (value->type != XA_INTEGER ||
value->format != 32 ||
@@ -1526,7 +1592,7 @@ radeon_set_property(xf86OutputPtr output, Atom property,
radeon_output->hPos = val;
if (radeon_output->tv_on && !IS_AVIVO_VARIANT)
RADEONUpdateHVPosition(output, &output->crtc->mode);
- return TRUE;
+
} else if (property == tv_vpos_atom) {
if (value->type != XA_INTEGER ||
value->format != 32 ||
@@ -1541,38 +1607,38 @@ radeon_set_property(xf86OutputPtr output, Atom property,
radeon_output->vPos = val;
if (radeon_output->tv_on && !IS_AVIVO_VARIANT)
RADEONUpdateHVPosition(output, &output->crtc->mode);
- return TRUE;
+
} else if (property == tv_std_atom) {
const char *s;
+ TVStd std = radeon_output->tvStd;
+
if (value->type != XA_STRING || value->format != 8)
return FALSE;
s = (char*)value->data;
if (value->size == strlen("ntsc") && !strncmp("ntsc", s, strlen("ntsc"))) {
radeon_output->tvStd = TV_STD_NTSC;
- return TRUE;
} else if (value->size == strlen("pal") && !strncmp("pal", s, strlen("pal"))) {
radeon_output->tvStd = TV_STD_PAL;
- return TRUE;
} else if (value->size == strlen("pal-m") && !strncmp("pal-m", s, strlen("pal-m"))) {
radeon_output->tvStd = TV_STD_PAL_M;
- return TRUE;
} else if (value->size == strlen("pal-60") && !strncmp("pal-60", s, strlen("pal-60"))) {
radeon_output->tvStd = TV_STD_PAL_60;
- return TRUE;
} else if (value->size == strlen("ntsc-j") && !strncmp("ntsc-j", s, strlen("ntsc-j"))) {
radeon_output->tvStd = TV_STD_NTSC_J;
- return TRUE;
} else if (value->size == strlen("scart-pal") && !strncmp("scart-pal", s, strlen("scart-pal"))) {
radeon_output->tvStd = TV_STD_SCART_PAL;
- return TRUE;
} else if (value->size == strlen("pal-cn") && !strncmp("pal-cn", s, strlen("pal-cn"))) {
radeon_output->tvStd = TV_STD_PAL_CN;
- return TRUE;
} else if (value->size == strlen("secam") && !strncmp("secam", s, strlen("secam"))) {
radeon_output->tvStd = TV_STD_SECAM;
- return TRUE;
+ } else
+ return FALSE;
+
+ if (!radeon_set_mode_for_property(output)) {
+ radeon_output->tvStd = std;
+ (void)radeon_set_mode_for_property(output);
+ return FALSE;
}
- return FALSE;
}
return TRUE;
@@ -1622,6 +1688,8 @@ void RADEONSetOutputType(ScrnInfoPtr pScrn, RADEONOutputPrivatePtr radeon_output
case CONNECTOR_HDMI_TYPE_A:
case CONNECTOR_HDMI_TYPE_B:
output = OUTPUT_HDMI; break;
+ case CONNECTOR_DISPLAY_PORT:
+ output = OUTPUT_DP; break;
case CONNECTOR_DIGITAL:
case CONNECTOR_NONE:
case CONNECTOR_UNSUPPORTED:
@@ -2139,16 +2207,17 @@ void RADEONInitConnector(xf86OutputPtr output)
RADEONInfoPtr info = RADEONPTR(pScrn);
RADEONOutputPrivatePtr radeon_output = output->driver_private;
- if (radeon_output->DACType == DAC_PRIMARY)
+ if (info->IsAtomBios &&
+ ((radeon_output->DACType == DAC_PRIMARY) ||
+ (radeon_output->DACType == DAC_TVDAC)))
+ radeon_output->load_detection = 1;
+ else if (radeon_output->DACType == DAC_PRIMARY)
radeon_output->load_detection = 1; /* primary dac, only drives vga */
- /*else if (radeon_output->DACType == DAC_TVDAC &&
- info->tvdac_use_count < 2)
- radeon_output->load_detection = 1;*/ /* only one output with tvdac */
else if ((radeon_output->DACType == DAC_TVDAC) &&
(xf86ReturnOptValBool(info->Options, OPTION_TVDAC_LOAD_DETECT, FALSE)))
radeon_output->load_detection = 1; /* shared tvdac between vga/dvi/tv */
else
- radeon_output->load_detection = 0; /* shared tvdac between vga/dvi/tv */
+ radeon_output->load_detection = 0;
if (radeon_output->type == OUTPUT_LVDS) {
radeon_output->rmx_type = RMX_FULL;
@@ -2189,6 +2258,9 @@ void RADEONInitConnector(xf86OutputPtr output)
RADEONGetTVDacAdjInfo(output);
}
+ if (OUTPUT_IS_DVI || (radeon_output->type == OUTPUT_HDMI))
+ radeon_output->coherent_mode = TRUE;
+
if (radeon_output->ddc_i2c.valid)
RADEONI2CInit(output, &radeon_output->pI2CBus, output->name, FALSE);
@@ -2729,11 +2801,12 @@ Bool RADEONSetupConnectors(ScrnInfoPtr pScrn)
for (i = 0 ; i < RADEON_MAX_BIOS_CONNECTOR; i++) {
if (info->BiosConnector[i].valid) {
+ RADEONOutputPrivatePtr radeon_output;
if (info->BiosConnector[i].ConnectorType == CONNECTOR_NONE)
continue;
- RADEONOutputPrivatePtr radeon_output = xnfcalloc(sizeof(RADEONOutputPrivateRec), 1);
+ radeon_output = xnfcalloc(sizeof(RADEONOutputPrivateRec), 1);
if (!radeon_output) {
return FALSE;
}
@@ -2742,6 +2815,7 @@ Bool RADEONSetupConnectors(ScrnInfoPtr pScrn)
radeon_output->devices = info->BiosConnector[i].devices;
radeon_output->output_id = info->BiosConnector[i].output_id;
radeon_output->ddc_i2c = info->BiosConnector[i].ddc_i2c;
+ radeon_output->igp_lane_info = info->BiosConnector[i].igp_lane_info;
if (radeon_output->ConnectorType == CONNECTOR_DVI_D)
radeon_output->DACType = DAC_NONE;
diff --git a/src/radeon_pci_chipset_gen.h b/src/radeon_pci_chipset_gen.h
index ad77dbd..7bfae55 100644
--- a/src/radeon_pci_chipset_gen.h
+++ b/src/radeon_pci_chipset_gen.h
@@ -201,9 +201,9 @@ PciChipsets RADEONPciChipsets[] = {
{ PCI_CHIP_RV530_71D6, PCI_CHIP_RV530_71D6, RES_SHARED_VGA },
{ PCI_CHIP_RV530_71DA, PCI_CHIP_RV530_71DA, RES_SHARED_VGA },
{ PCI_CHIP_RV530_71DE, PCI_CHIP_RV530_71DE, RES_SHARED_VGA },
- { PCI_CHIP_RV530_7200, PCI_CHIP_RV530_7200, RES_SHARED_VGA },
- { PCI_CHIP_RV530_7210, PCI_CHIP_RV530_7210, RES_SHARED_VGA },
- { PCI_CHIP_RV530_7211, PCI_CHIP_RV530_7211, RES_SHARED_VGA },
+ { PCI_CHIP_RV515_7200, PCI_CHIP_RV515_7200, RES_SHARED_VGA },
+ { PCI_CHIP_RV515_7210, PCI_CHIP_RV515_7210, RES_SHARED_VGA },
+ { PCI_CHIP_RV515_7211, PCI_CHIP_RV515_7211, RES_SHARED_VGA },
{ PCI_CHIP_R580_7240, PCI_CHIP_R580_7240, RES_SHARED_VGA },
{ PCI_CHIP_R580_7243, PCI_CHIP_R580_7243, RES_SHARED_VGA },
{ PCI_CHIP_R580_7244, PCI_CHIP_R580_7244, RES_SHARED_VGA },
diff --git a/src/radeon_pci_device_match_gen.h b/src/radeon_pci_device_match_gen.h
index 77ca75d..2a04f8d 100644
--- a/src/radeon_pci_device_match_gen.h
+++ b/src/radeon_pci_device_match_gen.h
@@ -201,9 +201,9 @@ static const struct pci_id_match radeon_device_match[] = {
ATI_DEVICE_MATCH( PCI_CHIP_RV530_71D6, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_RV530_71DA, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_RV530_71DE, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_RV530_7200, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_RV530_7210, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_RV530_7211, 0 ),
+ ATI_DEVICE_MATCH( PCI_CHIP_RV515_7200, 0 ),
+ ATI_DEVICE_MATCH( PCI_CHIP_RV515_7210, 0 ),
+ ATI_DEVICE_MATCH( PCI_CHIP_RV515_7211, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_R580_7240, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_R580_7243, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_R580_7244, 0 ),
diff --git a/src/radeon_probe.h b/src/radeon_probe.h
index ae24003..7dfce68 100644
--- a/src/radeon_probe.h
+++ b/src/radeon_probe.h
@@ -104,7 +104,8 @@ typedef enum
TMDS_INT = 1,
TMDS_EXT = 2,
TMDS_LVTMA = 3,
- TMDS_DDIA = 4
+ TMDS_DDIA = 4,
+ TMDS_UNIPHY = 5
} RADEONTmdsType;
typedef enum
@@ -203,6 +204,7 @@ typedef struct {
int devices;
int hpd_mask;
RADEONI2CBusRec ddc_i2c;
+ int igp_lane_info;
} RADEONBIOSConnector;
typedef struct _RADEONOutputPrivateRec {
@@ -253,6 +255,8 @@ typedef struct _RADEONOutputPrivateRec {
int load_detection;
/* dig block */
int transmitter_config;
+ Bool coherent_mode;
+ int igp_lane_info;
char *name;
int output_id;
diff --git a/src/radeon_reg.h b/src/radeon_reg.h
index 94d5f31..6245403 100644
--- a/src/radeon_reg.h
+++ b/src/radeon_reg.h
@@ -3990,6 +3990,123 @@
# define R300_PVS_LAST_VTX_SRC_INST_SHIFT 0
#define R300_VAP_PVS_VECTOR_INDX_REG 0x2200
#define R300_VAP_PVS_VECTOR_DATA_REG 0x2204
+/* PVS instructions */
+/* Opcode and dst instruction */
+#define R300_PVS_DST_OPCODE(x) (x << 0)
+/* Vector ops */
+# define R300_VECTOR_NO_OP 0
+# define R300_VE_DOT_PRODUCT 1
+# define R300_VE_MULTIPLY 2
+# define R300_VE_ADD 3
+# define R300_VE_MULTIPLY_ADD 4
+# define R300_VE_DISTANCE_VECTOR 5
+# define R300_VE_FRACTION 6
+# define R300_VE_MAXIMUM 7
+# define R300_VE_MINIMUM 8
+# define R300_VE_SET_GREATER_THAN_EQUAL 9
+# define R300_VE_SET_LESS_THAN 10
+# define R300_VE_MULTIPLYX2_ADD 11
+# define R300_VE_MULTIPLY_CLAMP 12
+# define R300_VE_FLT2FIX_DX 13
+# define R300_VE_FLT2FIX_DX_RND 14
+/* R500 additions */
+# define R500_VE_PRED_SET_EQ_PUSH 15
+# define R500_VE_PRED_SET_GT_PUSH 16
+# define R500_VE_PRED_SET_GTE_PUSH 17
+# define R500_VE_PRED_SET_NEQ_PUSH 18
+# define R500_VE_COND_WRITE_EQ 19
+# define R500_VE_COND_WRITE_GT 20
+# define R500_VE_COND_WRITE_GTE 21
+# define R500_VE_COND_WRITE_NEQ 22
+# define R500_VE_COND_MUX_EQ 23
+# define R500_VE_COND_MUX_GT 24
+# define R500_VE_COND_MUX_GTE 25
+# define R500_VE_SET_GREATER_THAN 26
+# define R500_VE_SET_EQUAL 27
+# define R500_VE_SET_NOT_EQUAL 28
+/* Math ops */
+# define R300_MATH_NO_OP 0
+# define R300_ME_EXP_BASE2_DX 1
+# define R300_ME_LOG_BASE2_DX 2
+# define R300_ME_EXP_BASEE_FF 3
+# define R300_ME_LIGHT_COEFF_DX 4
+# define R300_ME_POWER_FUNC_FF 5
+# define R300_ME_RECIP_DX 6
+# define R300_ME_RECIP_FF 7
+# define R300_ME_RECIP_SQRT_DX 8
+# define R300_ME_RECIP_SQRT_FF 9
+# define R300_ME_MULTIPLY 10
+# define R300_ME_EXP_BASE2_FULL_DX 11
+# define R300_ME_LOG_BASE2_FULL_DX 12
+# define R300_ME_POWER_FUNC_FF_CLAMP_B 13
+# define R300_ME_POWER_FUNC_FF_CLAMP_B1 14
+# define R300_ME_POWER_FUNC_FF_CLAMP_01 15
+# define R300_ME_SIN 16
+# define R300_ME_COS 17
+/* R500 additions */
+# define R500_ME_LOG_BASE2_IEEE 18
+# define R500_ME_RECIP_IEEE 19
+# define R500_ME_RECIP_SQRT_IEEE 20
+# define R500_ME_PRED_SET_EQ 21
+# define R500_ME_PRED_SET_GT 22
+# define R500_ME_PRED_SET_GTE 23
+# define R500_ME_PRED_SET_NEQ 24
+# define R500_ME_PRED_SET_CLR 25
+# define R500_ME_PRED_SET_INV 26
+# define R500_ME_PRED_SET_POP 27
+# define R500_ME_PRED_SET_RESTORE 28
+/* macro */
+# define R300_PVS_MACRO_OP_2CLK_MADD 0
+# define R300_PVS_MACRO_OP_2CLK_M2X_ADD 1
+#define R300_PVS_DST_MATH_INST (1 << 6)
+#define R300_PVS_DST_MACRO_INST (1 << 7)
+#define R300_PVS_DST_REG_TYPE(x) (x << 8)
+# define R300_PVS_DST_REG_TEMPORARY 0
+# define R300_PVS_DST_REG_A0 1
+# define R300_PVS_DST_REG_OUT 2
+# define R500_PVS_DST_REG_OUT_REPL_X 3
+# define R300_PVS_DST_REG_ALT_TEMPORARY 4
+# define R300_PVS_DST_REG_INPUT 5
+#define R300_PVS_DST_ADDR_MODE_1 (1 << 12)
+#define R300_PVS_DST_OFFSET(x) (x << 13)
+#define R300_PVS_DST_WE_X (1 << 20)
+#define R300_PVS_DST_WE_Y (1 << 21)
+#define R300_PVS_DST_WE_Z (1 << 22)
+#define R300_PVS_DST_WE_W (1 << 23)
+#define R300_PVS_DST_VE_SAT (1 << 24)
+#define R300_PVS_DST_ME_SAT (1 << 25)
+#define R300_PVS_DST_PRED_ENABLE (1 << 26)
+#define R300_PVS_DST_PRED_SENSE (1 << 27)
+#define R300_PVS_DST_DUAL_MATH_OP (1 << 28)
+#define R300_PVS_DST_ADDR_SEL(x) (x << 29)
+#define R300_PVS_DST_ADDR_MODE_0 (1 << 31)
+/* src operand instruction */
+#define R300_PVS_SRC_REG_TYPE(x) (x << 0)
+# define R300_PVS_SRC_REG_TEMPORARY 0
+# define R300_PVS_SRC_REG_INPUT 1
+# define R300_PVS_SRC_REG_CONSTANT 2
+# define R300_PVS_SRC_REG_ALT_TEMPORARY 3
+#define R300_SPARE_0 (1 << 2)
+#define R300_PVS_SRC_ABS_XYZW (1 << 3)
+#define R300_PVS_SRC_ADDR_MODE_0 (1 << 4)
+#define R300_PVS_SRC_OFFSET(x) (x << 5)
+#define R300_PVS_SRC_SWIZZLE_X(x) (x << 13)
+#define R300_PVS_SRC_SWIZZLE_Y(x) (x << 16)
+#define R300_PVS_SRC_SWIZZLE_Z(x) (x << 19)
+#define R300_PVS_SRC_SWIZZLE_W(x) (x << 22)
+# define R300_PVS_SRC_SELECT_X 0
+# define R300_PVS_SRC_SELECT_Y 1
+# define R300_PVS_SRC_SELECT_Z 2
+# define R300_PVS_SRC_SELECT_W 3
+# define R300_PVS_SRC_SELECT_FORCE_0 4
+# define R300_PVS_SRC_SELECT_FORCE_1 5
+#define R300_PVS_SRC_NEG_X (1 << 25)
+#define R300_PVS_SRC_NEG_Y (1 << 26)
+#define R300_PVS_SRC_NEG_Z (1 << 27)
+#define R300_PVS_SRC_NEG_W (1 << 28)
+#define R300_PVS_SRC_ADDR_SEL(x) (x << 29)
+#define R300_PVS_SRC_ADDR_MODE_1 (1 << 31)
+
#define R300_VAP_PVS_FLOW_CNTL_OPC 0x22DC
#define R300_VAP_OUT_VTX_FMT_0 0x2090
# define R300_VTX_POS_PRESENT (1 << 0)
@@ -4023,6 +4140,7 @@
# define R300_CLIP_DISABLE (1 << 16)
# define R300_UCP_CULL_ONLY_ENA (1 << 17)
# define R300_BOUNDARY_EDGE_FLAG_ENA (1 << 18)
+#define R300_VAP_PVS_STATE_FLUSH_REG 0x2284
#define R300_SU_TEX_WRAP 0x42a0
#define R300_SU_POLY_OFFSET_ENABLE 0x42b4
@@ -4040,6 +4158,7 @@
# define R300_RS_COUNT_HIRES_EN (1 << 18)
#define R300_RS_IP_0 0x4310
+#define R300_RS_IP_1 0x4314
# define R300_RS_TEX_PTR(x) (x << 0)
# define R300_RS_COL_PTR(x) (x << 6)
# define R300_RS_COL_FMT(x) (x << 9)
@@ -4067,7 +4186,10 @@
# define R300_RS_W_EN (1 << 4)
# define R300_TX_OFFSET_RS(x) (x << 5)
#define R300_RS_INST_0 0x4330
+#define R300_RS_INST_1 0x4334
+# define R300_INST_TEX_ID(x) (x << 0)
# define R300_RS_INST_TEX_CN_WRITE (1 << 3)
+# define R300_INST_TEX_ADDR(x) (x << 6)
#define R300_TX_INVALTAGS 0x4100
#define R300_TX_FILTER0_0 0x4400
@@ -4086,6 +4208,7 @@
# define R300_TX_MIN_FILTER_NEAREST (1 << 11)
# define R300_TX_MAG_FILTER_LINEAR (2 << 9)
# define R300_TX_MIN_FILTER_LINEAR (2 << 11)
+# define R300_TX_ID_SHIFT 28
#define R300_TX_FILTER1_0 0x4440
#define R300_TX_FORMAT0_0 0x4480
# define R300_TXWIDTH_SHIFT 0
@@ -4168,11 +4291,14 @@
# define R300_TX_FORMAT_SWAP_YUV (1 << 24)
#define R300_TX_FORMAT2_0 0x4500
+# define R500_TXWIDTH_11 (1 << 15)
+# define R500_TXHEIGHT_11 (1 << 16)
+
#define R300_TX_OFFSET_0 0x4540
# define R300_ENDIAN_SWAP_16_BIT (1 << 0)
# define R300_ENDIAN_SWAP_32_BIT (2 << 0)
# define R300_ENDIAN_SWAP_HALF_DWORD (3 << 0)
-# define R300_MACRO_TILE (1 << 2);
+# define R300_MACRO_TILE (1 << 2)
#define R300_TX_ENABLE 0x4104
# define R300_TEX_0_ENABLE (1 << 0)
@@ -4193,7 +4319,7 @@
# define R300_OUT_FMT_C2_16_MPEG (7 << 0)
# define R300_OUT_FMT_C2_4 (8 << 0)
# define R300_OUT_FMT_C_3_3_2 (9 << 0)
-# define R300_OUT_FMT_C_6_5_6 (10 << 0)
+# define R300_OUT_FMT_C_5_6_5 (10 << 0)
# define R300_OUT_FMT_C_11_11_10 (11 << 0)
# define R300_OUT_FMT_C_10_11_11 (12 << 0)
# define R300_OUT_FMT_C_2_10_10_10 (13 << 0)
@@ -4241,6 +4367,8 @@
#define R300_US_CODE_ADDR_2 0x4618
#define R300_US_CODE_ADDR_3 0x461c
#define R300_US_TEX_INST_0 0x4620
+#define R300_US_TEX_INST_1 0x4624
+#define R300_US_TEX_INST_2 0x4628
# define R300_TEX_SRC_ADDR(x) (x << 0)
# define R300_TEX_DST_ADDR(x) (x << 6)
# define R300_TEX_ID(x) (x << 11)
@@ -4251,6 +4379,8 @@
# define R300_TEX_INST_PROJ 3
# define R300_TEX_INST_LODBIAS 4
#define R300_US_ALU_RGB_ADDR_0 0x46c0
+#define R300_US_ALU_RGB_ADDR_1 0x46c4
+#define R300_US_ALU_RGB_ADDR_2 0x46c8
/* for ADDR0-2, values 0-31 specify a location in the pixel stack,
values 32-63 specify a constant */
# define R300_ALU_RGB_ADDR0(x) (x << 0)
@@ -4270,6 +4400,8 @@
# define R300_ALU_RGB_TARGET_C (2 << 29)
# define R300_ALU_RGB_TARGET_D (3 << 29)
#define R300_US_ALU_RGB_INST_0 0x48c0
+#define R300_US_ALU_RGB_INST_1 0x48c4
+#define R300_US_ALU_RGB_INST_2 0x48c8
# define R300_ALU_RGB_SEL_A(x) (x << 0)
# define R300_ALU_RGB_SRC0_RGB 0
# define R300_ALU_RGB_SRC0_RRR 1
@@ -4339,6 +4471,8 @@
# define R300_ALU_RGB_CLAMP (1 << 30)
# define R300_ALU_RGB_INSERT_NOP (1 << 31)
#define R300_US_ALU_ALPHA_ADDR_0 0x47c0
+#define R300_US_ALU_ALPHA_ADDR_1 0x47c4
+#define R300_US_ALU_ALPHA_ADDR_2 0x47c8
/* for ADDR0-2, values 0-31 specify a location in the pixel stack,
values 32-63 specify a constant */
# define R300_ALU_ALPHA_ADDR0(x) (x << 0)
@@ -4357,6 +4491,8 @@
# define R300_ALU_ALPHA_TARGET_C (2 << 25)
# define R300_ALU_ALPHA_TARGET_D (3 << 25)
#define R300_US_ALU_ALPHA_INST_0 0x49c0
+#define R300_US_ALU_ALPHA_INST_1 0x49c4
+#define R300_US_ALU_ALPHA_INST_2 0x49c8
# define R300_ALU_ALPHA_SEL_A(x) (x << 0)
# define R300_ALU_ALPHA_SRC0_R 0
# define R300_ALU_ALPHA_SRC0_G 1
@@ -4433,6 +4569,9 @@
#define R300_RB3D_ZTOP 0x4f14
#define R300_RB3D_ROPCNTL 0x4e18
#define R300_RB3D_BLENDCNTL 0x4e04
+# define R300_ALPHA_BLEND_ENABLE (1 << 0)
+# define R300_SEPARATE_ALPHA_ENABLE (1 << 1)
+# define R300_READ_ENABLE (1 << 2)
#define R300_RB3D_ABLENDCNTL 0x4e08
#define R300_RB3D_DSTCACHE_CTLSTAT 0x4e4c
#define R300_RB3D_COLOROFFSET0 0x4e28
@@ -4956,17 +5095,18 @@
#define R500_GA_US_VECTOR_DATA 0x4254
#define R500_RS_INST_0 0x4320
-#define R500_RS_INST_TEX_ID_SHIFT 0
-#define R500_RS_INST_TEX_CN_WRITE (1 << 4)
-#define R500_RS_INST_TEX_ADDR_SHIFT 5
-#define R500_RS_INST_COL_ID_SHIFT 12
-#define R500_RS_INST_COL_CN_NO_WRITE (0 << 16)
-#define R500_RS_INST_COL_CN_WRITE (1 << 16)
-#define R500_RS_INST_COL_CN_WRITE_FBUFFER (2 << 16)
-#define R500_RS_INST_COL_CN_WRITE_BACKFACE (3 << 16)
-#define R500_RS_INST_COL_COL_ADDR_SHIFT 18
-#define R500_RS_INST_TEX_ADJ (1 << 25)
-#define R500_RS_INST_W_CN (1 << 26)
+#define R500_RS_INST_1 0x4324
+# define R500_RS_INST_TEX_ID_SHIFT 0
+# define R500_RS_INST_TEX_CN_WRITE (1 << 4)
+# define R500_RS_INST_TEX_ADDR_SHIFT 5
+# define R500_RS_INST_COL_ID_SHIFT 12
+# define R500_RS_INST_COL_CN_NO_WRITE (0 << 16)
+# define R500_RS_INST_COL_CN_WRITE (1 << 16)
+# define R500_RS_INST_COL_CN_WRITE_FBUFFER (2 << 16)
+# define R500_RS_INST_COL_CN_WRITE_BACKFACE (3 << 16)
+# define R500_RS_INST_COL_COL_ADDR_SHIFT 18
+# define R500_RS_INST_TEX_ADJ (1 << 25)
+# define R500_RS_INST_W_CN (1 << 26)
#define R500_US_FC_CTRL 0x4624
#define R500_US_CODE_ADDR 0x4630
@@ -4974,16 +5114,17 @@
#define R500_US_CODE_OFFSET 0x4638
#define R500_RS_IP_0 0x4074
-#define R500_RS_IP_PTR_K0 62
-#define R500_RS_IP_PTR_K1 63
-#define R500_RS_IP_TEX_PTR_S_SHIFT 0
-#define R500_RS_IP_TEX_PTR_T_SHIFT 6
-#define R500_RS_IP_TEX_PTR_R_SHIFT 12
-#define R500_RS_IP_TEX_PTR_Q_SHIFT 18
-#define R500_RS_IP_COL_PTR_SHIFT 24
-#define R500_RS_IP_COL_FMT_SHIFT 27
-#define R500_RS_IP_COL_FMT_RGBA (0<<27)
-#define R500_RS_IP_OFFSET_EN (1 << 31)
+#define R500_RS_IP_1 0x4078
+# define R500_RS_IP_PTR_K0 62
+# define R500_RS_IP_PTR_K1 63
+# define R500_RS_IP_TEX_PTR_S_SHIFT 0
+# define R500_RS_IP_TEX_PTR_T_SHIFT 6
+# define R500_RS_IP_TEX_PTR_R_SHIFT 12
+# define R500_RS_IP_TEX_PTR_Q_SHIFT 18
+# define R500_RS_IP_COL_PTR_SHIFT 24
+# define R500_RS_IP_COL_FMT_SHIFT 27
+# define R500_RS_IP_COL_FMT_RGBA (0 << 27)
+# define R500_RS_IP_OFFSET_EN (1 << 31)
#endif
diff --git a/src/radeon_render.c b/src/radeon_render.c
index a80d136..950753c 100644
--- a/src/radeon_render.c
+++ b/src/radeon_render.c
@@ -250,10 +250,17 @@ static __inline__ int
ATILog2(int val)
{
int bits;
-
+#if (defined __i386__ || defined __x86_64__) && (defined __GNUC__)
+ __asm volatile("bsrl %1, %0"
+ : "=r" (bits)
+ : "c" (val)
+ );
+ return bits;
+#else
for (bits = 0; val != 0; val >>= 1, ++bits)
;
return bits - 1;
+#endif
}
static void
diff --git a/src/radeon_textured_video.c b/src/radeon_textured_video.c
index 329a834..0a6598d 100644
--- a/src/radeon_textured_video.c
+++ b/src/radeon_textured_video.c
@@ -46,6 +46,9 @@
#define IMAGE_MAX_WIDTH 2048
#define IMAGE_MAX_HEIGHT 2048
+#define IMAGE_MAX_WIDTH_R500 4096
+#define IMAGE_MAX_HEIGHT_R500 4096
+
static Bool
RADEONTilingEnabled(ScrnInfoPtr pScrn, PixmapPtr pPix)
{
@@ -60,7 +63,7 @@ RADEONTilingEnabled(ScrnInfoPtr pScrn, PixmapPtr pPix)
} else
#endif
{
- if (info->tilingEnabled)
+ if (info->tilingEnabled && ((pPix->devPrivate.ptr - info->FB) == 0))
return TRUE;
else
return FALSE;
@@ -300,6 +303,16 @@ static XF86VideoEncodingRec DummyEncoding[1] =
}
};
+static XF86VideoEncodingRec DummyEncodingR500[1] =
+{
+ {
+ 0,
+ "XV_IMAGE",
+ IMAGE_MAX_WIDTH_R500, IMAGE_MAX_HEIGHT_R500,
+ {1, 1}
+ }
+};
+
#define NUM_FORMATS 3
static XF86VideoFormatRec Formats[NUM_FORMATS] =
@@ -326,6 +339,8 @@ static XF86ImageRec Images[NUM_IMAGES] =
XF86VideoAdaptorPtr
RADEONSetupImageTexturedVideo(ScreenPtr pScreen)
{
+ ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum];
+ RADEONInfoPtr info = RADEONPTR(pScrn);
RADEONPortPrivPtr pPortPriv;
XF86VideoAdaptorPtr adapt;
int i;
@@ -340,7 +355,10 @@ RADEONSetupImageTexturedVideo(ScreenPtr pScreen)
adapt->flags = 0;
adapt->name = "Radeon Textured Video";
adapt->nEncodings = 1;
- adapt->pEncodings = DummyEncoding;
+ if (IS_R500_3D)
+ adapt->pEncodings = DummyEncodingR500;
+ else
+ adapt->pEncodings = DummyEncoding;
adapt->nFormats = NUM_FORMATS;
adapt->pFormats = Formats;
adapt->nPorts = num_texture_ports;
diff --git a/src/radeon_textured_videofuncs.c b/src/radeon_textured_videofuncs.c
index 4ebb73b..d4a3343 100644
--- a/src/radeon_textured_videofuncs.c
+++ b/src/radeon_textured_videofuncs.c
@@ -80,10 +80,9 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
CARD32 txenable, colorpitch;
CARD32 blendcntl;
int dstxoff, dstyoff, pixel_shift;
- VIDEO_PREAMBLE();
-
BoxPtr pBox = REGION_RECTS(&pPriv->clip);
int nBox = REGION_NUM_RECTS(&pPriv->clip);
+ VIDEO_PREAMBLE();
pixel_shift = pPixmap->drawable.bitsPerPixel >> 4;
@@ -130,7 +129,8 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
if (IS_R300_VARIANT || IS_AVIVO_VARIANT) {
int has_tcl = ((info->ChipFamily != CHIP_FAMILY_RS690) &&
(info->ChipFamily != CHIP_FAMILY_RS740) &&
- (info->ChipFamily != CHIP_FAMILY_RS400));
+ (info->ChipFamily != CHIP_FAMILY_RS400) &&
+ (info->ChipFamily != CHIP_FAMILY_RV515));
switch (pPixmap->drawable.bitsPerPixel) {
case 16:
@@ -159,8 +159,8 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
txformat1 |= R300_TX_FORMAT_YUV_TO_RGB_CLAMP;
- txformat0 = (((pPriv->w - 1) << R300_TXWIDTH_SHIFT) |
- ((pPriv->h - 1) << R300_TXHEIGHT_SHIFT));
+ txformat0 = ((((pPriv->w - 1) & 0x7ff) << R300_TXWIDTH_SHIFT) |
+ (((pPriv->h - 1) & 0x7ff) << R300_TXHEIGHT_SHIFT));
txformat0 |= R300_TXPITCH_EN;
@@ -175,6 +175,12 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
txpitch = pPriv->src_pitch / 2;
txpitch -= 1;
+ if (IS_R500_3D && ((pPriv->w - 1) & 0x800))
+ txpitch |= R500_TXWIDTH_11;
+
+ if (IS_R500_3D && ((pPriv->h - 1) & 0x800))
+ txpitch |= R500_TXHEIGHT_11;
+
txoffset = pPriv->src_offset;
BEGIN_VIDEO(6);
@@ -268,16 +274,64 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
OUT_VIDEO_REG(R300_VAP_PVS_CODE_CNTL_1,
(1 << R300_PVS_LAST_VTX_SRC_INST_SHIFT));
OUT_VIDEO_REG(R300_VAP_PVS_VECTOR_INDX_REG, 0);
- OUT_VIDEO_REG(R300_VAP_PVS_VECTOR_DATA_REG,0x00f00203);
- OUT_VIDEO_REG(R300_VAP_PVS_VECTOR_DATA_REG,0x00d10001);
- OUT_VIDEO_REG(R300_VAP_PVS_VECTOR_DATA_REG,0x01248001);
- OUT_VIDEO_REG(R300_VAP_PVS_VECTOR_DATA_REG,0x01248001);
- OUT_VIDEO_REG(R300_VAP_PVS_VECTOR_DATA_REG,0x00f02203);
- OUT_VIDEO_REG(R300_VAP_PVS_VECTOR_DATA_REG,0x00d10141);
- OUT_VIDEO_REG(R300_VAP_PVS_VECTOR_DATA_REG,0x01248141);
- OUT_VIDEO_REG(R300_VAP_PVS_VECTOR_DATA_REG,0x01248141);
- OUT_VIDEO_REG(R300_VAP_PVS_FLOW_CNTL_OPC, 0);
+ OUT_VIDEO_REG(R300_VAP_PVS_VECTOR_DATA_REG,
+ (R300_PVS_DST_OPCODE(R300_VE_ADD) |
+ R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_OUT) |
+ R300_PVS_DST_OFFSET(0) |
+ R300_PVS_DST_WE_X | R300_PVS_DST_WE_Y |
+ R300_PVS_DST_WE_Z | R300_PVS_DST_WE_W));
+ OUT_VIDEO_REG(R300_VAP_PVS_VECTOR_DATA_REG,
+ (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
+ R300_PVS_SRC_OFFSET(0) |
+ R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) |
+ R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) |
+ R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_Z) |
+ R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_W)));
+ OUT_VIDEO_REG(R300_VAP_PVS_VECTOR_DATA_REG,
+ (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
+ R300_PVS_SRC_OFFSET(0) |
+ R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) |
+ R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) |
+ R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
+ R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
+ OUT_VIDEO_REG(R300_VAP_PVS_VECTOR_DATA_REG,
+ (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
+ R300_PVS_SRC_OFFSET(0) |
+ R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) |
+ R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) |
+ R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
+ R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
+
+ OUT_VIDEO_REG(R300_VAP_PVS_VECTOR_DATA_REG,
+ (R300_PVS_DST_OPCODE(R300_VE_ADD) |
+ R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_OUT) |
+ R300_PVS_DST_OFFSET(1) |
+ R300_PVS_DST_WE_X | R300_PVS_DST_WE_Y |
+ R300_PVS_DST_WE_Z | R300_PVS_DST_WE_W));
+ OUT_VIDEO_REG(R300_VAP_PVS_VECTOR_DATA_REG,
+ (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
+ R300_PVS_SRC_OFFSET(10) |
+ R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) |
+ R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) |
+ R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_Z) |
+ R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_W)));
+ OUT_VIDEO_REG(R300_VAP_PVS_VECTOR_DATA_REG,
+ (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
+ R300_PVS_SRC_OFFSET(10) |
+ R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) |
+ R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) |
+ R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
+ R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
+ OUT_VIDEO_REG(R300_VAP_PVS_VECTOR_DATA_REG,
+ (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) |
+ R300_PVS_SRC_OFFSET(10) |
+ R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) |
+ R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) |
+ R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) |
+ R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0)));
+
+ OUT_VIDEO_REG(R300_VAP_PVS_FLOW_CNTL_OPC, 0);
OUT_VIDEO_REG(R300_VAP_GB_VERT_CLIP_ADJ, 0x3f800000);
OUT_VIDEO_REG(R300_VAP_GB_VERT_DISC_ADJ, 0x3f800000);
@@ -291,9 +345,7 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
FINISH_VIDEO();
/* setup pixel shader */
- if (IS_R300_VARIANT ||
- (info->ChipFamily == CHIP_FAMILY_RS690) ||
- (info->ChipFamily == CHIP_FAMILY_RS740)) {
+ if (IS_R300_3D) {
BEGIN_VIDEO(16);
OUT_VIDEO_REG(R300_RS_COUNT,
((2 << R300_RS_COUNT_IT_COUNT_SHIFT) |
@@ -361,7 +413,8 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
R300_ALU_RGB_SEL_C(R300_ALU_RGB_0_0) |
R300_ALU_RGB_MOD_C(R300_ALU_RGB_MOD_NOP) |
R300_ALU_RGB_OP(R300_ALU_RGB_OP_MAD) |
- R300_ALU_RGB_OMOD(R300_ALU_RGB_OMOD_NONE)));
+ R300_ALU_RGB_OMOD(R300_ALU_RGB_OMOD_NONE) |
+ R300_ALU_RGB_CLAMP));
OUT_VIDEO_REG(R300_US_ALU_ALPHA_ADDR_0,
(R300_ALU_ALPHA_ADDR0(0) |
R300_ALU_ALPHA_ADDR1(0) |
@@ -379,7 +432,8 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
R300_ALU_ALPHA_SEL_C(R300_ALU_ALPHA_0_0) |
R300_ALU_ALPHA_MOD_C(R300_ALU_ALPHA_MOD_NOP) |
R300_ALU_ALPHA_OP(R300_ALU_ALPHA_OP_MAD) |
- R300_ALU_ALPHA_OMOD(R300_ALU_ALPHA_OMOD_NONE)));
+ R300_ALU_ALPHA_OMOD(R300_ALU_ALPHA_OMOD_NONE) |
+ R300_ALU_ALPHA_CLAMP));
FINISH_VIDEO();
} else {
BEGIN_VIDEO(23);
@@ -408,7 +462,9 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
R500_INST_RGB_WMASK_R |
R500_INST_RGB_WMASK_G |
R500_INST_RGB_WMASK_B |
- R500_INST_ALPHA_WMASK));
+ R500_INST_ALPHA_WMASK |
+ R500_INST_RGB_CLAMP |
+ R500_INST_ALPHA_CLAMP));
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_ID(0) |
R500_TEX_INST_LD |
@@ -443,7 +499,9 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
R500_INST_RGB_OMASK_R |
R500_INST_RGB_OMASK_G |
R500_INST_RGB_OMASK_B |
- R500_INST_ALPHA_OMASK));
+ R500_INST_ALPHA_OMASK |
+ R500_INST_RGB_CLAMP |
+ R500_INST_ALPHA_CLAMP));
OUT_VIDEO_REG(R500_GA_US_VECTOR_DATA, (R500_RGB_ADDR0(0) |
R500_RGB_ADDR1(0) |
diff --git a/src/theatre_detect.c b/src/theatre_detect.c
index d4c6ce8..79dcfe4 100644
--- a/src/theatre_detect.c
+++ b/src/theatre_detect.c
@@ -43,6 +43,7 @@
#include "generic_bus.h"
#include "theatre.h"
#include "theatre_reg.h"
+#include "theatre_detect.h"
static Bool theatre_read(TheatrePtr t,CARD32 reg, CARD32 *data)
{
generated by cgit v1.2.3 (git 2.25.1) at 2025-07-25 23:24:46 +0000