diff options
Diffstat (limited to 'contrib')
86 files changed, 39191 insertions, 0 deletions
diff --git a/contrib/Makefile.am b/contrib/Makefile.am index e7fdf5de5..acbdde39a 100644 --- a/contrib/Makefile.am +++ b/contrib/Makefile.am @@ -1,6 +1,19 @@ SUBDIRS = libmpcdec libxdg-basedir libdca nosefart gsm610 libmad a52dec \ libfaad + +if BUILD_DHA_KMOD +SUBDIRS += libdha +endif + +# vidix depends on portions of dha +if ENABLE_VIDIX +if !BUILD_DHA_KMOD +SUBDIRS += libdha +endif +SUBDIRS += vidix +endif + srcdir = $(shell cd @srcdir@; pwd) ffmpeg_builder = $(srcdir)/ffmpeg-universal.sh diff --git a/contrib/libdha/.hgignore b/contrib/libdha/.hgignore new file mode 100644 index 000000000..7b5ba91fb --- /dev/null +++ b/contrib/libdha/.hgignore @@ -0,0 +1,9 @@ +.libs +.deps +*.lo +*.la +pci_dev_ids.c +pci_ids.h +pci_names.c +pci_names.h +pci_vendors.h diff --git a/contrib/libdha/AsmMacros.h b/contrib/libdha/AsmMacros.h new file mode 100644 index 000000000..d1b136a7b --- /dev/null +++ b/contrib/libdha/AsmMacros.h @@ -0,0 +1,119 @@ +/* $XConsortium: AsmMacros.h /main/13 1996/10/25 11:33:12 kaleb $ */ +/* + * (c) Copyright 1993,1994 by David Wexelblat <dwex@xfree86.org> + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * DAVID WEXELBLAT BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF + * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + * + * Except as contained in this notice, the name of David Wexelblat shall not be + * used in advertising or otherwise to promote the sale, use or other dealings + * in this Software without prior written authorization from David Wexelblat. + * + */ +/* + * Copyright 1997 + * Digital Equipment Corporation. All rights reserved. + * This software is furnished under license and may be used and copied only in + * accordance with the following terms and conditions. Subject to these + * conditions, you may download, copy, install, use, modify and distribute + * this software in source and/or binary form. No title or ownership is + * transferred hereby. + * + * 1) Any source code used, modified or distributed must reproduce and retain + * this copyright notice and list of conditions as they appear in the source + * file. + * + * 2) No right is granted to use any trade name, trademark, or logo of Digital + * Equipment Corporation. Neither the "Digital Equipment Corporation" name + * nor any trademark or logo of Digital Equipment Corporation may be used + * to endorse or promote products derived from this software without the + * prior written permission of Digital Equipment Corporation. + * + * 3) This software is provided "AS-IS" and any express or implied warranties, + * including but not limited to, any implied warranties of merchantability, + * fitness for a particular purpose, or non-infringement are disclaimed. In + * no event shall DIGITAL be liable for any damages whatsoever, and in + * particular, DIGITAL shall not be liable for special, indirect, + * consequential, or incidental damages or damages for + * lost profits, loss of revenue or loss of use, whether such damages arise + * in contract, + * negligence, tort, under statute, in equity, at law or otherwise, even if + * advised of the possibility of such damage. + * + */ + +/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/chips/util/AsmMacros.h,v 1.1 2001/11/16 21:13:34 tsi Exp $ */ + +/* + * Modified for readability by Nick Kurshev +*/ + +#if defined(__GNUC__) || defined(__ICC) +#if defined(__alpha__) +#include "sysdep/AsmMacros_alpha.h" +#elif defined(__ia64__) +#include "sysdep/AsmMacros_ia64.h" +#elif defined(__sparc__) +#include "sysdep/AsmMacros_sparc.h" +#elif defined( __arm32__ ) +#include "sysdep/AsmMacros_arm32.h" +#elif defined(__powerpc__) +#include "sysdep/AsmMacros_powerpc.h" +#elif defined (__i386__) +#include "sysdep/AsmMacros_x86.h" +#else +#include "sysdep/AsmMacros_generic.h" +#endif + +#else /* __GNUC__ */ + +#if defined(_MINIX) && defined(_ACK) + +/* inb, outb, inw and outw are defined in the library */ +/* ... but I've no idea if the same is true for inl & outl */ + +extern u8_t inb(U16_t); +extern void outb(U16_t, U8_t); +extern u16_t inw(U16_t); +extern void outw(U16_t, U16_t); +extern u32_t inl(U16_t); +extern void outl(U16_t, U32_t); + +#else /* not _MINIX and _ACK */ + +# if defined(__STDC__) && (__STDC__ == 1) +# ifndef NCR +# define asm __asm +# endif +# endif +# ifdef SVR4 +# include <sys/types.h> +# ifndef __USLC__ +# define __USLC__ +# endif +# endif +#ifndef SCO325 +# include <sys/inline.h> +#else +# include "../common/scoasm.h" +#endif +#define intr_disable() asm("cli") +#define intr_enable() asm("sti") + +#endif /* _MINIX and _ACK */ +#endif /* __GNUC__ */ diff --git a/contrib/libdha/Makefile.am b/contrib/libdha/Makefile.am new file mode 100644 index 000000000..05aebb704 --- /dev/null +++ b/contrib/libdha/Makefile.am @@ -0,0 +1,44 @@ +include $(top_srcdir)/misc/Makefile.common + +SUBDIRS = bin oth sysdep + +if BUILD_DHA_KMOD +SUBDIRS += kernelhelper +endif + +AM_CFLAGS = $(DEFAULT_OCFLAGS) + +EXTRA_DIST = README pci_db2c.awk + +awk_generated = pci_dev_ids.c pci_ids.h pci_names.c pci_names.h pci_vendors.h +CLEANFILES = $(awk_generated) + +noinst_HEADERS = AsmMacros.h libdha.h pci_ids.h pci_names.h pci_vendors.h + +if ENABLE_VIDIX +noinst_LTLIBRARIES = libdha.la +endif + +libdha_la_SOURCES = libdha.c mtrr.c pci.c mmi.c ports.c irq.c cpu_flush.c +nodist_libdha_la_SOURCES = pci_names.c + +EXTRA_PROGRAMS = test + +test_SOURCES = test.c +test_LDADD = $(top_builddir)/src/video_out/libdha/libdha.la + +## for OpenBSD LIBS += -li386 + +## We have to create some files, on the fly, this is why this rule is needed. +pci_db2c.awk: +oth/pci.db: + +$(awk_generated): pci_db2c.awk oth/pci.db + LC_ALL=C $(AWK) -f $(top_srcdir)/src/video_out/libdha/pci_db2c.awk \ + $(top_srcdir)/src/video_out/libdha/oth/pci.db + +pci_names.lo: $(awk_generated) + source='$*.c' object='$@' libtool=yes \ + depfile='$(DEPDIR)/$*.Plo' tmpdepfile='$(DEPDIR)/$*.TPlo' \ + $(CCDEPMODE) $(depcomp) \ + $(LTCOMPILE) -c -o $@ `test -f $*.c || echo '$(srcdir)/'`$*.c diff --git a/contrib/libdha/README b/contrib/libdha/README new file mode 100644 index 000000000..a855880cd --- /dev/null +++ b/contrib/libdha/README @@ -0,0 +1,12 @@ +libdha - Library of Direct Hardware Access. +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +This library was designed for direct hardware access under different +OS and architectures. It's not linux specific only (like harddrake +and other). + +This library is based on gfxdump utility from GATOS project. +Full list of supported OS'es see in libdha.h + +Note: This library requires ROOT privileges or SUID'ed executable +file (same as XServer). +(Or use newly developed libdha kernel helper. Look at kernelhelper/dhahelper.c) diff --git a/contrib/libdha/bin/Makefile.am b/contrib/libdha/bin/Makefile.am new file mode 100644 index 000000000..24c6d3abf --- /dev/null +++ b/contrib/libdha/bin/Makefile.am @@ -0,0 +1,3 @@ +include $(top_srcdir)/misc/Makefile.common + +EXTRA_DIST = README mapdev.copyright mapdev.vxd diff --git a/contrib/libdha/bin/README b/contrib/libdha/bin/README new file mode 100644 index 000000000..fe4bfa6f3 --- /dev/null +++ b/contrib/libdha/bin/README @@ -0,0 +1,6 @@ +mapdev.vxd +~~~~~~~~~~ +mapdev.vxd - provides direct hardware access under Win9x. +install: Just copy it into %WINDOWS%\system folder and reboot. +note: This driver won't work under NT-based systems +(like WinNT, Win2000 and even WinME and WinXP due importing NT things). diff --git a/contrib/libdha/bin/mapdev.copyright b/contrib/libdha/bin/mapdev.copyright new file mode 100644 index 000000000..b22433d29 --- /dev/null +++ b/contrib/libdha/bin/mapdev.copyright @@ -0,0 +1,70 @@ +From khazzah@melita.com Mon Jun 23 21:48:19 1997 +Return-Path: <khazzah@melita.com> +Received: from melita.melita.com by max4.rrze.uni-erlangen.de; Mon, 23 Jun 1997 21:48:16 +0200 +Received: from mailgate.melita.com ([192.68.22.8]) by melita.melita.com (8.6.12/8.6.9) with SMTP id QAA29292 for <Stefan.Dirsch@stud.uni-erlangen.de>; Mon, 23 Jun 1997 16:17:55 -0400 +Received: by mailgate.melita.com with Microsoft Mail + id <33AEFD34@mailgate.melita.com>; Mon, 23 Jun 97 15:48:20 PDT +From: Karen Hazzah <khazzah@melita.com> +To: "'Stefan.Dirsch@stud.uni-erlangen.de'" <Stefan.Dirsch@stud.uni-erlangen.de> +Subject: Your post to vxd newsgroup +Date: Sun, 22 Jun 97 20:51:00 PDT +Message-ID: <33AEFD34@mailgate.melita.com> +Encoding: 22 TEXT +X-Mailer: Microsoft Mail V3.0 + + +I posted an answer to your question in the newsgroup. I also have +additional information for you. + +I can email you the binary for VxD which does exactly what you need: +given a physical address, returns a pointer that can be used by a +Win32 application. I'll also give you source for a Win32 app which +uses the VxD to read an area of physical memory. + +I don't offer this solution to everyone, since in most cases the +proper solution is for them to write a VxD which interacts with their +hardware, rather than simply getting a pointer to the hardware and +interacting with it from an application. + +However, in your case, you're just using a VxD as a tool to get your +Linux driver working...you shouldn't have to write a VxD for this :-) + +Let me know if you're interested. +=============================================================================== +Hello Karen + +A long time ago, you sent me your VXD for reading an area of physical +memory under Win32, so I could make register dumps of the graphic +chip. Did I ever mention, that it works perfectly for me? + +Why I contact you is, that I really would like to offer this solution +to all XFree86 members, so that it will be much easier in the future +for XFree86 to develop drivers for graphic boards. + +Can I count with your agreement? Would you like to add a special +copyright to your software? + +Stefan +=============================================================================== +From KHazzah@melita.com Wed Mar 4 00:00:28 1998 +Return-Path: <KHazzah@melita.com> +Received: from melita.melita.com (melita.com [192.68.22.2]) + by Galois.suse.de (8.8.8/8.8.8) with SMTP id AAA03709 + for <sndirsch@suse.de>; Wed, 4 Mar 1998 00:00:26 +0100 +Received: from norcross.melita.com (norcross.melita.com [192.68.22.10]) by melita.melita.com (8.6.12/8.6.9) with ESMTP id TAA31217 for <sndirsch@suse.de>; Tue, 3 Mar 1998 19:48:10 -0500 +Received: by zippy.melita.com with Internet Mail Service (5.5.1960.3) + id <F5X7MBSS>; Tue, 3 Mar 1998 18:00:26 -0500 +Message-ID: <D8EE8292EB83D111A15E00805FA67447166532@zippy.melita.com> +From: "Hazzah, Karen" <KHazzah@melita.com> +To: Stefan Dirsch <sndirsch@suse.de> +Subject: RE: VXD binary for Win32 for reading an area of physical memory +Date: Tue, 3 Mar 1998 18:00:25 -0500 +MIME-Version: 1.0 +X-Mailer: Internet Mail Service (5.5.1960.3) +Content-Type: text/plain +Status: ROr + +OK, you have my permission to make it publicly available, as is. + +If you make it available on the web (ftp, etc.), please give me the +URL so I can refer others to it. diff --git a/contrib/libdha/bin/mapdev.vxd b/contrib/libdha/bin/mapdev.vxd Binary files differnew file mode 100644 index 000000000..e09194b84 --- /dev/null +++ b/contrib/libdha/bin/mapdev.vxd diff --git a/contrib/libdha/cpu_flush.c b/contrib/libdha/cpu_flush.c new file mode 100644 index 000000000..9186f89e8 --- /dev/null +++ b/contrib/libdha/cpu_flush.c @@ -0,0 +1,23 @@ +/* CPU flush support */ +#include <stdio.h> +#include <sys/ioctl.h> +#include <errno.h> +#include <unistd.h> +#include <fcntl.h> +#include "libdha.h" +#include "kernelhelper/dhahelper.h" + +void cpu_flush(void *va,unsigned long length) +{ + int retval; + int libdha_fd=-1; + if( libdha_fd == -1) libdha_fd = open("/dev/dhahelper",O_RDWR); + if (libdha_fd > 0) + { + dhahelper_cpu_flush_t _l2; + _l2.va = va; + _l2.length = length; + retval = ioctl(libdha_fd, DHAHELPER_CPU_FLUSH, &_l2); + close(libdha_fd); + } +} diff --git a/contrib/libdha/irq.c b/contrib/libdha/irq.c new file mode 100644 index 000000000..abccaf74c --- /dev/null +++ b/contrib/libdha/irq.c @@ -0,0 +1,63 @@ +/* HW IRQ support */ +#include <stdio.h> +#include <sys/ioctl.h> +#include <sys/types.h> +#include <sys/mman.h> /* mlock */ +#include <pthread.h> +#include <errno.h> +#include <unistd.h> +#include <fcntl.h> +#include "libdha.h" +#include "kernelhelper/dhahelper.h" + + +static int libdha_fd=-1; +static int hwirq_locks=0; + +int hwirq_install(int bus, int dev, int func, + int ar, u_long ao, uint32_t ad) +{ + int retval; + if( libdha_fd == -1) libdha_fd = open("/dev/dhahelper",O_RDWR); + hwirq_locks++; + if (libdha_fd > 0) + { + dhahelper_irq_t _irq; + _irq.bus = bus; + _irq.dev = dev; + _irq.func = func; + _irq.ack_region = ar; + _irq.ack_offset = ao; + _irq.ack_data = ad; + retval = ioctl(libdha_fd, DHAHELPER_INSTALL_IRQ, &_irq); + return retval; + } + return errno; +} + +int hwirq_wait(unsigned irqnum) +{ + int retval; + if (libdha_fd > 0) + { + dhahelper_irq_t _irq; + _irq.num = irqnum; + retval = ioctl(libdha_fd, DHAHELPER_ACK_IRQ, &_irq); + return retval; + } + return EINVAL; +} + +int hwirq_uninstall(int bus, int dev, int func) +{ + if (libdha_fd > 0) + { + dhahelper_irq_t _irq; + _irq.bus = bus; + _irq.dev = dev; + _irq.func = func; + ioctl(libdha_fd, DHAHELPER_FREE_IRQ, &_irq); + } + if(!hwirq_locks) { close(libdha_fd); libdha_fd=-1; } + return 0; +} diff --git a/contrib/libdha/kernelhelper/Makefile.am b/contrib/libdha/kernelhelper/Makefile.am new file mode 100644 index 000000000..fffaab433 --- /dev/null +++ b/contrib/libdha/kernelhelper/Makefile.am @@ -0,0 +1,50 @@ +include $(top_srcdir)/misc/Makefile.common + +EXTRA_DIST = README dhahelper.c + +KCFLAGS = -O2 -Wall -D__KERNEL__ -DMODULE -include `echo $(LINUX_INCLUDE) | sed -e 's/\-I//g'`/linux/modversions.h + +KVERSION = $(shell $(SHELL) -c 'uname -r') +moddir = /lib/modules/$(KVERSION)/misc + +KCOMPILE = $(CC) $(CFLAGS) $(KCFLAGS) $(INCLUDES) $(LINUX_INCLUDE) + +if HAVE_LINUX +KERNEL_MODULE = dhahelper.o +endif + +noinst_HEADERS = dhahelper.h + +EXTRA_PROGRAMS = test +test_SOURCES = test.c + +dhahelper.o: + $(KCOMPILE) -c `test -f $*.c || echo '$(srcdir)/'`$*.c + +nodes: + $(MKNOD) -m 666 /dev/dhahelper c 252 0 + +all: $(KERNEL_MODULE) + +install-exec-local: $(KERNEL_MODULE) + @$(NORMAL_INSTALL) + $(mkinstalldirs) $(DESTDIR)$(moddir) + @list='$(KERNEL_MODULE)'; \ + for p in $$list; do \ + if test -f $$p; then \ + echo "$(INSTALL) -o root -g root -m 644 $$p $(DESTDIR)$(moddir)/$$p"; \ + $(INSTALL) -o root -g root -m 644 $$p $(DESTDIR)$(moddir)/$$p; \ + else :; fi; \ + done; \ + $(DEPMOD) -a + if test ! -c /dev/dhahelper; then \ + $(MAKE) nodes; \ + fi + +uninstall-local: + @$(NORMAL_UNINSTALL) + @list='$(KERNEL_MODULE)'; \ + for p in $$list; do \ + echo "rm -f $(DESTDIR)$(moddir)/`echo $$p|sed 's/$(EXEEXT)$$//'|sed '$(transform)'|sed 's/$$/$(EXEEXT)/'`"; \ + rm -f $(DESTDIR)$(moddir)/`echo $$p|sed 's/$(EXEEXT)$$//'|sed '$(transform)'|sed 's/$$/$(EXEEXT)/'`; \ + done diff --git a/contrib/libdha/kernelhelper/README b/contrib/libdha/kernelhelper/README new file mode 100644 index 000000000..98a7923b3 --- /dev/null +++ b/contrib/libdha/kernelhelper/README @@ -0,0 +1,38 @@ +dhahelper is small driver to provide some kernel function into userspace. +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +The main reason you need to use dhahelper is for busmastering. +(Btw, lacking of possibility to implement conversion of +virtual addresses into physical in userspace caused +implementing of so-called DRM drivers for Linux from +XFree86 side). +Second goal (still is unfinished) - provide possibility +to control port and physical memory access through +groups and access rights of this driver. (Unix way). + +Installation: +~~~~~~~~~~~~~ +just type in this directory: +make all install + +The device node /dev/dhahelper will be created. The initial +permissions of this node are restrictive. See below for information +on how to make it available to non-root users. + +Porting: +~~~~~~~~ +This driver was developed only for Linux. +So if someone will port that on other unices +then any patches are gladly accepted. + +WARNING: +~~~~~~~~ + +This driver violates some kernel security rules. To keep this driver +from anonymous access I suggest you create a new group (e.g. dha) for +/dev/dhahelper and set the permissions to 660 (or ug+rw,o-rw). Then +do one of the following: + +- add trusted users to group dha. +- make trusted applications SGID to dha. + +Good luck! diff --git a/contrib/libdha/kernelhelper/dhahelper.c b/contrib/libdha/kernelhelper/dhahelper.c new file mode 100644 index 000000000..0e755064a --- /dev/null +++ b/contrib/libdha/kernelhelper/dhahelper.c @@ -0,0 +1,1239 @@ +/* + Direct Hardware Access kernel helper + + (C) 2002 Alex Beregszaszi <alex@naxine.org> + (C) 2002-2003 Nick Kurshev <nickols_k@mail.ru> + (C) 2002-2004 MÃ¥ns RullgÃ¥rd <mru@users.sourceforge.net> + + Accessing hardware from userspace as USER (no root needed!) + + Tested on 2.2.x (2.2.19), 2.4.x (2.4.3,2.4.17) and 2.6.1. + + License: GPL + + WARNING! THIS MODULE VIOLATES SEVERAL SECURITY LINES! DON'T USE IT + ON PRODUCTION SYSTEMS, ONLY AT HOME, ON A "SINGLE-USER" SYSTEM. + NO WARRANTY! + + IF YOU WANT TO USE IT ON PRODUCTION SYSTEMS THEN PLEASE READ 'README' + FILE TO KNOW HOW TO PREVENT ANONYMOUS ACCESS TO THIS MODULE. + + Tech: + Communication between userspace and kernelspace goes over character + device using ioctl. + + Usage: + mknod -m 600 /dev/dhahelper c 252 0 + + Also you can change the major number, setting the "dhahelper_major" + module parameter, the default is 252, specified in dhahelper.h. + + Note: do not use other than minor==0, the module forbids it. + + TODO: + * select (request?) a "valid" major number (from Linux project? ;) + * make security + * is pci handling needed? (libdha does this with lowlevel port funcs) + * is mttr handling needed? + * test on older kernels (2.0.x (?)) +*/ + +#ifndef MODULE +#define MODULE +#endif + +#ifndef __KERNEL__ +#define __KERNEL__ +#endif + +#include <linux/config.h> + +#ifdef CONFIG_MODVERSION +#define MODVERSION +#include <linux/modversions.h> +#endif + +#include <linux/version.h> +#include <linux/module.h> +#include <linux/types.h> +#include <linux/kernel.h> +#include <linux/sched.h> +#include <linux/mm.h> +#include <linux/pagemap.h> +#include <linux/init.h> +#include <linux/pci.h> +#include <linux/interrupt.h> +#include <linux/vmalloc.h> +#include <linux/string.h> +#include <linux/errno.h> +#include <asm/io.h> +#include <asm/pgtable.h> +#include <asm/unistd.h> +#include <asm/uaccess.h> + +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,4,0) +#include <linux/malloc.h> +#else +#include <linux/slab.h> +#endif + +#include <linux/pci.h> +#include <linux/ioport.h> +#include <linux/init.h> + +#include <asm/uaccess.h> +#include <asm/system.h> +#include <asm/io.h> + +#include <linux/mman.h> + +#include <linux/fs.h> +#include <linux/unistd.h> + +#ifdef CONFIG_MTRR +#include <asm/mtrr.h> +#endif +#ifdef CONFIG_DEVFS_FS +#include <linux/devfs_fs_kernel.h> +#endif + +#include "dhahelper.h" + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0) +#define pte_offset(p,a) pte_offset_kernel(p,a) +#define LockPage(p) SetPageLocked(p) +#define UnlockPage(p) ClearPageLocked(p) +#define irqreturn(n) return(n) +#else +#define irqreturn_t void +#define irqreturn(n) return +#endif + +MODULE_AUTHOR("Alex Beregszaszi <alex@naxine.org>, Nick Kurshev <nickols_k@mail.ru>, MÃ¥ns RullgÃ¥rd <mru@users.sf.net>"); +MODULE_DESCRIPTION("Provides userspace access to hardware"); +#ifdef MODULE_LICENSE +MODULE_LICENSE("GPL"); +#endif + +static int dhahelper_major = DEFAULT_MAJOR; +MODULE_PARM(dhahelper_major, "i"); +MODULE_PARM_DESC(dhahelper_major, "Major number of dhahelper characterdevice"); + +/* 0 = silent */ +/* 1 = report errors (default) */ +/* 2 = debug */ +static int dhahelper_verbosity = 1; +MODULE_PARM(dhahelper_verbosity, "i"); +MODULE_PARM_DESC(dhahelper_verbosity, "Level of verbosity (0 = silent, 1 = only errors, 2 = debug)"); + +static int dhahelper_open(struct inode *inode, struct file *file) +{ + if (dhahelper_verbosity > 1) + printk(KERN_DEBUG "dhahelper: device opened\n"); + + if (MINOR(inode->i_rdev) != 0) + return -ENXIO; + +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,4,0) + MOD_INC_USE_COUNT; +#endif + + return 0; +} + +static int dhahelper_release(struct inode *inode, struct file *file) +{ + if (dhahelper_verbosity > 1) + printk(KERN_DEBUG "dhahelper: device released\n"); + + if (MINOR(inode->i_rdev) != 0) + return -ENXIO; + +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,4,0) + MOD_DEC_USE_COUNT; +#endif + + return 0; +} + +static int dhahelper_get_version(int * arg) +{ + int version = API_VERSION; + + if (copy_to_user(arg, &version, sizeof(int))) + { + if (dhahelper_verbosity > 0) + printk(KERN_ERR "dhahelper: failed copy to userspace\n"); + return -EFAULT; + } + return 0; +} + +static int dhahelper_port(dhahelper_port_t * arg) +{ + dhahelper_port_t port; + if (copy_from_user(&port, arg, sizeof(dhahelper_port_t))) + { + if (dhahelper_verbosity > 0) + printk(KERN_ERR "dhahelper: failed copy from userspace\n"); + return -EFAULT; + } + switch(port.operation) + { + case PORT_OP_READ: + { + switch(port.size) + { + case 1: + port.value = inb(port.addr); + break; + case 2: + port.value = inw(port.addr); + break; + case 4: + port.value = inl(port.addr); + break; + default: + if (dhahelper_verbosity > 0) + printk(KERN_ERR "dhahelper: invalid port read size (%d)\n", + port.size); + return -EINVAL; + } + break; + } + case PORT_OP_WRITE: + { + switch(port.size) + { + case 1: + outb(port.value, port.addr); + break; + case 2: + outw(port.value, port.addr); + break; + case 4: + outl(port.value, port.addr); + break; + default: + if (dhahelper_verbosity > 0) + printk(KERN_ERR "dhahelper: invalid port write size (%d)\n", + port.size); + return -EINVAL; + } + break; + } + default: + if (dhahelper_verbosity > 0) + printk(KERN_ERR "dhahelper: invalid port operation (%d)\n", + port.operation); + return -EINVAL; + } + /* copy back only if read was performed */ + if (port.operation == PORT_OP_READ) + if (copy_to_user(arg, &port, sizeof(dhahelper_port_t))) + { + if (dhahelper_verbosity > 0) + printk(KERN_ERR "dhahelper: failed copy to userspace\n"); + return -EFAULT; + } + return 0; +} + +/*******************************/ +/* Memory management functions */ +/* from kernel:/drivers/media/video/bttv-driver.c */ +/*******************************/ + +#define MDEBUG(x) do { } while(0) /* Debug memory management */ + +/* [DaveM] I've recoded most of this so that: + * 1) It's easier to tell what is happening + * 2) It's more portable, especially for translating things + * out of vmalloc mapped areas in the kernel. + * 3) Less unnecessary translations happen. + * + * The code used to assume that the kernel vmalloc mappings + * existed in the page tables of every process, this is simply + * not guarenteed. We now use pgd_offset_k which is the + * defined way to get at the kernel page tables. + */ + +/* Given PGD from the address space's page table, return the kernel + * virtual mapping of the physical memory mapped at ADR. + */ +static inline unsigned long uvirt_to_kva(pgd_t *pgd, unsigned long adr) +{ + unsigned long ret = 0UL; + pmd_t *pmd; + pte_t *ptep, pte; + + if (!pgd_none(*pgd)) { + pmd = pmd_offset(pgd, adr); + if (!pmd_none(*pmd)) { + ptep = pte_offset(pmd, adr); + pte = *ptep; + if(pte_present(pte)) { + ret = (unsigned long) page_address(pte_page(pte)); + ret |= (adr & (PAGE_SIZE - 1)); + + } + } + } + MDEBUG(printk("uv2kva(%lx-->%lx)", adr, ret)); + return ret; +} + +static inline unsigned long uvirt_to_bus(unsigned long adr) +{ + unsigned long kva, ret; + + kva = uvirt_to_kva(pgd_offset(current->mm, adr), adr); + ret = virt_to_bus((void *)kva); + MDEBUG(printk("uv2b(%lx-->%lx)", adr, ret)); + return ret; +} + +static inline unsigned long uvirt_to_pa(unsigned long adr) +{ + unsigned long kva, ret; + + kva = uvirt_to_kva(pgd_offset(current->mm, adr), adr); + ret = virt_to_phys((void *)kva); + MDEBUG(printk("uv2b(%lx-->%lx)", adr, ret)); + return ret; +} + +static inline unsigned long kvirt_to_bus(unsigned long va) +{ + unsigned long kva, ret; + + kva = uvirt_to_kva(pgd_offset_k(va), va); + ret = virt_to_bus((void *)kva); + MDEBUG(printk("kv2b(%lx-->%lx)", adr, ret)); + return ret; +} + +/* Here we want the physical address of the memory. + * This is used when initializing the contents of the + * area and marking the pages as reserved. + */ +static inline unsigned long kvirt_to_pa(unsigned long va) +{ + unsigned long kva, ret; + + kva = uvirt_to_kva(pgd_offset_k(va), va); + ret = __pa(kva); + MDEBUG(printk("kv2pa(%lx-->%lx)", adr, ret)); + return ret; +} + +static void * rvmalloc(signed long size) +{ + void * mem; + unsigned long adr, page; + + mem=vmalloc_32(size); + if (mem) + { + memset(mem, 0, size); /* Clear the ram out, no junk to the user */ + adr=(unsigned long) mem; + while (size > 0) + { + page = kvirt_to_pa(adr); + SetPageReserved(virt_to_page(__va(page))); + adr+=PAGE_SIZE; + size-=PAGE_SIZE; + } + } + return mem; +} + +static int pag_lock(unsigned long addr) +{ + unsigned long page; + unsigned long kva; + + kva = uvirt_to_kva(pgd_offset(current->mm, addr), addr); + if(kva) + { + lock_it: + page = uvirt_to_pa((unsigned long)addr); + LockPage(virt_to_page(__va(page))); + SetPageReserved(virt_to_page(__va(page))); + } + else + { + copy_from_user(&page,(char *)addr,1); /* try access it */ + kva = uvirt_to_kva(pgd_offset(current->mm, addr), addr); + if(kva) goto lock_it; + else return EPERM; + } + return 0; +} + +static int pag_unlock(unsigned long addr) +{ + unsigned long page; + unsigned long kva; + + kva = uvirt_to_kva(pgd_offset(current->mm, addr), addr); + if(kva) + { + page = uvirt_to_pa((unsigned long)addr); + UnlockPage(virt_to_page(__va(page))); + ClearPageReserved(virt_to_page(__va(page))); + return 0; + } + return EPERM; +} + + +static void rvfree(void * mem, signed long size) +{ + unsigned long adr, page; + + if (mem) + { + adr=(unsigned long) mem; + while (size > 0) + { + page = kvirt_to_pa(adr); + ClearPageReserved(virt_to_page(__va(page))); + adr+=PAGE_SIZE; + size-=PAGE_SIZE; + } + vfree(mem); + } +} + + +static int dhahelper_virt_to_phys(dhahelper_vmi_t *arg) +{ + dhahelper_vmi_t mem; + unsigned long i,nitems; + char *addr; + if (copy_from_user(&mem, arg, sizeof(dhahelper_vmi_t))) + { + if (dhahelper_verbosity > 0) + printk(KERN_ERR "dhahelper: failed copy from userspace\n"); + return -EFAULT; + } + nitems = mem.length / PAGE_SIZE; + if(mem.length % PAGE_SIZE) nitems++; + addr = mem.virtaddr; + for(i=0;i<nitems;i++) + { + unsigned long result; + result = uvirt_to_pa((unsigned long)addr); + if (copy_to_user(&mem.realaddr[i], &result, sizeof(unsigned long))) + { + if (dhahelper_verbosity > 0) + printk(KERN_ERR "dhahelper: failed copy to userspace\n"); + return -EFAULT; + } + addr += PAGE_SIZE; + } + return 0; +} + +static int dhahelper_virt_to_bus(dhahelper_vmi_t *arg) +{ + dhahelper_vmi_t mem; + unsigned long i,nitems; + char *addr; + if (copy_from_user(&mem, arg, sizeof(dhahelper_vmi_t))) + { + if (dhahelper_verbosity > 0) + printk(KERN_ERR "dhahelper: failed copy from userspace\n"); + return -EFAULT; + } + nitems = mem.length / PAGE_SIZE; + if(mem.length % PAGE_SIZE) nitems++; + addr = mem.virtaddr; + for(i=0;i<nitems;i++) + { + unsigned long result; + result = uvirt_to_bus((unsigned long)addr); + if (copy_to_user(&mem.realaddr[i], &result, sizeof(unsigned long))) + { + if (dhahelper_verbosity > 0) + printk(KERN_ERR "dhahelper: failed copy to userspace\n"); + return -EFAULT; + } + addr += PAGE_SIZE; + } + return 0; +} + + +static int dhahelper_alloc_pa(dhahelper_mem_t *arg) +{ + dhahelper_mem_t mem; + if (copy_from_user(&mem, arg, sizeof(dhahelper_mem_t))) + { + if (dhahelper_verbosity > 0) + printk(KERN_ERR "dhahelper: failed copy from userspace\n"); + return -EFAULT; + } + mem.addr = rvmalloc(mem.length); + if (copy_to_user(arg, &mem, sizeof(dhahelper_mem_t))) + { + if (dhahelper_verbosity > 0) + printk(KERN_ERR "dhahelper: failed copy to userspace\n"); + return -EFAULT; + } + return 0; +} + +static int dhahelper_free_pa(dhahelper_mem_t *arg) +{ + dhahelper_mem_t mem; + if (copy_from_user(&mem, arg, sizeof(dhahelper_mem_t))) + { + if (dhahelper_verbosity > 0) + printk(KERN_ERR "dhahelper: failed copy from userspace\n"); + return -EFAULT; + } + rvfree(mem.addr,mem.length); + return 0; +} + +static int dhahelper_lock_mem(dhahelper_mem_t *arg) +{ + dhahelper_mem_t mem; + int retval; + unsigned long i,nitems,addr; + if (copy_from_user(&mem, arg, sizeof(dhahelper_mem_t))) + { + if (dhahelper_verbosity > 0) + printk(KERN_ERR "dhahelper: failed copy from userspace\n"); + return -EFAULT; + } + nitems = mem.length / PAGE_SIZE; + if(mem.length % PAGE_SIZE) nitems++; + addr = (unsigned long)mem.addr; + for(i=0;i<nitems;i++) + { + retval = pag_lock((unsigned long)addr); + if(retval) + { + unsigned long j; + addr = (unsigned long)mem.addr; + for(j=0;j<i;j++) + { + pag_unlock(addr); + addr += PAGE_SIZE; + } + return retval; + } + addr += PAGE_SIZE; + } + return 0; +} + +static int dhahelper_unlock_mem(dhahelper_mem_t *arg) +{ + dhahelper_mem_t mem; + int retval; + unsigned long i,nitems,addr; + if (copy_from_user(&mem, arg, sizeof(dhahelper_mem_t))) + { + if (dhahelper_verbosity > 0) + printk(KERN_ERR "dhahelper: failed copy from userspace\n"); + return -EFAULT; + } + nitems = mem.length / PAGE_SIZE; + if(mem.length % PAGE_SIZE) nitems++; + addr = (unsigned long)mem.addr; + for(i=0;i<nitems;i++) + { + retval = pag_unlock((unsigned long)addr); + if(retval) return retval; + addr += PAGE_SIZE; + } + return 0; +} + +static struct dha_irq { + spinlock_t lock; + unsigned long flags; + int handled; + int rcvd; + volatile u32 *ack_addr; + u32 ack_data; + struct pci_dev *dev; + wait_queue_head_t wait; + unsigned long count; +} dha_irqs[256]; + +static irqreturn_t dhahelper_irq_handler(int irq, void *dev_id, + struct pt_regs *regs) +{ + spin_lock_irqsave(&dha_irqs[irq].lock, dha_irqs[irq].flags); + if(dha_irqs[irq].handled){ + dha_irqs[irq].rcvd = 1; + dha_irqs[irq].count++; + if(dha_irqs[irq].ack_addr){ + *dha_irqs[irq].ack_addr = dha_irqs[irq].ack_data; + mb(); + } + wake_up_interruptible(&dha_irqs[irq].wait); + } + spin_unlock_irqrestore(&dha_irqs[irq].lock, dha_irqs[irq].flags); + irqreturn(0); +} + +static int dhahelper_install_irq(dhahelper_irq_t *arg) +{ + dhahelper_irq_t my_irq; + struct pci_dev *pci; + long rlen; + int retval; + long ack_addr; + int irqn; + + if (copy_from_user(&my_irq, arg, sizeof(dhahelper_irq_t))) + { + if (dhahelper_verbosity > 0) + printk(KERN_ERR "dhahelper: failed copy from userspace\n"); + return -EFAULT; + } + + if(!(pci = pci_find_slot(my_irq.bus, PCI_DEVFN(my_irq.dev, my_irq.func)))) + return -EINVAL; + + rlen = pci_resource_len(pci, my_irq.ack_region); + if(my_irq.ack_offset > rlen - 4) + return -EINVAL; + + irqn = pci->irq; + + spin_lock_irqsave(&dha_irqs[irqn].lock, + dha_irqs[irqn].flags); + + if(dha_irqs[irqn].handled){ + retval = -EBUSY; + goto fail; + } + + if(my_irq.ack_region >= 0){ + ack_addr = pci_resource_start(pci, my_irq.ack_region); + ack_addr += my_irq.ack_offset; +#ifdef CONFIG_ALPHA + ack_addr += ((struct pci_controller *) pci->sysdata)->dense_mem_base; +#endif + /* FIXME: Other architectures */ + + dha_irqs[irqn].ack_addr = phys_to_virt(ack_addr); + dha_irqs[irqn].ack_data = my_irq.ack_data; + } else { + dha_irqs[irqn].ack_addr = 0; + } + + dha_irqs[irqn].lock = SPIN_LOCK_UNLOCKED; + dha_irqs[irqn].flags = 0; + dha_irqs[irqn].rcvd = 0; + dha_irqs[irqn].dev = pci; + init_waitqueue_head(&dha_irqs[irqn].wait); + dha_irqs[irqn].count = 0; + + retval = request_irq(irqn, dhahelper_irq_handler, + SA_SHIRQ, "dhahelper", pci); + + if(retval < 0) + goto fail; + + copy_to_user(&arg->num, &irqn, sizeof(irqn)); + + dha_irqs[irqn].handled = 1; + +out: + spin_unlock_irqrestore(&dha_irqs[irqn].lock, + dha_irqs[irqn].flags); + return retval; + +fail: + if(retval == -EINVAL){ + printk("dhahelper: bad irq number or handler\n"); + } else if(retval == -EBUSY){ + printk("dhahelper: IRQ %u busy\n", irqn); + } else { + printk("dhahelper: Could not install irq handler...\n"); + } + printk("dhahelper: Perhaps you need to let your BIOS assign an IRQ to your video card\n"); + goto out; +} + +static int dhahelper_free_irq(dhahelper_irq_t *arg) +{ + dhahelper_irq_t irq; + struct pci_dev *pci; + int irqn; + + if (copy_from_user(&irq, arg, sizeof(dhahelper_irq_t))) + { + if (dhahelper_verbosity > 0) + printk(KERN_ERR "dhahelper: failed copy from userspace\n"); + return -EFAULT; + } + + pci = pci_find_slot(irq.bus, PCI_DEVFN(irq.dev, irq.func)); + if(!pci) + return -EINVAL; + + irqn = pci->irq; + + spin_lock_irqsave(&dha_irqs[irqn].lock, dha_irqs[irqn].flags); + if(dha_irqs[irqn].handled) { + free_irq(irqn, pci); + dha_irqs[irqn].handled = 0; + printk("IRQ %i: %li\n", irqn, dha_irqs[irqn].count); + } + spin_unlock_irqrestore(&dha_irqs[irqn].lock, dha_irqs[irqn].flags); + return 0; +} + +static int dhahelper_ack_irq(dhahelper_irq_t *arg) +{ + dhahelper_irq_t irq; + int retval = 0; + DECLARE_WAITQUEUE(wait, current); + if (copy_from_user(&irq, arg, sizeof(dhahelper_irq_t))) + { + if (dhahelper_verbosity > 0) + printk(KERN_ERR "dhahelper: failed copy from userspace\n"); + return -EFAULT; + } + if(irq.num > 255) return -EINVAL; + if(!dha_irqs[irq.num].handled) return -ESRCH; + add_wait_queue(&dha_irqs[irq.num].wait, &wait); + set_current_state(TASK_INTERRUPTIBLE); + for(;;){ + int r; + spin_lock_irqsave(&dha_irqs[irq.num].lock, + dha_irqs[irq.num].flags); + r = dha_irqs[irq.num].rcvd; + spin_unlock_irqrestore(&dha_irqs[irq.num].lock, + dha_irqs[irq.num].flags); + + if(r){ + dha_irqs[irq.num].rcvd = 0; + break; + } + + if(signal_pending(current)){ + retval = -ERESTARTSYS; + break; + } + + schedule(); + } + set_current_state(TASK_RUNNING); + remove_wait_queue(&dha_irqs[irq.num].wait, &wait); + return retval; +} + +static int dhahelper_cpu_flush(dhahelper_cpu_flush_t *arg) +{ + dhahelper_cpu_flush_t my_l2; + if (copy_from_user(&my_l2, arg, sizeof(dhahelper_cpu_flush_t))) + { + if (dhahelper_verbosity > 0) + printk(KERN_ERR "dhahelper: failed copy from userspace\n"); + return -EFAULT; + } +#if defined(__i386__) + /* WBINVD writes all modified cache lines back to main memory */ + if(boot_cpu_data.x86 > 3) { __asm __volatile("wbinvd":::"memory"); } +#else + /* FIXME!!!*/ + mb(); /* declared in "asm/system.h" */ +#endif + return 0; +} + +static struct pci_dev *pdev = NULL; +static int dhahelper_pci_find(dhahelper_pci_device_t *arg) +{ + dhahelper_pci_device_t this_dev; + pdev = pci_find_device(PCI_ANY_ID, PCI_ANY_ID, pdev); + if(pdev) + { + this_dev.bus = pdev->bus->number; + this_dev.card = PCI_SLOT(pdev->devfn); + this_dev.func = PCI_FUNC(pdev->devfn); + this_dev.vendor = pdev->vendor; + this_dev.device = pdev->device; + this_dev.base0 = pci_resource_start (pdev, 0); + this_dev.base1 = pci_resource_start (pdev, 1); + this_dev.base2 = pci_resource_start (pdev, 2); + pci_read_config_dword(pdev, pdev->rom_base_reg, (u32*)&this_dev.baserom); + this_dev.base3 = pci_resource_start (pdev, 3); + this_dev.base4 = pci_resource_start (pdev, 4); + this_dev.base5 = pci_resource_start (pdev, 5); + pci_read_config_byte(pdev, PCI_INTERRUPT_LINE, &this_dev.irq); + pci_read_config_byte(pdev, PCI_INTERRUPT_PIN, &this_dev.ipin); + pci_read_config_byte(pdev, PCI_MIN_GNT, &this_dev.gnt); + pci_read_config_byte(pdev, PCI_MAX_LAT, &this_dev.lat); + } + else memset(&this_dev,0,sizeof(dhahelper_pci_device_t)); + if (copy_to_user(arg, &this_dev, sizeof(dhahelper_pci_device_t))) + { + if (dhahelper_verbosity > 0) + printk(KERN_ERR "dhahelper: failed copy to userspace\n"); + return -EFAULT; + } + return pdev?0:-ENODATA; +} + +static int dhahelper_pci_config(dhahelper_pci_config_t *arg) +{ + dhahelper_pci_config_t op; + struct pci_dev *pdev; + if (copy_from_user(&op, arg, sizeof(dhahelper_pci_config_t))) + { + if (dhahelper_verbosity > 0) + printk(KERN_ERR "dhahelper: failed copy from userspace\n"); + return -EFAULT; + } + pdev = pci_find_slot(op.bus,PCI_DEVFN(op.dev,op.func)); + if(!pdev) + { + if (dhahelper_verbosity > 0) + printk(KERN_ERR "dhahelper: can't identify device\n"); + return -EFAULT; + } + switch(op.operation) + { + case PCI_OP_READ: + switch(op.size) + { + case 1: + pci_read_config_byte(pdev,op.cmd,(u8*)&op.ret); + break; + case 2: + pci_read_config_word(pdev,op.cmd,(u16*)&op.ret); + break; + case 4: + pci_read_config_dword(pdev,op.cmd,(u32*)&op.ret); + break; + default: + if (dhahelper_verbosity > 0) + printk(KERN_ERR "dhahelper: wrong size of pci operation: %u \n",op.size); + return -EFAULT; + } + case PCI_OP_WRITE: + switch(op.size) + { + case 1: + pci_write_config_byte(pdev,op.cmd,op.ret); + break; + case 2: + pci_write_config_word(pdev,op.cmd,op.ret); + break; + case 4: + pci_write_config_dword(pdev,op.cmd,op.ret); + break; + default: + if (dhahelper_verbosity > 0) + printk(KERN_ERR "dhahelper: wrong size of pci operation: %u \n",op.size); + return -EFAULT; + } + default: + if (dhahelper_verbosity > 0) + printk(KERN_ERR "dhahelper: unknown pci operation %i\n",op.operation); + return -EFAULT; + } + if (copy_to_user(arg, &op, sizeof(dhahelper_pci_device_t))) + { + if (dhahelper_verbosity > 0) + printk(KERN_ERR "dhahelper: failed copy to userspace\n"); + return -EFAULT; + } + return 0; +} + +static int dhahelper_mtrr(dhahelper_mtrr_t *arg) +{ +#ifdef CONFIG_MTRR + dhahelper_mtrr_t op; + if (copy_from_user(&op, arg, sizeof(dhahelper_pci_config_t))) + { + if (dhahelper_verbosity > 0) + printk(KERN_ERR "dhahelper: failed copy from userspace\n"); + return -EFAULT; + } + switch(op.operation) + { + case MTRR_OP_ADD: + op.privat = mtrr_add (op.start,op.size,op.type,1); + break; + case MTRR_OP_DEL: + mtrr_del(op.privat, op.start, op.size); + break; + default: + if (dhahelper_verbosity > 0) + printk(KERN_ERR "dhahelper: unknown mtrr operation %i\n",op.operation); + return -EFAULT; + } + if (copy_to_user(arg, &op, sizeof(dhahelper_mtrr_t))) + { + if (dhahelper_verbosity > 0) + printk(KERN_ERR "dhahelper: failed copy to userspace\n"); + return -EFAULT; + } +#endif + return 0; +} + +static int dhahelper_ioctl(struct inode *inode, struct file *file, + unsigned int cmd, unsigned long arg) +{ + if (dhahelper_verbosity > 1) + printk(KERN_DEBUG "dhahelper: ioctl(cmd=%x, arg=%lx)\n", + cmd, arg); + + if (MINOR(inode->i_rdev) != 0) + return -ENXIO; + + switch(cmd) + { + case DHAHELPER_GET_VERSION: return dhahelper_get_version((int *)arg); + case DHAHELPER_PORT: return dhahelper_port((dhahelper_port_t *)arg); + case DHAHELPER_MTRR: return dhahelper_mtrr((dhahelper_mtrr_t *)arg); + case DHAHELPER_PCI_CONFIG: return dhahelper_pci_config((dhahelper_pci_config_t *)arg); + case DHAHELPER_VIRT_TO_PHYS:return dhahelper_virt_to_phys((dhahelper_vmi_t *)arg); + case DHAHELPER_VIRT_TO_BUS: return dhahelper_virt_to_bus((dhahelper_vmi_t *)arg); + case DHAHELPER_ALLOC_PA:return dhahelper_alloc_pa((dhahelper_mem_t *)arg); + case DHAHELPER_FREE_PA: return dhahelper_free_pa((dhahelper_mem_t *)arg); + case DHAHELPER_LOCK_MEM: return dhahelper_lock_mem((dhahelper_mem_t *)arg); + case DHAHELPER_UNLOCK_MEM: return dhahelper_unlock_mem((dhahelper_mem_t *)arg); + case DHAHELPER_INSTALL_IRQ: return dhahelper_install_irq((dhahelper_irq_t *)arg); + case DHAHELPER_ACK_IRQ: return dhahelper_ack_irq((dhahelper_irq_t *)arg); + case DHAHELPER_FREE_IRQ: return dhahelper_free_irq((dhahelper_irq_t *)arg); + case DHAHELPER_CPU_FLUSH: return dhahelper_cpu_flush((dhahelper_cpu_flush_t *)arg); + case DHAHELPER_PCI_FIND: return dhahelper_pci_find((dhahelper_pci_device_t *)arg); + default: + if (dhahelper_verbosity > 0) + printk(KERN_ERR "dhahelper: invalid ioctl (%x)\n", cmd); + return -EINVAL; + } + return 0; +} + +/* + fops functions were shamelessly stolen from linux-kernel project ;) +*/ + +static loff_t dhahelper_lseek(struct file * file, loff_t offset, int orig) +{ + switch (orig) { + case 0: + file->f_pos = offset; + return file->f_pos; + case 1: + file->f_pos += offset; + return file->f_pos; + default: + return -EINVAL; + } +} + +/* + * This funcion reads the *physical* memory. The f_pos points directly to the + * memory location. + */ +static ssize_t dhahelper_read(struct file * file, char * buf, + size_t count, loff_t *ppos) +{ + unsigned long p = *ppos; + unsigned long end_mem; + ssize_t read; + + end_mem = __pa(high_memory); + if (p >= end_mem) + return 0; + if (count > end_mem - p) + count = end_mem - p; + read = 0; +#if defined(__sparc__) || defined(__mc68000__) + /* we don't have page 0 mapped on sparc and m68k.. */ + if (p < PAGE_SIZE) { + unsigned long sz = PAGE_SIZE-p; + if (sz > count) + sz = count; + if (sz > 0) { + if (clear_user(buf, sz)) + return -EFAULT; + buf += sz; + p += sz; + count -= sz; + read += sz; + } + } +#endif + if (copy_to_user(buf, __va(p), count)) + return -EFAULT; + read += count; + *ppos += read; + return read; +} + +static ssize_t do_write_mem(struct file * file, void *p, unsigned long realp, + const char * buf, size_t count, loff_t *ppos) +{ + ssize_t written; + + written = 0; +#if defined(__sparc__) || defined(__mc68000__) + /* we don't have page 0 mapped on sparc and m68k.. */ + if (realp < PAGE_SIZE) { + unsigned long sz = PAGE_SIZE-realp; + if (sz > count) sz = count; + /* Hmm. Do something? */ + buf+=sz; + p+=sz; + count-=sz; + written+=sz; + } +#endif + if (copy_from_user(p, buf, count)) + return -EFAULT; + written += count; + *ppos += written; + return written; +} + +static ssize_t dhahelper_write(struct file * file, const char * buf, + size_t count, loff_t *ppos) +{ + unsigned long p = *ppos; + unsigned long end_mem; + + end_mem = __pa(high_memory); + if (p >= end_mem) + return 0; + if (count > end_mem - p) + count = end_mem - p; + return do_write_mem(file, __va(p), p, buf, count, ppos); +} + +#ifndef pgprot_noncached + +/* + * This should probably be per-architecture in <asm/pgtable.h> + */ +static inline pgprot_t pgprot_noncached(pgprot_t _prot) +{ + unsigned long prot = pgprot_val(_prot); + +#if defined(__i386__) || defined(__x86_64__) + /* On PPro and successors, PCD alone doesn't always mean + uncached because of interactions with the MTRRs. PCD | PWT + means definitely uncached. */ + if (boot_cpu_data.x86 > 3) + prot |= _PAGE_PCD | _PAGE_PWT; +#elif defined(__powerpc__) + prot |= _PAGE_NO_CACHE | _PAGE_GUARDED; +#elif defined(__mc68000__) +#ifdef SUN3_PAGE_NOCACHE + if (MMU_IS_SUN3) + prot |= SUN3_PAGE_NOCACHE; + else +#endif + if (MMU_IS_851 || MMU_IS_030) + prot |= _PAGE_NOCACHE030; + /* Use no-cache mode, serialized */ + else if (MMU_IS_040 || MMU_IS_060) + prot = (prot & _CACHEMASK040) | _PAGE_NOCACHE_S; +#endif + + return __pgprot(prot); +} + +#endif /* !pgprot_noncached */ + +/* + * Architectures vary in how they handle caching for addresses + * outside of main memory. + */ +static inline int noncached_address(unsigned long addr) +{ +#if defined(__i386__) + /* + * On the PPro and successors, the MTRRs are used to set + * memory types for physical addresses outside main memory, + * so blindly setting PCD or PWT on those pages is wrong. + * For Pentiums and earlier, the surround logic should disable + * caching for the high addresses through the KEN pin, but + * we maintain the tradition of paranoia in this code. + */ + return !( test_bit(X86_FEATURE_MTRR, boot_cpu_data.x86_capability) || + test_bit(X86_FEATURE_K6_MTRR, boot_cpu_data.x86_capability) || + test_bit(X86_FEATURE_CYRIX_ARR, boot_cpu_data.x86_capability) || + test_bit(X86_FEATURE_CENTAUR_MCR, boot_cpu_data.x86_capability) ) + && addr >= __pa(high_memory); +#else + return addr >= __pa(high_memory); +#endif +} + +static int dhahelper_mmap(struct file * file, struct vm_area_struct * vma) +{ + unsigned long offset = vma->vm_pgoff << PAGE_SHIFT; + int err; + + /* + * Accessing memory above the top the kernel knows about or + * through a file pointer that was marked O_SYNC will be + * done non-cached. + */ + if (noncached_address(offset) || (file->f_flags & O_SYNC)) + vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); + + /* Don't try to swap out physical pages.. */ + vma->vm_flags |= VM_RESERVED; + + /* + * Don't dump addresses that are not real memory to a core file. + */ + if (offset >= __pa(high_memory) || (file->f_flags & O_SYNC)) + vma->vm_flags |= VM_IO; + +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0) + err = remap_page_range(vma, vma->vm_start, offset, + vma->vm_end-vma->vm_start, vma->vm_page_prot); +#else + err = remap_page_range(vma->vm_start, offset, + vma->vm_end-vma->vm_start, vma->vm_page_prot); +#endif + if(err) + return -EAGAIN; + return 0; +} + +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,4,0) +static struct file_operations dhahelper_fops = +{ + /*llseek*/ dhahelper_lseek, + /*read*/ dhahelper_read, + /*write*/ dhahelper_write, + /*readdir*/ NULL, + /*poll*/ NULL, + /*ioctl*/ dhahelper_ioctl, + /*mmap*/ dhahelper_mmap, + /*open*/ dhahelper_open, + /*flush*/ NULL, + /*release*/ dhahelper_release, + /* zero out the last 5 entries too ? */ +}; +#else +static struct file_operations dhahelper_fops = +{ + owner: THIS_MODULE, + ioctl: dhahelper_ioctl, + open: dhahelper_open, + release: dhahelper_release, + llseek: dhahelper_lseek, + read: dhahelper_read, + write: dhahelper_write, + mmap: dhahelper_mmap, +}; +#endif + +#ifdef CONFIG_DEVFS_FS +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) +devfs_handle_t dha_devfsh; + +static int +register_dev(void) +{ + dha_devfsh = devfs_register(NULL, "dhahelper", DEVFS_FL_NONE, + dhahelper_major, 0, + S_IFCHR | S_IRUSR | S_IWUSR, + &dhahelper_fops, NULL); + if(!dha_devfsh) + return -EIO; + return 0; +} + +static void +unregister_dev(void) +{ + devfs_unregister(dha_devfsh); +} +#else /* VERSION < 2.6.0 */ +static int +register_dev(void) +{ + devfs_mk_cdev(MKDEV(dhahelper_major, 0), S_IFCHR | S_IRUSR | S_IWUSR, + "dhahelper"); + if(register_chrdev(dhahelper_major, "dhahelper", &dhahelper_fops)) + return -EIO; + return 0; +} + +static void +unregister_dev(void) +{ + devfs_remove("dhahelper"); + unregister_chrdev(dhahelper_major, "dhahelper"); +} +#endif /* VERSION < 2.6.0 */ +#else +static int +register_dev(void) +{ + return register_chrdev(dhahelper_major, "dhahelper", &dhahelper_fops); +} + +static void +unregister_dev(void) +{ + unregister_chrdev(dhahelper_major, "dhahelper"); +} +#endif /* defined CONFIG_DEVFS_FS */ + + +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,4,0) +int init_module(void) +#else +static int __init init_dhahelper(void) +#endif +{ + int err = 0; + printk(KERN_INFO "Direct Hardware Access kernel helper (C) Alex Beregszaszi\n"); + + err = register_dev(); + if(err){ + if (dhahelper_verbosity > 0) + printk(KERN_ERR "dhahelper: unable to register character device (major: %d)\n", + dhahelper_major); + return err; + } + memset(dha_irqs, 0, sizeof(dha_irqs)); + return 0; +} + +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,4,0) +void cleanup_module(void) +#else +static void __exit exit_dhahelper(void) +#endif +{ + unsigned i; + for(i=0;i<256;i++) + if(dha_irqs[i].handled) + free_irq(i, dha_irqs[i].dev); + + unregister_dev(); +} + +#ifdef EXPORT_NO_SYMBOLS +EXPORT_NO_SYMBOLS; +#endif + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,4,0) +module_init(init_dhahelper); +module_exit(exit_dhahelper); +#endif diff --git a/contrib/libdha/kernelhelper/dhahelper.h b/contrib/libdha/kernelhelper/dhahelper.h new file mode 100644 index 000000000..7db56abb5 --- /dev/null +++ b/contrib/libdha/kernelhelper/dhahelper.h @@ -0,0 +1,105 @@ +/* + Direct Hardware Access kernel helper + + (C) 2002 Alex Beregszaszi <alex@naxine.org> + (C) 2002-2003 Nick Kurshev <nickols_k@mail.ru> +*/ + +#ifndef DHAHELPER_H +#define DHAHELPER_H + +/* #include <linux/ioctl.h> */ + +/* feel free to change */ +#define DEFAULT_MAJOR 252 /* 240-254 LOCAL/EXPERIMENTAL USE */ + +#define API_VERSION 0x30 /* 3.0*/ + +typedef struct dhahelper_port_s +{ +#define PORT_OP_READ 1 +#define PORT_OP_WRITE 2 + int operation; + int size; + int addr; // FIXME - switch to void* (64bit) + int value; +} dhahelper_port_t; + +typedef struct dhahelper_mtrr_s +{ +#define MTRR_OP_ADD 1 +#define MTRR_OP_DEL 2 + int operation; + long start; + long size; + int type; + int privat; +} dhahelper_mtrr_t; + +typedef struct dhahelper_pci_config_s +{ +#define PCI_OP_READ 0 +#define PCI_OP_WRITE 1 + int operation; + int bus; + int dev; + int func; + int cmd; + int size; + long ret; +} dhahelper_pci_config_t; + +typedef struct dhahelper_vmi_s +{ + void * virtaddr; + unsigned long length; + unsigned long *realaddr; +}dhahelper_vmi_t; + +typedef struct dhahelper_mem_s +{ + void * addr; + unsigned long length; +}dhahelper_mem_t; + +typedef struct dhahelper_irq_s +{ + unsigned num; + int bus, dev, func; + int ack_region; + unsigned long ack_offset; + unsigned int ack_data; +}dhahelper_irq_t; + +typedef struct dhahelper_cpu_flush_s +{ + void *va; + unsigned long length; +}dhahelper_cpu_flush_t; + +typedef struct dhahelper_pci_device_s +{ + int bus,card,func; /* PCI/AGP bus:card:func */ + unsigned short vendor,device; /* Card vendor+device ID */ + unsigned long base0,base1,base2,baserom; /* Memory and I/O base addresses */ + unsigned long base3,base4,base5; /* Memory and I/O base addresses */ + unsigned char irq,ipin,gnt,lat; /* assigned IRQ parameters for this card */ +}dhahelper_pci_device_t; + +#define DHAHELPER_GET_VERSION _IOW('D', 0, int) +#define DHAHELPER_PORT _IOWR('D', 1, dhahelper_port_t) +#define DHAHELPER_MTRR _IOWR('D', 2, dhahelper_mtrr_t) +#define DHAHELPER_PCI_CONFIG _IOWR('D', 3, dhahelper_pci_config_t) +#define DHAHELPER_VIRT_TO_PHYS _IOWR('D', 4, dhahelper_vmi_t) +#define DHAHELPER_VIRT_TO_BUS _IOWR('D', 5, dhahelper_vmi_t) +#define DHAHELPER_ALLOC_PA _IOWR('D', 6, dhahelper_mem_t) +#define DHAHELPER_FREE_PA _IOWR('D', 7, dhahelper_mem_t) +#define DHAHELPER_LOCK_MEM _IOWR('D', 8, dhahelper_mem_t) +#define DHAHELPER_UNLOCK_MEM _IOWR('D', 9, dhahelper_mem_t) +#define DHAHELPER_INSTALL_IRQ _IOWR('D', 10, dhahelper_irq_t) +#define DHAHELPER_ACK_IRQ _IOWR('D', 11, dhahelper_irq_t) +#define DHAHELPER_FREE_IRQ _IOWR('D', 12, dhahelper_irq_t) +#define DHAHELPER_CPU_FLUSH _IOWR('D', 13, dhahelper_cpu_flush_t) +#define DHAHELPER_PCI_FIND _IOWR('D', 14, dhahelper_pci_device_t) + +#endif /* DHAHELPER_H */ diff --git a/contrib/libdha/kernelhelper/test.c b/contrib/libdha/kernelhelper/test.c new file mode 100644 index 000000000..d2d807f3f --- /dev/null +++ b/contrib/libdha/kernelhelper/test.c @@ -0,0 +1,49 @@ +#include <string.h> +#include <stdio.h> +#include <sys/ioctl.h> +#include <unistd.h> +#include <errno.h> +#include <fcntl.h> +#include <sys/mman.h> +#include <stdlib.h> + +#include "dhahelper.h" + +int main(int argc, char *argv[]) +{ + int fd; + int ret; + + fd = open("/dev/dhahelper", O_RDWR); + if(fd < 0){ + perror("dev/dhahelper"); + exit(1); + } + + ioctl(fd, DHAHELPER_GET_VERSION, &ret); + + printf("api version: %d\n", ret); + if (ret != API_VERSION) + printf("incompatible api!\n"); + + { + void *mem; + unsigned long size=256; + mem = mmap(0,size,PROT_READ|PROT_WRITE,MAP_SHARED,fd,0); + printf("allocated to %p\n", mem); + + if (argc > 1) + if (mem != 0) + { + int i; + + for (i = 0; i < 256; i++) + printf("[%x] ", *(int *)(mem+i)); + printf("\n"); + } + + munmap((void *)mem, size); + } + + return(0); +} diff --git a/contrib/libdha/libdha.c b/contrib/libdha/libdha.c new file mode 100644 index 000000000..73a4387a2 --- /dev/null +++ b/contrib/libdha/libdha.c @@ -0,0 +1,99 @@ +/* + libgha.c - Library for direct hardware access + Copyrights: + 1996/10/27 - Robin Cutshaw (robin@xfree86.org) + XFree86 3.3.3 implementation + 1999 - Øyvind Aabling. + Modified for GATOS/win/gfxdump. + + 2002 - library implementation by Nick Kurshev + - dhahelper and some changes by Alex Beregszaszi + + supported O/S's: SVR4, UnixWare, SCO, Solaris, + FreeBSD, NetBSD, 386BSD, BSDI BSD/386, + Linux, Mach/386, ISC + DOS (WATCOM 9.5 compiler), Win9x (with mapdev.vxd) + Licence: GPL + Original location: www.linuxvideo.org/gatos +*/ + +#include "config.h" + +#include "libdha.h" +#include <stdio.h> +#include <stdlib.h> +#include <string.h> +#include <fcntl.h> +#include <sys/stat.h> +#include <sys/types.h> +#ifdef ARCH_ALPHA +#include <sys/io.h> +#endif +#include <unistd.h> + +/* instead exit() use libdha_exit, and do the 'mother-application' deinit + only in this code */ +void libdha_exit(const char *message, int level) +{ + printf("libdha: FATAL: %s\n", message); + exit(level); /* FIXME */ +} + +#if defined(_WIN32) +#include "sysdep/libdha_win32.c" +#elif defined (__EMX__) +#include "sysdep/libdha_os2.c" +#else + +#if defined(SVR4) || defined(SCO325) +# if !(defined(sun) && defined (i386) && defined (SVR4)) +# define DEV_MEM "/dev/pmem" +# elif defined(PowerMAX_OS) +# define DEV_MEM "/dev/iomem" +# endif +# ifdef SCO325 +# undef DEV_MEM +# define DEV_MEM "/dev/mem" +# endif +# endif /* SVR4 */ + +/* Generic version */ +#include <sys/mman.h> +#include <sys/ioctl.h> +#ifndef DEV_MEM +#define DEV_MEM "/dev/mem" +#endif + +#include "kernelhelper/dhahelper.h" + +static int devmem_fd=-1; +static unsigned devmem_locks=0; +void *map_phys_mem(unsigned long base, unsigned long size) +{ +#ifdef ARCH_ALPHA +/* TODO: move it into sysdep */ + base += bus_base(); +#endif + if( devmem_fd == -1) + { + if ( (devmem_fd = open("/dev/dhahelper",O_RDWR)) < 0) + { + if ( (devmem_fd = open(DEV_MEM,O_RDWR)) == -1) + { + perror("libdha: open(/dev/mem) failed"); + exit(1); + } + } + } + devmem_locks++; + return mmap(0,size,PROT_READ|PROT_WRITE,MAP_SHARED,devmem_fd,base) ; +} + +void unmap_phys_mem(void *ptr, unsigned long size) +{ + int res=munmap(ptr,size) ; + if (res == -1) { perror("libdha: munmap() failed") ; exit(1) ; } + devmem_locks--; + if(!devmem_locks) { close(devmem_fd); devmem_fd=-1; } +} +#endif diff --git a/contrib/libdha/libdha.h b/contrib/libdha/libdha.h new file mode 100644 index 000000000..2bd8fe39b --- /dev/null +++ b/contrib/libdha/libdha.h @@ -0,0 +1,145 @@ +/* + libgha.h - Library for direct hardware access + Copyrights: + 1996/10/27 - Robin Cutshaw (robin@xfree86.org) + XFree86 3.3.3 implementation + 1999 - Øyvind Aabling. + Modified for GATOS/win/gfxdump. + 2002 - library implementation by Nick Kurshev + + supported O/S's: SVR4, UnixWare, SCO, Solaris, + FreeBSD, NetBSD, 386BSD, BSDI BSD/386, + Linux, Mach/386, ISC + DOS (WATCOM 9.5 compiler), Win9x (with mapdev.vxd) + Licence: GPL +*/ +#ifndef LIBDHA_H +#define LIBDHA_H + +#if defined (__FreeBSD__) +# include <inttypes.h> +#else +# include <stdint.h> +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +#define MAX_DEV_PER_VENDOR_CFG1 64 +#define MAX_PCI_DEVICES_PER_BUS 32 +#define MAX_PCI_DEVICES 64 +#define PCI_MULTIFUNC_DEV 0x80 + +typedef struct pciinfo_s +{ + int bus,card,func; /* PCI/AGP bus:card:func */ + unsigned short vendor,device; /* Card vendor+device ID */ + unsigned long base0,base1,base2,baserom; /* Memory and I/O base addresses */ + unsigned long base3,base4,base5; /* Memory and I/O base addresses */ + unsigned char irq,ipin,gnt,lat; /* assigned IRQ parameters for this card */ +// unsigned base0_limit, base1_limit, base2_limit, baserom_limit; +}pciinfo_t; + +extern int pci_config_read(unsigned char bus, unsigned char dev, unsigned char func, + unsigned char cmd, int len, unsigned long *val); +extern int pci_config_write(unsigned char bus, unsigned char dev, unsigned char func, + unsigned char cmd, int len, unsigned long val); + /* Fill array pci_list which must have size MAX_PCI_DEVICES + and return 0 if sucessful */ +extern int pci_scan(pciinfo_t *pci_list,unsigned *num_card); + + /* Enables/disables accessing to IO space from application side. + Should return 0 if o'k or errno on error. */ +extern int enable_app_io( void ); +extern int disable_app_io( void ); + +extern unsigned char INPORT8(unsigned idx); +extern unsigned short INPORT16(unsigned idx); +extern unsigned INPORT32(unsigned idx); +#define INPORT(idx) INPORT32(idx) +extern void OUTPORT8(unsigned idx,unsigned char val); +extern void OUTPORT16(unsigned idx,unsigned short val); +extern void OUTPORT32(unsigned idx,unsigned val); +#define OUTPORT(idx,val) OUTPORT32(idx,val) + +extern void * map_phys_mem(unsigned long base, unsigned long size); +extern void unmap_phys_mem(void *ptr, unsigned long size); + +/* These are the region types */ +#define MTRR_TYPE_UNCACHABLE 0 +#define MTRR_TYPE_WRCOMB 1 +#define MTRR_TYPE_WRTHROUGH 4 +#define MTRR_TYPE_WRPROT 5 +#define MTRR_TYPE_WRBACK 6 +extern int mtrr_set_type(unsigned base,unsigned size,int type); + +/* Busmastering support */ + /* returns 0 if support exists else errno */ +extern int bm_open( void ); +extern void bm_close( void ); + /* Converts virtual memory addresses into physical + returns 0 if OK else - errno + parray should have enough length to accept length/page_size + elements. virt_addr can be located in non-continious memory + block and can be allocated by malloc(). (kmalloc() is not + needed). Note: if you have some very old card which requires + continous memory block then you need to implement bm_kmalloc + bm_kfree functions here. NOTE2: to be sure that every page of + region is present in physical memory (is not swapped out) use + m(un)lock functions. Note3: Probably your card will want to + have page-aligned block for DMA transfer so use + memalign(PAGE_SIZE,mem_size) function to alloc such memory. */ +extern int bm_virt_to_phys( void * virt_addr, unsigned long length, + unsigned long * parray ); + /* Converts virtual memory addresses into bus address + Works in the same way as bm_virt_to_phys. + WARNING: This function will be die after implementing + bm_alloc_pci_shmem() because we really can't pass + any memory address to card. Example: 64-bit linear address + can't be passed into 32-bit card. Even more - some old + cards can access 24-bit address space only */ +extern int bm_virt_to_bus( void * virt_addr, unsigned long length, + unsigned long * barray ); + + /* NOTE: bm_alloc_pci_shmem() and bm_free_pci_shmem() + are still not implemented! + arguments: + pciinfo_t - specifies pci card for which memory should be shared + bitness - can be 16,24,32,64 specifies addressing possibilities + of the card + length - specifies size of memory which should allocated + op - specifies direction as combination flags TO_CARD,FROM_CARD + Return value - should be tuned + we need to have something like this: + struct pci_shmem + { + void * handler; + void * virt_addr + void * array_of_bus_addr[]; + unsigned long length; + } + NOTE2: After finalizing of these functions bm_virt_to_bus() will be die */ +extern void * bm_alloc_pci_shmem(pciinfo_t *, unsigned mem_bitness, unsigned long length,int op ); +extern void bm_free_pci_shmem(void * pci_shmem); + +extern int bm_lock_mem( const void * addr, unsigned long length ); +extern int bm_unlock_mem( const void * addr, unsigned long length ); + +/* HWIRQ support */ + +extern int hwirq_install(int bus, int dev, int func, + int areg, unsigned long aoff, uint32_t adata); +extern int hwirq_wait(unsigned irqnum); +extern int hwirq_uninstall(int bus, int dev, int func); + +/* CPU flushing support */ +extern void cpu_flush(void *va,unsigned long length); + +extern void libdha_exit(const char *message, int level); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/contrib/libdha/mmi.c b/contrib/libdha/mmi.c new file mode 100644 index 000000000..39d21926a --- /dev/null +++ b/contrib/libdha/mmi.c @@ -0,0 +1,112 @@ +/* Memory manager interface */ +#include <stdio.h> +#include <sys/ioctl.h> +#include <sys/types.h> +#include <sys/mman.h> /* mlock */ +#include <errno.h> +#include <unistd.h> +#include <fcntl.h> +#include "libdha.h" +#include "kernelhelper/dhahelper.h" + +static int libdha_fd=-1; + +#define ALLOWED_VER 0x10 +int bm_open( void ) +{ + int retv; + libdha_fd = open("/dev/dhahelper",O_RDWR); + retv = libdha_fd > 0 ? 0 : ENXIO; + if(!retv) + { + int ver; + ioctl(libdha_fd,DHAHELPER_GET_VERSION,&ver); + if(ver < ALLOWED_VER) + { + printf("libdha: You have wrong version (%i) of /dev/dhahelper\n" + "libdha: Please upgrade your driver up to ver=%i\n",ver,ALLOWED_VER); + retv = EINVAL; + close(libdha_fd); + } + } + else printf("libdha: Can't open /dev/dhahelper\n"); + return retv; +} + +void bm_close( void ) +{ + close(libdha_fd); +} + +int bm_virt_to_phys( void * virt_addr, unsigned long length, unsigned long * parray ) +{ + dhahelper_vmi_t vmi; + vmi.virtaddr = virt_addr; + vmi.length = length; + vmi.realaddr = parray; + if(libdha_fd > 0) return ioctl(libdha_fd,DHAHELPER_VIRT_TO_PHYS,&vmi); + return ENXIO; +} + +int bm_virt_to_bus( void * virt_addr, unsigned long length, unsigned long * barray ) +{ + dhahelper_vmi_t vmi; + vmi.virtaddr = virt_addr; + vmi.length = length; + vmi.realaddr = barray; + if(libdha_fd > 0) return ioctl(libdha_fd,DHAHELPER_VIRT_TO_BUS,&vmi); + return ENXIO; +} + +void * bm_alloc_pci_shmem(pciinfo_t *pi, unsigned mem_bitness, unsigned long length,int op ) +{ + printf("libdha: Pure virtual function call - bm_alloc_pci_shmem()\n"); +#if 0 + dhahelper_mem_t vmi; + vmi.length = length; + if(libdha_fd > 0) + { + if(ioctl(libdha_fd,DHAHELPER_ALLOC_PA,&vmi) == 0) + return vmi.addr; + } +#endif + return NULL; +} + +void bm_free_pci_shmem(void * pci_shmem) +{ + printf("libdha: Pure virtual function call - bm_free_pci_shmem()\n"); +#if 0 + dhahelper_mem_t vmi; + vmi.addr = virt_addr; + vmi.length = length; + if(libdha_fd > 0) + { + ioctl(libdha_fd,DHAHELPER_FREE_PA,&vmi); + } +#endif +} + +int bm_lock_mem( const void *addr, unsigned long length ) +{ + dhahelper_mem_t vmi; + vmi.addr = (void *) addr; + vmi.length = length; + if(libdha_fd > 0) + { + return ioctl(libdha_fd,DHAHELPER_LOCK_MEM,&vmi); + } + return mlock(addr,length); +} + +int bm_unlock_mem( const void * addr, unsigned long length ) +{ + dhahelper_mem_t vmi; + vmi.addr = (void *) addr; + vmi.length = length; + if(libdha_fd > 0) + { + return ioctl(libdha_fd,DHAHELPER_UNLOCK_MEM,&vmi); + } + return munlock(addr,length); +} diff --git a/contrib/libdha/mtrr.c b/contrib/libdha/mtrr.c new file mode 100644 index 000000000..48ae5a1fd --- /dev/null +++ b/contrib/libdha/mtrr.c @@ -0,0 +1,91 @@ +/* + mtrr.c - Stuff for optimizing memory access + Copyrights: + 2002 - Linux version by Nick Kurshev + Licence: GPL +*/ + +#include "config.h" + +#include <stdio.h> +#include <string.h> +#include <errno.h> +#include <unistd.h> +#include <fcntl.h> +#include <sys/ioctl.h> +#include "kernelhelper/dhahelper.h" +#include "libdha.h" + +#if defined (__i386__) && defined (__NetBSD__) +#include <sys/param.h> +#if __NetBSD_Version__ > 105240000 +#include <stdint.h> +#include <stdlib.h> +#include <machine/mtrr.h> +#include <machine/sysarch.h> +#endif +#endif + +int mtrr_set_type(unsigned base,unsigned size,int type) +{ + int dhahelper_fd; + dhahelper_fd = open("/dev/dhahelper",O_RDWR); + if(dhahelper_fd > 0) + { + int retval; + dhahelper_mtrr_t mtrrs; + mtrrs.operation = MTRR_OP_ADD; + mtrrs.start = base; + mtrrs.size = size; + mtrrs.type = type; + retval = ioctl(dhahelper_fd, DHAHELPER_ACK_IRQ, &mtrrs); + close(dhahelper_fd); + return retval; + } +#if defined (__NetBSD__) && (__NetBSD_Version__) > 105240000 + { + struct mtrr *mtrrp; + int n; + + mtrrp = malloc(sizeof (struct mtrr)); + mtrrp->base = base; + mtrrp->len = size; + mtrrp->type = type; + mtrrp->flags = MTRR_VALID | MTRR_PRIVATE; + n = 1; + + if (i386_set_mtrr(mtrrp, &n) < 0) { + free(mtrrp); + return errno; + } + free(mtrrp); + return 0; + } +#else + { + FILE * mtrr_fd; + char * stype; + switch(type) + { + case MTRR_TYPE_UNCACHABLE: stype = "uncachable"; break; + case MTRR_TYPE_WRCOMB: stype = "write-combining"; break; + case MTRR_TYPE_WRTHROUGH: stype = "write-through"; break; + case MTRR_TYPE_WRPROT: stype = "write-protect"; break; + case MTRR_TYPE_WRBACK: stype = "write-back"; break; + default: return EINVAL; + } + mtrr_fd = fopen("/proc/mtrr","wt"); + if(mtrr_fd) + { + char sout[256]; + unsigned wr_len; + sprintf(sout,"base=0x%08X size=0x%08X type=%s\n",base,size,stype); + wr_len = fprintf(mtrr_fd,"%s",sout); + /*printf("MTRR: %s\n",sout);*/ + fclose(mtrr_fd); + return wr_len == strlen(sout) ? 0 : EPERM; + } + } +#endif + return ENOSYS; +} diff --git a/contrib/libdha/oth/Makefile.am b/contrib/libdha/oth/Makefile.am new file mode 100644 index 000000000..55651d233 --- /dev/null +++ b/contrib/libdha/oth/Makefile.am @@ -0,0 +1,3 @@ +include $(top_srcdir)/misc/Makefile.common + +EXTRA_DIST = pci.db diff --git a/contrib/libdha/oth/pci.db b/contrib/libdha/oth/pci.db new file mode 100644 index 000000000..083b2892f --- /dev/null +++ b/contrib/libdha/oth/pci.db @@ -0,0 +1,9471 @@ +v 0000 Gammagraphx, Inc. 0 +v 001a Ascend Communications, Inc. 0 +v 0033 Paradyne corp. 0 +v 003d Lockheed Martin-Marietta Corp 0 +v 0059 Tiger Jet Network Inc. (Wrong ID) 0 Real TJN ID is e159, but they got it wrong several times --mj +v 0070 Hauppauge computer works Inc. 0 +d 00704000 WinTV PVR-350 0 +d 00704001 WinTV PVR-250 (v1) 0 +d 00704009 WinTV PVR-250 0 +d 00704801 WinTV PVR-250 MCE 0 +v 0071 Nebula Electronics Ltd. 0 +v 0095 Silicon Image, Inc. (Wrong ID) 0 +d 00950680 Ultra ATA/133 IDE RAID CONTROLLER CARD 0 +v 0100 Ncipher Corp Ltd 0 +v 018a LevelOne 0 018a is not LevelOne but there is a board misprogrammed +d 018a0106 FPC-0106TX misprogrammed [RTL81xx] 0 +v 021b Compaq Computer Corporation 0 021b is not Compaq but there is a board misprogrammed +d 021b8139 HNE-300 (RealTek RTL8139c) [iPaq Networking] 0 +v 0291 Davicom Semiconductor, Inc. 0 http://www.davicom.com.tw/ +d 02918212 DM9102A(DM9102AE, SM9102AF) Ethernet 100/10 MBit(Rev 40) 0 +v 02ac SpeedStream 0 SpeedStream is Efficient Networks, Inc, a Siemens Company +d 02ac1012 1012 PCMCIA 10/100 Ethernet Card [RTL81xx] 0 +v 0357 TTTech AG 0 +d 0357000a TTP-Monitoring Card V2.0 0 +v 05e3 CyberDoor 0 +d 05e30701 CBD516 0 +v 0675 Dynalink 0 +d 06751700 IS64PH ISDN Adapter 0 +d 06751702 IS64PH ISDN Adapter 0 +v 0925 VIA Technologies, Inc. (Wrong ID) 0 Wrong ID used in subsystem ID of VIA USB controllers. +v 09c1 Arris 0 +d 09c10704 CM 200E Cable Modem 0 +v 0a89 BREA Technologies Inc 0 +v 0b49 ASCII Corporation 0 +d 0b49064f Trance Vibrator 0 see http://homepage1.nifty.com/mcn/lab/machines/trance_vibrator/usbview.vib.txt +v 0e11 Compaq Computer Corporation 0 +d 0e110001 PCI to EISA Bridge 0 +d 0e110002 PCI to ISA Bridge 0 +d 0e110046 Smart Array 64xx 0 +s 0e1100460e11409a Smart Array 641 0 +s 0e1100460e11409b Smart Array 642 0 +s 0e1100460e11409c Smart Array 6400 0 +s 0e1100460e11409d Smart Array 6400 EM 0 +d 0e110049 NC7132 Gigabit Upgrade Module 0 +d 0e11004a NC6136 Gigabit Server Adapter 0 +d 0e11007c NC7770 1000BaseTX 0 +d 0e11007d NC6770 1000BaseTX 0 +d 0e110085 NC7780 1000BaseTX 0 +d 0e1100bb NC7760 0 +d 0e1100ca NC7771 0 +d 0e1100cb NC7781 0 +d 0e1100cf NC7772 0 +d 0e1100d0 NC7782 0 +d 0e1100d1 NC7783 0 +d 0e1100e3 NC7761 0 +d 0e110508 Netelligent 4/16 Token Ring 0 +d 0e111000 Triflex/Pentium Bridge, Model 1000 0 +d 0e112000 Triflex/Pentium Bridge, Model 2000 0 +d 0e113032 QVision 1280/p 0 +d 0e113033 QVision 1280/p 0 +d 0e113034 QVision 1280/p 0 +d 0e114000 4000 [Triflex] 0 +d 0e114030 SMART-2/P 0 +d 0e114031 SMART-2SL 0 +d 0e114032 Smart Array 3200 0 +d 0e114033 Smart Array 3100ES 0 +d 0e114034 Smart Array 221 0 +d 0e114040 Integrated Array 0 +d 0e114048 Compaq Raid LC2 0 +d 0e114050 Smart Array 4200 0 +d 0e114051 Smart Array 4250ES 0 +d 0e114058 Smart Array 431 0 +d 0e114070 Smart Array 5300 0 +d 0e114080 Smart Array 5i 0 +d 0e114082 Smart Array 532 0 +d 0e114083 Smart Array 5312 0 +d 0e114091 Smart Array 6i 0 +d 0e11409a Smart Array 641 0 +d 0e11409b Smart Array 642 0 +d 0e11409c Smart Array 6400 0 +d 0e11409d Smart Array 6400 EM 0 +d 0e116010 HotPlug PCI Bridge 6010 0 +d 0e117020 USB Controller 0 +d 0e11a0ec Fibre Channel Host Controller 0 +d 0e11a0f0 Advanced System Management Controller 0 +d 0e11a0f3 Triflex PCI to ISA Bridge 0 +d 0e11a0f7 PCI Hotplug Controller 0 +s 0e11a0f78086002a PCI Hotplug Controller A 0 +s 0e11a0f78086002b PCI Hotplug Controller B 0 +d 0e11a0f8 ZFMicro Chipset USB 0 +d 0e11a0fc FibreChannel HBA Tachyon 0 +d 0e11ae10 Smart-2/P RAID Controller 0 +s 0e11ae100e114030 Smart-2/P Array Controller 0 +s 0e11ae100e114031 Smart-2SL Array Controller 0 +s 0e11ae100e114032 Smart Array Controller 0 +s 0e11ae100e114033 Smart 3100ES Array Controller 0 +d 0e11ae29 MIS-L 0 +d 0e11ae2a MPC 0 +d 0e11ae2b MIS-E 0 +d 0e11ae31 System Management Controller 0 +d 0e11ae32 Netelligent 10/100 TX PCI UTP 0 +d 0e11ae33 Triflex Dual EIDE Controller 0 +d 0e11ae34 Netelligent 10 T PCI UTP 0 +d 0e11ae35 Integrated NetFlex-3/P 0 +d 0e11ae40 Netelligent Dual 10/100 TX PCI UTP 0 +d 0e11ae43 Netelligent Integrated 10/100 TX UTP 0 +d 0e11ae69 CETUS-L 0 +d 0e11ae6c Northstar 0 +d 0e11ae6d NorthStar CPU to PCI Bridge 0 +d 0e11b011 Netelligent 10/100 TX Embedded UTP 0 +d 0e11b012 Netelligent 10 T/2 PCI UTP/Coax 0 +d 0e11b01e NC3120 Fast Ethernet NIC 0 +d 0e11b01f NC3122 Fast Ethernet NIC 0 +d 0e11b02f NC1120 Ethernet NIC 0 +d 0e11b030 Netelligent 10/100 TX UTP 0 +d 0e11b04a 10/100 TX PCI Intel WOL UTP Controller 0 +d 0e11b060 Smart Array 5300 Controller 0 +d 0e11b0c6 NC3161 Fast Ethernet NIC 0 +d 0e11b0c7 NC3160 Fast Ethernet NIC 0 +d 0e11b0d7 NC3121 Fast Ethernet NIC 0 +d 0e11b0dd NC3131 Fast Ethernet NIC 0 +d 0e11b0de NC3132 Fast Ethernet Module 0 +d 0e11b0df NC6132 Gigabit Module 0 +d 0e11b0e0 NC6133 Gigabit Module 0 +d 0e11b0e1 NC3133 Fast Ethernet Module 0 +d 0e11b123 NC6134 Gigabit NIC 0 +d 0e11b134 NC3163 Fast Ethernet NIC 0 +d 0e11b13c NC3162 Fast Ethernet NIC 0 +d 0e11b144 NC3123 Fast Ethernet NIC 0 +d 0e11b163 NC3134 Fast Ethernet NIC 0 +d 0e11b164 NC3165 Fast Ethernet Upgrade Module 0 +d 0e11b178 Smart Array 5i/532 0 +s 0e11b1780e114080 Smart Array 5i 0 +s 0e11b1780e114082 Smart Array 532 0 +s 0e11b1780e114083 Smart Array 5312 0 +d 0e11b1a4 NC7131 Gigabit Server Adapter 0 +d 0e11b200 Memory Hot-Plug Controller 0 HP Memory Hot-Plug Controller +d 0e11b203 Integrated Lights Out Controller 0 +d 0e11b204 Integrated Lights Out Processor 0 +d 0e11f130 NetFlex-3/P ThunderLAN 1.0 0 +d 0e11f150 NetFlex-3/P ThunderLAN 2.3 0 +v 0e55 HaSoTec GmbH 0 +v 1000 LSI Logic / Symbios Logic 0 Formerly NCR +d 10000001 53c810 0 +s 1000000110001000 LSI53C810AE PCI to SCSI I/O Processor 0 +d 10000002 53c820 0 +d 10000003 53c825 0 +s 1000000310001000 LSI53C825AE PCI to SCSI I/O Processor (Ultra Wide) 0 +d 10000004 53c815 0 +d 10000005 53c810AP 0 +d 10000006 53c860 0 +s 1000000610001000 LSI53C860E PCI to Ultra SCSI I/O Processor 0 +d 1000000a 53c1510 0 +s 1000000a10001000 LSI53C1510 PCI to Dual Channel Wide Ultra2 SCSI Controller (Nonintelligent mode) 0 +d 1000000b 53C896/897 0 +s 1000000b0e116004 EOB003 Series SCSI host adapter 0 +s 1000000b10001000 LSI53C896/7 PCI to Dual Channel Ultra2 SCSI Multifunction Controller 0 +s 1000000b10001010 LSI22910 PCI to Dual Channel Ultra2 SCSI host adapter 0 +s 1000000b10001020 LSI21002 PCI to Dual Channel Ultra2 SCSI host adapter 0 +s 1000000b13e91000 6221L-4U 0 multifunction PCI card: Dual U2W SCSI, dual 10/100TX, graphics +d 1000000c 53c895 0 +s 1000000c10001010 LSI8951U PCI to Ultra2 SCSI host adapter 0 +s 1000000c10001020 LSI8952U PCI to Ultra2 SCSI host adapter 0 +s 1000000c1de13906 DC-390U2B SCSI adapter 0 +s 1000000c1de13907 DC-390U2W 0 +d 1000000d 53c885 0 +d 1000000f 53c875 0 +s 1000000f0e117004 Embedded Ultra Wide SCSI Controller 0 +s 1000000f10001000 LSI53C876/E PCI to Dual Channel SCSI Controller 0 +s 1000000f10001010 LSI22801 PCI to Dual Channel Ultra SCSI host adapter 0 +s 1000000f10001020 LSI22802 PCI to Dual Channel Ultra SCSI host adapter 0 +s 1000000f10928760 FirePort 40 Dual SCSI Controller 0 +s 1000000f1de13904 DC390F/U Ultra Wide SCSI Adapter 0 +s 1000000f4c531000 CC7/CR7/CP7/VC7/VP7/VR7 mainboard 0 +s 1000000f4c531050 CT7 mainboard 0 +d 10000010 53C1510 0 +s 100000100e114040 Integrated Array Controller 0 +s 100000100e114048 RAID LC2 Controller 0 +s 1000001010001000 53C1510 PCI to Dual Channel Wide Ultra2 SCSI Controller (Intelligent mode) 0 +d 10000012 53c895a 0 +s 1000001210001000 LSI53C895A PCI to Ultra2 SCSI Controller 0 +d 10000013 53c875a 0 +s 1000001310001000 LSI53C875A PCI to Ultra SCSI Controller 0 +d 10000020 53c1010 Ultra3 SCSI Adapter 0 +s 1000002010001000 LSI53C1010-33 PCI to Dual Channel Ultra160 SCSI Controller 0 +s 100000201de11020 DC-390U3W 0 +d 10000021 53c1010 66MHz Ultra3 SCSI Adapter 0 +s 1000002110001000 LSI53C1000/1000R/1010R/1010-66 PCI to Ultra160 SCSI Controller 0 +s 1000002110001010 Asus TR-DLS onboard 53C1010-66 0 +s 10000021124b1070 PMC-USCSI3 0 +s 100000214c531080 CT8 mainboard 0 +s 100000214c531300 P017 mezzanine (32-bit PMC) 0 +s 100000214c531310 P017 mezzanine (64-bit PMC) 0 +d 10000030 53c1030 PCI-X Fusion-MPT Dual Ultra320 SCSI 0 +s 1000003010280123 PowerEdge 2600 0 +s 100000301028014a PowerEdge 1750 0 +s 100000301028016c PowerEdge 1850 MPT Fusion SCSI/RAID (Perc 4) 0 +s 1000003010281010 LSI U320 SCSI Controller 0 +d 10000031 53c1030ZC PCI-X Fusion-MPT Dual Ultra320 SCSI 0 +d 10000032 53c1035 PCI-X Fusion-MPT Dual Ultra320 SCSI 0 +s 1000003210001000 LSI53C1020/1030 PCI-X to Ultra320 SCSI Controller 0 +d 10000033 1030ZC_53c1035 PCI-X Fusion-MPT Dual Ultra320 SCSI 0 +d 10000040 53c1035 PCI-X Fusion-MPT Dual Ultra320 SCSI 0 +s 1000004010000033 MegaRAID SCSI 320-2XR 0 +s 1000004010000066 MegaRAID SCSI 320-2XRWS 0 +d 10000041 53C1035ZC PCI-X Fusion-MPT Dual Ultra320 SCSI 0 +d 1000008f 53c875J 0 +s 1000008f10928000 FirePort 40 SCSI Controller 0 +s 1000008f10928760 FirePort 40 Dual SCSI Host Adapter 0 +d 10000407 MegaRAID 0 +s 1000040710000530 MegaRAID 530 SCSI 320-0X RAID Controller 0 +s 1000040710000531 MegaRAID 531 SCSI 320-4X RAID Controller 0 +s 1000040710000532 MegaRAID 532 SCSI 320-2X RAID Controller 0 +s 1000040710280531 PowerEdge Expandable RAID Controller 4/QC 0 +s 1000040710280533 PowerEdge Expandable RAID Controller 4/QC 0 +s 1000040780860530 MegaRAID Intel RAID Controller SRCZCRX 0 +s 1000040780860532 MegaRAID Intel RAID Controller SRCU42X 0 +d 10000408 MegaRAID 0 +s 1000040810000001 MegaRAID SCSI 320-1E RAID Controller 0 +s 1000040810000002 MegaRAID SCSI 320-2E RAID Controller 0 +s 100004081025004d MegaRAID ACER ROMB-2E RAID Controller 0 +s 1000040810280001 PowerEdge RAID Controller PERC4e/SC 0 +s 1000040810280002 PowerEdge RAID Controller PERC4e/DC 0 +s 1000040817341065 FSC MegaRAID PCI Express ROMB 0 +s 1000040880860002 MegaRAID Intel RAID Controller SRCU42E 0 +d 10000409 MegaRAID 0 +s 1000040910003004 MegaRAID SATA 300-4X RAID Controller 0 +s 1000040910003008 MegaRAID SATA 300-8X RAID Controller 0 +s 1000040980863008 MegaRAID RAID Controller SRCS28X 0 +s 1000040980863431 MegaRAID RAID Controller Alief SROMBU42E 0 +s 1000040980863499 MegaRAID RAID Controller Harwich SROMBU42E 0 +d 10000621 FC909 Fibre Channel Adapter 0 +d 10000622 FC929 Fibre Channel Adapter 0 +s 1000062210001020 44929 O Dual Fibre Channel card 0 +d 10000623 FC929 LAN 0 +d 10000624 FC919 Fibre Channel Adapter 0 +d 10000625 FC919 LAN 0 +d 10000626 FC929X Fibre Channel Adapter 0 +s 1000062610001010 7202-XP-LC Dual Fibre Channel card 0 +d 10000627 FC929X LAN 0 +d 10000628 FC919X Fibre Channel Adapter 0 +d 10000629 FC919X LAN 0 +d 10000701 83C885 NT50 DigitalScape Fast Ethernet 0 +d 10000702 Yellowfin G-NIC gigabit ethernet 0 +s 1000070213180000 PEI100X 0 +d 10000804 SA2010 0 +d 10000805 SA2010ZC 0 +d 10000806 SA2020 0 +d 10000807 SA2020ZC 0 +d 10000901 61C102 0 +d 10001000 63C815 0 +d 10001960 MegaRAID 0 +s 1000196010000518 MegaRAID 518 SCSI 320-2 Controller 0 +s 1000196010000520 MegaRAID 520 SCSI 320-1 Controller 0 +s 1000196010000522 MegaRAID 522 i4 133 RAID Controller 0 +s 1000196010000523 MegaRAID SATA 150-6 RAID Controller 0 +s 1000196010004523 MegaRAID SATA 150-4 RAID Controller 0 +s 100019601000a520 MegaRAID ZCR SCSI 320-0 Controller 0 +s 1000196010280518 MegaRAID 518 DELL PERC 4/DC RAID Controller 0 +s 1000196010280520 MegaRAID 520 DELL PERC 4/SC RAID Controller 0 +s 1000196010280531 PowerEdge Expandable RAID Controller 4/QC 0 +s 1000196010280533 PowerEdge Expandable RAID Controller 4/QC 0 +s 1000196080860520 MegaRAIDRAID Controller SRCU41L 0 +s 1000196080860523 MegaRAID RAID Controller SRCS16 0 +v 1001 Kolter Electronic 0 +d 10010010 PCI 1616 Measurement card with 32 digital I/O lines 0 +d 10010011 OPTO-PCI Opto-Isolated digital I/O board 0 +d 10010012 PCI-AD/DA Analogue I/O board 0 +d 10010013 PCI-OPTO-RELAIS Digital I/O board with relay outputs 0 +d 10010014 PCI-Counter/Timer Counter Timer board 0 +d 10010015 PCI-DAC416 Analogue output board 0 +d 10010016 PCI-MFB Analogue I/O board 0 +d 10010017 PROTO-3 PCI Prototyping board 0 +d 10019100 INI-9100/9100W SCSI Host 0 +v 1002 ATI Technologies Inc 0 +d 10023150 M24 1P [Radeon Mobility X600] 0 +d 10023154 M24 1T [FireGL M24 GL] 0 +d 10023e50 RV380 0x3e50 [Radeon X600] 0 +d 10023e54 RV380 0x3e54 [FireGL V3200] 0 +d 10023e70 RV380 [Radeon X600] Secondary 0 +d 10024136 Radeon IGP 320 M 0 +d 10024137 Radeon IGP330/340/350 0 +d 10024144 R300 AD [Radeon 9500 Pro] 0 +d 10024145 R300 AE [Radeon 9700 Pro] 0 New PCI ID provided by ATI developer relations (correction to above) +d 10024146 R300 AF [Radeon 9700 Pro] 0 New PCI ID provided by ATI developer relations (oops, correction to above) +d 10024147 R300 AG [FireGL Z1/X1] 0 +d 10024148 R350 AH [Radeon 9800] 0 +d 10024149 R350 AI [Radeon 9800] 0 +d 1002414a R350 AJ [Radeon 9800] 0 +d 1002414b R350 AK [Fire GL X2] 0 +d 10024150 RV350 AP [Radeon 9600] 0 New PCI ID provided by ATI developer relations +s 1002415010020002 R9600 Pro primary (Asus OEM for HP) 0 +s 1002415010020003 R9600 Pro secondary (Asus OEM for HP) 0 +s 1002415014584024 Giga-Byte GV-R96128D Primary 0 +s 10024150148c2064 PowerColor R96A-C3N 0 +s 10024150148c2066 PowerColor R96A-C3N 0 +s 10024150174b7c19 Sapphire Atlantis Radeon 9600 Pro 0 +s 10024150174b7c29 GC-R9600PRO Primary [Sapphire] 0 +s 1002415017ee2002 Radeon 9600 256Mb Primary 0 +s 1002415018bc0101 GC-R9600PRO Primary 0 +d 10024151 RV350 AQ [Radeon 9600] 0 New PCI ID provided by ATI developer relations +s 100241511043c004 A9600SE 0 +d 10024152 RV350 AR [Radeon 9600] 0 New PCI ID provided by ATI developer relations +s 1002415210020002 Radeon 9600XT 0 +s 100241521043c002 Radeon 9600 XT TVD 0 +d 10024153 RV350 AS [Radeon 9600 AS] 0 +d 10024154 RV350 AT [Fire GL T2] 0 +d 10024155 RV350 AU [Fire GL T2] 0 +d 10024156 RV350 AV [Fire GL T2] 0 +d 10024157 RV350 AW [Fire GL T2] 0 +d 10024158 68800AX [Mach32] 0 +d 10024164 R300 AD [Radeon 9500 Pro] (Secondary) 0 The PCI ID is unrelated to any DVI output. +d 10024165 R300 AE [Radeon 9700 Pro] (Secondary) 0 New PCI ID info provided by ATI developer relations +d 10024166 R300 AF [Radeon 9700 Pro] (Secondary) 0 New PCI ID info provided by ATI developer relations +d 10024168 Radeon R350 [Radeon 9800] (Secondary) 0 New PCI ID provided by ATI developer relations +d 10024170 RV350 AP [Radeon 9600] (Secondary) 0 New PCI ID provided by ATI developer relations (correction to above) +s 1002417014584025 Giga-Byte GV-R96128D Secondary 0 +s 10024170148c2067 PowerColor R96A-C3N (Secondary) 0 +s 10024170174b7c28 GC-R9600PRO Secondary [Sapphire] 0 +s 1002417017ee2003 Radeon 9600 256Mb Secondary 0 +s 1002417018bc0100 GC-R9600PRO Secondary 0 +d 10024171 RV350 AQ [Radeon 9600] (Secondary) 0 New PCI ID provided by ATI developer relations (correction to above) +s 100241711043c005 A9600SE (Secondary) 0 +d 10024172 RV350 AR [Radeon 9600] (Secondary) 0 New PCI ID provided by ATI developer relations (correction to above) +s 1002417210020003 Radeon 9600XT (Secondary) 0 +s 100241721043c003 A9600XT (Secondary) 0 +d 10024173 RV350 ?? [Radeon 9550] (Secondary) 0 +d 10024237 Radeon 7000 IGP 0 +d 10024242 R200 BB [Radeon All in Wonder 8500DV] 0 +s 10024242100202aa Radeon 8500 AIW DV Edition 0 +d 10024243 R200 BC [Radeon All in Wonder 8500] 0 +d 10024336 Radeon Mobility U1 0 +s 10024336103c0024 Pavilion ze4400 builtin Video 0 +d 10024337 Radeon IGP 330M/340M/350M 0 +s 100243371014053a ThinkPad R40e (2684-HVG) builtin VGA controller 0 +s 10024337103c0850 Radeon IGP 345M 0 +d 10024341 IXP150 AC'97 Audio Controller 0 +d 10024345 EHCI USB Controller 0 +d 10024347 OHCI USB Controller #1 0 +d 10024348 OHCI USB Controller #2 0 +d 1002434d IXP AC'97 Modem 0 +d 10024353 ATI SMBus 0 Radeon 9100 IGP integrated +d 10024354 215CT [Mach64 CT] 0 +d 10024358 210888CX [Mach64 CX] 0 +d 10024437 Radeon Mobility 7000 IGP 0 +d 10024554 210888ET [Mach64 ET] 0 +d 10024654 Mach64 VT 0 +d 10024742 3D Rage Pro AGP 1X/2X 0 +s 1002474210020040 Rage Pro Turbo AGP 2X 0 +s 1002474210020044 Rage Pro Turbo AGP 2X 0 +s 1002474210020061 Rage Pro AIW AGP 2X 0 +s 1002474210020062 Rage Pro AIW AGP 2X 0 +s 1002474210020063 Rage Pro AIW AGP 2X 0 +s 1002474210020080 Rage Pro Turbo AGP 2X 0 +s 1002474210020084 Rage Pro Turbo AGP 2X 0 +s 1002474210024742 Rage Pro Turbo AGP 2X 0 +s 1002474210028001 Rage Pro Turbo AGP 2X 0 +s 1002474210280082 Rage Pro Turbo AGP 2X 0 +s 1002474210284082 Optiplex GX1 Onboard Display Adapter 0 +s 1002474210288082 Rage Pro Turbo AGP 2X 0 +s 100247421028c082 Rage Pro Turbo AGP 2X 0 +s 1002474280864152 Xpert 98D AGP 2X 0 +s 100247428086464a Rage Pro Turbo AGP 2X 0 +d 10024744 3D Rage Pro AGP 1X 0 +s 1002474410024744 Rage Pro Turbo AGP 0 +d 10024747 3D Rage Pro 0 +d 10024749 3D Rage Pro 0 +s 1002474910020061 Rage Pro AIW 0 +s 1002474910020062 Rage Pro AIW 0 +d 1002474c Rage XC 0 +d 1002474d Rage XL AGP 2X 0 +s 1002474d10020004 Xpert 98 RXL AGP 2X 0 +s 1002474d10020008 Xpert 98 RXL AGP 2X 0 +s 1002474d10020080 Rage XL AGP 2X 0 +s 1002474d10020084 Xpert 98 AGP 2X 0 +s 1002474d1002474d Rage XL AGP 0 +s 1002474d1033806a Rage XL AGP 0 +d 1002474e Rage XC AGP 0 +s 1002474e1002474e Rage XC AGP 0 +d 1002474f Rage XL 0 +s 1002474f10020008 Rage XL 0 +s 1002474f1002474f Rage XL 0 +d 10024750 3D Rage Pro 215GP 0 +s 1002475010020040 Rage Pro Turbo 0 +s 1002475010020044 Rage Pro Turbo 0 +s 1002475010020080 Rage Pro Turbo 0 +s 1002475010020084 Rage Pro Turbo 0 +s 1002475010024750 Rage Pro Turbo 0 +d 10024751 3D Rage Pro 215GQ 0 +d 10024752 Rage XL 0 +s 1002475210020008 Rage XL 0 +s 1002475210024752 Rage XL 0 +s 1002475210028008 Rage XL 0 +s 10024752102800ce PowerEdge 1400 0 +s 10024752102800d1 PowerEdge 2550 0 +s 10024752102800d9 PowerEdge 2500 0 +s 1002475280863411 SDS2 Mainboard 0 +s 1002475280863427 S875WP1-E mainboard 0 +d 10024753 Rage XC 0 +s 1002475310024753 Rage XC 0 +d 10024754 3D Rage I/II 215GT [Mach64 GT] 0 +d 10024755 3D Rage II+ 215GTB [Mach64 GTB] 0 +d 10024756 3D Rage IIC 215IIC [Mach64 GT IIC] 0 +s 1002475610024756 Rage IIC 0 +d 10024757 3D Rage IIC AGP 0 +s 1002475710024757 Rage IIC AGP 0 +s 1002475710280089 Rage 3D IIC 0 +s 1002475710284082 Rage 3D IIC 0 +s 1002475710288082 Rage 3D IIC 0 +s 100247571028c082 Rage 3D IIC 0 +d 10024758 210888GX [Mach64 GX] 0 +d 10024759 3D Rage IIC 0 +d 1002475a 3D Rage IIC AGP 0 +s 1002475a10020084 Rage 3D Pro AGP 2x XPERT 98 0 +s 1002475a10020087 Rage 3D IIC 0 +s 1002475a1002475a Rage IIC AGP 0 +d 10024964 Radeon RV250 Id [Radeon 9000] 0 +d 10024965 Radeon RV250 Ie [Radeon 9000] 0 +d 10024966 Radeon RV250 If [Radeon 9000] 0 +s 1002496610f10002 RV250 If [Tachyon G9000 PRO] 0 +s 10024966148c2039 RV250 If [Radeon 9000 Pro "Evil Commando"] 0 +s 1002496615099a00 RV250 If [Radeon 9000 "AT009"] 0 +s 1002496616810040 RV250 If [3D prophet 9000] 0 New subdevice - 3D Prophet 9000 PCI by Hercules. AGP version probably would have same ID, so not specified. +s 10024966174b7176 RV250 If [Sapphire Radeon 9000 Pro] 0 +s 10024966174b7192 RV250 If [Radeon 9000 "Atlantis"] 0 +s 1002496617af2005 RV250 If [Excalibur Radeon 9000 Pro] 0 +s 1002496617af2006 RV250 If [Excalibur Radeon 9000] 0 +d 10024967 Radeon RV250 Ig [Radeon 9000] 0 +d 1002496e Radeon RV250 [Radeon 9000] (Secondary) 0 +d 10024a48 R420 JH [Radeon X800] 0 +d 10024a49 R420 JI [Radeon X800PRO] 0 +d 10024a4a R420 JJ [Radeon X800SE] 0 +d 10024a4b R420 JK [Radeon X800] 0 +d 10024a4c R420 JL [Radeon X800] 0 +d 10024a4d R420 JM [FireGL X3] 0 +d 10024a4e M18 JN [Radeon Mobility 9800] 0 +d 10024a50 R420 JP [Radeon X800XT] 0 +d 10024a70 R420 [X800XT-PE] (Secondary) 0 +d 10024c42 3D Rage LT Pro AGP-133 0 +s 10024c420e11b0e7 Rage LT Pro (Compaq Presario 5240) 0 +s 10024c420e11b0e8 Rage 3D LT Pro 0 +s 10024c420e11b10e 3D Rage LT Pro (Compaq Armada 1750) 0 +s 10024c4210020040 Rage LT Pro AGP 2X 0 +s 10024c4210020044 Rage LT Pro AGP 2X 0 +s 10024c4210024c42 Rage LT Pro AGP 2X 0 +s 10024c4210028001 Rage LT Pro AGP 2X 0 +s 10024c4210280085 Rage 3D LT Pro 0 +d 10024c44 3D Rage LT Pro AGP-66 0 +d 10024c45 Rage Mobility M3 AGP 0 +d 10024c46 Rage Mobility M3 AGP 2x 0 +s 10024c46102800b1 Latitude C600 0 +d 10024c47 3D Rage LT-G 215LG 0 +d 10024c49 3D Rage LT Pro 0 +s 10024c4910020004 Rage LT Pro 0 +s 10024c4910020040 Rage LT Pro 0 +s 10024c4910020044 Rage LT Pro 0 +s 10024c4910024c49 Rage LT Pro 0 +d 10024c4d Rage Mobility P/M AGP 2x 0 +s 10024c4d0e11b111 Armada M700 0 +s 10024c4d0e11b160 Armada E500 0 +s 10024c4d10020084 Xpert 98 AGP 2X (Mobility) 0 +s 10024c4d10140154 ThinkPad A20m 0 +s 10024c4d102800aa Latitude CPt 0 +d 10024c4e Rage Mobility L AGP 2x 0 +d 10024c50 3D Rage LT Pro 0 +s 10024c5010024c50 Rage LT Pro 0 +d 10024c51 3D Rage LT Pro 0 +d 10024c52 Rage Mobility P/M 0 +s 10024c5210338112 Versa Note VXi 0 +d 10024c53 Rage Mobility L 0 +d 10024c54 264LT [Mach64 LT] 0 +d 10024c57 Radeon Mobility M7 LW [Radeon Mobility 7500] 0 +s 10024c5710140517 ThinkPad T30 0 +s 10024c57102800e6 Radeon Mobility M7 LW (Dell Inspiron 8100) 0 +s 10024c571028012a Latitude C640 0 +s 10024c57144dc006 Radeon Mobility M7 LW in vpr Matrix 170B4 0 +d 10024c58 Radeon RV200 LX [Mobility FireGL 7800 M7] 0 +d 10024c59 Radeon Mobility M6 LY 0 +s 10024c5910140235 ThinkPad A30/A30p (2652/2653) 0 +s 10024c5910140239 ThinkPad X22/X23/X24 0 +s 10024c59104d80e7 VAIO PCG-GR214EP/GR214MP/GR215MP/GR314MP/GR315MP 0 +d 10024c5a Radeon Mobility M6 LZ 0 +d 10024c64 Radeon R250 Ld [Radeon Mobility 9000 M9] 0 +d 10024c65 Radeon R250 Le [Radeon Mobility 9000 M9] 0 +d 10024c66 Radeon R250 Lf [FireGL 9000] 0 +d 10024c67 Radeon R250 Lg [Radeon Mobility 9000 M9] 0 +d 10024c6e Radeon R250 Ln [Radeon Mobility 9000 M9] [Secondary] 0 Secondary chip to the Lf +d 10024d46 Rage Mobility M4 AGP 0 +d 10024d4c Rage Mobility M4 AGP 0 +d 10024e44 Radeon R300 ND [Radeon 9700 Pro] 0 +d 10024e45 Radeon R300 NE [Radeon 9500 Pro] 0 +s 10024e4510020002 Radeon R300 NE [Radeon 9500 Pro] 0 +s 10024e4516810002 Hercules 3D Prophet 9500 PRO [Radeon 9500 Pro] 0 +d 10024e46 RV350 NF [Radeon 9600] 0 New PCI ID provided by ATI developer relations (correction to above) +d 10024e47 Radeon R300 NG [FireGL X1] 0 +d 10024e48 Radeon R350 [Radeon 9800 Pro] 0 (added pro) +d 10024e49 Radeon R350 [Radeon 9800] 0 New PCI ID provided by ATI developer relations +d 10024e4a RV350 NJ [Radeon 9800 XT] 0 +d 10024e4b R350 NK [Fire GL X2] 0 +d 10024e50 RV350 [Mobility Radeon 9600 M10] 0 New PCI ID provided by ATI developer relations +s 10024e501025005a TravelMate 290 0 +s 10024e50103c0890 NC6000 laptop 0 +s 10024e5017341055 Amilo M1420W 0 +d 10024e51 M10 NQ [Radeon Mobility 9600] 0 +d 10024e52 RV350 [Mobility Radeon 9600 M10] 0 +d 10024e53 M10 NS [Radeon Mobility 9600] 0 +d 10024e54 M10 NT [FireGL Mobility T2] 0 +d 10024e56 M11 NV [FireGL Mobility T2e] 0 +d 10024e64 Radeon R300 [Radeon 9700 Pro] (Secondary) 0 +d 10024e65 Radeon R300 [Radeon 9500 Pro] (Secondary) 0 +s 10024e6510020003 Radeon R300 NE [Radeon 9500 Pro] 0 +s 10024e6516810003 Hercules 3D Prophet 9500 PRO [Radeon 9500 Pro] (Secondary) 0 +d 10024e66 RV350 NF [Radeon 9600] (Secondary) 0 New PCI ID provided by ATI developer relations (correction to above) +d 10024e67 Radeon R300 [FireGL X1] (Secondary) 0 +d 10024e68 Radeon R350 [Radeon 9800 Pro] (Secondary) 0 (added pro) +d 10024e69 Radeon R350 [Radeon 9800] (Secondary) 0 New PCI ID provided by ATI developer relations +d 10024e6a RV350 NJ [Radeon 9800 XT] (Secondary) 0 +d 10025041 Rage 128 PA/PRO 0 +d 10025042 Rage 128 PB/PRO AGP 2x 0 +d 10025043 Rage 128 PC/PRO AGP 4x 0 +d 10025044 Rage 128 PD/PRO TMDS 0 +s 1002504410020028 Rage 128 AIW 0 +s 1002504410020029 Rage 128 AIW 0 +d 10025045 Rage 128 PE/PRO AGP 2x TMDS 0 +d 10025046 Rage 128 PF/PRO AGP 4x TMDS 0 +s 1002504610020004 Rage Fury Pro 0 +s 1002504610020008 Rage Fury Pro/Xpert 2000 Pro 0 +s 1002504610020014 Rage Fury Pro 0 +s 1002504610020018 Rage Fury Pro/Xpert 2000 Pro 0 +s 1002504610020028 Rage 128 Pro AIW AGP 0 +s 100250461002002a Rage 128 Pro AIW AGP 0 +s 1002504610020048 Rage Fury Pro 0 +s 1002504610022000 Rage Fury MAXX AGP 4x (TMDS) (VGA device) 0 +s 1002504610022001 Rage Fury MAXX AGP 4x (TMDS) (Extra device?!) 0 +d 10025047 Rage 128 PG/PRO 0 +d 10025048 Rage 128 PH/PRO AGP 2x 0 +d 10025049 Rage 128 PI/PRO AGP 4x 0 +d 1002504a Rage 128 PJ/PRO TMDS 0 +d 1002504b Rage 128 PK/PRO AGP 2x TMDS 0 +d 1002504c Rage 128 PL/PRO AGP 4x TMDS 0 +d 1002504d Rage 128 PM/PRO 0 +d 1002504e Rage 128 PN/PRO AGP 2x 0 +d 1002504f Rage 128 PO/PRO AGP 4x 0 +d 10025050 Rage 128 PP/PRO TMDS [Xpert 128] 0 +s 1002505010020008 Xpert 128 0 +d 10025051 Rage 128 PQ/PRO AGP 2x TMDS 0 +d 10025052 Rage 128 PR/PRO AGP 4x TMDS 0 +d 10025053 Rage 128 PS/PRO 0 +d 10025054 Rage 128 PT/PRO AGP 2x 0 +d 10025055 Rage 128 PU/PRO AGP 4x 0 +d 10025056 Rage 128 PV/PRO TMDS 0 +d 10025057 Rage 128 PW/PRO AGP 2x TMDS 0 +d 10025058 Rage 128 PX/PRO AGP 4x TMDS 0 +d 10025144 Radeon R100 QD [Radeon 7200] 0 +s 1002514410020008 Radeon 7000/Radeon VE 0 +s 1002514410020009 Radeon 7000/Radeon 0 +s 100251441002000a Radeon 7000/Radeon 0 +s 100251441002001a Radeon 7000/Radeon 0 +s 1002514410020029 Radeon AIW 0 +s 1002514410020038 Radeon 7000/Radeon 0 +s 1002514410020039 Radeon 7000/Radeon 0 +s 100251441002008a Radeon 7000/Radeon 0 +s 10025144100200ba Radeon 7000/Radeon 0 +s 1002514410020139 Radeon 7000/Radeon 0 +s 100251441002028a Radeon 7000/Radeon 0 +s 10025144100202aa Radeon AIW 0 +s 100251441002053a Radeon 7000/Radeon 0 +d 10025145 Radeon R100 QE 0 +d 10025146 Radeon R100 QF 0 +d 10025147 Radeon R100 QG 0 +d 10025148 Radeon R200 QH [Radeon 8500] 0 +s 100251481002010a FireGL 8800 64Mb 0 +s 1002514810020152 FireGL 8800 128Mb 0 +s 1002514810020162 FireGL 8700 32Mb 0 +s 1002514810020172 FireGL 8700 64Mb 0 +d 10025149 Radeon R200 QI 0 +d 1002514a Radeon R200 QJ 0 +d 1002514b Radeon R200 QK 0 +d 1002514c Radeon R200 QL [Radeon 8500 LE] 0 +s 1002514c1002003a Radeon R200 QL [Radeon 8500 LE] 0 +s 1002514c1002013a Radeon 8500 0 +s 1002514c148c2026 R200 QL [Radeon 8500 Evil Master II Multi Display Edition] 0 +s 1002514c16810010 Radeon 8500 [3D Prophet 8500 128Mb] 0 +s 1002514c174b7149 Radeon R200 QL [Sapphire Radeon 8500 LE] 0 +d 1002514d Radeon R200 QM [Radeon 9100] 0 +d 1002514e Radeon R200 QN [Radeon 8500LE] 0 +d 1002514f Radeon R200 QO [Radeon 8500LE] 0 +d 10025154 R200 QT [Radeon 8500] 0 +d 10025155 R200 QU [Radeon 9100] 0 +d 10025157 Radeon RV200 QW [Radeon 7500] 0 +s 100251571002013a Radeon 7500 0 +s 100251571002103a Dell Optiplex GX260 0 +s 1002515714584000 RV200 QW [RADEON 7500 PRO MAYA AR] 0 +s 10025157148c2024 RV200 QW [Radeon 7500LE Dual Display] 0 +s 10025157148c2025 RV200 QW [Radeon 7500 Evil Master Multi Display Edition] 0 +s 10025157148c2036 RV200 QW [Radeon 7500 PCI Dual Display] 0 +s 10025157174b7146 RV200 QW [Radeon 7500 LE] 0 +s 10025157174b7147 RV200 QW [Sapphire Radeon 7500LE] 0 +s 10025157174b7161 Radeon RV200 QW [Radeon 7500 LE] 0 +s 1002515717af0202 RV200 QW [Excalibur Radeon 7500LE] 0 +d 10025158 Radeon RV200 QX [Radeon 7500] 0 +d 10025159 Radeon RV100 QY [Radeon 7000/VE] 0 +s 100251591002000a Radeon 7000/Radeon VE 0 +s 100251591002000b Radeon 7000 0 +s 1002515910020038 Radeon 7000/Radeon VE 0 +s 100251591002003a Radeon 7000/Radeon VE 0 +s 10025159100200ba Radeon 7000/Radeon VE 0 +s 100251591002013a Radeon 7000/Radeon VE 0 +s 1002515914584002 RV100 QY [RADEON 7000 PRO MAYA AV Series] 0 +s 10025159148c2003 RV100 QY [Radeon 7000 Multi-Display Edition] 0 +s 10025159148c2023 RV100 QY [Radeon 7000 Evil Master Multi-Display] 0 +s 10025159174b7112 RV100 QY [Sapphire Radeon VE 7000] 0 +s 10025159174b7c28 Sapphire Radeon VE 7000 DDR 0 +s 1002515917870202 RV100 QY [Excalibur Radeon 7000] 0 +d 1002515a Radeon RV100 QZ [Radeon 7000/VE] 0 +d 10025168 Radeon R200 Qh 0 +d 10025169 Radeon R200 Qi 0 +d 1002516a Radeon R200 Qj 0 +d 1002516b Radeon R200 Qk 0 +d 1002516c Radeon R200 Ql 0 This one is not in ATI documentation, but is in XFree86 source code +d 10025245 Rage 128 RE/SG 0 +s 1002524510020008 Xpert 128 0 +s 1002524510020028 Rage 128 AIW 0 +s 1002524510020029 Rage 128 AIW 0 +s 1002524510020068 Rage 128 AIW 0 +d 10025246 Rage 128 RF/SG AGP 0 +s 1002524610020004 Magnum/Xpert 128/Xpert 99 0 +s 1002524610020008 Magnum/Xpert128/X99/Xpert2000 0 +s 1002524610020028 Rage 128 AIW AGP 0 +s 1002524610020044 Rage Fury/Xpert 128/Xpert 2000 0 +s 1002524610020068 Rage 128 AIW AGP 0 +s 1002524610020448 Rage Fury 0 +d 10025247 Rage 128 RG 0 +d 1002524b Rage 128 RK/VR 0 +d 1002524c Rage 128 RL/VR AGP 0 +s 1002524c10020008 Xpert 99/Xpert 2000 0 +s 1002524c10020088 Xpert 99 0 +d 10025345 Rage 128 SE/4x 0 +d 10025346 Rage 128 SF/4x AGP 2x 0 +s 1002534610020048 RAGE 128 16MB VGA TVOUT AMC PAL 0 +d 10025347 Rage 128 SG/4x AGP 4x 0 +d 10025348 Rage 128 SH 0 +d 1002534b Rage 128 SK/4x 0 +d 1002534c Rage 128 SL/4x AGP 2x 0 +d 1002534d Rage 128 SM/4x AGP 4x 0 +s 1002534d10020008 Xpert 99/Xpert 2000 0 +s 1002534d10020018 Xpert 2000 0 +d 1002534e Rage 128 4x 0 +d 10025354 Mach 64 VT 0 +s 1002535410025654 Mach 64 reference 0 +d 10025446 Rage 128 Pro Ultra TF 0 +s 1002544610020004 Rage Fury Pro 0 +s 1002544610020008 Rage Fury Pro/Xpert 2000 Pro 0 +s 1002544610020018 Rage Fury Pro/Xpert 2000 Pro 0 +s 1002544610020028 Rage 128 AIW Pro AGP 0 +s 1002544610020029 Rage 128 AIW 0 +s 100254461002002a Rage 128 AIW Pro AGP 0 +s 100254461002002b Rage 128 AIW 0 +s 1002544610020048 Xpert 2000 Pro 0 +d 1002544c Rage 128 Pro Ultra TL 0 +d 10025452 Rage 128 Pro Ultra TR 0 +s 100254521002001c Rage 128 Pro 4XL 0 +s 10025452103c1279 Rage 128 Pro 4XL 0 +d 10025453 Rage 128 Pro Ultra TS 0 +d 10025454 Rage 128 Pro Ultra TT 0 +d 10025455 Rage 128 Pro Ultra TU 0 +d 10025460 M22 [Radeon Mobility M300] 0 +d 10025464 M22 [FireGL GL] 0 +d 10025548 R423 UH [Radeon X800 (PCIE)] 0 +d 10025549 R423 UI [Radeon X800PRO (PCIE)] 0 +d 1002554a R423 UJ [Radeon X800LE (PCIE)] 0 +d 1002554b R423 UK [Radeon X800SE (PCIE)] 0 +d 10025551 R423 UQ [FireGL V7200 (PCIE)] 0 +d 10025552 R423 UR [FireGL V5100 (PCIE)] 0 +d 10025554 R423 UT [FireGL V7100 (PCIE)] 0 +d 1002556b Radeon R423 UK (PCIE) [X800 SE] (Secondary) 0 +d 10025654 264VT [Mach64 VT] 0 +s 1002565410025654 Mach64VT Reference 0 +d 10025655 264VT3 [Mach64 VT3] 0 +d 10025656 264VT4 [Mach64 VT4] 0 +d 10025830 RS300 Host Bridge 0 +d 10025831 RS300 Host Bridge 0 +d 10025832 RS300 Host Bridge 0 +d 10025833 Radeon 9100 IGP Host Bridge 0 +d 10025834 Radeon 9100 IGP 0 +d 10025835 RS300M AGP [Radeon Mobility 9100IGP] 0 +d 10025838 Radeon 9100 IGP AGP Bridge 0 +d 10025941 RV280 [Radeon 9200] (Secondary) 0 +s 10025941174b7c12 Sapphire Radeon 9200 0 +s 1002594117af200d Excalibur Radeon 9200 0 http://www.hightech.com.hk/html/9200.htm +s 1002594118bc0050 GeXcube GC-R9200-C3 (Secondary) 0 +d 10025944 RV280 [Radeon 9200 SE (PCI)] 0 +d 10025960 RV280 [Radeon 9200 PRO] 0 +d 10025961 RV280 [Radeon 9200] 0 +s 1002596110022f72 All-in-Wonder 9200 Series 0 +s 1002596112ab5961 YUAN SMARTVGA Radeon 9200 0 +s 1002596114584018 Gigabyte Radeon 9200 0 +s 10025961174b7c13 Sapphire Radeon 9200 0 +s 1002596117af200c Excalibur Radeon 9200 0 http://www.hightech.com.hk/html/9200.htm +s 1002596118bc0050 Radeon 9200 Game Buster 0 +s 1002596118bc0051 GeXcube GC-R9200-C3 0 +s 1002596118bc0053 Radeon 9200 Game Buster VIVO 0 +d 10025962 RV280 [Radeon 9200] 0 +d 10025964 RV280 [Radeon 9200 SE] 0 +s 100259641043c006 ASUS Radeon 9200 SE / TD / 128M 0 +s 1002596414584018 Radeon 9200 SE 0 +s 10025964148c2073 CN-AG92E 0 +s 10025964174b7c13 Sapphire Radeon 9200 SE 0 +s 1002596417875964 Excalibur 9200SE VIVO 128M 0 +s 1002596417af2012 Radeon 9200 SE Excalibur 0 +s 1002596418bc0170 Sapphire Radeon 9200 SE 128MB Game Buster 0 +s 1002596418bc0173 GC-R9200L(SE)-C3H [Radeon 9200 Game Buster] 0 128MB DDR, DVI/VGA/TV out +d 10025b60 RV370 5B60 [Radeon X300 (PCIE)] 0 +s 10025b601043002a EAX300SE 0 +d 10025b62 RV370 5B62 [Radeon X600 (PCIE)] 0 +d 10025b64 RV370 5B64 [FireGL V3100 (PCIE)] 0 +d 10025b65 RV370 5B65 [FireGL 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1022200012592701 AT-2700FX 100Mb Ethernet 0 +s 102220004c531000 CC7/CR7/CP7/VC7/VP7/VR7 mainboard 0 +s 102220004c531010 CP5/CR6 mainboard 0 +s 102220004c531020 VR6 mainboard 0 +s 102220004c531030 PC5 mainboard 0 +s 102220004c531040 CL7 mainboard 0 +s 102220004c531060 PC7 mainboard 0 +d 10222001 79c978 [HomePNA] 0 +s 1022200110920a78 Multimedia Home Network Adapter 0 +s 1022200116680299 ActionLink Home Network Adapter 0 +d 10222003 Am 1771 MBW [Alchemy] 0 +d 10222020 53c974 [PCscsi] 0 +d 10222040 79c974 0 +d 10223000 ELanSC520 Microcontroller 0 +d 10227006 AMD-751 [Irongate] System Controller 0 +d 10227007 AMD-751 [Irongate] AGP Bridge 0 +d 1022700a AMD-IGR4 AGP Host to PCI Bridge 0 +d 1022700b AMD-IGR4 PCI to PCI Bridge 0 +d 1022700c AMD-760 MP [IGD4-2P] System Controller 0 +d 1022700d AMD-760 MP [IGD4-2P] AGP Bridge 0 +d 1022700e AMD-760 [IGD4-1P] System Controller 0 +d 1022700f AMD-760 [IGD4-1P] AGP Bridge 0 +d 10227400 AMD-755 [Cobra] ISA 0 +d 10227401 AMD-755 [Cobra] IDE 0 +d 10227403 AMD-755 [Cobra] ACPI 0 +d 10227404 AMD-755 [Cobra] USB 0 +d 10227408 AMD-756 [Viper] ISA 0 +d 10227409 AMD-756 [Viper] IDE 0 +d 1022740b AMD-756 [Viper] ACPI 0 +d 1022740c AMD-756 [Viper] USB 0 +d 10227410 AMD-766 [ViperPlus] ISA 0 +d 10227411 AMD-766 [ViperPlus] IDE 0 +d 10227413 AMD-766 [ViperPlus] ACPI 0 +d 10227414 AMD-766 [ViperPlus] USB 0 +d 10227440 AMD-768 [Opus] ISA 0 +s 1022744010438044 A7M-D Mainboard 0 +d 10227441 AMD-768 [Opus] IDE 0 +d 10227443 AMD-768 [Opus] ACPI 0 +s 1022744310438044 A7M-D Mainboard 0 +d 10227445 AMD-768 [Opus] Audio 0 +d 10227446 AMD-768 [Opus] MC97 Modem (Smart Link HAMR5600 compatible) 0 +d 10227448 AMD-768 [Opus] PCI 0 +d 10227449 AMD-768 [Opus] USB 0 +d 10227450 AMD-8131 PCI-X Bridge 0 +d 10227451 AMD-8131 PCI-X APIC 0 +d 10227454 AMD-8151 System Controller 0 +d 10227455 AMD-8151 AGP Bridge 0 +d 10227460 AMD-8111 PCI 0 +s 10227460161f3017 HDAMB 0 +d 10227461 AMD-8111 USB 0 +d 10227462 AMD-8111 Ethernet 0 +d 10227464 AMD-8111 USB 0 +s 10227464161f3017 HDAMB 0 +d 10227468 AMD-8111 LPC 0 +s 10227468161f3017 HDAMB 0 +d 10227469 AMD-8111 IDE 0 +s 10227469161f3017 HDAMB 0 +d 1022746a AMD-8111 SMBus 2.0 0 +d 1022746b AMD-8111 ACPI 0 +s 1022746b161f3017 HDAMB 0 +d 1022746d AMD-8111 AC97 Audio 0 +s 1022746d161f3017 HDAMB 0 +d 1022746e AMD-8111 MC97 Modem 0 +d 1022756b AMD-8111 ACPI 0 +v 1023 Trident Microsystems 0 +d 10230194 82C194 0 +d 10232000 4DWave DX 0 +d 10232001 4DWave NX 0 +s 10232001122d1400 Trident PCI288-Q3DII (NX) 0 +d 10232100 CyberBlade XP4m32 0 +d 10238400 CyberBlade/i7 0 +s 1023840010238400 CyberBlade i7 AGP 0 +d 10238420 CyberBlade/i7d 0 +s 102384200e11b15a CyberBlade i7 AGP 0 +d 10238500 CyberBlade/i1 0 +d 10238520 CyberBlade i1 0 +s 102385200e11b16e CyberBlade i1 AGP 0 +s 1023852010238520 CyberBlade i1 AGP 0 +d 10238620 CyberBlade/i1 0 +s 1023862010140502 ThinkPad R30/T30 0 +d 10238820 CyberBlade XPAi1 0 +d 10239320 TGUI 9320 0 +d 10239350 GUI Accelerator 0 +d 10239360 Flat panel GUI Accelerator 0 +d 10239382 Cyber 9382 [Reference design] 0 +d 10239383 Cyber 9383 [Reference design] 0 +d 10239385 Cyber 9385 [Reference design] 0 +d 10239386 Cyber 9386 0 +d 10239388 Cyber 9388 0 +d 10239397 Cyber 9397 0 +d 1023939a Cyber 9397DVD 0 +d 10239420 TGUI 9420 0 +d 10239430 TGUI 9430 0 +d 10239440 TGUI 9440 0 +d 10239460 TGUI 9460 0 +d 10239470 TGUI 9470 0 +d 10239520 Cyber 9520 0 +d 10239525 Cyber 9525 0 +s 1023952510cf1094 Lifebook C6155 0 +d 10239540 Cyber 9540 0 +d 10239660 TGUI 9660/938x/968x 0 +d 10239680 TGUI 9680 0 +d 10239682 TGUI 9682 0 +d 10239683 TGUI 9683 0 +d 10239685 ProVIDIA 9685 0 +d 10239750 3DImage 9750 0 +s 1023975010149750 3DImage 9750 0 +s 1023975010239750 3DImage 9750 0 +d 10239753 TGUI 9753 0 +d 10239754 TGUI 9754 0 +d 10239759 TGUI 975 0 +d 10239783 TGUI 9783 0 +d 10239785 TGUI 9785 0 +d 10239850 3DImage 9850 0 +d 10239880 Blade 3D PCI/AGP 0 +s 1023988010239880 Blade 3D 0 +d 10239910 CyberBlade/XP 0 +d 10239930 CyberBlade/XPm 0 +v 1024 Zenith Data Systems 0 +v 1025 Acer Incorporated [ALI] 0 +d 10251435 M1435 0 +d 10251445 M1445 0 +d 10251449 M1449 0 +d 10251451 M1451 0 +d 10251461 M1461 0 +d 10251489 M1489 0 +d 10251511 M1511 0 +d 10251512 ALI M1512 Aladdin 0 +d 10251513 M1513 0 +d 10251521 ALI M1521 Aladdin III CPU Bridge 0 +s 1025152110b91521 ALI M1521 Aladdin III CPU Bridge 0 +d 10251523 ALI M1523 ISA Bridge 0 +s 1025152310b91523 ALI M1523 ISA Bridge 0 +d 10251531 M1531 Northbridge [Aladdin IV/IV+] 0 +d 10251533 M1533 PCI-to-ISA Bridge 0 +s 1025153310b91533 ALI M1533 Aladdin IV/V ISA South Bridge 0 +d 10251535 M1535 PCI Bridge + Super I/O + FIR 0 +d 10251541 M1541 Northbridge [Aladdin V] 0 +s 1025154110b91541 ALI M1541 Aladdin V/V+ AGP+PCI North Bridge 0 +d 10251542 M1542 Northbridge [Aladdin V] 0 +d 10251543 M1543 PCI-to-ISA Bridge + Super I/O + FIR 0 +d 10251561 M1561 Northbridge [Aladdin 7] 0 +d 10251621 M1621 Northbridge [Aladdin-Pro II] 0 +d 10251631 M1631 Northbridge+3D Graphics [Aladdin TNT2] 0 +d 10251641 M1641 Northbridge [Aladdin-Pro IV] 0 +d 10251647 M1647 [MaGiK1] PCI North Bridge 0 +d 10251671 M1671 Northbridge [ALADDiN-P4] 0 +d 10251672 Northbridge [CyberALADDiN-P4] 0 +d 10253141 M3141 0 +d 10253143 M3143 0 +d 10253145 M3145 0 +d 10253147 M3147 0 +d 10253149 M3149 0 +d 10253151 M3151 0 +d 10253307 M3307 MPEG-I Video Controller 0 +d 10253309 M3309 MPEG-II Video w/ Software Audio Decoder 0 +d 10253321 M3321 MPEG-II Audio/Video Decoder 0 +d 10255212 M4803 0 +d 10255215 ALI PCI EIDE Controller 0 +d 10255217 M5217H 0 +d 10255219 M5219 0 +d 10255225 M5225 0 +d 10255229 M5229 0 +d 10255235 M5235 0 +d 10255237 M5237 PCI USB Host Controller 0 +d 10255240 EIDE Controller 0 +d 10255241 PCMCIA Bridge 0 +d 10255242 General Purpose Controller 0 +d 10255243 PCI to PCI Bridge Controller 0 +d 10255244 Floppy Disk Controller 0 +d 10255247 M1541 PCI to PCI Bridge 0 +d 10255251 M5251 P1394 Controller 0 +d 10255427 PCI to AGP Bridge 0 +d 10255451 M5451 PCI AC-Link Controller Audio Device 0 +d 10255453 M5453 PCI AC-Link Controller Modem Device 0 +d 10257101 M7101 PCI PMU Power Management Controller 0 +s 1025710110b97101 M7101 PCI PMU Power Management Controller 0 +v 1028 Dell 0 +d 10280001 PowerEdge Expandable RAID Controller 2/Si 0 +s 1028000110280001 PowerEdge 2400 0 +d 10280002 PowerEdge Expandable RAID Controller 3/Di 0 +s 1028000210280002 PowerEdge 4400 0 +d 10280003 PowerEdge Expandable RAID Controller 3/Si 0 +s 1028000310280003 PowerEdge 2450 0 +d 10280006 PowerEdge Expandable RAID Controller 3/Di 0 +d 10280007 Remote Access Card III 0 +d 10280008 Remote Access Card III 0 +d 10280009 Remote Access Card III: BMC/SMIC device not present 0 +d 1028000a PowerEdge Expandable RAID Controller 3/Di 0 +d 1028000c Embedded Remote Access or ERA/O 0 +d 1028000d Embedded Remote Access: BMC/SMIC device 0 +d 1028000e PowerEdge Expandable RAID controller 4/Di 0 +d 1028000f PowerEdge Expandable RAID controller 4/Di 0 +d 10280010 Remote Access Card 4 0 +d 10280011 Remote Access Card 4 Daughter Card 0 +d 10280012 Remote Access Card 4 Daughter Card Virtual UART 0 +d 10280013 PowerEdge Expandable RAID controller 4 0 +s 102800131028016c PowerEdge Expandable RAID Controller 4e/Si 0 +s 102800131028016d PowerEdge Expandable RAID Controller 4e/Di 0 +s 102800131028016e PowerEdge Expandable RAID Controller 4e/Di 0 +s 102800131028016f PowerEdge Expandable RAID Controller 4e/Di 0 +s 1028001310280170 PowerEdge Expandable RAID Controller 4e/Di 0 +d 10280014 Remote Access Card 4 Daughter Card SMIC interface 0 +v 1029 Siemens Nixdorf IS 0 +v 102a LSI Logic 0 +d 102a0000 HYDRA 0 +d 102a0010 ASPEN 0 +d 102a001f AHA-2940U2/U2W /7890/7891 SCSI Controllers 0 +s 102a001f9005000f 2940U2W SCSI Controller 0 +s 102a001f90050106 2940U2W SCSI Controller 0 +s 102a001f9005a180 2940U2W SCSI Controller 0 +d 102a00c5 AIC-7899 U160/m SCSI Controller 0 +s 102a00c5102800c5 PowerEdge 2550/2650/4600 0 +d 102a00cf AIC-7899P U160/m 0 +s 102a00cf10280106 PowerEdge 4600 0 +s 102a00cf10280121 PowerEdge 2650 0 +v 102b Matrox Graphics, Inc. 0 +d 102b0010 MGA-I [Impression?] 0 DJ: I've a suspicion that 0010 is a duplicate of 0d10. +d 102b0100 MGA 1064SG [Mystique] 0 +d 102b0518 MGA-II [Athena] 0 +d 102b0519 MGA 2064W [Millennium] 0 +d 102b051a MGA 1064SG [Mystique] 0 +s 102b051a102b0100 MGA-1064SG Mystique 0 +s 102b051a102b1100 MGA-1084SG Mystique 0 +s 102b051a102b1200 MGA-1084SG Mystique 0 +s 102b051a1100102b MGA-1084SG Mystique 0 +s 102b051a110a0018 Scenic Pro C5 (D1025) 0 +d 102b051b MGA 2164W [Millennium II] 0 +s 102b051b102b051b MGA-2164W Millennium II 0 +s 102b051b102b1100 MGA-2164W Millennium II 0 +s 102b051b102b1200 MGA-2164W Millennium II 0 +d 102b051e MGA 1064SG [Mystique] AGP 0 +d 102b051f MGA 2164W [Millennium II] AGP 0 +d 102b0520 MGA G200 0 +s 102b0520102bdbc2 G200 Multi-Monitor 0 +s 102b0520102bdbc8 G200 Multi-Monitor 0 +s 102b0520102bdbe2 G200 Multi-Monitor 0 +s 102b0520102bdbe8 G200 Multi-Monitor 0 +s 102b0520102bff03 Millennium G200 SD 0 +s 102b0520102bff04 Marvel G200 0 +d 102b0521 MGA G200 AGP 0 +s 102b05211014ff03 Millennium G200 AGP 0 +s 102b0521102b48e9 Mystique G200 AGP 0 +s 102b0521102b48f8 Millennium G200 SD AGP 0 +s 102b0521102b4a60 Millennium G200 LE AGP 0 +s 102b0521102b4a64 Millennium G200 AGP 0 +s 102b0521102bc93c Millennium G200 AGP 0 +s 102b0521102bc9b0 Millennium G200 AGP 0 +s 102b0521102bc9bc Millennium G200 AGP 0 +s 102b0521102bca60 Millennium G250 LE AGP 0 +s 102b0521102bca6c Millennium G250 AGP 0 +s 102b0521102bdbbc Millennium G200 AGP 0 +s 102b0521102bdbc2 Millennium G200 MMS (Dual G200) 0 +s 102b0521102bdbc3 G200 Multi-Monitor 0 +s 102b0521102bdbc8 Millennium G200 MMS (Dual G200) 0 +s 102b0521102bdbd2 G200 Multi-Monitor 0 +s 102b0521102bdbd3 G200 Multi-Monitor 0 +s 102b0521102bdbd4 G200 Multi-Monitor 0 +s 102b0521102bdbd5 G200 Multi-Monitor 0 +s 102b0521102bdbd8 G200 Multi-Monitor 0 +s 102b0521102bdbd9 G200 Multi-Monitor 0 +s 102b0521102bdbe2 Millennium G200 MMS (Quad G200) 0 +s 102b0521102bdbe3 G200 Multi-Monitor 0 +s 102b0521102bdbe8 Millennium G200 MMS (Quad G200) 0 +s 102b0521102bdbf2 G200 Multi-Monitor 0 +s 102b0521102bdbf3 G200 Multi-Monitor 0 +s 102b0521102bdbf4 G200 Multi-Monitor 0 +s 102b0521102bdbf5 G200 Multi-Monitor 0 +s 102b0521102bdbf8 G200 Multi-Monitor 0 +s 102b0521102bdbf9 G200 Multi-Monitor 0 +s 102b0521102bf806 Mystique G200 Video AGP 0 +s 102b0521102bff00 MGA-G200 AGP 0 +s 102b0521102bff02 Mystique G200 AGP 0 +s 102b0521102bff03 Millennium G200 AGP 0 +s 102b0521102bff04 Marvel G200 AGP 0 +s 102b0521110a0032 MGA-G200 AGP 0 +d 102b0525 MGA G400 AGP 0 +s 102b05250e11b16f MGA-G400 AGP 0 +s 102b0525102b0328 Millennium G400 16Mb SDRAM 0 +s 102b0525102b0338 Millennium G400 16Mb SDRAM 0 +s 102b0525102b0378 Millennium G400 32Mb SDRAM 0 +s 102b0525102b0541 Millennium G450 Dual Head 0 +s 102b0525102b0542 Millennium G450 Dual Head LX 0 +s 102b0525102b0543 Millennium G450 Single Head LX 0 +s 102b0525102b0641 Millennium G450 32Mb SDRAM Dual Head 0 +s 102b0525102b0642 Millennium G450 32Mb SDRAM Dual Head LX 0 +s 102b0525102b0643 Millennium G450 32Mb SDRAM Single Head LX 0 +s 102b0525102b07c0 Millennium G450 Dual Head LE 0 +s 102b0525102b07c1 Millennium G450 SDR Dual Head LE 0 +s 102b0525102b0d41 Millennium G450 Dual Head PCI 0 +s 102b0525102b0d42 Millennium G450 Dual Head LX PCI 0 +s 102b0525102b0d43 Millennium G450 32Mb Dual Head PCI 0 +s 102b0525102b0e00 Marvel G450 eTV 0 +s 102b0525102b0e01 Marvel G450 eTV 0 +s 102b0525102b0e02 Marvel G450 eTV 0 +s 102b0525102b0e03 Marvel G450 eTV 0 +s 102b0525102b0f80 Millennium G450 Low Profile 0 +s 102b0525102b0f81 Millennium G450 Low Profile 0 +s 102b0525102b0f82 Millennium G450 Low Profile DVI 0 +s 102b0525102b0f83 Millennium G450 Low Profile DVI 0 +s 102b0525102b19d8 Millennium G400 16Mb SGRAM 0 +s 102b0525102b19f8 Millennium G400 32Mb SGRAM 0 +s 102b0525102b2159 Millennium G400 Dual Head 16Mb 0 +s 102b0525102b2179 Millennium G400 MAX/Dual Head 32Mb 0 +s 102b0525102b217d Millennium G400 Dual Head Max 0 +s 102b0525102b23c0 Millennium G450 0 +s 102b0525102b23c1 Millennium G450 0 +s 102b0525102b23c2 Millennium G450 DVI 0 +s 102b0525102b23c3 Millennium G450 DVI 0 +s 102b0525102b2f58 Millennium G400 0 +s 102b0525102b2f78 Millennium G400 0 +s 102b0525102b3693 Marvel G400 AGP 0 +s 102b0525102b5dd0 4Sight II 0 +s 102b0525102b5f50 4Sight II 0 +s 102b0525102b5f51 4Sight II 0 +s 102b0525102b5f52 4Sight II 0 +s 102b0525102b9010 Millennium G400 Dual Head 0 +s 102b052514580400 GA-G400 0 +s 102b052517050001 Millennium G450 32MB SGRAM 0 +s 102b052517050002 Millennium G450 16MB SGRAM 0 +s 102b052517050003 Millennium G450 32MB 0 +s 102b052517050004 Millennium G450 16MB 0 +d 102b0527 MGA Parhelia AGP 0 +s 102b0527102b0840 Parhelia 128Mb 0 +d 102b0d10 MGA Ultima/Impression 0 +d 102b1000 MGA G100 [Productiva] 0 +s 102b1000102bff01 Productiva G100 0 +s 102b1000102bff05 Productiva G100 Multi-Monitor 0 +d 102b1001 MGA G100 [Productiva] AGP 0 +s 102b1001102b1001 MGA-G100 AGP 0 +s 102b1001102bff00 MGA-G100 AGP 0 +s 102b1001102bff01 MGA-G100 Productiva AGP 0 +s 102b1001102bff03 Millennium G100 AGP 0 +s 102b1001102bff04 MGA-G100 AGP 0 +s 102b1001102bff05 MGA-G100 Productiva AGP Multi-Monitor 0 +s 102b1001110a001e MGA-G100 AGP 0 +d 102b2007 MGA Mistral 0 +d 102b2527 MGA G550 AGP 0 +s 102b2527102b0f83 Millennium G550 0 +s 102b2527102b0f84 Millennium G550 Dual Head DDR 32Mb 0 +s 102b2527102b1e41 Millennium G550 0 +d 102b2537 MGA G650 AGP 0 +d 102b4536 VIA Framegrabber 0 +d 102b6573 Shark 10/100 Multiport SwitchNIC 0 +v 102c Chips and Technologies 0 +d 102c00b8 F64310 0 +d 102c00c0 F69000 HiQVideo 0 +s 102c00c0102c00c0 F69000 HiQVideo 0 +s 102c00c04c531000 CC7/CR7/CP7/VC7/VP7/VR7 mainboard 0 +s 102c00c04c531010 CP5/CR6 mainboard 0 +s 102c00c04c531020 VR6 mainboard 0 +s 102c00c04c531030 PC5 mainboard 0 +s 102c00c04c531050 CT7 mainboard 0 +s 102c00c04c531051 CE7 mainboard 0 +d 102c00d0 F65545 0 +d 102c00d8 F65545 0 +d 102c00dc F65548 0 +d 102c00e0 F65550 0 +d 102c00e4 F65554 0 +d 102c00e5 F65555 HiQVPro 0 +s 102c00e50e11b049 Armada 1700 Laptop Display Controller 0 +d 102c00f0 F68554 0 +d 102c00f4 F68554 HiQVision 0 +d 102c00f5 F68555 0 +d 102c0c30 F69030 0 +s 102c0c304c531000 CC7/CR7/CP7/VC7/VP7/VR7 mainboard 0 +s 102c0c304c531050 CT7 mainboard 0 +s 102c0c304c531051 CE7 mainboard 0 +s 102c0c304c531080 CT8 mainboard 0 C5C project cancelled +v 102d Wyse Technology Inc. 0 +d 102d50dc 3328 Audio 0 +v 102e Olivetti Advanced Technology 0 +v 102f Toshiba America 0 +d 102f0009 r4x00 0 +d 102f000a TX3927 MIPS RISC PCI Controller 0 +d 102f0020 ATM Meteor 155 0 +s 102f0020102f00f8 ATM Meteor 155 0 +d 102f0030 TC35815CF PCI 10/100 Mbit Ethernet Controller 0 +d 102f0031 TC35815CF PCI 10/100 Mbit Ethernet Controller with WOL 0 +d 102f0105 TC86C001 [goku-s] IDE 0 +d 102f0106 TC86C001 [goku-s] USB 1.1 Host 0 +d 102f0107 TC86C001 [goku-s] USB Device Controller 0 +d 102f0108 TC86C001 [goku-s] I2C/SIO/GPIO Controller 0 +d 102f0180 TX4927/38 MIPS RISC PCI Controller 0 +d 102f0181 TX4925 MIPS RISC PCI Controller 0 +d 102f0182 TX4937 MIPS RISC PCI Controller 0 +v 1030 TMC Research 0 +v 1031 Miro Computer Products AG 0 +d 10315601 DC20 ASIC 0 +d 10315607 Video I/O & motion JPEG compressor 0 +d 10315631 Media 3D 0 +d 10316057 MiroVideo DC10/DC30+ 0 +v 1032 Compaq 0 +v 1033 NEC Corporation 0 +d 10330000 Vr4181A USB Host or Function Control Unit 0 +d 10330001 PCI to 486-like bus Bridge 0 +d 10330002 PCI to VL98 Bridge 0 +d 10330003 ATM Controller 0 +d 10330004 R4000 PCI Bridge 0 +d 10330005 PCI to 486-like bus Bridge 0 +d 10330006 PC-9800 Graphic Accelerator 0 +d 10330007 PCI to UX-Bus Bridge 0 +d 10330008 PC-9800 Graphic Accelerator 0 +d 10330009 PCI to PC9800 Core-Graph Bridge 0 +d 10330016 PCI to VL Bridge 0 +d 1033001a [Nile II] 0 +d 10330021 Vrc4373 [Nile I] 0 +d 10330029 PowerVR PCX1 0 +d 1033002a PowerVR 3D 0 +d 1033002c Star Alpha 2 0 +d 1033002d PCI to C-bus Bridge 0 +d 10330035 USB 0 +s 1033003511790001 USB 0 +s 1033003512ee7000 Root Hub 0 +s 1033003517990001 Root Hub 0 +s 10330035807d0035 PCI-USB2 (OHCI subsystem) 0 +d 1033003b PCI to C-bus Bridge 0 +d 1033003e NAPCCARD Cardbus Controller 0 +d 10330046 PowerVR PCX2 [midas] 0 +d 1033005a Vrc5074 [Nile 4] 0 +d 10330063 Firewarden 0 +d 10330067 PowerVR Neon 250 Chipset 0 +s 1033006710100020 PowerVR Neon 250 AGP 32Mb 0 +s 1033006710100080 PowerVR Neon 250 AGP 16Mb 0 +s 1033006710100088 PowerVR Neon 250 16Mb 0 +s 1033006710100090 PowerVR Neon 250 AGP 16Mb 0 +s 1033006710100098 PowerVR Neon 250 16Mb 0 +s 10330067101000a0 PowerVR Neon 250 AGP 32Mb 0 +s 10330067101000a8 PowerVR Neon 250 32Mb 0 +s 1033006710100120 PowerVR Neon 250 AGP 32Mb 0 +d 10330074 56k Voice Modem 0 +s 1033007410338014 RCV56ACF 56k Voice Modem 0 +d 1033009b Vrc5476 0 +d 103300a5 VRC4173 0 +d 103300a6 VRC5477 AC97 0 +d 103300cd IEEE 1394 [OrangeLink] Host Controller 0 +s 103300cd12ee8011 Root hub 0 +d 103300ce IEEE 1394 Host Controller 0 +d 103300df Vr4131 0 +d 103300e0 USB 2.0 0 +s 103300e00ee43383 Sitecom IEEE 1394 / USB2.0 Combo Card 0 +s 103300e012ee7001 Root hub 0 +s 103300e017990002 Root Hub 0 +s 103300e0807d1043 PCI-USB2 (EHCI subsystem) 0 +d 103300e7 IEEE 1394 Host Controller 0 +d 103300f2 uPD72874 IEEE1394 OHCI 1.1 3-port PHY-Link Ctrlr 0 +d 103300f3 uPD6113x Multimedia Decoder/Processor [EMMA2] 0 +d 1033010c VR7701 0 +v 1034 Framatome Connectors USA Inc. 0 +v 1035 Comp. & Comm. Research Lab 0 +v 1036 Future Domain Corp. 0 +d 10360000 TMC-18C30 [36C70] 0 +v 1037 Hitachi Micro Systems 0 +v 1038 AMP, Inc 0 +v 1039 Silicon Integrated Systems [SiS] 0 +d 10390001 Virtual PCI-to-PCI bridge (AGP) 0 +d 10390002 SG86C202 0 +d 10390006 85C501/2/3 0 +d 10390008 SiS85C503/5513 (LPC Bridge) 0 +d 10390009 ACPI 0 +d 10390016 SiS961/2 SMBus Controller 0 source: http://members.datafast.net.au/dft0802/downloads/pcidevs.txt +d 10390018 SiS85C503/5513 (LPC Bridge) 0 +d 10390180 RAID bus controller 180 SATA/PATA [SiS] 0 Controller for 2 PATA and 2 SATA channels +d 10390181 SiS SATA 0 +d 10390200 5597/5598/6326 VGA 0 +s 1039020010390000 SiS5597 SVGA (Shared RAM) 0 +d 10390204 82C204 0 +d 10390205 SG86C205 0 +d 10390300 300/305 PCI/AGP VGA Display Adapter 0 +s 10390300107d2720 Leadtek WinFast VR300 0 +d 10390310 315H PCI/AGP VGA Display Adapter 0 +d 10390315 315 PCI/AGP VGA Display Adapter 0 +d 10390325 315PRO PCI/AGP VGA Display Adapter 0 +d 10390330 330 [Xabre] PCI/AGP VGA Display Adapter 0 +d 10390406 85C501/2 0 +d 10390496 85C496 0 +d 10390530 530 Host 0 +d 10390540 540 Host 0 +d 10390550 550 Host 0 +d 10390597 5513C 0 +d 10390601 85C601 0 +d 10390620 620 Host 0 +d 10390630 630 Host 0 +d 10390633 633 Host 0 +d 10390635 635 Host 0 +d 10390645 SiS645 Host & Memory & AGP Controller 0 +d 10390646 SiS645DX Host & Memory & AGP Controller 0 +d 10390648 SiS 645xx 0 +d 10390650 650/M650 Host 0 +d 10390651 651 Host 0 +d 10390655 655 Host 0 +d 10390660 660 Host 0 +d 10390661 661FX/M661FX/M661MX Host 0 +d 10390730 730 Host 0 +d 10390733 733 Host 0 +d 10390735 735 Host 0 +d 10390740 740 Host 0 +d 10390741 741/741GX/M741 Host 0 +d 10390745 745 Host 0 +d 10390746 746 Host 0 +d 10390755 755 Host 0 +d 10390760 760/M760 Host 0 +d 10390900 SiS900 PCI Fast Ethernet 0 +s 1039090010190a14 K7S5A motherboard 0 +s 1039090010390900 SiS900 10/100 Ethernet Adapter 0 +s 1039090010438035 CUSI-FX motherboard 0 +d 10390961 SiS961 [MuTIOL Media IO] 0 +d 10390962 SiS962 [MuTIOL Media IO] 0 +d 10390963 SiS963 [MuTIOL Media IO] 0 +d 10390964 SiS964 [MuTIOL Media IO] 0 +d 10390965 SiS965 [MuTIOL Media IO] 0 +d 10393602 83C602 0 +d 10395107 5107 0 +d 10395300 SiS540 PCI Display Adapter 0 +d 10395315 550 PCI/AGP VGA Display Adapter 0 +d 10395401 486 PCI Chipset 0 +d 10395511 5511/5512 0 +d 10395513 5513 [IDE] 0 +s 1039551310190970 P6STP-FL motherboard 0 +s 1039551310395513 SiS5513 EIDE Controller (A,B step) 0 +s 1039551310438035 CUSI-FX motherboard 0 +d 10395517 5517 0 +d 10395571 5571 0 +d 10395581 5581 Pentium Chipset 0 +d 10395582 5582 0 +d 10395591 5591/5592 Host 0 +d 10395596 5596 Pentium Chipset 0 +d 10395597 5597 [SiS5582] 0 +d 10395600 5600 Host 0 +d 10396204 Video decoder & MPEG interface 0 +d 10396205 VGA Controller 0 +d 10396236 6236 3D-AGP 0 +d 10396300 630/730 PCI/AGP VGA Display Adapter 0 +s 1039630010190970 P6STP-FL motherboard 0 +s 1039630010438035 CUSI-FX motherboard 0 +d 10396306 530/620 PCI/AGP VGA Display Adapter 0 +s 1039630610396306 SiS530,620 GUI Accelerator+3D 0 +d 10396325 65x/M650/740 PCI/AGP VGA Display Adapter 0 +d 10396326 86C326 5598/6326 0 +s 1039632610396326 SiS6326 GUI Accelerator 0 +s 1039632610920a50 SpeedStar A50 0 +s 1039632610920a70 SpeedStar A70 0 +s 1039632610924910 SpeedStar A70 0 +s 1039632610924920 SpeedStar A70 0 +s 1039632615696326 SiS6326 GUI Accelerator 0 +d 10396330 661/741/760 PCI/AGP VGA Display Adapter 0 +s 1039633010396330 [M]661xX/[M]741[GX]/[M]760 PCI/AGP VGA Adapter 0 +d 10397001 USB 1.0 Controller 0 +s 1039700110190a14 K7S5A motherboard 0 +s 1039700110397000 Onboard USB Controller 0 +d 10397002 USB 2.0 Controller 0 +s 1039700215097002 Onboard USB Controller 0 +d 10397007 FireWire Controller 0 +d 10397012 Sound Controller 0 +d 10397013 AC'97 Modem Controller 0 There are may be different modem codecs here (Intel537 compatible and incompatible) +d 10397016 SiS7016 PCI Fast Ethernet Adapter 0 +s 1039701610397016 SiS7016 10/100 Ethernet Adapter 0 +d 10397018 SiS PCI Audio Accelerator 0 +s 10397018101401b6 SiS PCI Audio Accelerator 0 +s 10397018101401b7 SiS PCI Audio Accelerator 0 +s 1039701810197018 SiS PCI Audio Accelerator 0 +s 103970181025000e SiS PCI Audio Accelerator 0 +s 1039701810250018 SiS PCI Audio Accelerator 0 +s 1039701810397018 SiS PCI Audio Accelerator 0 +s 103970181043800b SiS PCI Audio Accelerator 0 +s 1039701810547018 SiS PCI Audio Accelerator 0 +s 10397018107d5330 SiS PCI Audio Accelerator 0 +s 10397018107d5350 SiS PCI Audio Accelerator 0 +s 1039701811703209 SiS PCI Audio Accelerator 0 +s 103970181462400a SiS PCI Audio Accelerator 0 +s 1039701814a42089 SiS PCI Audio Accelerator 0 +s 1039701814cd2194 SiS PCI Audio Accelerator 0 +s 1039701814ff1100 SiS PCI Audio Accelerator 0 +s 10397018152d8808 SiS PCI Audio Accelerator 0 +s 1039701815581103 SiS PCI Audio Accelerator 0 +s 1039701815582200 SiS PCI Audio Accelerator 0 +s 1039701815637018 SiS PCI Audio Accelerator 0 +s 1039701815c50111 SiS PCI Audio Accelerator 0 +s 10397018270fa171 SiS PCI Audio Accelerator 0 +s 10397018a0a00022 SiS PCI Audio Accelerator 0 +d 10397019 SiS7019 Audio Accelerator 0 +v 103a Seiko Epson Corporation 0 +v 103b Tatung Co. of America 0 +v 103c Hewlett-Packard Company 0 +d 103c1005 A4977A Visualize EG 0 +d 103c1006 Visualize FX6 0 +d 103c1008 Visualize FX4 0 +d 103c100a Visualize FX2 0 +d 103c1028 Tach TL Fibre Channel Host Adapter 0 +d 103c1029 Tach XL2 Fibre Channel Host Adapter 0 +s 103c1029107e000f Interphase 5560 Fibre Channel Adapter 0 +s 103c102990049210 1Gb/2Gb Family Fibre Channel Controller 0 +s 103c102990049211 1Gb/2Gb Family Fibre Channel Controller 0 +d 103c102a Tach TS Fibre Channel Host Adapter 0 +s 103c102a107e000e Interphase 5540/5541 Fibre Channel Adapter 0 +s 103c102a90049110 1Gb/2Gb Family Fibre Channel Controller 0 +s 103c102a90049111 1Gb/2Gb Family Fibre Channel Controller 0 +d 103c1030 J2585A DeskDirect 10/100VG NIC 0 +d 103c1031 J2585B HP 10/100VG PCI LAN Adapter 0 +s 103c1031103c1040 J2973A DeskDirect 10BaseT NIC 0 +s 103c1031103c1041 J2585B DeskDirect 10/100VG NIC 0 +s 103c1031103c1042 J2970A DeskDirect 10BaseT/2 NIC 0 +d 103c1040 J2973A DeskDirect 10BaseT NIC 0 +d 103c1041 J2585B DeskDirect 10/100 NIC 0 +d 103c1042 J2970A DeskDirect 10BaseT/2 NIC 0 +d 103c1048 Diva Serial [GSP] Multiport UART 0 +s 103c1048103c1049 Tosca Console 0 +s 103c1048103c104a Tosca Secondary 0 +s 103c1048103c104b Maestro SP2 0 +s 103c1048103c1223 Superdome Console 0 +s 103c1048103c1226 Keystone SP2 0 +s 103c1048103c1227 Powerbar SP2 0 +s 103c1048103c1282 Everest SP2 0 +d 103c1054 PCI Local Bus Adapter 0 +d 103c1064 79C970 PCnet Ethernet Controller 0 +d 103c108b Visualize FXe 0 +d 103c10c1 NetServer Smart IRQ Router 0 +d 103c10ed TopTools Remote Control 0 +d 103c1200 82557B 10/100 NIC 0 +d 103c1219 NetServer PCI Hot-Plug Controller 0 +d 103c121a NetServer SMIC Controller 0 +d 103c121b NetServer Legacy COM Port Decoder 0 +d 103c121c NetServer PCI COM Port Decoder 0 +d 103c1229 zx1 System Bus Adapter 0 +d 103c122a zx1 I/O Controller 0 +d 103c122e zx1 Local Bus Adapter 0 +d 103c127c sx1000 I/O Controller 0 +d 103c1290 Auxiliary Diva Serial Port 0 +d 103c2910 E2910A PCIBus Exerciser 0 +d 103c2925 E2925A 32 Bit, 33 MHzPCI Exerciser & Analyzer 0 +v 103e Solliday Engineering 0 +v 103f Synopsys/Logic Modeling Group 0 +v 1040 Accelgraphics Inc. 0 +v 1041 Computrend 0 +v 1042 Micron 0 +d 10421000 PC Tech RZ1000 0 +d 10421001 PC Tech RZ1001 0 +d 10423000 Samurai_0 0 +d 10423010 Samurai_1 0 +d 10423020 Samurai_IDE 0 +v 1043 ASUSTeK Computer Inc. 0 +d 10430675 ISDNLink P-IN100-ST-D 0 +d 10434015 v7100 SDRAM [GeForce2 MX] 0 +d 10434021 v7100 Combo Deluxe [GeForce2 MX + TV tuner] 0 +d 10434057 v8200 GeForce 3 0 +d 10438043 v8240 PAL 128M [P4T] Motherboard 0 +d 1043807b v9280/TD [Geforce4 TI4200 8X With TV-Out and DVI] 0 +d 104380bb v9180 Magic/T [GeForce4 MX440 AGP 8x 64MB TV-out] 0 +v 1044 Adaptec (formerly DPT) 0 +d 10441012 Domino RAID Engine 0 +d 1044a400 SmartCache/Raid I-IV Controller 0 +d 1044a500 PCI Bridge 0 +d 1044a501 SmartRAID V Controller 0 +s 1044a5011044c001 PM1554U2 Ultra2 Single Channel 0 +s 1044a5011044c002 PM1654U2 Ultra2 Single Channel 0 +s 1044a5011044c003 PM1564U3 Ultra3 Single Channel 0 +s 1044a5011044c004 PM1564U3 Ultra3 Dual Channel 0 +s 1044a5011044c005 PM1554U2 Ultra2 Single Channel (NON ACPI) 0 +s 1044a5011044c00a PM2554U2 Ultra2 Single Channel 0 +s 1044a5011044c00b PM2654U2 Ultra2 Single Channel 0 +s 1044a5011044c00c PM2664U3 Ultra3 Single Channel 0 +s 1044a5011044c00d PM2664U3 Ultra3 Dual Channel 0 +s 1044a5011044c00e PM2554U2 Ultra2 Single Channel (NON ACPI) 0 +s 1044a5011044c00f PM2654U2 Ultra2 Single Channel (NON ACPI) 0 +s 1044a5011044c014 PM3754U2 Ultra2 Single Channel (NON ACPI) 0 +s 1044a5011044c015 PM3755U2B Ultra2 Single Channel (NON ACPI) 0 +s 1044a5011044c016 PM3755F Fibre Channel (NON ACPI) 0 +s 1044a5011044c01e PM3757U2 Ultra2 Single Channel 0 +s 1044a5011044c01f PM3757U2 Ultra2 Dual Channel 0 +s 1044a5011044c020 PM3767U3 Ultra3 Dual Channel 0 +s 1044a5011044c021 PM3767U3 Ultra3 Quad Channel 0 +s 1044a5011044c028 PM2865U3 Ultra3 Single Channel 0 +s 1044a5011044c029 PM2865U3 Ultra3 Dual Channel 0 +s 1044a5011044c02a PM2865F Fibre Channel 0 +s 1044a5011044c03c 2000S Ultra3 Single Channel 0 +s 1044a5011044c03d 2000S Ultra3 Dual Channel 0 +s 1044a5011044c03e 2000F Fibre Channel 0 +s 1044a5011044c046 3000S Ultra3 Single Channel 0 +s 1044a5011044c047 3000S Ultra3 Dual Channel 0 +s 1044a5011044c048 3000F Fibre Channel 0 +s 1044a5011044c050 5000S Ultra3 Single Channel 0 +s 1044a5011044c051 5000S Ultra3 Dual Channel 0 +s 1044a5011044c052 5000F Fibre Channel 0 +s 1044a5011044c05a 2400A UDMA Four Channel 0 +s 1044a5011044c05b 2400A UDMA Four Channel DAC 0 +s 1044a5011044c064 3010S Ultra3 Dual Channel 0 +s 1044a5011044c065 3010S Ultra3 Four Channel 0 +s 1044a5011044c066 3010S Fibre Channel 0 +d 1044a511 SmartRAID V Controller 0 +s 1044a5111044c032 ASR-2005S I2O Zero Channel 0 +v 1045 OPTi Inc. 0 +d 1045a0f8 82C750 [Vendetta] USB Controller 0 +d 1045c101 92C264 0 +d 1045c178 92C178 0 +d 1045c556 82X556 [Viper] 0 +d 1045c557 82C557 [Viper-M] 0 +d 1045c558 82C558 [Viper-M ISA+IDE] 0 +d 1045c567 82C750 [Vendetta], device 0 0 +d 1045c568 82C750 [Vendetta], device 1 0 +d 1045c569 82C579 [Viper XPress+ Chipset] 0 +d 1045c621 82C621 [Viper-M/N+] 0 +d 1045c700 82C700 [FireStar] 0 +d 1045c701 82C701 [FireStar Plus] 0 +d 1045c814 82C814 [Firebridge 1] 0 +d 1045c822 82C822 0 +d 1045c824 82C824 0 +d 1045c825 82C825 [Firebridge 2] 0 +d 1045c832 82C832 0 +d 1045c861 82C861 0 +d 1045c895 82C895 0 +d 1045c935 EV1935 ECTIVA MachOne PCIAudio 0 +d 1045d568 82C825 [Firebridge 2] 0 +d 1045d721 IDE [FireStar] 0 +v 1046 IPC Corporation, Ltd. 0 +v 1047 Genoa Systems Corp 0 +v 1048 Elsa AG 0 +d 10480c60 Gladiac MX 0 +d 10480d22 Quadro4 900XGL [ELSA GLoria4 900XGL] 0 +d 10481000 QuickStep 1000 0 +d 10483000 QuickStep 3000 0 +d 10488901 Gloria XL 0 +v 1049 Fountain Technologies, Inc. 0 +v 104a STMicroelectronics 0 # nee SGS Thomson Microelectronics +d 104a0008 STG 2000X 0 +d 104a0009 STG 1764X 0 +d 104a0010 STG4000 [3D Prophet Kyro Series] 0 +d 104a0209 STPC Consumer/Industrial North- and Southbridge 0 +d 104a020a STPC Atlas/ConsumerS/Consumer IIA Northbridge 0 +d 104a0210 STPC Atlas ISA Bridge 0 From <http://gatekeeper.dec.com/pub/BSD/FreeBSD/FreeBSD-stable/src/share/misc/pci_vendors> +d 104a021a STPC Consumer S Southbridge 0 +d 104a021b STPC Consumer IIA Southbridge 0 +d 104a0500 ST70137 [Unicorn] ADSL DMT Transceiver 0 +d 104a0564 STPC Client Northbridge 0 +d 104a0981 21x4x DEC-Tulip compatible 10/100 Ethernet 0 +d 104a1746 STG 1764X 0 +d 104a2774 21x4x DEC-Tulip compatible 10/100 Ethernet 0 +d 104a3520 MPEG-II decoder card 0 +d 104a55cc STPC Client Southbridge 0 +v 104b BusLogic 0 +d 104b0140 BT-946C (old) [multimaster 01] 0 +d 104b1040 BT-946C (BA80C30) [MultiMaster 10] 0 +d 104b8130 Flashpoint LT 0 +v 104c Texas Instruments 0 +d 104c0500 100 MBit LAN Controller 0 +d 104c0508 TMS380C2X Compressor Interface 0 +d 104c1000 Eagle i/f AS 0 +d 104c104c PCI1510 PC card Cardbus Controller 0 +d 104c3d04 TVP4010 [Permedia] 0 +d 104c3d07 TVP4020 [Permedia 2] 0 +s 104c3d0710114d10 Comet 0 +s 104c3d071040000f AccelStar II 0 +s 104c3d0710400011 AccelStar II 0 +s 104c3d0710480a31 WINNER 2000 0 +s 104c3d0710480a32 GLoria Synergy 0 +s 104c3d0710480a35 GLoria Synergy 0 +s 104c3d07107d2633 WinFast 3D L2300 0 +s 104c3d0710920127 FIRE GL 1000 PRO 0 +s 104c3d0710920136 FIRE GL 1000 PRO 0 +s 104c3d0710920141 FIRE GL 1000 PRO 0 +s 104c3d0710920146 FIRE GL 1000 PRO 0 +s 104c3d0710920148 FIRE GL 1000 PRO 0 +s 104c3d0710920149 FIRE GL 1000 PRO 0 +s 104c3d0710920152 FIRE GL 1000 PRO 0 +s 104c3d0710920154 FIRE GL 1000 PRO 0 +s 104c3d0710920155 FIRE GL 1000 PRO 0 +s 104c3d0710920156 FIRE GL 1000 PRO 0 +s 104c3d0710920157 FIRE GL 1000 PRO 0 +s 104c3d0710973d01 Jeronimo Pro 0 +s 104c3d071102100f Graphics Blaster Extreme 0 +s 104c3d073d3d0100 Reference Permedia 2 3D 0 +d 104c8000 PCILynx/PCILynx2 IEEE 1394 Link Layer Controller 0 +s 104c8000e4bf1010 CF1-1-SNARE 0 +s 104c8000e4bf1020 CF1-2-SNARE 0 +d 104c8009 FireWire Controller 0 +s 104c8009104d8032 8032 OHCI i.LINK (IEEE 1394) Controller 0 +d 104c8017 PCI4410 FireWire Controller 0 +d 104c8019 TSB12LV23 IEEE-1394 Controller 0 +s 104c801911bd000a Studio DV500-1394 0 +s 104c801911bd000e Studio DV 0 +s 104c8019e4bf1010 CF2-1-CYMBAL 0 +d 104c8020 TSB12LV26 IEEE-1394 Controller (Link) 0 +d 104c8021 TSB43AA22 IEEE-1394 Controller (PHY/Link Integrated) 0 +s 104c8021104d80df Vaio PCG-FX403 0 +s 104c8021104d80e7 VAIO PCG-GR214EP/GR214MP/GR215MP/GR314MP/GR315MP 0 +d 104c8022 TSB43AB22 IEEE-1394a-2000 Controller (PHY/Link) 0 +d 104c8023 TSB43AB22/A IEEE-1394a-2000 Controller (PHY/Link) 0 +d 104c8024 TSB43AB23 IEEE-1394a-2000 Controller (PHY/Link) 0 +d 104c8025 TSB82AA2 IEEE-1394b Link Layer Controller 0 +s 104c802555aa55aa FireWire 800 PCI Card 0 +d 104c8026 TSB43AB21 IEEE-1394a-2000 Controller (PHY/Link) 0 +d 104c8027 PCI4451 IEEE-1394 Controller 0 +s 104c8027102800e6 PCI4451 IEEE-1394 Controller (Dell Inspiron 8100) 0 +d 104c8029 PCI4510 IEEE-1394 Controller 0 +s 104c802910280163 Latitude D505 0 +s 104c802910718160 MIM2900 0 +d 104c802e PCI7x20 1394a-2000 OHCI Two-Port PHY/Link-Layer Controller 0 +d 104c8201 PCI1620 Firmware Loading Function 0 +d 104c8400 ACX 100 22Mbps Wireless Interface 0 +s 104c840000fc16ec U.S. Robotics 22 Mbps Wireless PC Card (model 2210) 0 +s 104c840000fd16ec U.S. Robotics 22Mbps Wireless PCI Adapter (model 2216) 0 +s 104c840011863b00 DWL-650+ PC Card cardbus 22Mbs Wireless Adapter [AirPlus] 0 +s 104c840011863b01 DWL-520+ 22Mbps PCI Wireless Adapter 0 +d 104c8401 ACX 100 22Mbps Wireless Interface 0 +d 104c9000 Wireless Interface (of unknown type) 0 OK, this info is almost useless as is, but at least it's known that it's a wireless card. More info requested from reporter (whi +d 104c9066 ACX 111 54Mbps Wireless Interface 0 +d 104ca001 TDC1570 0 +d 104ca100 TDC1561 0 +d 104ca102 TNETA1575 HyperSAR Plus w/PCI Host i/f & UTOPIA i/f 0 +d 104ca106 TMS320C6205 Fixed Point DSP 0 +s 104ca106175c5000 ASI50xx Audio Adapter 0 +s 104ca106175c8700 ASI87xx Radio Tuner card 0 +d 104cac10 PCI1050 0 +d 104cac11 PCI1053 0 +d 104cac12 PCI1130 0 +d 104cac13 PCI1031 0 +d 104cac15 PCI1131 0 +d 104cac16 PCI1250 0 +s 104cac1610140092 ThinkPad 600 0 +d 104cac17 PCI1220 0 +d 104cac18 PCI1260 0 +d 104cac19 PCI1221 0 +d 104cac1a PCI1210 0 +d 104cac1b PCI1450 0 +s 104cac1b0e11b113 Armada M700 0 +d 104cac1c PCI1225 0 +s 104cac1c0e11b121 Armada E500 0 +s 104cac1c10280088 Dell Computer Corporation Latitude CPi A400XT 0 +d 104cac1d PCI1251A 0 +d 104cac1e PCI1211 0 +d 104cac1f PCI1251B 0 +d 104cac20 TI 2030 0 +d 104cac21 PCI2031 0 +d 104cac22 PCI2032 PCI Docking Bridge 0 +d 104cac23 PCI2250 PCI-to-PCI Bridge 0 +d 104cac28 PCI2050 PCI-to-PCI Bridge 0 +d 104cac30 PCI1260 PC card Cardbus Controller 0 +d 104cac40 PCI4450 PC card Cardbus Controller 0 +d 104cac41 PCI4410 PC card Cardbus Controller 0 +d 104cac42 PCI4451 PC card Cardbus Controller 0 +s 104cac42102800e6 PCI4451 PC card CardBus Controller (Dell Inspiron 8100) 0 +d 104cac44 PCI4510 PC card Cardbus Controller 0 +s 104cac4410280163 Latitude D505 0 +s 104cac4410718160 MIM2000 0 +d 104cac46 PCI4520 PC card Cardbus Controller 0 +d 104cac50 PCI1410 PC card Cardbus Controller 0 +d 104cac51 PCI1420 0 +s 104cac511014023b ThinkPad T23 (2647-4MG) 0 +s 104cac51102800b1 Latitude C600 0 +s 104cac511028012a Latitude C640 0 +s 104cac51103380cd Versa Note VXi 0 +s 104cac5110cf1095 Lifebook C6155 0 +s 104cac51e4bf1000 CP2-2-HIPHOP 0 +d 104cac52 PCI1451 PC card Cardbus Controller 0 +d 104cac53 PCI1421 PC card Cardbus Controller 0 +d 104cac54 PCI1620 PC Card Controller 0 +d 104cac55 PCI1520 PC card Cardbus Controller 0 +s 104cac5510140512 ThinkPad T30/T40 0 +d 104cac56 PCI1510 PC card Cardbus Controller 0 +s 104cac5610140528 ThinkPad R40e (2684-HVG) Cardbus Controller 0 +d 104cac60 PCI2040 PCI to DSP Bridge Controller 0 +s 104cac60175c5100 ASI51xx Audio Adapter 0 +s 104cac60175c6100 ASI61xx Audio Adapter 0 +s 104cac60175c6200 ASI62xx Audio Adapter 0 +d 104cac8d PCI 7620 0 +d 104cac8e PCI7420 CardBus Controller 0 +d 104cac8f PCI7420/PCI7620 Dual Socket CardBus and Smart Card Cont. w/ 1394a-2000 OHCI Two-Port PHY/Link-Layer Cont. and SD/MS-Pro Sockets 0 +d 104cfe00 FireWire Host Controller 0 +d 104cfe03 12C01A FireWire Host Controller 0 +v 104d Sony Corporation 0 +d 104d8009 CXD1947Q i.LINK Controller 0 +d 104d8039 CXD3222 i.LINK Controller 0 +d 104d8056 Rockwell HCF 56K modem 0 +d 104d808a Memory Stick Controller 0 +v 104e Oak Technology, Inc 0 +d 104e0017 OTI-64017 0 +d 104e0107 OTI-107 [Spitfire] 0 +d 104e0109 Video Adapter 0 +d 104e0111 OTI-64111 [Spitfire] 0 +d 104e0217 OTI-64217 0 +d 104e0317 OTI-64317 0 +v 104f Co-time Computer Ltd 0 +v 1050 Winbond Electronics Corp 0 +d 10500000 NE2000 0 +d 10500001 W83769F 0 +d 10500105 W82C105 0 +d 10500840 W89C840 0 +s 1050084010500001 W89C840 Ethernet Adapter 0 +s 1050084010500840 W89C840 Ethernet Adapter 0 +d 10500940 W89C940 0 +d 10505a5a W89C940F 0 +d 10506692 W6692 0 +d 10509921 W99200F MPEG-1 Video Encoder 0 +d 10509922 W99200F/W9922PF MPEG-1/2 Video Encoder 0 +d 10509970 W9970CF 0 +v 1051 Anigma, Inc. 0 +v 1052 ?Young Micro Systems 0 +v 1053 Young Micro Systems 0 +v 1054 Hitachi, Ltd 0 +v 1055 Efar Microsystems 0 +d 10559130 SLC90E66 [Victory66] IDE 0 +d 10559460 SLC90E66 [Victory66] ISA 0 +d 10559462 SLC90E66 [Victory66] USB 0 +d 10559463 SLC90E66 [Victory66] ACPI 0 +v 1056 ICL 0 +v 1057 Motorola 0 Motorola made a mistake and used 1507 instead of 1057 in some chips. Please look at the 1507 entry as well when updating this. +d 10570001 MPC105 [Eagle] 0 +d 10570002 MPC106 [Grackle] 0 +d 10570003 MPC8240 [Kahlua] 0 +d 10570004 MPC107 0 +d 10570006 MPC8245 [Unity] 0 +d 10570008 MPC8540 0 +d 10570009 MPC8560 0 +d 10570100 MC145575 [HFC-PCI] 0 +d 10570431 KTI829c 100VG 0 +d 10571801 DSP56301 Digital Signal Processor 0 +s 1057180114fb0101 Transas Radar Imitator Board [RIM] 0 +s 1057180114fb0102 Transas Radar Imitator Board [RIM-2] 0 +s 1057180114fb0202 Transas Radar Integrator Board [RIB-2] 0 +s 1057180114fb0611 1 channel CAN bus Controller [CanPci-1] 0 +s 1057180114fb0612 2 channels CAN bus Controller [CanPci-2] 0 +s 1057180114fb0613 3 channels CAN bus Controller [CanPci-3] 0 +s 1057180114fb0614 4 channels CAN bus Controller [CanPci-4] 0 +s 1057180114fb0621 1 channel CAN bus Controller [CanPci2-1] 0 +s 1057180114fb0622 2 channels CAN bus Controller [CanPci2-2] 0 +s 1057180114fb0810 Transas VTS Radar Integrator Board [RIB-4] 0 +s 10571801175c4200 ASI4215 Audio Adapter 0 +s 10571801175c4300 ASI43xx Audio Adapter 0 +s 10571801175c4400 ASI4401 Audio Adapter 0 +s 10571801ecc00030 Layla 0 +d 105718c0 MPC8265A/MPC8266 0 +d 105718c1 MPC8271/MPC8272 0 +d 10574801 Raven 0 +d 10574802 Falcon 0 +d 10574803 Hawk 0 +d 10574806 CPX8216 0 +d 10574d68 20268 0 +d 10575600 SM56 PCI Modem 0 +s 1057560010570300 SM56 PCI Speakerphone Modem 0 +s 1057560010570301 SM56 PCI Voice Modem 0 +s 1057560010570302 SM56 PCI Fax Modem 0 +s 1057560010575600 SM56 PCI Voice modem 0 +s 1057560013d20300 SM56 PCI Speakerphone Modem 0 +s 1057560013d20301 SM56 PCI Voice modem 0 +s 1057560013d20302 SM56 PCI Fax Modem 0 +s 1057560014360300 SM56 PCI Speakerphone Modem 0 +s 1057560014360301 SM56 PCI Voice modem 0 +s 1057560014360302 SM56 PCI Fax Modem 0 +s 10575600144f100c SM56 PCI Fax Modem 0 +s 1057560014940300 SM56 PCI Speakerphone Modem 0 +s 1057560014940301 SM56 PCI Voice modem 0 +s 1057560014c80300 SM56 PCI Speakerphone Modem 0 +s 1057560014c80302 SM56 PCI Fax Modem 0 +s 1057560016680300 SM56 PCI Speakerphone Modem 0 +s 1057560016680302 SM56 PCI Fax Modem 0 +d 10575803 MPC5200 0 +d 10576400 MPC190 Security Processor (S1 family, encryption) 0 +d 10576405 MPC184 Security Processor (S1 family) 0 +v 1058 Electronics & Telecommunications RSH 0 +v 1059 Teknor Industrial Computers Inc 0 +v 105a Promise Technology, Inc. 0 +d 105a0d30 PDC20265 (FastTrak100 Lite/Ultra100) 0 more correct description from promise linux sources +s 105a0d30105a4d33 Ultra100 0 +d 105a0d38 20263 0 +s 105a0d38105a4d39 Fasttrak66 0 +d 105a1275 20275 0 +d 105a3318 PDC20318 (SATA150 TX4) 0 +d 105a3319 PDC20319 (FastTrak S150 TX4) 0 +s 105a331980863427 S875WP1-E mainboard 0 +d 105a3371 PDC20371 (FastTrak S150 TX2plus) 0 +d 105a3373 PDC20378 (FastTrak 378/SATA 378) 0 +s 105a3373104380f5 PC-DL Deluxe motherboard 0 +s 105a33731462702e K8T NEO FIS2R motherboard 0 +d 105a3375 PDC20375 (SATA150 TX2plus) 0 +d 105a3376 PDC20376 (FastTrak 376) 0 +s 105a33761043809e A7V8X motherboard 0 +d 105a3574 PDC20579 SATAII 150 IDE Controller 0 +d 105a3d18 PDC20518 SATAII 150 IDE Controller 0 +d 105a4d30 PDC20267 (FastTrak100/Ultra100) 0 +s 105a4d30105a4d33 Ultra100 0 +s 105a4d30105a4d39 FastTrak100 0 +d 105a4d33 20246 0 +s 105a4d33105a4d33 20246 IDE Controller 0 +d 105a4d38 PDC20262 (FastTrak66/Ultra66) 0 +s 105a4d38105a4d30 Ultra Device on SuperTrak 0 +s 105a4d38105a4d33 Ultra66 0 +s 105a4d38105a4d39 FastTrak66 0 +d 105a4d68 PDC20268 (Ultra100 TX2) 0 +s 105a4d68105a4d68 Ultra100TX2 0 +d 105a4d69 20269 0 +s 105a4d69105a4d68 Ultra133TX2 0 +d 105a5275 PDC20276 (MBFastTrak133 Lite) 0 +s 105a5275105a0275 SuperTrak SX6000 IDE 0 +s 105a5275105a1275 MBFastTrak133 Lite (tm) Controller (RAID mode) 0 +s 105a52751458b001 MBUltra 133 0 +d 105a5300 DC5300 0 +d 105a6268 PDC20270 (FastTrak100 LP/TX2/TX4) 0 +s 105a6268105a4d68 FastTrak100 TX2 0 +d 105a6269 PDC20271 (FastTrak TX2000) 0 +s 105a6269105a6269 FastTrak TX2/TX2000 0 +d 105a6621 PDC20621 (FastTrak S150 SX4/FastTrak SX4000 lite) 0 +d 105a6622 PDC20621 [SATA150 SX4] 4 Channel IDE RAID Controller 0 +d 105a6626 PDC20618 (Ultra 618) 0 +d 105a6629 PDC20619 (FastTrak TX4000) 0 +d 105a7275 PDC20277 (SBFastTrak133 Lite) 0 +v 105b Foxconn International, Inc. 0 +v 105c Wipro Infotech Limited 0 +v 105d Number 9 Computer Company 0 +d 105d2309 Imagine 128 0 +d 105d2339 Imagine 128-II 0 +s 105d2339105d0000 Imagine 128 series 2 4Mb VRAM 0 +s 105d2339105d0001 Imagine 128 series 2 4Mb VRAM 0 +s 105d2339105d0002 Imagine 128 series 2 4Mb VRAM 0 +s 105d2339105d0003 Imagine 128 series 2 4Mb VRAM 0 +s 105d2339105d0004 Imagine 128 series 2 4Mb VRAM 0 +s 105d2339105d0005 Imagine 128 series 2 4Mb VRAM 0 +s 105d2339105d0006 Imagine 128 series 2 4Mb VRAM 0 +s 105d2339105d0007 Imagine 128 series 2 4Mb VRAM 0 +s 105d2339105d0008 Imagine 128 series 2e 4Mb DRAM 0 +s 105d2339105d0009 Imagine 128 series 2e 4Mb DRAM 0 +s 105d2339105d000a Imagine 128 series 2 8Mb VRAM 0 +s 105d2339105d000b Imagine 128 series 2 8Mb H-VRAM 0 +s 105d233911a4000a Barco Metheus 5 Megapixel 0 +s 105d233913cc0000 Barco Metheus 5 Megapixel 0 +s 105d233913cc0004 Barco Metheus 5 Megapixel 0 +s 105d233913cc0005 Barco Metheus 5 Megapixel 0 +s 105d233913cc0006 Barco Metheus 5 Megapixel 0 +s 105d233913cc0008 Barco Metheus 5 Megapixel 0 +s 105d233913cc0009 Barco Metheus 5 Megapixel 0 +s 105d233913cc000a Barco Metheus 5 Megapixel 0 +s 105d233913cc000c Barco Metheus 5 Megapixel 0 +d 105d493d Imagine 128 T2R [Ticket to Ride] 0 +s 105d493d11a4000a Barco Metheus 5 Megapixel, Dual Head 0 +s 105d493d11a4000b Barco Metheus 5 Megapixel, Dual Head 0 +s 105d493d13cc0002 Barco Metheus 4 Megapixel, Dual Head 0 +s 105d493d13cc0003 Barco Metheus 5 Megapixel, Dual Head 0 +s 105d493d13cc0007 Barco Metheus 5 Megapixel, Dual Head 0 +s 105d493d13cc0008 Barco Metheus 5 Megapixel, Dual Head 0 +s 105d493d13cc0009 Barco Metheus 5 Megapixel, Dual Head 0 +s 105d493d13cc000a Barco Metheus 5 Megapixel, Dual Head 0 +d 105d5348 Revolution 4 0 +s 105d5348105d0037 Revolution IV-FP AGP (For SGI 1600SW) 0 +v 105e Vtech Computers Ltd 0 +v 105f Infotronic America Inc 0 +v 1060 United Microelectronics [UMC] 0 +d 10600001 UM82C881 0 +d 10600002 UM82C886 0 +d 10600101 UM8673F 0 +d 10600881 UM8881 0 +d 10600886 UM8886F 0 +d 10600891 UM8891A 0 +d 10601001 UM886A 0 +d 1060673a UM8886BF 0 +d 1060673b EIDE Master/DMA 0 +d 10608710 UM8710 0 +d 1060886a UM8886A 0 +d 10608881 UM8881F 0 +d 10608886 UM8886F 0 +d 1060888a UM8886A 0 +d 10608891 UM8891A 0 +d 10609017 UM9017F 0 +d 10609018 UM9018 0 +d 10609026 UM9026 0 +d 1060e881 UM8881N 0 +d 1060e886 UM8886N 0 +d 1060e88a UM8886N 0 +d 1060e891 UM8891N 0 +v 1061 I.I.T. 0 +d 10610001 AGX016 0 +d 10610002 IIT3204/3501 0 +v 1062 Maspar Computer Corp 0 +v 1063 Ocean Office Automation 0 +v 1064 Alcatel 0 +v 1065 Texas Microsystems 0 +v 1066 PicoPower Technology 0 +d 10660000 PT80C826 0 +d 10660001 PT86C521 [Vesuvius v1] Host Bridge 0 +d 10660002 PT86C523 [Vesuvius v3] PCI-ISA Bridge Master 0 +d 10660003 PT86C524 [Nile] PCI-to-PCI Bridge 0 +d 10660004 PT86C525 [Nile-II] PCI-to-PCI Bridge 0 +d 10660005 National PC87550 System Controller 0 +d 10668002 PT86C523 [Vesuvius v3] PCI-ISA Bridge Slave 0 +v 1067 Mitsubishi Electric 0 +d 10670301 AccelGraphics AccelECLIPSE 0 +d 10670304 AccelGALAXY A2100 [OEM Evans & Sutherland] 0 +d 10670308 Tornado 3000 [OEM Evans & Sutherland] 0 +d 10671002 VG500 [VolumePro Volume Rendering Accelerator] 0 +v 1068 Diversified Technology 0 +v 1069 Mylex Corporation 0 +d 10690001 DAC960P 0 +d 10690002 DAC960PD 0 +d 10690010 DAC960PG 0 +d 10690020 DAC960LA 0 +d 10690050 AcceleRAID 352/170/160 support Device 0 +d 1069b166 Gemstone chipset SCSI controller 0 +s 1069b16610140242 iSeries 2872 DASD IOA 0 +s 1069b16610140266 Dual Channel PCI-X U320 SCSI Adapter 0 +s 1069b16610140278 Dual Channel PCI-X U320 SCSI RAID Adapter 0 +d 1069ba55 eXtremeRAID 1100 support Device 0 +d 1069ba56 eXtremeRAID 2000/3000 support Device 0 +v 106a Aten Research Inc 0 +v 106b Apple Computer Inc. 0 +d 106b0001 Bandit PowerPC host bridge 0 +d 106b0002 Grand Central I/O 0 +d 106b0003 Control Video 0 +d 106b0004 PlanB Video-In 0 +d 106b0007 O'Hare I/O 0 +d 106b000e Hydra Mac I/O 0 +d 106b0010 Heathrow Mac I/O 0 +d 106b0017 Paddington Mac I/O 0 +d 106b0018 UniNorth FireWire 0 +d 106b0019 KeyLargo USB 0 +d 106b001e UniNorth Internal PCI 0 +d 106b001f UniNorth PCI 0 +d 106b0020 UniNorth AGP 0 +d 106b0021 UniNorth GMAC (Sun GEM) 0 +d 106b0022 KeyLargo Mac I/O 0 +d 106b0024 UniNorth/Pangea GMAC (Sun GEM) 0 +d 106b0025 KeyLargo/Pangea Mac I/O 0 +d 106b0026 KeyLargo/Pangea USB 0 +d 106b0027 UniNorth/Pangea AGP 0 +d 106b0028 UniNorth/Pangea PCI 0 +d 106b0029 UniNorth/Pangea Internal PCI 0 +d 106b002d UniNorth 1.5 AGP 0 +d 106b002e UniNorth 1.5 PCI 0 +d 106b002f UniNorth 1.5 Internal PCI 0 +d 106b0030 UniNorth/Pangea FireWire 0 +d 106b0031 UniNorth 2 FireWire 0 +d 106b0032 UniNorth 2 GMAC (Sun GEM) 0 +d 106b0033 UniNorth 2 ATA/100 0 +d 106b0034 UniNorth 2 AGP 0 +d 106b0035 UniNorth 2 PCI 0 +d 106b0036 UniNorth 2 Internal PCI 0 +d 106b003b UniNorth/Intrepid ATA/100 0 +d 106b003e KeyLargo/Intrepid Mac I/O 0 +d 106b003f KeyLargo/Intrepid USB 0 +d 106b0040 K2 KeyLargo USB 0 +d 106b0041 K2 KeyLargo Mac/IO 0 +d 106b0042 K2 FireWire 0 +d 106b0043 K2 ATA/100 0 +d 106b0045 K2 HT-PCI Bridge 0 +d 106b0046 K2 HT-PCI Bridge 0 +d 106b0047 K2 HT-PCI Bridge 0 +d 106b0048 K2 HT-PCI Bridge 0 +d 106b0049 K2 HT-PCI Bridge 0 +d 106b004b U3 AGP 0 +d 106b004c K2 GMAC (Sun GEM) 0 +d 106b004f Shasta Mac I/O 0 +d 106b0050 Shasta IDE 0 +d 106b0051 Shasta (Sun GEM) 0 +d 106b0052 Shasta Firewire 0 +d 106b0053 Shasta PCI Bridge 0 +d 106b0054 Shasta PCI Bridge 0 +d 106b0055 Shasta PCI Bridge 0 +d 106b0058 U3L AGP Bridge 0 +d 106b1645 Tigon3 Gigabit Ethernet NIC (BCM5701) 0 +v 106c Hynix Semiconductor 0 +d 106c8801 Dual Pentium ISA/PCI Motherboard 0 +d 106c8802 PowerPC ISA/PCI Motherboard 0 +d 106c8803 Dual Window Graphics Accelerator 0 +d 106c8804 LAN Controller 0 +d 106c8805 100-BaseT LAN 0 +v 106d Sequent Computer Systems 0 +v 106e DFI, Inc 0 +v 106f City Gate Development Ltd 0 +v 1070 Daewoo Telecom Ltd 0 +v 1071 Mitac 0 +d 10718160 Mitac 8060B Mobile Platform 0 +v 1072 GIT Co Ltd 0 +v 1073 Yamaha Corporation 0 +d 10730001 3D GUI Accelerator 0 +d 10730002 YGV615 [RPA3 3D-Graphics Controller] 0 +d 10730003 YMF-740 0 +d 10730004 YMF-724 0 +s 1073000410730004 YMF724-Based PCI Audio Adapter 0 +d 10730005 DS1 Audio 0 +s 1073000510730005 DS-XG PCI Audio CODEC 0 +d 10730006 DS1 Audio 0 +d 10730008 DS1 Audio 0 +s 1073000810730008 DS-XG PCI Audio CODEC 0 +d 1073000a DS1L Audio 0 +s 1073000a10730004 DS-XG PCI Audio CODEC 0 +s 1073000a1073000a DS-XG PCI Audio CODEC 0 +d 1073000c YMF-740C [DS-1L Audio Controller] 0 +s 1073000c107a000c DS-XG PCI Audio CODEC 0 +d 1073000d YMF-724F [DS-1 Audio Controller] 0 +s 1073000d1073000d DS-XG PCI Audio CODEC 0 +d 10730010 YMF-744B [DS-1S Audio Controller] 0 +s 1073001010730006 DS-XG PCI Audio CODEC 0 +s 1073001010730010 DS-XG PCI Audio CODEC 0 +d 10730012 YMF-754 [DS-1E Audio Controller] 0 +s 1073001210730012 DS-XG PCI Audio Codec 0 +d 10730020 DS-1 Audio 0 +d 10732000 DS2416 Digital Mixing Card 0 +s 1073200010732000 DS2416 Digital Mixing Card 0 +v 1074 NexGen Microsystems 0 +d 10744e78 82c500/1 0 +v 1075 Advanced Integrations Research 0 +v 1076 Chaintech Computer Co. Ltd 0 +v 1077 QLogic Corp. 0 +d 10771016 ISP10160 Single Channel Ultra3 SCSI Processor 0 +d 10771020 ISP1020 Fast-wide SCSI 0 +d 10771022 ISP1022 Fast-wide SCSI 0 +d 10771080 ISP1080 SCSI Host Adapter 0 +d 10771216 ISP12160 Dual Channel Ultra3 SCSI Processor 0 +s 10771216101e8471 QLA12160 on AMI MegaRAID 0 +s 10771216101e8493 QLA12160 on AMI MegaRAID 0 +d 10771240 ISP1240 SCSI Host Adapter 0 +d 10771280 ISP1280 SCSI Host Adapter 0 +d 10772020 ISP2020A Fast!SCSI Basic Adapter 0 +d 10772100 QLA2100 64-bit Fibre Channel Adapter 0 +s 1077210010770001 QLA2100 64-bit Fibre Channel Adapter 0 +d 10772200 QLA2200 64-bit Fibre Channel Adapter 0 +s 1077220010770002 QLA2200 0 +d 10772300 QLA2300 64-bit Fibre Channel Adapter 0 +d 10772312 QLA2312 Fibre Channel Adapter 0 +v 1078 Cyrix Corporation 0 +d 10780000 5510 [Grappa] 0 +d 10780001 PCI Master 0 +d 10780002 5520 [Cognac] 0 +d 10780100 5530 Legacy [Kahlua] 0 +d 10780101 5530 SMI [Kahlua] 0 +d 10780102 5530 IDE [Kahlua] 0 +d 10780103 5530 Audio [Kahlua] 0 +d 10780104 5530 Video [Kahlua] 0 +d 10780400 ZFMicro PCI Bridge 0 +d 10780401 ZFMicro Chipset SMI 0 +d 10780402 ZFMicro Chipset IDE 0 +d 10780403 ZFMicro Expansion Bus 0 +v 1079 I-Bus 0 +v 107a NetWorth 0 +v 107b Gateway 2000 0 +v 107c LG Electronics [Lucky Goldstar Co. Ltd] 0 +v 107d LeadTek Research Inc. 0 +d 107d0000 P86C850 0 +d 107d2134 WinFast 3D S320 II 0 +d 107d2971 [GeForce FX 5900] WinFast A350 TDH MyViVo 0 +v 107e Interphase Corporation 0 +d 107e0001 5515 ATM Adapter [Flipper] 0 +d 107e0002 100 VG AnyLan Controller 0 +d 107e0004 5526 Fibre Channel Host Adapter 0 +d 107e0005 x526 Fibre Channel Host Adapter 0 +d 107e0008 5525/5575 ATM Adapter (155 Mbit) [Atlantic] 0 +d 107e9003 5535-4P-BRI-ST 0 +d 107e9007 5535-4P-BRI-U 0 +d 107e9008 5535-1P-SR 0 +d 107e900c 5535-1P-SR-ST 0 +d 107e900e 5535-1P-SR-U 0 +d 107e9011 5535-1P-PRI 0 +d 107e9013 5535-2P-PRI 0 +d 107e9023 5536-4P-BRI-ST 0 +d 107e9027 5536-4P-BRI-U 0 +d 107e9031 5536-1P-PRI 0 +d 107e9033 5536-2P-PRI 0 +v 107f Data Technology Corporation 0 +d 107f0802 SL82C105 0 +v 1080 Contaq Microsystems 0 +d 10800600 82C599 0 +d 1080c691 Cypress CY82C691 0 +d 1080c693 82c693 0 +v 1081 Supermac Technology 0 +d 10810d47 Radius PCI to NuBUS Bridge 0 +v 1082 EFA Corporation of America 0 +v 1083 Forex Computer Corporation 0 +d 10830001 FR710 0 +v 1084 Parador 0 +v 1085 Tulip Computers Int.B.V. 0 +v 1086 J. Bond Computer Systems 0 +v 1087 Cache Computer 0 +v 1088 Microcomputer Systems (M) Son 0 +v 1089 Data General Corporation 0 +v 108a SBS Technologies 0 Formerly Bit3 Computer Corp. +d 108a0001 VME Bridge Model 617 0 +d 108a0010 VME Bridge Model 618 0 +d 108a0040 dataBLIZZARD 0 +d 108a3000 VME Bridge Model 2706 0 +v 108c Oakleigh Systems Inc. 0 +v 108d Olicom 0 +d 108d0001 Token-Ring 16/4 PCI Adapter (3136/3137) 0 +d 108d0002 16/4 Token Ring 0 +d 108d0004 RapidFire 3139 Token-Ring 16/4 PCI Adapter 0 +s 108d0004108d0004 OC-3139/3140 RapidFire Token-Ring 16/4 Adapter 0 +d 108d0005 GoCard 3250 Token-Ring 16/4 CardBus PC Card 0 +d 108d0006 OC-3530 RapidFire Token-Ring 100 0 +d 108d0007 RapidFire 3141 Token-Ring 16/4 PCI Fiber Adapter 0 +s 108d0007108d0007 OC-3141 RapidFire Token-Ring 16/4 Adapter 0 +d 108d0008 RapidFire 3540 HSTR 100/16/4 PCI Adapter 0 +s 108d0008108d0008 OC-3540 RapidFire HSTR 100/16/4 Adapter 0 +d 108d0011 OC-2315 0 +d 108d0012 OC-2325 0 +d 108d0013 OC-2183/2185 0 +d 108d0014 OC-2326 0 +d 108d0019 OC-2327/2250 10/100 Ethernet Adapter 0 +s 108d0019108d0016 OC-2327 Rapidfire 10/100 Ethernet Adapter 0 +s 108d0019108d0017 OC-2250 GoCard 10/100 Ethernet Adapter 0 +d 108d0021 OC-6151/6152 [RapidFire ATM 155] 0 +d 108d0022 ATM Adapter 0 +v 108e Sun Microsystems Computer Corp. 0 +d 108e0001 EBUS 0 +d 108e1000 EBUS 0 +d 108e1001 Happy Meal 0 +d 108e1100 RIO EBUS 0 +d 108e1101 RIO GEM 0 +d 108e1102 RIO 1394 0 +d 108e1103 RIO USB 0 +d 108e2bad GEM 0 +d 108e5000 Simba Advanced PCI Bridge 0 +d 108e5043 SunPCI Co-processor 0 +d 108e8000 Psycho PCI Bus Module 0 +d 108e8001 Schizo PCI Bus Module 0 +d 108ea000 Ultra IIi 0 +d 108ea001 Ultra IIe 0 +d 108ea801 Tomatillo PCI Bus Module 0 +d 108eabba Cassini 10/100/1000 0 +v 108f Systemsoft 0 +v 1090 Encore Computer Corporation 0 +v 1091 Intergraph Corporation 0 +d 10910020 3D graphics processor 0 +d 10910021 3D graphics processor w/Texturing 0 +d 10910040 3D graphics frame buffer 0 +d 10910041 3D graphics frame buffer 0 +d 10910060 Proprietary bus bridge 0 +d 109100e4 Powerstorm 4D50T 0 +d 10910720 Motion JPEG codec 0 +d 109107a0 Sun Expert3D-Lite Graphics Accelerator 0 +d 10911091 Sun Expert3D Graphics Accelerator 0 +v 1092 Diamond Multimedia Systems 0 +d 109200a0 Speedstar Pro SE 0 +d 109200a8 Speedstar 64 0 +d 10920550 Viper V550 0 +d 109208d4 Supra 2260 Modem 0 +d 1092094c SupraExpress 56i Pro 0 +d 10921092 Viper V330 0 +d 10926120 Maximum DVD 0 +d 10928810 Stealth SE 0 +d 10928811 Stealth 64/SE 0 +d 10928880 Stealth 0 +d 10928881 Stealth 0 +d 109288b0 Stealth 64 0 +d 109288b1 Stealth 64 0 +d 109288c0 Stealth 64 0 +d 109288c1 Stealth 64 0 +d 109288d0 Stealth 64 0 +d 109288d1 Stealth 64 0 +d 109288f0 Stealth 64 0 +d 109288f1 Stealth 64 0 +d 10929999 DMD-I0928-1 "Monster sound" sound chip 0 +v 1093 National Instruments 0 +d 10930160 PCI-DIO-96 0 +d 10930162 PCI-MIO-16XE-50 0 +d 10931170 PCI-MIO-16XE-10 0 +d 10931180 PCI-MIO-16E-1 0 +d 10931190 PCI-MIO-16E-4 0 +d 10931330 PCI-6031E 0 +d 10931350 PCI-6071E 0 +d 109314e0 PCI-6110 0 +d 109314f0 PCI-6111 0 +d 109317d0 PCI-6503 0 +d 10931870 PCI-6713 0 +d 10931880 PCI-6711 0 +d 109318b0 PCI-6052E 0 +d 10932410 PCI-6733 0 +d 10932890 PCI-6036E 0 +d 10932a60 PCI-6023E 0 +d 10932a70 PCI-6024E 0 +d 10932a80 PCI-6025E 0 +d 10932c80 PCI-6035E 0 +d 10932ca0 PCI-6034E 0 +d 1093b001 IMAQ-PCI-1408 0 +d 1093b011 IMAQ-PXI-1408 0 +d 1093b021 IMAQ-PCI-1424 0 +d 1093b031 IMAQ-PCI-1413 0 +d 1093b041 IMAQ-PCI-1407 0 +d 1093b051 IMAQ-PXI-1407 0 +d 1093b061 IMAQ-PCI-1411 0 +d 1093b071 IMAQ-PCI-1422 0 +d 1093b081 IMAQ-PXI-1422 0 +d 1093b091 IMAQ-PXI-1411 0 +d 1093c801 PCI-GPIB 0 +d 1093c831 PCI-GPIB bridge 0 +v 1094 First International Computers [FIC] 0 +v 1095 Silicon Image, Inc. (formerly CMD Technology Inc) 0 +d 10950240 Adaptec AAR-1210SA SATA HostRAID Controller 0 +d 10950640 PCI0640 0 +d 10950643 PCI0643 0 +d 10950646 PCI0646 0 +d 10950647 PCI0647 0 +d 10950648 PCI0648 0 +d 10950649 SiI 0649 Ultra ATA/100 PCI to ATA Host Controller 0 +s 109506490e11005d Integrated Ultra ATA-100 Dual Channel Controller 0 +s 109506490e11007e Integrated Ultra ATA-100 IDE RAID Controller 0 +s 10950649101e0649 AMI MegaRAID IDE 100 Controller 0 +d 10950650 PBC0650A 0 +d 10950670 USB0670 0 +s 1095067010950670 USB0670 0 +d 10950673 USB0673 0 +d 10950680 PCI0680 Ultra ATA-133 Host Controller 0 +s 1095068010953680 Winic W-680 (Silicon Image 680 based) 0 +d 10953112 SiI 3112 [SATALink/SATARaid] Serial ATA Controller 0 +s 1095311210953112 SiI 3112 SATALink Controller 0 +s 1095311210956112 SiI 3112 SATARaid Controller 0 +d 10953114 SiI 3114 [SATALink/SATARaid] Serial ATA Controller 0 +s 1095311410953114 SiI 3114 SATALink Controller 0 +s 1095311410956114 SiI 3114 SATARaid Controller 0 +d 10953124 SiI 3124 PCI-X Serial ATA Controller 0 +s 1095312410953124 SiI 3124 PCI-X Serial ATA Controller 0 +d 10953512 SiI 3512 [SATALink/SATARaid] Serial ATA Controller 0 +s 1095351210953512 SiI 3512 SATALink Controller 0 +s 1095351210956512 SiI 3512 SATARaid Controller 0 +v 1096 Alacron 0 +v 1097 Appian Technology 0 +v 1098 Quantum Designs (H.K.) Ltd 0 +d 10980001 QD-8500 0 +d 10980002 QD-8580 0 +v 1099 Samsung Electronics Co., Ltd 0 +v 109a Packard Bell 0 +v 109b Gemlight Computer Ltd. 0 +v 109c Megachips Corporation 0 +v 109d Zida Technologies Ltd. 0 +v 109e Brooktree Corporation 0 +d 109e0350 Bt848 Video Capture 0 +d 109e0351 Bt849A Video capture 0 +d 109e0369 Bt878 Video Capture 0 +s 109e036910020001 TV-Wonder 0 +s 109e036910020003 TV-Wonder/VE 0 +d 109e036c Bt879(?) Video Capture 0 +s 109e036c13e90070 Win/TV (Video Section) 0 +d 109e036e Bt878 Video Capture 0 +s 109e036e007013eb WinTV Series 0 +s 109e036e0070ff01 Viewcast Osprey 200 0 +s 109e036e00710101 DigiTV PCI 0 +s 109e036e107d6606 WinFast TV 2000 0 +s 109e036e11bd0012 PCTV pro (TV + FM stereo receiver) 0 +s 109e036e11bd001c PCTV Sat (DBC receiver) 0 +s 109e036e127a0001 Bt878 Mediastream Controller NTSC 0 +s 109e036e127a0002 Bt878 Mediastream Controller PAL BG 0 +s 109e036e127a0003 Bt878a Mediastream Controller PAL BG 0 +s 109e036e127a0048 Bt878/832 Mediastream Controller 0 +s 109e036e144f3000 MagicTView CPH060 - Video 0 +s 109e036e14610002 TV98 Series (TV/No FM/Remote) 0 +s 109e036e14610004 AVerTV WDM Video Capture 0 +s 109e036e14610761 AverTV DVB-T 0 +s 109e036e14f10001 Bt878 Mediastream Controller NTSC 0 +s 109e036e14f10002 Bt878 Mediastream Controller PAL BG 0 +s 109e036e14f10003 Bt878a Mediastream Controller PAL BG 0 +s 109e036e14f10048 Bt878/832 Mediastream Controller 0 +s 109e036e18220001 VisionPlus DVB card 0 +s 109e036e18511850 FlyVideo'98 - Video 0 +s 109e036e18511851 FlyVideo II 0 +s 109e036e18521852 FlyVideo'98 - Video (with FM Tuner) 0 +s 109e036e270ffc00 Digitop DTT-1000 0 +s 109e036ebd111200 PCTV pro (TV + FM stereo receiver) 0 +d 109e036f Bt879 Video Capture 0 +s 109e036f127a0044 Bt879 Video Capture NTSC 0 +s 109e036f127a0122 Bt879 Video Capture PAL I 0 +s 109e036f127a0144 Bt879 Video Capture NTSC 0 +s 109e036f127a0222 Bt879 Video Capture PAL BG 0 +s 109e036f127a0244 Bt879a Video Capture NTSC 0 +s 109e036f127a0322 Bt879 Video Capture NTSC 0 +s 109e036f127a0422 Bt879 Video Capture NTSC 0 +s 109e036f127a1122 Bt879 Video Capture PAL I 0 +s 109e036f127a1222 Bt879 Video Capture PAL BG 0 +s 109e036f127a1322 Bt879 Video Capture NTSC 0 +s 109e036f127a1522 Bt879a Video Capture PAL I 0 +s 109e036f127a1622 Bt879a Video Capture PAL BG 0 +s 109e036f127a1722 Bt879a Video Capture NTSC 0 +s 109e036f14f10044 Bt879 Video Capture NTSC 0 +s 109e036f14f10122 Bt879 Video Capture PAL I 0 +s 109e036f14f10144 Bt879 Video Capture NTSC 0 +s 109e036f14f10222 Bt879 Video Capture PAL BG 0 +s 109e036f14f10244 Bt879a Video Capture NTSC 0 +s 109e036f14f10322 Bt879 Video Capture NTSC 0 +s 109e036f14f10422 Bt879 Video Capture NTSC 0 +s 109e036f14f11122 Bt879 Video Capture PAL I 0 +s 109e036f14f11222 Bt879 Video Capture PAL BG 0 +s 109e036f14f11322 Bt879 Video Capture NTSC 0 +s 109e036f14f11522 Bt879a Video Capture PAL I 0 +s 109e036f14f11622 Bt879a Video Capture PAL BG 0 +s 109e036f14f11722 Bt879a Video Capture NTSC 0 +s 109e036f18511850 FlyVideo'98 - Video 0 +s 109e036f18511851 FlyVideo II 0 +s 109e036f18521852 FlyVideo'98 - Video (with FM Tuner) 0 +d 109e0370 Bt880 Video Capture 0 +s 109e037018511850 FlyVideo'98 0 +s 109e037018511851 FlyVideo'98 EZ - video 0 +s 109e037018521852 FlyVideo'98 (with FM Tuner) 0 +d 109e0878 Bt878 Audio Capture 0 +s 109e0878007013eb WinTV Series 0 +s 109e08780070ff01 Viewcast Osprey 200 0 +s 109e087800710101 DigiTV PCI 0 +s 109e087810020001 TV-Wonder 0 +s 109e087810020003 TV-Wonder/VE 0 +s 109e087811bd0012 PCTV pro (TV + FM stereo receiver, audio section) 0 +s 109e087811bd001c PCTV Sat (DBC receiver) 0 +s 109e0878127a0001 Bt878 Video Capture (Audio Section) 0 +s 109e0878127a0002 Bt878 Video Capture (Audio Section) 0 +s 109e0878127a0003 Bt878 Video Capture (Audio Section) 0 +s 109e0878127a0048 Bt878 Video Capture (Audio Section) 0 +s 109e087813e90070 Win/TV (Audio Section) 0 +s 109e0878144f3000 MagicTView CPH060 - Audio 0 +s 109e087814610004 AVerTV WDM Audio Capture 0 +s 109e087814610761 AVerTV DVB-T 0 +s 109e087814f10001 Bt878 Video Capture (Audio Section) 0 +s 109e087814f10002 Bt878 Video Capture (Audio Section) 0 +s 109e087814f10003 Bt878 Video Capture (Audio Section) 0 +s 109e087814f10048 Bt878 Video Capture (Audio Section) 0 +s 109e087818220001 VisionPlus DVB Card 0 +s 109e0878270ffc00 Digitop DTT-1000 0 +s 109e0878bd111200 PCTV pro (TV + FM stereo receiver, audio section) 0 +d 109e0879 Bt879 Audio Capture 0 +s 109e0879127a0044 Bt879 Video Capture (Audio Section) 0 +s 109e0879127a0122 Bt879 Video Capture (Audio Section) 0 +s 109e0879127a0144 Bt879 Video Capture (Audio Section) 0 +s 109e0879127a0222 Bt879 Video Capture (Audio Section) 0 +s 109e0879127a0244 Bt879 Video Capture (Audio Section) 0 +s 109e0879127a0322 Bt879 Video Capture (Audio Section) 0 +s 109e0879127a0422 Bt879 Video Capture (Audio Section) 0 +s 109e0879127a1122 Bt879 Video Capture (Audio Section) 0 +s 109e0879127a1222 Bt879 Video Capture (Audio Section) 0 +s 109e0879127a1322 Bt879 Video Capture (Audio Section) 0 +s 109e0879127a1522 Bt879 Video Capture (Audio Section) 0 +s 109e0879127a1622 Bt879 Video Capture (Audio Section) 0 +s 109e0879127a1722 Bt879 Video Capture (Audio Section) 0 +s 109e087914f10044 Bt879 Video Capture (Audio Section) 0 +s 109e087914f10122 Bt879 Video Capture (Audio Section) 0 +s 109e087914f10144 Bt879 Video Capture (Audio Section) 0 +s 109e087914f10222 Bt879 Video Capture (Audio Section) 0 +s 109e087914f10244 Bt879 Video Capture (Audio Section) 0 +s 109e087914f10322 Bt879 Video Capture (Audio Section) 0 +s 109e087914f10422 Bt879 Video Capture (Audio Section) 0 +s 109e087914f11122 Bt879 Video Capture (Audio Section) 0 +s 109e087914f11222 Bt879 Video Capture (Audio Section) 0 +s 109e087914f11322 Bt879 Video Capture (Audio Section) 0 +s 109e087914f11522 Bt879 Video Capture (Audio Section) 0 +s 109e087914f11622 Bt879 Video Capture (Audio Section) 0 +s 109e087914f11722 Bt879 Video Capture (Audio Section) 0 +d 109e0880 Bt880 Audio Capture 0 +d 109e2115 BtV 2115 Mediastream controller 0 +d 109e2125 BtV 2125 Mediastream controller 0 +d 109e2164 BtV 2164 0 +d 109e2165 BtV 2165 0 +d 109e8230 Bt8230 ATM Segment/Reassembly Ctrlr (SRC) 0 +d 109e8472 Bt8472 0 +d 109e8474 Bt8474 0 +v 109f Trigem Computer Inc. 0 +v 10a0 Meidensha Corporation 0 +v 10a1 Juko Electronics Ind. Co. Ltd 0 +v 10a2 Quantum Corporation 0 +v 10a3 Everex Systems Inc 0 +v 10a4 Globe Manufacturing Sales 0 +v 10a5 Smart Link Ltd. 0 +d 10a53052 SmartPCI562 56K Modem 0 +d 10a55449 SmartPCI561 modem 0 +v 10a6 Informtech Industrial Ltd. 0 +v 10a7 Benchmarq Microelectronics 0 +v 10a8 Sierra Semiconductor 0 +d 10a80000 STB Horizon 64 0 +v 10a9 Silicon Graphics, Inc. 0 +d 10a90001 Crosstalk to PCI Bridge 0 +d 10a90002 Linc I/O controller 0 +d 10a90003 IOC3 I/O controller 0 +d 10a90004 O2 MACE 0 +d 10a90005 RAD Audio 0 +d 10a90006 HPCEX 0 +d 10a90007 RPCEX 0 +d 10a90008 DiVO VIP 0 +d 10a90009 AceNIC Gigabit Ethernet 0 +s 10a9000910a98002 AceNIC Gigabit Ethernet 0 +d 10a90010 AMP Video I/O 0 +d 10a90011 GRIP 0 +d 10a90012 SGH PSHAC GSN 0 +d 10a91001 Magic Carpet 0 +d 10a91002 Lithium 0 +d 10a91003 Dual JPEG 1 0 +d 10a91004 Dual JPEG 2 0 +d 10a91005 Dual JPEG 3 0 +d 10a91006 Dual JPEG 4 0 +d 10a91007 Dual JPEG 5 0 +d 10a91008 Cesium 0 +d 10a9100a IOC4 I/O controller 0 +d 10a92001 Fibre Channel 0 +d 10a92002 ASDE 0 +d 10a98001 O2 1394 0 +d 10a98002 G-net NT 0 +v 10aa ACC Microelectronics 0 +d 10aa0000 ACCM 2188 0 +v 10ab Digicom 0 +v 10ac Honeywell IAC 0 +v 10ad Symphony Labs 0 +d 10ad0001 W83769F 0 +d 10ad0003 SL82C103 0 +d 10ad0005 SL82C105 0 +d 10ad0103 SL82c103 0 +d 10ad0105 SL82c105 0 +d 10ad0565 W83C553 0 +v 10ae Cornerstone Technology 0 +v 10af Micro Computer Systems Inc 0 +v 10b0 CardExpert Technology 0 +v 10b1 Cabletron Systems Inc 0 +v 10b2 Raytheon Company 0 +v 10b3 Databook Inc 0 +d 10b33106 DB87144 0 +d 10b3b106 DB87144 0 +v 10b4 STB Systems Inc 0 +d 10b41b1d Velocity 128 3D 0 +s 10b41b1d10b4237e Velocity 4400 0 +v 10b5 PLX Technology, Inc. 0 +d 10b50001 i960 PCI bus interface 0 +d 10b51076 VScom 800 8 port serial adaptor 0 +d 10b51077 VScom 400 4 port serial adaptor 0 +d 10b51078 VScom 210 2 port serial and 1 port parallel adaptor 0 +d 10b51103 VScom 200 2 port serial adaptor 0 +d 10b51146 VScom 010 1 port parallel adaptor 0 +d 10b51147 VScom 020 2 port parallel adaptor 0 +d 10b52724 Thales PCSM Security Card 0 +d 10b59030 PCI <-> IOBus Bridge Hot Swap 0 +s 10b5903010b52862 Alpermann+Velte PCL PCI LV (3V/5V): Timecode Reader Board 0 +s 10b5903010b52906 Alpermann+Velte PCI TS (3V/5V): Time Synchronisation Board 0 +s 10b5903010b52940 Alpermann+Velte PCL PCI D (3V/5V): Timecode Reader Board 0 +s 10b5903015ed1002 MCCS 8-port Serial Hot Swap 0 +s 10b5903015ed1003 MCCS 16-port Serial Hot Swap 0 +d 10b59036 9036 0 +d 10b59050 PCI <-> IOBus Bridge 0 +s 10b5905010b51067 IXXAT CAN i165 0 +s 10b5905010b51172 IK220 (Heidenhain) 0 +s 10b5905010b52036 SatPak GPS 0 +s 10b5905010b52221 Alpermann+Velte PCL PCI LV: Timecode Reader Board 0 +s 10b5905010b52273 SH-ARC SoHard ARCnet card 0 +s 10b5905010b52431 Alpermann+Velte PCL PCI D: Timecode Reader Board 0 +s 10b5905010b52905 Alpermann+Velte PCI TS: Time Synchronisation Board 0 +s 10b5905010b59050 MP9050 0 +s 10b5905014980362 TPMC866 8 Channel Serial Card 0 +s 10b5905015220001 RockForce 4 Port V.90 Data/Fax/Voice Modem 0 +s 10b5905015220002 RockForce 2 Port V.90 Data/Fax/Voice Modem 0 +s 10b5905015220003 RockForce 6 Port V.90 Data/Fax/Voice Modem 0 +s 10b5905015220004 RockForce 8 Port V.90 Data/Fax/Voice Modem 0 +s 10b5905015220010 RockForce2000 4 Port V.90 Data/Fax/Voice Modem 0 +s 10b5905015220020 RockForce2000 2 Port V.90 Data/Fax/Voice Modem 0 +s 10b5905015ed1000 Macrolink MCCS 8-port Serial 0 +s 10b5905015ed1001 Macrolink MCCS 16-port Serial 0 +s 10b5905015ed1002 Macrolink MCCS 8-port Serial Hot Swap 0 +s 10b5905015ed1003 Macrolink MCCS 16-port Serial Hot Swap 0 +s 10b5905056542036 OpenSwitch 6 Telephony card 0 Sorry, there was a typo +s 10b5905056543132 OpenSwitch 12 Telephony card 0 Sorry, there was a typo +s 10b5905056545634 OpenLine4 Telephony Card 0 +s 10b59050d531c002 PCIntelliCAN 2xSJA1000 CAN bus 0 +s 10b59050d84d4006 EX-4006 1P 0 +s 10b59050d84d4008 EX-4008 1P EPP/ECP 0 +s 10b59050d84d4014 EX-4014 2P 0 +s 10b59050d84d4018 EX-4018 3P EPP/ECP 0 +s 10b59050d84d4025 EX-4025 1S(16C550) RS-232 0 +s 10b59050d84d4027 EX-4027 1S(16C650) RS-232 0 +s 10b59050d84d4028 EX-4028 1S(16C850) RS-232 0 +s 10b59050d84d4036 EX-4036 2S(16C650) RS-232 0 +s 10b59050d84d4037 EX-4037 2S(16C650) RS-232 0 +s 10b59050d84d4038 EX-4038 2S(16C850) RS-232 0 +s 10b59050d84d4052 EX-4052 1S(16C550) RS-422/485 0 +s 10b59050d84d4053 EX-4053 2S(16C550) RS-422/485 0 +s 10b59050d84d4055 EX-4055 4S(16C550) RS-232 0 +s 10b59050d84d4058 EX-4055 4S(16C650) RS-232 0 +s 10b59050d84d4065 EX-4065 8S(16C550) RS-232 0 +s 10b59050d84d4068 EX-4068 8S(16C650) RS-232 0 +s 10b59050d84d4078 EX-4078 2S(16C552) RS-232+1P 0 +d 10b59054 PCI <-> IOBus Bridge 0 +s 10b5905410b52455 Wessex Techology PHIL-PCI 0 +s 10b5905410b52696 Innes Corp AM Radcap card 0 +s 10b5905410b52717 Innes Corp Auricon card 0 +s 10b5905410b52844 Innes Corp TVS Encoder card 0 +s 10b5905412d90002 PCI Prosody Card rev 1.5 0 +s 10b5905416df0011 PIKA PrimeNet MM PCI 0 +s 10b5905416df0012 PIKA PrimeNet MM cPCI 8 0 +s 10b5905416df0013 PIKA PrimeNet MM cPCI 8 (without CAS Signaling Option) 0 +s 10b5905416df0014 PIKA PrimeNet MM cPCI 4 0 +s 10b5905416df0015 PIKA Daytona MM 0 +s 10b5905416df0016 PIKA InLine MM 0 +d 10b59056 Francois 0 +s 10b5905610b52979 CellinkBlade 11 - CPCI board VoATM AAL1 0 +d 10b59060 9060 0 +d 10b5906d 9060SD 0 +s 10b5906d125c0640 Aries 16000P 0 +d 10b5906e 9060ES 0 +d 10b59080 9080 0 +s 10b59080103c10eb (Agilent) E2777B 83K Series PCI based Optical Communication Interface 0 +s 10b59080103c10ec (Agilent) E6978-66442 PCI CIC 0 +s 10b5908010b59080 9080 [real subsystem ID not set] 0 +s 10b59080129d0002 Aculab PCI Prosidy card 0 +s 10b5908012d90002 PCI Prosody Card 0 +s 10b5908012df4422 4422PCI ["Do-All" Telemetry Data Aquisition System] 0 +d 10b5bb04 B&B 3PCIOSD1A Isolated PCI Serial 0 +v 10b6 Madge Networks 0 +d 10b60001 Smart 16/4 PCI Ringnode 0 +d 10b60002 Smart 16/4 PCI Ringnode Mk2 0 +s 10b6000210b60002 Smart 16/4 PCI Ringnode Mk2 0 +s 10b6000210b60006 16/4 CardBus Adapter 0 +d 10b60003 Smart 16/4 PCI Ringnode Mk3 0 +s 10b600030e11b0fd Compaq NC4621 PCI, 4/16, WOL 0 +s 10b6000310b60003 Smart 16/4 PCI Ringnode Mk3 0 +s 10b6000310b60007 Presto PCI Plus Adapter 0 +d 10b60004 Smart 16/4 PCI Ringnode Mk1 0 +d 10b60006 16/4 Cardbus Adapter 0 +s 10b6000610b60006 16/4 CardBus Adapter 0 +d 10b60007 Presto PCI Adapter 0 +s 10b6000710b60007 Presto PCI 0 +d 10b60009 Smart 100/16/4 PCI-HS Ringnode 0 +s 10b6000910b60009 Smart 100/16/4 PCI-HS Ringnode 0 +d 10b6000a Smart 100/16/4 PCI Ringnode 0 +s 10b6000a10b6000a Smart 100/16/4 PCI Ringnode 0 +d 10b6000b 16/4 CardBus Adapter Mk2 0 +s 10b6000b10b60008 16/4 CardBus Adapter Mk2 0 +s 10b6000b10b6000b 16/4 Cardbus Adapter Mk2 0 +d 10b6000c RapidFire 3140V2 16/4 TR Adapter 0 +s 10b6000c10b6000c RapidFire 3140V2 16/4 TR Adapter 0 +d 10b61000 Collage 25/155 ATM Client Adapter 0 +d 10b61001 Collage 155 ATM Server Adapter 0 +v 10b7 3Com Corporation 0 +d 10b70001 3c985 1000BaseSX (SX/TX) 0 +d 10b70013 AR5212 802.11abg NIC (3CRDAG675) 0 +s 10b7001310b72031 3CRDAG675 11a/b/g Wireless PCI Adapter 0 +d 10b70910 3C910-A01 0 +d 10b71006 MINI PCI type 3B Data Fax Modem 0 +d 10b71007 Mini PCI 56k Winmodem 0 +s 10b7100710b7615c Mini PCI 56K Modem 0 +d 10b71201 3c982-TXM 10/100baseTX Dual Port A [Hydra] 0 +d 10b71202 3c982-TXM 10/100baseTX Dual Port B [Hydra] 0 +d 10b71700 3c940 10/100/1000Base-T [Marvell] 0 +s 10b71700104380eb P4P800 Mainboard 0 +s 10b7170010b70010 3C940 Gigabit LOM Ethernet Adapter 0 +s 10b7170010b70020 3C941 Gigabit LOM Ethernet Adapter 0 +s 10b71700147b1407 KV8-MAX3 motherboard 0 +d 10b73390 3c339 TokenLink Velocity 0 +d 10b73590 3c359 TokenLink Velocity XL 0 +s 10b7359010b73590 TokenLink Velocity XL Adapter (3C359/359B) 0 +d 10b74500 3c450 HomePNA [Tornado] 0 +d 10b75055 3c555 Laptop Hurricane 0 +d 10b75057 3c575 Megahertz 10/100 LAN CardBus [Boomerang] 0 +s 10b7505710b75a57 3C575 Megahertz 10/100 LAN Cardbus PC Card 0 +d 10b75157 3cCFE575BT Megahertz 10/100 LAN CardBus [Cyclone] 0 +s 10b7515710b75b57 3C575 Megahertz 10/100 LAN Cardbus PC Card 0 +d 10b75257 3cCFE575CT CardBus [Cyclone] 0 +s 10b7525710b75c57 FE575C-3Com 10/100 LAN CardBus-Fast Ethernet 0 +d 10b75900 3c590 10BaseT [Vortex] 0 +d 10b75920 3c592 EISA 10mbps Demon/Vortex 0 +d 10b75950 3c595 100BaseTX [Vortex] 0 +d 10b75951 3c595 100BaseT4 [Vortex] 0 +d 10b75952 3c595 100Base-MII [Vortex] 0 +d 10b75970 3c597 EISA Fast Demon/Vortex 0 +d 10b75b57 3c595 Megahertz 10/100 LAN CardBus [Boomerang] 0 +s 10b75b5710b75b57 3C575 Megahertz 10/100 LAN Cardbus PC Card 0 +d 10b76000 3CRSHPW796 [OfficeConnect Wireless CardBus] 0 +d 10b76001 3com 3CRWE154G72 [Office Connect Wireless LAN Adapter] 0 +d 10b76055 3c556 Hurricane CardBus [Cyclone] 0 +d 10b76056 3c556B CardBus [Tornado] 0 +s 10b7605610b76556 10/100 Mini PCI Ethernet Adapter 0 +d 10b76560 3cCFE656 CardBus [Cyclone] 0 +s 10b7656010b7656a 3CCFEM656 10/100 LAN+56K Modem CardBus 0 +d 10b76561 3cCFEM656 10/100 LAN+56K Modem CardBus 0 +s 10b7656110b7656b 3CCFEM656 10/100 LAN+56K Modem CardBus 0 +d 10b76562 3cCFEM656B 10/100 LAN+Winmodem CardBus [Cyclone] 0 +s 10b7656210b7656b 3CCFEM656B 10/100 LAN+56K Modem CardBus 0 +d 10b76563 3cCFEM656B 10/100 LAN+56K Modem CardBus 0 +s 10b7656310b7656b 3CCFEM656 10/100 LAN+56K Modem CardBus 0 +d 10b76564 3cXFEM656C 10/100 LAN+Winmodem CardBus [Tornado] 0 +d 10b77646 3cSOHO100-TX Hurricane 0 +d 10b77770 3CRWE777 PCI(PLX) Wireless Adaptor [Airconnect] 0 +d 10b77940 3c803 FDDILink UTP Controller 0 +d 10b77980 3c804 FDDILink SAS Controller 0 +d 10b77990 3c805 FDDILink DAS Controller 0 +d 10b780eb 3c940B 10/100/1000Base-T 0 +d 10b78811 Token ring 0 +d 10b79000 3c900 10BaseT [Boomerang] 0 +d 10b79001 3c900 10Mbps Combo [Boomerang] 0 +d 10b79004 3c900B-TPO Etherlink XL [Cyclone] 0 +s 10b7900410b79004 3C900B-TPO Etherlink XL TPO 10Mb 0 +d 10b79005 3c900B-Combo Etherlink XL [Cyclone] 0 +s 10b7900510b79005 3C900B-Combo Etherlink XL Combo 0 +d 10b79006 3c900B-TPC Etherlink XL [Cyclone] 0 +d 10b7900a 3c900B-FL 10base-FL [Cyclone] 0 +d 10b79050 3c905 100BaseTX [Boomerang] 0 +d 10b79051 3c905 100BaseT4 [Boomerang] 0 +d 10b79055 3c905B 100BaseTX [Cyclone] 0 +s 10b7905510280080 3C905B Fast Etherlink XL 10/100 0 +s 10b7905510280081 3C905B Fast Etherlink XL 10/100 0 +s 10b7905510280082 3C905B Fast Etherlink XL 10/100 0 +s 10b7905510280083 3C905B Fast Etherlink XL 10/100 0 +s 10b7905510280084 3C905B Fast Etherlink XL 10/100 0 +s 10b7905510280085 3C905B Fast Etherlink XL 10/100 0 +s 10b7905510280086 3C905B Fast Etherlink XL 10/100 0 +s 10b7905510280087 3C905B Fast Etherlink XL 10/100 0 +s 10b7905510280088 3C905B Fast Etherlink XL 10/100 0 +s 10b7905510280089 3C905B Fast Etherlink XL 10/100 0 +s 10b7905510280090 3C905B Fast Etherlink XL 10/100 0 +s 10b7905510280091 3C905B Fast Etherlink XL 10/100 0 +s 10b7905510280092 3C905B Fast Etherlink XL 10/100 0 +s 10b7905510280093 3C905B Fast Etherlink XL 10/100 0 +s 10b7905510280094 3C905B Fast Etherlink XL 10/100 0 +s 10b7905510280095 3C905B Fast Etherlink XL 10/100 0 +s 10b7905510280096 3C905B Fast Etherlink XL 10/100 0 +s 10b7905510280097 3C905B Fast Etherlink XL 10/100 0 +s 10b7905510280098 3C905B Fast Etherlink XL 10/100 0 +s 10b7905510280099 3C905B Fast Etherlink XL 10/100 0 +s 10b7905510b79055 3C905B Fast Etherlink XL 10/100 0 +d 10b79056 3c905B-T4 Fast EtherLink XL [Cyclone] 0 +d 10b79058 3c905B Deluxe Etherlink 10/100/BNC [Cyclone] 0 +d 10b7905a 3c905B-FX Fast Etherlink XL FX 100baseFx [Cyclone] 0 +d 10b79200 3c905C-TX/TX-M [Tornado] 0 +s 10b7920010280095 3C920 Integrated Fast Ethernet Controller 0 +s 10b7920010280097 3C920 Integrated Fast Ethernet Controller 0 +s 10b79200102800fe Optiplex GX240 0 +s 10b792001028012a 3C920 Integrated Fast Ethernet Controller [Latitude C640] 0 +s 10b7920010b71000 3C905C-TX Fast Etherlink for PC Management NIC 0 +s 10b7920010b77000 10/100 Mini PCI Ethernet Adapter 0 +s 10b7920010f12466 Tiger MPX S2466 (3C920 Integrated Fast Ethernet Controller) 0 +d 10b79201 3C920B-EMB Integrated Fast Ethernet Controller [Tornado] 0 +s 10b79201104380ab A7N8X Deluxe onboard 3C920B-EMB Integrated Fast Ethernet Controller 0 +d 10b79202 3Com 3C920B-EMB-WNM Integrated Fast Ethernet Controller 0 +d 10b79210 3C920B-EMB-WNM Integrated Fast Ethernet Controller 0 +d 10b79300 3CSOHO100B-TX 910-A01 [tulip] 0 +d 10b79800 3c980-TX Fast Etherlink XL Server Adapter [Cyclone] 0 +s 10b7980010b79800 3c980-TX Fast Etherlink XL Server Adapter 0 +d 10b79805 3c980-C 10/100baseTX NIC [Python-T] 0 +s 10b7980510b71201 EtherLink Server 10/100 Dual Port A 0 +s 10b7980510b71202 EtherLink Server 10/100 Dual Port B 0 +s 10b7980510b79805 3c980 10/100baseTX NIC [Python-T] 0 +s 10b7980510f12462 Thunder K7 S2462 0 +d 10b79900 3C990-TX [Typhoon] 0 +d 10b79902 3CR990-TX-95 [Typhoon 56-bit] 0 +d 10b79903 3CR990-TX-97 [Typhoon 168-bit] 0 +d 10b79904 3C990B-TX-M/3C990BSVR [Typhoon2] 0 +s 10b7990410b71000 3CR990B-TX-M [Typhoon2] 0 +s 10b7990410b72000 3CR990BSVR [Typhoon2 Server] 0 +d 10b79905 3CR990-FX-95/97/95 [Typhon Fiber] 0 +s 10b7990510b71101 3CR990-FX-95 [Typhoon Fiber 56-bit] 0 +s 10b7990510b71102 3CR990-FX-97 [Typhoon Fiber 168-bit] 0 +s 10b7990510b72101 3CR990-FX-95 Server [Typhoon Fiber 56-bit] 0 +s 10b7990510b72102 3CR990-FX-97 Server [Typhoon Fiber 168-bit] 0 +d 10b79908 3CR990SVR95 [Typhoon Server 56-bit] 0 +d 10b79909 3CR990SVR97 [Typhoon Server 168-bit] 0 +d 10b7990a 3C990SVR [Typhoon Server] 0 +d 10b7990b 3C990SVR [Typhoon Server] 0 +v 10b8 Standard Microsystems Corp [SMC] 0 +d 10b80005 83c170 EPIC/100 Fast Ethernet Adapter 0 +s 10b800051055e000 LANEPIC 10/100 [EVB171Q-PCI] 0 +s 10b800051055e002 LANEPIC 10/100 [EVB171G-PCI] 0 +s 10b8000510b8a011 EtherPower II 10/100 0 +s 10b8000510b8a014 EtherPower II 10/100 0 +s 10b8000510b8a015 EtherPower II 10/100 0 +s 10b8000510b8a016 EtherPower II 10/100 0 +s 10b8000510b8a017 EtherPower II 10/100 0 +d 10b80006 83c175 EPIC/100 Fast Ethernet Adapter 0 +s 10b800061055e100 LANEPIC Cardbus Fast Ethernet Adapter 0 +s 10b800061055e102 LANEPIC Cardbus Fast Ethernet Adapter 0 +s 10b800061055e300 LANEPIC Cardbus Fast Ethernet Adapter 0 +s 10b800061055e302 LANEPIC Cardbus Fast Ethernet Adapter 0 +s 10b8000610b8a012 LANEPIC Cardbus Fast Ethernet Adapter 0 +s 10b8000613a28002 LANEPIC Cardbus Fast Ethernet Adapter 0 +s 10b8000613a28006 LANEPIC Cardbus Fast Ethernet Adapter 0 +d 10b81000 FDC 37c665 0 +d 10b81001 FDC 37C922 0 +d 10b82802 SMC2802W [EZ Connect g] 0 802.11g card +d 10b8a011 83C170QF 0 +d 10b8b106 SMC34C90 0 +v 10b9 ALi Corporation 0 +d 10b90101 CMI8338/C3DX PCI Audio Device 0 +d 10b90111 C-Media CMI8738/C3DX Audio Device (OEM) 0 +s 10b9011110b90111 C-Media CMI8738/C3DX Audio Device (OEM) 0 +d 10b90780 Multi-IO Card 0 +d 10b90782 Multi-IO Card 0 +d 10b91435 M1435 0 +d 10b91445 M1445 0 +d 10b91449 M1449 0 +d 10b91451 M1451 0 +d 10b91461 M1461 0 +d 10b91489 M1489 0 +d 10b91511 M1511 [Aladdin] 0 +d 10b91512 M1512 [Aladdin] 0 +d 10b91513 M1513 [Aladdin] 0 +d 10b91521 M1521 [Aladdin III] 0 +s 10b9152110b91521 ALI M1521 Aladdin III CPU Bridge 0 +d 10b91523 M1523 0 +s 10b9152310b91523 ALI M1523 ISA Bridge 0 +d 10b91531 M1531 [Aladdin IV] 0 +d 10b91533 M1533 PCI to ISA Bridge [Aladdin IV] 0 +s 10b915331014053b ThinkPad R40e (2684-HVG) PCI to ISA Bridge 0 +s 10b9153310b91533 ALI M1533 Aladdin IV ISA Bridge 0 +d 10b91541 M1541 0 +s 10b9154110b91541 ALI M1541 Aladdin V/V+ AGP System Controller 0 +d 10b91543 M1543 0 +d 10b91563 M1563 HyperTransport South Bridge 0 +d 10b91621 M1621 0 +d 10b91631 ALI M1631 PCI North Bridge Aladdin Pro III 0 +d 10b91632 M1632M Northbridge+Trident 0 +d 10b91641 ALI M1641 PCI North Bridge Aladdin Pro IV 0 +d 10b91644 M1644/M1644T Northbridge+Trident 0 +d 10b91646 M1646 Northbridge+Trident 0 +d 10b91647 M1647 Northbridge [MAGiK 1 / MobileMAGiK 1] 0 +d 10b91651 M1651/M1651T Northbridge [Aladdin-Pro 5/5M,Aladdin-Pro 5T/5TM] 0 +d 10b91671 M1671 Super P4 Northbridge [AGP4X,PCI and SDR/DDR] 0 +d 10b91672 M1672 Northbridge [CyberALADDiN-P4] 0 +d 10b91681 M1681 P4 Northbridge [AGP8X,HyperTransport and SDR/DDR] 0 +d 10b91687 M1687 K8 Northbridge [AGP8X and HyperTransport] 0 +d 10b91689 M1689 K8 Northbridge [Super K8 Single Chip] 0 +d 10b93141 M3141 0 +d 10b93143 M3143 0 +d 10b93145 M3145 0 +d 10b93147 M3147 0 +d 10b93149 M3149 0 +d 10b93151 M3151 0 +d 10b93307 M3307 0 +d 10b93309 M3309 0 +d 10b93323 M3325 Video/Audio Decoder 0 +d 10b95212 M4803 0 +d 10b95215 MS4803 0 +d 10b95217 M5217H 0 +d 10b95219 M5219 0 +d 10b95225 M5225 0 +d 10b95229 M5229 IDE 0 +s 10b952291014050f ThinkPad R30 0 +s 10b952291014053d ThinkPad R40e (2684-HVG) builtin IDE 0 +s 10b95229103c0024 Pavilion ze4400 builtin IDE 0 +s 10b9522910438053 A7A266 Motherboard IDE 0 +d 10b95235 M5225 0 +d 10b95237 USB 1.1 Controller 0 +s 10b9523710140540 ThinkPad R40e (2684-HVG) builtin USB 0 +s 10b95237103c0024 Pavilion ze4400 builtin USB 0 +d 10b95239 USB 2.0 Controller 0 +d 10b95243 M1541 PCI to AGP Controller 0 +d 10b95246 AGP8X Controller 0 +d 10b95247 PCI to AGP Controller 0 +d 10b95249 M5249 HTT to PCI Bridge 0 +d 10b95251 M5251 P1394 OHCI 1.0 Controller 0 +d 10b95253 M5253 P1394 OHCI 1.1 Controller 0 +d 10b95261 M5261 Ethernet Controller 0 +d 10b95263 M5263 Ethernet Controller 0 +d 10b95281 ALi M5281 Serial ATA / RAID Host Controller 0 +d 10b95450 Lucent Technologies Soft Modem AMR 0 +d 10b95451 M5451 PCI AC-Link Controller Audio Device 0 +s 10b9545110140506 ThinkPad R30 0 +s 10b954511014053e ThinkPad R40e (2684-HVG) builtin Audio 0 +s 10b95451103c0024 Pavilion ze4400 builtin Audio 0 +s 10b9545110b95451 HP Compaq nc4010 (DY885AA#ABN) 0 +d 10b95453 M5453 PCI AC-Link Controller Modem Device 0 +d 10b95455 M5455 PCI AC-Link Controller Audio Device 0 +d 10b95457 M5457 AC'97 Modem Controller 0 +s 10b9545710140535 ThinkPad R40e (2684-HVG) builtin modem 0 +s 10b95457103c0024 Pavilion ze4400 builtin Modem Device 0 +d 10b95459 SmartLink SmartPCI561 56K Modem 0 Same but more usefull for driver's lookup +d 10b9545a SmartLink SmartPCI563 56K Modem 0 SmartLink PCI SoftModem +d 10b95471 M5471 Memory Stick Controller 0 +d 10b95473 M5473 SD-MMC Controller 0 +d 10b97101 M7101 Power Management Controller [PMU] 0 +s 10b9710110140510 ThinkPad R30 0 +s 10b971011014053c ThinkPad R40e (2684-HVG) Power Management Controller 0 +s 10b97101103c0024 Pavilion ze4400 0 +v 10ba Mitsubishi Electric Corp. 0 +d 10ba0301 AccelGraphics AccelECLIPSE 0 +d 10ba0304 AccelGALAXY A2100 [OEM Evans & Sutherland] 0 +d 10ba0308 Tornado 3000 [OEM Evans & Sutherland] 0 +d 10ba1002 VG500 [VolumePro Volume Rendering Accelerator] 0 +v 10bb Dapha Electronics Corporation 0 +v 10bc Advanced Logic Research 0 +v 10bd Surecom Technology 0 +d 10bd0e34 NE-34 0 +v 10be Tseng Labs International Co. 0 +v 10bf Most Inc 0 +v 10c0 Boca Research Inc. 0 +v 10c1 ICM Co., Ltd. 0 +v 10c2 Auspex Systems Inc. 0 +v 10c3 Samsung Semiconductors, Inc. 0 +d 10c31100 Smartether100 SC1100 LAN Adapter (i82557B) 0 +v 10c4 Award Software International Inc. 0 +v 10c5 Xerox Corporation 0 +v 10c6 Rambus Inc. 0 +v 10c7 Media Vision 0 +v 10c8 Neomagic Corporation 0 +d 10c80001 NM2070 [MagicGraph 128] 0 +d 10c80002 NM2090 [MagicGraph 128V] 0 +d 10c80003 NM2093 [MagicGraph 128ZV] 0 +d 10c80004 NM2160 [MagicGraph 128XD] 0 +s 10c80004101400ba MagicGraph 128XD 0 +s 10c8000410251007 MagicGraph 128XD 0 +s 10c8000410280074 MagicGraph 128XD 0 +s 10c8000410280075 MagicGraph 128XD 0 +s 10c800041028007d MagicGraph 128XD 0 +s 10c800041028007e MagicGraph 128XD 0 +s 10c800041033802f MagicGraph 128XD 0 +s 10c80004104d801b MagicGraph 128XD 0 +s 10c80004104d802f MagicGraph 128XD 0 +s 10c80004104d830b MagicGraph 128XD 0 +s 10c8000410ba0e00 MagicGraph 128XD 0 +s 10c8000410c80004 MagicGraph 128XD 0 +s 10c8000410cf1029 MagicGraph 128XD 0 +s 10c8000410f78308 MagicGraph 128XD 0 +s 10c8000410f78309 MagicGraph 128XD 0 +s 10c8000410f7830b MagicGraph 128XD 0 +s 10c8000410f7830d MagicGraph 128XD 0 +s 10c8000410f78312 MagicGraph 128XD 0 +d 10c80005 NM2200 [MagicGraph 256AV] 0 +s 10c80005101400dd ThinkPad 570 0 +s 10c8000510280088 Latitude CPi A 0 +d 10c80006 NM2360 [MagicMedia 256ZX] 0 +d 10c80016 NM2380 [MagicMedia 256XL+] 0 +s 10c8001610c80016 MagicMedia 256XL+ 0 +d 10c80025 NM2230 [MagicGraph 256AV+] 0 +d 10c80083 NM2093 [MagicGraph 128ZV+] 0 +d 10c88005 NM2200 [MagicMedia 256AV Audio] 0 +s 10c880050e11b0d1 MagicMedia 256AV Audio Device on Discovery 0 +s 10c880050e11b126 MagicMedia 256AV Audio Device on Durango 0 +s 10c88005101400dd MagicMedia 256AV Audio Device on BlackTip Thinkpad 0 +s 10c8800510251003 MagicMedia 256AV Audio Device on TravelMate 720 0 +s 10c8800510280088 Latitude CPi A 0 +s 10c880051028008f MagicMedia 256AV Audio Device on Colorado Inspiron 0 +s 10c88005103c0007 MagicMedia 256AV Audio Device on Voyager II 0 +s 10c88005103c0008 MagicMedia 256AV Audio Device on Voyager III 0 +s 10c88005103c000d MagicMedia 256AV Audio Device on Omnibook 900 0 +s 10c8800510c88005 MagicMedia 256AV Audio Device on FireAnt 0 +s 10c88005110a8005 MagicMedia 256AV Audio Device 0 +s 10c8800514c00004 MagicMedia 256AV Audio Device 0 +d 10c88006 NM2360 [MagicMedia 256ZX Audio] 0 +d 10c88016 NM2380 [MagicMedia 256XL+ Audio] 0 +v 10c9 Dataexpert Corporation 0 +v 10ca Fujitsu Microelectr., Inc. 0 +v 10cb Omron Corporation 0 +v 10cc Mai Logic Incorporated 0 nee Mentor ARC Inc +d 10cc0660 Articia S Host Bridge 0 +d 10cc0661 Articia S PCI Bridge 0 +v 10cd Advanced System Products, Inc 0 +d 10cd1100 ASC1100 0 +d 10cd1200 ASC1200 [(abp940) Fast SCSI-II] 0 +d 10cd1300 ABP940-U / ABP960-U 0 +s 10cd130010cd1310 ASC1300 SCSI Adapter 0 +d 10cd2300 ABP940-UW 0 +d 10cd2500 ABP940-U2W 0 +v 10ce Radius 0 +v 10cf Fujitsu Limited. 0 nee Citicorp TTI +d 10cf2001 mb86605 0 +v 10d1 FuturePlus Systems Corp. 0 +v 10d2 Molex Incorporated 0 +v 10d3 Jabil Circuit Inc 0 +v 10d4 Hualon Microelectronics 0 +v 10d5 Autologic Inc. 0 +v 10d6 Cetia 0 +v 10d7 BCM Advanced Research 0 +v 10d8 Advanced Peripherals Labs 0 +v 10d9 Macronix, Inc. [MXIC] 0 +d 10d90512 MX98713 0 +d 10d90531 MX987x5 0 +s 10d9053111861200 DFE-540TX ProFAST 10/100 Adapter 0 +d 10d98625 MX86250 0 +d 10d98888 MX86200 0 +v 10da Compaq IPG-Austin 0 +d 10da0508 TC4048 Token Ring 4/16 0 +d 10da3390 Tl3c3x9 0 +v 10db Rohm LSI Systems, Inc. 0 +v 10dc CERN/ECP/EDU 0 +d 10dc0001 STAR/RD24 SCI-PCI (PMC) 0 +d 10dc0002 TAR/RD24 SCI-PCI (PMC) 0 +d 10dc0021 HIPPI destination 0 +d 10dc0022 HIPPI source 0 +d 10dc10dc ATT2C15-3 FPGA 0 +v 10dd Evans & Sutherland 0 +v 10de nVidia Corporation 0 +d 10de0008 NV1 [EDGE 3D] 0 +d 10de0009 NV1 [EDGE 3D] 0 +d 10de0010 NV2 [Mutara V08] 0 +d 10de0020 NV4 [RIVA TNT] 0 +s 10de002010430200 V3400 TNT 0 +s 10de002010480c18 Erazor II SGRAM 0 +s 10de002010480c1b Erazor II 0 +s 10de002010920550 Viper V550 0 +s 10de002010920552 Viper V550 0 +s 10de002010924804 Viper V550 0 +s 10de002010924808 Viper V550 0 +s 10de002010924810 Viper V550 0 +s 10de002010924812 Viper V550 0 +s 10de002010924815 Viper V550 0 +s 10de002010924820 Viper V550 with TV out 0 +s 10de002010924822 Viper V550 0 +s 10de002010924904 Viper V550 0 +s 10de002010924914 Viper V550 0 +s 10de002010928225 Viper V550 0 +s 10de002010b4273d Velocity 4400 0 +s 10de002010b4273e Velocity 4400 0 +s 10de002010b42740 Velocity 4400 0 +s 10de002010de0020 Riva TNT 0 +s 10de002011021015 Graphics Blaster CT6710 0 +s 10de002011021016 Graphics Blaster RIVA TNT 0 +d 10de0028 NV5 [RIVA TNT2/TNT2 Pro] 0 +s 10de002810430200 AGP-V3800 SGRAM 0 +s 10de002810430201 AGP-V3800 SDRAM 0 +s 10de002810430205 PCI-V3800 0 +s 10de002810434000 AGP-V3800PRO 0 +s 10de002810480c21 Synergy II 0 +s 10de002810480c31 Erazor III 0 +s 10de0028107d2134 WinFast 3D S320 II + TV-Out 0 +s 10de002810924804 Viper V770 0 +s 10de002810924a00 Viper V770 0 +s 10de002810924a02 Viper V770 Ultra 0 +s 10de002810925a00 RIVA TNT2/TNT2 Pro 0 +s 10de002810926a02 Viper V770 Ultra 0 +s 10de002810927a02 Viper V770 Ultra 0 +s 10de002810de0005 RIVA TNT2 Pro 0 +s 10de002810de000f Compaq NVIDIA TNT2 Pro 0 +s 10de002811021020 3D Blaster RIVA TNT2 0 +s 10de002811021026 3D Blaster RIVA TNT2 Digital 0 +s 10de002814af5810 Maxi Gamer Xentor 0 +d 10de0029 NV5 [RIVA TNT2 Ultra] 0 +s 10de002910430200 AGP-V3800 Deluxe 0 +s 10de002910430201 AGP-V3800 Ultra SDRAM 0 +s 10de002910430205 PCI-V3800 Ultra 0 +s 10de002911021021 3D Blaster RIVA TNT2 Ultra 0 +s 10de002911021029 3D Blaster RIVA TNT2 Ultra 0 +s 10de00291102102f 3D Blaster RIVA TNT2 Ultra 0 +s 10de002914af5820 Maxi Gamer Xentor 32 0 +d 10de002a NV5 [Riva TnT2] 0 +d 10de002b NV5 [Riva TnT2] 0 +d 10de002c NV6 [Vanta/Vanta LT] 0 +s 10de002c10430200 AGP-V3800 Combat SDRAM 0 +s 10de002c10430201 AGP-V3800 Combat 0 +s 10de002c10926820 Viper V730 0 +s 10de002c11021031 CT6938 VANTA 8MB 0 +s 10de002c11021034 CT6894 VANTA 16MB 0 +s 10de002c14af5008 Maxi Gamer Phoenix 2 0 +d 10de002d NV5M64 [RIVA TNT2 Model 64/Model 64 Pro] 0 +s 10de002d10430200 AGP-V3800M 0 +s 10de002d10430201 AGP-V3800M 0 +s 10de002d10480c3a Erazor III LT 0 +s 10de002d10de001e M64 AGP4x 0 +s 10de002d11021023 CT6892 RIVA TNT2 Value 0 +s 10de002d11021024 CT6932 RIVA TNT2 Value 32Mb 0 +s 10de002d1102102c CT6931 RIVA TNT2 Value [Jumper] 0 +s 10de002d14628808 MSI-8808 0 +s 10de002d15541041 Pixelview RIVA TNT2 M64 0 +d 10de002e NV6 [Vanta] 0 +d 10de002f NV6 [Vanta] 0 +d 10de0034 MCP04 SMBus 0 +d 10de0035 MCP04 IDE 0 +d 10de0036 MCP04 Serial ATA Controller 0 +d 10de0037 MCP04 Ethernet Controller 0 +d 10de0038 MCP04 Ethernet Controller 0 +d 10de003a MCP04 AC'97 Audio Controller 0 +d 10de003b MCP04 USB Controller 0 +d 10de003c MCP04 USB Controller 0 +d 10de003d MCP04 PCI Bridge 0 +d 10de003e MCP04 Serial ATA Controller 0 +d 10de0040 nv40 [GeForce 6800 Ultra] 0 +d 10de0041 NV40 [GeForce 6800] 0 +d 10de0042 NV40.2 0 +d 10de0043 NV40.3 0 +d 10de0045 NV40 [GeForce 6800 GT] 0 +d 10de0049 NV40GL 0 +d 10de004e NV40GL [Quadro FX 4000] 0 +d 10de0052 CK804 SMBus 0 +d 10de0053 CK804 IDE 0 +d 10de0054 CK804 Serial ATA Controller 0 +d 10de0055 CK804 Serial ATA Controller 0 +d 10de0056 CK804 Ethernet Controller 0 +d 10de0057 CK804 Ethernet Controller 0 +d 10de0059 CK804 AC'97 Audio Controller 0 +d 10de005a CK804 USB Controller 0 +d 10de005b CK804 USB Controller 0 +d 10de005c CK804 PCI Bridge 0 +d 10de005d CK804 PCIE Bridge 0 +d 10de005e CK804 Memory Controller 0 +d 10de0060 nForce2 ISA Bridge 0 +s 10de0060104380ad A7N8X Mainboard 0 +d 10de0064 nForce2 SMBus (MCP) 0 +d 10de0065 nForce2 IDE 0 +d 10de0066 nForce2 Ethernet Controller 0 +s 10de0066104380a7 A7N8X Mainboard onboard nForce2 Ethernet 0 +d 10de0067 nForce2 USB Controller 0 +s 10de006710430c11 A7N8X Mainboard 0 +d 10de0068 nForce2 USB Controller 0 +s 10de006810430c11 A7N8X Mainboard 0 +d 10de006a nForce2 AC97 Audio Controler (MCP) 0 +d 10de006b nForce MultiMedia audio [Via VT82C686B] 0 +s 10de006b10de006b nForce2 MCP Audio Processing Unit 0 +d 10de006c nForce2 External PCI Bridge 0 +d 10de006d nForce2 PCI Bridge 0 +d 10de006e nForce2 FireWire (IEEE 1394) Controller 0 +d 10de0084 MCP2A SMBus 0 +d 10de0085 MCP2A IDE 0 +d 10de0086 MCP2A Ethernet Controller 0 +d 10de0087 MCP2A USB Controller 0 +d 10de0088 MCP2A USB Controller 0 +d 10de008a MCP2S AC'97 Audio Controller 0 +d 10de008b MCP2A PCI Bridge 0 +d 10de008c MCP2A Ethernet Controller 0 +d 10de008e nForce2 Serial ATA Controller 0 +d 10de00a0 NV5 [Aladdin TNT2] 0 +s 10de00a014af5810 Maxi Gamer Xentor 0 +d 10de00c0 NV41.0 0 +d 10de00c1 NV41.1 0 +d 10de00c2 NV41.2 0 +d 10de00c8 NV41.8 0 +d 10de00ce NV41GL 0 +d 10de00d0 nForce3 LPC Bridge 0 +d 10de00d1 nForce3 Host Bridge 0 +d 10de00d2 nForce3 AGP Bridge 0 +d 10de00d3 CK804 Memory Controller 0 +d 10de00d4 nForce3 SMBus 0 +d 10de00d5 nForce3 IDE 0 +d 10de00d6 nForce3 Ethernet 0 +d 10de00d7 nForce3 USB 1.1 0 +d 10de00d8 nForce3 USB 2.0 0 +d 10de00da nForce3 Audio 0 +d 10de00dd nForce3 PCI Bridge 0 +d 10de00df CK8S Ethernet Controller 0 +d 10de00e1 nForce3 250Gb Host Bridge 0 +d 10de00e2 nForce3 250Gb AGP Host to PCI Bridge 0 +d 10de00e3 CK8S Serial ATA Controller (v2.5) 0 +d 10de00e4 nForce 250Gb PCI System Management 0 +d 10de00e5 CK8S Parallel ATA Controller (v2.5) 0 +d 10de00e6 CK8S Ethernet Controller 0 +d 10de00e7 CK8S USB Controller 0 +d 10de00e8 CK8S USB Controller 0 +d 10de00ea nForce3 250Gb AC'97 Audio Controller 0 +d 10de00ed nForce3 250Gb PCI-to-PCI Bridge 0 +d 10de00ee CK8S Serial ATA Controller (v2.5) 0 +d 10de00f0 NV40 [GeForce 6800/GeForce 6800 Ultra] 0 +d 10de00f1 NV43 [GeForce 6600/GeForce 6600 GT] 0 +d 10de00f2 NV43 [GeForce 6600 GT] 0 +d 10de00f8 NV45GL [Quadro FX 3400] 0 +d 10de00f9 NV40 [GeForce 6800 Ultra] 0 +d 10de00fa NV36 [GeForce PCX 5750] 0 +d 10de00fb NV35 [GeForce PCX 5900] 0 +d 10de00fc NV37GL [Quadro FX 330/GeForce PCX 5300] 0 +d 10de00fd NV37GL [Quadro FX 330] 0 +d 10de00fe NV38GL [Quadro FX 1300] 0 +d 10de00ff NV18 [GeForce PCX 4300] 0 +d 10de0100 NV10 [GeForce 256 SDR] 0 +s 10de010010430200 AGP-V6600 SGRAM 0 +s 10de010010430201 AGP-V6600 SDRAM 0 +s 10de010010434008 AGP-V6600 SGRAM 0 +s 10de010010434009 AGP-V6600 SDRAM 0 +s 10de01001102102d CT6941 GeForce 256 0 +s 10de010014af5022 3D Prophet SE 0 +d 10de0101 NV10DDR [GeForce 256 DDR] 0 +s 10de010110430202 AGP-V6800 DDR 0 +s 10de01011043400a AGP-V6800 DDR SGRAM 0 +s 10de01011043400b AGP-V6800 DDR SDRAM 0 +s 10de0101107d2822 WinFast GeForce 256 0 +s 10de01011102102e CT6971 GeForce 256 DDR 0 +s 10de010114af5021 3D Prophet DDR-DVI 0 +d 10de0103 NV10GL [Quadro] 0 +d 10de0110 NV11 [GeForce2 MX/MX 400] 0 +s 10de011010434015 AGP-V7100 Pro 0 +s 10de011010434031 V7100 Pro with TV output 0 +s 10de011010de0091 Dell OEM GeForce 2 MX 400 0 +s 10de011014628817 MSI GeForce2 MX400 Pro32S [MS-8817] 0 +s 10de011014af7102 3D Prophet II MX 0 +s 10de011014af7103 3D Prophet II MX Dual-Display 0 +d 10de0111 NV11DDR [GeForce2 MX 100 DDR/200 DDR] 0 +d 10de0112 NV11 [GeForce2 Go] 0 +d 10de0113 NV11GL [Quadro2 MXR/EX] 0 +d 10de0150 NV15 [GeForce2 GTS/Pro] 0 +s 10de015010434016 V7700 AGP Video Card 0 +s 10de0150107d2840 WinFast GeForce2 GTS with TV output 0 +s 10de0150107d2842 WinFast GeForce 2 Pro 0 +s 10de015014628831 Creative GeForce2 Pro 0 +d 10de0151 NV15DDR [GeForce2 Ti] 0 +s 10de01511043405f V7700Ti 0 +s 10de015114625506 Creative 3D Blaster Geforce2 Titanium 0 +d 10de0152 NV15BR [GeForce2 Ultra, Bladerunner] 0 +s 10de015210480c56 GLADIAC Ultra 0 +d 10de0153 NV15GL [Quadro2 Pro] 0 +d 10de0170 NV17 [GeForce4 MX 460] 0 +d 10de0171 NV17 [GeForce4 MX 440] 0 +s 10de017110b00002 Gainward Pro/600 TV 0 +s 10de017114628661 G4MX440-VTP 0 +s 10de017114628730 MX440SES-T (MS-8873) 0 +s 10de0171147b8f00 Abit Siluro GeForce4MX440 0 +d 10de0172 NV17 [GeForce4 MX 420] 0 +d 10de0173 NV17 [GeForce4 MX 440-SE] 0 +d 10de0174 NV17 [GeForce4 440 Go] 0 +d 10de0175 NV17 [GeForce4 420 Go] 0 +d 10de0176 NV17 [GeForce4 420 Go 32M] 0 +s 10de01764c531090 Cx9 / Vx9 mainboard 0 +d 10de0177 NV17 [GeForce4 460 Go] 0 +d 10de0178 NV17GL [Quadro4 550 XGL] 0 +d 10de0179 NV17 [GeForce4 440 Go 64M] 0 +s 10de017910de0179 GeForce4 MX (Mac) 0 +d 10de017a NV17GL [Quadro4 200/400 NVS] 0 +d 10de017b NV17GL [Quadro4 550 XGL] 0 +d 10de017c NV17GL [Quadro4 550 GoGL] 0 +d 10de017d NV17 [GeForce4 410 Go 16M] 0 +d 10de0181 NV18 [GeForce4 MX 440 AGP 8x] 0 +s 10de01811043806f V9180 Magic 0 +s 10de018114628880 MS-StarForce GeForce4 MX 440 with AGP8X 0 +s 10de018114628900 MS-8890 GeForce 4 MX440 AGP8X 0 +s 10de018114629350 MSI Geforce4 MX T8X with AGP8X 0 +s 10de0181147b8f0d Siluro GF4 MX-8X 0 +d 10de0182 NV18 [GeForce4 MX 440SE AGP 8x] 0 +d 10de0183 NV18 [GeForce4 MX 420 AGP 8x] 0 +d 10de0185 NV18 [GeForce4 MX 4000 AGP 8x] 0 +d 10de0186 NV18M [GeForce4 448 Go] 0 +d 10de0187 NV18M [GeForce4 488 Go] 0 +d 10de0188 NV18GL [Quadro4 580 XGL] 0 +d 10de018a NV18GL [Quadro4 NVS AGP 8x] 0 +d 10de018b NV18GL [Quadro4 380 XGL] 0 +d 10de018d NV18M [GeForce4 448 Go] 0 +d 10de01a0 NVCrush11 [GeForce2 MX Integrated Graphics] 0 +d 10de01a4 nForce CPU bridge 0 +d 10de01ab nForce 420 Memory Controller (DDR) 0 +d 10de01ac nForce 220/420 Memory Controller 0 +d 10de01ad nForce 220/420 Memory Controller 0 +d 10de01b0 nForce Audio 0 +d 10de01b1 nForce Audio 0 +d 10de01b2 nForce ISA Bridge 0 +d 10de01b4 nForce PCI System Management 0 +d 10de01b7 nForce AGP to PCI Bridge 0 +d 10de01b8 nForce PCI-to-PCI bridge 0 +d 10de01bc nForce IDE 0 +d 10de01c1 nForce AC'97 Modem Controller 0 +d 10de01c2 nForce USB Controller 0 +d 10de01c3 nForce Ethernet Controller 0 +d 10de01e0 nForce2 AGP (different version?) 0 +d 10de01e8 nForce2 AGP 0 +d 10de01ea nForce2 Memory Controller 0 0 +d 10de01eb nForce2 Memory Controller 1 0 +d 10de01ec nForce2 Memory Controller 2 0 +d 10de01ed nForce2 Memory Controller 3 0 +d 10de01ee nForce2 Memory Controller 4 0 +d 10de01ef nForce2 Memory Controller 5 0 +d 10de01f0 NV18 [GeForce4 MX - nForce GPU] 0 +d 10de0200 NV20 [GeForce3] 0 +s 10de02001043402f AGP-V8200 DDR 0 +d 10de0201 NV20 [GeForce3 Ti 200] 0 +d 10de0202 NV20 [GeForce3 Ti 500] 0 +s 10de02021043405b V8200 T5 0 +s 10de02021545002f Xtasy 6964 0 +d 10de0203 NV20DCC [Quadro DCC] 0 +d 10de0250 NV25 [GeForce4 Ti 4600] 0 +d 10de0251 NV25 [GeForce4 Ti 4400] 0 +s 10de025110438023 v8440 GeForce 4 Ti4400 0 +d 10de0252 NV25 [GeForce4 Ti] 0 +d 10de0253 NV25 [GeForce4 Ti 4200] 0 +s 10de0253107d2896 WinFast A250 LE TD (Dual VGA/TV-out/DVI) 0 +s 10de0253147b8f09 Siluro (Dual VGA/TV-out/DVI) 0 +d 10de0258 NV25GL [Quadro4 900 XGL] 0 +d 10de0259 NV25GL [Quadro4 750 XGL] 0 +d 10de025b NV25GL [Quadro4 700 XGL] 0 +d 10de0280 NV28 [GeForce4 Ti 4800] 0 +d 10de0281 NV28 [GeForce4 Ti 4200 AGP 8x] 0 +d 10de0282 NV28 [GeForce4 Ti 4800 SE] 0 +d 10de0286 NV28 [GeForce4 Ti 4200 Go AGP 8x] 0 +d 10de0288 NV28GL [Quadro4 980 XGL] 0 +d 10de0289 NV28GL [Quadro4 780 XGL] 0 +d 10de028c NV28GLM [Quadro4 700 GoGL] 0 +d 10de0300 NV30 [GeForce FX] 0 +d 10de0301 NV30 [GeForce FX 5800 Ultra] 0 +d 10de0302 NV30 [GeForce FX 5800] 0 +d 10de0308 NV30GL [Quadro FX 2000] 0 +d 10de0309 NV30GL [Quadro FX 1000] 0 +d 10de0311 NV31 [GeForce FX 5600 Ultra] 0 +d 10de0312 NV31 [GeForce FX 5600] 0 +d 10de0313 NV31 0 +d 10de0314 NV31 [GeForce FX 5600XT] 0 +s 10de03141043814a V9560XT/TD 0 +d 10de0316 NV31 0 +d 10de0317 NV31 0 +d 10de031a NV31M [GeForce FX Go 5600] 0 +d 10de031b NV31M [GeForce FX Go5650] 0 +d 10de031c NVIDIA Quadro FX 700 Go 0 +d 10de031d NV31 0 +d 10de031e NV31 0 +d 10de031f NV31 0 +d 10de0320 NV34 [GeForce FX 5200] 0 +d 10de0321 NV34 [GeForce FX 5200 Ultra] 0 +d 10de0322 NV34 [GeForce FX 5200] 0 +s 10de032214629171 MS-8917 (FX5200-T128) 0 +d 10de0323 NV34 [GeForce FX 5200LE] 0 +d 10de0324 NV34M [GeForce FX Go 5200] 0 +s 10de032410718160 MIM2000 0 +d 10de0325 NV34M [GeForce FX Go5250] 0 +d 10de0326 NV34 [GeForce FX 5500] 0 +d 10de0327 NV34 [GeForce FX 5100] 0 +d 10de0328 NV34M [GeForce FX Go 5200] 0 +d 10de0329 NV34M [GeForce FX Go5200] 0 +d 10de032a NV34GL [Quadro NVS 280 PCI] 0 +d 10de032b NV34GL [Quadro FX 500/600 PCI] 0 +d 10de032c NV34GLM [GeForce FX Go 5300] 0 +d 10de032d NV34 [GeForce FX Go5100] 0 +d 10de032f NV34 0 +d 10de0330 NV35 [GeForce FX 5900 Ultra] 0 +d 10de0331 NV35 [GeForce FX 5900] 0 +s 10de033110438145 V9950GE 0 +d 10de0332 NV35 [GeForce FX 5900XT] 0 +d 10de0333 NV38 [GeForce FX 5950 Ultra] 0 +d 10de0334 NV35 [GeForce FX 5900ZT] 0 +d 10de0338 NV35GL [Quadro FX 3000] 0 +d 10de033f NV35GL [Quadro FX 700] 0 +d 10de0341 NV36.1 [GeForce FX 5700 Ultra] 0 +d 10de0342 NV36.2 [GeForce FX 5700] 0 +d 10de0343 NV36 [GeForce FX 5700LE] 0 +d 10de0344 NV36.4 [GeForce FX 5700VE] 0 +d 10de0345 NV36.5 0 +d 10de0347 NV36 [GeForce FX Go5700] 0 +d 10de0348 NV36 [GeForce FX Go5700] 0 +d 10de0349 NV36 0 +d 10de034b NV36 0 +d 10de034c NV36 [Quadro FX Go1000] 0 +d 10de034e NV36GL [Quadro FX 1100] 0 +d 10de034f NV36GL 0 +v 10df Emulex Corporation 0 +d 10df1ae5 LP6000 Fibre Channel Host Adapter 0 +d 10df1ae6 LP 8000 Fibre Channel Host Adapter Alternate ID (JX1:2-3, JX2:1-2) 0 +d 10df1ae7 LP 8000 Fibre Channel Host Adapter Alternate ID (JX1:2-3, JX2:2-3) 0 +d 10dff015 LP1150e 0 +d 10dff085 LP850 Fibre Channel Adapter 0 +d 10dff095 LP952 Fibre Channel Adapter 0 +d 10dff098 LP982 Fibre Channel Adapter 0 +d 10dff0a1 LightPulse Fibre Channel Adapter 0 +d 10dff0a5 LP1050 0 +d 10dff0d5 LP1150 0 +d 10dff100 LP11000e 0 +d 10dff700 LP7000 Fibre Channel Host Adapter 0 +d 10dff701 LP 7000EFibre Channel Host Adapter Alternate ID (JX1:2-3, JX2:1-2) 0 +d 10dff800 LP8000 Fibre Channel Host Adapter 0 +d 10dff801 LP 8000 Fibre Channel Host Adapter Alternate ID (JX1:2-3, JX2:1-2) 0 +d 10dff900 LP9000 Fibre Channel Host Adapter 0 +d 10dff901 LP 9000 Fibre Channel Host Adapter Alternate ID (JX1:2-3, JX2:1-2) 0 +d 10dff980 LP9802 Fibre Channel Adapter 0 +d 10dff981 LP 9802 Fibre Channel Host Adapter Alternate ID 0 +d 10dff982 LP 9802 Fibre Channel Host Adapter Alternate ID 0 +d 10dffa00 LP10000 Fibre Channel Host Adapter 0 +d 10dffa01 LP101 0 +d 10dffb00 LightPulse Fibre Channel Adapter 0 +d 10dffd00 LP11000 0 +v 10e0 Integrated Micro Solutions Inc. 0 +d 10e05026 IMS5026/27/28 0 +d 10e05027 IMS5027 0 +d 10e05028 IMS5028 0 +d 10e08849 IMS8849 0 +d 10e08853 IMS8853 0 +d 10e09128 IMS9128 [Twin turbo 128] 0 +v 10e1 Tekram Technology Co.,Ltd. 0 +d 10e10391 TRM-S1040 0 +s 10e1039110e10391 DC-315U SCSI-3 Host Adapter 0 +d 10e1690c DC-690c 0 +d 10e1dc29 DC-290 0 +v 10e2 Aptix Corporation 0 +v 10e3 Tundra Semiconductor Corp. 0 +d 10e30000 CA91C042 [Universe] 0 +d 10e30860 CA91C860 [QSpan] 0 +d 10e30862 CA91C862A [QSpan-II] 0 +d 10e38260 CA91L8200B [Dual PCI PowerSpan II] 0 +d 10e38261 CA91L8260B [Single PCI PowerSpan II] 0 +v 10e4 Tandem Computers 0 +v 10e5 Micro Industries Corporation 0 +v 10e6 Gainbery Computer Products Inc. 0 +v 10e7 Vadem 0 +v 10e8 Applied Micro Circuits Corp. 0 +d 10e81072 INES GPIB-PCI (AMCC5920 based) 0 +d 10e82011 Q-Motion Video Capture/Edit board 0 +d 10e84750 S5930 [Matchmaker] 0 +d 10e85920 S5920 0 +d 10e88043 LANai4.x [Myrinet LANai interface chip] 0 +d 10e88062 S5933_PARASTATION 0 +d 10e8807d S5933 [Matchmaker] 0 +d 10e88088 Kongsberg Spacetec Format Synchronizer 0 +d 10e88089 Kongsberg Spacetec Serial Output Board 0 +d 10e8809c S5933_HEPC3 0 +d 10e880d7 PCI-9112 0 +d 10e880d9 PCI-9118 0 +d 10e880da PCI-9812 0 +d 10e8811a PCI-IEEE1355-DS-DE Interface 0 +d 10e8814c Fastcom ESCC-PCI (Commtech, Inc.) 0 +d 10e88170 S5933 [Matchmaker] (Chipset Development Tool) 0 +d 10e881e6 Multimedia video controller 0 sold with Roper Scientifc(Photometrics) CoolSnap HQ camera +d 10e88291 Fastcom 232/8-PCI (Commtech, Inc.) 0 +d 10e882c4 Fastcom 422/4-PCI (Commtech, Inc.) 0 +d 10e882c5 Fastcom 422/2-PCI (Commtech, Inc.) 0 +d 10e882c6 Fastcom IG422/1-PCI (Commtech, Inc.) 0 +d 10e882c7 Fastcom IG232/2-PCI (Commtech, Inc.) 0 +d 10e882ca Fastcom 232/4-PCI (Commtech, Inc.) 0 +d 10e882db AJA HDNTV HD SDI Framestore 0 +d 10e882e2 Fastcom DIO24H-PCI (Commtech, Inc.) 0 +d 10e88851 S5933 on Innes Corp FM Radio Capture card 0 +v 10e9 Alps Electric Co., Ltd. 0 +v 10ea Intergraphics Systems 0 +d 10ea1680 IGA-1680 0 +d 10ea1682 IGA-1682 0 +d 10ea1683 IGA-1683 0 +d 10ea2000 CyberPro 2000 0 +d 10ea2010 CyberPro 2000A 0 +d 10ea5000 CyberPro 5000 0 +d 10ea5050 CyberPro 5050 0 +d 10ea5202 CyberPro 5202 0 +d 10ea5252 CyberPro5252 0 CyberPro5202 Audio Function +v 10eb Artists Graphics 0 +d 10eb0101 3GA 0 +d 10eb8111 Twist3 Frame Grabber 0 +v 10ec Realtek Semiconductor Co., Ltd. 0 +d 10ec8029 RTL-8029(AS) 0 +s 10ec802910b82011 EZ-Card (SMC1208) 0 +s 10ec802910ec8029 RTL-8029(AS) 0 +s 10ec802911131208 EN1208 0 +s 10ec802911860300 DE-528 0 +s 10ec802912592400 AT-2400 0 +d 10ec8129 RTL-8129 0 +s 10ec812910ec8129 RT8129 Fast Ethernet Adapter 0 +d 10ec8138 RT8139 (B/C) Cardbus Fast Ethernet Adapter 0 +s 10ec813810ec8138 RT8139 (B/C) Fast Ethernet Adapter 0 +d 10ec8139 RTL-8139/8139C/8139C+ 0 +s 10ec81390357000a TTP-Monitoring Card V2.0 0 +s 10ec81391025005a TravelMate 290 0 +s 10ec813910258920 ALN-325 0 +s 10ec813910258921 ALN-325 0 +s 10ec813910718160 MIM2000 0 +s 10ec813910bd0320 EP-320X-R 0 +s 10ec813910ec8139 RT8139 0 +s 10ec81391113ec01 FNC-0107TX 0 +s 10ec813911861300 DFE-538TX 0 +s 10ec813911861320 SN5200 0 +s 10ec813911868139 DRN-32TX 0 +s 10ec813911f68139 FN22-3(A) LinxPRO Ethernet Adapter 0 +s 10ec813912592500 AT-2500TX 0 +s 10ec813912592503 AT-2500TX/ACPI 0 +s 10ec81391429d010 ND010 0 +s 10ec813914329130 EN-9130TX 0 +s 10ec813914368139 RT8139 0 +s 10ec81391458e000 GA-7VM400M/7VT600 Motherboard 0 +s 10ec8139146c1439 FE-1439TX 0 +s 10ec813914896001 GF100TXRII 0 +s 10ec813914896002 GF100TXRA 0 +s 10ec8139149c139a LFE-8139ATX 0 +s 10ec8139149c8139 LFE-8139TX 0 +s 10ec813914cb0200 LNR-100 Family 10/100 Base-TX Ethernet 0 +s 10ec813917995000 F5D5000 PCI Card/Desktop Network PCI Card 0 +s 10ec813926460001 EtheRx 0 +s 10ec81398e2e7000 KF-230TX 0 +s 10ec81398e2e7100 KF-230TX/2 0 +s 10ec8139a0a00007 ALN-325C 0 +d 10ec8169 RTL-8169 Gigabit Ethernet 0 +s 10ec81691259c107 CG-LAPCIGT 0 +s 10ec81691371434e ProG-2000L 0 +s 10ec81691458e000 GA-K8VT800 Pro Motherboard 0 +s 10ec81691462702c K8T NEO 2 motherboard 0 +d 10ec8180 RTL8180L 802.11b MAC 0 +d 10ec8197 SmartLAN56 56K Modem 0 +v 10ed Ascii Corporation 0 +d 10ed7310 V7310 0 +v 10ee Xilinx Corporation 0 +d 10ee3fc0 RME Digi96 0 +d 10ee3fc1 RME Digi96/8 0 +d 10ee3fc2 RME Digi96/8 Pro 0 +d 10ee3fc3 RME Digi96/8 Pad 0 +d 10ee3fc4 RME Digi9652 (Hammerfall) 0 +d 10ee3fc5 RME Hammerfall DSP 0 +d 10ee3fc6 RME Hammerfall DSP MADI 0 +d 10ee8381 Ellips Santos Frame Grabber 0 +v 10ef Racore Computer Products, Inc. 0 +d 10ef8154 M815x Token Ring Adapter 0 +v 10f0 Peritek Corporation 0 +v 10f1 Tyan Computer 0 +v 10f2 Achme Computer, Inc. 0 +v 10f3 Alaris, Inc. 0 +v 10f4 S-MOS Systems, Inc. 0 +v 10f5 NKK Corporation 0 +d 10f5a001 NDR4000 [NR4600 Bridge] 0 +v 10f6 Creative Electronic Systems SA 0 +v 10f7 Matsushita Electric Industrial Co., Ltd. 0 +v 10f8 Altos India Ltd 0 +v 10f9 PC Direct 0 +v 10fa Truevision 0 +d 10fa000c TARGA 1000 0 +v 10fb Thesys Gesellschaft für Mikroelektronik mbH 0 +d 10fb186f TH 6255 0 +v 10fc I-O Data Device, Inc. 0 +d 10fc0003 Cardbus IDE Controller 0 What's in the cardbus end of a Sony ACR-A01 card, comes with newer Vaio CD-RW drives +d 10fc0005 Cardbus SCSI CBSC II 0 +v 10fd Soyo Computer, Inc 0 +v 10fe Fast Multimedia AG 0 +v 10ff NCube 0 +v 1100 Jazz Multimedia 0 +v 1101 Initio Corporation 0 +d 11011060 INI-A100U2W 0 +d 11019100 INI-9100/9100W 0 +d 11019400 INI-940 0 +d 11019401 INI-950 0 +d 11019500 360P 0 +d 11019502 Initio INI-9100UW Ultra Wide SCSI Controller INIC-950P chip 0 +v 1102 Creative Labs 0 +d 11020002 SB Live! EMU10k1 0 +s 1102000211020020 CT4850 SBLive! Value 0 +s 1102000211020021 CT4620 SBLive! 0 +s 110200021102002f SBLive! mainboard implementation 0 +s 1102000211024001 E-mu APS 0 +s 1102000211028022 CT4780 SBLive! Value 0 +s 1102000211028023 CT4790 SoundBlaster PCI512 0 +s 1102000211028024 CT4760 SBLive! 0 +s 1102000211028025 SBLive! Mainboard Implementation 0 +s 1102000211028026 CT4830 SBLive! Value 0 +s 1102000211028027 CT4832 SBLive! Value 0 +s 1102000211028028 CT4760 SBLive! OEM version 0 +s 1102000211028031 CT4831 SBLive! Value 0 +s 1102000211028040 CT4760 SBLive! 0 +s 1102000211028051 CT4850 SBLive! Value 0 +s 1102000211028061 SBLive! Player 5.1 0 +s 1102000211028064 SB Live! 5.1 Model SB0100 0 +s 1102000211028065 SBLive! 5.1 Digital Model SB0220 0 +s 1102000211028067 SBLive! 5.1 eMicro 28028 0 +d 11020004 SB Audigy 0 +s 1102000411020051 SB0090 Audigy Player 0 +s 1102000411020053 SB0090 Audigy Player/OEM 0 +s 1102000411020058 SB0090 Audigy Player/OEM 0 +s 1102000411022002 SB Audigy 2 ZS (SB0350) 0 +d 11020006 [SB Live! Value] EMU10k1X 0 +d 11020007 SB Audigy LS 0 +s 1102000711021001 SB0310 Audigy LS 0 +s 1102000711021002 SB0312 Audigy LS 0 +d 11020008 SB0400 Audigy2 Value 0 +d 11024001 SB Audigy FireWire Port 0 +s 1102400111020010 SB Audigy FireWire Port 0 +d 11027002 SB Live! MIDI/Game Port 0 +s 1102700211020020 Gameport Joystick 0 +d 11027003 SB Audigy MIDI/Game port 0 +s 1102700311020040 SB Audigy MIDI/Game Port 0 +d 11027004 [SB Live! Value] Input device controller 0 +d 11027005 SB Audigy LS MIDI/Game port 0 +s 1102700511021001 SB0310 Audigy LS MIDI/Game port 0 +s 1102700511021002 SB0312 Audigy LS MIDI/Game port 0 +d 11028064 SB0100 [SBLive! 5.1 OEM] 0 +d 11028938 Ectiva EV1938 0 +v 1103 Triones Technologies, Inc. 0 +d 11030003 HPT343 0 +d 11030004 HPT366/368/370/370A/372 0 Revisions: 01=HPT366, 03=HPT370, 04=HPT370A, 05=HPT372 +s 1103000411030001 HPT370A 0 +s 1103000411030003 HPT343 / HPT345 / HPT363 UDMA33 0 +s 1103000411030004 HPT366 UDMA66 (r1) / HPT368 UDMA66 (r2) / HPT370 UDMA100 (r3) / HPT370 UDMA100 RAID (r4) 0 +s 1103000411030005 HPT370 UDMA100 0 +s 1103000411030006 HPT302 0 +s 1103000411030007 HPT371 UDMA133 0 +s 1103000411030008 HPT374 UDMA/ATA133 RAID Controller 0 +d 11030005 HPT372A 0 +d 11030006 HPT302 0 +d 11030007 HPT371 0 +d 11030008 HPT374 0 +d 11030009 HPT372N 0 +v 1104 RasterOps Corp. 0 +v 1105 Sigma Designs, Inc. 0 +d 11051105 REALmagic Xcard MPEG 1/2/3/4 DVD Decoder 0 +d 11058300 REALmagic Hollywood Plus DVD Decoder 0 +d 11058400 EM840x REALmagic DVD/MPEG-2 Audio/Video Decoder 0 +d 11058401 EM8401 REALmagic DVD/MPEG-2 A/V Decoder 0 +d 11058470 EM8470 REALmagic DVD/MPEG-4 A/V Decoder 0 +d 11058471 EM8471 REALmagic DVD/MPEG-4 A/V Decoder 0 +d 11058475 EM8475 REALmagic DVD/MPEG-4 A/V Decoder 0 +d 11058476 EM8476 REALmagic DVD/MPEG-4 A/V Decoder 0 +d 11058485 EM8485 REALmagic DVD/MPEG-4 A/V Decoder 0 +d 11058486 EM8486 REALmagic DVD/MPEG-4 A/V Decoder 0 +v 1106 VIA Technologies, Inc. 0 +d 11060102 Embedded VIA Ethernet Controller 0 +d 11060130 VT6305 1394.A Controller 0 +d 11060305 VT8363/8365 [KT133/KM133] 0 +s 1106030510438033 A7V Mainboard 0 +s 110603051043803e A7V-E Mainboard 0 +s 1106030510438042 A7V133/A7V133-C Mainboard 0 +s 11060305147ba401 KT7/KT7-RAID/KT7A/KT7A-RAID Mainboard 0 +d 11060391 VT8371 [KX133] 0 +d 11060501 VT8501 [Apollo MVP4] 0 +d 11060505 VT82C505 0 +d 11060561 VT82C576MV 0 Shares chip with :0576. The VT82C576M has :1571 instead of :0561. +d 11060571 VT82C586A/B/VT82C686/A/B/VT823x/A/C PIPC Bus Master IDE 0 +s 1106057110190985 P6VXA Motherboard 0 +s 1106057110190a81 L7VTA v1.0 Motherboard (KT400-8235) 0 +s 1106057110438052 VT8233A Bus Master ATA100/66/33 IDE 0 +s 110605711043808c A7V8X motherboard 0 +s 11060571104380a1 A7V8X-X motherboard rev. 1.01 0 +s 11060571104380ed A7V600 motherboard 0 +s 1106057111060571 VT82C586/B/VT82C686/A/B/VT8233/A/C/VT8235 PIPC Bus Master IDE 0 +s 1106057111790001 Magnia Z310 0 +s 110605711297f641 FX41 motherboard 0 +s 1106057114585002 GA-7VAX Mainboard 0 +s 1106057114627020 K8T NEO 2 motherboard 0 +s 11060571147b1407 KV8-MAX3 motherboard 0 +s 1106057118490571 K7VT2 motherboard 0 +d 11060576 VT82C576 3V [Apollo Master] 0 +d 11060585 VT82C585VP [Apollo VP1/VPX] 0 +d 11060586 VT82C586/A/B PCI-to-ISA [Apollo VP] 0 +s 1106058611060000 MVP3 ISA Bridge 0 +d 11060595 VT82C595 [Apollo VP2] 0 +d 11060596 VT82C596 ISA [Mobile South] 0 +s 1106059611060000 VT82C596/A/B PCI to ISA Bridge 0 +s 1106059614580596 VT82C596/A/B PCI to ISA Bridge 0 +d 11060597 VT82C597 [Apollo VP3] 0 +d 11060598 VT82C598 [Apollo MVP3] 0 +d 11060601 VT8601 [Apollo ProMedia] 0 +d 11060605 VT8605 [ProSavage PM133] 0 +s 110606051043802c CUV4X mainboard 0 +d 11060680 VT82C680 [Apollo P6] 0 +d 11060686 VT82C686 [Apollo Super South] 0 +s 1106068610190985 P6VXA Motherboard 0 +s 110606861043802c CUV4X mainboard 0 +s 1106068610438033 A7V Mainboard 0 +s 110606861043803e A7V-E Mainboard 0 +s 1106068610438040 A7M266 Mainboard 0 +s 1106068610438042 A7V133/A7V133-C Mainboard 0 +s 1106068611060000 VT82C686/A PCI to ISA Bridge 0 +s 1106068611060686 VT82C686/A PCI to ISA Bridge 0 +s 1106068611790001 Magnia Z310 0 +s 11060686147ba702 KG7-Lite Mainboard 0 +d 11060691 VT82C693A/694x [Apollo PRO133x] 0 +s 1106069110190985 P6VXA Motherboard 0 +s 1106069111790001 Magnia Z310 0 +s 1106069114580691 VT82C691 Apollo Pro System Controller 0 +d 11060693 VT82C693 [Apollo Pro Plus] 0 +d 11060698 VT82C693A [Apollo Pro133 AGP] 0 +d 11060926 VT82C926 [Amazon] 0 +d 11061000 VT82C570MV 0 +d 11061106 VT82C570MV 0 +d 11061571 VT82C576M/VT82C586 0 +d 11061595 VT82C595/97 [Apollo VP2/97] 0 +d 11063022 CLE266 0 +d 11063038 VT82xxxxx UHCI USB 1.1 Controller 0 This is *not* USB 2.0 as the existing entry suggests +s 1106303809251234 USB Controller 0 +s 1106303810190985 P6VXA Motherboard 0 +s 1106303810190a81 L7VTA v1.0 Motherboard (KT400-8235) 0 +s 110630381043808c VT6202 USB2.0 4 port controller 0 +s 11063038104380a1 A7V8X-X motherboard 0 +s 11063038104380ed A7V600 motherboard 0 +s 1106303811790001 Magnia Z310 0 +s 1106303814585004 GA-7VAX Mainboard 0 +s 1106303814627020 K8T NEO 2 motherboard 0 +s 11063038147b1407 KV8-MAX3 motherboard 0 +d 11063040 VT82C586B ACPI 0 +d 11063043 VT86C100A [Rhine] 0 +s 1106304310bd0000 VT86C100A Fast Ethernet Adapter 0 +s 1106304311060100 VT86C100A Fast Ethernet Adapter 0 +s 1106304311861400 DFE-530TX rev A 0 +d 11063044 IEEE 1394 Host Controller 0 +s 110630441025005a TravelMate 290 0 +s 1106304414581000 GA-7VT600-1394 Motherboard 0 +s 110630441462702d K8T NEO 2 motherboard 0 +d 11063050 VT82C596 Power Management 0 +d 11063051 VT82C596 Power Management 0 +d 11063053 VT6105M [Rhine-III] 0 +d 11063057 VT82C686 [Apollo Super ACPI] 0 +s 1106305710190985 P6VXA Motherboard 0 +s 1106305710438033 A7V Mainboard 0 +s 110630571043803e A7V-E Mainboard 0 +s 1106305710438040 A7M266 Mainboard 0 +s 1106305710438042 A7V133/A7V133-C Mainboard 0 +s 1106305711790001 Magnia Z310 0 +d 11063058 VT82C686 AC97 Audio Controller 0 +s 110630580e110097 SoundMax Digital Integrated Audio 0 +s 110630580e11b194 Soundmax integrated digital audio 0 +s 1106305810190985 P6VXA Motherboard 0 +s 1106305810431106 A7V133/A7V133-C Mainboard 0 +s 1106305811064511 Onboard Audio on EP7KXA 0 +s 1106305814587600 Onboard Audio 0 +s 1106305814623091 MS-6309 Onboard Audio 0 +s 1106305814623300 MS-6330 Onboard Audio 0 +s 1106305815dd7609 Onboard Audio 0 +d 11063059 VT8233/A/8235/8237 AC97 Audio Controller 0 +s 1106305910190a81 L7VTA v1.0 Motherboard (KT400-8235) 0 +s 1106305910438095 A7V8X Motherboard (Realtek ALC650 codec) 0 +s 11063059104380a1 A7V8X-X Motherboard 0 +s 11063059104380b0 A7V600 motherboard (ADI AD1980 codec [SoundMAX]) 0 +s 1106305911063059 L7VMM2 Motherboard 0 +s 1106305911064161 K7VT2 motherboard 0 +s 110630591297c160 FX41 motherboard (Realtek ALC650 codec) 0 +s 110630591458a002 GA-7VAX Onboard Audio (Realtek ALC650) 0 +s 1106305914620080 K8T NEO 2 motherboard 0 +s 1106305914623800 KT266 onboard audio 0 +s 11063059147b1407 KV8-MAX3 motherboard 0 +d 11063065 VT6102 [Rhine-II] 0 +s 11063065104380a1 A7V8X-X Motherboard 0 +s 1106306511060102 VT6102 [Rhine II] Embeded Ethernet Controller on VT8235 0 +s 1106306511861400 DFE-530TX rev A 0 +s 1106306511861401 DFE-530TX rev B 0 +s 1106306513b91421 LD-10/100AL PCI Fast Ethernet Adapter (rev.B) 0 +d 11063068 AC'97 Modem Controller 0 This hosts more than just the Intel 537 codec, it also hosts PCtel (SIL33) and SmartLink (SIL34) codecs +s 110630681462309e MS-6309 Saturn Motherboard 0 +d 11063074 VT8233 PCI to ISA Bridge 0 +s 1106307410438052 VT8233A 0 +d 11063091 VT8633 [Apollo Pro266] 0 +d 11063099 VT8366/A/7 [Apollo KT266/A/333] 0 +s 1106309910438064 A7V266-E Mainboard 0 +s 110630991043807f A7V333 Mainboard 0 +s 1106309918493099 K7VT2 motherboard 0 +d 11063101 VT8653 Host Bridge 0 +d 11063102 VT8662 Host Bridge 0 +d 11063103 VT8615 Host Bridge 0 +d 11063104 USB 2.0 0 +s 1106310410190a81 L7VTA v1.0 Motherboard (KT400-8235) 0 +s 110631041043808c A7V8X motherboard 0 +s 11063104104380a1 A7V8X-X motherboard rev 1.01 0 +s 11063104104380ed A7V600 motherboard 0 +s 110631041297f641 FX41 motherboard 0 +s 1106310414585004 GA-7VAX Mainboard 0 +s 1106310414627020 K8T NEO 2 motherboard 0 +s 11063104147b1407 KV8-MAX3 motherboard 0 +d 11063106 VT6105 [Rhine-III] 0 +s 1106310611861403 DFE-530TX rev C 0 +d 11063108 S3 Unichrome Pro VGA Adapter 0 +d 11063109 VT8233C PCI to ISA Bridge 0 +d 11063112 VT8361 [KLE133] Host Bridge 0 +d 11063116 VT8375 [KM266/KL266] Host Bridge 0 +s 110631161297f641 FX41 motherboard 0 +d 11063118 S3 Unichrome Pro VGA Adapter 0 +d 11063119 VT6120/VT6121/VT6122 Gigabit Ethernet Adapter 0 +d 11063122 VT8623 [Apollo CLE266] integrated CastleRock graphics 0 found on EPIA M6000/9000 mainboard +d 11063123 VT8623 [Apollo CLE266] 0 found on EPIA M6000/9000 mainboard +d 11063128 VT8753 [P4X266 AGP] 0 +d 11063133 VT3133 Host Bridge 0 +d 11063147 VT8233A ISA Bridge 0 +d 11063148 P4M266 Host Bridge 0 +d 11063149 VIA VT6420 SATA RAID Controller 0 +s 11063149104380ed A7V600 motherboard 0 +s 110631491458b003 GA-7VM400AM(F) Motherboard 0 +s 1106314914627020 K8T Neo 2 Motherboard 0 +d 11063156 P/KN266 Host Bridge 0 +d 11063164 VT6410 ATA133 RAID controller 0 on ASUS P4P800 +d 11063168 VT8374 P4X400 Host Controller/AGP Bridge 0 +d 11063177 VT8235 ISA Bridge 0 +s 1106317710190a81 L7VTA v1.0 Motherboard (KT400-8235) 0 +s 110631771043808c A7V8X motherboard 0 +s 11063177104380a1 A7V8X-X motherboard 0 +s 110631771297f641 FX41 motherboard 0 +s 1106317714585001 GA-7VAX Mainboard 0 +s 1106317718493177 K7VT2 motherboard 0 +d 11063188 VT8385 [K8T800 AGP] Host Bridge 0 +s 11063188147b1407 KV8-MAX3 motherboard 0 +d 11063189 VT8377 [KT400/KT600 AGP] Host Bridge 0 +s 110631891043807f A7V8X motherboard 0 +s 1106318914585000 GA-7VAX Mainboard 0 +d 11063204 K8M800 0 +d 11063205 VT8378 [KM400/A] Chipset Host Bridge 0 +s 1106320514585000 GA-7VM400M Motherboard 0 +d 11063227 VT8237 ISA bridge [KT600/K8T800 South] 0 +s 11063227104380ed A7V600 motherboard 0 +s 1106322711063227 DFI KT600-AL Motherboard 0 +s 1106322714585001 GA-7VT600 Motherboard 0 +s 11063227147b1407 KV8-MAX3 motherboard 0 +d 11064149 VIA VT6420 (ATA133) Controller 0 +d 11065030 VT82C596 ACPI [Apollo PRO] 0 +d 11066100 VT85C100A [Rhine II] 0 +d 11067204 K8M800 0 +d 11067205 VT8378 [S3 UniChrome] Integrated Video 0 S3 Graphics UniChromeâ„¢ 2D/3D Graphics with motion compensation +s 110672051458d000 Gigabyte GA-7VM400(A)M(F) Motherboard 0 +d 11068231 VT8231 [PCI-to-ISA Bridge] 0 +d 11068235 VT8235 ACPI 0 +d 11068305 VT8363/8365 [KT133/KM133 AGP] 0 +d 11068391 VT8371 [KX133 AGP] 0 +d 11068501 VT8501 [Apollo MVP4 AGP] 0 +d 11068596 VT82C596 [Apollo PRO AGP] 0 +d 11068597 VT82C597 [Apollo VP3 AGP] 0 +d 11068598 VT82C598/694x [Apollo MVP3/Pro133x AGP] 0 +s 1106859810190985 P6VXA Motherboard 0 +d 11068601 VT8601 [Apollo ProMedia AGP] 0 +d 11068605 VT8605 [PM133 AGP] 0 +d 11068691 VT82C691 [Apollo Pro] 0 +d 11068693 VT82C693 [Apollo Pro Plus] PCI Bridge 0 +d 1106b091 VT8633 [Apollo Pro266 AGP] 0 +d 1106b099 VT8366/A/7 [Apollo KT266/A/333 AGP] 0 +d 1106b101 VT8653 AGP Bridge 0 +d 1106b102 VT8362 AGP Bridge 0 +d 1106b103 VT8615 AGP Bridge 0 +d 1106b112 VT8361 [KLE133] AGP Bridge 0 +d 1106b168 VT8235 PCI Bridge 0 +d 1106b188 VT8237 PCI bridge [K8T800 South] 0 +s 1106b188147b1407 KV8-MAX3 motherboard 0 +d 1106b198 VT8237 PCI Bridge 0 +d 1106d104 VT8237 Integrated Fast Ethernet Controller 0 32-Bit PCI bus master Ethernet MAC with standard MII interface +v 1107 Stratus Computers 0 +d 11070576 VIA VT82C570MV [Apollo] (Wrong vendor ID!) 0 +v 1108 Proteon, Inc. 0 +d 11080100 p1690plus_AA 0 +d 11080101 p1690plus_AB 0 +d 11080105 P1690Plus 0 +d 11080108 P1690Plus 0 +d 11080138 P1690Plus 0 +d 11080139 P1690Plus 0 +d 1108013c P1690Plus 0 +d 1108013d P1690Plus 0 +v 1109 Cogent Data Technologies, Inc. 0 +d 11091400 EM110TX [EX110TX] 0 +v 110a Siemens Nixdorf AG 0 +d 110a0002 Pirahna 2-port 0 +d 110a0005 Tulip controller, power management, switch extender 0 +d 110a0006 FSC PINC (I/O-APIC) 0 +d 110a0015 FSC Multiprocessor Interrupt Controller 0 +d 110a001d FSC Copernicus Management Controller 0 +d 110a007b FSC Remote Service Controller, mailbox device 0 +d 110a007c FSC Remote Service Controller, shared memory device 0 +d 110a007d FSC Remote Service Controller, SMIC device 0 +d 110a2102 DSCC4 WAN adapter 0 +d 110a2104 Eicon Diva 2.02 compatible passive ISDN card 0 +d 110a3142 SIMATIC NET CP 5613A1 (Profibus Adapter) 0 +d 110a4021 SIMATIC NET CP 5512 (Profibus and MPI Cardbus Adapter) 0 +d 110a4029 SIMATIC NET CP 5613A2 (Profibus Adapter) 0 +d 110a4942 FPGA I-Bus Tracer for MBD 0 +d 110a6120 SZB6120 0 +v 110b Chromatic Research Inc. 0 +d 110b0001 Mpact Media Processor 0 +d 110b0004 Mpact 2 0 +v 110c Mini-Max Technology, Inc. 0 +v 110d Znyx Advanced Systems 0 +v 110e CPU Technology 0 +v 110f Ross Technology 0 +v 1110 Powerhouse Systems 0 +d 11106037 Firepower Powerized SMP I/O ASIC 0 +d 11106073 Firepower Powerized SMP I/O ASIC 0 +v 1111 Santa Cruz Operation 0 +v 1112 Osicom Technologies Inc 0 Also claimed to be RNS or Rockwell International, current PCISIG records list Osicom +d 11122200 FDDI Adapter 0 +d 11122300 Fast Ethernet Adapter 0 +d 11122340 4 Port Fast Ethernet Adapter 0 +d 11122400 ATM Adapter 0 +v 1113 Accton Technology Corporation 0 +d 11131211 SMC2-1211TX 0 +s 11131211103c1207 EN-1207D Fast Ethernet Adapter 0 +s 1113121111131211 EN-1207D Fast Ethernet Adapter 0 +d 11131216 EN-1216 Ethernet Adapter 0 +s 1113121611132242 EN2242 10/100 Ethernet Mini-PCI Card 0 +s 11131216111a1020 SpeedStream 1020 PCI 10/100 Ethernet Adaptor [EN-1207F-TX ?] 0 +d 11131217 EN-1217 Ethernet Adapter 0 +d 11135105 10Mbps Network card 0 +d 11139211 EN-1207D Fast Ethernet Adapter 0 +s 1113921111139211 EN-1207D Fast Ethernet Adapter 0 +d 11139511 21x4x DEC-Tulip compatible Fast Ethernet 0 +d 1113d301 CPWNA100 (Philips wireless PCMCIA) 0 +d 1113ec02 SMC 1244TX v3 0 +v 1114 Atmel Corporation 0 +d 11140506 802.11b Wireless Network Adaptor (at76c506) 0 +v 1115 3D Labs 0 +v 1116 Data Translation 0 +d 11160022 DT3001 0 +d 11160023 DT3002 0 +d 11160024 DT3003 0 +d 11160025 DT3004 0 +d 11160026 DT3005 0 +d 11160027 DT3001-PGL 0 +d 11160028 DT3003-PGL 0 +v 1117 Datacube, Inc 0 +d 11179500 Max-1C SVGA card 0 +d 11179501 Max-1C image processing 0 +v 1118 Berg Electronics 0 +v 1119 ICP Vortex Computersysteme GmbH 0 +d 11190000 GDT 6000/6020/6050 0 +d 11190001 GDT 6000B/6010 0 +d 11190002 GDT 6110/6510 0 +d 11190003 GDT 6120/6520 0 +d 11190004 GDT 6530 0 +d 11190005 GDT 6550 0 +d 11190006 GDT 6117/6517 0 +d 11190007 GDT 6127/6527 0 +d 11190008 GDT 6537 0 +d 11190009 GDT 6557/6557-ECC 0 +d 1119000a GDT 6115/6515 0 +d 1119000b GDT 6125/6525 0 +d 1119000c GDT 6535 0 +d 1119000d GDT 6555 0 +d 11190010 GDT 6115/6515 0 +d 11190011 GDT 6125/6525 0 +d 11190012 GDT 6535 0 +d 11190013 GDT 6555/6555-ECC 0 +d 11190100 GDT 6117RP/6517RP 0 +d 11190101 GDT 6127RP/6527RP 0 +d 11190102 GDT 6537RP 0 +d 11190103 GDT 6557RP 0 +d 11190104 GDT 6111RP/6511RP 0 +d 11190105 GDT 6121RP/6521RP 0 +d 11190110 GDT 6117RD/6517RD 0 +d 11190111 GDT 6127RD/6527RD 0 +d 11190112 GDT 6537RD 0 +d 11190113 GDT 6557RD 0 +d 11190114 GDT 6111RD/6511RD 0 +d 11190115 GDT 6121RD/6521RD 0 +d 11190118 GDT 6118RD/6518RD/6618RD 0 +d 11190119 GDT 6128RD/6528RD/6628RD 0 +d 1119011a GDT 6538RD/6638RD 0 +d 1119011b GDT 6558RD/6658RD 0 +d 11190120 GDT 6117RP2/6517RP2 0 +d 11190121 GDT 6127RP2/6527RP2 0 +d 11190122 GDT 6537RP2 0 +d 11190123 GDT 6557RP2 0 +d 11190124 GDT 6111RP2/6511RP2 0 +d 11190125 GDT 6121RP2/6521RP2 0 +d 11190136 GDT 6113RS/6513RS 0 +d 11190137 GDT 6123RS/6523RS 0 +d 11190138 GDT 6118RS/6518RS/6618RS 0 +d 11190139 GDT 6128RS/6528RS/6628RS 0 +d 1119013a GDT 6538RS/6638RS 0 +d 1119013b GDT 6558RS/6658RS 0 +d 1119013c GDT 6533RS/6633RS 0 +d 1119013d GDT 6543RS/6643RS 0 +d 1119013e GDT 6553RS/6653RS 0 +d 1119013f GDT 6563RS/6663RS 0 +d 11190166 GDT 7113RN/7513RN/7613RN 0 +d 11190167 GDT 7123RN/7523RN/7623RN 0 +d 11190168 GDT 7118RN/7518RN/7518RN 0 +d 11190169 GDT 7128RN/7528RN/7628RN 0 +d 1119016a GDT 7538RN/7638RN 0 +d 1119016b GDT 7558RN/7658RN 0 +d 1119016c GDT 7533RN/7633RN 0 +d 1119016d GDT 7543RN/7643RN 0 +d 1119016e GDT 7553RN/7653RN 0 +d 1119016f GDT 7563RN/7663RN 0 +d 111901d6 GDT 4x13RZ 0 +d 111901d7 GDT 4x23RZ 0 +d 111901f6 GDT 8x13RZ 0 +d 111901f7 GDT 8x23RZ 0 +d 111901fc GDT 8x33RZ 0 +d 111901fd GDT 8x43RZ 0 +d 111901fe GDT 8x53RZ 0 +d 111901ff GDT 8x63RZ 0 +d 11190210 GDT 6519RD/6619RD 0 +d 11190211 GDT 6529RD/6629RD 0 +d 11190260 GDT 7519RN/7619RN 0 +d 11190261 GDT 7529RN/7629RN 0 +d 111902ff GDT MAXRP 0 +d 11190300 GDT NEWRX 0 +v 111a Efficient Networks, Inc 0 +d 111a0000 155P-MF1 (FPGA) 0 +d 111a0002 155P-MF1 (ASIC) 0 +d 111a0003 ENI-25P ATM 0 +s 111a0003111a0000 ENI-25p Miniport ATM Adapter 0 +d 111a0005 SpeedStream (LANAI) 0 +s 111a0005111a0001 ENI-3010 ATM 0 +s 111a0005111a0009 ENI-3060 ADSL (VPI=0) 0 +s 111a0005111a0101 ENI-3010 ATM 0 +s 111a0005111a0109 ENI-3060CO ADSL (VPI=0) 0 +s 111a0005111a0809 ENI-3060 ADSL (VPI=0 or 8) 0 +s 111a0005111a0909 ENI-3060CO ADSL (VPI=0 or 8) 0 +s 111a0005111a0a09 ENI-3060 ADSL (VPI=<0..15>) 0 +d 111a0007 SpeedStream ADSL 0 +s 111a0007111a1001 ENI-3061 ADSL [ASIC] 0 +d 111a1203 SpeedStream 1023 Wireless PCI Adapter 0 +v 111b Teledyne Electronic Systems 0 +v 111c Tricord Systems Inc. 0 +d 111c0001 Powerbis Bridge 0 +v 111d Integrated Device Technology, Inc. 0 +d 111d0001 IDT77201/77211 155Mbps ATM SAR Controller [NICStAR] 0 +d 111d0003 IDT77222/77252 155Mbps ATM MICRO ABR SAR Controller 0 +d 111d0004 IDT77V252 155Mbps ATM MICRO ABR SAR Controller 0 +d 111d0005 IDT77V222 155Mbps ATM MICRO ABR SAR Controller 0 +v 111e Eldec 0 +v 111f Precision Digital Images 0 +d 111f4a47 Precision MX Video engine interface 0 +d 111f5243 Frame capture bus interface 0 +v 1120 EMC Corporation 0 +v 1121 Zilog 0 +v 1122 Multi-tech Systems, Inc. 0 +v 1123 Excellent Design, Inc. 0 +v 1124 Leutron Vision AG 0 +v 1125 Eurocore 0 +v 1126 Vigra 0 +v 1127 FORE Systems Inc 0 +d 11270200 ForeRunner PCA-200 ATM 0 +d 11270210 PCA-200PC 0 +d 11270250 ATM 0 +d 11270300 ForeRunner PCA-200EPC ATM 0 +d 11270310 ATM 0 +d 11270400 ForeRunnerHE ATM Adapter 0 +s 1127040011270400 ForeRunnerHE ATM 0 +v 1129 Firmworks 0 +v 112a Hermes Electronics Company, Ltd. 0 +v 112b Linotype - Hell AG 0 +v 112c Zenith Data Systems 0 +v 112d Ravicad 0 +v 112e Infomedia Microelectronics Inc. 0 +v 112f Imaging Technology Inc 0 +d 112f0000 MVC IC-PCI 0 +d 112f0001 MVC IM-PCI Video frame grabber/processor 0 +v 1130 Computervision 0 +v 1131 Philips Semiconductors 0 +d 11311561 USB 1.1 Host Controller 0 +d 11311562 USB 2.0 Host Controller 0 +d 11313400 SmartPCI56(UCB1500) 56K Modem 0 +d 11315400 TriMedia TM1000/1100 0 +d 11315402 TriMedia TM-1300 0 +d 11317130 SAA7130 Video Broadcast Decoder 0 +s 1131713051680138 LiveView FlyVideo 2000 0 +d 11317133 SAA713X Audio+video broadcast decoder 0 +s 1131713351680138 LifeView FlyVideo 3000 0 +s 1131713351680212 LifeView FlyTV Platinum mini 0 +d 11317134 SAA7134 0 PCI audio and video broadcast decoder (http://www.semiconductors.philips.com/pip/saa7134hl) +d 11317135 SAA7135 Audio+video broadcast decoder 0 +d 11317145 SAA7145 0 +d 11317146 SAA7146 0 +s 11317146110a0000 Fujitsu/Siemens DVB-C card rev1.5 0 +s 11317146110affff Fujitsu/Siemens DVB-C card rev1.5 0 +s 1131714611314f56 KNC1 DVB-S Budget 0 +s 1131714611314f61 Fujitsu-Siemens Activy DVB-S Budget 0 +s 11317146114b2003 DVRaptor Video Edit/Capture Card 0 +s 1131714611bd0006 DV500 Overlay 0 +s 1131714611bd000a DV500 Overlay 0 +s 1131714613c20000 Siemens/Technotrend/Hauppauge DVB card rev1.3 or rev1.5 0 +s 1131714613c20001 Technotrend/Hauppauge DVB card rev1.3 or rev1.6 0 +s 1131714613c20002 Technotrend/Hauppauge DVB card rev2.1 0 +s 1131714613c20003 Technotrend/Hauppauge DVB card rev2.1 0 +s 1131714613c20004 Technotrend/Hauppauge DVB card rev2.1 0 +s 1131714613c20006 Technotrend/Hauppauge DVB card rev1.3 or rev1.6 0 +s 1131714613c20008 Technotrend/Hauppauge DVB-T 0 +s 1131714613c2000a Octal/Technotrend DVB-C for iTV 0 +s 1131714613c21003 Technotrend-Budget / Hauppauge WinTV-NOVA-S DVB card 0 +s 1131714613c21004 Technotrend-Budget / Hauppauge WinTV-NOVA-C DVB card 0 +s 1131714613c21005 Technotrend-Budget / Hauppauge WinTV-NOVA-T DVB card 0 +s 1131714613c2100c Technotrend-Budget / Hauppauge WinTV-NOVA-CI DVB card 0 +s 1131714613c2100f Technotrend-Budget / Hauppauge WinTV-NOVA-CI DVB card 0 +s 1131714613c21011 Technotrend-Budget / Hauppauge WinTV-NOVA-T DVB card 0 +s 1131714613c21013 SATELCO Multimedia DVB 0 +s 1131714613c21102 Technotrend/Hauppauge DVB card rev2.1 0 +v 1132 Mitel Corp. 0 +v 1133 Eicon Networks Corporation 0 This is the new official company name. See disclaimer on www.eicon.com for details! +d 11337901 EiconCard S90 0 +d 11337902 EiconCard S90 0 +d 11337911 EiconCard S91 0 +d 11337912 EiconCard S91 0 +d 11337941 EiconCard S94 0 +d 11337942 EiconCard S94 0 +d 11337943 EiconCard S94 0 +d 11337944 EiconCard S94 0 +d 1133b921 EiconCard P92 0 +d 1133b922 EiconCard P92 0 +d 1133b923 EiconCard P92 0 +d 1133e001 Diva Pro 2.0 S/T 0 +d 1133e002 Diva 2.0 S/T PCI 0 +d 1133e003 Diva Pro 2.0 U 0 +d 1133e004 Diva 2.0 U PCI 0 +d 1133e005 Diva 2.01 S/T PCI 0 +d 1133e006 Diva CT S/T PCI 0 +d 1133e007 Diva CT U PCI 0 +d 1133e008 Diva CT Lite S/T PCI 0 +d 1133e009 Diva CT Lite U PCI 0 +d 1133e00a Diva ISDN+V.90 PCI 0 +d 1133e00b Diva 2.02 PCI S/T 0 +d 1133e00c Diva 2.02 PCI U 0 +d 1133e00d Diva ISDN Pro 3.0 PCI 0 +d 1133e00e Diva ISDN+CT S/T PCI Rev 2 0 +d 1133e010 Diva Server BRI-2M PCI 0 +s 1133e010110a0021 Fujitsu Siemens ISDN S0 0 +s 1133e01080010014 Diva Server BRI-2M PCI Cornet NQ 0 +d 1133e011 Diva Server BRI S/T Rev 2 0 +d 1133e012 Diva Server 4BRI-8M PCI 0 +s 1133e01280010014 Diva Server 4BRI-8M PCI Cornet NQ 0 +d 1133e013 Diva Server 4BRI Rev 2 0 +s 1133e01311331300 Diva Server V-4BRI-8 0 +s 1133e0131133e013 Diva Server 4BRI-8M 2.0 PCI 0 +s 1133e01380010014 Diva Server 4BRI-8M 2.0 PCI Cornet NQ 0 +d 1133e014 Diva Server PRI-30M PCI 0 +s 1133e01400080100 Diva Server PRI-30M PCI 0 +s 1133e01480010014 Diva Server PRI-30M PCI Cornet NQ 0 +d 1133e015 DIVA Server PRI Rev 2 0 +s 1133e0151133e015 Diva Server PRI 2.0 PCI 0 +s 1133e01580010014 Diva Server PRI 2.0 PCI Cornet NQ 0 +d 1133e016 Diva Server Voice 4BRI PCI 0 +s 1133e01680010014 Diva Server PRI Cornet NQ 0 +d 1133e017 Diva Server Voice 4BRI Rev 2 0 +s 1133e0171133e017 Diva Server Voice 4BRI-8M 2.0 PCI 0 +s 1133e01780010014 Diva Server Voice 4BRI-8M 2.0 PCI Cornet NQ 0 +d 1133e018 Diva Server BRI-2M 2.0 PCI 0 +s 1133e01811331800 Diva Server V-BRI-2 0 +s 1133e0181133e018 Diva Server BRI-2M 2.0 PCI 0 +s 1133e01880010014 Diva Server BRI-2M 2.0 PCI Cornet NQ 0 +d 1133e019 Diva Server Voice PRI Rev 2 0 +s 1133e0191133e019 Diva Server Voice PRI 2.0 PCI 0 +s 1133e01980010014 Diva Server Voice PRI 2.0 PCI Cornet NQ 0 +d 1133e01a Diva Server 2FX 0 +d 1133e01b Diva Server Voice BRI-2M 2.0 PCI 0 +s 1133e01b1133e01b Diva Server Voice BRI-2M 2.0 PCI 0 +s 1133e01b80010014 Diva Server Voice BRI-2M 2.0 PCI Cornet NQ 0 +d 1133e01c Diva Server PRI Rev 3 0 +s 1133e01c11331c01 Diva Server PRI/E1/T1-8 0 +s 1133e01c11331c02 Diva Server PRI/T1-24 0 +s 1133e01c11331c03 Diva Server PRI/E1-30 0 +s 1133e01c11331c04 Diva Server PRI/E1/T1 0 +s 1133e01c11331c05 Diva Server V-PRI/T1-24 0 +s 1133e01c11331c06 Diva Server V-PRI/E1-30 0 +s 1133e01c11331c07 Diva Server PRI/E1/T1-8 Cornet NQ 0 +s 1133e01c11331c08 Diva Server PRI/T1-24 Cornet NQ 0 +s 1133e01c11331c09 Diva Server PRI/E1-30 Cornet NQ 0 +s 1133e01c11331c0a Diva Server PRI/E1/T1 Cornet NQ 0 +s 1133e01c11331c0b Diva Server V-PRI/T1-24 Cornet NQ 0 +s 1133e01c11331c0c Diva Server V-PRI/E1-30 Cornet NQ 0 +d 1133e01e Diva Server 2PRI 0 +s 1133e01e11331e00 Diva Server V-2PRI/E1-60 0 +s 1133e01e11331e01 Diva Server V-2PRI/T1-48 0 +s 1133e01e11331e02 Diva Server 2PRI/E1-60 0 +s 1133e01e11331e03 Diva Server 2PRI/T1-48 0 +d 1133e020 Diva Server 4PRI 0 +s 1133e02011332000 Diva Server V-4PRI/E1-120 0 +s 1133e02011332001 Diva Server V-4PRI/T1-96 0 +s 1133e02011332002 Diva Server 4PRI/E1-120 0 +s 1133e02011332003 Diva Server 4PRI/T1-96 0 +d 1133e024 Diva Server Analog-4P 0 +s 1133e02411332400 Diva Server V-Analog-4P 0 +s 1133e0241133e024 Diva Server Analog-4P 0 +d 1133e028 Diva Server Analog-8P 0 +s 1133e02811332800 Diva Server V-Analog-8P 0 +s 1133e0281133e028 Diva Server Analog-8P 0 +v 1134 Mercury Computer Systems 0 +d 11340001 Raceway Bridge 0 +d 11340002 Dual PCI to RapidIO Bridge 0 +v 1135 Fuji Xerox Co Ltd 0 +d 11350001 Printer controller 0 +v 1136 Momentum Data Systems 0 +v 1137 Cisco Systems Inc 0 +v 1138 Ziatech Corporation 0 +d 11388905 8905 [STD 32 Bridge] 0 +v 1139 Dynamic Pictures, Inc 0 +d 11390001 VGA Compatable 3D Graphics 0 +v 113a FWB Inc 0 +v 113b Network Computing Devices 0 +v 113c Cyclone Microsystems, Inc. 0 +d 113c0000 PCI-9060 i960 Bridge 0 +d 113c0001 PCI-SDK [PCI i960 Evaluation Platform] 0 +d 113c0911 PCI-911 [i960Jx-based Intelligent I/O Controller] 0 +d 113c0912 PCI-912 [i960CF-based Intelligent I/O Controller] 0 +d 113c0913 PCI-913 0 +d 113c0914 PCI-914 [I/O Controller w/ secondary PCI bus] 0 +v 113d Leading Edge Products Inc 0 +v 113e Sanyo Electric Co - Computer Engineering Dept 0 +v 113f Equinox Systems, Inc. 0 +d 113f0808 SST-64P Adapter 0 +d 113f1010 SST-128P Adapter 0 +d 113f80c0 SST-16P DB Adapter 0 +d 113f80c4 SST-16P RJ Adapter 0 +d 113f80c8 SST-16P Adapter 0 +d 113f8888 SST-4P Adapter 0 +d 113f9090 SST-8P Adapter 0 +v 1140 Intervoice Inc 0 +v 1141 Crest Microsystem Inc 0 +v 1142 Alliance Semiconductor Corporation 0 +d 11423210 AP6410 0 +d 11426422 ProVideo 6422 0 +d 11426424 ProVideo 6424 0 +d 11426425 ProMotion AT25 0 +d 1142643d ProMotion AT3D 0 +v 1143 NetPower, Inc 0 +v 1144 Cincinnati Milacron 0 +d 11440001 Noservo controller 0 +v 1145 Workbit Corporation 0 +d 11458007 NinjaSCSI-32 Workbit 0 +d 1145f007 NinjaSCSI-32 KME 0 +d 1145f010 NinjaSCSI-32 Workbit 0 +d 1145f012 NinjaSCSI-32 Logitec 0 +d 1145f013 NinjaSCSI-32 Logitec 0 +d 1145f015 NinjaSCSI-32 Melco 0 +v 1146 Force Computers 0 +v 1147 Interface Corp 0 +v 1148 SysKonnect 0 Formerly (Schneider & Koch) +d 11484000 FDDI Adapter 0 +s 114840000e11b03b Netelligent 100 FDDI DAS Fibre SC 0 +s 114840000e11b03c Netelligent 100 FDDI SAS Fibre SC 0 +s 114840000e11b03d Netelligent 100 FDDI DAS UTP 0 +s 114840000e11b03e Netelligent 100 FDDI SAS UTP 0 +s 114840000e11b03f Netelligent 100 FDDI SAS Fibre MIC 0 +s 1148400011485521 FDDI SK-5521 (SK-NET FDDI-UP) 0 +s 1148400011485522 FDDI SK-5522 (SK-NET FDDI-UP DAS) 0 +s 1148400011485541 FDDI SK-5541 (SK-NET FDDI-FP) 0 +s 1148400011485543 FDDI SK-5543 (SK-NET FDDI-LP) 0 +s 1148400011485544 FDDI SK-5544 (SK-NET FDDI-LP DAS) 0 +s 1148400011485821 FDDI SK-5821 (SK-NET FDDI-UP64) 0 +s 1148400011485822 FDDI SK-5822 (SK-NET FDDI-UP64 DAS) 0 +s 1148400011485841 FDDI SK-5841 (SK-NET FDDI-FP64) 0 +s 1148400011485843 FDDI SK-5843 (SK-NET FDDI-LP64) 0 +s 1148400011485844 FDDI SK-5844 (SK-NET FDDI-LP64 DAS) 0 +d 11484200 Token Ring adapter 0 +d 11484300 SK-98xx Gigabit Ethernet Server Adapter 0 +s 1148430011489821 SK-9821 Gigabit Ethernet Server Adapter (SK-NET GE-T) 0 +s 1148430011489822 SK-9822 Gigabit Ethernet Server Adapter (SK-NET GE-T dual link) 0 +s 1148430011489841 SK-9841 Gigabit Ethernet Server Adapter (SK-NET GE-LX) 0 +s 1148430011489842 SK-9842 Gigabit Ethernet Server Adapter (SK-NET GE-LX dual link) 0 +s 1148430011489843 SK-9843 Gigabit Ethernet Server Adapter (SK-NET GE-SX) 0 +s 1148430011489844 SK-9844 Gigabit Ethernet Server Adapter (SK-NET GE-SX dual link) 0 +s 1148430011489861 SK-9861 Gigabit Ethernet Server Adapter (SK-NET GE-SX Volition) 0 +s 1148430011489862 SK-9862 Gigabit Ethernet Server Adapter (SK-NET GE-SX Volition dual link) 0 +s 1148430011489871 SK-9871 Gigabit Ethernet Server Adapter (SK-NET GE-ZX) 0 +s 1148430011489872 SK-9872 Gigabit Ethernet Server Adapter (SK-NET GE-ZX dual link) 0 +s 1148430012592970 AT-2970SX Gigabit Ethernet Adapter 0 +s 1148430012592971 AT-2970LX Gigabit Ethernet Adapter 0 +s 1148430012592972 AT-2970TX Gigabit Ethernet Adapter 0 +s 1148430012592973 AT-2971SX Gigabit Ethernet Adapter 0 +s 1148430012592974 AT-2971T Gigabit Ethernet Adapter 0 +s 1148430012592975 AT-2970SX/2SC Gigabit Ethernet Adapter 0 +s 1148430012592976 AT-2970LX/2SC Gigabit Ethernet Adapter 0 +s 1148430012592977 AT-2970TX/2TX Gigabit Ethernet Adapter 0 +d 11484320 SK-98xx V2.0 Gigabit Ethernet Adapter 0 +s 1148432011480121 Marvell RDK-8001 Adapter 0 +s 1148432011480221 Marvell RDK-8002 Adapter 0 +s 1148432011480321 Marvell RDK-8003 Adapter 0 +s 1148432011480421 Marvell RDK-8004 Adapter 0 +s 1148432011480621 Marvell RDK-8006 Adapter 0 +s 1148432011480721 Marvell RDK-8007 Adapter 0 +s 1148432011480821 Marvell RDK-8008 Adapter 0 +s 1148432011480921 Marvell RDK-8009 Adapter 0 +s 1148432011481121 Marvell RDK-8011 Adapter 0 +s 1148432011481221 Marvell RDK-8012 Adapter 0 +s 1148432011483221 SK-9521 V2.0 10/100/1000Base-T Adapter 0 +s 1148432011485021 SK-9821 V2.0 Gigabit Ethernet 10/100/1000Base-T Adapter 0 +s 1148432011485041 SK-9841 V2.0 Gigabit Ethernet 1000Base-LX Adapter 0 +s 1148432011485043 SK-9843 V2.0 Gigabit Ethernet 1000Base-SX Adapter 0 +s 1148432011485051 SK-9851 V2.0 Gigabit Ethernet 1000Base-SX Adapter 0 +s 1148432011485061 SK-9861 V2.0 Gigabit Ethernet 1000Base-SX Adapter 0 +s 1148432011485071 SK-9871 V2.0 Gigabit Ethernet 1000Base-ZX Adapter 0 +s 1148432011489521 SK-9521 10/100/1000Base-T Adapter 0 +d 11484400 SK-9Dxx Gigabit Ethernet Adapter 0 +d 11484500 SK-9Mxx Gigabit Ethernet Adapter 0 +d 11489e00 SK-9Exx 10/100/1000Base-T Adapter 0 +s 11489e0011482100 SK-9E21 Server Adapter 0 +s 11489e00114821d0 SK-9E21D 10/100/1000Base-T Adapter 0 +s 11489e0011482200 SK-9E22 Server Adapter 0 +s 11489e0011488100 SK-9E81 Server Adapter 0 +s 11489e0011488200 SK-9E82 Server Adapter 0 +s 11489e0011489100 SK-9E91 Server Adapter 0 +s 11489e0011489200 SK-9E92 Server Adapter 0 +v 1149 Win System Corporation 0 +v 114a VMIC 0 +d 114a5579 VMIPCI-5579 (Reflective Memory Card) 0 +d 114a5587 VMIPCI-5587 (Reflective Memory Card) 0 +d 114a6504 VMIC PCI 7755 FPGA 0 +d 114a7587 VMIVME-7587 0 +v 114b Canopus Co., Ltd 0 +v 114c Annabooks 0 +v 114d IC Corporation 0 +v 114e Nikon Systems Inc 0 +v 114f Digi International 0 +d 114f0002 AccelePort EPC 0 +d 114f0003 RightSwitch SE-6 0 +d 114f0004 AccelePort Xem 0 +d 114f0005 AccelePort Xr 0 +d 114f0006 AccelePort Xr,C/X 0 +d 114f0009 AccelePort Xr/J 0 +d 114f000a AccelePort EPC/J 0 +d 114f000c DataFirePRIme T1 (1-port) 0 +d 114f000d SyncPort 2-Port (x.25/FR) 0 +d 114f0011 AccelePort 8r EIA-232 (IBM) 0 +d 114f0012 AccelePort 8r EIA-422 0 +d 114f0013 AccelePort Xr 0 +d 114f0014 AccelePort 8r EIA-422 0 +d 114f0015 AccelePort Xem 0 +d 114f0016 AccelePort EPC/X 0 +d 114f0017 AccelePort C/X 0 +d 114f001a DataFirePRIme E1 (1-port) 0 +d 114f001b AccelePort C/X (IBM) 0 +d 114f001d DataFire RAS T1/E1/PRI 0 +s 114f001d114f0050 DataFire RAS E1 Adapter 0 +s 114f001d114f0051 DataFire RAS Dual E1 Adapter 0 +s 114f001d114f0052 DataFire RAS T1 Adapter 0 +s 114f001d114f0053 DataFire RAS Dual T1 Adapter 0 +d 114f0023 AccelePort RAS 0 +d 114f0024 DataFire RAS B4 ST/U 0 +s 114f0024114f0030 DataFire RAS BRI U Adapter 0 +s 114f0024114f0031 DataFire RAS BRI S/T Adapter 0 +d 114f0026 AccelePort 4r 920 0 +d 114f0027 AccelePort Xr 920 0 +d 114f0028 ClassicBoard 4 0 +d 114f0029 ClassicBoard 8 0 +d 114f0034 AccelePort 2r 920 0 +d 114f0035 DataFire DSP T1/E1/PRI cPCI 0 +d 114f0040 AccelePort Xp 0 +d 114f0042 AccelePort 2p 0 +d 114f0043 AccelePort 4p 0 +d 114f0044 AccelePort 8p 0 +d 114f0045 AccelePort 16p 0 +d 114f004e AccelePort 32p 0 +d 114f0070 Datafire Micro V IOM2 (Europe) 0 +d 114f0071 Datafire Micro V (Europe) 0 +d 114f0072 Datafire Micro V IOM2 (North America) 0 +d 114f0073 Datafire Micro V (North America) 0 +d 114f00b0 Digi Neo 4 0 +d 114f00b1 Digi Neo 8 0 +d 114f00c8 Digi Neo 2 DB9 0 +d 114f00c9 Digi Neo 2 DB9 PRI 0 +d 114f00ca Digi Neo 2 RJ45 0 +d 114f00cb Digi Neo 2 RJ45 PRI 0 +d 114f00d0 ClassicBoard 4 422 0 +d 114f00d1 ClassicBoard 8 422 0 +d 114f6001 Avanstar 0 +v 1150 Thinking Machines Corp 0 +v 1151 JAE Electronics Inc. 0 +v 1152 Megatek 0 +v 1153 Land Win Electronic Corp 0 +v 1154 Melco Inc 0 +v 1155 Pine Technology Ltd 0 +v 1156 Periscope Engineering 0 +v 1157 Avsys Corporation 0 +v 1158 Voarx R & D Inc 0 +d 11583011 Tokenet/vg 1001/10m anylan 0 +d 11589050 Lanfleet/Truevalue 0 +d 11589051 Lanfleet/Truevalue 0 +v 1159 Mutech Corp 0 +d 11590001 MV-1000 0 +v 115a Harlequin Ltd 0 +v 115b Parallax Graphics 0 +v 115c Photron Ltd. 0 +v 115d Xircom 0 +d 115d0003 Cardbus Ethernet 10/100 0 +s 115d000310140181 10/100 EtherJet Cardbus Adapter 0 +s 115d000310141181 10/100 EtherJet Cardbus Adapter 0 +s 115d000310148181 10/100 EtherJet Cardbus Adapter 0 +s 115d000310149181 10/100 EtherJet Cardbus Adapter 0 +s 115d0003115d0181 Cardbus Ethernet 10/100 0 +s 115d0003115d1181 Cardbus Ethernet 10/100 0 +s 115d000311790181 Cardbus Ethernet 10/100 0 +s 115d000380868181 EtherExpress PRO/100 Mobile CardBus 32 Adapter 0 +s 115d000380869181 EtherExpress PRO/100 Mobile CardBus 32 Adapter 0 +d 115d0005 Cardbus Ethernet 10/100 0 +s 115d000510140182 10/100 EtherJet Cardbus Adapter 0 +s 115d000510141182 10/100 EtherJet Cardbus Adapter 0 +s 115d0005115d0182 Cardbus Ethernet 10/100 0 +s 115d0005115d1182 Cardbus Ethernet 10/100 0 +d 115d0007 Cardbus Ethernet 10/100 0 +s 115d000710140182 10/100 EtherJet Cardbus Adapter 0 +s 115d000710141182 10/100 EtherJet Cardbus Adapter 0 +s 115d0007115d0182 Cardbus Ethernet 10/100 0 +s 115d0007115d1182 Cardbus Ethernet 10/100 0 +d 115d000b Cardbus Ethernet 10/100 0 +s 115d000b10140183 10/100 EtherJet Cardbus Adapter 0 +s 115d000b115d0183 Cardbus Ethernet 10/100 0 +d 115d000c Mini-PCI V.90 56k Modem 0 +d 115d000f Cardbus Ethernet 10/100 0 +s 115d000f10140183 10/100 EtherJet Cardbus Adapter 0 +s 115d000f115d0183 Cardbus Ethernet 10/100 0 +d 115d00d4 Mini-PCI K56Flex Modem 0 +d 115d0101 Cardbus 56k modem 0 +s 115d0101115d1081 Cardbus 56k Modem 0 +d 115d0103 Cardbus Ethernet + 56k Modem 0 +s 115d010310149181 Cardbus 56k Modem 0 +s 115d010311151181 Cardbus Ethernet 100 + 56k Modem 0 +s 115d0103115d1181 CBEM56G-100 Ethernet + 56k Modem 0 +s 115d010380869181 PRO/100 LAN + Modem56 CardBus 0 +v 115e Peer Protocols Inc 0 +v 115f Maxtor Corporation 0 +v 1160 Megasoft Inc 0 +v 1161 PFU Limited 0 +v 1162 OA Laboratory Co Ltd 0 +v 1163 Rendition 0 +d 11630001 Verite 1000 0 +d 11632000 Verite V2000/V2100/V2200 0 +s 1163200010922000 Stealth II S220 0 +v 1164 Advanced Peripherals Technologies 0 +v 1165 Imagraph Corporation 0 +d 11650001 Motion TPEG Recorder/Player with audio 0 +v 1166 ServerWorks 0 +d 11660000 CMIC-LE 0 +d 11660005 CNB20-LE Host Bridge 0 +d 11660006 CNB20HE Host Bridge 0 +d 11660007 CNB20-LE Host Bridge 0 +d 11660008 CNB20HE Host Bridge 0 +d 11660009 CNB20LE Host Bridge 0 +d 11660010 CIOB30 0 +d 11660011 CMIC-HE 0 +d 11660012 CMIC-WS Host Bridge (GC-LE chipset) 0 +d 11660013 CNB20-HE Host Bridge 0 +d 11660014 CMIC-LE Host Bridge (GC-LE chipset) 0 +d 11660015 CMIC-GC Host Bridge 0 +d 11660016 CMIC-GC Host Bridge 0 +d 11660017 GCNB-LE Host Bridge 0 +d 11660101 CIOB-X2 PCI-X I/O Bridge 0 +d 11660110 CIOB-E I/O Bridge with Gigabit Ethernet 0 +d 11660200 OSB4 South Bridge 0 +d 11660201 CSB5 South Bridge 0 +s 116602014c531080 CT8 mainboard 0 +d 11660203 CSB6 South Bridge 0 +d 11660211 OSB4 IDE Controller 0 +d 11660212 CSB5 IDE Controller 0 +s 116602124c531080 CT8 mainboard 0 +d 11660213 CSB6 RAID/IDE Controller 0 +d 11660217 CSB6 IDE Controller 0 +d 11660220 OSB4/CSB5 OHCI USB Controller 0 +s 116602204c531080 CT8 mainboard 0 +d 11660221 CSB6 OHCI USB Controller 0 +d 11660225 CSB5 LPC bridge 0 +s 116602254c531080 CT8 mainboard 0 cancelled +d 11660227 GCLE-2 Host Bridge 0 +d 11660230 CSB5 LPC bridge 0 +s 116602304c531080 CT8 mainboard 0 +d 11660240 K2 SATA 0 +v 1167 Mutoh Industries Inc 0 +v 1168 Thine Electronics Inc 0 +v 1169 Centre for Development of Advanced Computing 0 +v 116a Polaris Communications 0 +d 116a6100 Bus/Tag Channel 0 +d 116a6800 Escon Channel 0 +d 116a7100 Bus/Tag Channel 0 +d 116a7800 Escon Channel 0 +v 116b Connectware Inc 0 +v 116c Intelligent Resources Integrated Systems 0 +v 116d Martin-Marietta 0 +v 116e Electronics for Imaging 0 +v 116f Workstation Technology 0 +v 1170 Inventec Corporation 0 +v 1171 Loughborough Sound Images Plc 0 +v 1172 Altera Corporation 0 +v 1173 Adobe Systems, Inc 0 +v 1174 Bridgeport Machines 0 +v 1175 Mitron Computer Inc. 0 +v 1176 SBE Incorporated 0 +v 1177 Silicon Engineering 0 +v 1178 Alfa, Inc. 0 +d 1178afa1 Fast Ethernet Adapter 0 +v 1179 Toshiba America Info Systems 0 +d 11790103 EX-IDE Type-B 0 +d 11790404 DVD Decoder card 0 +d 11790406 Tecra Video Capture device 0 +d 11790407 DVD Decoder card (Version 2) 0 +d 11790601 601 0 +d 11790603 ToPIC95 PCI to CardBus Bridge for Notebooks 0 +d 1179060a ToPIC95 0 +d 1179060f ToPIC97 0 +d 11790617 ToPIC100 PCI to Cardbus Bridge with ZV Support 0 +d 11790618 CPU to PCI and PCI to ISA bridge 0 +d 11790701 FIR Port 0 Claimed to be Lucent DSP1645 [Mars], but that's apparently incorrect. Does anyone know the correct ID? +d 11790804 TC6371AF SmartMedia Controller 0 +d 11790805 SD TypA Controller 0 +d 11790d01 FIR Port Type-DO 0 +s 11790d0111790001 FIR Port Type-DO 0 +v 117a A-Trend Technology 0 +v 117b L G Electronics, Inc. 0 +v 117c Atto Technology 0 +v 117d Becton & Dickinson 0 +v 117e T/R Systems 0 +v 117f Integrated Circuit Systems 0 +v 1180 Ricoh Co Ltd 0 +d 11800465 RL5c465 0 +d 11800466 RL5c466 0 +d 11800475 RL5c475 0 +s 11800475144dc006 vpr Matrix 170B4 CardBus bridge 0 +d 11800476 RL5c476 II 0 +s 1180047610140185 ThinkPad A/T/X Series 0 +s 11800476104d80df Vaio PCG-FX403 0 +s 11800476104d80e7 VAIO PCG-GR214EP/GR214MP/GR215MP/GR314MP/GR315MP 0 +s 1180047614ef0220 PCD-RP-220S 0 +d 11800477 RL5c477 0 +d 11800478 RL5c478 0 +s 1180047810140184 ThinkPad A30p (2653-64G) 0 +d 11800522 R5C522 IEEE 1394 Controller 0 +s 11800522101401cf ThinkPad A30p (2653-64G) 0 +d 11800551 R5C551 IEEE 1394 Controller 0 +s 11800551144dc006 vpr Matrix 170B4 0 +d 11800552 R5C552 IEEE 1394 Controller 0 +s 1180055210140511 ThinkPad A/T/X Series 0 +v 1181 Telmatics International 0 +v 1183 Fujikura Ltd 0 +v 1184 Forks Inc 0 +v 1185 Dataworld International Ltd 0 +v 1186 D-Link System Inc 0 +d 11860100 DC21041 0 +d 11861002 DL10050 Sundance Ethernet 0 +s 1186100211861002 DFE-550TX 0 +s 1186100211861012 DFE-580TX 0 +d 11861025 AirPlus Xtreme G DWL-G650 Adapter 0 +d 11861026 AirXpert DWL-AG650 Wireless Cardbus Adapter 0 +d 11861043 AirXpert DWL-AG650 Wireless Cardbus Adapter 0 +d 11861300 RTL8139 Ethernet 0 +s 1186130011861300 DFE-538TX 10/100 Ethernet Adapter 0 +s 1186130011861301 DFE-530TX+ 10/100 Ethernet Adapter 0 +d 11861340 DFE-690TXD CardBus PC Card 0 +d 11861541 DFE-680TXD CardBus PC Card 0 +d 11861561 DRP-32TXD Cardbus PC Card 0 +d 11862027 AirPlus Xtreme G DWL-G520 Adapter 0 +d 11863203 AirPlus Xtreme G DWL-G520 Adapter 0 +d 11863300 DWL-510 2.4GHz Wireless PCI Adapter 0 +d 11863a03 AirPro DWL-A650 Wireless Cardbus Adapter(rev.B) 0 +d 11863a04 AirPro DWL-AB650 Multimode Wireless Cardbus Adapter 0 +d 11863a05 AirPro DWL-AB520 Multimode Wireless PCI Adapter 0 +d 11863a07 AirXpert DWL-AG650 Wireless Cardbus Adapter 0 +d 11863a08 AirXpert DWL-AG520 Wireless PCI Adapter 0 +d 11863a10 AirXpert DWL-AG650 Wireless Cardbus Adapter(rev.B) 0 +d 11863a11 AirXpert DWL-AG520 Wireless PCI Adapter(rev.B) 0 +d 11863a12 AirPlus DWL-G650 Wireless Cardbus Adapter(rev.C) 0 +d 11863a13 AirPlus DWL-G520 Wireless PCI Adapter(rev.B) 0 +d 11863a14 AirPremier DWL-AG530 Wireless PCI Adapter 0 +d 11863a63 AirXpert DWL-AG660 Wireless Cardbus Adapter 0 +d 11863b05 DWL-G650+ CardBus PC Card 0 +d 11864000 DL2000-based Gigabit Ethernet 0 +d 11864c00 Gigabit Ethernet Adapter 0 +s 11864c0011864c00 DGE-530T Gigabit Ethernet Adapter 0 +d 11868400 D-Link DWL-650+ CardBus PC Card 0 +v 1187 Advanced Technology Laboratories, Inc. 0 +v 1188 Shima Seiki Manufacturing Ltd. 0 +v 1189 Matsushita Electronics Co Ltd 0 +v 118a Hilevel Technology 0 +v 118b Hypertec Pty Limited 0 +v 118c Corollary, Inc 0 +d 118c0014 PCIB [C-bus II to PCI bus host bridge chip] 0 +d 118c1117 Intel 8-way XEON Profusion Chipset [Cache Coherency Filter] 0 +v 118d BitFlow Inc 0 +d 118d0001 Raptor-PCI framegrabber 0 +d 118d0012 Model 12 Road Runner Frame Grabber 0 +d 118d0014 Model 14 Road Runner Frame Grabber 0 +d 118d0024 Model 24 Road Runner Frame Grabber 0 +d 118d0044 Model 44 Road Runner Frame Grabber 0 +d 118d0112 Model 12 Road Runner Frame Grabber 0 +d 118d0114 Model 14 Road Runner Frame Grabber 0 +d 118d0124 Model 24 Road Runner Frame Grabber 0 +d 118d0144 Model 44 Road Runner Frame Grabber 0 +d 118d0212 Model 12 Road Runner Frame Grabber 0 +d 118d0214 Model 14 Road Runner Frame Grabber 0 +d 118d0224 Model 24 Road Runner Frame Grabber 0 +d 118d0244 Model 44 Road Runner Frame Grabber 0 +d 118d0312 Model 12 Road Runner Frame Grabber 0 +d 118d0314 Model 14 Road Runner Frame Grabber 0 +d 118d0324 Model 24 Road Runner Frame Grabber 0 +d 118d0344 Model 44 Road Runner Frame Grabber 0 +v 118e Hermstedt GmbH 0 +v 118f Green Logic 0 +v 1190 Tripace 0 +d 1190c731 TP-910/920/940 PCI Ultra(Wide) SCSI Adapter 0 +v 1191 Artop Electronic Corp 0 +d 11910003 SCSI Cache Host Adapter 0 +d 11910004 ATP8400 0 +d 11910005 ATP850UF 0 +d 11910006 ATP860 NO-BIOS 0 +d 11910007 ATP860 0 +d 11910008 ATP865 NO-ROM 0 +d 11910009 ATP865 0 +d 11918002 AEC6710 SCSI-2 Host Adapter 0 +d 11918010 AEC6712UW SCSI 0 +d 11918020 AEC6712U SCSI 0 +d 11918030 AEC6712S SCSI 0 +d 11918040 AEC6712D SCSI 0 +d 11918050 AEC6712SUW SCSI 0 +v 1192 Densan Company Ltd 0 +v 1193 Zeitnet Inc. 0 +d 11930001 1221 0 +d 11930002 1225 0 +v 1194 Toucan Technology 0 +v 1195 Ratoc System Inc 0 +v 1196 Hytec Electronics Ltd 0 +v 1197 Gage Applied Sciences, Inc. 0 +d 1197010c CompuScope 82G 8bit 2GS/s Analog Input Card 0 +v 1198 Lambda Systems Inc 0 +v 1199 Attachmate Corporation 0 +v 119a Mind Share, Inc. 0 +v 119b Omega Micro Inc. 0 +d 119b1221 82C092G 0 +v 119c Information Technology Inst. 0 +v 119d Bug, Inc. Sapporo Japan 0 +v 119e Fujitsu Microelectronics Ltd. 0 +d 119e0001 FireStream 155 0 +d 119e0003 FireStream 50 0 +v 119f Bull HN Information Systems 0 +v 11a0 Convex Computer Corporation 0 +v 11a1 Hamamatsu Photonics K.K. 0 +v 11a2 Sierra Research and Technology 0 +v 11a3 Deuretzbacher GmbH & Co. Eng. KG 0 +v 11a4 Barco Graphics NV 0 +v 11a5 Microunity Systems Eng. Inc 0 +v 11a6 Pure Data Ltd. 0 +v 11a7 Power Computing Corp. 0 +v 11a8 Systech Corp. 0 +v 11a9 InnoSys Inc. 0 +d 11a94240 AMCC S933Q Intelligent Serial Card 0 +v 11aa Actel 0 +v 11ab Marvell Technology Group Ltd. 0 Formerly Galileo Technology, Inc. +d 11ab0146 GT-64010/64010A System Controller 0 +d 11ab138f W8300 802.11 Adapter (rev 07) 0 +d 11ab1fa6 Marvell W8300 802.11 Adapter 0 +d 11ab4320 Gigabit Ethernet Controller 0 +s 11ab432010190f38 Marvell 88E8001 Gigabit Ethernet Controller (ECS) 0 +s 11ab432010198001 Marvell 88E8001 Gigabit Ethernet Controller (ECS) 0 +s 11ab43201043173c Marvell 88E8001 Gigabit Ethernet Controller (Asus) 0 +s 11ab43201043811a Marvell 88E8001 Gigabit Ethernet Controller (Asus) 0 +s 11ab4320105b0c19 Marvell 88E8001 Gigabit Ethernet Controller (Foxconn) 0 +s 11ab432010b8b452 SMC EZ Card 1000 (SMC9452TXV.2) 0 +s 11ab432011ab0121 Marvell RDK-8001 0 +s 11ab432011ab0321 Marvell RDK-8003 0 +s 11ab432011ab1021 Marvell RDK-8010 0 +s 11ab432011ab5021 Marvell Yukon Gigabit Ethernet 10/100/1000Base-T Controller (64 bit) 0 +s 11ab432011ab9521 Marvell Yukon Gigabit Ethernet 10/100/1000Base-T Controller (32 bit) 0 +s 11ab43201458e000 Marvell 88E8001 Gigabit Ethernet Controller (Gigabyte) 0 +s 11ab4320147b1406 Marvell 88E8001 Gigabit Ethernet Controller (Abit) 0 +s 11ab432015d40047 Marvell 88E8001 Gigabit Ethernet Controller (Iwill) 0 +s 11ab432016959025 Marvell 88E8001 Gigabit Ethernet Controller (Epox) 0 +s 11ab432017f21c03 Marvell 88E8001 Gigabit Ethernet Controller (Albatron) 0 +s 11ab4320270f2803 Marvell 88E8001 Gigabit Ethernet Controller (Chaintech) 0 +d 11ab4350 Fast Ethernet Controller 0 +s 11ab435011790001 Marvell 88E8035 Fast Ethernet Controller (Toshiba) 0 +s 11ab435011ab3521 Marvell RDK-8035 0 +s 11ab43501854000d Marvell 88E8035 Fast Ethernet Controller (LGE) 0 +s 11ab43501854000e Marvell 88E8035 Fast Ethernet Controller (LGE) 0 +s 11ab43501854000f Marvell 88E8035 Fast Ethernet Controller (LGE) 0 +s 11ab435018540011 Marvell 88E8035 Fast Ethernet Controller (LGE) 0 +s 11ab435018540012 Marvell 88E8035 Fast Ethernet Controller (LGE) 0 +s 11ab435018540016 Marvell 88E8035 Fast Ethernet Controller (LGE) 0 +s 11ab435018540017 Marvell 88E8035 Fast Ethernet Controller (LGE) 0 +s 11ab435018540018 Marvell 88E8035 Fast Ethernet Controller (LGE) 0 +s 11ab435018540019 Marvell 88E8035 Fast Ethernet Controller (LGE) 0 +s 11ab43501854001c Marvell 88E8035 Fast Ethernet Controller (LGE) 0 +s 11ab43501854001e Marvell 88E8035 Fast Ethernet Controller (LGE) 0 +s 11ab435018540020 Marvell 88E8035 Fast Ethernet Controller (LGE) 0 +d 11ab4351 Fast Ethernet Controller 0 +s 11ab4351107b4009 Marvell 88E8036 Fast Ethernet Controller (Wistron) 0 +s 11ab435110f78338 Marvell 88E8036 Fast Ethernet Controller (Panasonic) 0 +s 11ab435111790001 Marvell 88E8036 Fast Ethernet Controller (Toshiba) 0 +s 11ab43511179ff00 Marvell 88E8036 Fast Ethernet Controller (Compal) 0 +s 11ab43511179ff10 Marvell 88E8036 Fast Ethernet Controller (Inventec) 0 +s 11ab435111ab3621 Marvell RDK-8036 0 +s 11ab435113d1ac12 Abocom EFE3K - 10/100 Ethernet Expresscard 0 +s 11ab4351161f203d Marvell 88E8036 Fast Ethernet Controller (Arima) 0 +s 11ab43511854000d Marvell 88E8036 Fast Ethernet Controller (LGE) 0 +s 11ab43511854000e Marvell 88E8036 Fast Ethernet Controller (LGE) 0 +s 11ab43511854000f Marvell 88E8036 Fast Ethernet Controller (LGE) 0 +s 11ab435118540011 Marvell 88E8036 Fast Ethernet Controller (LGE) 0 +s 11ab435118540012 Marvell 88E8036 Fast Ethernet Controller (LGE) 0 +s 11ab435118540016 Marvell 88E8036 Fast Ethernet Controller (LGE) 0 +s 11ab435118540017 Marvell 88E8036 Fast Ethernet Controller (LGE) 0 +s 11ab435118540018 Marvell 88E8036 Fast Ethernet Controller (LGE) 0 +s 11ab435118540019 Marvell 88E8036 Fast Ethernet Controller (LGE) 0 +s 11ab43511854001c Marvell 88E8036 Fast Ethernet Controller (LGE) 0 +s 11ab43511854001e Marvell 88E8036 Fast Ethernet Controller (LGE) 0 +s 11ab435118540020 Marvell 88E8036 Fast Ethernet Controller (LGE) 0 +d 11ab4360 Gigabit Ethernet Controller 0 +s 11ab436010438134 Marvell 88E8052 Gigabit Ethernet Controller (Asus) 0 +s 11ab4360107b4009 Marvell 88E8052 Gigabit Ethernet Controller (Wistron) 0 +s 11ab436011ab5221 Marvell RDK-8052 0 +s 11ab43601458e000 Marvell 88E8052 Gigabit Ethernet Controller (Gigabyte) 0 +s 11ab43601462052c Marvell 88E8052 Gigabit Ethernet Controller (MSI) 0 +s 11ab436018498052 Marvell 88E8052 Gigabit Ethernet Controller (ASRock) 0 +s 11ab43601940e000 Marvell 88E8052 Gigabit Ethernet Controller (Gigabyte) 0 +s 11ab4360a0a00509 Marvell 88E8052 Gigabit Ethernet Controller (Aopen) 0 +d 11ab4361 Gigabit Ethernet Controller 0 +s 11ab4361107b3015 Marvell 88E8050 Gigabit Ethernet Controller (Gateway) 0 +s 11ab436111ab5021 Marvell 88E8050 Gigabit Ethernet Controller (Intel) 0 +s 11ab436180863063 D925XCVLK mainboard 0 +d 11ab4362 Gigabit Ethernet Controller 0 +s 11ab4362103c2a0d Marvell 88E8053 Gigabit Ethernet Controller (Asus) 0 +s 11ab436210438142 Marvell 88E8053 Gigabit Ethernet Controller (Asus) 0 +s 11ab4362109f3197 Marvell 88E8053 Gigabit Ethernet Controller (Trigem) 0 +s 11ab436210f78338 Marvell 88E8053 Gigabit Ethernet Controller (Panasonic) 0 +s 11ab436210fda430 Marvell 88E8053 Gigabit Ethernet Controller (SOYO) 0 +s 11ab436211790001 Marvell 88E8053 Gigabit Ethernet Controller (Toshiba) 0 +s 11ab43621179ff00 Marvell 88E8053 Gigabit Ethernet Controller (Compal) 0 +s 11ab43621179ff10 Marvell 88E8053 Gigabit Ethernet Controller (Inventec) 0 +s 11ab436211ab5321 Marvell RDK-8053 0 +s 11ab43621297c240 Marvell 88E8053 Gigabit Ethernet Controller (Shuttle) 0 +s 11ab43621297c241 Marvell 88E8053 Gigabit Ethernet Controller (Shuttle) 0 +s 11ab43621297c242 Marvell 88E8053 Gigabit Ethernet Controller (Shuttle) 0 +s 11ab43621297c243 Marvell 88E8053 Gigabit Ethernet Controller (Shuttle) 0 +s 11ab43621297c244 Marvell 88E8053 Gigabit Ethernet Controller (Shuttle) 0 +s 11ab436213d1ac11 Abocom EGE5K - Giga Ethernet Expresscard 0 +s 11ab43621458e000 Marvell 88E8053 Gigabit Ethernet Controller (Gigabyte) 0 +s 11ab43621462058c Marvell 88E8053 Gigabit Ethernet Controller (MSI) 0 +s 11ab436214c00012 Marvell 88E8053 Gigabit Ethernet Controller (Compal) 0 +s 11ab4362155804a0 Marvell 88E8053 Gigabit Ethernet Controller (Clevo) 0 +s 11ab436215bd1003 Marvell 88E8053 Gigabit Ethernet Controller (DFI) 0 +s 11ab4362161f203c Marvell 88E8053 Gigabit Ethernet Controller (Arima) 0 +s 11ab4362161f203d Marvell 88E8053 Gigabit Ethernet Controller (Arima) 0 +s 11ab436216959029 Marvell 88E8053 Gigabit Ethernet Controller (Epox) 0 +s 11ab436217f22c08 Marvell 88E8053 Gigabit Ethernet Controller (Albatron) 0 +s 11ab436217ff0585 Marvell 88E8053 Gigabit Ethernet Controller (Quanta) 0 +s 11ab436218498053 Marvell 88E8053 Gigabit Ethernet Controller (ASRock) 0 +s 11ab43621854000b Marvell 88E8053 Gigabit Ethernet Controller (LGE) 0 +s 11ab43621854000c Marvell 88E8053 Gigabit Ethernet Controller (LGE) 0 +s 11ab436218540010 Marvell 88E8053 Gigabit Ethernet Controller (LGE) 0 +s 11ab436218540013 Marvell 88E8053 Gigabit Ethernet Controller (LGE) 0 +s 11ab436218540014 Marvell 88E8053 Gigabit Ethernet Controller (LGE) 0 +s 11ab436218540015 Marvell 88E8053 Gigabit Ethernet Controller (LGE) 0 +s 11ab43621854001a Marvell 88E8053 Gigabit Ethernet Controller (LGE) 0 +s 11ab43621854001b Marvell 88E8053 Gigabit Ethernet Controller (LGE) 0 +s 11ab43621854001d Marvell 88E8053 Gigabit Ethernet Controller (LGE) 0 +s 11ab43621854001f Marvell 88E8053 Gigabit Ethernet Controller (LGE) 0 +s 11ab436218540021 Marvell 88E8053 Gigabit Ethernet Controller (LGE) 0 +s 11ab436218540022 Marvell 88E8053 Gigabit Ethernet Controller (LGE) 0 +s 11ab43621940e000 Marvell 88E8053 Gigabit Ethernet Controller (Gigabyte) 0 +s 11ab4362270f2801 Marvell 88E8053 Gigabit Ethernet Controller (Chaintech) 0 +s 11ab4362a0a00506 Marvell 88E8053 Gigabit Ethernet Controller (Aopen) 0 +d 11ab4611 GT-64115 System Controller 0 +d 11ab4620 GT-64120/64120A/64121A System Controller 0 +d 11ab4801 GT-48001 0 +d 11ab5040 MV88SX5040 4-port SATA I PCI-X Controller 0 +d 11ab5041 MV88SX5041 4-port SATA I PCI-X Controller 0 +d 11ab5080 MV88SX5080 8-port SATA I PCI-X Controller 0 +d 11ab5081 MV88SX5081 8-port SATA I PCI-X Controller 0 +d 11ab6041 MV88SX6041 4-port SATA II PCI-X Controller 0 +d 11ab6081 MV88SX6081 8-port SATA II PCI-X Controller 0 +d 11ab6460 MV64360/64361/64362 System Controller 0 +d 11abf003 GT-64010 Primary Image Piranha Image Generator 0 +v 11ac Canon Information Systems Research Aust. 0 +v 11ad Lite-On Communications Inc 0 +d 11ad0002 LNE100TX 0 +s 11ad000211ad0002 LNE100TX 0 +s 11ad000211ad0003 LNE100TX 0 +s 11ad000211adf003 LNE100TX 0 +s 11ad000211adffff LNE100TX 0 +s 11ad00021385f004 FA310TX 0 +d 11adc115 LNE100TX [Linksys EtherFast 10/100] 0 +s 11adc11511adc001 LNE100TX [ver 2.0] 0 +v 11ae Aztech System Ltd 0 +v 11af Avid Technology Inc. 0 +d 11af0001 [Cinema] 0 +v 11b0 V3 Semiconductor Inc. 0 +d 11b00002 V300PSC 0 +d 11b00292 V292PBC [Am29030/40 Bridge] 0 +d 11b00960 V96xPBC 0 +d 11b0c960 V96DPC 0 +v 11b1 Apricot Computers 0 +v 11b2 Eastman Kodak 0 +v 11b3 Barr Systems Inc. 0 +v 11b4 Leitch Technology International 0 +v 11b5 Radstone Technology Plc 0 +v 11b6 United Video Corp 0 +v 11b7 Motorola 0 +v 11b8 XPoint Technologies, Inc 0 +d 11b80001 Quad PeerMaster 0 +v 11b9 Pathlight Technology Inc. 0 +d 11b9c0ed SSA Controller 0 +v 11ba Videotron Corp 0 +v 11bb Pyramid Technology 0 +v 11bc Network Peripherals Inc 0 +d 11bc0001 NP-PCI 0 +v 11bd Pinnacle Systems Inc. 0 +v 11be International Microcircuits Inc 0 +v 11bf Astrodesign, Inc. 0 +v 11c0 Hewlett Packard 0 +v 11c1 Agere Systems (former Lucent Microelectronics) 0 +d 11c10440 56k WinModem 0 +s 11c1044010338015 LT WinModem 56k Data+Fax+Voice+Dsvd 0 +s 11c1044010338047 LT WinModem 56k Data+Fax+Voice+Dsvd 0 +s 11c104401033804f LT WinModem 56k Data+Fax+Voice+Dsvd 0 +s 11c1044010cf102c LB LT Modem V.90 56k 0 +s 11c1044010cf104a BIBLO LT Modem 56k 0 +s 11c1044010cf105f LB2 LT Modem V.90 56k 0 +s 11c1044011790001 Internal V.90 Modem 0 +s 11c1044011c10440 LT WinModem 56k Data+Fax+Voice+Dsvd 0 +s 11c10440122d4101 MDP7800-U Modem 0 +s 11c10440122d4102 MDP7800SP-U Modem 0 +s 11c1044013e00040 LT WinModem 56k Data+Fax+Voice+Dsvd 0 +s 11c1044013e00440 LT WinModem 56k Data+Fax+Voice+Dsvd 0 +s 11c1044013e00441 LT WinModem 56k Data+Fax+Voice+Dsvd 0 +s 11c1044013e00450 LT WinModem 56k Data+Fax+Voice+Dsvd 0 +s 11c1044013e0f100 LT WinModem 56k Data+Fax+Voice+Dsvd 0 +s 11c1044013e0f101 LT WinModem 56k Data+Fax+Voice+Dsvd 0 +s 11c10440144d2101 LT56PV Modem 0 +s 11c10440149f0440 LT WinModem 56k Data+Fax+Voice+Dsvd 0 +d 11c10441 56k WinModem 0 +s 11c104411033804d LT WinModem 56k Data+Fax 0 +s 11c1044110338065 LT WinModem 56k Data+Fax 0 +s 11c1044110920440 Supra 56i 0 +s 11c1044111790001 Internal V.90 Modem 0 +s 11c1044111c10440 LT WinModem 56k Data+Fax 0 +s 11c1044111c10441 LT WinModem 56k Data+Fax 0 +s 11c10441122d4100 MDP7800-U Modem 0 +s 11c1044113e00040 LT WinModem 56k Data+Fax 0 +s 11c1044113e00100 LT WinModem 56k Data+Fax 0 +s 11c1044113e00410 LT WinModem 56k Data+Fax 0 +s 11c1044113e00420 TelePath Internet 56k WinModem 0 +s 11c1044113e00440 LT WinModem 56k Data+Fax 0 +s 11c1044113e00443 LT WinModem 56k Data+Fax 0 +s 11c1044113e0f102 LT WinModem 56k Data+Fax 0 +s 11c1044114169804 CommWave 56k Modem 0 +s 11c10441141d0440 LT WinModem 56k Data+Fax 0 +s 11c10441144f0441 Lucent 56k V.90 DF Modem 0 +s 11c10441144f0449 Lucent 56k V.90 DF Modem 0 +s 11c10441144f110d Lucent Win Modem 0 +s 11c1044114680441 Presario 56k V.90 DF Modem 0 +s 11c1044116680440 Lucent Win Modem 0 +d 11c10442 56k WinModem 0 +s 11c1044211c10440 LT WinModem 56k Data+Fax+Voice+VoiceView+Dsvd 0 +s 11c1044211c10442 LT WinModem 56k Data+Fax+Voice+VoiceView+Dsvd 0 +s 11c1044213e00412 LT WinModem 56k Data+Fax+Voice+VoiceView+Dsvd 0 +s 11c1044213e00442 LT WinModem 56k Data+Fax+Voice+VoiceView+Dsvd 0 +s 11c1044213fc2471 LT WinModem 56k Data+Fax+Voice+VoiceView+Dsvd 0 +s 11c10442144d2104 LT56PT Modem 0 +s 11c10442144f1104 LT WinModem 56k Data+Fax+Voice+VoiceView+Dsvd 0 +s 11c10442149f0440 LT WinModem 56k Data+Fax+Voice+VoiceView+Dsvd 0 +s 11c1044216680440 LT WinModem 56k Data+Fax+Voice+VoiceView+Dsvd 0 +d 11c10443 LT WinModem 0 +d 11c10444 LT WinModem 0 +d 11c10445 LT WinModem 0 +s 11c1044580862203 PRO/100+ MiniPCI (probably an Ambit U98.003.C.00 combo card) 0 +s 11c1044580862204 PRO/100+ MiniPCI on Armada E500 0 +d 11c10446 LT WinModem 0 +d 11c10447 LT WinModem 0 +d 11c10448 WinModem 56k 0 +s 11c1044810140131 Lucent Win Modem 0 +s 11c1044810338066 LT WinModem 56k Data+Fax+Voice+Dsvd 0 +s 11c1044813e00030 56k Voice Modem 0 +s 11c1044813e00040 LT WinModem 56k Data+Fax+Voice+Dsvd 0 +s 11c1044816682400 LT WinModem 56k (MiniPCI Ethernet+Modem) 0 Actiontech eth+modem card as used by Dell &c. +d 11c10449 WinModem 56k 0 +s 11c104490e11b14d 56k V.90 Modem 0 +s 11c1044913e00020 LT WinModem 56k Data+Fax 0 +s 11c1044913e00041 TelePath Internet 56k WinModem 0 +s 11c1044914360440 Lucent Win Modem 0 +s 11c10449144f0449 Lucent 56k V.90 DFi Modem 0 +s 11c1044914680410 IBM ThinkPad T23 (2647-4MG) 0 +s 11c1044914680440 Lucent Win Modem 0 +s 11c1044914680449 Presario 56k V.90 DFi Modem 0 +d 11c1044a F-1156IV WinModem (V90, 56KFlex) 0 +s 11c1044a10cf1072 LB Global LT Modem 0 +s 11c1044a13e00012 LT WinModem 56k Data+Fax+Voice+VoiceView+Dsvd 0 +s 11c1044a13e00042 LT WinModem 56k Data+Fax+Voice+VoiceView+Dsvd 0 +s 11c1044a144f1005 LT WinModem 56k Data+Fax+Voice+VoiceView+Dsvd 0 +d 11c1044b LT WinModem 0 +d 11c1044c LT WinModem 0 +d 11c1044d LT WinModem 0 +d 11c1044e LT WinModem 0 +d 11c1044f V90 WildWire Modem 0 +d 11c10450 LT WinModem 0 +s 11c10450103380a8 Versa Note Vxi 0 +s 11c10450144f4005 Magnia SG20 0 +d 11c10451 LT WinModem 0 +d 11c10452 LT WinModem 0 +d 11c10453 LT WinModem 0 +d 11c10454 LT WinModem 0 +d 11c10455 LT WinModem 0 +d 11c10456 LT WinModem 0 +d 11c10457 LT WinModem 0 +d 11c10458 LT WinModem 0 +d 11c10459 LT WinModem 0 +d 11c1045a LT WinModem 0 +d 11c1045c LT WinModem 0 +d 11c10461 V90 WildWire Modem 0 +d 11c10462 V90 WildWire Modem 0 +d 11c10480 Venus Modem (V90, 56KFlex) 0 +d 11c1048c V.92 56K WinModem 0 +d 11c1048f V.92 56k WinModem 0 InPorte Home Internal 56k Modem/fax/answering machine/SMS Features +d 11c15801 USB 0 +d 11c15802 USS-312 USB Controller 0 +d 11c15803 USS-344S USB Controller 0 4 port PCI USB Controller made by Agere (formely Lucent) +d 11c15811 FW323 0 +s 11c158118086524c D865PERL mainboard 0 +s 11c15811dead0800 FireWire Host Bus Adapter 0 +d 11c1ab10 WL60010 Wireless LAN MAC 0 +d 11c1ab11 WL60040 Multimode Wireles LAN MAC 0 +s 11c1ab1111c1ab12 WaveLAN 11abg Cardbus card (Model 1102) 0 +s 11c1ab1111c1ab13 WaveLAN 11abg MiniPCI card (Model 0512) 0 +s 11c1ab1111c1ab15 WaveLAN 11abg Cardbus card (Model 1106) 0 +s 11c1ab1111c1ab16 WaveLAN 11abg MiniPCI card (Model 0516) 0 +d 11c1ab20 ORiNOCO PCI Adapter 0 +d 11c1ab21 Agere Wireless PCI Adapter 0 +d 11c1ab30 Hermes2 Mini-PCI WaveLAN a/b/g 0 +s 11c1ab3014cd2012 Hermes2 Mini-PCI WaveLAN a/b/g 0 +v 11c2 Sand Microelectronics 0 +v 11c3 NEC Corporation 0 +v 11c4 Document Technologies, Inc 0 +v 11c5 Shiva Corporation 0 +v 11c6 Dainippon Screen Mfg. Co. Ltd 0 +v 11c7 D.C.M. Data Systems 0 +v 11c8 Dolphin Interconnect Solutions AS 0 +d 11c80658 PSB32 SCI-Adapter D31x 0 +d 11c8d665 PSB64 SCI-Adapter D32x 0 +d 11c8d667 PSB66 SCI-Adapter D33x 0 +v 11c9 Magma 0 +d 11c90010 16-line serial port w/- DMA 0 +d 11c90011 4-line serial port w/- DMA 0 +v 11ca LSI Systems, Inc 0 +v 11cb Specialix Research Ltd. 0 +d 11cb2000 PCI_9050 0 +s 11cb200011cb0200 SX 0 +s 11cb200011cbb008 I/O8+ 0 +d 11cb4000 SUPI_1 0 +d 11cb8000 T225 0 +v 11cc Michels & Kleberhoff Computer GmbH 0 +v 11cd HAL Computer Systems, Inc. 0 +v 11ce Netaccess 0 +v 11cf Pioneer Electronic Corporation 0 +v 11d0 Lockheed Martin Federal Systems-Manassas 0 +v 11d1 Auravision 0 +d 11d101f7 VxP524 0 +v 11d2 Intercom Inc. 0 +v 11d3 Trancell Systems Inc 0 +v 11d4 Analog Devices 0 +d 11d41535 Blackfin BF535 processor 0 +d 11d41805 SM56 PCI modem 0 +d 11d41889 AD1889 sound chip 0 +v 11d5 Ikon Corporation 0 +d 11d50115 10115 0 +d 11d50117 10117 0 +v 11d6 Tekelec Telecom 0 +v 11d7 Trenton Technology, Inc. 0 +v 11d8 Image Technologies Development 0 +v 11d9 TEC Corporation 0 +v 11da Novell 0 +v 11db Sega Enterprises Ltd 0 +v 11dc Questra Corporation 0 +v 11dd Crosfield Electronics Limited 0 +v 11de Zoran Corporation 0 +d 11de6057 ZR36057PQC Video cutting chipset 0 +s 11de605710317efe DC10 Plus 0 +s 11de60571031fc00 MiroVIDEO DC50, Motion JPEG Capture/CODEC Board 0 +s 11de605713ca4231 JPEG/TV Card 0 +d 11de6120 ZR36120 0 +s 11de61201328f001 Cinemaster C DVD Decoder 0 +v 11df New Wave PDG 0 +v 11e0 Cray Communications A/S 0 +v 11e1 GEC Plessey Semi Inc. 0 +v 11e2 Samsung Information Systems America 0 +v 11e3 Quicklogic Corporation 0 +d 11e35030 PC Watchdog 0 +v 11e4 Second Wave Inc 0 +v 11e5 IIX Consulting 0 +v 11e6 Mitsui-Zosen System Research 0 +v 11e7 Toshiba America, Elec. Company 0 +v 11e8 Digital Processing Systems Inc. 0 +v 11e9 Highwater Designs Ltd. 0 +v 11ea Elsag Bailey 0 +v 11eb Formation Inc. 0 +v 11ec Coreco Inc 0 +v 11ed Mediamatics 0 +v 11ee Dome Imaging Systems Inc 0 +v 11ef Nicolet Technologies B.V. 0 +v 11f0 Compu-Shack 0 +d 11f04231 FDDI 0 +d 11f04232 FASTline UTP Quattro 0 +d 11f04233 FASTline FO 0 +d 11f04234 FASTline UTP 0 +d 11f04235 FASTline-II UTP 0 +d 11f04236 FASTline-II FO 0 +d 11f04731 GIGAline 0 +v 11f1 Symbios Logic Inc 0 +v 11f2 Picture Tel Japan K.K. 0 +v 11f3 Keithley Metrabyte 0 +v 11f4 Kinetic Systems Corporation 0 +d 11f42915 CAMAC controller 0 +v 11f5 Computing Devices International 0 +v 11f6 Compex 0 +d 11f60112 ENet100VG4 0 +d 11f60113 FreedomLine 100 0 +d 11f61401 ReadyLink 2000 0 +d 11f62011 RL100-ATX 10/100 0 +s 11f6201111f62011 RL100-ATX 0 +d 11f62201 ReadyLink 100TX (Winbond W89C840) 0 +s 11f6220111f62011 ReadyLink 100TX 0 +d 11f69881 RL100TX Fast Ethernet 0 +v 11f7 Scientific Atlanta 0 +v 11f8 PMC-Sierra Inc. 0 +d 11f87375 PM7375 [LASAR-155 ATM SAR] 0 +v 11f9 I-Cube Inc 0 +v 11fa Kasan Electronics Company, Ltd. 0 +v 11fb Datel Inc 0 +v 11fc Silicon Magic 0 +v 11fd High Street Consultants 0 +v 11fe Comtrol Corporation 0 +d 11fe0001 RocketPort 32 port w/external I/F 0 +d 11fe0002 RocketPort 8 port w/external I/F 0 +d 11fe0003 RocketPort 16 port w/external I/F 0 +d 11fe0004 RocketPort 4 port w/quad cable 0 +d 11fe0005 RocketPort 8 port w/octa cable 0 +d 11fe0006 RocketPort 8 port w/RJ11 connectors 0 +d 11fe0007 RocketPort 4 port w/RJ11 connectors 0 +d 11fe0008 RocketPort 8 port w/ DB78 SNI (Siemens) connector 0 +d 11fe0009 RocketPort 16 port w/ DB78 SNI (Siemens) connector 0 +d 11fe000a RocketPort Plus 4 port 0 +d 11fe000b RocketPort Plus 8 port 0 +d 11fe000c RocketModem 6 port 0 +d 11fe000d RocketModem 4-port 0 +d 11fe000e RocketPort Plus 2 port RS232 0 +d 11fe000f RocketPort Plus 2 port RS422 0 +d 11fe0801 RocketPort UPCI 32 port w/external I/F 0 +d 11fe0802 RocketPort UPCI 8 port w/external I/F 0 +d 11fe0803 RocketPort UPCI 16 port w/external I/F 0 +d 11fe0805 RocketPort UPCI 8 port w/octa cable 0 +d 11fe080c RocketModem III 8 port 0 +d 11fe080d RocketModem III 4 port 0 +d 11fe0903 RocketPort Compact PCI 16 port w/external I/F 0 +d 11fe8015 RocketPort 4-port UART 16954 0 +v 11ff Scion Corporation 0 +d 11ff0003 AG-5 0 +v 1200 CSS Corporation 0 +v 1201 Vista Controls Corp 0 +v 1202 Network General Corp. 0 +d 12024300 Gigabit Ethernet Adapter 0 +s 1202430012029841 SK-9841 LX 0 +s 1202430012029842 SK-9841 LX dual link 0 +s 1202430012029843 SK-9843 SX 0 +s 1202430012029844 SK-9843 SX dual link 0 +v 1203 Bayer Corporation, Agfa Division 0 +v 1204 Lattice Semiconductor Corporation 0 +v 1205 Array Corporation 0 +v 1206 Amdahl Corporation 0 +v 1208 Parsytec GmbH 0 +d 12084853 HS-Link Device 0 +v 1209 SCI Systems Inc 0 +v 120a Synaptel 0 +v 120b Adaptive Solutions 0 +v 120c Technical Corp. 0 +v 120d Compression Labs, Inc. 0 +v 120e Cyclades Corporation 0 +d 120e0100 Cyclom-Y below first megabyte 0 +d 120e0101 Cyclom-Y above first megabyte 0 +d 120e0102 Cyclom-4Y below first megabyte 0 +d 120e0103 Cyclom-4Y above first megabyte 0 +d 120e0104 Cyclom-8Y below first megabyte 0 +d 120e0105 Cyclom-8Y above first megabyte 0 +d 120e0200 Cyclades-Z below first megabyte 0 +d 120e0201 Cyclades-Z above first megabyte 0 +d 120e0300 PC300/RSV or /X21 (2 ports) 0 +d 120e0301 PC300/RSV or /X21 (1 port) 0 +d 120e0310 PC300/TE (2 ports) 0 +d 120e0311 PC300/TE (1 port) 0 +d 120e0320 PC300/TE-M (2 ports) 0 +d 120e0321 PC300/TE-M (1 port) 0 +d 120e0400 PC400 0 +v 120f Essential Communications 0 +d 120f0001 Roadrunner serial HIPPI 0 +v 1210 Hyperparallel Technologies 0 +v 1211 Braintech Inc 0 +v 1212 Kingston Technology Corp. 0 +v 1213 Applied Intelligent Systems, Inc. 0 +v 1214 Performance Technologies, Inc. 0 +v 1215 Interware Co., Ltd 0 +v 1216 Purup Prepress A/S 0 +v 1217 O2 Micro, Inc. 0 +d 12176729 OZ6729 0 +d 1217673a OZ6730 0 +d 12176832 OZ6832/6833 Cardbus Controller 0 +d 12176836 OZ6836/6860 Cardbus Controller 0 +d 12176872 OZ6812 Cardbus Controller 0 +d 12176925 OZ6922 Cardbus Controller 0 +d 12176933 OZ6933 Cardbus Controller 0 +s 1217693310251016 Travelmate 612 TX 0 +d 12176972 OZ6912 Cardbus Controller 0 +s 121769721014020c ThinkPad R30 0 +s 1217697211790001 Magnia Z310 0 +d 12177110 OZ711Mx MultiMediaBay Accelerator 0 +s 12177110103c0890 NC6000 laptop 0 +d 12177112 OZ711EC1/M1 SmartCardBus MultiMediaBay Controller 0 +d 12177113 OZ711EC1 SmartCardBus Controller 0 +d 12177114 OZ711M1 SmartCardBus MultiMediaBay Controller 0 +d 121771e2 OZ711E2 SmartCardBus Controller 0 +d 12177212 OZ711M2 SmartCardBus MultiMediaBay Controller 0 +d 12177213 OZ6933E CardBus Controller 0 +d 12177223 OZ711M3 SmartCardBus MultiMediaBay Controller 0 +s 12177223103c0890 NC6000 laptop 0 +v 1218 Hybricon Corp. 0 +v 1219 First Virtual Corporation 0 +v 121a 3Dfx Interactive, Inc. 0 +d 121a0001 Voodoo 0 +d 121a0002 Voodoo 2 0 +d 121a0003 Voodoo Banshee 0 +s 121a000310920003 Monster Fusion 0 +s 121a000310924000 Monster Fusion 0 +s 121a000310924002 Monster Fusion 0 +s 121a000310924801 Monster Fusion AGP 0 +s 121a000310924803 Monster Fusion AGP 0 +s 121a000310928030 Monster Fusion 0 +s 121a000310928035 Monster Fusion AGP 0 +s 121a000310b00001 Dragon 4000 0 +s 121a000311021018 3D Blaster Banshee VE 0 +s 121a0003121a0001 Voodoo Banshee AGP 0 +s 121a0003121a0003 Voodoo Banshee AGP SGRAM 0 +s 121a0003121a0004 Voodoo Banshee 0 +s 121a0003139c0016 Raven 0 +s 121a0003139c0017 Raven 0 +s 121a000314af0002 Maxi Gamer Phoenix 0 +d 121a0004 Voodoo Banshee [Velocity 100] 0 +d 121a0005 Voodoo 3 0 +s 121a0005121a0004 Voodoo3 AGP 0 +s 121a0005121a0030 Voodoo3 AGP 0 +s 121a0005121a0031 Voodoo3 AGP 0 +s 121a0005121a0034 Voodoo3 AGP 0 +s 121a0005121a0036 Voodoo3 2000 PCI 0 +s 121a0005121a0037 Voodoo3 AGP 0 +s 121a0005121a0038 Voodoo3 AGP 0 +s 121a0005121a003a Voodoo3 AGP 0 +s 121a0005121a0044 Voodoo3 0 +s 121a0005121a004b Velocity 100 0 +s 121a0005121a004c Velocity 200 0 +s 121a0005121a004d Voodoo3 AGP 0 +s 121a0005121a004e Voodoo3 AGP 0 +s 121a0005121a0051 Voodoo3 AGP 0 +s 121a0005121a0052 Voodoo3 AGP 0 +s 121a0005121a0060 Voodoo3 3500 TV (NTSC) 0 +s 121a0005121a0061 Voodoo3 3500 TV (PAL) 0 +s 121a0005121a0062 Voodoo3 3500 TV (SECAM) 0 +d 121a0009 Voodoo 4 / Voodoo 5 0 +s 121a0009121a0003 Voodoo5 PCI 5500 0 +s 121a0009121a0009 Voodoo5 AGP 5500/6000 0 +d 121a0057 Voodoo 3/3000 [Avenger] 0 +v 121b Advanced Telecommunications Modules 0 +v 121c Nippon Texaco., Ltd 0 +v 121d Lippert Automationstechnik GmbH 0 +v 121e CSPI 0 +v 121f Arcus Technology, Inc. 0 +v 1220 Ariel Corporation 0 +d 12201220 AMCC 5933 TMS320C80 DSP/Imaging board 0 +v 1221 Contec Co., Ltd 0 +v 1222 Ancor Communications, Inc. 0 +v 1223 Artesyn Communication Products 0 +d 12230003 PM/Link 0 +d 12230004 PM/T1 0 +d 12230005 PM/E1 0 +d 12230008 PM/SLS 0 +d 12230009 BajaSpan Resource Target 0 +d 1223000a BajaSpan Section 0 0 +d 1223000b BajaSpan Section 1 0 +d 1223000c BajaSpan Section 2 0 +d 1223000d BajaSpan Section 3 0 +d 1223000e PM/PPC 0 +v 1224 Interactive Images 0 +v 1225 Power I/O, Inc. 0 +v 1227 Tech-Source 0 +d 12270006 Raptor GFX 8P 0 +v 1228 Norsk Elektro Optikk A/S 0 +v 1229 Data Kinesis Inc. 0 +v 122a Integrated Telecom 0 +v 122b LG Industrial Systems Co., Ltd 0 +v 122c Sican GmbH 0 +v 122d Aztech System Ltd 0 +d 122d1206 368DSP 0 +d 122d1400 Trident PCI288-Q3DII (NX) 0 +d 122d50dc 3328 Audio 0 +s 122d50dc122d0001 3328 Audio 0 +d 122d80da 3328 Audio 0 +s 122d80da122d0001 3328 Audio 0 +v 122e Xyratex 0 +v 122f Andrew Corporation 0 +v 1230 Fishcamp Engineering 0 +v 1231 Woodward McCoach, Inc. 0 +v 1232 GPT Limited 0 +v 1233 Bus-Tech, Inc. 0 +v 1234 Technical Corp. 0 +v 1235 Risq Modular Systems, Inc. 0 +v 1236 Sigma Designs Corporation 0 +d 12360000 RealMagic64/GX 0 +d 12366401 REALmagic 64/GX (SD 6425) 0 +v 1237 Alta Technology Corporation 0 +v 1238 Adtran 0 +v 1239 3DO Company 0 +v 123a Visicom Laboratories, Inc. 0 +v 123b Seeq Technology, Inc. 0 +v 123c Century Systems, Inc. 0 +v 123d Engineering Design Team, Inc. 0 +d 123d0000 EasyConnect 8/32 0 +d 123d0002 EasyConnect 8/64 0 +d 123d0003 EasyIO 0 +v 123e Simutech, Inc. 0 +v 123f C-Cube Microsystems 0 +d 123f00e4 MPEG 0 +d 123f8120 E4? 0 +s 123f812011bd0006 DV500 E4 0 +s 123f812011bd000a DV500 E4 0 +d 123f8888 Cinemaster C 3.0 DVD Decoder 0 +s 123f888810020001 Cinemaster C 3.0 DVD Decoder 0 +s 123f888810020002 Cinemaster C 3.0 DVD Decoder 0 +s 123f888813280001 Cinemaster C 3.0 DVD Decoder 0 +v 1240 Marathon Technologies Corp. 0 +v 1241 DSC Communications 0 +v 1242 JNI Corporation 0 Formerly Jaycor Networks, Inc. +d 12421560 JNIC-1560 PCI-X Fibre Channel Controller 0 +s 1242156012426562 FCX2-6562 Dual Channel PCI-X Fibre Channel Adapter 0 +s 124215601242656a FCX-6562 PCI-X Fibre Channel Adapter 0 +d 12424643 FCI-1063 Fibre Channel Adapter 0 +d 12426562 FCX2-6562 Dual Channel PCI-X Fibre Channel Adapter 0 +d 1242656a FCX-6562 PCI-X Fibre Channel Adapter 0 +v 1243 Delphax 0 +v 1244 AVM Audiovisuelles MKTG & Computer System GmbH 0 +d 12440700 B1 ISDN 0 +d 12440800 C4 ISDN 0 +d 12440a00 A1 ISDN [Fritz] 0 +s 12440a0012440a00 FRITZ!Card ISDN Controller 0 +d 12440e00 Fritz!PCI v2.0 ISDN 0 +d 12441100 C2 ISDN 0 +d 12441200 T1 ISDN 0 +d 12442700 Fritz!Card DSL SL 0 +d 12442900 Fritz!Card DSL v2.0 0 +v 1245 A.P.D., S.A. 0 +v 1246 Dipix Technologies, Inc. 0 +v 1247 Xylon Research, Inc. 0 +v 1248 Central Data Corporation 0 +v 1249 Samsung Electronics Co., Ltd. 0 +v 124a AEG Electrocom GmbH 0 +v 124b SBS/Greenspring Modular I/O 0 +d 124b0040 PCI-40A or cPCI-200 Quad IndustryPack carrier 0 +s 124b0040124b9080 PCI9080 Bridge 0 +v 124c Solitron Technologies, Inc. 0 +v 124d Stallion Technologies, Inc. 0 +d 124d0000 EasyConnection 8/32 0 +d 124d0002 EasyConnection 8/64 0 +d 124d0003 EasyIO 0 +d 124d0004 EasyConnection/RA 0 +v 124e Cylink 0 +v 124f Infotrend Technology, Inc. 0 +d 124f0041 IFT-2000 Series RAID Controller 0 +v 1250 Hitachi Microcomputer System Ltd 0 +v 1251 VLSI Solutions Oy 0 +v 1253 Guzik Technical Enterprises 0 +v 1254 Linear Systems Ltd. 0 +v 1255 Optibase Ltd 0 +d 12551110 MPEG Forge 0 +d 12551210 MPEG Fusion 0 +d 12552110 VideoPlex 0 +d 12552120 VideoPlex CC 0 +d 12552130 VideoQuest 0 +v 1256 Perceptive Solutions, Inc. 0 +d 12564201 PCI-2220I 0 +d 12564401 PCI-2240I 0 +d 12565201 PCI-2000 0 +v 1257 Vertex Networks, Inc. 0 +v 1258 Gilbarco, Inc. 0 +v 1259 Allied Telesyn International 0 +d 12592560 AT-2560 Fast Ethernet Adapter (i82557B) 0 +d 1259a117 RTL81xx Fast Ethernet 0 +d 1259a120 21x4x DEC-Tulip compatible 10/100 Ethernet 0 +v 125a ABB Power Systems 0 +v 125b Asix Electronics Corporation 0 +d 125b1400 ALFA GFC2204 Fast Ethernet 0 +v 125c Aurora Technologies, Inc. 0 +d 125c0101 Saturn 4520P 0 +d 125c0640 Aries 16000P 0 +v 125d ESS Technology 0 +d 125d0000 ES336H Fax Modem (Early Model) 0 +d 125d1948 Solo? 0 +d 125d1968 ES1968 Maestro 2 0 +s 125d196810280085 ES1968 Maestro-2 PCI 0 +s 125d196810338051 ES1968 Maestro-2 Audiodrive 0 +d 125d1969 ES1969 Solo-1 Audiodrive 0 +s 125d196910140166 ES1969 SOLO-1 AudioDrive on IBM Aptiva Mainboard 0 +s 125d1969125d8888 Solo-1 Audio Adapter 0 +d 125d1978 ES1978 Maestro 2E 0 +s 125d19780e11b112 Armada M700/E500 0 +s 125d19781033803c ES1978 Maestro-2E Audiodrive 0 +s 125d197810338058 ES1978 Maestro-2E Audiodrive 0 +s 125d197810924000 Monster Sound MX400 0 +s 125d197811790001 ES1978 Maestro-2E Audiodrive 0 +d 125d1988 ES1988 Allegro-1 0 +s 125d198810924100 Sonic Impact S100 0 +s 125d1988125d1988 ESS Allegro-1 Audiodrive 0 +d 125d1989 ESS Modem 0 +s 125d1989125d1989 ESS Modem 0 +d 125d1998 ES1983S Maestro-3i PCI Audio Accelerator 0 +s 125d1998102800b1 Latitude C600 0 +s 125d1998102800e6 ES1983S Maestro-3i (Dell Inspiron 8100) 0 +d 125d1999 ES1983S Maestro-3i PCI Modem Accelerator 0 +d 125d199a ES1983S Maestro-3i PCI Audio Accelerator 0 +d 125d199b ES1983S Maestro-3i PCI Modem Accelerator 0 +d 125d2808 ES336H Fax Modem (Later Model) 0 +d 125d2838 ES2838/2839 SuperLink Modem 0 +d 125d2898 ES2898 Modem 0 +s 125d2898125d0424 ES56-PI Data Fax Modem 0 +s 125d2898125d0425 ES56T-PI Data Fax Modem 0 +s 125d2898125d0426 ES56V-PI Data Fax Modem 0 +s 125d2898125d0427 VW-PI Data Fax Modem 0 +s 125d2898125d0428 ES56ST-PI Data Fax Modem 0 +s 125d2898125d0429 ES56SV-PI Data Fax Modem 0 +s 125d2898147ac001 ES56-PI Data Fax Modem 0 +s 125d289814fe0428 ES56-PI Data Fax Modem 0 +s 125d289814fe0429 ES56-PI Data Fax Modem 0 +v 125e Specialvideo Engineering SRL 0 +v 125f Concurrent Technologies, Inc. 0 +v 1260 Intersil Corporation 0 +d 12603872 Prism 2.5 Wavelan chipset 0 +s 1260387214680202 LAN-Express IEEE 802.11b Wireless LAN 0 +d 12603873 Prism 2.5 Wavelan chipset 0 +s 1260387311863501 DWL-520 Wireless PCI Adapter 0 +s 1260387311863700 DWL-520 Wireless PCI Adapter, Rev E1 0 +s 1260387313854105 MA311 802.11b wireless adapter 0 +s 1260387316680414 HWP01170-01 802.11b PCI Wireless Adapter 0 +s 1260387316a51601 AIR.mate PC-400 PCI Wireless LAN Adapter 0 +s 1260387317373874 WMP11 Wireless 802.11b PCI Adapter 0 +s 1260387380862513 Wireless 802.11b MiniPCI Adapter 0 +d 12603886 ISL3886 [Prism Javelin/Prism Xbow] 0 +s 1260388617cf0037 Z-Com XG-901 and clones Wireless Adapter 0 +d 12603890 Intersil ISL3890 [Prism GT/Prism Duette] 0 +s 1260389010b82802 SMC2802W Wireless PCI Adapter 0 +s 1260389010b82835 SMC2835W Wireless Cardbus Adapter 0 +s 1260389010b8a835 SMC2835W V2 Wireless Cardbus Adapter 0 +s 126038901113ee03 SMC2802W V2 Wireless PCI Adapter 0 +s 1260389011863202 DWL-G650 A1 Wireless Adapter 0 +s 126038901259c104 CG-WLCB54GT Wireless Adapter 0 +s 1260389013854800 WG511 Wireless Adapter 0 +s 1260389016a51605 ALLNET ALL0271 Wireless PCI Adapter 0 +s 1260389017cf0014 Z-Com XG-600 and clones Wireless Adapter 0 +s 1260389017cf0020 Z-Com XG-900 and clones Wireless Adapter 0 +d 12608130 HMP8130 NTSC/PAL Video Decoder 0 +d 12608131 HMP8131 NTSC/PAL Video Decoder 0 +v 1261 Matsushita-Kotobuki Electronics Industries, Ltd. 0 +v 1262 ES Computer Company, Ltd. 0 +v 1263 Sonic Solutions 0 +v 1264 Aval Nagasaki Corporation 0 +v 1265 Casio Computer Co., Ltd. 0 +v 1266 Microdyne Corporation 0 +d 12660001 NE10/100 Adapter (i82557B) 0 +d 12661910 NE2000Plus (RT8029) Ethernet Adapter 0 +s 1266191012661910 NE2000Plus Ethernet Adapter 0 +v 1267 S. A. Telecommunications 0 +d 12675352 PCR2101 0 +d 12675a4b Telsat Turbo 0 +v 1268 Tektronix 0 +v 1269 Thomson-CSF/TTM 0 +v 126a Lexmark International, Inc. 0 +v 126b Adax, Inc. 0 +v 126c Northern Telecom 0 +d 126c1211 10/100BaseTX [RTL81xx] 0 +d 126c126c 802.11b Wireless Ethernet Adapter 0 +v 126d Splash Technology, Inc. 0 +v 126e Sumitomo Metal Industries, Ltd. 0 +v 126f Silicon Motion, Inc. 0 +d 126f0501 SM501 VoyagerGX 0 +d 126f0710 SM710 LynxEM 0 +d 126f0712 SM712 LynxEM+ 0 +d 126f0720 SM720 Lynx3DM 0 +d 126f0730 SM731 Cougar3DR 0 +d 126f0810 SM810 LynxE 0 +d 126f0811 SM811 LynxE 0 +d 126f0820 SM820 Lynx3D 0 +d 126f0910 SM910 0 +v 1270 Olympus Optical Co., Ltd. 0 +v 1271 GW Instruments 0 +v 1272 Telematics International 0 +v 1273 Hughes Network Systems 0 +d 12730002 DirecPC 0 +v 1274 Ensoniq 0 +d 12741171 ES1373 [AudioPCI] (also Creative Labs CT5803) 0 +d 12741371 ES1371 [AudioPCI-97] 0 +s 127413710e110024 AudioPCI on Motherboard Compaq Deskpro 0 +s 127413710e11b1a7 ES1371, ES1373 AudioPCI 0 +s 12741371103380ac ES1371, ES1373 AudioPCI 0 +s 1274137110421854 Tazer 0 +s 12741371107b8054 Tabor2 0 +s 1274137112741371 Creative Sound Blaster AudioPCI64V, AudioPCI128 0 +s 1274137114626470 ES1371, ES1373 AudioPCI On Motherboard MS-6147 1.1A 0 +s 1274137114626560 ES1371, ES1373 AudioPCI On Motherboard MS-6156 1.10 0 +s 1274137114626630 ES1371, ES1373 AudioPCI On Motherboard MS-6163BX 1.0A 0 +s 1274137114626631 ES1371, ES1373 AudioPCI On Motherboard MS-6163VIA 1.0A 0 +s 1274137114626632 ES1371, ES1373 AudioPCI On Motherboard MS-6163BX 2.0A 0 +s 1274137114626633 ES1371, ES1373 AudioPCI On Motherboard MS-6163VIA 2.0A 0 +s 1274137114626820 ES1371, ES1373 AudioPCI On Motherboard MS-6182 1.00 0 +s 1274137114626822 ES1371, ES1373 AudioPCI On Motherboard MS-6182 1.00A 0 +s 1274137114626830 ES1371, ES1373 AudioPCI On Motherboard MS-6183 1.00 0 +s 1274137114626880 ES1371, ES1373 AudioPCI On Motherboard MS-6188 1.00 0 +s 1274137114626900 ES1371, ES1373 AudioPCI On Motherboard MS-6190 1.00 0 +s 1274137114626910 ES1371, ES1373 AudioPCI On Motherboard MS-6191 0 +s 1274137114626930 ES1371, ES1373 AudioPCI On Motherboard MS-6193 0 +s 1274137114626990 ES1371, ES1373 AudioPCI On Motherboard MS-6199BX 2.0A 0 +s 1274137114626991 ES1371, ES1373 AudioPCI On Motherboard MS-6199VIA 2.0A 0 +s 1274137114a42077 ES1371, ES1373 AudioPCI On Motherboard KR639 0 +s 1274137114a42105 ES1371, ES1373 AudioPCI On Motherboard MR800 0 +s 1274137114a42107 ES1371, ES1373 AudioPCI On Motherboard MR801 0 +s 1274137114a42172 ES1371, ES1373 AudioPCI On Motherboard DR739 0 +s 1274137115099902 ES1371, ES1373 AudioPCI On Motherboard KW11 0 +s 1274137115099903 ES1371, ES1373 AudioPCI On Motherboard KW31 0 +s 1274137115099904 ES1371, ES1373 AudioPCI On Motherboard KA11 0 +s 1274137115099905 ES1371, ES1373 AudioPCI On Motherboard KC13 0 +s 12741371152d8801 ES1371, ES1373 AudioPCI On Motherboard CP810E 0 +s 12741371152d8802 ES1371, ES1373 AudioPCI On Motherboard CP810 0 +s 12741371152d8803 ES1371, ES1373 AudioPCI On Motherboard P3810E 0 +s 12741371152d8804 ES1371, ES1373 AudioPCI On Motherboard P3810-S 0 +s 12741371152d8805 ES1371, ES1373 AudioPCI On Motherboard P3820-S 0 +s 12741371270f2001 ES1371, ES1373 AudioPCI On Motherboard 6CTR 0 +s 12741371270f2200 ES1371, ES1373 AudioPCI On Motherboard 6WTX 0 +s 12741371270f3000 ES1371, ES1373 AudioPCI On Motherboard 6WSV 0 +s 12741371270f3100 ES1371, ES1373 AudioPCI On Motherboard 6WIV2 0 +s 12741371270f3102 ES1371, ES1373 AudioPCI On Motherboard 6WIV 0 +s 12741371270f7060 ES1371, ES1373 AudioPCI On Motherboard 6ASA2 0 +s 1274137180864249 ES1371, ES1373 AudioPCI On Motherboard BI440ZX 0 +s 127413718086424c ES1371, ES1373 AudioPCI On Motherboard BL440ZX 0 +s 127413718086425a ES1371, ES1373 AudioPCI On Motherboard BZ440ZX 0 +s 1274137180864341 ES1371, ES1373 AudioPCI On Motherboard Cayman 0 +s 1274137180864343 ES1371, ES1373 AudioPCI On Motherboard Cape Cod 0 +s 1274137180864649 ES1371, ES1373 AudioPCI On Motherboard Fire Island 0 +s 127413718086464a ES1371, ES1373 AudioPCI On Motherboard FJ440ZX 0 +s 1274137180864d4f ES1371, ES1373 AudioPCI On Motherboard Montreal 0 +s 1274137180864f43 ES1371, ES1373 AudioPCI On Motherboard OC440LX 0 +s 1274137180865243 ES1371, ES1373 AudioPCI On Motherboard RC440BX 0 +s 1274137180865352 ES1371, ES1373 AudioPCI On Motherboard SunRiver 0 +s 1274137180865643 ES1371, ES1373 AudioPCI On Motherboard Vancouver 0 +s 1274137180865753 ES1371, ES1373 AudioPCI On Motherboard WS440BX 0 +d 12745000 ES1370 [AudioPCI] 0 +d 12745880 5880 AudioPCI 0 +s 1274588012742000 Creative Sound Blaster AudioPCI128 0 +s 1274588012742003 Creative SoundBlaster AudioPCI 128 0 +s 1274588012745880 Creative Sound Blaster AudioPCI128 0 +s 1274588012748001 Sound Blaster 16PCI 4.1ch 0 +s 127458801458a000 5880 AudioPCI On Motherboard 6OXET 0 +s 1274588014626880 5880 AudioPCI On Motherboard MS-6188 1.00 0 +s 12745880270f2001 5880 AudioPCI On Motherboard 6CTR 0 +s 12745880270f2200 5880 AudioPCI On Motherboard 6WTX 0 +s 12745880270f7040 5880 AudioPCI On Motherboard 6ATA4 0 +v 1275 Network Appliance Corporation 0 +v 1276 Switched Network Technologies, Inc. 0 +v 1277 Comstream 0 +v 1278 Transtech Parallel Systems Ltd. 0 +d 12780701 TPE3/TM3 PowerPC Node 0 +d 12780710 TPE5 PowerPC PCI board 0 +v 1279 Transmeta Corporation 0 +d 12790295 Northbridge 0 +d 12790395 LongRun Northbridge 0 +d 12790396 SDRAM controller 0 +d 12790397 BIOS scratchpad 0 +v 127a Rockwell International 0 +d 127a1002 HCF 56k Data/Fax Modem 0 +s 127a10021092094c SupraExpress 56i PRO [Diamond SUP2380] 0 +s 127a1002122d4002 HPG / MDP3858-U 0 +s 127a1002122d4005 MDP3858-E 0 +s 127a1002122d4007 MDP3858-A/-NZ 0 +s 127a1002122d4012 MDP3858-SA 0 +s 127a1002122d4017 MDP3858-W 0 +s 127a1002122d4018 MDP3858-W 0 +s 127a1002127a1002 Rockwell 56K D/F HCF Modem 0 +d 127a1003 HCF 56k Data/Fax Modem 0 +s 127a10030e11b0bc 229-DF Zephyr 0 +s 127a10030e11b114 229-DF Cheetah 0 +s 127a10031033802b 229-DF 0 +s 127a100313df1003 PCI56RX Modem 0 +s 127a100313e00117 IBM 0 +s 127a100313e00147 IBM F-1156IV+/R3 Spain V.90 Modem 0 +s 127a100313e00197 IBM 0 +s 127a100313e001c7 IBM F-1156IV+/R3 WW V.90 Modem 0 +s 127a100313e001f7 IBM 0 +s 127a100314361003 IBM 0 +s 127a100314361103 IBM 5614PM3G V.90 Modem 0 +s 127a100314361602 Compaq 229-DF Ducati 0 +d 127a1004 HCF 56k Data/Fax/Voice Modem 0 +s 127a100410481500 MicroLink 56k Modem 0 +s 127a100410cf1059 Fujitsu 229-DFRT 0 +d 127a1005 HCF 56k Data/Fax/Voice/Spkp (w/Handset) Modem 0 +s 127a100510338029 229-DFSV 0 +s 127a100510338054 Modem 0 +s 127a100510cf103c Fujitsu 0 +s 127a100510cf1055 Fujitsu 229-DFSV 0 +s 127a100510cf1056 Fujitsu 229-DFSV 0 +s 127a1005122d4003 MDP3858SP-U 0 +s 127a1005122d4006 Packard Bell MDP3858V-E 0 +s 127a1005122d4008 MDP3858SP-A/SP-NZ 0 +s 127a1005122d4009 MDP3858SP-E 0 +s 127a1005122d4010 MDP3858V-U 0 +s 127a1005122d4011 MDP3858SP-SA 0 +s 127a1005122d4013 MDP3858V-A/V-NZ 0 +s 127a1005122d4015 MDP3858SP-W 0 +s 127a1005122d4016 MDP3858V-W 0 +s 127a1005122d4019 MDP3858V-SA 0 +s 127a100513df1005 PCI56RVP Modem 0 +s 127a100513e00187 IBM 0 +s 127a100513e001a7 IBM 0 +s 127a100513e001b7 IBM DF-1156IV+/R3 Spain V.90 Modem 0 +s 127a100513e001d7 IBM DF-1156IV+/R3 WW V.90 Modem 0 +s 127a100514361005 IBM 0 +s 127a100514361105 IBM 0 +s 127a100514371105 IBM 5614PS3G V.90 Modem 0 +d 127a1022 HCF 56k Modem 0 +s 127a102214361303 M3-5614PM3G V.90 Modem 0 +d 127a1023 HCF 56k Data/Fax Modem 0 +s 127a1023122d4020 Packard Bell MDP3858-WE 0 +s 127a1023122d4023 MDP3858-UE 0 +s 127a102313e00247 IBM F-1156IV+/R6 Spain V.90 Modem 0 +s 127a102313e00297 IBM 0 +s 127a102313e002c7 IBM F-1156IV+/R6 WW V.90 Modem 0 +s 127a102314361203 IBM 0 +s 127a102314361303 IBM 0 +d 127a1024 HCF 56k Data/Fax/Voice Modem 0 +d 127a1025 HCF 56k Data/Fax/Voice/Spkp (w/Handset) Modem 0 +s 127a102510cf106a Fujitsu 235-DFSV 0 +s 127a1025122d4021 Packard Bell MDP3858V-WE 0 +s 127a1025122d4022 MDP3858SP-WE 0 +s 127a1025122d4024 MDP3858V-UE 0 +s 127a1025122d4025 MDP3858SP-UE 0 +d 127a1026 HCF 56k PCI Speakerphone Modem 0 +d 127a1032 HCF 56k Modem 0 +d 127a1033 HCF 56k Modem 0 +d 127a1034 HCF 56k Modem 0 +d 127a1035 HCF 56k PCI Speakerphone Modem 0 +d 127a1036 HCF 56k Modem 0 +d 127a1085 HCF 56k Volcano PCI Modem 0 +d 127a2005 HCF 56k Data/Fax Modem 0 +s 127a2005104d8044 229-DFSV 0 +s 127a2005104d8045 229-DFSV 0 +s 127a2005104d8055 PBE/Aztech 235W-DFSV 0 +s 127a2005104d8056 235-DFSV 0 +s 127a2005104d805a Modem 0 +s 127a2005104d805f Modem 0 +s 127a2005104d8074 Modem 0 +d 127a2013 HSF 56k Data/Fax Modem 0 +s 127a201311790001 Modem 0 +s 127a20131179ff00 Modem 0 +d 127a2014 HSF 56k Data/Fax/Voice Modem 0 +s 127a201410cf1057 Fujitsu Citicorp III 0 +s 127a2014122d4050 MSP3880-U 0 +s 127a2014122d4055 MSP3880-W 0 +d 127a2015 HSF 56k Data/Fax/Voice/Spkp (w/Handset) Modem 0 +s 127a201510cf1063 Fujitsu 0 +s 127a201510cf1064 Fujitsu 0 +s 127a201514682015 Fujitsu 0 +d 127a2016 HSF 56k Data/Fax/Voice/Spkp Modem 0 +s 127a2016122d4051 MSP3880V-W 0 +s 127a2016122d4052 MSP3880SP-W 0 +s 127a2016122d4054 MSP3880V-U 0 +s 127a2016122d4056 MSP3880SP-U 0 +s 127a2016122d4057 MSP3880SP-A 0 +d 127a4311 Riptide HSF 56k PCI Modem 0 +s 127a4311127a4311 Ring Modular? Riptide HSF RT HP Dom 0 +s 127a431113e00210 HP-GVC 0 +d 127a4320 Riptide PCI Audio Controller 0 +s 127a432012354320 Riptide PCI Audio Controller 0 +d 127a4321 Riptide HCF 56k PCI Modem 0 +s 127a432112354321 Hewlett Packard DF 0 +s 127a432112354324 Hewlett Packard DF 0 +s 127a432113e00210 Hewlett Packard DF 0 +s 127a4321144d2321 Riptide 0 +d 127a4322 Riptide PCI Game Controller 0 +s 127a432212354322 Riptide PCI Game Controller 0 +d 127a8234 RapidFire 616X ATM155 Adapter 0 +s 127a8234108d0022 RapidFire 616X ATM155 Adapter 0 +s 127a8234108d0027 RapidFire 616X ATM155 Adapter 0 +v 127b Pixera Corporation 0 +v 127c Crosspoint Solutions, Inc. 0 +v 127d Vela Research 0 +v 127e Winnov, L.P. 0 +v 127f Fujifilm 0 +v 1280 Photoscript Group Ltd. 0 +v 1281 Yokogawa Electric Corporation 0 +v 1282 Davicom Semiconductor, Inc. 0 +d 12829009 Ethernet 100/10 MBit 0 +d 12829100 21x4x DEC-Tulip compatible 10/100 Ethernet 0 +d 12829102 21x4x DEC-Tulip compatible 10/100 Ethernet 0 +d 12829132 Ethernet 100/10 MBit 0 +v 1283 Integrated Technology Express, Inc. 0 +d 1283673a IT8330G 0 +d 12838212 IT/ITE8212 Dual channel ATA RAID controller (PCI version seems to be IT8212, embedded seems to be ITE8212) 0 +s 1283821212830001 IT/ITE8212 Dual channel ATA RAID controller 0 +d 12838330 IT8330G 0 +d 12838872 IT8874F PCI Dual Serial Port Controller 0 +d 12838888 IT8888F PCI to ISA Bridge with SMB 0 +d 12838889 IT8889F PCI to ISA Bridge 0 +d 1283e886 IT8330G 0 +v 1284 Sahara Networks, Inc. 0 +v 1285 Platform Technologies, Inc. 0 +d 12850100 AGOGO sound chip (aka ESS Maestro 1) 0 +v 1286 Mazet GmbH 0 +v 1287 M-Pact, Inc. 0 +d 1287001e LS220D DVD Decoder 0 +d 1287001f LS220C DVD Decoder 0 +v 1288 Timestep Corporation 0 +v 1289 AVC Technology, Inc. 0 +v 128a Asante Technologies, Inc. 0 +v 128b Transwitch Corporation 0 +v 128c Retix Corporation 0 +v 128d G2 Networks, Inc. 0 +d 128d0021 ATM155 Adapter 0 +v 128e Hoontech Corporation/Samho Multi Tech Ltd. 0 +d 128e0008 ST128 WSS/SB 0 +d 128e0009 ST128 SAM9407 0 +d 128e000a ST128 Game Port 0 +d 128e000b ST128 MPU Port 0 +d 128e000c ST128 Ctrl Port 0 +v 128f Tateno Dennou, Inc. 0 +v 1290 Sord Computer Corporation 0 +v 1291 NCS Computer Italia 0 +v 1292 Tritech Microelectronics Inc 0 +v 1293 Media Reality Technology 0 +v 1294 Rhetorex, Inc. 0 +v 1295 Imagenation Corporation 0 +v 1296 Kofax Image Products 0 +v 1297 Holco Enterprise Co, Ltd/Shuttle Computer 0 +v 1298 Spellcaster Telecommunications Inc. 0 +v 1299 Knowledge Technology Lab. 0 +v 129a VMetro, inc. 0 +d 129a0615 PBT-615 PCI-X Bus Analyzer 0 +v 129b Image Access 0 +v 129c Jaycor 0 +v 129d Compcore Multimedia, Inc. 0 +v 129e Victor Company of Japan, Ltd. 0 +v 129f OEC Medical Systems, Inc. 0 +v 12a0 Allen-Bradley Company 0 +v 12a1 Simpact Associates, Inc. 0 +v 12a2 Newgen Systems Corporation 0 +v 12a3 Lucent Technologies 0 +d 12a38105 T8105 H100 Digital Switch 0 +v 12a4 NTT Electronics Technology Company 0 +v 12a5 Vision Dynamics Ltd. 0 +v 12a6 Scalable Networks, Inc. 0 +v 12a7 AMO GmbH 0 +v 12a8 News Datacom 0 +v 12a9 Xiotech Corporation 0 +v 12aa SDL Communications, Inc. 0 +v 12ab Yuan Yuan Enterprise Co., Ltd. 0 +d 12ab0002 AU8830 [Vortex2] Based Sound Card With A3D Support 0 +d 12ab3000 MPG-200C PCI DVD Decoder Card 0 +v 12ac Measurex Corporation 0 +v 12ad Multidata GmbH 0 +v 12ae Alteon Networks Inc. 0 +d 12ae0001 AceNIC Gigabit Ethernet 0 +s 12ae000110140104 Gigabit Ethernet-SX PCI Adapter 0 +s 12ae000112ae0001 Gigabit Ethernet-SX (Universal) 0 +s 12ae000114100104 Gigabit Ethernet-SX PCI Adapter 0 +d 12ae0002 AceNIC Gigabit Ethernet (Copper) 0 +s 12ae000210a98002 Acenic Gigabit Ethernet 0 +s 12ae000212ae0002 Gigabit Ethernet-T (3C986-T) 0 +d 12ae00fa Farallon PN9100-T Gigabit Ethernet 0 +v 12af TDK USA Corp 0 +v 12b0 Jorge Scientific Corp 0 +v 12b1 GammaLink 0 +v 12b2 General Signal Networks 0 +v 12b3 Inter-Face Co Ltd 0 +v 12b4 FutureTel Inc 0 +v 12b5 Granite Systems Inc. 0 +v 12b6 Natural Microsystems 0 +v 12b7 Cognex Modular Vision Systems Div. - Acumen Inc. 0 +v 12b8 Korg 0 +v 12b9 3Com Corp, Modem Division (formerly US Robotics) 0 +d 12b91006 WinModem 0 +s 12b9100612b9005c USR 56k Internal Voice WinModem (Model 3472) 0 +s 12b9100612b9005e USR 56k Internal WinModem (Models 662975) 0 +s 12b9100612b90062 USR 56k Internal Voice WinModem (Model 662978) 0 +s 12b9100612b90068 USR 56k Internal Voice WinModem (Model 5690) 0 +s 12b9100612b9007a USR 56k Internal Voice WinModem (Model 662974) 0 +s 12b9100612b9007f USR 56k Internal WinModem (Models 5698, 5699) 0 +s 12b9100612b90080 USR 56k Internal WinModem (Models 2975, 3528) 0 +s 12b9100612b90081 USR 56k Internal Voice WinModem (Models 2974, 3529) 0 +s 12b9100612b90091 USR 56k Internal Voice WinModem (Model 2978) 0 +d 12b91007 USR 56k Internal WinModem 0 +s 12b9100712b900a3 USR 56k Internal WinModem (Model 3595) 0 +d 12b91008 56K FaxModem Model 5610 0 +s 12b9100812b900a2 USR 56k Internal FAX Modem (Model 2977) 0 +s 12b9100812b900aa USR 56k Internal Voice Modem (Model 2976) 0 +s 12b9100812b900ab USR 56k Internal Voice Modem (Model 5609) 0 +s 12b9100812b900ac USR 56k Internal Voice Modem (Model 3298) 0 +s 12b9100812b900ad USR 56k Internal FAX Modem (Model 5610) 0 +v 12ba BittWare, Inc. 0 +v 12bb Nippon Unisoft Corporation 0 +v 12bc Array Microsystems 0 +v 12bd Computerm Corp. 0 +v 12be Anchor Chips Inc. 0 +d 12be3041 AN3041Q CO-MEM 0 +d 12be3042 AN3042Q CO-MEM Lite 0 +s 12be304212be3042 Anchor Chips Lite Evaluation Board 0 +v 12bf Fujifilm Microdevices 0 +v 12c0 Infimed 0 +v 12c1 GMM Research Corp 0 +v 12c2 Mentec Limited 0 +v 12c3 Holtek Microelectronics Inc 0 +d 12c30058 PCI NE2K Ethernet 0 +d 12c35598 PCI NE2K Ethernet 0 +v 12c4 Connect Tech Inc 0 +v 12c5 Picture Elements Incorporated 0 +d 12c5007e Imaging/Scanning Subsystem Engine 0 +d 12c5007f Imaging/Scanning Subsystem Engine 0 +d 12c50081 PCIVST [Grayscale Thresholding Engine] 0 +d 12c50085 Video Simulator/Sender 0 +d 12c50086 THR2 Multi-scale Thresholder 0 +v 12c6 Mitani Corporation 0 +v 12c7 Dialogic Corp 0 +v 12c8 G Force Co, Ltd 0 +v 12c9 Gigi Operations 0 +v 12ca Integrated Computing Engines 0 +v 12cb Antex Electronics Corporation 0 +v 12cc Pluto Technologies International 0 +v 12cd Aims Lab 0 +v 12ce Netspeed Inc. 0 +v 12cf Prophet Systems, Inc. 0 +v 12d0 GDE Systems, Inc. 0 +v 12d1 PSITech 0 +v 12d2 NVidia / SGS Thomson (Joint Venture) 0 +d 12d20008 NV1 0 +d 12d20009 DAC64 0 +d 12d20018 Riva128 0 +s 12d2001810480c10 VICTORY Erazor 0 +s 12d20018107b8030 STB Velocity 128 0 +s 12d2001810920350 Viper V330 0 +s 12d2001810921092 Viper V330 0 +s 12d2001810b41b1b STB Velocity 128 0 +s 12d2001810b41b1d STB Velocity 128 0 +s 12d2001810b41b1e STB Velocity 128, PAL TV-Out 0 +s 12d2001810b41b20 STB Velocity 128 Sapphire 0 +s 12d2001810b41b21 STB Velocity 128 0 +s 12d2001810b41b22 STB Velocity 128 AGP, NTSC TV-Out 0 +s 12d2001810b41b23 STB Velocity 128 AGP, PAL TV-Out 0 +s 12d2001810b41b27 STB Velocity 128 DVD 0 +s 12d2001810b41b88 MVP Pro 128 0 +s 12d2001810b4222a STB Velocity 128 AGP 0 +s 12d2001810b42230 STB Velocity 128 0 +s 12d2001810b42232 STB Velocity 128 0 +s 12d2001810b42235 STB Velocity 128 AGP 0 +s 12d200182a1554a3 3DVision-SAGP / 3DexPlorer 3000 0 +d 12d20019 Riva128ZX 0 +d 12d20020 TNT 0 +d 12d20028 TNT2 0 +d 12d20029 UTNT2 0 +d 12d2002c VTNT2 0 +d 12d200a0 ITNT2 0 +v 12d3 Vingmed Sound A/S 0 +v 12d4 Ulticom (Formerly DGM&S) 0 +d 12d40200 T1 Card 0 +v 12d5 Equator Technologies Inc 0 +v 12d6 Analogic Corp 0 +v 12d7 Biotronic SRL 0 +v 12d8 Pericom Semiconductor 0 +v 12d9 Aculab PLC 0 +d 12d90002 PCI Prosody 0 +d 12d90004 cPCI Prosody 0 +d 12d90005 Aculab E1/T1 PCI card 0 +v 12da True Time Inc. 0 +v 12db Annapolis Micro Systems, Inc 0 +v 12dc Symicron Computer Communication Ltd. 0 +v 12dd Management Graphics 0 +v 12de Rainbow Technologies 0 +d 12de0200 CryptoSwift CS200 0 +v 12df SBS Technologies Inc 0 +v 12e0 Chase Research 0 +d 12e00010 ST16C654 Quad UART 0 +d 12e00020 ST16C654 Quad UART 0 +d 12e00030 ST16C654 Quad UART 0 +v 12e1 Nintendo Co, Ltd 0 +v 12e2 Datum Inc. Bancomm-Timing Division 0 +v 12e3 Imation Corp - Medical Imaging Systems 0 +v 12e4 Brooktrout Technology Inc 0 +v 12e5 Apex Semiconductor Inc 0 +v 12e6 Cirel Systems 0 +v 12e7 Sunsgroup Corporation 0 +v 12e8 Crisc Corp 0 +v 12e9 GE Spacenet 0 +v 12ea Zuken 0 +v 12eb Aureal Semiconductor 0 +d 12eb0001 Vortex 1 0 +s 12eb0001104d8036 AU8820 Vortex Digital Audio Processor 0 +s 12eb000110922000 Sonic Impact A3D 0 +s 12eb000110922100 Sonic Impact A3D 0 +s 12eb000110922110 Sonic Impact A3D 0 +s 12eb000110922200 Sonic Impact A3D 0 +s 12eb0001122d1002 AU8820 Vortex Digital Audio Processor 0 +s 12eb000112eb0001 AU8820 Vortex Digital Audio Processor 0 +s 12eb000150533355 Montego 0 +d 12eb0002 Vortex 2 0 +s 12eb0002104d8049 AU8830 Vortex 3D Digital Audio Processor 0 +s 12eb0002104d807b AU8830 Vortex 3D Digital Audio Processor 0 +s 12eb000210923000 Monster Sound II 0 +s 12eb000210923001 Monster Sound II 0 +s 12eb000210923002 Monster Sound II 0 +s 12eb000210923003 Monster Sound II 0 +s 12eb000210923004 Monster Sound II 0 +s 12eb000212eb0001 AU8830 Vortex 3D Digital Audio Processor 0 +s 12eb000212eb0002 AU8830 Vortex 3D Digital Audio Processor 0 +s 12eb000212eb0088 AU8830 Vortex 3D Digital Audio Processor 0 +s 12eb0002144d3510 AU8830 Vortex 3D Digital Audio Processor 0 +s 12eb000250533356 Montego II 0 +d 12eb0003 AU8810 Vortex Digital Audio Processor 0 +s 12eb0003104d8049 AU8810 Vortex Digital Audio Processor 0 +s 12eb0003104d8077 AU8810 Vortex Digital Audio Processor 0 +s 12eb0003109f1000 AU8810 Vortex Digital Audio Processor 0 +s 12eb000312eb0003 AU8810 Vortex Digital Audio Processor 0 +s 12eb000314626780 AU8810 Vortex Digital Audio Processor 0 +s 12eb000314a42073 AU8810 Vortex Digital Audio Processor 0 +s 12eb000314a42091 AU8810 Vortex Digital Audio Processor 0 +s 12eb000314a42104 AU8810 Vortex Digital Audio Processor 0 +s 12eb000314a42106 AU8810 Vortex Digital Audio Processor 0 +d 12eb8803 Vortex 56k Software Modem 0 +s 12eb880312eb8803 Vortex 56k Software Modem 0 +v 12ec 3A International, Inc. 0 +v 12ed Optivision Inc. 0 +v 12ee Orange Micro 0 +v 12ef Vienna Systems 0 +v 12f0 Pentek 0 +v 12f1 Sorenson Vision Inc 0 +v 12f2 Gammagraphx, Inc. 0 +v 12f3 Radstone Technology 0 +v 12f4 Megatel 0 +v 12f5 Forks 0 +v 12f6 Dawson France 0 +v 12f7 Cognex 0 +v 12f8 Electronic Design GmbH 0 +d 12f80002 VideoMaker 0 +v 12f9 Four Fold Ltd 0 +v 12fb Spectrum Signal Processing 0 +v 12fc Capital Equipment Corp 0 +v 12fd I2S 0 +v 12fe ESD Electronic System Design GmbH 0 +v 12ff Lexicon 0 +v 1300 Harman International Industries Inc 0 +v 1302 Computer Sciences Corp 0 +v 1303 Innovative Integration 0 +v 1304 Juniper Networks 0 +v 1305 Netphone, Inc 0 +v 1306 Duet Technologies 0 +v 1307 Measurement Computing 0 Formerly ComputerBoards +d 13070001 PCI-DAS1602/16 0 +d 1307000b PCI-DIO48H 0 +d 1307000c PCI-PDISO8 0 +d 1307000d PCI-PDISO16 0 +d 1307000f PCI-DAS1200 0 +d 13070010 PCI-DAS1602/12 0 +d 13070014 PCI-DIO24H 0 +d 13070015 PCI-DIO24H/CTR3 0 +d 13070016 PCI-DIO48H/CTR15 0 +d 13070017 PCI-DIO96H 0 +d 13070018 PCI-CTR05 0 +d 13070019 PCI-DAS1200/JR 0 +d 1307001a PCI-DAS1001 0 +d 1307001b PCI-DAS1002 0 +d 1307001c PCI-DAS1602JR/16 0 +d 1307001d PCI-DAS6402/16 0 +d 1307001e PCI-DAS6402/12 0 +d 1307001f PCI-DAS16/M1 0 +d 13070020 PCI-DDA02/12 0 +d 13070021 PCI-DDA04/12 0 +d 13070022 PCI-DDA08/12 0 +d 13070023 PCI-DDA02/16 0 +d 13070024 PCI-DDA04/16 0 +d 13070025 PCI-DDA08/16 0 +d 13070026 PCI-DAC04/12-HS 0 +d 13070027 PCI-DAC04/16-HS 0 +d 13070028 PCI-DIO24 0 +d 13070029 PCI-DAS08 0 +d 1307002c PCI-INT32 0 +d 13070033 PCI-DUAL-AC5 0 +d 13070034 PCI-DAS-TC 0 +d 13070035 PCI-DAS64/M1/16 0 +d 13070036 PCI-DAS64/M2/16 0 +d 13070037 PCI-DAS64/M3/16 0 +d 1307004c PCI-DAS1000 0 +d 1307004d PCI-QUAD04 0 +d 13070052 PCI-DAS4020/12 0 +d 1307005e PCI-DAS6025 0 +v 1308 Jato Technologies Inc. 0 +d 13080001 NetCelerator Adapter 0 +s 1308000113080001 NetCelerator Adapter 0 +v 1309 AB Semiconductor Ltd 0 +v 130a Mitsubishi Electric Microcomputer 0 +v 130b Colorgraphic Communications Corp 0 +v 130c Ambex Technologies, Inc 0 +v 130d Accelerix Inc 0 +v 130e Yamatake-Honeywell Co. Ltd 0 +v 130f Advanet Inc 0 +v 1310 Gespac 0 +v 1311 Videoserver, Inc 0 +v 1312 Acuity Imaging, Inc 0 +v 1313 Yaskawa Electric Co. 0 +v 1316 Teradyne Inc 0 +v 1317 Linksys 0 +d 13170981 21x4x DEC-Tulip compatible 10/100 Ethernet 0 +d 13170985 NC100 Network Everywhere Fast Ethernet 10/100 0 +d 13171985 21x4x DEC-Tulip compatible 10/100 Ethernet 0 +d 13172850 HSP MicroModem 56 0 +d 13178201 ADMtek ADM8211 802.11b Wireless Interface 0 +s 1317820110b82635 SMC2635W 802.11b (11Mbps) wireless lan pcmcia (cardbus) card 0 +s 1317820113178201 SMC2635W 802.11b (11mbps) wireless lan pcmcia (cardbus) card 0 +d 13178211 ADMtek ADM8211 802.11b Wireless Interface 0 +d 13179511 21x4x DEC-Tulip compatible 10/100 Ethernet 0 +v 1318 Packet Engines Inc. 0 +d 13180911 GNIC-II PCI Gigabit Ethernet [Hamachi] 0 +v 1319 Fortemedia, Inc 0 +d 13190801 Xwave QS3000A [FM801] 0 +d 13190802 Xwave QS3000A [FM801 game port] 0 +d 13191000 FM801 PCI Audio 0 +d 13191001 FM801 PCI Joystick 0 +v 131a Finisar Corp. 0 +v 131c Nippon Electro-Sensory Devices Corp 0 +v 131d Sysmic, Inc. 0 +v 131e Xinex Networks Inc 0 +v 131f Siig Inc 0 +d 131f1000 CyberSerial (1-port) 16550 0 +d 131f1001 CyberSerial (1-port) 16650 0 +d 131f1002 CyberSerial (1-port) 16850 0 +d 131f1010 Duet 1S(16550)+1P 0 +d 131f1011 Duet 1S(16650)+1P 0 +d 131f1012 Duet 1S(16850)+1P 0 +d 131f1020 CyberParallel (1-port) 0 +d 131f1021 CyberParallel (2-port) 0 +d 131f1030 CyberSerial (2-port) 16550 0 +d 131f1031 CyberSerial (2-port) 16650 0 +d 131f1032 CyberSerial (2-port) 16850 0 +d 131f1034 Trio 2S(16550)+1P 0 +d 131f1035 Trio 2S(16650)+1P 0 +d 131f1036 Trio 2S(16850)+1P 0 +d 131f1050 CyberSerial (4-port) 16550 0 +d 131f1051 CyberSerial (4-port) 16650 0 +d 131f1052 CyberSerial (4-port) 16850 0 +d 131f2000 CyberSerial (1-port) 16550 0 +d 131f2001 CyberSerial (1-port) 16650 0 +d 131f2002 CyberSerial (1-port) 16850 0 +d 131f2010 Duet 1S(16550)+1P 0 +d 131f2011 Duet 1S(16650)+1P 0 +d 131f2012 Duet 1S(16850)+1P 0 +d 131f2020 CyberParallel (1-port) 0 +d 131f2021 CyberParallel (2-port) 0 +d 131f2030 CyberSerial (2-port) 16550 0 +s 131f2030131f2030 PCI Serial Card 0 +d 131f2031 CyberSerial (2-port) 16650 0 +d 131f2032 CyberSerial (2-port) 16850 0 +d 131f2040 Trio 1S(16550)+2P 0 +d 131f2041 Trio 1S(16650)+2P 0 +d 131f2042 Trio 1S(16850)+2P 0 +d 131f2050 CyberSerial (4-port) 16550 0 +d 131f2051 CyberSerial (4-port) 16650 0 +d 131f2052 CyberSerial (4-port) 16850 0 +d 131f2060 Trio 2S(16550)+1P 0 +d 131f2061 Trio 2S(16650)+1P 0 +d 131f2062 Trio 2S(16850)+1P 0 +d 131f2081 CyberSerial (8-port) ST16654 0 +v 1320 Crypto AG 0 +v 1321 Arcobel Graphics BV 0 +v 1322 MTT Co., Ltd 0 +v 1323 Dome Inc 0 +v 1324 Sphere Communications 0 +v 1325 Salix Technologies, Inc 0 +v 1326 Seachange international 0 +v 1327 Voss scientific 0 +v 1328 quadrant international 0 +v 1329 Productivity Enhancement 0 +v 132a Microcom Inc. 0 +v 132b Broadband Technologies 0 +v 132c Micrel Inc 0 +v 132d Integrated Silicon Solution, Inc. 0 +v 1330 MMC Networks 0 +v 1331 Radisys Corp. 0 +d 13310030 ENP-2611 0 +d 13318200 82600 Host Bridge 0 +d 13318201 82600 IDE 0 +d 13318202 82600 USB 0 +d 13318210 82600 PCI Bridge 0 +v 1332 Micro Memory 0 +d 13325415 MM-5415CN PCI Memory Module with Battery Backup 0 +d 13325425 MM-5425CN PCI 64/66 Memory Module with Battery Backup 0 +v 1334 Redcreek Communications, Inc 0 +v 1335 Videomail, Inc 0 +v 1337 Third Planet Publishing 0 +v 1338 BT Electronics 0 +v 133a Vtel Corp 0 +v 133b Softcom Microsystems 0 +v 133c Holontech Corp 0 +v 133d SS Technologies 0 +v 133e Virtual Computer Corp 0 +v 133f SCM Microsystems 0 +v 1340 Atalla Corp 0 +v 1341 Kyoto Microcomputer Co 0 +v 1342 Promax Systems Inc 0 +v 1343 Phylon Communications Inc 0 +v 1344 Crucial Technology 0 +v 1345 Arescom Inc 0 +v 1347 Odetics 0 +v 1349 Sumitomo Electric Industries, Ltd. 0 +v 134a DTC Technology Corp. 0 +d 134a0001 Domex 536 0 +d 134a0002 Domex DMX3194UP SCSI Adapter 0 +v 134b ARK Research Corp. 0 +v 134c Chori Joho System Co. Ltd 0 +v 134d PCTel Inc 0 +d 134d2189 HSP56 MicroModem 0 +d 134d2486 2304WT V.92 MDC Modem 0 +d 134d7890 HSP MicroModem 56 0 +s 134d7890134d0001 PCT789 adapter 0 +d 134d7891 HSP MicroModem 56 0 +s 134d7891134d0001 HSP MicroModem 56 0 +d 134d7892 HSP MicroModem 56 0 +d 134d7893 HSP MicroModem 56 0 +d 134d7894 HSP MicroModem 56 0 +d 134d7895 HSP MicroModem 56 0 +d 134d7896 HSP MicroModem 56 0 +d 134d7897 HSP MicroModem 56 0 +v 134e CSTI 0 +v 134f Algo System Co Ltd 0 +v 1350 Systec Co. Ltd 0 +v 1351 Sonix Inc 0 +v 1353 Thales Idatys 0 +d 13530002 Proserver 0 +d 13530003 PCI-FUT 0 +d 13530004 PCI-S0 0 +d 13530005 PCI-FUT-S0 0 +v 1354 Dwave System Inc 0 +v 1355 Kratos Analytical Ltd 0 +v 1356 The Logical Co 0 +v 1359 Prisa Networks 0 +v 135a Brain Boxes 0 +v 135b Giganet Inc 0 +v 135c Quatech Inc 0 +d 135c0010 QSC-100 0 +d 135c0020 DSC-100 0 +d 135c0030 DSC-200/300 0 +d 135c0040 QSC-200/300 0 +d 135c0050 ESC-100D 0 +d 135c0060 ESC-100M 0 +d 135c00f0 MPAC-100 Syncronous Serial Card (Zilog 85230) 0 +d 135c0170 QSCLP-100 0 +d 135c0180 DSCLP-100 0 +d 135c0190 SSCLP-100 0 +d 135c01a0 QSCLP-200/300 0 +d 135c01b0 DSCLP-200/300 0 +d 135c01c0 SSCLP-200/300 0 +v 135d ABB Network Partner AB 0 +v 135e Sealevel Systems Inc 0 +d 135e5101 Route 56.PCI - Multi-Protocol Serial Interface (Zilog Z16C32) 0 +d 135e7101 Single Port RS-232/422/485/530 0 +d 135e7201 Dual Port RS-232/422/485 Interface 0 +d 135e7202 Dual Port RS-232 Interface 0 +d 135e7401 Four Port RS-232 Interface 0 +d 135e7402 Four Port RS-422/485 Interface 0 +d 135e7801 Eight Port RS-232 Interface 0 +d 135e8001 8001 Digital I/O Adapter 0 +v 135f I-Data International A-S 0 +v 1360 Meinberg Funkuhren 0 +d 13600101 PCI32 DCF77 Radio Clock 0 +d 13600102 PCI509 DCF77 Radio Clock 0 +d 13600103 PCI510 DCF77 Radio Clock 0 +d 13600201 GPS167PCI GPS Receiver 0 +d 13600202 GPS168PCI GPS Receiver 0 +d 13600203 GPS169PCI GPS Receiver 0 +d 13600301 TCR510PCI IRIG Receiver 0 +v 1361 Soliton Systems K.K. 0 +v 1362 Fujifacom Corporation 0 +v 1363 Phoenix Technology Ltd 0 +v 1364 ATM Communications Inc 0 +v 1365 Hypercope GmbH 0 +v 1366 Teijin Seiki Co. Ltd 0 +v 1367 Hitachi Zosen Corporation 0 +v 1368 Skyware Corporation 0 +v 1369 Digigram 0 +v 136a High Soft Tech 0 +v 136b Kawasaki Steel Corporation 0 +d 136bff01 KL5A72002 Motion JPEG 0 +v 136c Adtek System Science Co Ltd 0 +v 136d Gigalabs Inc 0 +v 136f Applied Magic Inc 0 +v 1370 ATL Products 0 +v 1371 CNet Technology Inc 0 +d 1371434e GigaCard Network Adapter 0 +s 1371434e1371434e N-Way PCI-Bus Giga-Card 1000/100/10Mbps(L) 0 +v 1373 Silicon Vision Inc 0 +v 1374 Silicom Ltd 0 +v 1375 Argosystems Inc 0 +v 1376 LMC 0 +v 1377 Electronic Equipment Production & Distribution GmbH 0 +v 1378 Telemann Co. Ltd 0 +v 1379 Asahi Kasei Microsystems Co Ltd 0 +v 137a Mark of the Unicorn Inc 0 +d 137a0001 PCI-324 Audiowire Interface 0 +v 137b PPT Vision 0 +v 137c Iwatsu Electric Co Ltd 0 +v 137d Dynachip Corporation 0 +v 137e Patriot Scientific Corporation 0 +v 137f Japan Satellite Systems Inc 0 +v 1380 Sanritz Automation Co Ltd 0 +v 1381 Brains Co. Ltd 0 +v 1382 Marian - Electronic & Software 0 +d 13820001 ARC88 audio recording card 0 +d 13822088 Marc-8 MIDI 8 channel audio card 0 +v 1383 Controlnet Inc 0 +v 1384 Reality Simulation Systems Inc 0 +v 1385 Netgear 0 +d 13850013 WG311T 0 Note: This lists as Atheros Communications, Inc. AR5212 802.11abg NIC because of Madwifi +d 13854100 802.11b Wireless Adapter (MA301) 0 +d 13854105 MA311 802.11b wireless adapter 0 +d 13854400 WAG511 802.11a/b/g Dual Band Wireless PC Card 0 +d 13854600 WAG511 802.11a/b/g Dual Band Wireless PC Card 0 +d 13854601 WAG511 802.11a/b/g Dual Band Wireless PC Card 0 +d 13854610 WAG511 802.11a/b/g Dual Band Wireless PC Card 0 +d 13854a00 WAG311 802.11a/g Wireless PCI Adapter 0 +d 13854c00 WG311v2 54 Mbps Wireless PCI Adapter 0 +d 1385620a GA620 Gigabit Ethernet 0 +d 1385622a GA622 0 +d 1385630a GA630 Gigabit Ethernet 0 +d 1385f004 FA310TX 0 +v 1386 Video Domain Technologies 0 +v 1387 Systran Corp 0 +v 1388 Hitachi Information Technology Co Ltd 0 +v 1389 Applicom International 0 +d 13890001 PCI1500PFB [Intelligent fieldbus adaptor] 0 +v 138a Fusion Micromedia Corp 0 +v 138b Tokimec Inc 0 +v 138c Silicon Reality 0 +v 138d Future Techno Designs pte Ltd 0 +v 138e Basler GmbH 0 +v 138f Patapsco Designs Inc 0 +v 1390 Concept Development Inc 0 +v 1391 Development Concepts Inc 0 +v 1392 Medialight Inc 0 +v 1393 Moxa Technologies Co Ltd 0 +d 13931040 Smartio C104H/PCI 0 +d 13931141 Industrio CP-114 0 +d 13931680 Smartio C168H/PCI 0 +d 13932040 Intellio CP-204J 0 +d 13932180 Intellio C218 Turbo PCI 0 +d 13933200 Intellio C320 Turbo PCI 0 +v 1394 Level One Communications 0 +d 13940001 LXT1001 Gigabit Ethernet 0 +s 1394000113940001 NetCelerator Adapter 0 +v 1395 Ambicom Inc 0 +v 1396 Cipher Systems Inc 0 +v 1397 Cologne Chip Designs GmbH 0 +d 13972bd0 ISDN network controller [HFC-PCI] 0 +s 13972bd013972bd0 ISDN Board 0 +s 13972bd0e4bf1000 CI1-1-Harp 0 +v 1398 Clarion co. Ltd 0 +v 1399 Rios systems Co Ltd 0 +v 139a Alacritech Inc 0 +d 139a0001 Quad Port 10/100 Server Accelerator 0 +d 139a0003 Single Port 10/100 Server Accelerator 0 +d 139a0005 Single Port Gigabit Server Accelerator 0 +v 139b Mediasonic Multimedia Systems Ltd 0 +v 139c Quantum 3d Inc 0 +v 139d EPL limited 0 +v 139e Media4 0 +v 139f Aethra s.r.l. 0 +v 13a0 Crystal Group Inc 0 +v 13a1 Kawasaki Heavy Industries Ltd 0 +v 13a2 Ositech Communications Inc 0 +v 13a3 Hifn Inc. 0 +d 13a30005 7751 Security Processor 0 +d 13a30006 6500 Public Key Processor 0 +d 13a30007 7811 Security Processor 0 +d 13a30012 7951 Security Processor 0 +d 13a30014 78XX Security Processor 0 +d 13a30016 8065 Security Processor 0 +d 13a30017 8165 Security Processor 0 +d 13a30018 8154 Security Processor 0 +v 13a4 Rascom Inc 0 +v 13a5 Audio Digital Imaging Inc 0 +v 13a6 Videonics Inc 0 +v 13a7 Teles AG 0 +v 13a8 Exar Corp. 0 +d 13a80154 XR17C154 Quad UART 0 +d 13a80158 XR17C158 Octal UART 0 +v 13a9 Siemens Medical Systems, Ultrasound Group 0 +v 13aa Broadband Networks Inc 0 +v 13ab Arcom Control Systems Ltd 0 +v 13ac Motion Media Technology Ltd 0 +v 13ad Nexus Inc 0 +v 13ae ALD Technology Ltd 0 +v 13af T.Sqware 0 +v 13b0 Maxspeed Corp 0 +v 13b1 Tamura corporation 0 +v 13b2 Techno Chips Co. Ltd 0 +v 13b3 Lanart Corporation 0 +v 13b4 Wellbean Co Inc 0 +v 13b5 ARM 0 +v 13b6 Dlog GmbH 0 +v 13b7 Logic Devices Inc 0 +v 13b8 Nokia Telecommunications oy 0 +v 13b9 Elecom Co Ltd 0 +v 13ba Oxford Instruments 0 +v 13bb Sanyo Technosound Co Ltd 0 +v 13bc Bitran Corporation 0 +v 13bd Sharp corporation 0 +v 13be Miroku Jyoho Service Co. Ltd 0 +v 13bf Sharewave Inc 0 +v 13c0 Microgate Corporation 0 +d 13c00010 SyncLink Adapter v1 0 +d 13c00020 SyncLink SCC Adapter 0 +d 13c00030 SyncLink Multiport Adapter 0 +d 13c00210 SyncLink Adapter v2 0 +v 13c1 3ware Inc 0 +d 13c11000 3ware Inc 3ware 5xxx/6xxx-series PATA-RAID 0 +d 13c11001 3ware Inc 3ware 7xxx/8xxx-series PATA/SATA-RAID 0 +s 13c1100113c11001 3ware Inc 3ware 7xxx/8xxx-series PATA/SATA-RAID 0 +d 13c11002 3ware Inc 3ware 9xxx-series SATA-RAID 0 +v 13c2 Technotrend Systemtechnik GmbH 0 +v 13c3 Janz Computer AG 0 +v 13c4 Phase Metrics 0 +v 13c5 Alphi Technology Corp 0 +v 13c6 Condor Engineering Inc 0 +d 13c60520 CEI-520 A429 Card 0 +d 13c60620 CEI-620 A429 Card 0 +d 13c60820 CEI-820 A429 Card 0 +v 13c7 Blue Chip Technology Ltd 0 +v 13c8 Apptech Inc 0 +v 13c9 Eaton Corporation 0 +v 13ca Iomega Corporation 0 +v 13cb Yano Electric Co Ltd 0 +v 13cc Metheus Corporation 0 +v 13cd Compatible Systems Corporation 0 +v 13ce Cocom A/S 0 +v 13cf Studio Audio & Video Ltd 0 +v 13d0 Techsan Electronics Co Ltd 0 +d 13d02103 B2C2 FlexCopII DVB chip / Technisat SkyStar2 DVB card 0 +d 13d02200 B2C2 FlexCopIII DVB chip / Technisat SkyStar2 DVB card 0 +v 13d1 Abocom Systems Inc 0 +d 13d1ab02 ADMtek Centaur-C rev 17 [D-Link DFE-680TX] CardBus Fast Ethernet Adapter 0 +d 13d1ab03 21x4x DEC-Tulip compatible 10/100 Ethernet 0 +d 13d1ab06 RTL8139 [FE2000VX] CardBus Fast Ethernet Attached Port Adapter 0 +d 13d1ab08 21x4x DEC-Tulip compatible 10/100 Ethernet 0 +v 13d2 Shark Multimedia Inc 0 +v 13d3 IMC Networks 0 +v 13d4 Graphics Microsystems Inc 0 +v 13d5 Media 100 Inc 0 +v 13d6 K.I. Technology Co Ltd 0 +v 13d7 Toshiba Engineering Corporation 0 +v 13d8 Phobos corporation 0 +v 13d9 Apex PC Solutions Inc 0 +v 13da Intresource Systems pte Ltd 0 +v 13db Janich & Klass Computertechnik GmbH 0 +v 13dc Netboost Corporation 0 +v 13dd Multimedia Bundle Inc 0 +v 13de ABB Robotics Products AB 0 +v 13df E-Tech Inc 0 +d 13df0001 PCI56RVP Modem 0 +s 13df000113df0001 PCI56RVP Modem 0 +v 13e0 GVC Corporation 0 +v 13e1 Silicom Multimedia Systems Inc 0 +v 13e2 Dynamics Research Corporation 0 +v 13e3 Nest Inc 0 +v 13e4 Calculex Inc 0 +v 13e5 Telesoft Design Ltd 0 +v 13e6 Argosy research Inc 0 +v 13e7 NAC Incorporated 0 +v 13e8 Chip Express Corporation 0 +v 13e9 Intraserver Technology Inc 0 +v 13ea Dallas Semiconductor 0 +v 13eb Hauppauge Computer Works Inc 0 +v 13ec Zydacron Inc 0 +v 13ed Raytheion E-Systems 0 +v 13ee Hayes Microcomputer Products Inc 0 +v 13ef Coppercom Inc 0 +v 13f0 Sundance Technology Inc 0 +d 13f00201 ST201 Sundance Ethernet 0 +v 13f1 Oce' - Technologies B.V. 0 +v 13f2 Ford Microelectronics Inc 0 +v 13f3 Mcdata Corporation 0 +v 13f4 Troika Networks, Inc. 0 +d 13f41401 Zentai Fibre Channel Adapter 0 +v 13f5 Kansai Electric Co. Ltd 0 +v 13f6 C-Media Electronics Inc 0 +d 13f60011 CMI8738 0 +d 13f60100 CM8338A 0 +s 13f6010013f6ffff CMI8338/C3DX PCI Audio Device 0 +d 13f60101 CM8338B 0 +s 13f6010113f60101 CMI8338-031 PCI Audio Device 0 +d 13f60111 CM8738 0 +s 13f6011110190970 P6STP-FL motherboard 0 +s 13f6011110438035 CUSI-FX motherboard 0 +s 13f6011110438077 CMI8738 6-channel audio controller 0 +s 13f60111104380e2 CMI8738 6ch-MX 0 +s 13f6011113f60111 CMI8738/C3DX PCI Audio Device 0 +s 13f601111681a000 Gamesurround MUSE XL 0 +d 13f60211 CM8738 0 +v 13f7 Wildfire Communications 0 +v 13f8 Ad Lib Multimedia Inc 0 +v 13f9 NTT Advanced Technology Corp. 0 +v 13fa Pentland Systems Ltd 0 +v 13fb Aydin Corp 0 +v 13fc Computer Peripherals International 0 +v 13fd Micro Science Inc 0 +v 13fe Advantech Co. Ltd 0 +d 13fe1240 PCI-1240 4-channel stepper motor controller card w. Nova Electronics MCX314 0 +d 13fe1600 PCI-1612 4-port RS-232/422/485 PCI Communication Card 0 +d 13fe1752 PCI-1752 0 +d 13fe1754 PCI-1754 0 +d 13fe1756 PCI-1756 0 +v 13ff Silicon Spice Inc 0 +v 1400 Artx Inc 0 +d 14001401 9432 TX 0 +v 1401 CR-Systems A/S 0 +v 1402 Meilhaus Electronic GmbH 0 +v 1403 Ascor Inc 0 +v 1404 Fundamental Software Inc 0 +v 1405 Excalibur Systems Inc 0 +v 1406 Oce' Printing Systems GmbH 0 +v 1407 Lava Computer mfg Inc 0 +d 14070100 Lava Dual Serial 0 +d 14070101 Lava Quatro A 0 +d 14070102 Lava Quatro B 0 +d 14070120 Quattro-PCI A 0 +d 14070121 Quattro-PCI B 0 +d 14070180 Lava Octo A 0 +d 14070181 Lava Octo B 0 +d 14070200 Lava Port Plus 0 +d 14070201 Lava Quad A 0 +d 14070202 Lava Quad B 0 +d 14070220 Lava Quattro PCI Ports A/B 0 +d 14070221 Lava Quattro PCI Ports C/D 0 +d 14070500 Lava Single Serial 0 +d 14070600 Lava Port 650 0 +d 14078000 Lava Parallel 0 +d 14078001 Dual parallel port controller A 0 +d 14078002 Lava Dual Parallel port A 0 +d 14078003 Lava Dual Parallel port B 0 +d 14078800 BOCA Research IOPPAR 0 +v 1408 Aloka Co. Ltd 0 +v 1409 Timedia Technology Co Ltd 0 +d 14097168 PCI2S550 (Dual 16550 UART) 0 +v 140a DSP Research Inc 0 +v 140b Ramix Inc 0 +v 140c Elmic Systems Inc 0 +v 140d Matsushita Electric Works Ltd 0 +v 140e Goepel Electronic GmbH 0 +v 140f Salient Systems Corp 0 +v 1410 Midas lab Inc 0 +v 1411 Ikos Systems Inc 0 +v 1412 VIA Technologies Inc. 0 formerly IC Ensemble Inc. +d 14121712 ICE1712 [Envy24] PCI Multi-Channel I/O Controller 0 +s 141217121412d638 M-Audio Delta 410 0 +d 14121724 VT1720/24 [Envy24PT/HT] PCI Multi-Channel Audio Controller 0 +v 1413 Addonics 0 +v 1414 Microsoft Corporation 0 +v 1415 Oxford Semiconductor Ltd 0 +d 14158403 VScom 011H-EP1 1 port parallel adaptor 0 +d 14159501 OX16PCI954 (Quad 16950 UART) function 0 0 +s 14159501131f2050 CyberPro (4-port) 0 +s 1415950115ed2000 MCCR Serial p0-3 of 8 0 +s 1415950115ed2001 MCCR Serial p0-3 of 16 0 +d 1415950a EXSYS EX-41092 Dual 16950 Serial adapter 0 +d 1415950b OXCB950 Cardbus 16950 UART 0 +d 14159511 OX16PCI954 (Quad 16950 UART) function 1 0 +s 1415951115ed2000 MCCR Serial p4-7 of 8 0 +s 1415951115ed2001 MCCR Serial p4-15 of 16 0 +d 14159521 OX16PCI952 (Dual 16950 UART) 0 +v 1416 Multiwave Innovation pte Ltd 0 +v 1417 Convergenet Technologies Inc 0 +v 1418 Kyushu electronics systems Inc 0 +v 1419 Excel Switching Corp 0 +v 141a Apache Micro Peripherals Inc 0 +v 141b Zoom Telephonics Inc 0 +v 141d Digitan Systems Inc 0 +v 141e Fanuc Ltd 0 +v 141f Visiontech Ltd 0 +v 1420 Psion Dacom plc 0 +d 14208002 Gold Card NetGlobal 56k+10/100Mb CardBus (Ethernet part) 0 +d 14208003 Gold Card NetGlobal 56k+10/100Mb CardBus (Modem part) 0 +v 1421 Ads Technologies Inc 0 +v 1422 Ygrec Systems Co Ltd 0 +v 1423 Custom Technology Corp. 0 +v 1424 Videoserver Connections 0 +v 1425 Chelsio Communications Inc 0 +v 1426 Storage Technology Corp. 0 +v 1427 Better On-Line Solutions 0 +v 1428 Edec Co Ltd 0 +v 1429 Unex Technology Corp. 0 +v 142a Kingmax Technology Inc 0 +v 142b Radiolan 0 +v 142c Minton Optic Industry Co Ltd 0 +v 142d Pix stream Inc 0 +v 142e Vitec Multimedia 0 +d 142e4020 VM2-2 [Video Maker 2] MPEG1/2 Encoder 0 +v 142f Radicom Research Inc 0 +v 1430 ITT Aerospace/Communications Division 0 +v 1431 Gilat Satellite Networks 0 +v 1432 Edimax Computer Co. 0 +d 14329130 RTL81xx Fast Ethernet 0 +v 1433 Eltec Elektronik GmbH 0 +v 1435 Real Time Devices US Inc. 0 +v 1436 CIS Technology Inc 0 +v 1437 Nissin Inc Co 0 +v 1438 Atmel-dream 0 +v 1439 Outsource Engineering & Mfg. Inc 0 +v 143a Stargate Solutions Inc 0 +v 143b Canon Research Center, America 0 +v 143c Amlogic Inc 0 +v 143d Tamarack Microelectronics Inc 0 +v 143e Jones Futurex Inc 0 +v 143f Lightwell Co Ltd - Zax Division 0 +v 1440 ALGOL Corp. 0 +v 1441 AGIE Ltd 0 +v 1442 Phoenix Contact GmbH & Co. 0 +v 1443 Unibrain S.A. 0 +v 1444 TRW 0 +v 1445 Logical DO Ltd 0 +v 1446 Graphin Co Ltd 0 +v 1447 AIM GmBH 0 +v 1448 Alesis Studio Electronics 0 +v 1449 TUT Systems Inc 0 +v 144a Adlink Technology 0 +d 144a7296 PCI-7296 0 +d 144a7432 PCI-7432 0 +d 144a7433 PCI-7433 0 +d 144a7434 PCI-7434 0 +d 144a7841 PCI-7841 0 +d 144a8133 PCI-8133 0 +d 144a8164 PCI-8164 0 +d 144a8554 PCI-8554 0 +d 144a9111 PCI-9111 0 +d 144a9113 PCI-9113 0 +d 144a9114 PCI-9114 0 +v 144b Loronix Information Systems Inc 0 +v 144c Catalina Research Inc 0 +v 144d Samsung Electronics Co Ltd 0 +v 144e OLITEC 0 +v 144f Askey Computer Corp. 0 +v 1450 Octave Communications Ind. 0 +v 1451 SP3D Chip Design GmBH 0 +v 1453 MYCOM Inc 0 +v 1454 Altiga Networks 0 +v 1455 Logic Plus Plus Inc 0 +v 1456 Advanced Hardware Architectures 0 +v 1457 Nuera Communications Inc 0 +v 1458 Giga-byte Technology 0 +v 1459 DOOIN Electronics 0 +v 145a Escalate Networks Inc 0 +v 145b PRAIM SRL 0 +v 145c Cryptek 0 +v 145d Gallant Computer Inc 0 +v 145e Aashima Technology B.V. 0 +v 145f Baldor Electric Company 0 +d 145f0001 NextMove PCI 0 +v 1460 DYNARC INC 0 +v 1461 Avermedia Technologies Inc 0 +v 1462 Micro-Star International Co., Ltd. 0 +d 14626825 PCI Card wireless 11g [PC54G] 0 +d 14628725 NVIDIA NV25 [GeForce4 Ti 4600] VGA Adapter 0 +d 14629000 NVIDIA NV28 [GeForce4 Ti 4800] VGA Adapter 0 MSI G4Ti4800, 128MB DDR SDRAM, TV-Out, DVI-I +d 14629119 NVIDIA NV31 [GeForce FX 5600XT] VGA Adapter 0 +v 1463 Fast Corporation 0 +v 1464 Interactive Circuits & Systems Ltd 0 +v 1465 GN NETTEST Telecom DIV. 0 +v 1466 Designpro Inc. 0 +v 1467 DIGICOM SPA 0 +v 1468 AMBIT Microsystem Corp. 0 +v 1469 Cleveland Motion Controls 0 +v 146a IFR 0 +v 146b Parascan Technologies Ltd 0 +v 146c Ruby Tech Corp. 0 +d 146c1430 FE-1430TX Fast Ethernet PCI Adapter 0 +v 146d Tachyon, INC. 0 +v 146e Williams Electronics Games, Inc. 0 +v 146f Multi Dimensional Consulting Inc 0 +v 1470 Bay Networks 0 +v 1471 Integrated Telecom Express Inc 0 +v 1472 DAIKIN Industries, Ltd 0 +v 1473 ZAPEX Technologies Inc 0 +v 1474 Doug Carson & Associates 0 +v 1475 PICAZO Communications 0 +v 1476 MORTARA Instrument Inc 0 +v 1477 Net Insight 0 +v 1478 DIATREND Corporation 0 +v 1479 TORAY Industries Inc 0 +v 147a FORMOSA Industrial Computing 0 +v 147b ABIT Computer Corp. 0 +v 147c AWARE, Inc. 0 +v 147d Interworks Computer Products 0 +v 147e Matsushita Graphic Communication Systems, Inc. 0 +v 147f NIHON UNISYS, Ltd. 0 +v 1480 SCII Telecom 0 +v 1481 BIOPAC Systems Inc 0 +v 1482 ISYTEC - Integrierte Systemtechnik GmBH 0 +v 1483 LABWAY Corporation 0 +v 1484 Logic Corporation 0 +v 1485 ERMA - Electronic GmBH 0 +v 1486 L3 Communications Telemetry & Instrumentation 0 +v 1487 MARQUETTE Medical Systems 0 +v 1488 KONTRON Electronik GmBH 0 +v 1489 KYE Systems Corporation 0 +v 148a OPTO 0 +v 148b INNOMEDIALOGIC Inc. 0 +v 148c C.P. Technology Co. Ltd 0 +v 148d DIGICOM Systems, Inc. 0 +d 148d1003 HCF 56k Data/Fax Modem 0 +v 148e OSI Plus Corporation 0 +v 148f Plant Equipment, Inc. 0 +v 1490 Stone Microsystems PTY Ltd. 0 +v 1491 ZEAL Corporation 0 +v 1492 Time Logic Corporation 0 +v 1493 MAKER Communications 0 +v 1494 WINTOP Technology, Inc. 0 +v 1495 TOKAI Communications Industry Co. Ltd 0 +v 1496 JOYTECH Computer Co., Ltd. 0 +v 1497 SMA Regelsysteme GmBH 0 +v 1498 TEWS Datentechnik GmBH 0 +d 149830c8 TPCI200 0 +v 1499 EMTEC CO., Ltd 0 +v 149a ANDOR Technology Ltd 0 +v 149b SEIKO Instruments Inc 0 +v 149c OVISLINK Corp. 0 +v 149d NEWTEK Inc 0 +d 149d0001 Video Toaster for PC 0 +v 149e Mapletree Networks Inc. 0 +v 149f LECTRON Co Ltd 0 +v 14a0 SOFTING GmBH 0 +v 14a1 Systembase Co Ltd 0 +v 14a2 Millennium Engineering Inc 0 +v 14a3 Maverick Networks 0 +v 14a4 GVC/BCM Advanced Research 0 +v 14a5 XIONICS Document Technologies Inc 0 +v 14a6 INOVA Computers GmBH & Co KG 0 +v 14a7 MYTHOS Systems Inc 0 +v 14a8 FEATRON Technologies Corporation 0 +v 14a9 HIVERTEC Inc 0 +v 14aa Advanced MOS Technology Inc 0 +v 14ab Mentor Graphics Corp. 0 +v 14ac Novaweb Technologies Inc 0 +v 14ad Time Space Radio AB 0 +v 14ae CTI, Inc 0 +v 14af Guillemot Corporation 0 +d 14af7102 3D Prophet II MX 0 +v 14b0 BST Communication Technology Ltd 0 +v 14b1 Nextcom K.K. 0 +v 14b2 ENNOVATE Networks Inc 0 +v 14b3 XPEED Inc 0 +d 14b30000 DSL NIC 0 +v 14b4 PHILIPS Business Electronics B.V. 0 +v 14b5 Creamware GmBH 0 +d 14b50200 Scope 0 +d 14b50300 Pulsar 0 +d 14b50400 PulsarSRB 0 +d 14b50600 Pulsar2 0 +d 14b50800 DSP-Board 0 +d 14b50900 DSP-Board 0 +d 14b50a00 DSP-Board 0 +d 14b50b00 DSP-Board 0 +v 14b6 Quantum Data Corp. 0 +v 14b7 PROXIM Inc 0 +d 14b70001 Symphony 4110 0 +v 14b8 Techsoft Technology Co Ltd 0 +v 14b9 AIRONET Wireless Communications 0 +d 14b90001 PC4800 0 +d 14b90340 PC4800 0 +d 14b90350 PC4800 0 +d 14b94500 PC4500 0 +d 14b94800 Cisco Aironet 340 802.11b Wireless LAN Adapter/Aironet PC4800 0 +d 14b9a504 Cisco Aironet Wireless 802.11b 0 +d 14b9a505 Cisco Aironet CB20a 802.11a Wireless LAN Adapter 0 +d 14b9a506 Cisco Aironet Mini PCI b/g 0 +v 14ba INTERNIX Inc. 0 +v 14bb SEMTECH Corporation 0 +v 14bc Globespan Semiconductor Inc. 0 +v 14bd CARDIO Control N.V. 0 +v 14be L3 Communications 0 +v 14bf SPIDER Communications Inc. 0 +v 14c0 COMPAL Electronics Inc 0 +v 14c1 MYRICOM Inc. 0 +d 14c18043 Myrinet 2000 Scalable Cluster Interconnect 0 +v 14c2 DTK Computer 0 +v 14c3 MEDIATEK Corp. 0 +v 14c4 IWASAKI Information Systems Co Ltd 0 +v 14c5 Automation Products AB 0 +v 14c6 Data Race Inc 0 +v 14c7 Modular Technology Holdings Ltd 0 +v 14c8 Turbocomm Tech. Inc. 0 +v 14c9 ODIN Telesystems Inc 0 +v 14ca PE Logic Corp. 0 +v 14cb Billionton Systems Inc 0 +v 14cc NAKAYO Telecommunications Inc 0 +v 14cd Universal Scientific Ind. 0 +v 14ce Whistle Communications 0 +v 14cf TEK Microsystems Inc. 0 +v 14d0 Ericsson Axe R & D 0 +v 14d1 Computer Hi-Tech Co Ltd 0 +v 14d2 Titan Electronics Inc 0 +d 14d28001 VScom 010L 1 port parallel adaptor 0 +d 14d28002 VScom 020L 2 port parallel adaptor 0 +d 14d28010 VScom 100L 1 port serial adaptor 0 +d 14d28011 VScom 110L 1 port serial and 1 port parallel adaptor 0 +d 14d28020 VScom 200L 1 port serial adaptor 0 +d 14d28021 VScom 210L 2 port serial and 1 port parallel adaptor 0 +d 14d28040 VScom 400L 4 port serial adaptor 0 +d 14d28080 VScom 800L 8 port serial adaptor 0 +d 14d2a000 VScom 010H 1 port parallel adaptor 0 +d 14d2a001 VScom 100H 1 port serial adaptor 0 +d 14d2a003 VScom 400H 4 port serial adaptor 0 +d 14d2a004 VScom 400HF1 4 port serial adaptor 0 +d 14d2a005 VScom 200H 2 port serial adaptor 0 +d 14d2e001 VScom 010HV2 1 port parallel adaptor 0 +d 14d2e010 VScom 100HV2 1 port serial adaptor 0 +d 14d2e020 VScom 200HV2 2 port serial adaptor 0 +v 14d3 CIRTECH (UK) Ltd 0 +v 14d4 Panacom Technology Corp 0 +v 14d5 Nitsuko Corporation 0 +v 14d6 Accusys Inc 0 +v 14d7 Hirakawa Hewtech Corp 0 +v 14d8 HOPF Elektronik GmBH 0 +v 14d9 Alliance Semiconductor Corporation 0 Formerly SiPackets, Inc., formerly API NetWorks, Inc., formerly Alpha Processor, Inc. +d 14d90010 AP1011/SP1011 HyperTransport-PCI Bridge [Sturgeon] 0 +d 14d99000 AS90L10204/10208 HyperTransport to PCI-X Bridge 0 +v 14da National Aerospace Laboratories 0 +v 14db AFAVLAB Technology Inc 0 +d 14db2120 TK9902 0 +v 14dc Amplicon Liveline Ltd 0 +d 14dc0000 PCI230 0 +d 14dc0001 PCI242 0 +d 14dc0002 PCI244 0 +d 14dc0003 PCI247 0 +d 14dc0004 PCI248 0 +d 14dc0005 PCI249 0 +d 14dc0006 PCI260 0 +d 14dc0007 PCI224 0 +d 14dc0008 PCI234 0 +d 14dc0009 PCI236 0 +d 14dc000a PCI272 0 +d 14dc000b PCI215 0 +v 14dd Boulder Design Labs Inc 0 +v 14de Applied Integration Corporation 0 +v 14df ASIC Communications Corp 0 +v 14e1 INVERTEX 0 +v 14e2 INFOLIBRIA 0 +v 14e3 AMTELCO 0 +v 14e4 Broadcom Corporation 0 +d 14e40800 Sentry5 Chipcommon I/O Controller 0 +d 14e40804 Sentry5 PCI Bridge 0 +d 14e40805 Sentry5 MIPS32 CPU 0 +d 14e40806 Sentry5 Ethernet Controller 0 +d 14e4080b Sentry5 Crypto Accelerator 0 +d 14e4080f Sentry5 DDR/SDR RAM Controller 0 +d 14e40811 Sentry5 External Interface Core 0 +d 14e40816 BCM3302 Sentry5 MIPS32 CPU 0 +d 14e41644 NetXtreme BCM5700 Gigabit Ethernet 0 +s 14e4164410140277 Broadcom Vigil B5700 1000Base-T 0 +s 14e41644102800d1 Broadcom BCM5700 0 +s 14e4164410280106 Broadcom BCM5700 0 +s 14e4164410280109 Broadcom BCM5700 1000Base-T 0 +s 14e416441028010a Broadcom BCM5700 1000BaseTX 0 +s 14e4164410b71000 3C996-T 1000Base-T 0 +s 14e4164410b71001 3C996B-T 1000Base-T 0 +s 14e4164410b71002 3C996C-T 1000Base-T 0 +s 14e4164410b71003 3C997-T 1000Base-T Dual Port 0 +s 14e4164410b71004 3C996-SX 1000Base-SX 0 +s 14e4164410b71005 3C997-SX 1000Base-SX Dual Port 0 +s 14e4164410b71008 3C942 Gigabit LOM (31X31) 0 +s 14e4164414e40002 NetXtreme 1000Base-SX 0 +s 14e4164414e40003 NetXtreme 1000Base-SX 0 +s 14e4164414e40004 NetXtreme 1000Base-T 0 +s 14e4164414e41028 NetXtreme 1000BaseTX 0 +s 14e4164414e41644 BCM5700 1000Base-T 0 +d 14e41645 NetXtreme BCM5701 Gigabit Ethernet 0 +s 14e416450e11007c NC7770 Gigabit Server Adapter (PCI-X, 10/100/1000-T) 0 +s 14e416450e11007d NC6770 Gigabit Server Adapter (PCI-X, 1000-SX) 0 +s 14e416450e110085 NC7780 Gigabit Server Adapter (embedded, WOL) 0 +s 14e416450e110099 NC7780 Gigabit Server Adapter (embedded, WOL) 0 +s 14e416450e11009a NC7770 Gigabit Server Adapter (PCI-X, 10/100/1000-T) 0 +s 14e416450e1100c1 NC6770 Gigabit Server Adapter (PCI-X, 1000-SX) 0 +s 14e4164510280121 Broadcom BCM5701 1000Base-T 0 +s 14e41645103c128a HP 1000Base-T (PCI) [A7061A] 0 +s 14e41645103c128b HP 1000Base-SX (PCI) [A7073A] 0 +s 14e41645103c12a4 HP Core Lan 1000Base-T 0 +s 14e41645103c12c1 HP IOX Core Lan 1000Base-T [A7109AX] 0 +s 14e4164510a98010 SGI IO9 Gigabit Ethernet (Copper) 0 +s 14e4164510a98011 SGI Gigabit Ethernet (Copper) 0 +s 14e4164510a98012 SGI Gigabit Ethernet (Fiber) 0 +s 14e4164510b71004 3C996-SX 1000Base-SX 0 +s 14e4164510b71006 3C996B-T 1000Base-T 0 +s 14e4164510b71007 3C1000-T 1000Base-T 0 +s 14e4164510b71008 3C940-BR01 1000Base-T 0 +s 14e4164514e40001 BCM5701 1000Base-T 0 +s 14e4164514e40005 BCM5701 1000Base-T 0 +s 14e4164514e40006 BCM5701 1000Base-T 0 +s 14e4164514e40007 BCM5701 1000Base-SX 0 +s 14e4164514e40008 BCM5701 1000Base-T 0 +s 14e4164514e48008 BCM5701 1000Base-T 0 +d 14e41646 NetXtreme BCM5702 Gigabit Ethernet 0 +s 14e416460e1100bb NC7760 1000BaseTX 0 +s 14e4164610280126 Broadcom BCM5702 1000BaseTX 0 +s 14e4164614e48009 BCM5702 1000BaseTX 0 +d 14e41647 NetXtreme BCM5703 Gigabit Ethernet 0 +s 14e416470e110099 NC7780 1000BaseTX 0 +s 14e416470e11009a NC7770 1000BaseTX 0 +s 14e4164710a98010 SGI IO9 Gigabit Ethernet (Copper) 0 +s 14e4164714e40009 BCM5703 1000BaseTX 0 +s 14e4164714e4000a BCM5703 1000BaseSX 0 +s 14e4164714e4000b BCM5703 1000BaseTX 0 +s 14e4164714e48009 BCM5703 1000BaseTX 0 +s 14e4164714e4800a BCM5703 1000BaseTX 0 +d 14e41648 NetXtreme BCM5704 Gigabit Ethernet 0 +s 14e416480e1100cf NC7772 Gigabit Server Adapter (PCI-X, 10,100,1000-T) 0 +s 14e416480e1100d0 NC7782 Gigabit Server Adapter (PCI-X, 10,100,1000-T) 0 +s 14e416480e1100d1 NC7783 Gigabit Server Adapter (PCI-X, 10,100,1000-T) 0 +s 14e4164810b72000 3C998-T Dual Port 10/100/1000 PCI-X 0 +s 14e4164810b73000 3C999-T Quad Port 10/100/1000 PCI-X 0 +s 14e4164811661648 NetXtreme CIOB-E 1000Base-T 0 +d 14e4164a NetXtreme II BCM5706 Gigabit Ethernet 0 +d 14e4164d NetXtreme BCM5702FE Gigabit Ethernet 0 +d 14e41653 NetXtreme BCM5705 Gigabit Ethernet 0 +s 14e416530e1100e3 NC7761 Gigabit Server Adapter 0 +d 14e41654 NetXtreme BCM5705_2 Gigabit Ethernet 0 +s 14e416540e1100e3 NC7761 Gigabit Server Adapter 0 +s 14e41654103c3100 NC1020 HP ProLiant Gigabit Server Adapter 32 PCI 0 +d 14e41659 NetXtreme BCM5721 Gigabit Ethernet PCI Express 0 +d 14e4165d NetXtreme BCM5705M Gigabit Ethernet 0 +d 14e4165e NetXtreme BCM5705M_2 Gigabit Ethernet 0 +s 14e4165e103c0890 NC6000 laptop 0 +d 14e4166e 570x 10/100 Integrated Controller 0 +d 14e41677 NetXtreme BCM5751 Gigabit Ethernet PCI Express 0 +s 14e4167710280179 Optiplex GX280 0 +d 14e4167d NetXtreme BCM5751M Gigabit Ethernet PCI Express 0 +d 14e4167e NetXtreme BCM5751F Fast Ethernet PCI Express 0 +d 14e41696 NetXtreme BCM5782 Gigabit Ethernet 0 +s 14e41696103c12bc HP d530 CMT (DG746A) 0 +s 14e4169614e4000d NetXtreme BCM5782 1000Base-T 0 +d 14e4169c NetXtreme BCM5788 Gigabit Ethernet 0 +d 14e4169d NetLink BCM5789 Gigabit Ethernet PCI Express 0 +d 14e416a6 NetXtreme BCM5702X Gigabit Ethernet 0 +s 14e416a60e1100bb NC7760 Gigabit Server Adapter (PCI-X, 10/100/1000-T) 0 +s 14e416a610280126 BCM5702 1000Base-T 0 +s 14e416a614e4000c BCM5702 1000Base-T 0 +s 14e416a614e48009 BCM5702 1000Base-T 0 +d 14e416a7 NetXtreme BCM5703X Gigabit Ethernet 0 +s 14e416a70e1100ca NC7771 Gigabit Server Adapter (PCI-X, 10,100,1000-T) 0 +s 14e416a70e1100cb NC7781 Gigabit Server Adapter (PCI-X, 10,100,1000-T) 0 +s 14e416a714e40009 NetXtreme BCM5703 1000Base-T 0 +s 14e416a714e4000a NetXtreme BCM5703 1000Base-SX 0 +s 14e416a714e4000b NetXtreme BCM5703 1000Base-T 0 +s 14e416a714e4800a NetXtreme BCM5703 1000Base-T 0 +d 14e416a8 NetXtreme BCM5704S Gigabit Ethernet 0 +s 14e416a810b72001 3C998-SX Dual Port 1000-SX PCI-X 0 +d 14e416aa NetXtreme II BCM5706S Gigabit Ethernet 0 +d 14e416c6 NetXtreme BCM5702A3 Gigabit Ethernet 0 +s 14e416c610b71100 3C1000B-T 10/100/1000 PCI 0 +s 14e416c614e4000c BCM5702 1000Base-T 0 +s 14e416c614e48009 BCM5702 1000Base-T 0 +d 14e416c7 NetXtreme BCM5703 Gigabit Ethernet 0 +s 14e416c70e1100ca NC7771 Gigabit Server Adapter (PCI-X, 10,100,1000-T) 0 +s 14e416c70e1100cb NC7781 Gigabit Server Adapter (PCI-X, 10,100,1000-T) 0 +s 14e416c7103c12c3 HP Combo FC/GigE-SX [A9782A] 0 +s 14e416c7103c12ca HP Combo FC/GigE-T [A9784A] 0 +s 14e416c714e40009 NetXtreme BCM5703 1000Base-T 0 +s 14e416c714e4000a NetXtreme BCM5703 1000Base-SX 0 +d 14e416dd NetLink BCM5781 Gigabit Ethernet PCI Express 0 +d 14e416f7 NetXtreme BCM5753 Gigabit Ethernet PCI Express 0 +d 14e416fd NetXtreme BCM5753M Gigabit Ethernet PCI Express 0 +d 14e416fe NetXtreme BCM5753F Fast Ethernet PCI Express 0 +d 14e4170c BCM4401-B0 100Base-TX 0 +d 14e4170d NetXtreme BCM5901 100Base-TX 0 +s 14e4170d10140545 ThinkPad R40e (2684-HVG) builtin ethernet controller 0 +d 14e4170e NetXtreme BCM5901 100Base-TX 0 +d 14e43352 BCM3352 0 +d 14e43360 BCM3360 0 +d 14e44210 BCM4210 iLine10 HomePNA 2.0 0 +d 14e44211 BCM4211 iLine10 HomePNA 2.0 + V.90 56k modem 0 +d 14e44212 BCM4212 v.90 56k modem 0 +d 14e44301 BCM4303 802.11b Wireless LAN Controller 0 +s 14e4430110280407 TrueMobile 1180 Onboard WLAN 0 +s 14e4430110430120 WL-103b Wireless LAN PC Card 0 +d 14e44305 BCM4307 V.90 56k Modem 0 +d 14e44306 BCM4307 Ethernet Controller 0 +d 14e44307 BCM4307 802.11b Wireless LAN Controller 0 +d 14e44310 BCM4310 Chipcommon I/OController 0 +d 14e44312 BCM4310 UART 0 +d 14e44313 BCM4310 Ethernet Controller 0 +d 14e44315 BCM4310 USB Controller 0 +d 14e44320 BCM4306 802.11b/g Wireless LAN Controller 0 +s 14e4432010280001 TrueMobile 1300 WLAN Mini-PCI Card 0 +s 14e4432010280003 Wireless 1350 WLAN Mini-PCI Card 0 +s 14e443201043100f WL-100G 0 +s 14e4432014e44320 Linksys WMP54G PCI 0 +s 14e4432017374320 WPC54G 0 +s 14e4432017997010 Belkin F5D7010 54g Wireless Network card 0 +d 14e44321 BCM4306 802.11a Wireless LAN Controller 0 +d 14e44322 BCM4306 UART 0 +d 14e44324 BCM4309 802.11a/b/g 0 +s 14e4432410280001 Truemobile 1400 0 +s 14e4432410280003 Truemobile 1450 MiniPCI 0 +d 14e44325 BCM43xG 802.11b/g 0 +s 14e4432514140003 Wireless Notebook Adapter MN-720 0 +s 14e4432514140004 Wireless PCI Adapter MN-730 0 +d 14e44326 BCM4307 Chipcommon I/O Controller? 0 probably this is a correct ID... +d 14e44401 BCM4401 100Base-T 0 +s 14e44401104380a8 A7V8X motherboard 0 +d 14e44402 BCM4402 Integrated 10/100BaseT 0 +d 14e44403 BCM4402 V.90 56k Modem 0 +d 14e44410 BCM4413 iLine32 HomePNA 2.0 0 +d 14e44411 BCM4413 V.90 56k modem 0 +d 14e44412 BCM4412 10/100BaseT 0 +d 14e44430 BCM44xx CardBus iLine32 HomePNA 2.0 0 +d 14e44432 BCM4432 CardBus 10/100BaseT 0 +d 14e44610 BCM4610 Sentry5 PCI to SB Bridge 0 +d 14e44611 BCM4610 Sentry5 iLine32 HomePNA 1.0 0 +d 14e44612 BCM4610 Sentry5 V.90 56k Modem 0 +d 14e44613 BCM4610 Sentry5 Ethernet Controller 0 +d 14e44614 BCM4610 Sentry5 External Interface 0 +d 14e44615 BCM4610 Sentry5 USB Controller 0 +d 14e44704 BCM4704 PCI to SB Bridge 0 +d 14e44705 BCM4704 Sentry5 802.11b Wireless LAN Controller 0 +d 14e44706 BCM4704 Sentry5 Ethernet Controller 0 +d 14e44707 BCM4704 Sentry5 USB Controller 0 +d 14e44708 BCM4704 Crypto Accelerator 0 +d 14e44710 BCM4710 Sentry5 PCI to SB Bridge 0 +d 14e44711 BCM47xx Sentry5 iLine32 HomePNA 2.0 0 +d 14e44712 BCM47xx V.92 56k modem 0 +d 14e44713 Sentry5 Ethernet Controller 0 +d 14e44714 BCM47xx Sentry5 External Interface 0 +d 14e44715 Sentry5 USB Controller 0 +d 14e44716 BCM47xx Sentry5 USB Host Controller 0 +d 14e44717 BCM47xx Sentry5 USB Device Controller 0 +d 14e44718 Sentry5 Crypto Accelerator 0 +d 14e44720 BCM4712 MIPS CPU 0 +d 14e45365 BCM5365P Sentry5 Host Bridge 0 +d 14e45600 BCM5600 StrataSwitch 24+2 Ethernet Switch Controller 0 +d 14e45605 BCM5605 StrataSwitch 24+2 Ethernet Switch Controller 0 +d 14e45615 BCM5615 StrataSwitch 24+2 Ethernet Switch Controller 0 +d 14e45625 BCM5625 StrataSwitch 24+2 Ethernet Switch Controller 0 +d 14e45645 BCM5645 StrataSwitch 24+2 Ethernet Switch Controller 0 +d 14e45670 BCM5670 8-Port 10GE Ethernet Switch Fabric 0 +d 14e45680 BCM5680 G-Switch 8 Port Gigabit Ethernet Switch Controller 0 +d 14e45690 BCM5690 12-port Multi-Layer Gigabit Ethernet Switch 0 +d 14e45691 BCM5691 GE/10GE 8+2 Gigabit Ethernet Switch Controller 0 +d 14e45820 BCM5820 Crypto Accelerator 0 +d 14e45821 BCM5821 Crypto Accelerator 0 +d 14e45822 BCM5822 Crypto Accelerator 0 +d 14e45823 BCM5823 Crypto Accelerator 0 +d 14e45824 BCM5824 Crypto Accelerator 0 +d 14e45840 BCM5840 Crypto Accelerator 0 +d 14e45841 BCM5841 Crypto Accelerator 0 +d 14e45850 BCM5850 Crypto Accelerator 0 +v 14e5 Pixelfusion Ltd 0 +v 14e6 SHINING Technology Inc 0 +v 14e7 3CX 0 +v 14e8 RAYCER Inc 0 +v 14e9 GARNETS System CO Ltd 0 +v 14ea Planex Communications, Inc 0 +d 14eaab06 FNW-3603-TX CardBus Fast Ethernet 0 +d 14eaab07 RTL81xx RealTek Ethernet 0 +v 14eb SEIKO EPSON Corp 0 +v 14ec ACQIRIS 0 +v 14ed DATAKINETICS Ltd 0 +v 14ee MASPRO KENKOH Corp 0 +v 14ef CARRY Computer ENG. CO Ltd 0 +v 14f0 CANON RESEACH CENTRE FRANCE 0 +v 14f1 Conexant 0 +d 14f11002 HCF 56k Modem 0 +d 14f11003 HCF 56k Modem 0 +d 14f11004 HCF 56k Modem 0 +d 14f11005 HCF 56k Modem 0 +d 14f11006 HCF 56k Modem 0 +d 14f11022 HCF 56k Modem 0 +d 14f11023 HCF 56k Modem 0 +d 14f11024 HCF 56k Modem 0 +d 14f11025 HCF 56k Modem 0 +d 14f11026 HCF 56k Modem 0 +d 14f11032 HCF 56k Modem 0 +d 14f11033 HCF 56k Data/Fax Modem 0 +s 14f1103310338077 NEC 0 +s 14f11033122d4027 Dell Zeus - MDP3880-W(B) Data Fax Modem 0 +s 14f11033122d4030 Dell Mercury - MDP3880-U(B) Data Fax Modem 0 +s 14f11033122d4034 Dell Thor - MDP3880-W(U) Data Fax Modem 0 +s 14f1103313e0020d Dell Copper 0 +s 14f1103313e0020e Dell Silver 0 +s 14f1103313e00261 IBM 0 +s 14f1103313e00290 Compaq Goldwing 0 +s 14f1103313e002a0 IBM 0 +s 14f1103313e002b0 IBM 0 +s 14f1103313e002c0 Compaq Scooter 0 +s 14f1103313e002d0 IBM 0 +s 14f11033144f1500 IBM P85-DF (1) 0 +s 14f11033144f1501 IBM P85-DF (2) 0 +s 14f11033144f150a IBM P85-DF (3) 0 +s 14f11033144f150b IBM P85-DF Low Profile (1) 0 +s 14f11033144f1510 IBM P85-DF Low Profile (2) 0 +d 14f11034 HCF 56k Data/Fax/Voice Modem 0 +d 14f11035 HCF 56k Data/Fax/Voice/Spkp (w/Handset) Modem 0 +s 14f1103510cf1098 Fujitsu P85-DFSV 0 +d 14f11036 HCF 56k Data/Fax/Voice/Spkp Modem 0 +s 14f11036104d8067 HCF 56k Modem 0 +s 14f11036122d4029 MDP3880SP-W 0 +s 14f11036122d4031 MDP3880SP-U 0 +s 14f1103613e00209 Dell Titanium 0 +s 14f1103613e0020a Dell Graphite 0 +s 14f1103613e00260 Gateway Red Owl 0 +s 14f1103613e00270 Gateway White Horse 0 +d 14f11052 HCF 56k Data/Fax Modem (Worldwide) 0 +d 14f11053 HCF 56k Data/Fax Modem (Worldwide) 0 +d 14f11054 HCF 56k Data/Fax/Voice Modem (Worldwide) 0 +d 14f11055 HCF 56k Data/Fax/Voice/Spkp (w/Handset) Modem (Worldwide) 0 +d 14f11056 HCF 56k Data/Fax/Voice/Spkp Modem (Worldwide) 0 +d 14f11057 HCF 56k Data/Fax/Voice/Spkp Modem (Worldwide) 0 +d 14f11059 HCF 56k Data/Fax/Voice Modem (Worldwide) 0 +d 14f11063 HCF 56k Data/Fax Modem 0 +d 14f11064 HCF 56k Data/Fax/Voice Modem 0 +d 14f11065 HCF 56k Data/Fax/Voice/Spkp (w/Handset) Modem 0 +d 14f11066 HCF 56k Data/Fax/Voice/Spkp Modem 0 +s 14f11066122d4033 Dell Athena - MDP3900V-U 0 +d 14f11433 HCF 56k Data/Fax Modem 0 +d 14f11434 HCF 56k Data/Fax/Voice Modem 0 +d 14f11435 HCF 56k Data/Fax/Voice/Spkp (w/Handset) Modem 0 +d 14f11436 HCF 56k Data/Fax Modem 0 +d 14f11453 HCF 56k Data/Fax Modem 0 +s 14f1145313e00240 IBM 0 +s 14f1145313e00250 IBM 0 +s 14f11453144f1502 IBM P95-DF (1) 0 +s 14f11453144f1503 IBM P95-DF (2) 0 +d 14f11454 HCF 56k Data/Fax/Voice Modem 0 +d 14f11455 HCF 56k Data/Fax/Voice/Spkp (w/Handset) Modem 0 +d 14f11456 HCF 56k Data/Fax/Voice/Spkp Modem 0 +s 14f11456122d4035 Dell Europa - MDP3900V-W 0 +s 14f11456122d4302 Dell MP3930V-W(C) MiniPCI 0 +d 14f11610 ADSL AccessRunner PCI Arbitration Device 0 +d 14f11611 AccessRunner PCI ADSL Interface Device 0 +d 14f11620 ADSL AccessRunner V2 PCI Arbitration Device 0 +d 14f11621 AccessRunner V2 PCI ADSL Interface Device 0 +d 14f11622 AccessRunner V2 PCI ADSL Yukon WAN Adapter 0 +d 14f11803 HCF 56k Modem 0 +s 14f118030e110023 623-LAN Grizzly 0 +s 14f118030e110043 623-LAN Yogi 0 +d 14f11815 HCF 56k Modem 0 +s 14f118150e110022 Grizzly 0 +s 14f118150e110042 Yogi 0 +d 14f12003 HSF 56k Data/Fax Modem 0 +d 14f12004 HSF 56k Data/Fax/Voice Modem 0 +d 14f12005 HSF 56k Data/Fax/Voice/Spkp (w/Handset) Modem 0 +d 14f12006 HSF 56k Data/Fax/Voice/Spkp Modem 0 +d 14f12013 HSF 56k Data/Fax Modem 0 +s 14f120130e11b195 Bear 0 +s 14f120130e11b196 Seminole 1 0 +s 14f120130e11b1be Seminole 2 0 +s 14f1201310258013 Acer 0 +s 14f120131033809d NEC 0 +s 14f12013103380bc NEC 0 +s 14f12013155d6793 HP 0 +s 14f12013155d8850 E Machines 0 +d 14f12014 HSF 56k Data/Fax/Voice Modem 0 +d 14f12015 HSF 56k Data/Fax/Voice/Spkp (w/Handset) Modem 0 +d 14f12016 HSF 56k Data/Fax/Voice/Spkp Modem 0 +d 14f12043 HSF 56k Data/Fax Modem (WorldW SmartDAA) 0 +d 14f12044 HSF 56k Data/Fax/Voice Modem (WorldW SmartDAA) 0 +d 14f12045 HSF 56k Data/Fax/Voice/Spkp (w/Handset) Modem (WorldW SmartDAA) 0 +d 14f12046 HSF 56k Data/Fax/Voice/Spkp Modem (WorldW SmartDAA) 0 +d 14f12063 HSF 56k Data/Fax Modem (SmartDAA) 0 +d 14f12064 HSF 56k Data/Fax/Voice Modem (SmartDAA) 0 +d 14f12065 HSF 56k Data/Fax/Voice/Spkp (w/Handset) Modem (SmartDAA) 0 +d 14f12066 HSF 56k Data/Fax/Voice/Spkp Modem (SmartDAA) 0 +d 14f12093 HSF 56k Modem 0 +s 14f12093155d2f07 Legend 0 +d 14f12143 HSF 56k Data/Fax/Cell Modem (Mob WorldW SmartDAA) 0 +d 14f12144 HSF 56k Data/Fax/Voice/Cell Modem (Mob WorldW SmartDAA) 0 +d 14f12145 HSF 56k Data/Fax/Voice/Spkp (w/HS)/Cell Modem (Mob WorldW SmartDAA) 0 +d 14f12146 HSF 56k Data/Fax/Voice/Spkp/Cell Modem (Mob WorldW SmartDAA) 0 +d 14f12163 HSF 56k Data/Fax/Cell Modem (Mob SmartDAA) 0 +d 14f12164 HSF 56k Data/Fax/Voice/Cell Modem (Mob SmartDAA) 0 +d 14f12165 HSF 56k Data/Fax/Voice/Spkp (w/HS)/Cell Modem (Mob SmartDAA) 0 +d 14f12166 HSF 56k Data/Fax/Voice/Spkp/Cell Modem (Mob SmartDAA) 0 +d 14f12343 HSF 56k Data/Fax CardBus Modem (Mob WorldW SmartDAA) 0 +d 14f12344 HSF 56k Data/Fax/Voice CardBus Modem (Mob WorldW SmartDAA) 0 +d 14f12345 HSF 56k Data/Fax/Voice/Spkp (w/HS) CardBus Modem (Mob WorldW SmartDAA) 0 +d 14f12346 HSF 56k Data/Fax/Voice/Spkp CardBus Modem (Mob WorldW SmartDAA) 0 +d 14f12363 HSF 56k Data/Fax CardBus Modem (Mob SmartDAA) 0 +d 14f12364 HSF 56k Data/Fax/Voice CardBus Modem (Mob SmartDAA) 0 +d 14f12365 HSF 56k Data/Fax/Voice/Spkp (w/HS) CardBus Modem (Mob SmartDAA) 0 +d 14f12366 HSF 56k Data/Fax/Voice/Spkp CardBus Modem (Mob SmartDAA) 0 +d 14f12443 HSF 56k Data/Fax Modem (Mob WorldW SmartDAA) 0 +s 14f12443104d8075 Modem 0 +s 14f12443104d8083 Modem 0 +s 14f12443104d8097 Modem 0 +d 14f12444 HSF 56k Data/Fax/Voice Modem (Mob WorldW SmartDAA) 0 +d 14f12445 HSF 56k Data/Fax/Voice/Spkp (w/HS) Modem (Mob WorldW SmartDAA) 0 +d 14f12446 HSF 56k Data/Fax/Voice/Spkp Modem (Mob WorldW SmartDAA) 0 +d 14f12463 HSF 56k Data/Fax Modem (Mob SmartDAA) 0 +d 14f12464 HSF 56k Data/Fax/Voice Modem (Mob SmartDAA) 0 +d 14f12465 HSF 56k Data/Fax/Voice/Spkp (w/HS) Modem (Mob SmartDAA) 0 +d 14f12466 HSF 56k Data/Fax/Voice/Spkp Modem (Mob SmartDAA) 0 +d 14f12f00 HSF 56k HSFi Modem 0 +s 14f12f0013e08d84 IBM HSFi V.90 0 +s 14f12f0013e08d85 Compaq Stinger 0 +s 14f12f0014f12004 Dynalink 56PMi 0 +d 14f12f02 HSF 56k HSFi Data/Fax 0 +d 14f12f11 HSF 56k HSFi Modem 0 +d 14f18234 RS8234 ATM SAR Controller [ServiceSAR Plus] 0 +d 14f18800 Winfast TV2000 XP 0 +v 14f2 MOBILITY Electronics 0 +d 14f20120 EV1000 bridge 0 +d 14f20121 EV1000 Parallel port 0 +d 14f20122 EV1000 Serial port 0 +d 14f20123 EV1000 Keyboard controller 0 +d 14f20124 EV1000 Mouse controller 0 +v 14f3 BroadLogic 0 +d 14f32030 2030 DVB-S Satellite Reciever 0 +d 14f32050 2050 DVB-T Terrestrial (Cable) Reciever 0 +d 14f32060 2060 ATSC Terrestrial (Cable) Reciever 0 +v 14f4 TOKYO Electronic Industry CO Ltd 0 +v 14f5 SOPAC Ltd 0 +v 14f6 COYOTE Technologies LLC 0 +v 14f7 WOLF Technology Inc 0 +v 14f8 AUDIOCODES Inc 0 +d 14f82077 TP-240 dual span E1 VoIP PCI card 0 +v 14f9 AG COMMUNICATIONS 0 +v 14fa WANDEL & GOCHERMANN 0 +v 14fb TRANSAS MARINE (UK) Ltd 0 +v 14fc Quadrics Ltd 0 +d 14fc0000 QsNet Elan3 Network Adapter 0 +d 14fc0001 QsNetII Elan4 Network Adapter 0 +v 14fd JAPAN Computer Industry Inc 0 +v 14fe ARCHTEK TELECOM Corp 0 +v 14ff TWINHEAD INTERNATIONAL Corp 0 +v 1500 DELTA Electronics, Inc 0 +d 15001360 RTL81xx RealTek Ethernet 0 +v 1501 BANKSOFT CANADA Ltd 0 +v 1502 MITSUBISHI ELECTRIC LOGISTICS SUPPORT Co Ltd 0 +v 1503 KAWASAKI LSI USA Inc 0 +v 1504 KAISER Electronics 0 +v 1505 ITA INGENIEURBURO FUR TESTAUFGABEN GmbH 0 +v 1506 CHAMELEON Systems Inc 0 +v 1507 Motorola ?? / HTEC 0 Should be HTEC Ltd, but there are no known HTEC chips and 1507 is already used by mistake by Motorola (see vendor ID 1057). +d 15070001 MPC105 [Eagle] 0 +d 15070002 MPC106 [Grackle] 0 +d 15070003 MPC8240 [Kahlua] 0 +d 15070100 MC145575 [HFC-PCI] 0 +d 15070431 KTI829c 100VG 0 +d 15074801 Raven 0 +d 15074802 Falcon 0 +d 15074803 Hawk 0 +d 15074806 CPX8216 0 +v 1508 HONDA CONNECTORS/MHOTRONICS Inc 0 +v 1509 FIRST INTERNATIONAL Computer Inc 0 +v 150a FORVUS RESEARCH Inc 0 +v 150b YAMASHITA Systems Corp 0 +v 150c KYOPAL CO Ltd 0 +v 150d WARPSPPED Inc 0 +v 150e C-PORT Corp 0 +v 150f INTEC GmbH 0 +v 1510 BEHAVIOR TECH Computer Corp 0 +v 1511 CENTILLIUM Technology Corp 0 +v 1512 ROSUN Technologies Inc 0 +v 1513 Raychem 0 +v 1514 TFL LAN Inc 0 +v 1515 Advent design 0 +v 1516 MYSON Technology Inc 0 +d 15160800 MTD-8xx 100/10M Ethernet PCI Adapter 0 +d 15160803 SURECOM EP-320X-S 100/10M Ethernet PCI Adapter 0 +s 15160803132010bd SURECOM EP-320X-S 100/10M Ethernet PCI Adapter 0 +d 15160891 MTD-8xx 100/10M Ethernet PCI Adapter 0 +v 1517 ECHOTEK Corp 0 +v 1518 PEP MODULAR Computers GmbH 0 +v 1519 TELEFON AKTIEBOLAGET LM Ericsson 0 +v 151a Globetek 0 +d 151a1002 PCI-1002 0 +d 151a1004 PCI-1004 0 +d 151a1008 PCI-1008 0 +v 151b COMBOX Ltd 0 +v 151c DIGITAL AUDIO LABS Inc 0 +v 151d Fujitsu Computer Products Of America 0 +v 151e MATRIX Corp 0 +v 151f TOPIC SEMICONDUCTOR Corp 0 +d 151f0000 TP560 Data/Fax/Voice 56k modem 0 +v 1520 CHAPLET System Inc 0 +v 1521 BELL Corp 0 +v 1522 MainPine Ltd 0 +d 15220100 PCI <-> IOBus Bridge 0 +s 1522010015220200 RockForceDUO 2 Port V.92/V.44 Data/Fax/Voice Modem 0 +s 1522010015220300 RockForceQUATRO 4 Port V.92/V.44 Data/Fax/Voice Modem 0 +s 1522010015220400 RockForceDUO+ 2 Port V.92/V.44 Data/Fax/Voice Modem 0 +s 1522010015220500 RockForceQUATRO+ 4 Port V.92/V.44 Data/Fax/Voice Modem 0 +s 1522010015220600 RockForce+ 2 Port V.90 Data/Fax/Voice Modem 0 +s 1522010015220700 RockForce+ 4 Port V.90 Data/Fax/Voice Modem 0 +s 1522010015220800 RockForceOCTO+ 8 Port V.92/V.44 Data/Fax/Voice Modem 0 +s 1522010015220c00 RockForceDUO+ 2 Port V.92/V.44 Data, V.34 Super-G3 Fax, Voice Modem 0 +s 1522010015220d00 RockForceQUATRO+ 4 Port V.92/V.44 Data, V.34 Super-G3 Fax, Voice Modem 0 +s 1522010015221d00 RockForceOCTO+ 8 Port V.92/V.44 Data, V.34 Super-G3 Fax, Voice Modem 0 this is a correction to a recent entry. 1522:0E00 should be 1522:1D00 +v 1523 MUSIC Semiconductors 0 +v 1524 ENE Technology Inc 0 +d 15240510 CB710 Memory Card Reader Controller 0 +d 15240610 PCI Smart Card Reader Controller 0 +d 15241211 CB1211 Cardbus Controller 0 +d 15241225 CB1225 Cardbus Controller 0 +d 15241410 CB1410 Cardbus Controller 0 +s 152414101025005a TravelMate 290 0 +d 15241411 CB-710/2/4 Cardbus Controller 0 +d 15241412 CB-712/4 Cardbus Controller 0 +d 15241420 CB1420 Cardbus Controller 0 +d 15241421 CB-720/2/4 Cardbus Controller 0 +d 15241422 CB-722/4 Cardbus Controller 0 +v 1525 IMPACT Technologies 0 +v 1526 ISS, Inc 0 +v 1527 SOLECTRON 0 +v 1528 ACKSYS 0 +v 1529 AMERICAN MICROSystems Inc 0 +v 152a QUICKTURN DESIGN Systems 0 +v 152b FLYTECH Technology CO Ltd 0 +v 152c MACRAIGOR Systems LLC 0 +v 152d QUANTA Computer Inc 0 +v 152e MELEC Inc 0 +v 152f PHILIPS - CRYPTO 0 +v 1530 ACQIS Technology Inc 0 +v 1531 CHRYON Corp 0 +v 1532 ECHELON Corp 0 +v 1533 BALTIMORE 0 +v 1534 ROAD Corp 0 +v 1535 EVERGREEN Technologies Inc 0 +v 1537 DATALEX COMMUNCATIONS 0 +v 1538 ARALION Inc 0 +d 15380303 ARS106S Ultra ATA 133/100/66 Host Controller 0 +v 1539 ATELIER INFORMATIQUES et ELECTRONIQUE ETUDES S.A. 0 +v 153a ONO SOKKI 0 +v 153b TERRATEC Electronic GmbH 0 +d 153b1144 Aureon 5.1 0 +d 153b1147 Aureon 5.1 Sky 0 Terratec seems to use several IDs for the same card. +d 153b1158 Philips Semiconductors SAA7134 (rev 01) [Terratec Cinergy 600 TV] 0 +v 153c ANTAL Electronic 0 +v 153d FILANET Corp 0 +v 153e TECHWELL Inc 0 +v 153f MIPS DENMARK 0 +v 1540 PROVIDEO MULTIMEDIA Co Ltd 0 +v 1541 MACHONE Communications 0 +v 1542 VIVID Technology Inc 0 +v 1543 SILICON Laboratories 0 +d 15433052 Intel 537 [Winmodem] 0 +d 15434c22 Si3036 MC'97 DAA 0 +v 1544 DCM DATA Systems 0 +v 1545 VISIONTEK 0 +v 1546 IOI Technology Corp 0 +v 1547 MITUTOYO Corp 0 +v 1548 JET PROPULSION Laboratory 0 +v 1549 INTERCONNECT Systems Solutions 0 +v 154a MAX Technologies Inc 0 +v 154b COMPUTEX Co Ltd 0 +v 154c VISUAL Technology Inc 0 +v 154d PAN INTERNATIONAL Industrial Corp 0 +v 154e SERVOTEST Ltd 0 +v 154f STRATABEAM Technology 0 +v 1550 OPEN NETWORK Co Ltd 0 +v 1551 SMART Electronic DEVELOPMENT GmBH 0 +v 1552 RACAL AIRTECH Ltd 0 +v 1553 CHICONY Electronics Co Ltd 0 +v 1554 PROLINK Microsystems Corp 0 +v 1555 GESYTEC GmBH 0 +v 1556 PLD APPLICATIONS 0 +v 1557 MEDIASTAR Co Ltd 0 +v 1558 CLEVO/KAPOK Computer 0 +v 1559 SI LOGIC Ltd 0 +v 155a INNOMEDIA Inc 0 +v 155b PROTAC INTERNATIONAL Corp 0 +v 155c Cemax-Icon Inc 0 +v 155d Mac System Co Ltd 0 +v 155e LP Elektronik GmbH 0 +v 155f Perle Systems Ltd 0 +v 1560 Terayon Communications Systems 0 +v 1561 Viewgraphics Inc 0 +v 1562 Symbol Technologies 0 +v 1563 A-Trend Technology Co Ltd 0 +v 1564 Yamakatsu Electronics Industry Co Ltd 0 +v 1565 Biostar Microtech Int'l Corp 0 +v 1566 Ardent Technologies Inc 0 +v 1567 Jungsoft 0 +v 1568 DDK Electronics Inc 0 +v 1569 Palit Microsystems Inc. 0 +v 156a Avtec Systems 0 +v 156b 2wire Inc 0 +v 156c Vidac Electronics GmbH 0 +v 156d Alpha-Top Corp 0 +v 156e Alfa Inc 0 +v 156f M-Systems Flash Disk Pioneers Ltd 0 +v 1570 Lecroy Corp 0 +v 1571 Contemporary Controls 0 +d 1571a001 CCSI PCI20-485 ARCnet 0 +d 1571a002 CCSI PCI20-485D ARCnet 0 +d 1571a003 CCSI PCI20-485X ARCnet 0 +d 1571a004 CCSI PCI20-CXB ARCnet 0 +d 1571a005 CCSI PCI20-CXS ARCnet 0 +d 1571a006 CCSI PCI20-FOG-SMA ARCnet 0 +d 1571a007 CCSI PCI20-FOG-ST ARCnet 0 +d 1571a008 CCSI PCI20-TB5 ARCnet 0 +d 1571a009 CCSI PCI20-5-485 5Mbit ARCnet 0 +d 1571a00a CCSI PCI20-5-485D 5Mbit ARCnet 0 +d 1571a00b CCSI PCI20-5-485X 5Mbit ARCnet 0 +d 1571a00c CCSI PCI20-5-FOG-ST 5Mbit ARCnet 0 +d 1571a00d CCSI PCI20-5-FOG-SMA 5Mbit ARCnet 0 +d 1571a201 CCSI PCI22-485 10Mbit ARCnet 0 +d 1571a202 CCSI PCI22-485D 10Mbit ARCnet 0 +d 1571a203 CCSI PCI22-485X 10Mbit ARCnet 0 +d 1571a204 CCSI PCI22-CHB 10Mbit ARCnet 0 +d 1571a205 CCSI PCI22-FOG_ST 10Mbit ARCnet 0 +d 1571a206 CCSI PCI22-THB 10Mbit ARCnet 0 +v 1572 Otis Elevator Company 0 +v 1573 Lattice - Vantis 0 +v 1574 Fairchild Semiconductor 0 +v 1575 Voltaire Advanced Data Security Ltd 0 +v 1576 Viewcast COM 0 +v 1578 HITT 0 +v 1579 Dual Technology Corp 0 +v 157a Japan Elecronics Ind Inc 0 +v 157b Star Multimedia Corp 0 +v 157c Eurosoft (UK) 0 +d 157c8001 Fix2000 PCI Y2K Compliance Card 0 +v 157d Gemflex Networks 0 +v 157e Transition Networks 0 +v 157f PX Instruments Technology Ltd 0 +v 1580 Primex Aerospace Co 0 +v 1581 SEH Computertechnik GmbH 0 +v 1582 Cytec Corp 0 +v 1583 Inet Technologies Inc 0 +v 1584 Uniwill Computer Corp 0 +v 1585 Logitron 0 +v 1586 Lancast Inc 0 +v 1587 Konica Corp 0 +v 1588 Solidum Systems Corp 0 +v 1589 Atlantek Microsystems Pty Ltd 0 +v 158a Digalog Systems Inc 0 +v 158b Allied Data Technologies 0 +v 158c Hitachi Semiconductor & Devices Sales Co Ltd 0 +v 158d Point Multimedia Systems 0 +v 158e Lara Technology Inc 0 +v 158f Ditect Coop 0 +v 1590 3pardata Inc 0 +v 1591 ARN 0 +v 1592 Syba Tech Ltd 0 +d 15920781 Multi-IO Card 0 +d 15920782 Parallel Port Card 2xEPP 0 +d 15920783 Multi-IO Card 0 +d 15920785 Multi-IO Card 0 +d 15920786 Multi-IO Card 0 +d 15920787 Multi-IO Card 0 +d 15920788 Multi-IO Card 0 +d 1592078a Multi-IO Card 0 +v 1593 Bops Inc 0 +v 1594 Netgame Ltd 0 +v 1595 Diva Systems Corp 0 +v 1596 Folsom Research Inc 0 +v 1597 Memec Design Services 0 +v 1598 Granite Microsystems 0 +v 1599 Delta Electronics Inc 0 +v 159a General Instrument 0 +v 159b Faraday Technology Corp 0 +v 159c Stratus Computer Systems 0 +v 159d Ningbo Harrison Electronics Co Ltd 0 +v 159e A-Max Technology Co Ltd 0 +v 159f Galea Network Security 0 +v 15a0 Compumaster SRL 0 +v 15a1 Geocast Network Systems 0 +v 15a2 Catalyst Enterprises Inc 0 +d 15a20001 TA700 PCI Bus Analyzer/Exerciser 0 +v 15a3 Italtel 0 +v 15a4 X-Net OY 0 +v 15a5 Toyota Macs Inc 0 +v 15a6 Sunlight Ultrasound Technologies Ltd 0 +v 15a7 SSE Telecom Inc 0 +v 15a8 Shanghai Communications Technologies Center 0 +v 15aa Moreton Bay 0 +v 15ab Bluesteel Networks Inc 0 +v 15ac North Atlantic Instruments 0 +v 15ad VMware Inc 0 +d 15ad0405 [VMware SVGA II] PCI Display Adapter 0 +d 15ad0710 Virtual SVGA 0 +d 15ad0720 VMware High-Speed Virtual NIC [vmxnet] 0 +v 15ae Amersham Pharmacia Biotech 0 +v 15b0 Zoltrix International Ltd 0 +v 15b1 Source Technology Inc 0 +v 15b2 Mosaid Technologies Inc 0 +v 15b3 Mellanox Technologies 0 +d 15b35274 MT21108 InfiniBridge 0 +d 15b35a44 MT23108 InfiniHost 0 +d 15b35a45 MT23108 [Infinihost HCA Flash Recovery] 0 +d 15b35a46 MT23108 PCI Bridge 0 +d 15b35e8c MT24204 [InfiniHost III Lx HCA] 0 +d 15b35e8d MT24204 [InfiniHost III Lx HCA Flash Recovery] 0 +d 15b36278 MT25208 InfiniHost III Ex (Tavor compatibility mode) 0 +d 15b36279 MT25208 [InfiniHost III Ex HCA Flash Recovery] 0 +d 15b36282 MT25208 InfiniHost III Ex 0 +v 15b4 CCI/TRIAD 0 +v 15b5 Cimetrics Inc 0 +v 15b6 Texas Memory Systems Inc 0 +v 15b7 Sandisk Corp 0 +v 15b8 ADDI-DATA GmbH 0 +v 15b9 Maestro Digital Communications 0 +v 15ba Impacct Technology Corp 0 +v 15bb Portwell Inc 0 +v 15bc Agilent Technologies 0 +d 15bc2922 64 Bit, 133MHz PCI-X Exerciser & Protocol Checker 0 +d 15bc2928 64 Bit, 66MHz PCI Exerciser & Analyzer 0 +d 15bc2929 64 Bit, 133MHz PCI-X Analyzer & Exerciser 0 +v 15bd DFI Inc 0 +v 15be Sola Electronics 0 +v 15bf High Tech Computer Corp (HTC) 0 +v 15c0 BVM Ltd 0 +v 15c1 Quantel 0 +v 15c2 Newer Technology Inc 0 +v 15c3 Taiwan Mycomp Co Ltd 0 +v 15c4 EVSX Inc 0 +v 15c5 Procomp Informatics Ltd 0 +d 15c58010 1394b - 1394 Firewire 3-Port Host Adapter Card 0 +v 15c6 Technical University of Budapest 0 +v 15c7 Tateyama System Laboratory Co Ltd 0 +d 15c70349 Tateyama C-PCI PLC/NC card Rev.01A 0 +v 15c8 Penta Media Co Ltd 0 +v 15c9 Serome Technology Inc 0 +v 15ca Bitboys OY 0 +v 15cb AG Electronics Ltd 0 +v 15cc Hotrail Inc 0 +v 15cd Dreamtech Co Ltd 0 +v 15ce Genrad Inc 0 +v 15cf Hilscher GmbH 0 +v 15d1 Infineon Technologies AG 0 +v 15d2 FIC (First International Computer Inc) 0 +v 15d3 NDS Technologies Israel Ltd 0 +v 15d4 Iwill Corp 0 +v 15d5 Tatung Co 0 +v 15d6 Entridia Corp 0 +v 15d7 Rockwell-Collins Inc 0 +v 15d8 Cybernetics Technology Co Ltd 0 +v 15d9 Super Micro Computer Inc 0 +v 15da Cyberfirm Inc 0 +v 15db Applied Computing Systems Inc 0 +v 15dc Litronic Inc 0 +d 15dc0001 Argus 300 PCI Cryptography Module 0 +v 15dd Sigmatel Inc 0 +v 15de Malleable Technologies Inc 0 +v 15df Infinilink Corp 0 +v 15e0 Cacheflow Inc 0 +v 15e1 Voice Technologies Group Inc 0 +v 15e2 Quicknet Technologies Inc 0 +v 15e3 Networth Technologies Inc 0 +v 15e4 VSN Systemen BV 0 +v 15e5 Valley technologies Inc 0 +v 15e6 Agere Inc 0 +v 15e7 Get Engineering Corp 0 +v 15e8 National Datacomm Corp 0 +d 15e80130 Wireless PCI Card 0 +v 15e9 Pacific Digital Corp 0 +d 15e91841 ADMA-100 DiscStaQ ATA Controller 0 +v 15ea Tokyo Denshi Sekei K.K. 0 +v 15eb Drsearch GmbH 0 +v 15ec Beckhoff GmbH 0 +d 15ec3101 FC3101 Profibus DP 1 Channel PCI 0 +d 15ec5102 FC5102 0 +v 15ed Macrolink Inc 0 +v 15ee In Win Development Inc 0 +v 15ef Intelligent Paradigm Inc 0 +v 15f0 B-Tree Systems Inc 0 +v 15f1 Times N Systems Inc 0 +v 15f2 Diagnostic Instruments Inc 0 +v 15f3 Digitmedia Corp 0 +v 15f4 Valuesoft 0 +v 15f5 Power Micro Research 0 +v 15f6 Extreme Packet Device Inc 0 +v 15f7 Banctec 0 +v 15f8 Koga Electronics Co 0 +v 15f9 Zenith Electronics Corp 0 +v 15fa J.P. Axzam Corp 0 +v 15fb Zilog Inc 0 +v 15fc Techsan Electronics Co Ltd 0 +v 15fd N-CUBED.NET 0 +v 15fe Kinpo Electronics Inc 0 +v 15ff Fastpoint Technologies Inc 0 +v 1600 Northrop Grumman - Canada Ltd 0 +v 1601 Tenta Technology 0 +v 1602 Prosys-tec Inc 0 +v 1603 Nokia Wireless Communications 0 +v 1604 Central System Research Co Ltd 0 +v 1605 Pairgain Technologies 0 +v 1606 Europop AG 0 +v 1607 Lava Semiconductor Manufacturing Inc 0 +v 1608 Automated Wagering International 0 +v 1609 Scimetric Instruments Inc 0 +v 1612 Telesynergy Research Inc. 0 +v 1619 FarSite Communications Ltd 0 +d 16190400 FarSync T2P (2 port X.21/V.35/V.24) 0 +d 16190440 FarSync T4P (4 port X.21/V.35/V.24) 0 +v 161f Rioworks 0 www.rioworks.com +v 1626 TDK Semiconductor Corp. 0 +d 16268410 RTL81xx Fast Ethernet 0 +v 1629 Kongsberg Spacetec AS 0 +d 16291003 Format synchronizer v3.0 0 +d 16292002 Fast Universal Data Output 0 +v 1637 Linksys 0 This seems to occur on their 802.11b Wireless card WMP-11 +d 16373874 Linksys 802.11b WMP11 PCI Wireless card 0 +v 1638 Standard Microsystems Corp [SMC] 0 +d 16381100 SMC2602W EZConnect / Addtron AWA-100 / Eumitcom PCI WL11000 0 +v 163c Smart Link Ltd. 0 +d 163c3052 SmartLink SmartPCI562 56K Modem 0 +d 163c5449 SmartPCI561 Modem 0 +v 1657 Brocade Communications Systems, Inc. 0 +v 165a Epix Inc 0 +d 165ac100 PIXCI(R) CL1 Camera Link Video Capture Board [custom QL5232] 0 +d 165ad200 PIXCI(R) D2X Digital Video Capture Board [custom QL5232] 0 +d 165ad300 PIXCI(R) D3X Digital Video Capture Board [custom QL5232] 0 +v 165d Hsing Tech. Enterprise Co., Ltd. 0 +v 1661 Worldspace Corp. 0 +v 1668 Actiontec Electronics Inc 0 +d 16680100 Mini-PCI bridge 0 +v 166d Broadcom Corporation 0 Formerly SiByte, Inc. +d 166d0001 SiByte BCM1125/1125H/1250 System-on-a-Chip PCI 0 +d 166d0002 SiByte BCM1125H/1250 System-on-a-Chip HyperTransport 0 +v 1677 Bernecker + Rainer 0 +d 1677104e 5LS172.6 B&R Dual CAN Interface Card 0 +d 167712d7 5LS172.61 B&R Dual CAN Interface Card 0 +v 1681 Hercules 0 +d 16810010 Hercules 3d Prophet II Ultra 64MB [ 350 MHz NV15BR core, 128-bit DDR @ 460 MHz, 1.5v AGP4x ] 0 More specs, more accurate desc. +v 1688 CastleNet Technology Inc. 0 +d 16881170 WLAN 802.11b card 0 +v 168c Atheros Communications, Inc. 0 +d 168c0007 AR5000 802.11a Wireless Adapter 0 +d 168c0011 AR5210 802.11a NIC 0 +d 168c0012 AR5211 802.11ab NIC 0 +d 168c0013 AR5212 802.11abg NIC 0 +s 168c001311863202 D-link DWL-G650 B3 Wireless cardbus adapter 0 +s 168c001311863203 DWL-G520 Wireless PCI Adapter 0 +s 168c001311863a13 DWL-G520 Wireless PCI Adapter rev. B 0 +s 168c001311863a94 C54C Wireless 801.11g cardbus 0 +s 168c001313854d00 Netgear WG311T Wireless PCI Adapter 0 +s 168c001314b70a60 8482-WD ORiNOCO 11a/b/g Wireless PCI Adapter 0 +s 168c0013168c0013 WG511T Wireless CardBus Adapter 0 +s 168c0013168c1025 DWL-G650B2 Wireless CardBus Adapter 0 +s 168c0013168c2026 Netgate 5354MP ARIES a(108Mb turbo)/b/g MiniPCI Adapter 0 +d 168c1014 AR5212 802.11abg NIC 0 +v 16a5 Tekram Technology Co.,Ltd. 0 +v 16ab Global Sun Technology Inc 0 +d 16ab1100 GL24110P 0 +d 16ab1101 PLX9052 PCMCIA-to-PCI Wireless LAN 0 +d 16ab1102 PCMCIA-to-PCI Wireless Network Bridge 0 +v 16ae Safenet Inc 0 +d 16ae1141 SafeXcel-1141 0 +v 16b4 Aspex Semiconductor Ltd 0 +v 16be Creatix Polymedia GmbH 0 +v 16ca CENATEK Inc 0 +d 16ca0001 Rocket Drive DL 0 +v 16cd Densitron Technologies 0 +v 16df PIKA Technologies Inc. 0 www.pikatechnologies.com +v 16e3 European Space Agency 0 +d 16e31e0f LEON2FT Processor 0 +v 16ec U.S. Robotics 0 +d 16ec00ff USR997900 10/100 Mbps PCI Network Card 0 +d 16ec3685 Wireless Access PCI Adapter Model 022415 0 +v 16ed Sycron N. V. 0 +d 16ed1001 UMIO communication card 0 +v 16f3 Jetway Information Co., Ltd. 0 +v 16f4 Vweb Corp 0 +d 16f48000 VW2010 0 +v 16f6 VideoTele.com, Inc. 0 +v 1702 Internet Machines Corporation (IMC) 0 www.internetmachines.com +v 1705 Digital First, Inc. 0 +v 170b NetOctave 0 +d 170b0100 NSP2000-SSL crypto accelerator 0 +v 170c YottaYotta Inc. 0 +v 1725 Vitesse Semiconductor 0 Seems to be a 2nd ID for Vitesse Semiconductor +d 17257174 VSC7174 PCI/PCI-X Serial ATA Host Bus Controller 0 +v 172a Accelerated Encryption 0 +v 1734 Fujitsu Siemens Computer GmbH 0 +v 1737 Linksys 0 +d 17370013 WMP54G Wireless Pci Card 0 +d 17370015 WMP54GS Wireless Pci Card 0 +d 17371032 Gigabit Network Adapter 0 +s 1737103217370015 EG1032 v2 Instant Gigabit Network Adapter 0 +d 17371064 Gigabit Network Adapter 0 +s 1737106417370016 EG1064 v2 Instant Gigabit Network Adapter 0 +d 1737ab08 21x4x DEC-Tulip compatible 10/100 Ethernet 0 +d 1737ab09 21x4x DEC-Tulip compatible 10/100 Ethernet 0 +v 173b Altima (nee Broadcom) 0 +d 173b03e8 AC1000 Gigabit Ethernet 0 +d 173b03e9 AC1001 Gigabit Ethernet 0 +d 173b03ea AC9100 Gigabit Ethernet 0 +s 173b03ea173b0001 AC1002 0 +d 173b03eb AC1003 Gigabit Ethernet 0 +v 1743 Peppercon AG 0 +d 17438139 ROL/F-100 Fast Ethernet Adapter with ROL 0 +v 1749 RLX Technologies 0 +v 174b PC Partner Limited 0 +v 174d WellX Telecom SA 0 +v 175c AudioScience Inc 0 +v 175e Sanera Systems, Inc. 0 +v 1787 Hightech Information System Ltd. 0 +v 1796 Research Centre Juelich 0 also used by Struck Innovative Systeme for joint developments +d 17960001 SIS1100 [Gigabit link] 0 +d 17960002 HOTlink 0 +d 17960003 Counter Timer 0 +d 17960004 CAMAC Controller 0 +d 17960005 PROFIBUS 0 +d 17960006 AMCC HOTlink 0 +v 1797 JumpTec h, GMBH 0 +v 1799 Belkin 0 +d 17996001 Wireless PCI Card - F5D6001 0 +d 17996020 Wireless PCMCIA Card - F5D6020 0 +d 17996060 Wireless PDA Card - F5D6060 0 +d 17997000 Wireless PCI Card - F5D7000 0 +v 17a0 Genesys Logic, Inc 0 +d 17a08033 GL880S USB 1.1 controller 0 +d 17a08034 GL880S USB 2.0 controller 0 +v 17af Hightech Information System Ltd. 0 +v 17b3 Hawking Technologies 0 +d 17b3ab08 PN672TX 10/100 Ethernet 0 +v 17b4 Indra Networks, Inc. 0 +d 17b40011 WebEnhance 100 GZIP Compression Card 0 +v 17c0 Wistron Corp. 0 +v 17c2 Newisys, Inc. 0 +v 17cc NetChip Technology, Inc 0 +d 17cc2280 USB 2.0 0 +v 17d5 S2io Inc. 0 S2io ships 10Gb PCI-X Ethernet adapters www.s2io.com +v 17ee Connect Components Ltd 0 http://www.connect3d.com +v 17fe Linksys, A Division of Cisco Systems 0 +d 17fe2220 [AirConn] INPROCOMM IPN 2220 Wireless LAN Adapter (rev 01) 0 +v 1813 Ambient Technologies Inc 0 +d 18134000 HaM controllerless modem 0 +s 1813400016be0001 V9x HAM Data Fax Modem 0 +d 18134100 HaM plus Data Fax Modem 0 +s 1813410016be0002 V9x HAM 1394 0 +v 1814 RaLink 0 +d 18140101 Wireless PCI Adpator RT2400 / RT2460 0 +d 18140201 Ralink RT2500 802.11 Cardbus Reference Card 0 +s 181402011371001e CWC-854 Wireless-G CardBus Adapter 0 +s 181402011371001f CWM-854 Wireless-G Mini PCI Adapter 0 +s 1814020113710020 CWP-854 Wireless-G PCI Adapter 0 +v 1820 InfiniCon Systems Inc. 0 +v 1822 Twinhan Technology Co. Ltd 0 +v 182d SiteCom Europe BV 0 +d 182d3069 ISDN PCI DC-105V2 0 HFC-based ISDN card +v 1830 Credence Systems Corporation 0 +v 183b MikroM GmbH 0 +d 183b08a7 MVC100 DVI 0 +d 183b08a8 MVC101 SDI 0 +d 183b08a9 MVC102 DVI+Audio 0 +v 1849 ASRock Incorporation 0 +v 1851 Microtune, Inc. 0 +v 1852 Anritsu Corp. 0 +v 1867 Topspin Communications 0 +d 18675a44 MT23108 PCI-X HCA 0 +d 18675a45 MT23108 PCI-X HCA flash recovery 0 +d 18675a46 MT23108 PCI-X HCA bridge 0 +d 18676278 MT25208 InfiniHost III Ex (Tavor compatibility mode) 0 +d 18676282 MT25208 InfiniHost III Ex 0 +v 1888 Varisys Ltd 0 +d 18880301 VMFX1 FPGA PMC module 0 +d 18880601 VSM2 dual PMC carrier 0 +d 18880710 VS14x series PowerPC PCI board 0 +d 18880720 VS24x series PowerPC PCI board 0 +v 1894 KNC One 0 found e.g. on KNC DVB-S card +v 1896 B&B Electronics Manufacturing Company, Inc. 0 +v 18a1 Astute Networks Inc. 0 +v 18ac DViCO Corporation 0 +d 18acd810 FusionHDTV 3 Gold 0 +v 18bc Info-Tek Corp. 0 +v 18c8 Cray Inc 0 assigned to Octigabay System, which has been acquired by Cray +v 18c9 ARVOO Engineering BV 0 +v 18ca XGI - Xabre Graphics Inc 0 +d 18ca0040 Volari V8 0 +v 18e6 MPL AG 0 +d 18e60001 OSCI [Octal Serial Communication Interface] 0 +v 18f7 Commtech, Inc. 0 +d 18f70001 Fastcom ESCC-PCI-335 0 +d 18f70002 Fastcom 422/4-PCI-335 0 +d 18f70004 Fastcom 422/2-PCI-335 0 +d 18f70005 Fastcom IGESCC-PCI-ISO/1 0 +d 18f7000a Fastcom 232/4-PCI-335 0 +v 18fb Resilience Corporation 0 +v 1a08 Sierra semiconductor 0 +d 1a080000 SC15064 0 +v 1b13 Jaton Corp 0 +v 1c1c Symphony 0 +d 1c1c0001 82C101 0 +v 1d44 DPT 0 +d 1d44a400 PM2x24/PM3224 0 +v 1de1 Tekram Technology Co.,Ltd. 0 +d 1de10391 TRM-S1040 0 +d 1de12020 DC-390 0 +d 1de1690c 690c 0 +d 1de1dc29 DC290 0 +v 1fc0 Tumsan Oy 0 +d 1fc00300 E2200 Dual E1/Rawpipe Card 0 +v 2000 Smart Link Ltd. 0 +v 2001 Temporal Research Ltd 0 +v 2003 Smart Link Ltd. 0 +v 2004 Smart Link Ltd. 0 +v 21c3 21st Century Computer Corp. 0 +v 2348 Racore 0 +d 23482010 8142 100VG/AnyLAN 0 +v 2646 Kingston Technologies 0 +v 270b Xantel Corporation 0 +v 270f Chaintech Computer Co. Ltd 0 +v 2711 AVID Technology Inc. 0 +v 2a15 3D Vision(?) 0 +v 3000 Hansol Electronics Inc. 0 +v 3142 Post Impression Systems. 0 +v 3388 Hint Corp 0 +d 33880013 HiNT HC4 PCI to ISDN bridge, Multimedia audio controller 0 +d 33880014 HiNT HC4 PCI to ISDN bridge, Network controller 0 +d 33880020 HB6 Universal PCI-PCI bridge (transparent mode) 0 +d 33880021 HB6 Universal PCI-PCI bridge (non-transparent mode) 0 +s 338800214c531050 CT7 mainboard 0 +s 338800214c531080 CT8 mainboard 0 +s 338800214c5310a0 CA3/CR3 mainboard 0 +s 338800214c533010 PPCI mezzanine (32-bit PMC) 0 +s 338800214c533011 PPCI mezzanine (64-bit PMC) 0 +d 33880022 HiNT HB4 PCI-PCI Bridge (PCI6150) 0 +d 33880026 HB2 PCI-PCI Bridge 0 +d 3388101a E.Band [AudioTrak Inca88] 0 +d 3388101b E.Band [AudioTrak Inca88] 0 +d 33888011 VXPro II Chipset 0 +s 3388801133888011 VXPro II Chipset CPU to PCI Bridge 0 +d 33888012 VXPro II Chipset 0 +s 3388801233888012 VXPro II Chipset PCI to ISA Bridge 0 +d 33888013 VXPro II IDE 0 +s 3388801333888013 VXPro II Chipset EIDE Controller 0 +v 3411 Quantum Designs (H.K.) Inc 0 +v 3513 ARCOM Control Systems Ltd 0 +v 3842 eVga.com. Corp. 0 +v 38ef 4Links 0 +v 3d3d 3DLabs 0 +d 3d3d0001 GLINT 300SX 0 +d 3d3d0002 GLINT 500TX 0 +d 3d3d0003 GLINT Delta 0 +d 3d3d0004 Permedia 0 +d 3d3d0005 Permedia 0 +d 3d3d0006 GLINT MX 0 +d 3d3d0007 3D Extreme 0 +d 3d3d0008 GLINT Gamma G1 0 +d 3d3d0009 Permedia II 2D+3D 0 +s 3d3d000910400011 AccelStar II 0 +s 3d3d000913e91000 6221L-4U 0 +s 3d3d00093d3d0100 AccelStar II 3D Accelerator 0 +s 3d3d00093d3d0111 Permedia 3:16 0 +s 3d3d00093d3d0114 Santa Ana 0 +s 3d3d00093d3d0116 Oxygen GVX1 0 +s 3d3d00093d3d0119 Scirocco 0 +s 3d3d00093d3d0120 Santa Ana PCL 0 +s 3d3d00093d3d0125 Oxygen VX1 0 +s 3d3d00093d3d0127 Permedia3 Create! 0 +d 3d3d000a GLINT R3 0 +s 3d3d000a3d3d0121 Oxygen VX1 0 +d 3d3d000c GLINT R3 [Oxygen VX1] 0 +s 3d3d000c3d3d0144 Oxygen VX1-4X AGP [Permedia 4] 0 +d 3d3d000d GLint R4 rev A 0 +d 3d3d0011 GLint R4 rev B 0 +d 3d3d0012 GLint R5 rev A 0 +d 3d3d0013 GLint R5 rev B 0 +d 3d3d0020 VP10 visual processor 0 +d 3d3d0022 VP10 visual processor 0 P10 generic II +d 3d3d0024 VP9 visual processor 0 +d 3d3d0100 Permedia II 2D+3D 0 +d 3d3d07a1 Wildcat III 6210 0 +d 3d3d07a2 Sun XVR-500 Graphics Accelerator 0 +d 3d3d07a3 Wildcat IV 7210 0 +d 3d3d1004 Permedia 0 +d 3d3d3d04 Permedia 0 +d 3d3dffff Glint VGA 0 +v 4005 Avance Logic Inc. 0 +d 40050300 ALS300 PCI Audio Device 0 +d 40050308 ALS300+ PCI Audio Device 0 +d 40050309 PCI Input Controller 0 +d 40051064 ALG-2064 0 +d 40052064 ALG-2064i 0 +d 40052128 ALG-2364A GUI Accelerator 0 +d 40052301 ALG-2301 0 +d 40052302 ALG-2302 0 +d 40052303 AVG-2302 GUI Accelerator 0 +d 40052364 ALG-2364A 0 +d 40052464 ALG-2464 0 +d 40052501 ALG-2564A/25128A 0 +d 40054000 ALS4000 Audio Chipset 0 +s 4005400040054000 ALS4000 Audio Chipset 0 +d 40054710 ALC200/200P 0 +v 4033 Addtron Technology Co, Inc. 0 +d 40331360 RTL8139 Ethernet 0 +v 4143 Digital Equipment Corp 0 +v 4144 Alpha Data 0 +v 416c Aladdin Knowledge Systems 0 +d 416c0100 AladdinCARD 0 +d 416c0200 CPC 0 +v 4444 Internext Compression Inc 0 +d 44440016 iTVC16 (CX23416) MPEG-2 Encoder 0 +s 4444001600704009 WinTV PVR 250 0 +d 44440803 iTVC15 MPEG-2 Encoder 0 +s 4444080300704000 WinTV PVR-350 0 +s 4444080300704001 WinTV PVR-250 0 +v 4468 Bridgeport machines 0 +v 4594 Cogetec Informatique Inc 0 +v 45fb Baldor Electric Company 0 +v 4680 Umax Computer Corp 0 +v 4843 Hercules Computer Technology Inc 0 +v 4916 RedCreek Communications Inc 0 +d 49161960 RedCreek PCI adapter 0 +v 4943 Growth Networks 0 +v 494f ACCES I/O Products, Inc. 0 +d 494f10e8 LPCI-COM-8SM 0 +v 4978 Axil Computer Inc 0 +v 4a14 NetVin 0 +d 4a145000 NV5000SC 0 +s 4a1450004a145000 RT8029-Based Ethernet Adapter 0 +v 4b10 Buslogic Inc. 0 +v 4c48 LUNG HWA Electronics 0 +v 4c53 SBS Technologies 0 +d 4c530000 PLUSTEST device 0 +s 4c5300004c533000 PLUSTEST card (PC104+) 0 +s 4c5300004c533001 PLUSTEST card (PMC) 0 +d 4c530001 PLUSTEST-MM device 0 +s 4c5300014c533002 PLUSTEST-MM card (PMC) 0 +v 4ca1 Seanix Technology Inc 0 +v 4d51 MediaQ Inc. 0 +d 4d510200 MQ-200 0 +v 4d54 Microtechnica Co Ltd 0 +v 4ddc ILC Data Device Corp 0 +d 4ddc0100 DD-42924I5-300 (ARINC 429 Data Bus) 0 +d 4ddc0801 BU-65570I1 MIL-STD-1553 Test and Simulation 0 +d 4ddc0802 BU-65570I2 MIL-STD-1553 Test and Simulation 0 +d 4ddc0811 BU-65572I1 MIL-STD-1553 Test and Simulation 0 +d 4ddc0812 BU-65572I2 MIL-STD-1553 Test and Simulation 0 +d 4ddc0881 BU-65570T1 MIL-STD-1553 Test and Simulation 0 +d 4ddc0882 BU-65570T2 MIL-STD-1553 Test and Simulation 0 +d 4ddc0891 BU-65572T1 MIL-STD-1553 Test and Simulation 0 +d 4ddc0892 BU-65572T2 MIL-STD-1553 Test and Simulation 0 +d 4ddc0901 BU-65565C1 MIL-STD-1553 Data Bus 0 +d 4ddc0902 BU-65565C2 MIL-STD-1553 Data Bus 0 +d 4ddc0903 BU-65565C3 MIL-STD-1553 Data Bus 0 +d 4ddc0904 BU-65565C4 MIL-STD-1553 Data Bus 0 +d 4ddc0b01 BU-65569I1 MIL-STD-1553 Data Bus 0 +d 4ddc0b02 BU-65569I2 MIL-STD-1553 Data Bus 0 +d 4ddc0b03 BU-65569I3 MIL-STD-1553 Data Bus 0 +d 4ddc0b04 BU-65569I4 MIL-STD-1553 Data Bus 0 +v 5046 GemTek Technology Corporation 0 +d 50461001 PCI Radio 0 +v 5053 Voyetra Technologies 0 +d 50532010 Daytona Audio Adapter 0 +v 5136 S S Technologies 0 +v 5143 Qualcomm Inc 0 +v 5145 Ensoniq (Old) 0 +d 51453031 Concert AudioPCI 0 +v 5168 Animation Technologies Inc. 0 +v 5301 Alliance Semiconductor Corp. 0 +d 53010001 ProMotion aT3D 0 +v 5333 S3 Inc. 0 +d 53330551 Plato/PX (system) 0 +d 53335631 86c325 [ViRGE] 0 +d 53338800 86c866 [Vision 866] 0 +d 53338801 86c964 [Vision 964] 0 +d 53338810 86c764_0 [Trio 32 vers 0] 0 +d 53338811 86c764/765 [Trio32/64/64V+] 0 +d 53338812 86cM65 [Aurora64V+] 0 +d 53338813 86c764_3 [Trio 32/64 vers 3] 0 +d 53338814 86c767 [Trio 64UV+] 0 +d 53338815 86cM65 [Aurora 128] 0 +d 5333883d 86c988 [ViRGE/VX] 0 +d 53338870 FireGL 0 +d 53338880 86c868 [Vision 868 VRAM] vers 0 0 +d 53338881 86c868 [Vision 868 VRAM] vers 1 0 +d 53338882 86c868 [Vision 868 VRAM] vers 2 0 +d 53338883 86c868 [Vision 868 VRAM] vers 3 0 +d 533388b0 86c928 [Vision 928 VRAM] vers 0 0 +d 533388b1 86c928 [Vision 928 VRAM] vers 1 0 +d 533388b2 86c928 [Vision 928 VRAM] vers 2 0 +d 533388b3 86c928 [Vision 928 VRAM] vers 3 0 +d 533388c0 86c864 [Vision 864 DRAM] vers 0 0 +d 533388c1 86c864 [Vision 864 DRAM] vers 1 0 +d 533388c2 86c864 [Vision 864-P DRAM] vers 2 0 +d 533388c3 86c864 [Vision 864-P DRAM] vers 3 0 +d 533388d0 86c964 [Vision 964 VRAM] vers 0 0 +d 533388d1 86c964 [Vision 964 VRAM] vers 1 0 +d 533388d2 86c964 [Vision 964-P VRAM] vers 2 0 +d 533388d3 86c964 [Vision 964-P VRAM] vers 3 0 +d 533388f0 86c968 [Vision 968 VRAM] rev 0 0 +d 533388f1 86c968 [Vision 968 VRAM] rev 1 0 +d 533388f2 86c968 [Vision 968 VRAM] rev 2 0 +d 533388f3 86c968 [Vision 968 VRAM] rev 3 0 +d 53338900 86c755 [Trio 64V2/DX] 0 +s 5333890053338900 86C775 Trio64V2/DX 0 +d 53338901 86c775/86c785 [Trio 64V2/DX or /GX] 0 +s 5333890153338901 86C775 Trio64V2/DX, 86C785 Trio64V2/GX 0 +d 53338902 Plato/PX 0 +d 53338903 Trio 3D business multimedia 0 +d 53338904 Trio 64 3D 0 +s 53338904101400db Integrated Trio3D 0 +s 5333890453338904 86C365 Trio3D AGP 0 +d 53338905 Trio 64V+ family 0 +d 53338906 Trio 64V+ family 0 +d 53338907 Trio 64V+ family 0 +d 53338908 Trio 64V+ family 0 +d 53338909 Trio 64V+ family 0 +d 5333890a Trio 64V+ family 0 +d 5333890b Trio 64V+ family 0 +d 5333890c Trio 64V+ family 0 +d 5333890d Trio 64V+ family 0 +d 5333890e Trio 64V+ family 0 +d 5333890f Trio 64V+ family 0 +d 53338a01 ViRGE/DX or /GX 0 +s 53338a010e11b032 ViRGE/GX 0 +s 53338a0110b41617 Nitro 3D 0 +s 53338a0110b41717 Nitro 3D 0 +s 53338a0153338a01 ViRGE/DX 0 +d 53338a10 ViRGE/GX2 0 +s 53338a1010928a10 Stealth 3D 4000 0 +d 53338a13 86c368 [Trio 3D/2X] 0 +s 53338a1353338a13 Trio3D/2X 0 +d 53338a20 86c794 [Savage 3D] 0 +s 53338a2053338a20 86C391 Savage3D 0 +d 53338a21 86c390 [Savage 3D/MV] 0 +s 53338a2153338a21 86C390 Savage3D/MV 0 +d 53338a22 Savage 4 0 +s 53338a2210338068 Savage 4 0 +s 53338a2210338069 Savage 4 0 +s 53338a2210338110 Savage4 LT 0 +s 53338a22105d0018 SR9 8Mb SDRAM 0 +s 53338a22105d002a SR9 Pro 16Mb SDRAM 0 +s 53338a22105d003a SR9 Pro 32Mb SDRAM 0 +s 53338a22105d092f SR9 Pro+ 16Mb SGRAM 0 +s 53338a2210924207 Stealth III S540 0 +s 53338a2210924800 Stealth III S540 0 +s 53338a2210924807 SpeedStar A90 0 +s 53338a2210924808 Stealth III S540 0 +s 53338a2210924809 Stealth III S540 0 +s 53338a221092480e Stealth III S540 0 +s 53338a2210924904 Stealth III S520 0 +s 53338a2210924905 SpeedStar A200 0 +s 53338a2210924a09 Stealth III S540 0 +s 53338a2210924a0b Stealth III S540 Xtreme 0 +s 53338a2210924a0f Stealth III S540 0 +s 53338a2210924e01 Stealth III S540 0 +s 53338a221102101d 3d Blaster Savage 4 0 +s 53338a221102101e 3d Blaster Savage 4 0 +s 53338a2253338100 86C394-397 Savage4 SDRAM 100 0 +s 53338a2253338110 86C394-397 Savage4 SDRAM 110 0 +s 53338a2253338125 86C394-397 Savage4 SDRAM 125 0 +s 53338a2253338143 86C394-397 Savage4 SDRAM 143 0 +s 53338a2253338a22 86C394-397 Savage4 0 +s 53338a2253338a2e 86C394-397 Savage4 32bit 0 +s 53338a2253339125 86C394-397 Savage4 SGRAM 125 0 +s 53338a2253339143 86C394-397 Savage4 SGRAM 143 0 +d 53338a23 Savage 4 0 +d 53338a25 ProSavage PM133 0 +d 53338a26 ProSavage KM133 0 +d 53338c00 ViRGE/M3 0 +d 53338c01 ViRGE/MX 0 +s 53338c0111790001 ViRGE/MX 0 +d 53338c02 ViRGE/MX+ 0 +d 53338c03 ViRGE/MX+MV 0 +d 53338c10 86C270-294 Savage/MX-MV 0 +d 53338c11 82C270-294 Savage/MX 0 +d 53338c12 86C270-294 Savage/IX-MV 0 +s 53338c121014017f ThinkPad T20 0 +d 53338c13 86C270-294 Savage/IX 0 +s 53338c1311790001 Magnia Z310 0 +d 53338c22 SuperSavage MX/128 0 +d 53338c24 SuperSavage MX/64 0 +d 53338c26 SuperSavage MX/64C 0 +d 53338c2a SuperSavage IX/128 SDR 0 +d 53338c2b SuperSavage IX/128 DDR 0 +d 53338c2c SuperSavage IX/64 SDR 0 +d 53338c2d SuperSavage IX/64 DDR 0 +d 53338c2e SuperSavage IX/C SDR 0 +s 53338c2e101401fc ThinkPad T23 (2647-4MG) 0 +d 53338c2f SuperSavage IX/C DDR 0 +d 53338d01 86C380 [ProSavageDDR K4M266] 0 +d 53338d02 VT8636A [ProSavage KN133] AGP4X VGA Controller (TwisterK) 0 +d 53338d03 VT8751 [ProSavageDDR P4M266] 0 +d 53338d04 VT8375 [ProSavage8 KM266/KL266] 0 +d 53339102 86C410 Savage 2000 0 +s 5333910210925932 Viper II Z200 0 +s 5333910210925934 Viper II Z200 0 +s 5333910210925952 Viper II Z200 0 +s 5333910210925954 Viper II Z200 0 +s 5333910210925a35 Viper II Z200 0 +s 5333910210925a37 Viper II Z200 0 +s 5333910210925a55 Viper II Z200 0 +s 5333910210925a57 Viper II Z200 0 +d 5333ca00 SonicVibes 0 +v 544c Teralogic Inc 0 +d 544c0350 TL880-based HDTV/ATSC tuner 0 +v 5455 Technische University Berlin 0 +d 54554458 S5933 0 +v 5519 Cnet Technologies, Inc. 0 +v 5544 Dunord Technologies 0 +d 55440001 I-30xx Scanner Interface 0 +v 5555 Genroco, Inc 0 +d 55550003 TURBOstor HFP-832 [HiPPI NIC] 0 +v 5654 VoiceTronix Pty Ltd 0 +d 56543132 OpenSwitch12 0 +v 5700 Netpower 0 +v 5851 Exacq Technologies 0 +v 6356 UltraStor 0 +v 6374 c't Magazin für Computertechnik 0 +d 63746773 GPPCI 0 +v 6409 Logitec Corp. 0 +v 6666 Decision Computer International Co. 0 +d 66660001 PCCOM4 0 +d 66660002 PCCOM8 0 +v 7604 O.N. Electronic Co Ltd. 0 +v 7bde MIDAC Corporation 0 +v 7fed PowerTV 0 +v 8008 Quancom Electronic GmbH 0 +d 80080010 WDOG1 [PCI-Watchdog 1] 0 +d 80080011 PWDOG2 [PCI-Watchdog 2] 0 +v 807d Asustek Computer, Inc. 0 Wrong ID used in subsystem ID of AsusTek PCI-USB2 PCI card. +v 8086 Intel Corp. 0 +d 80860007 82379AB 0 +d 80860008 Extended Express System Support Controller 0 +s 8086000800081000 WorldMark 4300 INCA ASIC 0 +d 80860039 21145 Fast Ethernet 0 +d 80860122 82437FX 0 +d 80860309 80303 I/O Processor PCI-to-PCI Bridge 0 +d 8086030d 80312 I/O Companion Chip PCI-to-PCI Bridge 0 +d 80860326 6700/6702PXH I/OxAPIC Interrupt Controller A 0 +d 80860327 6700PXH I/OxAPIC Interrupt Controller B 0 +d 80860329 6700PXH PCI Express-to-PCI Bridge A 0 +d 8086032a 6700PXH PCI Express-to-PCI Bridge B 0 +d 8086032c 6702PXH PCI Express-to-PCI Bridge A 0 +d 80860330 80332 [Dobson] I/O processor 0 A-segment bridge +d 80860331 80332 [Dobson] I/O processor 0 A-segment IOAPIC +d 80860332 80332 [Dobson] I/O processor 0 B-segment bridge +d 80860333 80332 [Dobson] I/O processor 0 B-segment IOAPIC +d 80860334 80332 [Dobson] I/O processor 0 Address Translation Unit (ATU) +d 80860335 80331 [Lindsay] I/O processor 0 PCI-X bridge +d 80860336 80331 [Lindsay] I/O processor 0 Address Translation Unit (ATU) +d 80860340 41210 [Lanai] Serial to Parallel PCI Bridge 0 A-segment bridge +d 80860341 41210 [Lanai] Serial to Parallel PCI Bridge 0 B-segment bridge +d 80860482 82375EB/SB PCI to EISA Bridge 0 +d 80860483 82424TX/ZX [Saturn] CPU to PCI bridge 0 +d 80860484 82378ZB/IB, 82379AB (SIO, SIO.A) PCI to ISA Bridge 0 +d 80860486 82425EX/ZX [Aries] PCIset with ISA bridge 0 +d 808604a3 82434LX/NX [Mercury/Neptune] Processor to PCI bridge 0 +d 808604d0 82437FX [Triton FX] 0 +d 80860500 E8870 Processor bus control 0 +d 80860501 E8870 Memory controller 0 +d 80860502 E8870 Scalability Port 0 0 and registers common to both SPs +d 80860503 E8870 Scalability Port 1 0 and global performance monitoring +d 80860510 E8870IO Hub Interface Port 0 registers (8-bit compatibility port) 0 +d 80860511 E8870IO Hub Interface Port 1 registers 0 +d 80860512 E8870IO Hub Interface Port 2 registers 0 +d 80860513 E8870IO Hub Interface Port 3 registers 0 +d 80860514 E8870IO Hub Interface Port 4 registers 0 +d 80860515 E8870IO General SIOH registers 0 +d 80860516 E8870IO RAS registers 0 +d 80860530 E8870SP Scalability Port 0 registers 0 +d 80860531 E8870SP Scalability Port 1 registers 0 +d 80860532 E8870SP Scalability Port 2 registers 0 +d 80860533 E8870SP Scalability Port 3 registers 0 +d 80860534 E8870SP Scalability Port 4 registers 0 +d 80860535 E8870SP Scalability Port 5 registers 0 +d 80860536 E8870SP Interleave registers 0 and 1 0 (bi-interleave 0) and global registers that are neither per-port nor per-interleave +d 80860537 E8870SP Interleave registers 2 and 3 0 (bi-interleave 1) +d 80860600 RAID Controller 0 +s 80860600808601c1 ICP Vortex GDT8546RZ 0 +s 80860600808601f7 SCRU32 0 +d 8086061f 80303 I/O Processor 0 uninitialized SRCU32 RAID Controller +d 80860960 80960RP [i960 RP Microprocessor/Bridge] 0 +d 80860962 80960RM [i960RM Bridge] 0 +d 80860964 80960RP [i960 RP Microprocessor/Bridge] 0 +d 80861000 82542 Gigabit Ethernet Controller 0 +s 808610000e11b0df NC1632 Gigabit Ethernet Adapter (1000-SX) 0 +s 808610000e11b0e0 NC1633 Gigabit Ethernet Adapter (1000-LX) 0 +s 808610000e11b123 NC1634 Gigabit Ethernet Adapter (1000-SX) 0 +s 8086100010140119 Netfinity Gigabit Ethernet SX Adapter 0 +s 8086100080861000 PRO/1000 Gigabit Server Adapter 0 +d 80861001 82543GC Gigabit Ethernet Controller (Fiber) 0 +s 808610010e11004a NC6136 Gigabit Server Adapter 0 +s 80861001101401ea Netfinity Gigabit Ethernet SX Adapter 0 +s 8086100180861002 PRO/1000 F Server Adapter 0 +s 8086100180861003 PRO/1000 F Server Adapter 0 +d 80861002 Pro 100 LAN+Modem 56 Cardbus II 0 +s 808610028086200e Pro 100 LAN+Modem 56 Cardbus II 0 +s 8086100280862013 Pro 100 SR Mobile Combo Adapter 0 +s 8086100280862017 Pro 100 S Combo Mobile Adapter 0 +d 80861004 82543GC Gigabit Ethernet Controller (Copper) 0 +s 808610040e110049 NC7132 Gigabit Upgrade Module 0 +s 808610040e11b1a4 NC7131 Gigabit Server Adapter 0 +s 80861004101410f2 Gigabit Ethernet Server Adapter 0 +s 8086100480861004 PRO/1000 T Server Adapter 0 +s 8086100480862004 PRO/1000 T Server Adapter 0 +d 80861008 82544EI Gigabit Ethernet Controller (Copper) 0 +s 8086100810140269 iSeries 1000/100/10 Ethernet Adapter 0 +s 808610081028011c PRO/1000 XT Network Connection 0 +s 8086100880861107 PRO/1000 XT Server Adapter 0 +s 8086100880862107 PRO/1000 XT Server Adapter 0 +s 8086100880862110 PRO/1000 XT Server Adapter 0 +s 8086100880863108 PRO/1000 XT Network Connection 0 +d 80861009 82544EI Gigabit Ethernet Controller (Fiber) 0 +s 8086100910140268 iSeries Gigabit Ethernet Adapter 0 +s 8086100980861109 PRO/1000 XF Server Adapter 0 +s 8086100980862109 PRO/1000 XF Server Adapter 0 +d 8086100c 82544GC Gigabit Ethernet Controller (Copper) 0 +s 8086100c80861112 PRO/1000 T Desktop Adapter 0 +s 8086100c80862112 PRO/1000 T Desktop Adapter 0 +d 8086100d 82544GC Gigabit Ethernet Controller (LOM) 0 +s 8086100d10280123 PRO/1000 XT Network Connection 0 +s 8086100d1079891f 82544GC Based Network Connection 0 +s 8086100d4c531080 CT8 mainboard 0 +s 8086100d8086110d 82544GC Based Network Connection 0 +d 8086100e 82540EM Gigabit Ethernet Controller 0 +s 8086100e10140265 PRO/1000 MT Network Connection 0 +s 8086100e10140267 PRO/1000 MT Network Connection 0 +s 8086100e1014026a PRO/1000 MT Network Connection 0 +s 8086100e1028002e Optiplex GX260 0 +s 8086100e10280151 PRO/1000 MT Network Connection 0 +s 8086100e107b8920 PRO/1000 MT Desktop Adapter 0 +s 8086100e8086001e PRO/1000 MT Desktop Adapter 0 +s 8086100e8086002e PRO/1000 MT Desktop Adapter 0 +d 8086100f 82545EM Gigabit Ethernet Controller (Copper) 0 +s 8086100f10140269 iSeries 1000/100/10 Ethernet Adapter 0 +s 8086100f1014028e PRO/1000 MT Network Connection 0 +s 8086100f80861000 PRO/1000 MT Network Connection 0 +s 8086100f80861001 PRO/1000 MT Server Adapter 0 +d 80861010 82546EB Gigabit Ethernet Controller (Copper) 0 +s 808610101014027c PRO/1000 MT Dual Port Network Adapter 0 +s 8086101018fb7872 RESlink-X 0 +s 808610104c531080 CT8 mainboard 0 +s 808610104c5310a0 CA3/CR3 mainboard 0 +s 8086101080861011 PRO/1000 MT Dual Port Server Adapter 0 +s 808610108086101a PRO/1000 MT Dual Port Network Adapter 0 +s 8086101080863424 SE7501HG2 Mainboard 0 +d 80861011 82545EM Gigabit Ethernet Controller (Fiber) 0 +s 8086101110140268 iSeries Gigabit Ethernet Adapter 0 +s 8086101180861002 PRO/1000 MF Server Adapter 0 +s 8086101180861003 PRO/1000 MF Server Adapter (LX) 0 +d 80861012 82546EB Gigabit Ethernet Controller (Fiber) 0 +s 8086101280861012 PRO/1000 MF Dual Port Server Adapter 0 +d 80861013 82541EI Gigabit Ethernet Controller (Copper) 0 +s 8086101380860013 PRO/1000 MT Network Connection 0 +s 8086101380861013 IBM ThinkCentre Network Card 0 +s 8086101380861113 PRO/1000 MT Desktop Adapter 0 +d 80861014 82541ER Gigabit Ethernet Controller 0 +d 80861015 82540EM Gigabit Ethernet Controller (LOM) 0 +d 80861016 82540EP Gigabit Ethernet Controller (LOM) 0 +s 808610161014052c PRO/1000 MT Mobile Connection 0 +s 8086101611790001 PRO/1000 MT Mobile Connection 0 +s 8086101680861016 PRO/1000 MT Mobile Connection 0 +d 80861017 82540EP Gigabit Ethernet Controller (LOM) 0 +s 8086101780861017 PR0/1000 MT Desktop Connection 0 +d 80861018 82541EI Gigabit Ethernet Controller 0 Update controller name from 82541EP to 82541EI +s 8086101880861018 PRO/1000 MT Desktop Adapter 0 +d 80861019 82547EI Gigabit Ethernet Controller (LOM) 0 +s 8086101914581019 GA-8IPE1000 Pro2 motherboard (865PE) 0 +s 8086101980861019 PRO/1000 CT Desktop Connection 0 +s 808610198086301f D865PERL mainboard 0 +s 8086101980863427 S875WP1-E mainboard 0 +d 8086101d 82546EB Gigabit Ethernet Controller 0 +s 8086101d80861000 PRO/1000 MT Quad Port Server Adapter 0 +d 8086101e 82540EP Gigabit Ethernet Controller (Mobile) 0 +s 8086101e10140549 PRO/1000 MT Mobile Connection 0 +s 8086101e11790001 PRO/1000 MT Mobile Connection 0 +s 8086101e8086101e PRO/1000 MT Mobile Connection 0 +d 80861026 82545GM Gigabit Ethernet Controller 0 +s 8086102680861000 PRO/1000 MT Server Connection 0 +s 8086102680861001 PRO/1000 MT Server Adapter 0 +s 8086102680861002 PRO/1000 MT Server Adapter 0 +s 8086102680861026 PRO/1000 MT Server Connection 0 +d 80861027 82545GM Gigabit Ethernet Controller 0 +s 8086102780861001 PRO/1000 MF Server Adapter(LX) 0 +s 8086102780861002 PRO/1000 MF Server Adapter(LX) 0 +s 8086102780861003 PRO/1000 MF Server Adapter(LX) 0 +s 8086102780861027 PRO/1000 MF Server Adapter 0 +d 80861028 82545GM Gigabit Ethernet Controller 0 +s 8086102880861028 PRO/1000 MB Server Adapter 0 +d 80861029 82559 Ethernet Controller 0 +d 80861030 82559 InBusiness 10/100 0 +d 80861031 82801CAM (ICH3) PRO/100 VE (LOM) Ethernet Controller 0 +s 8086103110140209 ThinkPad A/T/X Series 0 +s 80861031104d80e7 Vaio PCG-GR214EP/GR214MP/GR215MP/GR314MP/GR315MP 0 +s 80861031107b5350 EtherExpress PRO/100 VE 0 +s 8086103111790001 EtherExpress PRO/100 VE 0 +s 80861031144dc000 EtherExpress PRO/100 VE 0 +s 80861031144dc001 EtherExpress PRO/100 VE 0 +s 80861031144dc003 EtherExpress PRO/100 VE 0 +s 80861031144dc006 vpr Matrix 170B4 0 +d 80861032 82801CAM (ICH3) PRO/100 VE Ethernet Controller 0 +d 80861033 82801CAM (ICH3) PRO/100 VM (LOM) Ethernet Controller 0 +d 80861034 82801CAM (ICH3) PRO/100 VM Ethernet Controller 0 +d 80861035 82801CAM (ICH3)/82562EH (LOM) Ethernet Controller 0 +d 80861036 82801CAM (ICH3) 82562EH Ethernet Controller 0 +d 80861037 82801CAM (ICH3) Chipset Ethernet Controller 0 +d 80861038 82801CAM (ICH3) PRO/100 VM (KM) Ethernet Controller 0 +d 80861039 82801DB PRO/100 VE (LOM) Ethernet Controller 0 +s 8086103910140267 NetVista A30p 0 +d 8086103a 82801DB PRO/100 VE (CNR) Ethernet Controller 0 +d 8086103b 82801DB PRO/100 VM (LOM) Ethernet Controller 0 +d 8086103c 82801DB PRO/100 VM (CNR) Ethernet Controller 0 +d 8086103d 82801DB PRO/100 VE (MOB) Ethernet Controller 0 +d 8086103e 82801DB PRO/100 VM (MOB) Ethernet Controller 0 +d 80861040 536EP Data Fax Modem 0 +s 8086104016be1040 V.9X DSP Data Fax Modem 0 +d 80861043 PRO/Wireless LAN 2100 3B Mini PCI Adapter 0 +s 8086104380862527 MIM2000/Centrino 0 +d 80861048 PRO/10GbE LR Server Adapter 0 +s 808610488086a01f PRO/10GbE LR Server Adapter 0 +s 808610488086a11f PRO/10GbE LR Server Adapter 0 +d 80861050 82562EZ 10/100 Ethernet Controller 0 +s 808610501462728c 865PE Neo2 (MS-6728) 0 +s 808610501462758c MS-6758 (875P Neo) 0 +s 8086105080863427 S875WP1-E mainboard 0 +d 80861051 82801EB/ER (ICH5/ICH5R) integrated LAN Controller 0 +d 80861059 82551QM Ethernet Controller 0 +d 80861064 82562ET/EZ/GT/GZ - PRO/100 VE (LOM) Ethernet Controller 0 ICH-6 Component +d 80861065 82562ET/EZ/GT/GZ - PRO/100 VE Ethernet Controller 0 ICH-6 Component +d 80861066 82562 EM/EX/GX - PRO/100 VM (LOM) Ethernet Controller 0 ICH-6 Component +d 80861067 82562 EM/EX/GX - PRO/100 VM Ethernet Controller 0 ICH-6 Component +d 80861068 82562ET/EZ/GT/GZ - PRO/100 VE (LOM) Ethernet Controller Mobile 0 ICH-6 Component +d 80861069 82562 EM/EX/GX - PRO/100 VM (LOM) Ethernet Controller Mobile 0 ICH-6 Component +d 8086106a 82562G \t- PRO/100 VE (LOM) Ethernet Controller 0 ICH-6 Component +d 8086106b 82562G \t- PRO/100 VE Ethernet Controller Mobile 0 ICH-6 Component +d 80861075 82547GI Gigabit Ethernet Controller 0 +s 8086107510280165 PowerEdge 750 0 +s 8086107580860075 PRO/1000 CT Network Connection 0 +s 8086107580861075 PRO/1000 CT Network Connection 0 +d 80861076 82541GI/PI Gigabit Ethernet Controller 0 +s 8086107610280165 PowerEdge 750 0 +s 8086107680860076 PRO/1000 MT Network Connection 0 +s 8086107680861076 PRO/1000 MT Network Connection 0 +s 8086107680861176 PRO/1000 MT Desktop Adapter 0 +s 8086107680861276 PRO/1000 MT Desktop Adapter 0 +d 80861077 82541GI Gigabit Ethernet Controller 0 +s 8086107711790001 PRO/1000 MT Mobile Connection 0 +s 8086107780860077 PRO/1000 MT Mobile Connection 0 +s 8086107780861077 PRO/1000 MT Mobile Connection 0 +d 80861078 82541EI Gigabit Ethernet Controller 0 +s 8086107880861078 PRO/1000 MT Network Connection 0 +d 80861079 82546GB Gigabit Ethernet Controller 0 +s 80861079103c12a6 HP Dual Port 1000Base-T [A9900A] 0 +s 80861079103c12cf HP Core Dual Port 1000Base-T [AB352A] 0 +s 808610794c531090 Cx9 / Vx9 mainboard 0 +s 808610794c5310b0 CL9 mainboard 0 +s 8086107980860079 PRO/1000 MT Dual Port Network Connection 0 +s 8086107980861079 PRO/1000 MT Dual Port Network Connection 0 +s 8086107980861179 PRO/1000 MT Dual Port Network Connection 0 +s 808610798086117a PRO/1000 MT Dual Port Server Adapter 0 +d 8086107a 82546GB Gigabit Ethernet Controller 0 +s 8086107a103c12a8 HP Dual Port 1000base-SX [A9899A] 0 +s 8086107a8086107a PRO/1000 MF Dual Port Server Adapter 0 +s 8086107a8086127a PRO/1000 MF Dual Port Server Adapter 0 +d 8086107b 82546GB Gigabit Ethernet Controller 0 +s 8086107b8086007b PRO/1000 MB Dual Port Server Connection 0 +s 8086107b8086107b PRO/1000 MB Dual Port Server Connection 0 +d 80861107 PRO/1000 MF Server Adapter (LX) 0 +d 80861130 82815 815 Chipset Host Bridge and Memory Controller Hub 0 +s 8086113010251016 Travelmate 612 TX 0 +s 8086113010438027 TUSL2-C Mainboard 0 +s 80861130104d80df Vaio PCG-FX403 0 +s 8086113080864532 D815EEA2 mainboard 0 +s 8086113080864557 D815EGEW Mainboard 0 +d 80861131 82815 815 Chipset AGP Bridge 0 +d 80861132 82815 CGC [Chipset Graphics Controller] 0 +s 8086113210251016 Travelmate 612 TX 0 +s 80861132104d80df Vaio PCG-FX403 0 +s 8086113280864532 D815EEA2 Mainboard 0 +s 8086113280864557 D815EGEW Mainboard 0 +d 80861161 82806AA PCI64 Hub Advanced Programmable Interrupt Controller 0 +s 8086116180861161 82806AA PCI64 Hub APIC 0 +d 80861162 Xscale 80200 Big Endian Companion Chip 0 +d 80861200 Intel IXP1200 Network Processor 0 +s 80861200172a0000 AEP SSL Accelerator 0 +d 80861209 8255xER/82551IT Fast Ethernet Controller 0 +s 808612094c531050 CT7 mainboard 0 +s 808612094c531051 CE7 mainboard 0 +s 808612094c531070 PC6 mainboard 0 +d 80861221 82092AA PCI to PCMCIA Bridge 0 +d 80861222 82092AA IDE Controller 0 +d 80861223 SAA7116 0 +d 80861225 82452KX/GX [Orion] 0 +d 80861226 82596 PRO/10 PCI 0 +d 80861227 82865 EtherExpress PRO/100A 0 +d 80861228 82556 EtherExpress PRO/100 Smart 0 +d 80861229 82557/8/9 [Ethernet Pro 100] 0 the revision field differentiates between them (1-3 is 82557, 4-5 is 82558, 6-8 is 82559, 9 is 82559ER) +s 808612290e113001 82559 Fast Ethernet LOM with Alert on LAN* 0 +s 808612290e113002 82559 Fast Ethernet LOM with Alert on LAN* 0 +s 808612290e113003 82559 Fast Ethernet LOM with Alert on LAN* 0 +s 808612290e113004 82559 Fast Ethernet LOM with Alert on LAN* 0 +s 808612290e113005 82559 Fast Ethernet LOM with Alert on LAN* 0 +s 808612290e113006 82559 Fast Ethernet LOM with Alert on LAN* 0 +s 808612290e113007 82559 Fast Ethernet LOM with Alert on LAN* 0 +s 808612290e11b01e NC3120 Fast Ethernet NIC 0 +s 808612290e11b01f NC3122 Fast Ethernet NIC (dual port) 0 +s 808612290e11b02f NC1120 Ethernet NIC 0 +s 808612290e11b04a Netelligent 10/100TX NIC with Wake on LAN 0 +s 808612290e11b0c6 NC3161 Fast Ethernet NIC (embedded, WOL) 0 +s 808612290e11b0c7 NC3160 Fast Ethernet NIC (embedded) 0 +s 808612290e11b0d7 NC3121 Fast Ethernet NIC (WOL) 0 +s 808612290e11b0dd NC3131 Fast Ethernet NIC (dual port) 0 +s 808612290e11b0de NC3132 Fast Ethernet Module (dual port) 0 +s 808612290e11b0e1 NC3133 Fast Ethernet Module (100-FX) 0 +s 808612290e11b134 NC3163 Fast Ethernet NIC (embedded, WOL) 0 +s 808612290e11b13c NC3162 Fast Ethernet NIC (embedded) 0 +s 808612290e11b144 NC3123 Fast Ethernet NIC (WOL) 0 +s 808612290e11b163 NC3134 Fast Ethernet NIC (dual port) 0 +s 808612290e11b164 NC3135 Fast Ethernet Upgrade Module (dual port) 0 +s 808612290e11b1a4 NC7131 Gigabit Server Adapter 0 +s 808612291014005c 82558B Ethernet Pro 10/100 0 +s 80861229101401bc 82559 Fast Ethernet LAN On Motherboard 0 +s 80861229101401f1 10/100 Ethernet Server Adapter 0 +s 80861229101401f2 10/100 Ethernet Server Adapter 0 +s 8086122910140207 Ethernet Pro/100 S 0 +s 8086122910140232 10/100 Dual Port Server Adapter 0 +s 808612291014023a ThinkPad R30 0 +s 808612291014105c Netfinity 10/100 0 +s 8086122910142205 ThinkPad A22p 0 +s 808612291014305c 10/100 EtherJet Management Adapter 0 +s 808612291014405c 10/100 EtherJet Adapter with Alert on LAN 0 +s 808612291014505c 10/100 EtherJet Secure Management Adapter 0 +s 808612291014605c 10/100 EtherJet Secure Management Adapter 0 +s 808612291014705c 10/100 Netfinity 10/100 Ethernet Security Adapter 0 +s 808612291014805c 10/100 Netfinity 10/100 Ethernet Security Adapter 0 +s 808612291028009b PowerEdge 2500/2550 0 +s 80861229102800ce PowerEdge 1400 0 +s 8086122910338000 PC-9821X-B06 0 +s 8086122910338016 PK-UG-X006 0 +s 808612291033801f PK-UG-X006 0 +s 8086122910338026 PK-UG-X006 0 +s 8086122910338063 82559-based Fast Ethernet Adapter 0 +s 8086122910338064 82559-based Fast Ethernet Adapter 0 +s 80861229103c10c0 NetServer 10/100TX 0 +s 80861229103c10c3 NetServer 10/100TX 0 +s 80861229103c10ca NetServer 10/100TX 0 +s 80861229103c10cb NetServer 10/100TX 0 +s 80861229103c10e3 NetServer 10/100TX 0 +s 80861229103c10e4 NetServer 10/100TX 0 +s 80861229103c1200 NetServer 10/100TX 0 +s 8086122910c31100 SmartEther100 SC1100 0 +s 8086122910cf1115 8255x-based Ethernet Adapter (10/100) 0 +s 8086122910cf1143 8255x-based Ethernet Adapter (10/100) 0 +s 8086122911790001 8255x-based Ethernet Adapter (10/100) 0 +s 8086122911790002 PCI FastEther LAN on Docker 0 +s 8086122911790003 8255x-based Fast Ethernet 0 +s 8086122912592560 AT-2560 100 0 +s 8086122912592561 AT-2560 100 FX Ethernet Adapter 0 +s 8086122912660001 NE10/100 Adapter 0 +s 8086122913e91000 6221L-4U 0 +s 80861229144d2501 SEM-2000 MiniPCI LAN Adapter 0 +s 80861229144d2502 SEM-2100IL MiniPCI LAN Adapter 0 +s 8086122916681100 EtherExpress PRO/100B (TX) (MiniPCI Ethernet+Modem) 0 +s 808612294c531080 CT8 mainboard 0 +s 8086122980860001 EtherExpress PRO/100B (TX) 0 +s 8086122980860002 EtherExpress PRO/100B (T4) 0 +s 8086122980860003 EtherExpress PRO/10+ 0 +s 8086122980860004 EtherExpress PRO/100 WfM 0 +s 8086122980860005 82557 10/100 0 +s 8086122980860006 82557 10/100 with Wake on LAN 0 +s 8086122980860007 82558 10/100 Adapter 0 +s 8086122980860008 82558 10/100 with Wake on LAN 0 +s 8086122980860009 EtherExpress PRO/100+ 0 +s 808612298086000a EtherExpress PRO/100+ Management Adapter 0 +s 808612298086000b EtherExpress PRO/100+ 0 +s 808612298086000c EtherExpress PRO/100+ Management Adapter 0 +s 808612298086000d EtherExpress PRO/100+ Alert On LAN II* Adapter 0 +s 808612298086000e EtherExpress PRO/100+ Management Adapter with Alert On LAN* 0 +s 808612298086000f EtherExpress PRO/100 Desktop Adapter 0 +s 8086122980860010 EtherExpress PRO/100 S Management Adapter 0 +s 8086122980860011 EtherExpress PRO/100 S Management Adapter 0 +s 8086122980860012 EtherExpress PRO/100 S Advanced Management Adapter (D) 0 +s 8086122980860013 EtherExpress PRO/100 S Advanced Management Adapter (E) 0 +s 8086122980860030 EtherExpress PRO/100 Management Adapter with Alert On LAN* GC 0 +s 8086122980860031 EtherExpress PRO/100 Desktop Adapter 0 +s 8086122980860040 EtherExpress PRO/100 S Desktop Adapter 0 +s 8086122980860041 EtherExpress PRO/100 S Desktop Adapter 0 +s 8086122980860042 EtherExpress PRO/100 Desktop Adapter 0 +s 8086122980860050 EtherExpress PRO/100 S Desktop Adapter 0 +s 8086122980861009 EtherExpress PRO/100+ Server Adapter 0 +s 808612298086100c EtherExpress PRO/100+ Server Adapter (PILA8470B) 0 +s 8086122980861012 EtherExpress PRO/100 S Server Adapter (D) 0 +s 8086122980861013 EtherExpress PRO/100 S Server Adapter (E) 0 +s 8086122980861015 EtherExpress PRO/100 S Dual Port Server Adapter 0 +s 8086122980861017 EtherExpress PRO/100+ Dual Port Server Adapter 0 +s 8086122980861030 EtherExpress PRO/100+ Management Adapter with Alert On LAN* G Server 0 +s 8086122980861040 EtherExpress PRO/100 S Server Adapter 0 +s 8086122980861041 EtherExpress PRO/100 S Server Adapter 0 +s 8086122980861042 EtherExpress PRO/100 Server Adapter 0 +s 8086122980861050 EtherExpress PRO/100 S Server Adapter 0 +s 8086122980861051 EtherExpress PRO/100 Server Adapter 0 +s 8086122980861052 EtherExpress PRO/100 Server Adapter 0 +s 80861229808610f0 EtherExpress PRO/100+ Dual Port Adapter 0 +s 8086122980862009 EtherExpress PRO/100 S Mobile Adapter 0 +s 808612298086200d EtherExpress PRO/100 Cardbus 0 +s 808612298086200e EtherExpress PRO/100 LAN+V90 Cardbus Modem 0 +s 808612298086200f EtherExpress PRO/100 SR Mobile Adapter 0 +s 8086122980862010 EtherExpress PRO/100 S Mobile Combo Adapter 0 +s 8086122980862013 EtherExpress PRO/100 SR Mobile Combo Adapter 0 +s 8086122980862016 EtherExpress PRO/100 S Mobile Adapter 0 +s 8086122980862017 EtherExpress PRO/100 S Combo Mobile Adapter 0 +s 8086122980862018 EtherExpress PRO/100 SR Mobile Adapter 0 +s 8086122980862019 EtherExpress PRO/100 SR Combo Mobile Adapter 0 +s 8086122980862101 EtherExpress PRO/100 P Mobile Adapter 0 +s 8086122980862102 EtherExpress PRO/100 SP Mobile Adapter 0 +s 8086122980862103 EtherExpress PRO/100 SP Mobile Adapter 0 +s 8086122980862104 EtherExpress PRO/100 SP Mobile Adapter 0 +s 8086122980862105 EtherExpress PRO/100 SP Mobile Adapter 0 +s 8086122980862106 EtherExpress PRO/100 P Mobile Adapter 0 +s 8086122980862107 EtherExpress PRO/100 Network Connection 0 +s 8086122980862108 EtherExpress PRO/100 Network Connection 0 +s 8086122980862200 EtherExpress PRO/100 P Mobile Combo Adapter 0 +s 8086122980862201 EtherExpress PRO/100 P Mobile Combo Adapter 0 +s 8086122980862202 EtherExpress PRO/100 SP Mobile Combo Adapter 0 +s 8086122980862203 EtherExpress PRO/100+ MiniPCI 0 +s 8086122980862204 EtherExpress PRO/100+ MiniPCI 0 +s 8086122980862205 EtherExpress PRO/100 SP Mobile Combo Adapter 0 +s 8086122980862206 EtherExpress PRO/100 SP Mobile Combo Adapter 0 +s 8086122980862207 EtherExpress PRO/100 SP Mobile Combo Adapter 0 +s 8086122980862208 EtherExpress PRO/100 P Mobile Combo Adapter 0 +s 8086122980862402 EtherExpress PRO/100+ MiniPCI 0 +s 8086122980862407 EtherExpress PRO/100+ MiniPCI 0 +s 8086122980862408 EtherExpress PRO/100+ MiniPCI 0 +s 8086122980862409 EtherExpress PRO/100+ MiniPCI 0 +s 808612298086240f EtherExpress PRO/100+ MiniPCI 0 +s 8086122980862410 EtherExpress PRO/100+ MiniPCI 0 +s 8086122980862411 EtherExpress PRO/100+ MiniPCI 0 +s 8086122980862412 EtherExpress PRO/100+ MiniPCI 0 +s 8086122980862413 EtherExpress PRO/100+ MiniPCI 0 +s 8086122980863000 82559 Fast Ethernet LAN on Motherboard 0 +s 8086122980863001 82559 Fast Ethernet LOM with Basic Alert on LAN* 0 +s 8086122980863002 82559 Fast Ethernet LOM with Alert on LAN II* 0 +s 8086122980863006 EtherExpress PRO/100 S Network Connection 0 +s 8086122980863007 EtherExpress PRO/100 S Network Connection 0 +s 8086122980863008 EtherExpress PRO/100 Network Connection 0 +s 8086122980863010 EtherExpress PRO/100 S Network Connection 0 +s 8086122980863011 EtherExpress PRO/100 S Network Connection 0 +s 8086122980863012 EtherExpress PRO/100 Network Connection 0 +s 8086122980863411 SDS2 Mainboard 0 +d 8086122d 430FX - 82437FX TSC [Triton I] 0 +d 8086122e 82371FB PIIX ISA [Triton I] 0 +d 80861230 82371FB PIIX IDE [Triton I] 0 +d 80861231 DSVD Modem 0 +d 80861234 430MX - 82371MX Mobile PCI I/O IDE Xcelerator (MPIIX) 0 +d 80861235 430MX - 82437MX Mob. System Ctrlr (MTSC) & 82438MX Data Path (MTDP) 0 +d 80861237 440FX - 82441FX PMC [Natoma] 0 +d 80861239 82371FB PIIX IDE Interface 0 +d 8086123b 82380PB PCI to PCI Docking Bridge 0 +d 8086123c 82380AB (MISA) Mobile PCI-to-ISA Bridge 0 +d 8086123d 683053 Programmable Interrupt Device 0 +d 8086123e 82466GX (IHPC) Integrated Hot-Plug Controller 0 in" hidden" mode +d 8086123f 82466GX Integrated Hot-Plug Controller (IHPC) 0 +d 80861240 82752 (752) AGP Graphics Accelerator 0 +d 8086124b 82380FB (MPCI2) Mobile Docking Controller 0 +d 80861250 430HX - 82439HX TXC [Triton II] 0 +d 80861360 82806AA PCI64 Hub PCI Bridge 0 +d 80861361 82806AA PCI64 Hub Controller (HRes) 0 +s 8086136180861361 82806AA PCI64 Hub Controller (HRes) 0 +s 8086136180868000 82806AA PCI64 Hub Controller (HRes) 0 +d 80861460 82870P2 P64H2 Hub PCI Bridge 0 +d 80861461 82870P2 P64H2 I/OxAPIC 0 +s 8086146115d93480 P4DP6 0 +s 808614614c531090 Cx9 / Vx9 mainboard 0 +d 80861462 82870P2 P64H2 Hot Plug Controller 0 +d 80861960 80960RP [i960RP Microprocessor] 0 +s 80861960101e0431 MegaRAID 431 RAID Controller 0 +s 80861960101e0438 MegaRAID 438 Ultra2 LVD RAID Controller 0 +s 80861960101e0466 MegaRAID 466 Express Plus RAID Controller 0 +s 80861960101e0467 MegaRAID 467 Enterprise 1500 RAID Controller 0 +s 80861960101e0490 MegaRAID 490 Express 300 RAID Controller 0 +s 80861960101e0762 MegaRAID 762 Express RAID Controller 0 +s 80861960101e09a0 PowerEdge Expandable RAID Controller 2/SC 0 +s 8086196010280467 PowerEdge Expandable RAID Controller 2/DC 0 +s 8086196010281111 PowerEdge Expandable RAID Controller 2/SC 0 +s 80861960103c03a2 MegaRAID 0 +s 80861960103c10c6 MegaRAID 438, HP NetRAID-3Si 0 +s 80861960103c10c7 MegaRAID T5, Integrated HP NetRAID 0 +s 80861960103c10cc MegaRAID, Integrated HP NetRAID 0 +s 80861960103c10cd HP NetRAID-1Si 0 +s 80861960105a0000 SuperTrak 0 +s 80861960105a2168 SuperTrak Pro 0 +s 80861960105a5168 SuperTrak66/100 0 +s 8086196011111111 MegaRAID 466, PowerEdge Expandable RAID Controller 2/SC 0 +s 8086196011111112 PowerEdge Expandable RAID Controller 2/SC 0 +s 80861960113c03a2 MegaRAID 0 +s 80861960e4bf1010 CG1-RADIO 0 +s 80861960e4bf1020 CU2-QUARTET 0 +s 80861960e4bf1040 CU1-CHORUS 0 +s 80861960e4bf3100 CX1-BAND 0 +d 80861962 80960RM [i960RM Microprocessor] 0 +s 80861962105a0000 SuperTrak SX6000 I2O CPU 0 +d 80861a21 82840 840 (Carmel) Chipset Host Bridge (Hub A) 0 +d 80861a23 82840 840 (Carmel) Chipset AGP Bridge 0 +d 80861a24 82840 840 (Carmel) Chipset PCI Bridge (Hub B) 0 +d 80861a30 82845 845 (Brookdale) Chipset Host Bridge 0 +s 80861a301028010e Optiplex GX240 0 +d 80861a31 82845 845 (Brookdale) Chipset AGP Bridge 0 +d 80862410 82801AA ISA Bridge (LPC) 0 +d 80862411 82801AA IDE 0 +d 80862412 82801AA USB 0 +d 80862413 82801AA SMBus 0 +d 80862415 82801AA AC'97 Audio 0 +s 8086241510280095 Precision Workstation 220 Integrated Digital Audio 0 +s 8086241511d40040 SoundMAX Integrated Digital Audio 0 +s 8086241511d40048 SoundMAX Integrated Digital Audio 0 +s 8086241511d45340 SoundMAX Integrated Digital Audio 0 +d 80862416 82801AA AC'97 Modem 0 +d 80862418 82801AA PCI Bridge 0 +d 80862420 82801AB ISA Bridge (LPC) 0 +d 80862421 82801AB IDE 0 +d 80862422 82801AB USB 0 +d 80862423 82801AB SMBus 0 +d 80862425 82801AB AC'97 Audio 0 +s 8086242511d40040 SoundMAX Integrated Digital Audio 0 +s 8086242511d40048 SoundMAX Integrated Digital Audio 0 +d 80862426 82801AB AC'97 Modem 0 +d 80862428 82801AB PCI Bridge 0 +d 80862440 82801BA ISA Bridge (LPC) 0 +d 80862442 82801BA/BAM USB (Hub #1) 0 +s 80862442101401c6 Netvista A40/A40p 0 +s 8086244210251016 Travelmate 612 TX 0 +s 808624421028010e Optiplex GX240 0 +s 8086244210438027 TUSL2-C Mainboard 0 +s 80862442104d80df Vaio PCG-FX403 0 +s 80862442147b0507 TH7II-RAID 0 +s 8086244280864532 D815EEA2 mainboard 0 +s 8086244280864557 D815EGEW Mainboard 0 +d 80862443 82801BA/BAM SMBus 0 +s 80862443101401c6 Netvista A40/A40p 0 +s 8086244310251016 Travelmate 612 TX 0 +s 808624431028010e Optiplex GX240 0 +s 8086244310438027 TUSL2-C Mainboard 0 +s 80862443104d80df Vaio PCG-FX403 0 +s 80862443147b0507 TH7II-RAID 0 +s 8086244380864532 D815EEA2 mainboard 0 +s 8086244380864557 D815EGEW Mainboard 0 +d 80862444 82801BA/BAM USB (Hub #2) 0 +s 8086244410251016 Travelmate 612 TX 0 +s 808624441028010e Optiplex GX240 0 +s 8086244410438027 TUSL2-C Mainboard 0 +s 80862444104d80df Vaio PCG-FX403 0 +s 80862444147b0507 TH7II-RAID 0 +s 8086244480864532 D815EEA2 mainboard 0 +d 80862445 82801BA/BAM AC'97 Audio 0 +s 80862445101401c6 Netvista A40/A40p 0 +s 8086244510251016 Travelmate 612 TX 0 +s 80862445104d80df Vaio PCG-FX403 0 +s 8086244514623370 STAC9721 AC 0 +s 80862445147b0507 TH7II-RAID 0 +s 8086244580864557 D815EGEW Mainboard 0 +d 80862446 82801BA/BAM AC'97 Modem 0 +s 8086244610251016 Travelmate 612 TX 0 +s 80862446104d80df Vaio PCG-FX403 0 +d 80862448 82801 Mobile PCI Bridge 0 +d 80862449 82801BA/BAM/CA/CAM Ethernet Controller 0 +s 808624490e110012 EtherExpress PRO/100 VM 0 +s 808624490e110091 EtherExpress PRO/100 VE 0 +s 80862449101401ce EtherExpress PRO/100 VE 0 +s 80862449101401dc EtherExpress PRO/100 VE 0 +s 80862449101401eb EtherExpress PRO/100 VE 0 +s 80862449101401ec EtherExpress PRO/100 VE 0 +s 8086244910140202 EtherExpress PRO/100 VE 0 +s 8086244910140205 EtherExpress PRO/100 VE 0 +s 8086244910140217 EtherExpress PRO/100 VE 0 +s 8086244910140234 EtherExpress PRO/100 VE 0 +s 808624491014023d EtherExpress PRO/100 VE 0 +s 8086244910140244 EtherExpress PRO/100 VE 0 +s 8086244910140245 EtherExpress PRO/100 VE 0 +s 8086244910140265 PRO/100 VE Desktop Connection 0 +s 8086244910140267 PRO/100 VE Desktop Connection 0 +s 808624491014026a PRO/100 VE Desktop Connection 0 +s 80862449109f315d EtherExpress PRO/100 VE 0 +s 80862449109f3181 EtherExpress PRO/100 VE 0 +s 808624491179ff01 PRO/100 VE Network Connection 0 +s 8086244911867801 EtherExpress PRO/100 VE 0 +s 80862449144d2602 HomePNA 1M CNR 0 +s 8086244980863010 EtherExpress PRO/100 VE 0 +s 8086244980863011 EtherExpress PRO/100 VM 0 +s 8086244980863012 82562EH based Phoneline 0 +s 8086244980863013 EtherExpress PRO/100 VE 0 +s 8086244980863014 EtherExpress PRO/100 VM 0 +s 8086244980863015 82562EH based Phoneline 0 +s 8086244980863016 EtherExpress PRO/100 P Mobile Combo 0 +s 8086244980863017 EtherExpress PRO/100 P Mobile 0 +s 8086244980863018 EtherExpress PRO/100 0 +d 8086244a 82801BAM IDE U100 0 +s 8086244a10251016 Travelmate 612TX 0 +s 8086244a104d80df Vaio PCG-FX403 0 +d 8086244b 82801BA IDE U100 0 +s 8086244b101401c6 Netvista A40/A40p 0 +s 8086244b1028010e Optiplex GX240 0 +s 8086244b10438027 TUSL2-C Mainboard 0 +s 8086244b147b0507 TH7II-RAID 0 +s 8086244b80864532 D815EEA2 mainboard 0 +s 8086244b80864557 D815EGEW Mainboard 0 +d 8086244c 82801BAM ISA Bridge (LPC) 0 +d 8086244e 82801 PCI Bridge 0 +s 8086244e10140267 NetVista A30p 0 +d 80862450 82801E ISA Bridge (LPC) 0 +d 80862452 82801E USB 0 +d 80862453 82801E SMBus 0 +d 80862459 82801E Ethernet Controller 0 0 +d 8086245b 82801E IDE U100 0 +d 8086245d 82801E Ethernet Controller 1 0 +d 8086245e 82801E PCI Bridge 0 +d 80862480 82801CA LPC Interface Controller 0 +d 80862482 82801CA/CAM USB (Hub #1) 0 +s 8086248210140220 ThinkPad A/T/X Series 0 +s 80862482104d80e7 VAIO PCG-GR214EP/GR214MP/GR215MP/GR314MP/GR315MP 0 +s 8086248215d93480 P4DP6 0 +s 8086248280861958 vpr Matrix 170B4 0 +s 8086248280863424 SE7501HG2 Mainboard 0 +s 8086248280864541 Latitude C640 0 +d 80862483 82801CA/CAM SMBus Controller 0 +s 8086248310140220 ThinkPad A/T/X Series 0 +s 80862483104d80e7 VAIO PCG-GR214EP/GR214MP/GR215MP/GR314MP/GR315MP 0 +s 8086248315d93480 P4DP6 0 +s 8086248380861958 vpr Matrix 170B4 0 +d 80862484 82801CA/CAM USB (Hub #2) 0 +s 8086248410140220 ThinkPad A/T/X Series 0 +s 80862484104d80e7 VAIO PCG-GR214EP/GR214MP/GR215MP/GR314MP/GR315MP 0 +s 8086248415d93480 P4DP6 0 +s 8086248480861958 vpr Matrix 170B4 0 +d 80862485 82801CA/CAM AC'97 Audio Controller 0 +s 8086248510135959 Crystal WMD Audio Codec 0 +s 8086248510140222 ThinkPad T23 (2647-4MG) or A30/A30p (2652/2653) 0 +s 8086248510140508 ThinkPad T30 0 +s 808624851014051c ThinkPad A/T/X Series 0 +s 80862485104d80e7 VAIO PCG-GR214EP/GR214MP/GR215MP/GR314MP/GR315MP 0 +s 80862485144dc006 vpr Matrix 170B4 0 +d 80862486 82801CA/CAM AC'97 Modem Controller 0 +s 8086248610140223 ThinkPad A/T/X Series 0 +s 8086248610140503 ThinkPad R31 2656BBG 0 +s 808624861014051a ThinkPad A/T/X Series 0 +s 80862486101f1025 Acer 620 Series 0 +s 80862486104d80e7 VAIO PCG-GR214EP/GR214MP/GR215MP/GR314MP/GR315MP 0 +s 8086248611790001 Toshiba Satellite 1110 Z15 internal Modem 0 +s 80862486134d4c21 Dell Inspiron 2100 internal modem 0 +s 80862486144d2115 vpr Matrix 170B4 internal modem 0 +s 8086248614f15421 MD56ORD V.92 MDC Modem 0 +d 80862487 82801CA/CAM USB (Hub #3) 0 +s 8086248710140220 ThinkPad A/T/X Series 0 +s 80862487104d80e7 VAIO PCG-GR214EP/GR214MP/GR215MP/GR314MP/GR315MP 0 +s 8086248715d93480 P4DP6 0 +s 8086248780861958 vpr Matrix 170B4 0 +d 8086248a 82801CAM IDE U100 0 +s 8086248a10140220 ThinkPad A/T/X Series 0 +s 8086248a104d80e7 VAIO PCG-GR214EP/GR214MP/GR215MP/GR314MP/GR315MP 0 +s 8086248a80861958 vpr Matrix 170B4 0 +s 8086248a80864541 Latitude C640 0 +d 8086248b 82801CA Ultra ATA Storage Controller 0 +s 8086248b15d93480 P4DP6 0 +d 8086248c 82801CAM ISA Bridge (LPC) 0 +d 808624c0 82801DB/DBL (ICH4/ICH4-L) LPC Interface Bridge 0 +s 808624c010140267 NetVista A30p 0 +s 808624c014625800 845PE Max (MS-6580) 0 +d 808624c1 82801DBL (ICH4-L) IDE Controller 0 +d 808624c2 82801DB/DBL/DBM (ICH4/ICH4-L/ICH4-M) USB UHCI Controller #1 0 +s 808624c210140267 NetVista A30p 0 +s 808624c21025005a TravelMate 290 0 +s 808624c210280126 Optiplex GX260 0 +s 808624c210280163 Latitude D505 0 +s 808624c2103c0890 NC6000 laptop 0 +s 808624c210718160 MIM2000 0 +s 808624c214625800 845PE Max (MS-6580) 0 +s 808624c215092990 Averatec 5110H laptop 0 +s 808624c24c531090 Cx9 / Vx9 mainboard 0 +d 808624c3 82801DB/DBL/DBM (ICH4/ICH4-L/ICH4-M) SMBus Controller 0 +s 808624c310140267 NetVista A30p 0 +s 808624c31025005a TravelMate 290 0 +s 808624c310280126 Optiplex GX260 0 +s 808624c3103c0890 NC6000 laptop 0 +s 808624c310718160 MIM2000 0 +s 808624c3145824c2 GA-8PE667 Ultra 0 +s 808624c314625800 845PE Max (MS-6580) 0 +s 808624c34c531090 Cx9 / Vx9 mainboard 0 +d 808624c4 82801DB/DBL/DBM (ICH4/ICH4-L/ICH4-M) USB UHCI Controller #2 0 +s 808624c410140267 NetVista A30p 0 +s 808624c41025005a TravelMate 290 0 +s 808624c410280126 Optiplex GX260 0 +s 808624c410280163 Latitude D505 0 +s 808624c4103c0890 NC6000 laptop 0 +s 808624c410718160 MIM2000 0 +s 808624c414625800 845PE Max (MS-6580) 0 +s 808624c415092990 Averatec 5110H 0 +s 808624c44c531090 Cx9 / Vx9 mainboard 0 +d 808624c5 82801DB/DBL/DBM (ICH4/ICH4-L/ICH4-M) AC'97 Audio Controller 0 +s 808624c50e1100b8 Analog Devices Inc. codec [SoundMAX] 0 +s 808624c510140267 NetVista A30p 0 +s 808624c51025005a TravelMate 290 0 +s 808624c510280163 Latitude D505 0 +s 808624c5103c0890 NC6000 laptop 0 +s 808624c510718160 MIM2000 0 +s 808624c51458a002 GA-8PE667 Ultra 0 +s 808624c514625800 845PE Max (MS-6580) 0 +d 808624c6 82801DB/DBL/DBM (ICH4/ICH4-L/ICH4-M) AC'97 Modem Controller 0 +s 808624c61025005a TravelMate 290 0 +s 808624c6103c0890 NC6000 laptop 0 +s 808624c610718160 MIM2000 0 +d 808624c7 82801DB/DBL/DBM (ICH4/ICH4-L/ICH4-M) USB UHCI Controller #3 0 +s 808624c710140267 NetVista A30p 0 +s 808624c71025005a TravelMate 290 0 +s 808624c710280126 Optiplex GX260 0 +s 808624c710280163 Latitude D505 0 +s 808624c7103c0890 NC6000 laptop 0 +s 808624c710718160 MIM2000 0 +s 808624c714625800 845PE Max (MS-6580) 0 +s 808624c715092990 Averatec 5110H 0 +s 808624c74c531090 Cx9 / Vx9 mainboard 0 +d 808624ca 82801DBM (ICH4-M) IDE Controller 0 +s 808624ca1025005a TravelMate 290 0 +s 808624ca10280163 Latitude D505 0 +s 808624ca103c0890 NC6000 laptop 0 +s 808624ca10718160 MIM2000 0 +d 808624cb 82801DB (ICH4) IDE Controller 0 +s 808624cb10140267 NetVista A30p 0 +s 808624cb10280126 Optiplex GX260 0 +s 808624cb145824c2 GA-8PE667 Ultra 0 +s 808624cb14625800 845PE Max (MS-6580) 0 +s 808624cb4c531090 Cx9 / Vx9 mainboard 0 +d 808624cc 82801DBM (ICH4-M) LPC Interface Bridge 0 +d 808624cd 82801DB/DBM (ICH4/ICH4-M) USB2 EHCI Controller 0 +s 808624cd10140267 NetVista A30p 0 +s 808624cd1025005a TravelMate 290 0 +s 808624cd10280126 Optiplex GX260 0 +s 808624cd10280163 Latitude D505 0 +s 808624cd103c0890 NC6000 laptop 0 +s 808624cd10718160 MIM2000 0 +s 808624cd14623981 845PE Max (MS-6580) 0 +s 808624cd15091968 Averatec 5110H 0 +s 808624cd4c531090 Cx9 / Vx9 mainboard 0 +d 808624d0 82801EB/ER (ICH5/ICH5R) LPC Interface Bridge 0 +d 808624d1 82801EB (ICH5) SATA Controller 0 +s 808624d1103c12bc d530 CMT (DG746A) 0 +s 808624d1145824d1 GA-8IPE1000 Pro2 motherboard (865PE) 0 +s 808624d114627280 865PE Neo2 (MS-6728) 0 +s 808624d180863427 S875WP1-E mainboard 0 +s 808624d18086524c D865PERL mainboard 0 +d 808624d2 82801EB/ER (ICH5/ICH5R) USB UHCI Controller #1 0 +s 808624d2103c12bc d530 CMT (DG746A) 0 +s 808624d2104380a6 P4P800 Mainboard 0 +s 808624d2145824d2 GA-8KNXP motherboard (875P) 0 +s 808624d214627280 865PE Neo2 (MS-6728) 0 +s 808624d280863427 S875WP1-E mainboard 0 +s 808624d28086524c D865PERL mainboard 0 +d 808624d3 82801EB/ER (ICH5/ICH5R) SMBus Controller 0 +s 808624d3104380a6 P4P800 Mainboard 0 +s 808624d3145824d2 GA-8IPE1000 Pro2 motherboard (865PE) 0 +s 808624d314627280 865PE Neo2 (MS-6728) 0 +s 808624d380863427 S875WP1-E mainboard 0 +s 808624d38086524c D865PERL mainboard 0 +d 808624d4 82801EB/ER (ICH5/ICH5R) USB UHCI Controller #2 0 +s 808624d4103c12bc d530 CMT (DG746A) 0 +s 808624d4104380a6 P4P800 Mainboard 0 +s 808624d4145824d2 GA-8IPE1000 Pro2 motherboard (865PE) 0 +s 808624d414627280 865PE Neo2 (MS-6728) 0 +s 808624d480863427 S875WP1-E mainboard 0 +s 808624d48086524c D865PERL mainboard 0 +d 808624d5 82801EB/ER (ICH5/ICH5R) AC'97 Audio Controller 0 +s 808624d5103c12bc Analog Devices codec [SoundMAX Integrated Digital Audio] 0 +s 808624d5104380f3 P4P800 Mainboard 0 +s 808624d51458a002 GA-8KNXP motherboard (875P) 0 +s 808624d514627280 865PE Neo2 (MS-6728) 0 +s 808624d58086a000 D865PERL mainboard 0 +d 808624d6 82801EB/ER (ICH5/ICH5R) AC'97 Modem Controller 0 +d 808624d7 82801EB/ER (ICH5/ICH5R) USB UHCI #3 0 +s 808624d7103c12bc d530 CMT (DG746A) 0 +s 808624d7104380a6 P4P800 Mainboard 0 +s 808624d7145824d2 GA-8IPE1000 Pro2 motherboard (865PE) 0 +s 808624d714627280 865PE Neo2 (MS-6728) 0 +s 808624d780863427 S875WP1-E mainboard 0 +s 808624d78086524c D865PERL mainboard 0 +d 808624db 82801EB/ER (ICH5/ICH5R) IDE Controller 0 +s 808624db103c12bc d530 CMT (DG746A) 0 +s 808624db104380a6 P4P800 Mainboard 0 +s 808624db145824d2 GA-8IPE1000 Pro2 motherboard (865PE) 0 +s 808624db14627280 865PE Neo2 (MS-6728) 0 +s 808624db14627580 MSI 875P 0 +s 808624db80863427 S875WP1-E mainboard 0 +s 808624db8086524c D865PERL mainboard 0 +d 808624dc 82801EB (ICH5) LPC Interface Bridge 0 +d 808624dd 82801EB/ER (ICH5/ICH5R) USB2 EHCI Controller 0 +s 808624dd103c12bc d530 CMT (DG746A) 0 +s 808624dd104380a6 P4P800 Mainboard 0 +s 808624dd14585006 GA-8IPE1000 Pro2 motherboard (865PE) 0 +s 808624dd14627280 865PE Neo2 (MS-6728) 0 +s 808624dd80863427 S875WP1-E mainboard 0 +s 808624dd8086524c D865PERL mainboard 0 +d 808624de 82801EB/ER (ICH5/ICH5R) USB UHCI Controller #4 0 +s 808624de104380a6 P4P800 Mainboard 0 +s 808624de145824d2 GA-8IPE1000 Pro2 motherboard (865PE) 0 +s 808624de14627280 865PE Neo2 (MS-6728) 0 +s 808624de80863427 S875WP1-E mainboard 0 +s 808624de8086524c D865PERL mainboard 0 +d 808624df 82801ER (ICH5R) SATA Controller 0 +d 80862500 82820 820 (Camino) Chipset Host Bridge (MCH) 0 +s 8086250010280095 Precision Workstation 220 Chipset 0 +s 808625001043801c P3C-2000 system chipset 0 +d 80862501 82820 820 (Camino) Chipset Host Bridge (MCH) 0 +s 808625011043801c P3C-2000 system chipset 0 +d 8086250b 82820 820 (Camino) Chipset Host Bridge 0 +d 8086250f 82820 820 (Camino) Chipset AGP Bridge 0 +d 80862520 82805AA MTH Memory Translator Hub 0 +d 80862521 82804AA MRH-S Memory Repeater Hub for SDRAM 0 +d 80862530 82850 850 (Tehama) Chipset Host Bridge (MCH) 0 +s 80862530147b0507 TH7II-RAID 0 +d 80862531 82860 860 (Wombat) Chipset Host Bridge (MCH) 0 +d 80862532 82850 850 (Tehama) Chipset AGP Bridge 0 +d 80862533 82860 860 (Wombat) Chipset AGP Bridge 0 +d 80862534 82860 860 (Wombat) Chipset PCI Bridge 0 +d 80862540 E7500 Memory Controller Hub 0 +s 8086254015d93480 P4DP6 0 +d 80862541 E7500/E7501 Host RASUM Controller 0 +s 8086254115d93480 P4DP6 0 +s 808625414c531090 Cx9 / Vx9 mainboard 0 +s 8086254180863424 SE7501HG2 Mainboard 0 +d 80862543 E7500/E7501 Hub Interface B PCI-to-PCI Bridge 0 +d 80862544 E7500/E7501 Hub Interface B RASUM Controller 0 +s 808625444c531090 Cx9 / Vx9 mainboard 0 +d 80862545 E7500/E7501 Hub Interface C PCI-to-PCI Bridge 0 +d 80862546 E7500/E7501 Hub Interface C RASUM Controller 0 +d 80862547 E7500/E7501 Hub Interface D PCI-to-PCI Bridge 0 +d 80862548 E7500/E7501 Hub Interface D RASUM Controller 0 +d 8086254c E7501 Memory Controller Hub 0 +s 8086254c4c531090 Cx9 / Vx9 mainboard 0 +s 8086254c80863424 SE7501HG2 Mainboard 0 +d 80862550 E7505 Memory Controller Hub 0 +d 80862551 E7505/E7205 Series RAS Controller 0 +d 80862552 E7505/E7205 PCI-to-AGP Bridge 0 +d 80862553 E7505 Hub Interface B PCI-to-PCI Bridge 0 +d 80862554 E7505 Hub Interface B PCI-to-PCI Bridge RAS Controller 0 +d 8086255d E7205 Memory Controller Hub 0 +d 80862560 82845G/GL[Brookdale-G]/GE/PE DRAM Controller/Host-Hub Interface 0 +s 8086256010280126 Optiplex GX260 0 +s 8086256014582560 GA-8PE667 Ultra 0 +s 8086256014625800 845PE Max (MS-6580) 0 +d 80862561 82845G/GL[Brookdale-G]/GE/PE Host-to-AGP Bridge 0 +d 80862562 82845G/GL[Brookdale-G]/GE Chipset Integrated Graphics Device 0 +s 8086256210140267 NetVista A30p 0 +d 80862570 82865G/PE/P DRAM Controller/Host-Hub Interface 0 +s 80862570104380f2 P4P800 Mainboard 0 +s 8086257014582570 GA-8IPE1000 Pro2 motherboard (865PE) 0 +d 80862571 82865G/PE/P PCI to AGP Controller 0 +d 80862572 82865G Integrated Graphics Device 0 +d 80862573 82865G/PE/P PCI to CSA Bridge 0 +d 80862576 82865G/PE/P Processor to I/O Memory Interface 0 +d 80862578 82875P/E7210 Memory Controller Hub 0 +s 8086257814582578 GA-8KNXP motherboard (875P) 0 +s 8086257814627580 MS-6758 (875P Neo) 0 +s 8086257815d94580 Super Micro Computer Inc. P4SCE 0 Motherboard P4SCE +d 80862579 82875P Processor to AGP Controller 0 +d 8086257b 82875P/E7210 Processor to PCI to CSA Bridge 0 +d 8086257e 82875P/E7210 Processor to I/O Memory Interface 0 +d 80862580 915G/P/GV Processor to I/O Controller 0 +d 80862581 915G/P/GV PCI Express Root Port 0 +d 80862582 82915G Express Chipset Family Graphics Controller 0 +s 8086258210281079 Optiplex GX280 0 +d 80862584 925X/XE Memory Controller Hub 0 +d 80862585 925X/XE PCI Express Root Port 0 +d 80862588 E7220/E7221 Memory Controller Hub 0 +d 80862589 E7220/E7221 PCI Express Root Port 0 +d 8086258a E7221 Integrated Graphics Controller 0 +d 80862590 Mobile Memory Controller Hub 0 +d 80862591 Mobile Memory Controller Hub PCI Express Port 0 +d 80862592 Mobile Graphics Controller 0 +d 808625a1 6300ESB LPC Interface Controller 0 +d 808625a2 6300ESB PATA Storage Controller 0 +s 808625a24c5310b0 CL9 mainboard 0 +d 808625a3 6300ESB SATA Storage Controller 0 +s 808625a34c5310b0 CL9 mainboard 0 +d 808625a4 6300ESB SMBus Controller 0 +s 808625a44c5310b0 CL9 mainboard 0 +d 808625a6 6300ESB AC'97 Audio Controller 0 +s 808625a64c5310b0 CL9 mainboard 0 +d 808625a7 6300ESB AC'97 Modem Controller 0 +d 808625a9 6300ESB USB Universal Host Controller 0 +s 808625a94c5310b0 CL9 mainboard 0 +d 808625aa 6300ESB USB Universal Host Controller 0 +s 808625aa4c5310b0 CL9 mainboard 0 +d 808625ab 6300ESB Watchdog Timer 0 +s 808625ab4c5310b0 CL9 mainboard 0 +d 808625ac 6300ESB I/O Advanced Programmable Interrupt Controller 0 +s 808625ac4c5310b0 CL9 mainboard 0 +d 808625ad 6300ESB USB2 Enhanced Host Controller 0 +d 808625ae 6300ESB 64-bit PCI-X Bridge 0 +d 808625b0 6300ESB SATA RAID Controller 0 +d 80862600 Server Hub Interface 0 +d 80862601 Server Hub PCI Express x4 Port D 0 +d 80862602 Server Hub PCI Express x4 Port C0 0 +d 80862603 Server Hub PCI Express x4 Port C1 0 +d 80862604 Server Hub PCI Express x4 Port B0 0 +d 80862605 Server Hub PCI Express x4 Port B1 0 +d 80862606 Server Hub PCI Express x4 Port A0 0 +d 80862607 Server Hub PCI Express x4 Port A1 0 +d 80862608 Server Hub PCI Express x8 Port C 0 +d 80862609 Server Hub PCI Express x8 Port B 0 +d 8086260a Server Hub PCI Express x8 Port A 0 +d 8086260c Server Hub IMI Registers 0 +d 80862610 Server Hub System Bus, Boot, and Interrupt Registers 0 +d 80862611 Server Hub Address Mapping Registers 0 +d 80862612 Server Hub RAS Registers 0 +d 80862613 Server Hub Reserved Registers 0 +d 80862614 Server Hub Reserved Registers 0 +d 80862615 Server Hub Miscellaneous Registers 0 +d 80862617 Server Hub Reserved Registers 0 +d 80862618 Server Hub Reserved Registers 0 +d 80862619 Server Hub Reserved Registers 0 +d 8086261a Server Hub Reserved Registers 0 +d 8086261b Server Hub Reserved Registers 0 +d 8086261c Server Hub Reserved Registers 0 +d 8086261d Server Hub Reserved Registers 0 +d 8086261e Server Hub Reserved Registers 0 +d 80862620 External Memory Bridge 0 +d 80862621 External Memory Bridge Control Registers 0 +d 80862622 External Memory Bridge Memory Interleaving Registers 0 +d 80862623 External Memory Bridge DDR Initialization and Calibration 0 +d 80862624 External Memory Bridge Reserved Registers 0 +d 80862625 External Memory Bridge Reserved Registers 0 +d 80862626 External Memory Bridge Reserved Registers 0 +d 80862627 External Memory Bridge Reserved Registers 0 +d 80862640 82801FB/FR (ICH6/ICH6R) LPC Interface Bridge 0 +d 80862641 82801FBM (ICH6M) LPC Interface Bridge 0 +d 80862642 82801FW/FRW (ICH6W/ICH6RW) LPC Interface Bridge 0 +d 80862651 82801FB/FW (ICH6/ICH6W) SATA Controller 0 +s 8086265110280179 Optiplex GX280 0 +d 80862652 82801FR/FRW (ICH6R/ICH6RW) SATA Controller 0 +d 80862653 82801FBM (ICH6M) SATA Controller 0 +d 80862658 82801FB/FBM/FR/FW/FRW (ICH6 Family) USB UHCI #1 0 +s 8086265810280179 Optiplex GX280 0 +d 80862659 82801FB/FBM/FR/FW/FRW (ICH6 Family) USB UHCI #2 0 +s 8086265910280179 Optiplex GX280 0 +d 8086265a 82801FB/FBM/FR/FW/FRW (ICH6 Family) USB UHCI #3 0 +s 8086265a10280179 Optiplex GX280 0 +d 8086265b 82801FB/FBM/FR/FW/FRW (ICH6 Family) USB UHCI #4 0 +s 8086265b10280179 Optiplex GX280 0 +d 8086265c 82801FB/FBM/FR/FW/FRW (ICH6 Family) USB2 EHCI Controller 0 +s 8086265c10280179 Optiplex GX280 0 +d 80862660 82801FB/FBM/FR/FW/FRW (ICH6 Family) PCI Express Port 1 0 +d 80862662 82801FB/FBM/FR/FW/FRW (ICH6 Family) PCI Express Port 2 0 +d 80862664 82801FB/FBM/FR/FW/FRW (ICH6 Family) PCI Express Port 3 0 +d 80862666 82801FB/FBM/FR/FW/FRW (ICH6 Family) PCI Express Port 4 0 +d 80862668 82801FB/FBM/FR/FW/FRW (ICH6 Family) High Definition Audio Controller 0 +d 8086266a 82801FB/FBM/FR/FW/FRW (ICH6 Family) SMBus Controller 0 +s 8086266a10280179 Optiplex GX280 0 +d 8086266c 82801FB/FBM/FR/FW/FRW (ICH6 Family) LAN Controller 0 +d 8086266d 82801FB/FBM/FR/FW/FRW (ICH6 Family) AC'97 Modem Controller 0 +d 8086266e 82801FB/FBM/FR/FW/FRW (ICH6 Family) AC'97 Audio Controller 0 +s 8086266e10280179 Optiplex GX280 0 +d 8086266f 82801FB/FBM/FR/FW/FRW (ICH6 Family) IDE Controller 0 +d 80862782 82915G Express Chipset Family Graphics Controller 0 +d 80862792 Mobile Graphics Controller 0 +d 80863092 Integrated RAID 0 +d 80863200 GD31244 PCI-X SATA HBA 0 +d 80863340 82855PM Processor to I/O Controller 0 +s 808633401025005a TravelMate 290 0 +s 80863340103c0890 NC6000 laptop 0 +d 80863341 82855PM Processor to AGP Controller 0 +d 80863575 82830 830 Chipset Host Bridge 0 +s 808635751014021d ThinkPad A/T/X Series 0 +s 80863575104d80e7 VAIO PCG-GR214EP/GR214MP/GR215MP/GR314MP/GR315MP 0 +d 80863576 82830 830 Chipset AGP Bridge 0 +d 80863577 82830 CGC [Chipset Graphics Controller] 0 +s 8086357710140513 ThinkPad A/T/X Series 0 +d 80863578 82830 830 Chipset Host Bridge 0 +d 80863580 82852/82855 GM/GME/PM/GMV Processor to I/O Controller 0 +s 8086358010280163 Latitude D505 0 +s 808635804c5310b0 CL9 mainboard 0 +d 80863581 82852/82855 GM/GME/PM/GMV Processor to AGP Controller 0 +d 80863582 82852/855GM Integrated Graphics Device 0 +s 8086358210280163 Latitude D505 0 +s 808635824c5310b0 CL9 mainboard 0 +d 80863584 82852/82855 GM/GME/PM/GMV Processor to I/O Controller 0 +s 8086358410280163 Latitude D505 0 +s 808635844c5310b0 CL9 mainboard 0 +d 80863585 82852/82855 GM/GME/PM/GMV Processor to I/O Controller 0 +s 8086358510280163 Latitude D505 0 +s 808635854c5310b0 CL9 mainboard 0 +d 80863590 E7520 Memory Controller Hub 0 +d 80863591 E7525/E7520 Error Reporting Registers 0 +d 80863592 E7320 Memory Controller Hub 0 +d 80863593 E7320 Error Reporting Registers 0 +d 80863594 E7520 DMA Controller 0 +d 80863595 E7525/E7520/E7320 PCI Express Port A 0 +d 80863596 E7525/E7520/E7320 PCI Express Port A1 0 +d 80863597 E7525/E7520 PCI Express Port B 0 +d 80863598 E7520 PCI Express Port B1 0 +d 80863599 E7520 PCI Express Port C 0 +d 8086359a E7520 PCI Express Port C1 0 +d 8086359b E7525/E7520/E7320 Extended Configuration Registers 0 +d 8086359e E7525 Memory Controller Hub 0 +d 80864220 PRO/Wireless 2200BG 0 +d 80864223 PRO/Wireless 2915ABG MiniPCI Adapter 0 +d 80865200 EtherExpress PRO/100 Intelligent Server 0 +d 80865201 EtherExpress PRO/100 Intelligent Server 0 +s 8086520180860001 EtherExpress PRO/100 Server Ethernet Adapter 0 +d 8086530d 80310 IOP [IO Processor] 0 +d 80867000 82371SB PIIX3 ISA [Natoma/Triton II] 0 +d 80867010 82371SB PIIX3 IDE [Natoma/Triton II] 0 +d 80867020 82371SB PIIX3 USB [Natoma/Triton II] 0 +d 80867030 430VX - 82437VX TVX [Triton VX] 0 +d 80867050 Intel Intercast Video Capture Card 0 +d 80867100 430TX - 82439TX MTXC 0 +d 80867110 82371AB/EB/MB PIIX4 ISA 0 +s 8086711015ad1976 virtualHW v3 0 +d 80867111 82371AB/EB/MB PIIX4 IDE 0 +s 8086711115ad1976 virtualHW v3 0 +d 80867112 82371AB/EB/MB PIIX4 USB 0 +s 8086711215ad1976 virtualHW v3 0 +d 80867113 82371AB/EB/MB PIIX4 ACPI 0 +s 8086711315ad1976 virtualHW v3 0 +d 80867120 82810 GMCH [Graphics Memory Controller Hub] 0 +s 808671204c531040 CL7 mainboard 0 +s 808671204c531060 PC7 mainboard 0 +d 80867121 82810 CGC [Chipset Graphics Controller] 0 +s 808671214c531040 CL7 mainboard 0 +s 808671214c531060 PC7 mainboard 0 +s 8086712180864341 Cayman (CA810) Mainboard 0 +d 80867122 82810 DC-100 GMCH [Graphics Memory Controller Hub] 0 +d 80867123 82810 DC-100 CGC [Chipset Graphics Controller] 0 +d 80867124 82810E DC-133 GMCH [Graphics Memory Controller Hub] 0 +d 80867125 82810E DC-133 CGC [Chipset Graphics Controller] 0 +d 80867126 82810 DC-133 System and Graphics Controller 0 +d 80867128 82810-M DC-100 System and Graphics Controller 0 +d 8086712a 82810-M DC-133 System and Graphics Controller 0 +d 80867180 440LX/EX - 82443LX/EX Host bridge 0 +d 80867181 440LX/EX - 82443LX/EX AGP bridge 0 +d 80867190 440BX/ZX/DX - 82443BX/ZX/DX Host bridge 0 +s 808671900e110500 Armada 1750 Laptop System Chipset 0 +s 808671900e11b110 Armada M700/E500 0 +s 8086719011790001 Toshiba Tecra 8100 Laptop System Chipset 0 +s 8086719015ad1976 virtualHW v3 0 +s 808671904c531050 CT7 mainboard 0 +s 808671904c531051 CE7 mainboard 0 +d 80867191 440BX/ZX/DX - 82443BX/ZX/DX AGP bridge 0 +d 80867192 440BX/ZX/DX - 82443BX/ZX/DX Host bridge (AGP disabled) 0 +s 808671920e110460 Armada 1700 Laptop System Chipset 0 +s 808671924c531000 CC7/CR7/CP7/VC7/VP7/VR7 mainboard 0 +d 80867194 82440MX Host Bridge 0 +s 8086719410330000 Versa Note Vxi 0 +s 808671944c5310a0 CA3/CR3 mainboard 0 +d 80867195 82440MX AC'97 Audio Controller 0 +s 80867195103380cc Versa Note VXi 0 +s 8086719510cf1099 QSound_SigmaTel Stac97 PCI Audio 0 +s 8086719511d40040 SoundMAX Integrated Digital Audio 0 +s 8086719511d40048 SoundMAX Integrated Digital Audio 0 +d 80867196 82440MX AC'97 Modem Controller 0 +d 80867198 82440MX ISA Bridge 0 +d 80867199 82440MX EIDE Controller 0 +d 8086719a 82440MX USB Universal Host Controller 0 +d 8086719b 82440MX Power Management Controller 0 +d 808671a0 440GX - 82443GX Host bridge 0 +s 808671a04c531050 CT7 mainboard 0 +s 808671a04c531051 CE7 mainboard 0 +d 808671a1 440GX - 82443GX AGP bridge 0 +d 808671a2 440GX - 82443GX Host bridge (AGP disabled) 0 +s 808671a24c531000 CC7/CR7/CP7/VC7/VP7/VR7 mainboard 0 +d 80867600 82372FB PIIX5 ISA 0 +d 80867601 82372FB PIIX5 IDE 0 +d 80867602 82372FB PIIX5 USB 0 +d 80867603 82372FB PIIX5 SMBus 0 +d 80867800 82740 (i740) AGP Graphics Accelerator 0 +s 80867800003d0008 Starfighter AGP 0 +s 80867800003d000b Starfighter AGP 0 +s 8086780010920100 Stealth II G460 0 +s 8086780010b4201a Lightspeed 740 0 +s 8086780010b4202f Lightspeed 740 0 +s 8086780080860000 Terminator 2x/i 0 +s 8086780080860100 Intel740 Graphics Accelerator 0 +d 808684c4 450KX/GX [Orion] - 82454KX/GX PCI bridge 0 +d 808684c5 450KX/GX [Orion] - 82453KX/GX Memory controller 0 +d 808684ca 450NX - 82451NX Memory & I/O Controller 0 +d 808684cb 450NX - 82454NX/84460GX PCI Expander Bridge 0 +d 808684e0 460GX - 84460GX System Address Controller (SAC) 0 +d 808684e1 460GX - 84460GX System Data Controller (SDC) 0 +d 808684e2 460GX - 84460GX AGP Bridge (GXB function 2) 0 +d 808684e3 460GX - 84460GX Memory Address Controller (MAC) 0 +d 808684e4 460GX - 84460GX Memory Data Controller (MDC) 0 +d 808684e6 460GX - 82466GX Wide and fast PCI eXpander Bridge (WXB) 0 +d 808684ea 460GX - 84460GX AGP Bridge (GXB function 1) 0 +d 80868500 IXP4XX - Intel Network Processor family. IXP420, IXP421, IXP422, IXP425 and IXC1100 0 +d 80869000 IXP2000 Family Network Processor 0 +d 80869001 IXP2400 Network Processor 0 +d 80869004 IXP2800 Network Processor 0 +d 80869621 Integrated RAID 0 +d 80869622 Integrated RAID 0 +d 80869641 Integrated RAID 0 +d 808696a1 Integrated RAID 0 +d 8086a01f PRO/10GbE LR Server Adapter 0 retail verson +d 8086a11f PRO/10GbE LR Server Adapter 0 OEM version +d 8086b152 21152 PCI-to-PCI Bridge 0 +d 8086b154 21154 PCI-to-PCI Bridge 0 observed, and documented in Intel revision note; new mask of 1011:0026 +d 8086b555 21555 Non transparent PCI-to-PCI Bridge 0 +s 8086b55512d9000a PCI VoIP Gateway 0 +s 8086b5554c531050 CT7 mainboard 0 +s 8086b5554c531051 CE7 mainboard 0 +s 8086b555e4bf1000 CC8-1-BLUES 0 +d 8086ffff 450NX/GX [Orion] - 82453KX/GX Memory controller [BUG] 0 +v 8401 TRENDware International Inc. 0 +v 8800 Trigem Computer Inc. 0 +d 88002008 Video assistent component 0 +v 8866 T-Square Design Inc. 0 +v 8888 Silicon Magic 0 +v 8c4a Winbond 0 8c4a is not Winbond but there is a board misprogrammed +d 8c4a1980 W89C940 misprogrammed [ne2k] 0 +v 8e0e Computone Corporation 0 +v 8e2e KTI 0 +d 8e2e3000 ET32P2 0 +v 9004 Adaptec 0 +d 90040078 AHA-2940U_CN 0 +d 90041078 AIC-7810 0 +d 90041160 AIC-1160 [Family Fibre Channel Adapter] 0 +d 90042178 AIC-7821 0 +d 90043860 AHA-2930CU 0 +d 90043b78 AHA-4844W/4844UW 0 +d 90045075 AIC-755x 0 +d 90045078 AHA-7850 0 +s 9004507890047850 AHA-2904/Integrated AIC-7850 0 +d 90045175 AIC-755x 0 +d 90045178 AIC-7851 0 +d 90045275 AIC-755x 0 +d 90045278 AIC-7852 0 +d 90045375 AIC-755x 0 +d 90045378 AIC-7850 0 +d 90045475 AIC-755x 0 +d 90045478 AIC-7850 0 +d 90045575 AVA-2930 0 +d 90045578 AIC-7855 0 +d 90045647 ANA-7711 TCP Offload Engine 0 +s 9004564790047710 ANA-7711F TCP Offload Engine - Optical 0 +s 9004564790047711 ANA-7711LP TCP Offload Engine - Copper 0 +d 90045675 AIC-755x 0 +d 90045678 AIC-7856 0 +d 90045775 AIC-755x 0 +d 90045778 AIC-7850 0 +d 90045800 AIC-5800 0 +d 90045900 ANA-5910/5930/5940 ATM155 & 25 LAN Adapter 0 +d 90045905 ANA-5910A/5930A/5940A ATM Adapter 0 +d 90046038 AIC-3860 0 +d 90046075 AIC-1480 / APA-1480 0 +s 9004607590047560 AIC-1480 / APA-1480 Cardbus 0 +d 90046078 AIC-7860 0 +d 90046178 AIC-7861 0 +s 9004617890047861 AHA-2940AU Single 0 +d 90046278 AIC-7860 0 +d 90046378 AIC-7860 0 +d 90046478 AIC-786x 0 +d 90046578 AIC-786x 0 +d 90046678 AIC-786x 0 +d 90046778 AIC-786x 0 +d 90046915 ANA620xx/ANA69011A 0 +s 9004691590040008 ANA69011A/TX 10/100 0 +s 9004691590040009 ANA69011A/TX 10/100 0 +s 9004691590040010 ANA62022 2-port 10/100 0 +s 9004691590040018 ANA62044 4-port 10/100 0 +s 9004691590040019 ANA62044 4-port 10/100 0 +s 9004691590040020 ANA62022 2-port 10/100 0 +s 9004691590040028 ANA69011A/TX 10/100 0 +s 9004691590048008 ANA69011A/TX 64 bit 10/100 0 +s 9004691590048009 ANA69011A/TX 64 bit 10/100 0 +s 9004691590048010 ANA62022 2-port 64 bit 10/100 0 +s 9004691590048018 ANA62044 4-port 64 bit 10/100 0 +s 9004691590048019 ANA62044 4-port 64 bit 10/100 0 +s 9004691590048020 ANA62022 2-port 64 bit 10/100 0 +s 9004691590048028 ANA69011A/TX 64 bit 10/100 0 +d 90047078 AHA-294x / AIC-7870 0 +d 90047178 AHA-2940/2940W / AIC-7871 0 +d 90047278 AHA-3940/3940W / AIC-7872 0 +d 90047378 AHA-3985 / AIC-7873 0 +d 90047478 AHA-2944/2944W / AIC-7874 0 +d 90047578 AHA-3944/3944W / AIC-7875 0 +d 90047678 AHA-4944W/UW / AIC-7876 0 +d 90047710 ANA-7711F Network Accelerator Card (NAC) - Optical 0 +d 90047711 ANA-7711C Network Accelerator Card (NAC) - Copper 0 +d 90047778 AIC-787x 0 +d 90047810 AIC-7810 0 +d 90047815 AIC-7815 RAID+Memory Controller IC 0 +s 9004781590047815 ARO-1130U2 RAID Controller 0 +s 9004781590047840 AIC-7815 RAID+Memory Controller IC 0 +d 90047850 AIC-7850 0 +d 90047855 AHA-2930 0 +d 90047860 AIC-7860 0 +d 90047870 AIC-7870 0 +d 90047871 AHA-2940 0 +d 90047872 AHA-3940 0 +d 90047873 AHA-3980 0 +d 90047874 AHA-2944 0 +d 90047880 AIC-7880P 0 +d 90047890 AIC-7890 0 +d 90047891 AIC-789x 0 +d 90047892 AIC-789x 0 +d 90047893 AIC-789x 0 +d 90047894 AIC-789x 0 +d 90047895 AHA-2940U/UW / AHA-39xx / AIC-7895 0 +s 9004789590047890 AHA-2940U/2940UW Dual AHA-394xAU/AUW/AUWD AIC-7895B 0 +s 9004789590047891 AHA-2940U/2940UW Dual 0 +s 9004789590047892 AHA-3940AU/AUW/AUWD/UWD 0 +s 9004789590047894 AHA-3944AUWD 0 +s 9004789590047895 AHA-2940U/2940UW Dual AHA-394xAU/AUW/AUWD AIC-7895B 0 +s 9004789590047896 AHA-2940U/2940UW Dual AHA-394xAU/AUW/AUWD AIC-7895B 0 +s 9004789590047897 AHA-2940U/2940UW Dual AHA-394xAU/AUW/AUWD AIC-7895B 0 +d 90047896 AIC-789x 0 +d 90047897 AIC-789x 0 +d 90048078 AIC-7880U 0 +s 9004807890047880 AIC-7880P Ultra/Ultra Wide SCSI Chipset 0 +d 90048178 AHA-2940U/UW/D / AIC-7881U 0 +s 9004817890047881 AHA-2940UW SCSI Host Adapter 0 +d 90048278 AHA-3940U/UW/UWD / AIC-7882U 0 +d 90048378 AHA-3940U/UW / AIC-7883U 0 +d 90048478 AHA-2944UW / AIC-7884U 0 +d 90048578 AHA-3944U/UWD / AIC-7885 0 +d 90048678 AHA-4944UW / AIC-7886 0 +d 90048778 AHA-2940UW Pro / AIC-788x 0 +s 9004877890047887 2940UW Pro Ultra-Wide SCSI Controller 0 +d 90048878 AHA-2930UW / AIC-7888 0 +s 9004887890047888 AHA-2930UW SCSI Controller 0 +d 90048b78 ABA-1030 0 +d 9004ec78 AHA-4944W/UW 0 +v 9005 Adaptec 0 +d 90050010 AHA-2940U2/U2W 0 +s 9005001090052180 AHA-2940U2 SCSI Controller 0 +s 9005001090058100 AHA-2940U2B SCSI Controller 0 +s 900500109005a100 AHA-2940U2B SCSI Controller 0 +s 900500109005a180 AHA-2940U2W SCSI Controller 0 +s 900500109005e100 AHA-2950U2B SCSI Controller 0 +d 90050011 AHA-2930U2 0 +d 90050013 78902 0 +s 9005001390050003 AAA-131U2 Array1000 1 Channel RAID Controller 0 +s 900500139005000f AIC7890_ARO 0 +d 9005001f AHA-2940U2/U2W / 7890/7891 0 +s 9005001f9005000f 2940U2W SCSI Controller 0 +s 9005001f9005a180 2940U2W SCSI Controller 0 +d 90050020 AIC-7890 0 +d 9005002f AIC-7890 0 +d 90050030 AIC-7890 0 +d 9005003f AIC-7890 0 +d 90050050 AHA-3940U2x/395U2x 0 +s 900500509005f500 AHA-3950U2B 0 +s 900500509005ffff AHA-3950U2B 0 +d 90050051 AHA-3950U2D 0 +s 900500519005b500 AHA-3950U2D 0 +d 90050053 AIC-7896 SCSI Controller 0 +s 900500539005ffff AIC-7896 SCSI Controller mainboard implementation 0 +d 9005005f AIC-7896U2/7897U2 0 +d 90050080 AIC-7892A U160/m 0 +s 900500800e11e2a0 Compaq 64-Bit/66MHz Wide Ultra3 SCSI Adapter 0 +s 9005008090056220 AHA-29160C 0 +s 90050080900562a0 29160N Ultra160 SCSI Controller 0 +s 900500809005e220 29160LP Low Profile Ultra160 SCSI Controller 0 +s 900500809005e2a0 29160 Ultra160 SCSI Controller 0 +d 90050081 AIC-7892B U160/m 0 +s 90050081900562a1 19160 Ultra160 SCSI Controller 0 +d 90050083 AIC-7892D U160/m 0 +d 9005008f AIC-7892P U160/m 0 +s 9005008f11790001 Magnia Z310 0 +s 9005008f15d99005 Onboard SCSI Host Adapter 0 +d 900500c0 AHA-3960D / AIC-7899A U160/m 0 +s 900500c00e11f620 Compaq 64-Bit/66MHz Dual Channel Wide Ultra3 SCSI Adapter 0 +s 900500c09005f620 AHA-3960D U160/m 0 +d 900500c1 AIC-7899B U160/m 0 +d 900500c3 AIC-7899D U160/m 0 +d 900500c5 RAID subsystem HBA 0 +s 900500c5102800c5 PowerEdge 2400,2500,2550,4400 0 +d 900500cf AIC-7899P U160/m 0 +s 900500cf102800ce PowerEdge 1400 0 +s 900500cf102800d1 PowerEdge 2550 0 +s 900500cf102800d9 PowerEdge 2500 0 +s 900500cf10f12462 Thunder K7 S2462 0 +s 900500cf15d99005 Onboard SCSI Host Adapter 0 +s 900500cf80863411 SDS2 Mainboard 0 +d 90050250 ServeRAID Controller 0 +s 9005025010140279 ServeRAID-xx 0 +s 900502501014028c ServeRAID-xx 0 +d 90050279 ServeRAID 6M 0 from kernel sources +d 90050283 AAC-RAID 0 +s 9005028390050283 Catapult 0 +d 90050284 AAC-RAID 0 +s 9005028490050284 Tomcat 0 +d 90050285 AAC-RAID 0 +s 900502850e110295 SATA 6Ch (Bearcat) 0 +s 9005028510280287 PowerEdge Expandable RAID Controller 320/DC 0 +s 9005028510280291 CERC SATA RAID 2 PCI SATA 6ch (DellCorsair) 0 +s 9005028517aa0286 Legend S220 (Legend Crusader) 0 +s 9005028517aa0287 Legend S230 (Legend Vulcan) 0 +s 9005028590050285 2200S (Vulcan) 0 +s 9005028590050286 2120S (Crusader) 0 +s 9005028590050287 2200S (Vulcan-2m) 0 +s 9005028590050288 3230S (Harrier) 0 +s 9005028590050289 3240S (Tornado) 0 +s 900502859005028a ASR-2020S PCI-X ZCR (Skyhawk) 0 +s 900502859005028b ASR-2020S SO-DIMM PCI-X ZCR (Terminator) 0 +s 9005028590050290 AAR-2410SA PCI SATA 4ch (Jaguar II) 0 +s 9005028590050292 AAR-2810SA PCI SATA 8ch (Corsair-8) 0 +s 9005028590050293 AAR-21610SA PCI SATA 16ch (Corsair-16) 0 +s 9005028590050294 ESD SO-DIMM PCI-X SATA ZCR (Prowler) 0 +d 90050286 AAC-RAID (Rocket) 0 +s 900502869005028c ASR-2230S + ASR-2230SLP PCI-X (Lancer) 0 +d 90058000 ASC-29320A U320 0 +d 9005800f AIC-7901 U320 0 +d 90058010 ASC-39320 U320 0 +d 90058011 ASC-32320D U320 0 +s 900580110e1100ac ASC-39320D U320 0 +s 9005801190050041 ASC-39320D U320 0 +d 90058012 ASC-29320 U320 0 +d 90058013 ASC-29320B U320 0 +d 90058014 ASC-29320LP U320 0 +d 90058015 ASC-39320B U320 0 +d 90058016 ASC-39320A U320 0 +d 90058017 ASC-29320ALP U320 0 +d 9005801c ASC-39320D U320 0 +d 9005801d AIC-7902B U320 0 +d 9005801e AIC-7901A U320 0 +d 9005801f AIC-7902 U320 0 +d 90058080 ASC-29320A U320 w/HostRAID 0 +d 9005808f AIC-7901 U320 w/HostRAID 0 +d 90058090 ASC-39320 U320 w/HostRAID 0 +d 90058091 ASC-39320D U320 w/HostRAID 0 +d 90058092 ASC-29320 U320 w/HostRAID 0 +d 90058093 ASC-29320B U320 w/HostRAID 0 +d 90058094 ASC-29320LP U320 w/HostRAID 0 +d 90058095 ASC-39320(B) U320 w/HostRAID 0 +d 90058096 ASC-39320A U320 w/HostRAID 0 +d 90058097 ASC-29320ALP U320 w/HostRAID 0 +d 9005809c ASC-39320D(B) U320 w/HostRAID 0 +d 9005809d AIC-7902(B) U320 w/HostRAID 0 +d 9005809e AIC-7901A U320 w/HostRAID 0 +d 9005809f AIC-7902 U320 w/HostRAID 0 +v 907f Atronics 0 +d 907f2015 IDE-2015PL 0 +v 919a Gigapixel Corp 0 +v 9412 Holtek 0 +d 94126565 6565 0 +v 9699 Omni Media Technology Inc 0 +d 96996565 6565 0 +v 9710 NetMos Technology 0 +d 97107780 USB IRDA-port 0 +d 97109815 PCI 9815 Multi-I/O Controller 0 +s 9710981510000020 2P0S (2 port parallel adaptor) 0 +d 97109835 PCI 9835 Multi-I/O Controller 0 +s 9710983510000002 2S (16C550 UART) 0 +s 9710983510000012 1P2S 0 +d 97109845 PCI 9845 Multi-I/O Controller 0 +s 9710984510000004 0P4S (4 port 16550A serial card) 0 +s 9710984510000006 0P6S (6 port 16550a serial card) 0 +d 97109855 PCI 9855 Multi-I/O Controller 0 +s 9710985510000014 1P4S 0 +v 9902 Stargen Inc. 0 +d 99020001 SG2010 PCI over Starfabric Bridge 0 +d 99020002 SG2010 PCI to Starfabric Gateway 0 +d 99020003 SG1010 Starfabric Switch and PCI Bridge 0 +v a0a0 AOPEN Inc. 0 +v a0f1 UNISYS Corporation 0 +v a200 NEC Corporation 0 +v a259 Hewlett Packard 0 +v a25b Hewlett Packard GmbH PL24-MKT 0 +v a304 Sony 0 +v a727 3Com Corporation 0 +d a7270013 3CRPAG175 Wireless PC Card 0 +v aa42 Scitex Digital Video 0 +v ac1e Digital Receiver Technology Inc 0 +v ac3d Actuality Systems 0 +v aecb Adrienne Electronics Corporation 0 +v b1b3 Shiva Europe Limited 0 +v bd11 Pinnacle Systems, Inc. (Wrong ID) 0 Pinnacle should be 11bd, but they got it wrong several times --mj +v c001 TSI Telsys 0 +v c0a9 Micron/Crucial Technology 0 +v c0de Motorola 0 +v c0fe Motion Engineering, Inc. 0 +v ca50 Varian Australia Pty Ltd 0 +v cafe Chrysalis-ITS 0 +v cccc Catapult Communications 0 +v cddd Tyzx, Inc. 0 +d cddd0101 DeepSea 1 High Speed Stereo Vision Frame Grabber 0 +d cddd0200 DeepSea 2 High Speed Stereo Vision Frame Grabber 0 +v d4d4 Dy4 Systems Inc 0 +d d4d40601 PCI Mezzanine Card 0 +v d531 I+ME ACTIA GmbH 0 +v d84d Exsys 0 +v dead Indigita Corporation 0 +v e000 Winbond 0 +d e000e000 W89C940 0 +v e159 Tiger Jet Network Inc. 0 see also : http://www.schoenfeld.de/inside/Inside_CWMK3.txt maybe a misuse of TJN id or it use the TJN 3XX chip for other applic +d e1590001 Tiger3XX Modem/ISDN interface 0 +s e159000100590001 128k ISDN-S/T Adapter 0 +s e159000100590003 128k ISDN-U Adapter 0 +d e1590002 Tiger100APC ISDN chipset 0 +v e4bf EKF Elektronik GmbH 0 +v e55e Essence Technology, Inc. 0 Innovative and scalable network IC vendor +v ea01 Eagle Technology 0 +v ea60 RME 0 The main chip of all these devices is by Xilinx -> It could also be a Xilinx ID. +d ea609896 Digi32 0 +d ea609897 Digi32 Pro 0 +d ea609898 Digi32/8 0 +v eabb Aashima Technology B.V. 0 +v eace Endace Measurement Systems, Ltd 0 +d eace3100 DAG 3.10 OC-3/OC-12 0 +d eace3200 DAG 3.2x OC-3/OC-12 0 +d eace320e DAG 3.2E Fast Ethernet 0 +d eace340e DAG 3.4E Fast Ethernet 0 +d eace341e DAG 3.41E Fast Ethernet 0 +d eace3500 DAG 3.5 OC-3/OC-12 0 +d eace351c DAG 3.5ECM Fast Ethernet 0 +d eace4100 DAG 4.10 OC-48 0 +d eace4110 DAG 4.11 OC-48 0 +d eace4220 DAG 4.2 OC-48 0 +d eace422e DAG 4.2E Dual Gigabit Ethernet 0 +v ec80 Belkin Corporation 0 +d ec80ec00 F5D6000 0 +v ecc0 Echo Digital Audio Corporation 0 +d ecc00050 Gina24_301 0 +d ecc00051 Gina24_361 0 +d ecc00060 Layla24 0 +d ecc00070 Mona_301_80 0 +d ecc00071 Mona_301_66 0 +d ecc00072 Mona_361 0 +d ecc00080 Mia 0 +v edd8 ARK Logic Inc 0 +d edd8a091 1000PV [Stingray] 0 +d edd8a099 2000PV [Stingray] 0 +d edd8a0a1 2000MT 0 +d edd8a0a9 2000MI 0 +v f1d0 AJA Video 0 +d f1d0cafe KONA SD SMPTE 259M I/O 0 All boards I have seen have this ID not efac, though all docs say efac... +d f1d0efac KONA SD SMPTE 259M I/O 0 +d f1d0facd KONA HD SMPTE 292M I/O 0 +v fa57 Interagon AS 0 +d fa570001 PMC [Pattern Matching Chip] 0 +v febd Ultraview Corp. 0 +v feda Broadcom Inc (nee Epigram) 0 +d fedaa0fa BCM4210 iLine10 HomePNA 2.0 0 +d fedaa10e BCM4230 iLine10 HomePNA 2.0 0 +v fede Fedetec Inc. 0 IT & Telecom company, develops PCI Trunk cards <www.fedetec.es> +d fede0003 TABIC PCI v3 0 +v fffe VMWare Inc 0 +d fffe0405 Virtual SVGA 4.0 0 +d fffe0710 Virtual SVGA 0 +v ffff Illegal Vendor ID 0 diff --git a/contrib/libdha/pci.c b/contrib/libdha/pci.c new file mode 100644 index 000000000..db8f4ddd5 --- /dev/null +++ b/contrib/libdha/pci.c @@ -0,0 +1,834 @@ +/* + (C) 2002 - library implementation by Nick Kyrshev + XFree86 3.3.3 scanpci.c, modified for GATOS/win/gfxdump by Øyvind Aabling. + */ +/* $XConsortium: scanpci.c /main/25 1996/10/27 11:48:40 kaleb $ */ +/* + * name: scanpci.c + * + * purpose: This program will scan for and print details of + * devices on the PCI bus. + + * author: Robin Cutshaw (robin@xfree86.org) + * + * supported O/S's: SVR4, UnixWare, SCO, Solaris, + * FreeBSD, NetBSD, 386BSD, BSDI BSD/386, + * Linux, Mach/386, ISC + * DOS (WATCOM 9.5 compiler) + * + * compiling: [g]cc scanpci.c -o scanpci + * for SVR4 (not Solaris), UnixWare use: + * [g]cc -DSVR4 scanpci.c -o scanpci + * for DOS, watcom 9.5: + * wcc386p -zq -omaxet -7 -4s -s -w3 -d2 name.c + * and link with PharLap or other dos extender for exe + * + */ + +/* $XFree86: xc/programs/Xserver/hw/xfree86/etc/scanpci.c,v 3.34.2.17 1998/11/10 11:55:40 dawes Exp $ */ + +/* + * Copyright 1995 by Robin Cutshaw <robin@XFree86.Org> + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that + * copyright notice and this permission notice appear in supporting + * documentation, and that the names of the above listed copyright holder(s) + * not be used in advertising or publicity pertaining to distribution of + * the software without specific, written prior permission. The above listed + * copyright holder(s) make(s) no representations about the suitability of this + * software for any purpose. It is provided "as is" without express or + * implied warranty. + * + * THE ABOVE LISTED COPYRIGHT HOLDER(S) DISCLAIM(S) ALL WARRANTIES WITH REGARD + * TO THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY + * AND FITNESS, IN NO EVENT SHALL THE ABOVE LISTED COPYRIGHT HOLDER(S) BE + * LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY + * DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER + * IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING + * OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +#include "libdha.h" +#include <errno.h> +#include <string.h> +#include <stdio.h> +#include <unistd.h> +#include <fcntl.h> +#include <sys/ioctl.h> +#include "kernelhelper/dhahelper.h" + +#ifdef __unix__ +#include <unistd.h> +#endif + +#if 0 +#if defined(__SUNPRO_C) || defined(sun) || defined(__sun) +#include <sys/psw.h> +#else +#include <sys/seg.h> +#endif +#include <sys/v86.h> +#endif + +#if defined(Lynx) && defined(__powerpc__) +/* let's mimick the Linux Alpha stuff for LynxOS so we don't have + * to change too much code + */ +#include <smem.h> + +static unsigned char *pciConfBase; + +static __inline__ unsigned long +static swapl(unsigned long val) +{ + unsigned char *p = (unsigned char *)&val; + return ((p[3] << 24) | (p[2] << 16) | (p[1] << 8) | (p[0] << 0)); +} + + +#define BUS(tag) (((tag)>>16)&0xff) +#define DFN(tag) (((tag)>>8)&0xff) + +#define PCIBIOS_DEVICE_NOT_FOUND 0x86 +#define PCIBIOS_SUCCESSFUL 0x00 + +int pciconfig_read( + unsigned char bus, + unsigned char dev, + unsigned char offset, + int len, /* unused, alway 4 */ + unsigned long *val) +{ + unsigned long _val; + unsigned long *ptr; + + dev >>= 3; + if (bus || dev >= 16) { + *val = 0xFFFFFFFF; + return PCIBIOS_DEVICE_NOT_FOUND; + } else { + ptr = (unsigned long *)(pciConfBase + ((1<<dev) | offset)); + _val = swapl(*ptr); + } + *val = _val; + return PCIBIOS_SUCCESSFUL; +} + +int pciconfig_write( + unsigned char bus, + unsigned char dev, + unsigned char offset, + int len, /* unused, alway 4 */ + unsigned long val) +{ + unsigned long _val; + unsigned long *ptr; + + dev >>= 3; + _val = swapl(val); + if (bus || dev >= 16) { + return PCIBIOS_DEVICE_NOT_FOUND; + } else { + ptr = (unsigned long *)(pciConfBase + ((1<<dev) | offset)); + *ptr = _val; + } + return PCIBIOS_SUCCESSFUL; +} +#endif + +#if !defined(__powerpc__) +struct pci_config_reg { + /* start of official PCI config space header */ + union { + unsigned long device_vendor; + struct { + unsigned short vendor; + unsigned short device; + } dv; + } dv_id; +#define _device_vendor dv_id.device_vendor +#define _vendor dv_id.dv.vendor +#define _device dv_id.dv.device + union { + unsigned long status_command; + struct { + unsigned short command; + unsigned short status; + } sc; + } stat_cmd; +#define _status_command stat_cmd.status_command +#define _command stat_cmd.sc.command +#define _status stat_cmd.sc.status + union { + unsigned long class_revision; + struct { + unsigned char rev_id; + unsigned char prog_if; + unsigned char sub_class; + unsigned char base_class; + } cr; + } class_rev; +#define _class_revision class_rev.class_revision +#define _rev_id class_rev.cr.rev_id +#define _prog_if class_rev.cr.prog_if +#define _sub_class class_rev.cr.sub_class +#define _base_class class_rev.cr.base_class + union { + unsigned long bist_header_latency_cache; + struct { + unsigned char cache_line_size; + unsigned char latency_timer; + unsigned char header_type; + unsigned char bist; + } bhlc; + } bhlc; +#define _bist_header_latency_cache bhlc.bist_header_latency_cache +#define _cache_line_size bhlc.bhlc.cache_line_size +#define _latency_timer bhlc.bhlc.latency_timer +#define _header_type bhlc.bhlc.header_type +#define _bist bhlc.bhlc.bist + union { + struct { + unsigned long dv_base0; + unsigned long dv_base1; + unsigned long dv_base2; + unsigned long dv_base3; + unsigned long dv_base4; + unsigned long dv_base5; + } dv; + struct { + unsigned long bg_rsrvd[2]; + unsigned char primary_bus_number; + unsigned char secondary_bus_number; + unsigned char subordinate_bus_number; + unsigned char secondary_latency_timer; + unsigned char io_base; + unsigned char io_limit; + unsigned short secondary_status; + unsigned short mem_base; + unsigned short mem_limit; + unsigned short prefetch_mem_base; + unsigned short prefetch_mem_limit; + } bg; + } bc; +#define _base0 bc.dv.dv_base0 +#define _base1 bc.dv.dv_base1 +#define _base2 bc.dv.dv_base2 +#define _base3 bc.dv.dv_base3 +#define _base4 bc.dv.dv_base4 +#define _base5 bc.dv.dv_base5 +#define _primary_bus_number bc.bg.primary_bus_number +#define _secondary_bus_number bc.bg.secondary_bus_number +#define _subordinate_bus_number bc.bg.subordinate_bus_number +#define _secondary_latency_timer bc.bg.secondary_latency_timer +#define _io_base bc.bg.io_base +#define _io_limit bc.bg.io_limit +#define _secondary_status bc.bg.secondary_status +#define _mem_base bc.bg.mem_base +#define _mem_limit bc.bg.mem_limit +#define _prefetch_mem_base bc.bg.prefetch_mem_base +#define _prefetch_mem_limit bc.bg.prefetch_mem_limit + unsigned long rsvd1; + unsigned long rsvd2; + unsigned long _baserom; + unsigned long rsvd3; + unsigned long rsvd4; + union { + unsigned long max_min_ipin_iline; + struct { + unsigned char int_line; + unsigned char int_pin; + unsigned char min_gnt; + unsigned char max_lat; + } mmii; + } mmii; +#define _max_min_ipin_iline mmii.max_min_ipin_iline +#define _int_line mmii.mmii.int_line +#define _int_pin mmii.mmii.int_pin +#define _min_gnt mmii.mmii.min_gnt +#define _max_lat mmii.mmii.max_lat + /* I don't know how accurate or standard this is (DHD) */ + union { + unsigned long user_config; + struct { + unsigned char user_config_0; + unsigned char user_config_1; + unsigned char user_config_2; + unsigned char user_config_3; + } uc; + } uc; +#define _user_config uc.user_config +#define _user_config_0 uc.uc.user_config_0 +#define _user_config_1 uc.uc.user_config_1 +#define _user_config_2 uc.uc.user_config_2 +#define _user_config_3 uc.uc.user_config_3 + /* end of official PCI config space header */ + unsigned long _pcibusidx; + unsigned long _pcinumbus; + unsigned long _pcibuses[16]; + unsigned short _configtype; /* config type found */ + unsigned short _ioaddr; /* config type 1 - private I/O addr */ + unsigned long _cardnum; /* config type 2 - private card number */ +}; +#else +/* ppc is big endian, swapping bytes is not quite enough + * to interpret the PCI config registers... + */ +struct pci_config_reg { + /* start of official PCI config space header */ + union { + unsigned long device_vendor; + struct { + unsigned short device; + unsigned short vendor; + } dv; + } dv_id; +#define _device_vendor dv_id.device_vendor +#define _vendor dv_id.dv.vendor +#define _device dv_id.dv.device + union { + unsigned long status_command; + struct { + unsigned short status; + unsigned short command; + } sc; + } stat_cmd; +#define _status_command stat_cmd.status_command +#define _command stat_cmd.sc.command +#define _status stat_cmd.sc.status + union { + unsigned long class_revision; + struct { + unsigned char base_class; + unsigned char sub_class; + unsigned char prog_if; + unsigned char rev_id; + } cr; + } class_rev; +#define _class_revision class_rev.class_revision +#define _rev_id class_rev.cr.rev_id +#define _prog_if class_rev.cr.prog_if +#define _sub_class class_rev.cr.sub_class +#define _base_class class_rev.cr.base_class + union { + unsigned long bist_header_latency_cache; + struct { + unsigned char bist; + unsigned char header_type; + unsigned char latency_timer; + unsigned char cache_line_size; + } bhlc; + } bhlc; +#define _bist_header_latency_cache bhlc.bist_header_latency_cache +#define _cache_line_size bhlc.bhlc.cache_line_size +#define _latency_timer bhlc.bhlc.latency_timer +#define _header_type bhlc.bhlc.header_type +#define _bist bhlc.bhlc.bist + union { + struct { + unsigned long dv_base0; + unsigned long dv_base1; + unsigned long dv_base2; + unsigned long dv_base3; + unsigned long dv_base4; + unsigned long dv_base5; + } dv; +/* ?? */ + struct { + unsigned long bg_rsrvd[2]; + + unsigned char secondary_latency_timer; + unsigned char subordinate_bus_number; + unsigned char secondary_bus_number; + unsigned char primary_bus_number; + + unsigned short secondary_status; + unsigned char io_limit; + unsigned char io_base; + + unsigned short mem_limit; + unsigned short mem_base; + + unsigned short prefetch_mem_limit; + unsigned short prefetch_mem_base; + } bg; + } bc; +#define _base0 bc.dv.dv_base0 +#define _base1 bc.dv.dv_base1 +#define _base2 bc.dv.dv_base2 +#define _base3 bc.dv.dv_base3 +#define _base4 bc.dv.dv_base4 +#define _base5 bc.dv.dv_base5 +#define _primary_bus_number bc.bg.primary_bus_number +#define _secondary_bus_number bc.bg.secondary_bus_number +#define _subordinate_bus_number bc.bg.subordinate_bus_number +#define _secondary_latency_timer bc.bg.secondary_latency_timer +#define _io_base bc.bg.io_base +#define _io_limit bc.bg.io_limit +#define _secondary_status bc.bg.secondary_status +#define _mem_base bc.bg.mem_base +#define _mem_limit bc.bg.mem_limit +#define _prefetch_mem_base bc.bg.prefetch_mem_base +#define _prefetch_mem_limit bc.bg.prefetch_mem_limit + unsigned long rsvd1; + unsigned long rsvd2; + unsigned long _baserom; + unsigned long rsvd3; + unsigned long rsvd4; + union { + unsigned long max_min_ipin_iline; + struct { + unsigned char max_lat; + unsigned char min_gnt; + unsigned char int_pin; + unsigned char int_line; + } mmii; + } mmii; +#define _max_min_ipin_iline mmii.max_min_ipin_iline +#define _int_line mmii.mmii.int_line +#define _int_pin mmii.mmii.int_pin +#define _min_gnt mmii.mmii.min_gnt +#define _max_lat mmii.mmii.max_lat + /* I don't know how accurate or standard this is (DHD) */ + union { + unsigned long user_config; + struct { + unsigned char user_config_3; + unsigned char user_config_2; + unsigned char user_config_1; + unsigned char user_config_0; + } uc; + } uc; +#define _user_config uc.user_config +#define _user_config_0 uc.uc.user_config_0 +#define _user_config_1 uc.uc.user_config_1 +#define _user_config_2 uc.uc.user_config_2 +#define _user_config_3 uc.uc.user_config_3 + /* end of official PCI config space header */ + unsigned long _pcibusidx; + unsigned long _pcinumbus; + unsigned long _pcibuses[16]; + unsigned short _ioaddr; /* config type 1 - private I/O addr */ + unsigned short _configtype; /* config type found */ + unsigned long _cardnum; /* config type 2 - private card number */ +}; +#endif + +#define MAX_DEV_PER_VENDOR_CFG1 64 +#define MAX_PCI_DEVICES_PER_BUS 32 +#define MAX_PCI_DEVICES 64 +#define NF ((void (*)())NULL), { 0.0, 0, 0, NULL } +#define PCI_MULTIFUNC_DEV 0x80 +#define PCI_ID_REG 0x00 +#define PCI_CMD_STAT_REG 0x04 +#define PCI_CLASS_REG 0x08 +#define PCI_HEADER_MISC 0x0C +#define PCI_MAP_REG_START 0x10 +#define PCI_MAP_ROM_REG 0x30 +#define PCI_INTERRUPT_REG 0x3C +#define PCI_INTERRUPT_PIN 0x3D /* 8 bits */ +#define PCI_MIN_GNT 0x3E /* 8 bits */ +#define PCI_MAX_LAT 0x3F /* 8 bits */ +#define PCI_REG_USERCONFIG 0x40 + +static int pcibus=-1, pcicard=-1, pcifunc=-1 ; +/*static struct pci_device *pcidev=NULL ;*/ + +#if defined(__alpha__) +#define PCI_EN 0x00000000 +#else +#define PCI_EN 0x80000000 +#endif + +#define PCI_MODE1_ADDRESS_REG 0xCF8 +#define PCI_MODE1_DATA_REG 0xCFC + +#define PCI_MODE2_ENABLE_REG 0xCF8 +#ifdef PC98 +#define PCI_MODE2_FORWARD_REG 0xCF9 +#else +#define PCI_MODE2_FORWARD_REG 0xCFA +#endif + +/* cpu depended stuff */ +#if defined(__alpha__) +#include "sysdep/pci_alpha.c" +#elif defined(__ia64__) +#include "sysdep/pci_ia64.c" +#elif defined(__sparc__) +#include "sysdep/pci_sparc.c" +#elif defined( __arm32__ ) +#include "sysdep/pci_arm32.c" +#elif defined(__powerpc__) +#include "sysdep/pci_powerpc.c" +#elif defined( __i386__ ) +#include "sysdep/pci_x86.c" +#else +#include "sysdep/pci_generic_cpu.c" +#endif + +static int pcicards=0 ; +static pciinfo_t *pci_lst; + +static void identify_card(struct pci_config_reg *pcr) +{ + + if (pcicards>=MAX_PCI_DEVICES) return ; + + pci_lst[pcicards].bus = pcibus ; + pci_lst[pcicards].card = pcicard ; + pci_lst[pcicards].func = pcifunc ; + pci_lst[pcicards].vendor = pcr->_vendor ; + pci_lst[pcicards].device = pcr->_device ; + pci_lst[pcicards].base0 = 0xFFFFFFFF ; + pci_lst[pcicards].base1 = 0xFFFFFFFF ; + pci_lst[pcicards].base2 = 0xFFFFFFFF ; + pci_lst[pcicards].base3 = 0xFFFFFFFF ; + pci_lst[pcicards].base4 = 0xFFFFFFFF ; + pci_lst[pcicards].base5 = 0xFFFFFFFF ; + pci_lst[pcicards].baserom = 0x000C0000 ; + if (pcr->_base0) pci_lst[pcicards].base0 = pcr->_base0 & + ((pcr->_base0&0x1) ? 0xFFFFFFFC : 0xFFFFFFF0) ; + if (pcr->_base1) pci_lst[pcicards].base1 = pcr->_base1 & + ((pcr->_base1&0x1) ? 0xFFFFFFFC : 0xFFFFFFF0) ; + if (pcr->_base2) pci_lst[pcicards].base2 = pcr->_base2 & + ((pcr->_base2&0x1) ? 0xFFFFFFFC : 0xFFFFFFF0) ; + if (pcr->_base3) pci_lst[pcicards].base3 = pcr->_base3 & + ((pcr->_base0&0x1) ? 0xFFFFFFFC : 0xFFFFFFF0) ; + if (pcr->_base4) pci_lst[pcicards].base4 = pcr->_base4 & + ((pcr->_base1&0x1) ? 0xFFFFFFFC : 0xFFFFFFF0) ; + if (pcr->_base5) pci_lst[pcicards].base5 = pcr->_base5 & + ((pcr->_base2&0x1) ? 0xFFFFFFFC : 0xFFFFFFF0) ; + if (pcr->_baserom) pci_lst[pcicards].baserom = pcr->_baserom ; + pci_lst[pcicards].irq = pcr->_int_line; + pci_lst[pcicards].ipin= pcr->_int_pin; + pci_lst[pcicards].gnt = pcr->_min_gnt; + pci_lst[pcicards].lat = pcr->_max_lat; + + pcicards++; +} + +/*main(int argc, char *argv[])*/ +static int __pci_scan(pciinfo_t *pci_list,unsigned *num_pci) +{ + unsigned int idx; + struct pci_config_reg pcr; + int do_mode1_scan = 0, do_mode2_scan = 0; + int func, hostbridges=0; + int ret = -1; + + pci_lst = pci_list; + pcicards = 0; + + ret = enable_app_io(); + if (ret != 0) + return(ret); + + if((pcr._configtype = pci_config_type()) == 0xFFFF) return ENODEV; + + /* Try pci config 1 probe first */ + + if ((pcr._configtype == 1) || do_mode1_scan) { + /*printf("\nPCI probing configuration type 1\n");*/ + + pcr._ioaddr = 0xFFFF; + + pcr._pcibuses[0] = 0; + pcr._pcinumbus = 1; + pcr._pcibusidx = 0; + idx = 0; + + do { + /*printf("Probing for devices on PCI bus %d:\n\n", pcr._pcibusidx);*/ + + for (pcr._cardnum = 0x0; pcr._cardnum < MAX_PCI_DEVICES_PER_BUS; + pcr._cardnum += 0x1) { + func = 0; + do { /* loop over the different functions, if present */ + pcr._device_vendor = pci_get_vendor(pcr._pcibuses[pcr._pcibusidx], pcr._cardnum, + func); + if ((pcr._vendor == 0xFFFF) || (pcr._device == 0xFFFF)) + break; /* nothing there */ + + /*printf("\npci bus 0x%x cardnum 0x%02x function 0x%04x: vendor 0x%04x device 0x%04x\n", + pcr._pcibuses[pcr._pcibusidx], pcr._cardnum, func, + pcr._vendor, pcr._device);*/ + pcibus = pcr._pcibuses[pcr._pcibusidx]; + pcicard = pcr._cardnum; + pcifunc = func; + + pcr._status_command = pci_config_read_long(pcr._pcibuses[pcr._pcibusidx], + pcr._cardnum,func,PCI_CMD_STAT_REG); + pcr._class_revision = pci_config_read_long(pcr._pcibuses[pcr._pcibusidx], + pcr._cardnum,func,PCI_CLASS_REG); + pcr._bist_header_latency_cache = pci_config_read_long(pcr._pcibuses[pcr._pcibusidx], + pcr._cardnum,func,PCI_HEADER_MISC); + pcr._base0 = pci_config_read_long(pcr._pcibuses[pcr._pcibusidx], + pcr._cardnum,func,PCI_MAP_REG_START); + pcr._base1 = pci_config_read_long(pcr._pcibuses[pcr._pcibusidx], + pcr._cardnum,func,PCI_MAP_REG_START+4); + pcr._base2 = pci_config_read_long(pcr._pcibuses[pcr._pcibusidx], + pcr._cardnum,func,PCI_MAP_REG_START+8); + pcr._base3 = pci_config_read_long(pcr._pcibuses[pcr._pcibusidx], + pcr._cardnum,func,PCI_MAP_REG_START+0x0C); + pcr._base4 = pci_config_read_long(pcr._pcibuses[pcr._pcibusidx], + pcr._cardnum,func,PCI_MAP_REG_START+0x10); + pcr._base5 = pci_config_read_long(pcr._pcibuses[pcr._pcibusidx], + pcr._cardnum,func,PCI_MAP_REG_START+0x14); + pcr._baserom = pci_config_read_long(pcr._pcibuses[pcr._pcibusidx], + pcr._cardnum,func,PCI_MAP_ROM_REG); +#if 0 + pcr._int_pin = pci_config_read_byte(pcr._pcibuses[pcr._pcibusidx], + pcr._cardnum,func,PCI_INTERRUPT_PIN); + pcr._int_line = pci_config_read_byte(pcr._pcibuses[pcr._pcibusidx], + pcr._cardnum,func,PCI_INTERRUPT_REG); + pcr._min_gnt = pci_config_read_byte(pcr._pcibuses[pcr._pcibusidx], + pcr._cardnum,func,PCI_MIN_GNT); + pcr._max_lat = pci_config_read_byte(pcr._pcibuses[pcr._pcibusidx], + pcr._cardnum,func,PCI_MAX_LAT); +#else + pcr._max_min_ipin_iline = pci_config_read_long(pcr._pcibuses[pcr._pcibusidx], + pcr._cardnum,func,PCI_INTERRUPT_REG); +#endif + pcr._user_config = pci_config_read_long(pcr._pcibuses[pcr._pcibusidx], + pcr._cardnum,func,PCI_REG_USERCONFIG); + /* check for pci-pci bridges */ +#define PCI_CLASS_MASK 0xff000000 +#define PCI_SUBCLASS_MASK 0x00ff0000 +#define PCI_CLASS_BRIDGE 0x06000000 +#define PCI_SUBCLASS_BRIDGE_PCI 0x00040000 + switch(pcr._class_revision & (PCI_CLASS_MASK|PCI_SUBCLASS_MASK)) { + case PCI_CLASS_BRIDGE|PCI_SUBCLASS_BRIDGE_PCI: + if (pcr._secondary_bus_number > 0) { + pcr._pcibuses[pcr._pcinumbus++] = pcr._secondary_bus_number; + } + break; + case PCI_CLASS_BRIDGE: + if ( ++hostbridges > 1) { + pcr._pcibuses[pcr._pcinumbus] = pcr._pcinumbus; + pcr._pcinumbus++; + } + break; + default: + break; + } + if((func==0) && ((pcr._header_type & PCI_MULTIFUNC_DEV) == 0)) { + /* not a multi function device */ + func = 8; + } else { + func++; + } + + if (idx++ >= MAX_PCI_DEVICES) + continue; + + identify_card(&pcr); + } while( func < 8 ); + } + } while (++pcr._pcibusidx < pcr._pcinumbus); + } + +#if !defined(__alpha__) && !defined(__powerpc__) + /* Now try pci config 2 probe (deprecated) */ + + if ((pcr._configtype == 2) || do_mode2_scan) { + OUTPORT8(PCI_MODE2_ENABLE_REG, 0xF1); + OUTPORT8(PCI_MODE2_FORWARD_REG, 0x00); /* bus 0 for now */ + + /*printf("\nPCI probing configuration type 2\n");*/ + + pcr._pcibuses[0] = 0; + pcr._pcinumbus = 1; + pcr._pcibusidx = 0; + idx = 0; + + do { + for (pcr._ioaddr = 0xC000; pcr._ioaddr < 0xD000; pcr._ioaddr += 0x0100){ + OUTPORT8(PCI_MODE2_FORWARD_REG, pcr._pcibuses[pcr._pcibusidx]); /* bus 0 for now */ + pcr._device_vendor = INPORT32(pcr._ioaddr); + OUTPORT8(PCI_MODE2_FORWARD_REG, 0x00); /* bus 0 for now */ + + if ((pcr._vendor == 0xFFFF) || (pcr._device == 0xFFFF)) + continue; + if ((pcr._vendor == 0xF0F0) || (pcr._device == 0xF0F0)) + continue; /* catch ASUS P55TP4XE motherboards */ + + /*printf("\npci bus 0x%x slot at 0x%04x, vendor 0x%04x device 0x%04x\n", + pcr._pcibuses[pcr._pcibusidx], pcr._ioaddr, pcr._vendor, + pcr._device);*/ + pcibus = pcr._pcibuses[pcr._pcibusidx] ; + pcicard = pcr._ioaddr ; pcifunc = 0 ; + + OUTPORT8(PCI_MODE2_FORWARD_REG, pcr._pcibuses[pcr._pcibusidx]); /* bus 0 for now */ + pcr._status_command = INPORT32(pcr._ioaddr + 0x04); + pcr._class_revision = INPORT32(pcr._ioaddr + 0x08); + pcr._bist_header_latency_cache = INPORT32(pcr._ioaddr + 0x0C); + pcr._base0 = INPORT32(pcr._ioaddr + 0x10); + pcr._base1 = INPORT32(pcr._ioaddr + 0x14); + pcr._base2 = INPORT32(pcr._ioaddr + 0x18); + pcr._base3 = INPORT32(pcr._ioaddr + 0x1C); + pcr._base4 = INPORT32(pcr._ioaddr + 0x20); + pcr._base5 = INPORT32(pcr._ioaddr + 0x24); + pcr._baserom = INPORT32(pcr._ioaddr + 0x30); + pcr._max_min_ipin_iline = INPORT8(pcr._ioaddr + 0x3C); + pcr._user_config = INPORT32(pcr._ioaddr + 0x40); + OUTPORT8(PCI_MODE2_FORWARD_REG, 0x00); /* bus 0 for now */ + + /* check for pci-pci bridges (currently we only know Digital) */ + if ((pcr._vendor == 0x1011) && (pcr._device == 0x0001)) + if (pcr._secondary_bus_number > 0) + pcr._pcibuses[pcr._pcinumbus++] = pcr._secondary_bus_number; + + if (idx++ >= MAX_PCI_DEVICES) + continue; + + identify_card(&pcr); + } + } while (++pcr._pcibusidx < pcr._pcinumbus); + + OUTPORT8(PCI_MODE2_ENABLE_REG, 0x00); + } + +#endif /* __alpha__ */ + + disable_app_io(); + *num_pci = pcicards; + + return 0 ; + +} + +#if !defined(ENOTSUP) +#if defined(EOPNOTSUPP) +#define ENOTSUP EOPNOTSUPP +#else +#warning "ENOTSUP nor EOPNOTSUPP defined!" +#endif +#endif + +int pci_scan(pciinfo_t *pci_list,unsigned *num_pci) +{ + int libdha_fd; + if ( (libdha_fd = open("/dev/dhahelper",O_RDWR)) < 0) + { + return __pci_scan(pci_list,num_pci); + } + else + { + dhahelper_pci_device_t pci_dev; + unsigned idx; + idx = 0; + while(ioctl(libdha_fd, DHAHELPER_PCI_FIND, &pci_dev)==0) + { + pci_list[idx].bus = pci_dev.bus; + pci_list[idx].card = pci_dev.card; + pci_list[idx].func = pci_dev.func; + pci_list[idx].vendor = pci_dev.vendor; + pci_list[idx].device = pci_dev.device; + pci_list[idx].base0 = pci_dev.base0?pci_dev.base0:0xFFFFFFFF; + pci_list[idx].base1 = pci_dev.base1?pci_dev.base1:0xFFFFFFFF; + pci_list[idx].base2 = pci_dev.base2?pci_dev.base2:0xFFFFFFFF; + pci_list[idx].baserom = pci_dev.baserom?pci_dev.baserom:0x000C0000; + pci_list[idx].base3 = pci_dev.base3?pci_dev.base3:0xFFFFFFFF; + pci_list[idx].base4 = pci_dev.base4?pci_dev.base4:0xFFFFFFFF; + pci_list[idx].base5 = pci_dev.base5?pci_dev.base5:0xFFFFFFFF; + pci_list[idx].irq = pci_dev.irq; + pci_list[idx].ipin = pci_dev.ipin; + pci_list[idx].gnt = pci_dev.gnt; + pci_list[idx].lat = pci_dev.lat; + idx++; + } + *num_pci=idx; + close(libdha_fd); + } + return 0; +} + +int pci_config_read(unsigned char bus, unsigned char dev, unsigned char func, + unsigned char cmd, int len, unsigned long *val) +{ + int ret; + int dhahelper_fd; + if ( (dhahelper_fd = open("/dev/dhahelper",O_RDWR)) > 0) + { + int retval; + dhahelper_pci_config_t pcic; + pcic.operation = PCI_OP_READ; + pcic.bus = bus; + pcic.dev = dev; + pcic.func = func; + pcic.cmd = cmd; + pcic.size = len; + retval = ioctl(dhahelper_fd, DHAHELPER_PCI_CONFIG, &pcic); + close(dhahelper_fd); + *val = pcic.ret; + return retval; + } + ret = enable_app_io(); + if (ret != 0) + return(ret); + switch(len) + { + case 4: + ret = pci_config_read_long(bus, dev, func, cmd); + break; + case 2: + ret = pci_config_read_word(bus, dev, func, cmd); + break; + case 1: + ret = pci_config_read_byte(bus, dev, func, cmd); + break; + default: + printf("libdha_pci: wrong length to read: %u\n",len); + } + disable_app_io(); + + *val = ret; + return(0); +} + +int pci_config_write(unsigned char bus, unsigned char dev, unsigned char func, + unsigned char cmd, int len, unsigned long val) +{ + int ret; + + int dhahelper_fd; + if ( (dhahelper_fd = open("/dev/dhahelper",O_RDWR)) > 0) + { + int retval; + dhahelper_pci_config_t pcic; + pcic.operation = PCI_OP_WRITE; + pcic.bus = bus; + pcic.dev = dev; + pcic.func = func; + pcic.cmd = cmd; + pcic.size = len; + pcic.ret = val; + retval = ioctl(dhahelper_fd, DHAHELPER_PCI_CONFIG, &pcic); + close(dhahelper_fd); + return retval; + } + ret = enable_app_io(); + if (ret != 0) + return ret; + switch(len) + { + case 4: + pci_config_write_long(bus, dev, func, cmd, val); + break; + case 2: + pci_config_write_word(bus, dev, func, cmd, val); + break; + case 1: + pci_config_write_byte(bus, dev, func, cmd, val); + break; + default: + printf("libdha_pci: wrong length to read: %u\n",len); + } + disable_app_io(); + + return 0; +} diff --git a/contrib/libdha/pci_db2c.awk b/contrib/libdha/pci_db2c.awk new file mode 100644 index 000000000..feaa1c7a1 --- /dev/null +++ b/contrib/libdha/pci_db2c.awk @@ -0,0 +1,267 @@ +# This file converts given pci.db to "C" source and header files +# For latest version of pci ids see: http://pciids.sf.net +# Copyright 2002 Nick Kurshev +# +# Usage: awk -f pci_db2c.awk pci.db +# +# Tested with Gawk v 3.0.x and Mawk 1.3.3 +# But it should work with standard Awk implementations (hopefully). +# (Nobody tested it with Nawk, but it should work, too). +# + +BEGIN { + + if(ARGC != 2) { +# check for arguments: + print "Usage awk -f pci_db2c.awk pci.db (and make sure pci.db file exists first)"; + exit(1); + } + in_file = ARGV[1]; + vendor_file = "pci_vendors.h"; + ids_file = "pci_ids.h" + name_file = "pci_names.c" + name_h_file = "pci_names.h" + dev_ids_file = "pci_dev_ids.c" + line=0; +# print out head lines + print_head(vendor_file); + print_head(ids_file); + print_head(name_file); + print_head(name_h_file); + print_head(dev_ids_file); + print "#ifndef PCI_VENDORS_INCLUDED" >vendor_file + print "#define PCI_VENDORS_INCLUDED 1">vendor_file + print "" >vendor_file + print "#ifndef PCI_IDS_INCLUDED" >ids_file + print "#define PCI_IDS_INCLUDED 1">ids_file + print "" >ids_file + print "#include \"pci_vendors.h\"">ids_file + print "" >ids_file + + print "#ifndef PCI_NAMES_INCLUDED" >name_h_file + print "#define PCI_NAMES_INCLUDED 1">name_h_file + print "" >name_h_file + print_name_struct(name_h_file); + print "#include <stddef.h>">name_file + print "#include \"pci_names.h\"">name_file + print "#include \"pci_dev_ids.c\"">name_file + print "">name_file + print "static struct vendor_id_s vendor_ids[] = {">name_file + first_pass=1; + init_name_db(); + while(getline <in_file) + { +# count up lines + line++; + n=split($0, field, "[\t]"); + name_field = kill_double_quoting(field[3]) + if(field[1] == "v" && length(field[3])>0 && field[4] == "0") + { + init_device_db() + svend_name = get_short_vendor_name(field[3]) + printf("#define VENDOR_%s\t", svend_name) >vendor_file; + if(length(svend_name) < 9) printf("\t") >vendor_file; + printf("0x%s /*%s*/\n",field[2], name_field) >vendor_file; + printf("{ 0x%s, \"%s\", dev_lst_%s },\n",field[2], name_field, field[2]) >name_file; + printf("/* Vendor: %s: %s */\n", field[2], name_field) > ids_file + if(first_pass == 1) { first_pass=0; } + else { print "{ 0xFFFF, NULL }\n};" >dev_ids_file; } + printf("static const struct device_id_s dev_lst_%s[]={\n", field[2])>dev_ids_file + } + if(field[1] == "d" && length(field[3])>0 && field[4] == "0") + { + sdev_name = get_short_device_name(field[3]) + full_name = sprintf("#define DEVICE_%s_%s", svend_name, sdev_name); + printf("%s\t", full_name) >ids_file + if(length(full_name) < 9) printf("\t") >ids_file; + if(length(full_name) < 17) printf("\t") >ids_file; + if(length(full_name) < 25) printf("\t") >ids_file; + if(length(full_name) < 32) printf("\t") >ids_file; + if(length(full_name) < 40) printf("\t") >ids_file; + if(length(full_name) < 48) printf("\t") >ids_file; + printf("0x%s /*%s*/\n", substr(field[2], 5), name_field) >ids_file + printf("{ 0x%s, \"%s\" },\n", substr(field[2], 5), name_field) >dev_ids_file + } + if(field[1] == "s" && length(field[3])>0 && field[4] == "0") + { + subdev_name = get_short_subdevice_name(field[3]) + full_name = sprintf("#define SUBDEVICE_%s_%s", svend_name, subdev_name) + printf("\t%s\t", full_name) >ids_file + if(length(full_name) < 9) printf("\t") >ids_file; + if(length(full_name) < 17) printf("\t") >ids_file; + if(length(full_name) < 25) printf("\t") >ids_file; + if(length(full_name) < 32) printf("\t") >ids_file; + if(length(full_name) < 40) printf("\t") >ids_file; + printf("0x%s /*%s*/\n", substr(field[2], 9), name_field) >ids_file + } + } + print "Total lines parsed:", line; + print "">vendor_file + print "#endif/*PCI_VENDORS_INCLUDED*/">vendor_file + print "">ids_file + print "#endif/*PCI_IDS_INCLUDED*/">ids_file + print "">name_h_file + print "#endif/*PCI_NAMES_INCLUDED*/">name_h_file + print "};">name_file + print "{ 0xFFFF, NULL }" >dev_ids_file; + print "};">dev_ids_file + print_func_bodies(name_file); +} + +function print_head( out_file) +{ + print "/*" >out_file; + printf(" * File: %s\n", out_file) >out_file; + printf(" * This file was generated automatically. Don't modify it.\n") >out_file; + print "*/" >out_file; + return; +} + +function print_name_struct(out_file) +{ + print "#ifdef __cplusplus" >out_file + print "extern \"C\" {" >out_file + print "#endif" >out_file + print "">out_file + print "struct device_id_s" >out_file + print "{" >out_file + print "\tunsigned short\tid;" >out_file + print "\tconst char *\tname;" >out_file + print "};" >out_file + print "">out_file + print "struct vendor_id_s" >out_file + print "{" >out_file + print "\tunsigned short\tid;" >out_file + print "\tconst char *\tname;" >out_file + print "\tconst struct device_id_s *\tdev_list;" >out_file + print "};" >out_file + print "extern const char *pci_vendor_name(unsigned short id);">out_file + print "extern const char *pci_device_name(unsigned short vendor_id, unsigned short device_id);">out_file + print "">out_file + print "#ifdef __cplusplus" >out_file + print "}" >out_file + print "#endif" >out_file + return +} + +function print_func_bodies(out_file) +{ + print "">out_file + print "const char *pci_vendor_name(unsigned short id)" >out_file + print "{" >out_file + print " unsigned i;" >out_file + print " for(i=0;i<sizeof(vendor_ids)/sizeof(struct vendor_id_s);i++)">out_file + print " {" >out_file + print "\tif(vendor_ids[i].id == id) return vendor_ids[i].name;" >out_file + print " }" >out_file + print " return NULL;" >out_file + print "}">out_file + print "" >out_file + print "const char *pci_device_name(unsigned short vendor_id, unsigned short device_id)" >out_file + print "{" >out_file + print " unsigned i, j;" >out_file + print " for(i=0;i<sizeof(vendor_ids)/sizeof(struct vendor_id_s);i++)">out_file + print " {" >out_file + print "\tif(vendor_ids[i].id == vendor_id)" >out_file + print "\t{" >out_file + print "\t j=0;" >out_file + print "\t while(vendor_ids[i].dev_list[j].id != 0xFFFF)" >out_file + print "\t {">out_file + print "\t\tif(vendor_ids[i].dev_list[j].id == device_id) return vendor_ids[i].dev_list[j].name;">out_file + print "\t\tj++;">out_file + print "\t };">out_file + print "\t break;" >out_file + print "\t}" >out_file + print " }" >out_file + print " return NULL;">out_file + print "}">out_file + return +} + +function kill_double_quoting(fld) +{ + n=split(fld,phrases, "[\"]"); + new_fld = phrases[1] + for(i=2;i<=n;i++) new_fld = sprintf("%s\\\"%s", new_fld, phrases[i]) + return new_fld +} + +function init_name_db() +{ + vendor_names[1]="" +} + +function init_device_db() +{ +# delete device_names + for( i in device_names ) delete device_names[i]; + device_names[1]="" +# delete subdevice_names + for( i in subdevice_names ) delete subdevice_names[i]; + subdevice_names[1] = "" +} + +function get_short_vendor_name(from) +{ + n=split(from, name, "[ ]"); + new_name = toupper(name[1]); + if(length(new_name)<3) new_name = sprintf("%s_%s", new_name, toupper(name[2])); + n=split(new_name, name, "[^0-9A-Za-z]"); + svendor = name[1]; + for(i=2;i<=n;i++) svendor=sprintf("%s%s%s", svendor, length(name[i])?"_":"", name[i]); + new_name = svendor; + vend_suffix = 2; +# check for unique + while(new_name in vendor_names) + { + new_name = sprintf("%s%u", svendor, vend_suffix) + vend_suffix = vend_suffix + 1; + } +# Add new name in array of vendor's names + vendor_names[new_name] = new_name + return new_name; +} + +function get_short_device_name(from_name) +{ + n=split(from_name, name, "[ ]"); + new_name = toupper(name[1]); + if(length(name[2])) new_name = sprintf("%s_%s", new_name, toupper(name[2])); + if(length(name[3])) new_name = sprintf("%s_%s", new_name, toupper(name[3])); + n=split(new_name, name, "[^0-9A-Za-z]"); + sdevice = name[1]; + for(i=2;i<=n;i++) sdevice=sprintf("%s%s%s", sdevice, length(name[i])?"_":"", name[i]); + new_name = sdevice; + dev_suffix = 2; +# check for unique + while(new_name in device_names) + { + new_name = sprintf("%s%u", sdevice, dev_suffix) + dev_suffix = dev_suffix + 1; + } +# Add new name in array of device names + device_names[new_name] = new_name + return new_name; +} + +function get_short_subdevice_name(from_name) +{ + n=split(from_name, name, "[ ]"); + new_name = toupper(name[1]); + if(length(name[2])) new_name = sprintf("%s_%s", new_name, toupper(name[2])); + if(length(name[3])) new_name = sprintf("%s_%s", new_name, toupper(name[3])); + n=split(new_name, name, "[^0-9A-Za-z]"); + ssdevice = name[1]; + for(i=2;i<=n;i++) ssdevice=sprintf("%s%s%s", ssdevice, length(name[i])?"_":"", name[i]); + new_name = ssdevice; + sdev_suffix = 2; +# check for unique + while(new_name in subdevice_names) + { + new_name = sprintf("%s%u", ssdevice, sdev_suffix) + sdev_suffix = sdev_suffix + 1; + } +# Add new name in array of subdevice names + subdevice_names[new_name] = new_name + return new_name; +} diff --git a/contrib/libdha/ports.c b/contrib/libdha/ports.c new file mode 100644 index 000000000..b531082d3 --- /dev/null +++ b/contrib/libdha/ports.c @@ -0,0 +1,219 @@ +/* + (C) 2002 - library implementation by Nick Kyrshev + XFree86 3.3.3 scanpci.c, modified for GATOS/win/gfxdump by Øyvind Aabling. + */ +/* $XConsortium: scanpci.c /main/25 1996/10/27 11:48:40 kaleb $ */ +/* + * name: scanpci.c + * + * purpose: This program will scan for and print details of + * devices on the PCI bus. + + * author: Robin Cutshaw (robin@xfree86.org) + * + * supported O/S's: SVR4, UnixWare, SCO, Solaris, + * FreeBSD, NetBSD, 386BSD, BSDI BSD/386, + * Linux, Mach/386, ISC + * DOS (WATCOM 9.5 compiler) + * + * compiling: [g]cc scanpci.c -o scanpci + * for SVR4 (not Solaris), UnixWare use: + * [g]cc -DSVR4 scanpci.c -o scanpci + * for DOS, watcom 9.5: + * wcc386p -zq -omaxet -7 -4s -s -w3 -d2 name.c + * and link with PharLap or other dos extender for exe + * + */ + +/* $XFree86: xc/programs/Xserver/hw/xfree86/etc/scanpci.c,v 3.34.2.17 1998/11/10 11:55:40 dawes Exp $ */ + +/* + * Copyright 1995 by Robin Cutshaw <robin@XFree86.Org> + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that + * copyright notice and this permission notice appear in supporting + * documentation, and that the names of the above listed copyright holder(s) + * not be used in advertising or publicity pertaining to distribution of + * the software without specific, written prior permission. The above listed + * copyright holder(s) make(s) no representations about the suitability of this + * software for any purpose. It is provided "as is" without express or + * implied warranty. + * + * THE ABOVE LISTED COPYRIGHT HOLDER(S) DISCLAIM(S) ALL WARRANTIES WITH REGARD + * TO THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY + * AND FITNESS, IN NO EVENT SHALL THE ABOVE LISTED COPYRIGHT HOLDER(S) BE + * LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY + * DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER + * IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING + * OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ +#include <sys/ioctl.h> +#include <stdio.h> +#include <stdlib.h> +#include <string.h> +#include <fcntl.h> +#include <sys/stat.h> +#include <sys/types.h> +#ifdef ARCH_ALPHA +#include <sys/io.h> +#endif +#include <unistd.h> + +#include "libdha.h" +#include "AsmMacros.h" +#include "kernelhelper/dhahelper.h" + +/* OS depended stuff */ +#if defined (linux) +#include "sysdep/pci_linux.c" +#elif defined (__FreeBSD__) +#include "sysdep/pci_freebsd.c" +#elif defined (__386BSD__) +#include "sysdep/pci_386bsd.c" +#elif defined (__NetBSD__) +#include "sysdep/pci_netbsd.c" +#elif defined (__OpenBSD__) +#include "sysdep/pci_openbsd.c" +#elif defined (__bsdi__) +#include "sysdep/pci_bsdi.c" +#elif defined (Lynx) +#include "sysdep/pci_lynx.c" +#elif defined (MACH386) +#include "sysdep/pci_mach386.c" +#elif defined (__SVR4) +#if !defined(SVR4) +#define SVR4 +#endif +#include "sysdep/pci_svr4.c" +#elif defined (SCO) +#include "sysdep/pci_sco.c" +#elif defined (ISC) +#include "sysdep/pci_isc.c" +#elif defined (__EMX__) +#include "sysdep/pci_os2.c" +#elif defined (_WIN32) || defined(__CYGWIN__) +#include "sysdep/pci_win32.c" +#else +#include "sysdep/pci_generic_os.c" +#endif + +static int dhahelper_fd=-1; +static unsigned dhahelper_counter=0; +int enable_app_io( void ) +{ + if((dhahelper_fd=open("/dev/dhahelper",O_RDWR)) < 0) return enable_os_io(); + dhahelper_counter++; + return 0; +} + +int disable_app_io( void ) +{ + dhahelper_counter--; + if(dhahelper_fd > 0) + { + if(!dhahelper_counter) + { + close(dhahelper_fd); + dhahelper_fd = -1; + } + } + else return disable_os_io(); + return 0; +} + +unsigned char INPORT8(unsigned idx) +{ + if (dhahelper_fd > 0) + { + dhahelper_port_t _port; + + _port.operation = PORT_OP_READ; + _port.addr = idx; + _port.size = 1; + if (ioctl(dhahelper_fd, DHAHELPER_PORT, &_port) == 0) + return _port.value; + } + return inb(idx); +} + +unsigned short INPORT16(unsigned idx) +{ + if (dhahelper_fd > 0) + { + dhahelper_port_t _port; + + _port.operation = PORT_OP_READ; + _port.addr = idx; + _port.size = 2; + if (ioctl(dhahelper_fd, DHAHELPER_PORT, &_port) == 0) + return _port.value; + } + return inw(idx); +} + +unsigned INPORT32(unsigned idx) +{ + if (dhahelper_fd > 0) + { + dhahelper_port_t _port; + + _port.operation = PORT_OP_READ; + _port.addr = idx; + _port.size = 4; + if (ioctl(dhahelper_fd, DHAHELPER_PORT, &_port) == 0) + return _port.value; + } + return inl(idx); +} + +void OUTPORT8(unsigned idx,unsigned char val) +{ + if (dhahelper_fd > 0) + { + dhahelper_port_t _port; + + _port.operation = PORT_OP_WRITE; + _port.addr = idx; + _port.size = 1; + _port.value = val; + if (ioctl(dhahelper_fd, DHAHELPER_PORT, &_port) == 0) + return; + } + else outb(idx,val); +} + +void OUTPORT16(unsigned idx,unsigned short val) +{ + if (dhahelper_fd > 0) + { + dhahelper_port_t _port; + + _port.operation = PORT_OP_WRITE; + _port.addr = idx; + _port.size = 2; + _port.value = val; + if (ioctl(dhahelper_fd, DHAHELPER_PORT, &_port) == 0) + return; + } + else outw(idx,val); +} + +void OUTPORT32(unsigned idx,unsigned val) +{ + if (dhahelper_fd > 0) + { + dhahelper_port_t _port; + + _port.operation = PORT_OP_WRITE; + _port.addr = idx; + _port.size = 4; + _port.value = val; + if (ioctl(dhahelper_fd, DHAHELPER_PORT, &_port) == 0) + return; + } + else outl(idx,val); +} + diff --git a/contrib/libdha/sysdep/AsmMacros_alpha.h b/contrib/libdha/sysdep/AsmMacros_alpha.h new file mode 100644 index 000000000..59da53891 --- /dev/null +++ b/contrib/libdha/sysdep/AsmMacros_alpha.h @@ -0,0 +1,26 @@ +/* + This file is based on: + $XFree86: xc/programs/Xserver/hw/xfree86/drivers/chips/util/AsmMacros.h,v 1.1 2001/11/16 21:13:34 tsi Exp $ + Modified for readability by Nick Kurshev +*/ + +#ifndef __ASM_MACROS_ALPHA_H +#define __ASM_MACROS_ALPHA_H +#if defined (linux) +#include <sys/io.h> +#elif defined (__FreeBSD__) +#include <sys/types.h> +extern void outb(u_int32_t port, u_int8_t val); +extern void outw(u_int32_t port, u_int16_t val); +extern void outl(u_int32_t port, u_int32_t val); +extern u_int8_t inb(u_int32_t port); +extern u_int16_t inw(u_int32_t port); +extern u_int32_t inl(u_int32_t port); +#else +#include "sysdep/AsmMacros_generic.h" +#endif + +#define intr_disable() +#define intr_enable() + +#endif diff --git a/contrib/libdha/sysdep/AsmMacros_arm32.h b/contrib/libdha/sysdep/AsmMacros_arm32.h new file mode 100644 index 000000000..e618d32ee --- /dev/null +++ b/contrib/libdha/sysdep/AsmMacros_arm32.h @@ -0,0 +1,50 @@ +/* + This file is based on: + $XFree86: xc/programs/Xserver/hw/xfree86/drivers/chips/util/AsmMacros.h,v 1.1 2001/11/16 21:13:34 tsi Exp $ + Modified for readability by Nick Kurshev +*/ + +#ifndef __ASM_MACROS_ARM32_H +#define __ASM_MACROS_ARM32_H +unsigned int IOPortBase; /* Memory mapped I/O port area */ + +static __inline__ void outb(short port,char val) +{ + if ((unsigned short)port >= 0x400) return; + *(volatile unsigned char*)(((unsigned short)(port))+IOPortBase) = val; +} + +static __inline__ void outw(short port,short val) +{ + if ((unsigned short)port >= 0x400) return; + *(volatile unsigned short*)(((unsigned short)(port))+IOPortBase) = val; +} + +static __inline__ void outl(short port,int val) +{ + if ((unsigned short)port >= 0x400) return; + *(volatile unsigned long*)(((unsigned short)(port))+IOPortBase) = val; +} + +static __inline__ unsigned int inb(short port) +{ + if ((unsigned short)port >= 0x400) return((unsigned int)-1); + return(*(volatile unsigned char*)(((unsigned short)(port))+IOPortBase)); +} + +static __inline__ unsigned int inw(short port) +{ + if ((unsigned short)port >= 0x400) return((unsigned int)-1); + return(*(volatile unsigned short*)(((unsigned short)(port))+IOPortBase)); +} + +static __inline__ unsigned int inl(short port) +{ + if ((unsigned short)port >= 0x400) return((unsigned int)-1); + return(*(volatile unsigned long*)(((unsigned short)(port))+IOPortBase)); +} + +#define intr_disable() +#define intr_enable() + +#endif diff --git a/contrib/libdha/sysdep/AsmMacros_generic.h b/contrib/libdha/sysdep/AsmMacros_generic.h new file mode 100644 index 000000000..183f831e5 --- /dev/null +++ b/contrib/libdha/sysdep/AsmMacros_generic.h @@ -0,0 +1,56 @@ +/* + Generic stuff to compile VIDIX only on any system (SCRATCH) +*/ + +#ifndef __ASM_MACROS_GENERIC_H +#define __ASM_MACROS_GENERIC_H + +#warning This stuff is not ported on your system + +static __inline__ void outb(short port,char val) +{ + printf("outb: generic function call\n"); + return; +} + +static __inline__ void outw(short port,short val) +{ + printf("outw: generic function call\n"); + return; +} + +static __inline__ void outl(short port,unsigned int val) +{ + printf("outl: generic function call\n"); + return; +} + +static __inline__ unsigned int inb(short port) +{ + printf("inb: generic function call\n"); + return 0; +} + +static __inline__ unsigned int inw(short port) +{ + printf("inw: generic function call\n"); + return 0; +} + +static __inline__ unsigned int inl(short port) +{ + printf("inl: generic function call\n"); + return 0; +} + +static __inline__ void intr_disable() +{ + printf("intr_disable: generic function call\n"); +} + +static __inline__ void intr_enable() +{ + printf("intr_enable: generic function call\n"); +} + +#endif diff --git a/contrib/libdha/sysdep/AsmMacros_ia64.h b/contrib/libdha/sysdep/AsmMacros_ia64.h new file mode 100644 index 000000000..7d6123f33 --- /dev/null +++ b/contrib/libdha/sysdep/AsmMacros_ia64.h @@ -0,0 +1,16 @@ +/* + This file is based on: + $XFree86: xc/programs/Xserver/hw/xfree86/drivers/chips/util/AsmMacros.h,v 1.1 2001/11/16 21:13:34 tsi Exp $ + Modified for readability by Nick Kurshev +*/ + +#ifndef __ASM_MACROS_IA64_H +#define __ASM_MACROS_IA64_H + +#if defined(linux) +#include <sys/io.h> +#else +#include "sysdep/AsmMacros_generic.h" +#endif + +#endif diff --git a/contrib/libdha/sysdep/AsmMacros_powerpc.h b/contrib/libdha/sysdep/AsmMacros_powerpc.h new file mode 100644 index 000000000..2169c96b4 --- /dev/null +++ b/contrib/libdha/sysdep/AsmMacros_powerpc.h @@ -0,0 +1,66 @@ +/* + This file is based on: + $XFree86: xc/programs/Xserver/hw/xfree86/drivers/chips/util/AsmMacros.h,v 1.1 2001/11/16 21:13:34 tsi Exp $ + Modified for readability by Nick Kurshev +*/ + +#ifndef __ASM_MACROS_POWERPC_H +#define __ASM_MACROS_POWERPC_H + +#if defined(Lynx) || defined(__OpenBSD__) + +extern unsigned char *ioBase; + +static __inline__ volatile void eieio() +{ + __asm__ __volatile__ ("eieio"); +} + +static __inline__ void outb(short port, unsigned char value) +{ + *(unsigned char *)(ioBase + port) = value; eieio(); +} + +static __inline__ void outw(short port, unsigned short value) +{ + *(unsigned short *)(ioBase + port) = value; eieio(); +} + +static __inline__ void outl(short port, unsigned short value) +{ + *(unsigned long *)(ioBase + port) = value; eieio(); +} + +static __inline__ unsigned char inb(short port) +{ + unsigned char val; + val = *((unsigned char *)(ioBase + port)); eieio(); + return(val); +} + +static __inline__ unsigned short inw(short port) +{ + unsigned short val; + val = *((unsigned short *)(ioBase + port)); eieio(); + return(val); +} + +static __inline__ unsigned long inl(short port) +{ + unsigned long val; + val = *((unsigned long *)(ioBase + port)); eieio(); + return(val); +} + +#define intr_disable() +#define intr_enable() + +#else + #ifdef linux + /*nothing*/ + #else + #include "sysdep/AsmMacros_generic.h" + #endif +#endif + +#endif diff --git a/contrib/libdha/sysdep/AsmMacros_sparc.h b/contrib/libdha/sysdep/AsmMacros_sparc.h new file mode 100644 index 000000000..f6717b4bb --- /dev/null +++ b/contrib/libdha/sysdep/AsmMacros_sparc.h @@ -0,0 +1,53 @@ +/* + This file is based on: + $XFree86: xc/programs/Xserver/hw/xfree86/drivers/chips/util/AsmMacros.h,v 1.1 2001/11/16 21:13:34 tsi Exp $ + Modified for readability by Nick Kurshev +*/ + +#ifndef __ASM_MACROS_SPARC_H +#define __ASM_MACROS_SPARC_H + +#ifndef ASI_PL +#define ASI_PL 0x88 +#endif + +static __inline__ void outb(unsigned long port, char val) +{ + __asm__ __volatile__("stba %0, [%1] %2" : : "r" (val), "r" (port), "i" (ASI_PL)); +} + +static __inline__ void outw(unsigned long port, char val) +{ + __asm__ __volatile__("stha %0, [%1] %2" : : "r" (val), "r" (port), "i" (ASI_PL)); +} + +static __inline__ void outl(unsigned long port, char val) +{ + __asm__ __volatile__("sta %0, [%1] %2" : : "r" (val), "r" (port), "i" (ASI_PL)); +} + +static __inline__ unsigned int inb(unsigned long port) +{ + unsigned char ret; + __asm__ __volatile__("lduba [%1] %2, %0" : "=r" (ret) : "r" (port), "i" (ASI_PL)); + return ret; +} + +static __inline__ unsigned int inw(unsigned long port) +{ + unsigned char ret; + __asm__ __volatile__("lduha [%1] %2, %0" : "=r" (ret) : "r" (port), "i" (ASI_PL)); + return ret; +} + +static __inline__ unsigned int inl(unsigned long port) +{ + unsigned char ret; + __asm__ __volatile__("lda [%1] %2, %0" : "=r" (ret) : "r" (port), "i" (ASI_PL)); + return ret; +} + +#define intr_disable() +#define intr_enable() + +#endif diff --git a/contrib/libdha/sysdep/AsmMacros_x86.h b/contrib/libdha/sysdep/AsmMacros_x86.h new file mode 100644 index 000000000..97dcaae16 --- /dev/null +++ b/contrib/libdha/sysdep/AsmMacros_x86.h @@ -0,0 +1,72 @@ +/* + This file is based on: + $XFree86: xc/programs/Xserver/hw/xfree86/drivers/chips/util/AsmMacros.h,v 1.1 2001/11/16 21:13:34 tsi Exp $ + Modified for readability by Nick Kurshev +*/ + +#ifndef __ASM_MACROS_X86_H +#define __ASM_MACROS_X86_H + +#if defined (WINNT) +#include "sysdep/AsmMacros_generic.h" +#else + +#include "config.h" + +static __inline__ void outb(short port,char val) +{ + __asm__ __volatile__("outb %0,%1" : :"a" (val), "d" (port)); + return; +} + +static __inline__ void outw(short port,short val) +{ + __asm__ __volatile__("outw %0,%1" : :"a" (val), "d" (port)); + return; +} + +static __inline__ void outl(short port,unsigned int val) +{ + __asm__ __volatile__("outl %0,%1" : :"a" (val), "d" (port)); + return; +} + +static __inline__ unsigned int inb(short port) +{ + unsigned char ret; + __asm__ __volatile__("inb %1,%0" : + "=a" (ret) : + "d" (port)); + return ret; +} + +static __inline__ unsigned int inw(short port) +{ + unsigned short ret; + __asm__ __volatile__("inw %1,%0" : + "=a" (ret) : + "d" (port)); + return ret; +} + +static __inline__ unsigned int inl(short port) +{ + unsigned int ret; + __asm__ __volatile__("inl %1,%0" : + "=a" (ret) : + "d" (port)); + return ret; +} + +static __inline__ void intr_disable() +{ + __asm__ __volatile__("cli"); +} + +static __inline__ void intr_enable() +{ + __asm__ __volatile__("sti"); +} + +#endif +#endif diff --git a/contrib/libdha/sysdep/Makefile.am b/contrib/libdha/sysdep/Makefile.am new file mode 100644 index 000000000..807572c39 --- /dev/null +++ b/contrib/libdha/sysdep/Makefile.am @@ -0,0 +1,35 @@ +include $(top_srcdir)/misc/Makefile.common + +EXTRA_DIST = \ + libdha_os2.c \ + libdha_win32.c \ + pci_386bsd.c \ + pci_alpha.c \ + pci_arm32.c \ + pci_bsdi.c \ + pci_freebsd.c \ + pci_generic_cpu.c \ + pci_generic_os.c \ + pci_ia64.c \ + pci_isc.c \ + pci_linux.c \ + pci_lynx.c \ + pci_mach386.c \ + pci_netbsd.c \ + pci_openbsd.c \ + pci_os2.c \ + pci_powerpc.c \ + pci_sco.c \ + pci_sparc.c \ + pci_svr4.c \ + pci_win32.c \ + pci_x86.c + +noinst_HEADERS = \ + AsmMacros_alpha.h \ + AsmMacros_arm32.h \ + AsmMacros_generic.h \ + AsmMacros_ia64.h \ + AsmMacros_powerpc.h \ + AsmMacros_sparc.h \ + AsmMacros_x86.h diff --git a/contrib/libdha/sysdep/libdha_os2.c b/contrib/libdha/sysdep/libdha_os2.c new file mode 100644 index 000000000..041f6be71 --- /dev/null +++ b/contrib/libdha/sysdep/libdha_os2.c @@ -0,0 +1,161 @@ +/* $XFree86: xc/programs/Xserver/hw/xfree86/os-support/os2/os2_video.c,v 3.14 2000/10/28 01:42:28 mvojkovi Exp $ */ +/* Modified for libdha by Nick Kurshev. */ +/* + * (c) Copyright 1994,1999 by Holger Veit + * <Holger.Veit@gmd.de> + * Modified 1996 by Sebastien Marineau <marineau@genie.uottawa.ca> + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * HOLGER VEIT BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF + * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + * + * Except as contained in this notice, the name of Holger Veit shall not be + * used in advertising or otherwise to promote the sale, use or other dealings + * in this Software without prior written authorization from Holger Veit. + * + */ +/* $XConsortium: os2_video.c /main/8 1996/10/27 11:49:02 kaleb $ */ + +#define INCL_DOSFILEMGR +#include "os2.h" + +/***************************************************************************/ +/* Video Memory Mapping helper functions */ +/***************************************************************************/ + +/* This section uses the xf86sup.sys driver developed for xfree86. + * The driver allows mapping of physical memory + * You must install it with a line DEVICE=path\xf86sup.sys in config.sys. + */ + +static HFILE mapdev = -1; +static ULONG stored_virt_addr; +static char* mappath = "\\DEV\\PMAP$"; +static HFILE open_mmap() +{ + APIRET rc; + ULONG action; + + if (mapdev != -1) + return mapdev; + + rc = DosOpen((PSZ)mappath, (PHFILE)&mapdev, (PULONG)&action, + (ULONG)0, FILE_SYSTEM, FILE_OPEN, + OPEN_SHARE_DENYNONE|OPEN_FLAGS_NOINHERIT|OPEN_ACCESS_READONLY, + (ULONG)0); + if (rc!=0) + mapdev = -1; + return mapdev; +} + +static void close_mmap() +{ + if (mapdev != -1) + DosClose(mapdev); + mapdev = -1; +} + +/* this structure is used as a parameter packet for the direct access + * ioctl of pmap$ + */ + +/* Changed here for structure of driver PMAP$ */ + +typedef struct{ + ULONG addr; + ULONG size; +} DIOParPkt; + +/* This is the data packet for the mapping function */ + +typedef struct { + ULONG addr; + USHORT sel; +} DIODtaPkt; + +/***************************************************************************/ +/* Video Memory Mapping section */ +/***************************************************************************/ + +static long callcount = 0L; + +/* ARGSUSED */ +void * map_phys_mem(unsigned long base, unsigned long size) +{ + DIOParPkt par; + ULONG plen; + DIODtaPkt dta; + ULONG dlen; + static BOOL ErrRedir = FALSE; + APIRET rc; + + par.addr = (ULONG)base; + par.size = (ULONG)size; + plen = sizeof(par); + dlen = sizeof(dta); + + open_mmap(); + if (mapdev == -1) + { + perror("libdha: device xf86sup.sys is not installed"); + exit(1); + } + if ((rc=DosDevIOCtl(mapdev, (ULONG)0x76, (ULONG)0x44, + (PVOID)&par, (ULONG)plen, (PULONG)&plen, + (PVOID)&dta, (ULONG)dlen, (PULONG)&dlen)) == 0) { + if (dlen==sizeof(dta)) { + callcount++; + return (void *)dta.addr; + } + /*else fail*/ + } + return (void *)-1; +} + +/* ARGSUSED */ +void unmap_phys_mem(void * base, unsigned long size) +{ + DIOParPkt par; + ULONG plen,vmaddr; + +/* We need here the VIRTADDR for unmapping, not the physical address */ +/* This should be taken care of either here by keeping track of allocated */ +/* pointers, but this is also already done in the driver... Thus it would */ +/* be a waste to do this tracking twice. Can this be changed when the fn. */ +/* is called? This would require tracking this function in all servers, */ +/* and changing it appropriately to call this with the virtual adress */ +/* If the above mapping function is only called once, then we can store */ +/* the virtual adress and use it here.... */ + + par.addr = (ULONG)base; + par.size = 0xffffffff; /* This is the virtual address parameter. Set this to ignore */ + plen = sizeof(par); + + if (mapdev != -1) + { + DosDevIOCtl(mapdev, (ULONG)0x76, (ULONG)0x46, + (PVOID)&par, (ULONG)plen, (PULONG)&plen, + &vmaddr, sizeof(ULONG), &plen); + callcount--; + } +/* Now if more than one region has been allocated and we close the driver, + * the other pointers will immediately become invalid. We avoid closing + * driver for now, but this should be fixed for server exit + */ + + if(!callcount) close_mmap(); +} diff --git a/contrib/libdha/sysdep/libdha_win32.c b/contrib/libdha/sysdep/libdha_win32.c new file mode 100644 index 000000000..75c5dfb94 --- /dev/null +++ b/contrib/libdha/sysdep/libdha_win32.c @@ -0,0 +1,70 @@ +/* + MAPDEV.h - include file for VxD MAPDEV + Copyright (c) 1996 Vireo Software, Inc. + Modified for libdha by Nick Kurshev. +*/ + +#include <windows.h> + +/* + This is the request structure that applications use + to request services from the MAPDEV VxD. +*/ + +typedef struct _MapDevRequest +{ + DWORD mdr_ServiceID; /* supplied by caller */ + LPVOID mdr_PhysicalAddress; /* supplied by caller */ + DWORD mdr_SizeInBytes; /* supplied by caller */ + LPVOID mdr_LinearAddress; /* returned by VxD */ + WORD mdr_Selector; /* returned if 16-bit caller */ + WORD mdr_Status; /* MDR_xxxx code below */ +} MAPDEVREQUEST, *PMAPDEVREQUEST; + +#define MDR_SERVICE_MAP CTL_CODE(FILE_DEVICE_UNKNOWN, 1, METHOD_NEITHER, FILE_ANY_ACCESS) +#define MDR_SERVICE_UNMAP CTL_CODE(FILE_DEVICE_UNKNOWN, 2, METHOD_NEITHER, FILE_ANY_ACCESS) + +#define MDR_STATUS_SUCCESS 1 +#define MDR_STATUS_ERROR 0 +/*#include "winioctl.h"*/ +#define FILE_DEVICE_UNKNOWN 0x00000022 +#define METHOD_NEITHER 3 +#define FILE_ANY_ACCESS 0 +#define CTL_CODE( DeviceType, Function, Method, Access ) ( \ + ((DeviceType)<<16) | ((Access)<<14) | ((Function)<<2) | (Method) ) + +/* Memory Map a piece of Real Memory */ +void *map_phys_mem(unsigned base, unsigned size) { + + HANDLE hDevice ; + PVOID inBuf[1] ; /* buffer for struct pointer to VxD */ + DWORD RetInfo[2] ; /* buffer to receive data from VxD */ + DWORD cbBytesReturned ; /* count of bytes returned from VxD */ + MAPDEVREQUEST req ; /* map device request structure */ + DWORD *pNicstar, Status, Time ; int i ; char *endptr ; + const PCHAR VxDName = "\\\\.\\MAPDEV.VXD" ; + const PCHAR VxDNameAlreadyLoaded = "\\\\.\\MAPDEV" ; + + hDevice = CreateFile(VxDName, 0,0,0, + CREATE_NEW, FILE_FLAG_DELETE_ON_CLOSE, 0) ; + if (hDevice == INVALID_HANDLE_VALUE) + hDevice = CreateFile(VxDNameAlreadyLoaded, 0,0,0, + CREATE_NEW, FILE_FLAG_DELETE_ON_CLOSE, 0) ; + if (hDevice == INVALID_HANDLE_VALUE) { + fprintf(stderr, "Cannot open driver, error=%08lx\n", GetLastError()) ; + exit(1) ; } + + req.mdr_ServiceID = MDR_SERVICE_MAP ; + req.mdr_PhysicalAddress = (PVOID)base ; + req.mdr_SizeInBytes = size ; + inBuf[0] = &req ; + + if ( ! DeviceIoControl(hDevice, MDR_SERVICE_MAP, inBuf, sizeof(PVOID), + NULL, 0, &cbBytesReturned, NULL) ) { + fprintf(stderr, "Failed to map device\n") ; exit(1) ; } + + return (void*)req.mdr_LinearAddress ; +} + +void unmap_phys_mem(void *ptr, unsigned size) { } + diff --git a/contrib/libdha/sysdep/pci_386bsd.c b/contrib/libdha/sysdep/pci_386bsd.c new file mode 100644 index 000000000..d00ecb078 --- /dev/null +++ b/contrib/libdha/sysdep/pci_386bsd.c @@ -0,0 +1,38 @@ +/* + This file is based on: + $XFree86: xc/programs/Xserver/hw/xfree86/etc/scanpci.c,v 3.34.2.17 1998/11/10 11:55:40 dawes Exp $ + Modified for readability by Nick Kurshev +*/ +#include <errno.h> +#include <sys/file.h> +#include <machine/console.h> +#ifndef GCCUSESGAS +#define GCCUSESGAS +#endif + +static int io_fd; + +static __inline__ int enable_os_io(void) +{ + io_fd = -1 ; + if ((io_fd = open("/dev/console", O_RDWR, 0)) < 0) { + perror("/dev/console"); + return(errno); + } + if (ioctl(io_fd, KDENABIO, 0) < 0) { + perror("ioctl(KDENABIO)"); + return(errno); + } + return(0); +} + +static __inline__ int disable_os_io(void) +{ + if (ioctl(io_fd, KDDISABIO, 0) < 0) { + perror("ioctl(KDDISABIO)"); + close(io_fd); + return(errno); + } + close(io_fd); + return(0); +} diff --git a/contrib/libdha/sysdep/pci_alpha.c b/contrib/libdha/sysdep/pci_alpha.c new file mode 100644 index 000000000..74c3eb687 --- /dev/null +++ b/contrib/libdha/sysdep/pci_alpha.c @@ -0,0 +1,80 @@ +/* + This file is based on: + $XFree86: xc/programs/Xserver/hw/xfree86/etc/scanpci.c,v 3.34.2.17 1998/11/10 11:55:40 dawes Exp $ + Modified for readability by Nick Kurshev +*/ + +static int pci_config_type( void ) { return 1; } + +static int pci_get_vendor( + unsigned char bus, + unsigned char dev, + int func) +{ + unsigned long retval; + pciconfig_read(bus, dev<<3, PCI_ID_REG, 4, &retval); + return retval; +} + +static long pci_config_read_long( + unsigned char bus, + unsigned char dev, + int func, + unsigned cmd) +{ + unsigned long retval; + pciconfig_read(bus, dev<<3, cmd, 4, &retval); + return retval; +} + +static long pci_config_read_word( + unsigned char bus, + unsigned char dev, + int func, + unsigned cmd) +{ + unsigned long retval; + pciconfig_read(bus, dev<<3, cmd, 2, &retval); + return retval; +} + +static long pci_config_read_byte( + unsigned char bus, + unsigned char dev, + int func, + unsigned cmd) +{ + unsigned long retval; + pciconfig_read(bus, dev<<3, cmd, 1, &retval); + return retval; +} + +static void pci_config_write_long( + unsigned char bus, + unsigned char dev, + int func, + unsigned cmd, + long val) +{ + pciconfig_write(bus, dev<<3, cmd, 4, val); +} + +static void pci_config_write_word( + unsigned char bus, + unsigned char dev, + int func, + unsigned cmd, + long val) +{ + pciconfig_write(bus, dev<<3, cmd, 2, val); +} + +static void pci_config_write_byte( + unsigned char bus, + unsigned char dev, + int func, + unsigned cmd, + long val) +{ + pciconfig_write(bus, dev<<3, cmd, 1, val); +} diff --git a/contrib/libdha/sysdep/pci_arm32.c b/contrib/libdha/sysdep/pci_arm32.c new file mode 100644 index 000000000..6920b615e --- /dev/null +++ b/contrib/libdha/sysdep/pci_arm32.c @@ -0,0 +1,123 @@ +/* + This file is based on: + $XFree86: xc/programs/Xserver/hw/xfree86/etc/scanpci.c,v 3.34.2.17 1998/11/10 11:55:40 dawes Exp $ + Modified for readability by Nick Kurshev +*/ + +static int pci_config_type( void ) +{ + unsigned long tmplong1, tmplong2; + unsigned char tmp1, tmp2; + int retval; + retval = 0; + + OUTPORT8(PCI_MODE2_ENABLE_REG, 0x00); + OUTPORT8(PCI_MODE2_FORWARD_REG, 0x00); + tmp1 = INPORT8(PCI_MODE2_ENABLE_REG); + tmp2 = INPORT8(PCI_MODE2_FORWARD_REG); + if ((tmp1 == 0x00) && (tmp2 == 0x00)) { + retval = 2; + /*printf("PCI says configuration type 2\n");*/ + } else { + tmplong1 = INPORT32(PCI_MODE1_ADDRESS_REG); + OUTPORT32(PCI_MODE1_ADDRESS_REG, PCI_EN); + tmplong2 = INPORT32(PCI_MODE1_ADDRESS_REG); + OUTPORT32(PCI_MODE1_ADDRESS_REG, tmplong1); + if (tmplong2 == PCI_EN) { + retval = 1; + /*printf("PCI says configuration type 1\n");*/ + } else { + /*printf("No PCI !\n");*/ + disable_app_io(); + /*exit(1);*/ + retval = 0xFFFF; + } + } + return retval; +} + +static int pci_get_vendor( + unsigned char bus, + unsigned char dev, + int func) +{ + unsigned long config_cmd; + config_cmd = PCI_EN | (bus<<16) | (dev<<11) | (func<<8); + OUTPORT32(PCI_MODE1_ADDRESS_REG, config_cmd); + return INPORT32(PCI_MODE1_DATA_REG); +} + +static long pci_config_read_long( + unsigned char bus, + unsigned char dev, + int func, + unsigned cmd) +{ + unsigned long config_cmd; + config_cmd = PCI_EN | (bus<<16) | (dev<<11) | (func<<8); + OUTPORT32(PCI_MODE1_ADDRESS_REG, config_cmd | cmd); + return INPORT32(PCI_MODE1_DATA_REG); +} + +static long pci_config_read_word( + unsigned char bus, + unsigned char dev, + int func, + unsigned cmd) +{ + unsigned long config_cmd; + config_cmd = PCI_EN | (bus<<16) | (dev<<11) | (func<<8); + OUTPORT32(PCI_MODE1_ADDRESS_REG, config_cmd | cmd); + return INPORT16(PCI_MODE1_DATA_REG); +} + +static long pci_config_read_byte( + unsigned char bus, + unsigned char dev, + int func, + unsigned cmd) +{ + unsigned long config_cmd; + config_cmd = PCI_EN | (bus<<16) | (dev<<11) | (func<<8); + OUTPORT32(PCI_MODE1_ADDRESS_REG, config_cmd | cmd); + return INPORT8(PCI_MODE1_DATA_REG); +} + +static void pci_config_write_long( + unsigned char bus, + unsigned char dev, + int func, + unsigned cmd, + long val) +{ + unsigned long config_cmd; + config_cmd = PCI_EN | (bus<<16) | (dev<<11) | (func<<8); + OUTPORT32(PCI_MODE1_ADDRESS_REG, config_cmd | cmd); + OUTPORT32(PCI_MODE1_DATA_REG,val); +} + +static void pci_config_write_word( + unsigned char bus, + unsigned char dev, + int func, + unsigned cmd, + unsigned val) +{ + unsigned long config_cmd; + config_cmd = PCI_EN | (bus<<16) | (dev<<11) | (func<<8); + OUTPORT32(PCI_MODE1_ADDRESS_REG, config_cmd | cmd); + OUTPORT16(PCI_MODE1_DATA_REG,val); +} + +static void pci_config_write_byte( + unsigned char bus, + unsigned char dev, + int func, + unsigned cmd, + long val) +{ + unsigned long config_cmd; + config_cmd = PCI_EN | (bus<<16) | (dev<<11) | (func<<8); + OUTPORT32(PCI_MODE1_ADDRESS_REG, config_cmd | cmd); + OUTPORT8(PCI_MODE1_DATA_REG,val); +} diff --git a/contrib/libdha/sysdep/pci_bsdi.c b/contrib/libdha/sysdep/pci_bsdi.c new file mode 100644 index 000000000..b6b142054 --- /dev/null +++ b/contrib/libdha/sysdep/pci_bsdi.c @@ -0,0 +1,39 @@ +/* + This file is based on: + $XFree86: xc/programs/Xserver/hw/xfree86/etc/scanpci.c,v 3.34.2.17 1998/11/10 11:55:40 dawes Exp $ + Modified for readability by Nick Kurshev +*/ +#include <errno.h> +#include <sys/file.h> +#include <sys/ioctl.h> +#include <i386/isa/pcconsioctl.h> +#ifndef GCCUSESGAS +#define GCCUSESGAS +#endif + +static int io_fd; + +static __inline__ int enable_os_io(void) +{ + io_fd = -1 ; + if ((io_fd = open("/dev/console", O_RDWR, 0)) < 0) { + perror("/dev/console"); + return(errno); + } + if (ioctl(io_fd, PCCONENABIOPL, 0) < 0) { + perror("ioctl(PCCONENABIOPL)"); + return(errno); + } + return(0); +} + +static __inline__ int disable_os_io(void) +{ + if (ioctl(io_fd, PCCONDISABIOPL, 0) < 0) { + perror("ioctl(PCCONDISABIOPL)"); + close(io_fd); + return(errno); + } + close(io_fd); + return(0); +} diff --git a/contrib/libdha/sysdep/pci_freebsd.c b/contrib/libdha/sysdep/pci_freebsd.c new file mode 100644 index 000000000..9ad4b15f2 --- /dev/null +++ b/contrib/libdha/sysdep/pci_freebsd.c @@ -0,0 +1,41 @@ +/* + This file is based on: + $XFree86: xc/programs/Xserver/hw/xfree86/etc/scanpci.c,v 3.34.2.17 1998/11/10 11:55:40 dawes Exp $ + Modified for readability by Nick Kurshev +*/ +#include <errno.h> +#include <sys/file.h> +/* machine/console.h seems to be outdated by recent FreeBSD * + * however pcvt_ioctl.h seems to exist for very long time */ +/* #include <machine/console.h>*/ +#include <machine/pcvt_ioctl.h> +#ifndef GCCUSESGAS +#define GCCUSESGAS +#endif + +static int io_fd; + +static __inline__ int enable_os_io(void) +{ + io_fd = -1 ; + if ((io_fd = open("/dev/console", O_RDWR, 0)) < 0) { + perror("/dev/console"); + return(errno); + } + if (ioctl(io_fd, KDENABIO, 0) < 0) { + perror("ioctl(KDENABIO)"); + return(errno); + } + return(0); +} + +static __inline__ int disable_os_io(void) +{ + if (ioctl(io_fd, KDDISABIO, 0) < 0) { + perror("ioctl(KDDISABIO)"); + close(io_fd); + return(errno); + } + close(io_fd); + return(0); +} diff --git a/contrib/libdha/sysdep/pci_generic_cpu.c b/contrib/libdha/sysdep/pci_generic_cpu.c new file mode 100644 index 000000000..729d48b5a --- /dev/null +++ b/contrib/libdha/sysdep/pci_generic_cpu.c @@ -0,0 +1,79 @@ +/* + Generic stuff to compile VIDIX only on any system (SCRATCH) +*/ +#warning This stuff is not ported on your system + +static int pci_config_type( void ) +{ + printf("pci_config_type: generic function call\n"); + return 0xFFFF; +} + +static int pci_get_vendor( + unsigned char bus, + unsigned char dev, + int func) +{ + printf("pci_get_vendor: generic function call\n"); + return 0; +} + +static long pci_config_read_long( + unsigned char bus, + unsigned char dev, + int func, + unsigned cmd) +{ + printf("pci_config_read_long: generic function call\n"); + return 0; +} + +static long pci_config_read_word( + unsigned char bus, + unsigned char dev, + int func, + unsigned cmd) +{ + printf("pci_config_read_word: generic function call\n"); + return 0; +} + +static long pci_config_read_byte( + unsigned char bus, + unsigned char dev, + int func, + unsigned cmd) +{ + printf("pci_config_read_byte: generic function call\n"); + return 0; +} + +static void pci_config_write_long( + unsigned char bus, + unsigned char dev, + int func, + unsigned cmd, + long val) +{ + printf("pci_config_write_long: generic function call\n"); +} + +static void pci_config_write_word( + unsigned char bus, + unsigned char dev, + int func, + unsigned cmd, + long val) +{ + printf("pci_config_write_word: generic function call\n"); +} + +static void pci_config_write_byte( + unsigned char bus, + unsigned char dev, + int func, + unsigned cmd, + long val) +{ + printf("pci_config_write_byte: generic function call\n"); +} diff --git a/contrib/libdha/sysdep/pci_generic_os.c b/contrib/libdha/sysdep/pci_generic_os.c new file mode 100644 index 000000000..8855bb4ba --- /dev/null +++ b/contrib/libdha/sysdep/pci_generic_os.c @@ -0,0 +1,15 @@ +/* + Generic stuff to compile VIDIX only on any system (SCRATCH) +*/ +#warn This stuff is not ported on yur system +static __inline__ int enable_os_io(void) +{ + printf("enable_os_io: generic function call\n"); + return 0; +} + +static __inline__ int disable_os_io(void) +{ + printf("disable_os_io: generic function call\n"); + return 0; +} diff --git a/contrib/libdha/sysdep/pci_ia64.c b/contrib/libdha/sysdep/pci_ia64.c new file mode 100644 index 000000000..ef2074ab2 --- /dev/null +++ b/contrib/libdha/sysdep/pci_ia64.c @@ -0,0 +1,123 @@ +/* + This file is based on: + $XFree86: xc/programs/Xserver/hw/xfree86/etc/scanpci.c,v 3.34.2.17 1998/11/10 11:55:40 dawes Exp $ + Modified for readability by Nick Kurshev +*/ + +static int pci_config_type( void ) +{ + unsigned long tmplong1, tmplong2; + unsigned char tmp1, tmp2; + int retval; + retval = 0; + + OUTPORT8(PCI_MODE2_ENABLE_REG, 0x00); + OUTPORT8(PCI_MODE2_FORWARD_REG, 0x00); + tmp1 = INPORT8(PCI_MODE2_ENABLE_REG); + tmp2 = INPORT8(PCI_MODE2_FORWARD_REG); + if ((tmp1 == 0x00) && (tmp2 == 0x00)) { + retval = 2; + /*printf("PCI says configuration type 2\n");*/ + } else { + tmplong1 = INPORT32(PCI_MODE1_ADDRESS_REG); + OUTPORT32(PCI_MODE1_ADDRESS_REG, PCI_EN); + tmplong2 = INPORT32(PCI_MODE1_ADDRESS_REG); + OUTPORT32(PCI_MODE1_ADDRESS_REG, tmplong1); + if (tmplong2 == PCI_EN) { + retval = 1; + /*printf("PCI says configuration type 1\n");*/ + } else { + /*printf("No PCI !\n");*/ + disable_app_io(); + /*exit(1);*/ + retval = 0xFFFF; + } + } + return retval; +} + +static int pci_get_vendor( + unsigned char bus, + unsigned char dev, + int func) +{ + unsigned long config_cmd; + config_cmd = PCI_EN | (bus<<16) | (dev<<11) | (func<<8); + OUTPORT32(PCI_MODE1_ADDRESS_REG, config_cmd); + return INPORT32(PCI_MODE1_DATA_REG); +} + +static long pci_config_read_long( + unsigned char bus, + unsigned char dev, + int func, + unsigned cmd) +{ + unsigned long config_cmd; + config_cmd = PCI_EN | (bus<<16) | (dev<<11) | (func<<8); + OUTPORT32(PCI_MODE1_ADDRESS_REG, config_cmd | cmd); + return INPORT32(PCI_MODE1_DATA_REG); +} + +static long pci_config_read_word( + unsigned char bus, + unsigned char dev, + int func, + unsigned cmd) +{ + unsigned long config_cmd; + config_cmd = PCI_EN | (bus<<16) | (dev<<11) | (func<<8); + OUTPORT32(PCI_MODE1_ADDRESS_REG, config_cmd | cmd); + return INPORT16(PCI_MODE1_DATA_REG); +} + +static long pci_config_read_byte( + unsigned char bus, + unsigned char dev, + int func, + unsigned cmd) +{ + unsigned long config_cmd; + config_cmd = PCI_EN | (bus<<16) | (dev<<11) | (func<<8); + OUTPORT32(PCI_MODE1_ADDRESS_REG, config_cmd | cmd); + return INPORT8(PCI_MODE1_DATA_REG); +} + +static void pci_config_write_long( + unsigned char bus, + unsigned char dev, + int func, + unsigned cmd, + long val) +{ + unsigned long config_cmd; + config_cmd = PCI_EN | (bus<<16) | (dev<<11) | (func<<8); + OUTPORT32(PCI_MODE1_ADDRESS_REG, config_cmd | cmd); + OUTPORT32(PCI_MODE1_DATA_REG,val); +} + +static void pci_config_write_word( + unsigned char bus, + unsigned char dev, + int func, + unsigned cmd, + long val) +{ + unsigned long config_cmd; + config_cmd = PCI_EN | (bus<<16) | (dev<<11) | (func<<8); + OUTPORT32(PCI_MODE1_ADDRESS_REG, config_cmd | cmd); + OUTPORT16(PCI_MODE1_DATA_REG,val); +} + +static void pci_config_write_byte( + unsigned char bus, + unsigned char dev, + int func, + unsigned cmd, + long val) +{ + unsigned long config_cmd; + config_cmd = PCI_EN | (bus<<16) | (dev<<11) | (func<<8); + OUTPORT32(PCI_MODE1_ADDRESS_REG, config_cmd | cmd); + OUTPORT8(PCI_MODE1_DATA_REG,val); +} diff --git a/contrib/libdha/sysdep/pci_isc.c b/contrib/libdha/sysdep/pci_isc.c new file mode 100644 index 000000000..5b5a59182 --- /dev/null +++ b/contrib/libdha/sysdep/pci_isc.c @@ -0,0 +1,32 @@ +/* + This file is based on: + $XFree86: xc/programs/Xserver/hw/xfree86/etc/scanpci.c,v 3.34.2.17 1998/11/10 11:55:40 dawes Exp $ + Modified for readability by Nick Kurshev +*/ +#include <sys/param.h> +#include <sys/immu.h> +#include <sys/region.h> +#include <sys/proc.h> +#include <sys/tss.h> +#include <sys/sysi86.h> +#include <sys/v86.h> + +static __inline__ int enable_os_io(void) +{ +#if defined(SI86IOPL) + sysi86(SI86IOPL, 3); +#else + sysi86(SI86V86, V86SC_IOPL, PS_IOPL); +#endif + return(0); +} + +static __inline__ int disable_os_io(void) +{ +#if defined(SI86IOPL) + sysi86(SI86IOPL, 0); +#else + sysi86(SI86V86, V86SC_IOPL, 0); +#endif + return(0); +} diff --git a/contrib/libdha/sysdep/pci_linux.c b/contrib/libdha/sysdep/pci_linux.c new file mode 100644 index 000000000..1d2116da6 --- /dev/null +++ b/contrib/libdha/sysdep/pci_linux.c @@ -0,0 +1,54 @@ +/* + This file is based on: + $XFree86: xc/programs/Xserver/hw/xfree86/etc/scanpci.c,v 3.34.2.17 1998/11/10 11:55:40 dawes Exp $ + Modified for readability by Nick Kurshev +*/ +#include <errno.h> +#ifdef __i386__ +#include <sys/perm.h> +#else +#ifndef __sparc__ +#include <sys/io.h> +#endif +#endif + +#include "config.h" + +#ifdef CONFIG_DHAHELPER +#include <fcntl.h> +int dhahelper_initialized = 0; +int dhahelper_fd = 0; +#endif + +#if defined(__sparc__) || defined(__powerpc__) +#define iopl(x) (0) +#endif + +static __inline__ int enable_os_io(void) +{ +#ifdef CONFIG_DHAHELPER + dhahelper_fd = open("/dev/dhahelper", O_RDWR); + if (dhahelper_fd > 0) + { + dhahelper_initialized = 1; + return(0); + } + dhahelper_initialized = -1; +#endif + + if (iopl(3) != 0) + return(errno); + return(0); +} + +static __inline__ int disable_os_io(void) +{ +#ifdef CONFIG_DHAHELPER + if (dhahelper_initialized == 1) + close(dhahelper_fd); + else +#endif + if (iopl(0) != 0) + return(errno); + return(0); +} diff --git a/contrib/libdha/sysdep/pci_lynx.c b/contrib/libdha/sysdep/pci_lynx.c new file mode 100644 index 000000000..b698f6308 --- /dev/null +++ b/contrib/libdha/sysdep/pci_lynx.c @@ -0,0 +1,93 @@ +/* + This file is based on: + $XFree86: xc/programs/Xserver/hw/xfree86/etc/scanpci.c,v 3.34.2.17 1998/11/10 11:55:40 dawes Exp $ + Modified for readability by Nick Kurshev +*/ + +#if defined(Lynx_22) +#ifndef GCCUSESGAS +#define GCCUSESGAS +#endif + +/* let's mimick the Linux Alpha stuff for LynxOS so we don't have + * to change too much code + */ +#include <smem.h> + +static unsigned char *pciConfBase; + +static __inline__ void enable_os_io(void) +{ + pciConfBase = (unsigned char *) smem_create("PCI-CONF", + (char *)0x80800000, 64*1024, SM_READ|SM_WRITE); + if (pciConfBase == (void *) -1) + exit(1); +} + +static __inline__ void disable_os_io(void) +{ + smem_create(NULL, (char *) pciConfBase, 0, SM_DETACH); + smem_remove("PCI-CONF"); + pciConfBase = NULL; +} + +#include <smem.h> + +static unsigned char *pciConfBase; + +static __inline__ unsigned long +static swapl(unsigned long val) +{ + unsigned char *p = (unsigned char *)&val; + return ((p[3] << 24) | (p[2] << 16) | (p[1] << 8) | (p[0] << 0)); +} + + +#define BUS(tag) (((tag)>>16)&0xff) +#define DFN(tag) (((tag)>>8)&0xff) + +#define PCIBIOS_DEVICE_NOT_FOUND 0x86 +#define PCIBIOS_SUCCESSFUL 0x00 + +static int pciconfig_read( + unsigned char bus, + unsigned char dev, + unsigned char offset, + int len, /* unused, alway 4 */ + unsigned long *val) +{ + unsigned long _val; + unsigned long *ptr; + + dev >>= 3; + if (bus || dev >= 16) { + *val = 0xFFFFFFFF; + return PCIBIOS_DEVICE_NOT_FOUND; + } else { + ptr = (unsigned long *)(pciConfBase + ((1<<dev) | offset)); + _val = swapl(*ptr); + } + *val = _val; + return PCIBIOS_SUCCESSFUL; +} + +static int pciconfig_write( + unsigned char bus, + unsigned char dev, + unsigned char offset, + int len, /* unused, alway 4 */ + unsigned long val) +{ + unsigned long _val; + unsigned long *ptr; + + dev >>= 3; + _val = swapl(val); + if (bus || dev >= 16) { + return PCIBIOS_DEVICE_NOT_FOUND; + } else { + ptr = (unsigned long *)(pciConfBase + ((1<<dev) | offset)); + *ptr = _val; + } + return PCIBIOS_SUCCESSFUL; +} diff --git a/contrib/libdha/sysdep/pci_mach386.c b/contrib/libdha/sysdep/pci_mach386.c new file mode 100644 index 000000000..31621862b --- /dev/null +++ b/contrib/libdha/sysdep/pci_mach386.c @@ -0,0 +1,25 @@ +/* + This file is based on: + $XFree86: xc/programs/Xserver/hw/xfree86/etc/scanpci.c,v 3.34.2.17 1998/11/10 11:55:40 dawes Exp $ + Modified for readability by Nick Kurshev +*/ + +#include <errno.h> + +static int io_fd; + +static __inline__ int enable_os_io(void) +{ + io_fd = -1 ; + if ((io_fd = open("/dev/iopl", O_RDWR, 0)) < 0) { + perror("/dev/iopl"); + return(errno); + } + return(0); +} + +static __inline__ int disable_os_io(void) +{ + close(io_fd); + return(0); +} diff --git a/contrib/libdha/sysdep/pci_netbsd.c b/contrib/libdha/sysdep/pci_netbsd.c new file mode 100644 index 000000000..793944beb --- /dev/null +++ b/contrib/libdha/sysdep/pci_netbsd.c @@ -0,0 +1,44 @@ +/* + This file is based on: + $XFree86: xc/programs/Xserver/hw/xfree86/etc/scanpci.c,v 3.34.2.17 1998/11/10 11:55:40 dawes Exp $ + Modified for readability by Nick Kurshev +*/ +#include <errno.h> +#include <sys/param.h> +#include <sys/file.h> +#include <machine/sysarch.h> +#ifndef GCCUSESGAS +#define GCCUSESGAS +#endif + +static int io_fd; + +static __inline__ int enable_os_io(void) +{ + io_fd = -1 ; +#if !defined(USE_I386_IOPL) + if ((io_fd = open("/dev/io", O_RDWR, 0)) < 0) { + perror("/dev/io"); + return(errno); + } +#else + if (i386_iopl(1) < 0) { + perror("i386_iopl"); + return(errno); + } +#endif /* USE_I386_IOPL */ + return(0); +} + +static __inline__ int disable_os_io(void) +{ +#if !defined(USE_I386_IOPL) + close(io_fd); +#else + if (i386_iopl(0) < 0) { + perror("i386_iopl"); + return(errno); + } +#endif /* NetBSD1_1 */ + return(0); +} diff --git a/contrib/libdha/sysdep/pci_openbsd.c b/contrib/libdha/sysdep/pci_openbsd.c new file mode 100644 index 000000000..89c85eab6 --- /dev/null +++ b/contrib/libdha/sysdep/pci_openbsd.c @@ -0,0 +1,27 @@ +/* + This file is based on: + $XFree86: xc/programs/Xserver/hw/xfree86/etc/scanpci.c,v 3.34.2.17 1998/11/10 11:55:40 dawes Exp $ + Modified for readability by Nick Kurshev +*/ + +#ifdef __i386__ + +#include <errno.h> +#include <sys/types.h> +#include <machine/sysarch.h> + +static __inline__ int enable_os_io(void) +{ + if (i386_iopl(1) < 0) { + perror("i386_iopl"); + return(errno); + } + return(0); +} + +static __inline__ int disable_os_io(void) +{ + /* Nothing to do */ + return(0); +} +#endif diff --git a/contrib/libdha/sysdep/pci_os2.c b/contrib/libdha/sysdep/pci_os2.c new file mode 100644 index 000000000..ddfc0c0ea --- /dev/null +++ b/contrib/libdha/sysdep/pci_os2.c @@ -0,0 +1,55 @@ +/* + This file is based on: + $XFree86: xc/programs/Xserver/hw/xfree86/etc/scanpci.c,v 3.34.2.17 1998/11/10 11:55:40 dawes Exp $ + Modified for readability by Nick Kurshev +*/ +#define INCL_DOSFILEMGR +#include <os2.h> + +static USHORT callgate[3] = {0,0,0}; + +static __inline__ int enable_os_io(void) +{ + HFILE hfd; + ULONG dlen,action; + APIRET rc; + static char *ioDrvPath = "/dev/fastio$"; + + if (DosOpen((PSZ)ioDrvPath, (PHFILE)&hfd, (PULONG)&action, + (ULONG)0, FILE_SYSTEM, FILE_OPEN, + OPEN_SHARE_DENYNONE|OPEN_FLAGS_NOINHERIT|OPEN_ACCESS_READONLY, + (ULONG)0) != 0) { + fprintf(stderr,"Error opening fastio$ driver...\n"); + fprintf(stderr,"Please install xf86sup.sys in config.sys!\n"); + return(42); + } + callgate[0] = callgate[1] = 0; + +/* Get callgate from driver for fast io to ports and other stuff */ + + rc = DosDevIOCtl(hfd, (ULONG)0x76, (ULONG)0x64, + NULL, 0, NULL, + (ULONG*)&callgate[2], sizeof(USHORT), &dlen); + if (rc) { + fprintf(stderr,"xf86-OS/2: EnableIOPorts failed, rc=%d, dlen=%d; emergency exit\n", + rc,dlen); + DosClose(hfd); + return(42); + } + +/* Calling callgate with function 13 sets IOPL for the program */ + + asm volatile ("movl $13,%%ebx;.byte 0xff,0x1d;.long _callgate" + : /*no outputs */ + : /*no inputs */ + : "eax","ebx","ecx","edx","cc"); + + DosClose(hfd); + return(0); +} + +static __inline__ int disable_os_io(void) +{ +/* Nothing to do */ + return(0); +} diff --git a/contrib/libdha/sysdep/pci_powerpc.c b/contrib/libdha/sysdep/pci_powerpc.c new file mode 100644 index 000000000..667b4db37 --- /dev/null +++ b/contrib/libdha/sysdep/pci_powerpc.c @@ -0,0 +1,250 @@ +/* + This file is based on: + $XFree86: xc/programs/Xserver/hw/xfree86/etc/scanpci.c,v 3.34.2.17 1998/11/10 11:55:40 dawes Exp $ + Modified for readability by Nick Kurshev +*/ + +static int pci_config_type( void ) { return 1; } +#ifdef linux +#include <fcntl.h> +#include <sys/io.h> +#include <linux/pci.h> +#include "../../bswap.h" +#endif + +#ifdef linux +static int pci_get_vendor( + unsigned char bus, + unsigned char dev, + int func) +{ + int retval; + char path[100]; + int fd; + short vendor, device; + sprintf(path,"/proc/bus/pci/%02d/%02x.0", bus, dev); + fd = open(path,O_RDONLY|O_SYNC); + if (fd == -1) { + retval=0xFFFF; + } + else if (pread(fd, &vendor, 2, PCI_VENDOR_ID) == 2 && + pread(fd, &device, 2, PCI_DEVICE_ID) == 2) { + vendor = bswap_16(vendor); + device = bswap_16(device); + retval = vendor + (device<<16); /*no worries about byte order, + all ppc are bigendian*/ + } else { + retval = 0xFFFF; + } + if (fd > 0) { + close(fd); + } + return retval; +} +#else +static int pci_get_vendor( + unsigned char bus, + unsigned char dev, + int func) +{ + int retval; + pciconfig_read(bus, dev<<3, PCI_ID_REG, 4, &retval); + return retval; +} +#endif +#ifdef linux +static long pci_config_read_long( + unsigned char bus, + unsigned char dev, + int func, + unsigned cmd) +{ + long retval; + char path[100]; + int fd; + sprintf(path,"/proc/bus/pci/%02d/%02x.0", bus, dev); + fd = open(path,O_RDONLY|O_SYNC); + if (fd == -1) { + retval=0; + } + else if (pread(fd, &retval, 4, cmd) == 4) { + retval = bswap_32(retval); + } else { + retval = 0; + } + if (fd > 0) { + close(fd); + } + return retval; +} + +static long pci_config_read_word( + unsigned char bus, + unsigned char dev, + int func, + unsigned cmd) +{ + long retval; + char path[100]; + int fd; + sprintf(path,"/proc/bus/pci/%02d/%02x.0", bus, dev); + fd = open(path,O_RDONLY|O_SYNC); + if (fd == -1) { + retval=0; + } + else if (pread(fd, &retval, 2, cmd) == 2) { + retval = bswap_16(retval); + } else { + retval = 0; + } + if (fd > 0) { + close(fd); + } + return retval; +} + +static long pci_config_read_byte( + unsigned char bus, + unsigned char dev, + int func, + unsigned cmd) +{ + long retval; + char path[100]; + int fd; + sprintf(path,"/proc/bus/pci/%02d/%02x.0", bus, dev); + fd = open(path,O_RDONLY|O_SYNC); + if (fd == -1) { + retval=0; + } + else if (pread(fd, &retval, 1, cmd) != 1) { + retval = 0; + } + if (fd > 0) { + close(fd); + } + return retval; +} + +static void pci_config_write_long( + unsigned char bus, + unsigned char dev, + int func, + unsigned cmd, + long val) +{ + char path[100]; + int fd; + val = bswap_32(val); + sprintf(path,"/proc/bus/pci/%02d/%02x.0", bus, dev); + fd = open(path,O_RDONLY|O_SYNC); + if (fd > 0) { + pwrite(fd, &val, 4, cmd); + close(fd); + } +} + +static void pci_config_write_word( + unsigned char bus, + unsigned char dev, + int func, + unsigned cmd, + long val) +{ + char path[100]; + int fd; + val = bswap_16(val); + sprintf(path,"/proc/bus/pci/%02d/%02x.0", bus, dev); + fd = open(path,O_RDONLY|O_SYNC); + if (fd > 0) { + pwrite(fd, &val, 2, cmd); + close(fd); + } +} + +static void pci_config_write_byte( + unsigned char bus, + unsigned char dev, + int func, + unsigned cmd, + long val) +{ + char path[100]; + int fd; + sprintf(path,"/proc/bus/pci/%02d/%02x.0", bus, dev); + fd = open(path,O_RDONLY|O_SYNC); + if (fd > 0) { + pwrite(fd, &val, 1, cmd); + close(fd); + } +} +#else +static long pci_config_read_long( + unsigned char bus, + unsigned char dev, + int func, + unsigned cmd) +{ + long retval; + pciconfig_read(bus, dev<<3, cmd, 4, &retval); + return retval; +} + +static long pci_config_read_word( + unsigned char bus, + unsigned char dev, + int func, + unsigned cmd) +{ + long retval; + pciconfig_read(bus, dev<<3, cmd, 2, &retval); + return retval; +} + +static long pci_config_read_byte( + unsigned char bus, + unsigned char dev, + int func, + unsigned cmd) +{ + long retval; + pciconfig_read(bus, dev<<3, cmd, 1, &retval); + return retval; +} + +static void pci_config_write_long( + unsigned char bus, + unsigned char dev, + int func, + unsigned cmd, + long val) +{ + long retval; + pciconfig_write(bus, dev<<3, cmd, 4, val); + return retval; +} + +static void pci_config_write_word( + unsigned char bus, + unsigned char dev, + int func, + unsigned cmd, + long val) +{ + long retval; + pciconfig_write(bus, dev<<3, cmd, 2, val); + return retval; +} + +static void pci_config_write_byte( + unsigned char bus, + unsigned char dev, + int func, + unsigned cmd, + long val) +{ + long retval; + pciconfig_write(bus, dev<<3, cmd, 1, val); + return retval; +} +#endif diff --git a/contrib/libdha/sysdep/pci_sco.c b/contrib/libdha/sysdep/pci_sco.c new file mode 100644 index 000000000..9cb2282ad --- /dev/null +++ b/contrib/libdha/sysdep/pci_sco.c @@ -0,0 +1,33 @@ +/* + This file is based on: + $XFree86: xc/programs/Xserver/hw/xfree86/etc/scanpci.c,v 3.34.2.17 1998/11/10 11:55:40 dawes Exp $ + Modified for readability by Nick Kurshev +*/ +#include <sys/console.h> +#include <sys/param.h> +#include <sys/immu.h> +#include <sys/region.h> +#include <sys/proc.h> +#include <sys/tss.h> +#include <sys/sysi86.h> +#include <sys/v86.h> + +static __inline__ int enable_os_io(void) +{ +#if defined(SI86IOPL) + sysi86(SI86IOPL, 3); +#else + sysi86(SI86V86, V86SC_IOPL, PS_IOPL); +#endif + return(0); +} + +static __inline__ int disable_os_io(void) +{ +#if defined(SI86IOPL) + sysi86(SI86IOPL, 0); +#else + sysi86(SI86V86, V86SC_IOPL, 0); +#endif + return(0); +} diff --git a/contrib/libdha/sysdep/pci_sparc.c b/contrib/libdha/sysdep/pci_sparc.c new file mode 100644 index 000000000..ef2074ab2 --- /dev/null +++ b/contrib/libdha/sysdep/pci_sparc.c @@ -0,0 +1,123 @@ +/* + This file is based on: + $XFree86: xc/programs/Xserver/hw/xfree86/etc/scanpci.c,v 3.34.2.17 1998/11/10 11:55:40 dawes Exp $ + Modified for readability by Nick Kurshev +*/ + +static int pci_config_type( void ) +{ + unsigned long tmplong1, tmplong2; + unsigned char tmp1, tmp2; + int retval; + retval = 0; + + OUTPORT8(PCI_MODE2_ENABLE_REG, 0x00); + OUTPORT8(PCI_MODE2_FORWARD_REG, 0x00); + tmp1 = INPORT8(PCI_MODE2_ENABLE_REG); + tmp2 = INPORT8(PCI_MODE2_FORWARD_REG); + if ((tmp1 == 0x00) && (tmp2 == 0x00)) { + retval = 2; + /*printf("PCI says configuration type 2\n");*/ + } else { + tmplong1 = INPORT32(PCI_MODE1_ADDRESS_REG); + OUTPORT32(PCI_MODE1_ADDRESS_REG, PCI_EN); + tmplong2 = INPORT32(PCI_MODE1_ADDRESS_REG); + OUTPORT32(PCI_MODE1_ADDRESS_REG, tmplong1); + if (tmplong2 == PCI_EN) { + retval = 1; + /*printf("PCI says configuration type 1\n");*/ + } else { + /*printf("No PCI !\n");*/ + disable_app_io(); + /*exit(1);*/ + retval = 0xFFFF; + } + } + return retval; +} + +static int pci_get_vendor( + unsigned char bus, + unsigned char dev, + int func) +{ + unsigned long config_cmd; + config_cmd = PCI_EN | (bus<<16) | (dev<<11) | (func<<8); + OUTPORT32(PCI_MODE1_ADDRESS_REG, config_cmd); + return INPORT32(PCI_MODE1_DATA_REG); +} + +static long pci_config_read_long( + unsigned char bus, + unsigned char dev, + int func, + unsigned cmd) +{ + unsigned long config_cmd; + config_cmd = PCI_EN | (bus<<16) | (dev<<11) | (func<<8); + OUTPORT32(PCI_MODE1_ADDRESS_REG, config_cmd | cmd); + return INPORT32(PCI_MODE1_DATA_REG); +} + +static long pci_config_read_word( + unsigned char bus, + unsigned char dev, + int func, + unsigned cmd) +{ + unsigned long config_cmd; + config_cmd = PCI_EN | (bus<<16) | (dev<<11) | (func<<8); + OUTPORT32(PCI_MODE1_ADDRESS_REG, config_cmd | cmd); + return INPORT16(PCI_MODE1_DATA_REG); +} + +static long pci_config_read_byte( + unsigned char bus, + unsigned char dev, + int func, + unsigned cmd) +{ + unsigned long config_cmd; + config_cmd = PCI_EN | (bus<<16) | (dev<<11) | (func<<8); + OUTPORT32(PCI_MODE1_ADDRESS_REG, config_cmd | cmd); + return INPORT8(PCI_MODE1_DATA_REG); +} + +static void pci_config_write_long( + unsigned char bus, + unsigned char dev, + int func, + unsigned cmd, + long val) +{ + unsigned long config_cmd; + config_cmd = PCI_EN | (bus<<16) | (dev<<11) | (func<<8); + OUTPORT32(PCI_MODE1_ADDRESS_REG, config_cmd | cmd); + OUTPORT32(PCI_MODE1_DATA_REG,val); +} + +static void pci_config_write_word( + unsigned char bus, + unsigned char dev, + int func, + unsigned cmd, + long val) +{ + unsigned long config_cmd; + config_cmd = PCI_EN | (bus<<16) | (dev<<11) | (func<<8); + OUTPORT32(PCI_MODE1_ADDRESS_REG, config_cmd | cmd); + OUTPORT16(PCI_MODE1_DATA_REG,val); +} + +static void pci_config_write_byte( + unsigned char bus, + unsigned char dev, + int func, + unsigned cmd, + long val) +{ + unsigned long config_cmd; + config_cmd = PCI_EN | (bus<<16) | (dev<<11) | (func<<8); + OUTPORT32(PCI_MODE1_ADDRESS_REG, config_cmd | cmd); + OUTPORT8(PCI_MODE1_DATA_REG,val); +} diff --git a/contrib/libdha/sysdep/pci_svr4.c b/contrib/libdha/sysdep/pci_svr4.c new file mode 100644 index 000000000..bcce5c901 --- /dev/null +++ b/contrib/libdha/sysdep/pci_svr4.c @@ -0,0 +1,42 @@ +/* + This file is based on: + $XFree86: xc/programs/Xserver/hw/xfree86/etc/scanpci.c,v 3.34.2.17 1998/11/10 11:55:40 dawes Exp $ + Modified for readability by Nick Kurshev +*/ +#include <sys/types.h> +#include <sys/proc.h> +#include <sys/tss.h> +#if defined(NCR) +#define __STDC +#include <sys/sysi86.h> +#undef __STDC +#else +#include <sys/sysi86.h> +#endif + +#if defined(sun) +# ifndef __EXTENSIONS__ +# define __EXTENSIONS__ +# endif +# include <sys/psw.h> +#endif + +static __inline__ int enable_os_io(void) +{ +#if defined(SI86IOPL) + sysi86(SI86IOPL, 3); +#else + sysi86(SI86V86, V86SC_IOPL, PS_IOPL); +#endif + return(0); +} + +static __inline__ int disable_os_io(void) +{ +#if defined(SI86IOPL) + sysi86(SI86IOPL, 0); +#else + sysi86(SI86V86, V86SC_IOPL, 0); +#endif + return(0); +} diff --git a/contrib/libdha/sysdep/pci_win32.c b/contrib/libdha/sysdep/pci_win32.c new file mode 100644 index 000000000..1c88cb13e --- /dev/null +++ b/contrib/libdha/sysdep/pci_win32.c @@ -0,0 +1,18 @@ +/* + This file is based on: + $XFree86: xc/programs/Xserver/hw/xfree86/etc/scanpci.c,v 3.34.2.17 1998/11/10 11:55:40 dawes Exp $ + Modified for readability by Nick Kurshev +*/ +#include <windows.h> + +/* Nothing to do for Win9x. For WinNT I have no solution */ + +static __inline__ int enable_os_io(void) +{ + return(0); +} + +static __inline__ int disable_os_io(void) +{ + return(0); +} diff --git a/contrib/libdha/sysdep/pci_x86.c b/contrib/libdha/sysdep/pci_x86.c new file mode 100644 index 000000000..ef2074ab2 --- /dev/null +++ b/contrib/libdha/sysdep/pci_x86.c @@ -0,0 +1,123 @@ +/* + This file is based on: + $XFree86: xc/programs/Xserver/hw/xfree86/etc/scanpci.c,v 3.34.2.17 1998/11/10 11:55:40 dawes Exp $ + Modified for readability by Nick Kurshev +*/ + +static int pci_config_type( void ) +{ + unsigned long tmplong1, tmplong2; + unsigned char tmp1, tmp2; + int retval; + retval = 0; + + OUTPORT8(PCI_MODE2_ENABLE_REG, 0x00); + OUTPORT8(PCI_MODE2_FORWARD_REG, 0x00); + tmp1 = INPORT8(PCI_MODE2_ENABLE_REG); + tmp2 = INPORT8(PCI_MODE2_FORWARD_REG); + if ((tmp1 == 0x00) && (tmp2 == 0x00)) { + retval = 2; + /*printf("PCI says configuration type 2\n");*/ + } else { + tmplong1 = INPORT32(PCI_MODE1_ADDRESS_REG); + OUTPORT32(PCI_MODE1_ADDRESS_REG, PCI_EN); + tmplong2 = INPORT32(PCI_MODE1_ADDRESS_REG); + OUTPORT32(PCI_MODE1_ADDRESS_REG, tmplong1); + if (tmplong2 == PCI_EN) { + retval = 1; + /*printf("PCI says configuration type 1\n");*/ + } else { + /*printf("No PCI !\n");*/ + disable_app_io(); + /*exit(1);*/ + retval = 0xFFFF; + } + } + return retval; +} + +static int pci_get_vendor( + unsigned char bus, + unsigned char dev, + int func) +{ + unsigned long config_cmd; + config_cmd = PCI_EN | (bus<<16) | (dev<<11) | (func<<8); + OUTPORT32(PCI_MODE1_ADDRESS_REG, config_cmd); + return INPORT32(PCI_MODE1_DATA_REG); +} + +static long pci_config_read_long( + unsigned char bus, + unsigned char dev, + int func, + unsigned cmd) +{ + unsigned long config_cmd; + config_cmd = PCI_EN | (bus<<16) | (dev<<11) | (func<<8); + OUTPORT32(PCI_MODE1_ADDRESS_REG, config_cmd | cmd); + return INPORT32(PCI_MODE1_DATA_REG); +} + +static long pci_config_read_word( + unsigned char bus, + unsigned char dev, + int func, + unsigned cmd) +{ + unsigned long config_cmd; + config_cmd = PCI_EN | (bus<<16) | (dev<<11) | (func<<8); + OUTPORT32(PCI_MODE1_ADDRESS_REG, config_cmd | cmd); + return INPORT16(PCI_MODE1_DATA_REG); +} + +static long pci_config_read_byte( + unsigned char bus, + unsigned char dev, + int func, + unsigned cmd) +{ + unsigned long config_cmd; + config_cmd = PCI_EN | (bus<<16) | (dev<<11) | (func<<8); + OUTPORT32(PCI_MODE1_ADDRESS_REG, config_cmd | cmd); + return INPORT8(PCI_MODE1_DATA_REG); +} + +static void pci_config_write_long( + unsigned char bus, + unsigned char dev, + int func, + unsigned cmd, + long val) +{ + unsigned long config_cmd; + config_cmd = PCI_EN | (bus<<16) | (dev<<11) | (func<<8); + OUTPORT32(PCI_MODE1_ADDRESS_REG, config_cmd | cmd); + OUTPORT32(PCI_MODE1_DATA_REG,val); +} + +static void pci_config_write_word( + unsigned char bus, + unsigned char dev, + int func, + unsigned cmd, + long val) +{ + unsigned long config_cmd; + config_cmd = PCI_EN | (bus<<16) | (dev<<11) | (func<<8); + OUTPORT32(PCI_MODE1_ADDRESS_REG, config_cmd | cmd); + OUTPORT16(PCI_MODE1_DATA_REG,val); +} + +static void pci_config_write_byte( + unsigned char bus, + unsigned char dev, + int func, + unsigned cmd, + long val) +{ + unsigned long config_cmd; + config_cmd = PCI_EN | (bus<<16) | (dev<<11) | (func<<8); + OUTPORT32(PCI_MODE1_ADDRESS_REG, config_cmd | cmd); + OUTPORT8(PCI_MODE1_DATA_REG,val); +} diff --git a/contrib/libdha/test.c b/contrib/libdha/test.c new file mode 100644 index 000000000..857e739c6 --- /dev/null +++ b/contrib/libdha/test.c @@ -0,0 +1,48 @@ +#include "libdha.h" +#include "pci_names.h" +#include <stdio.h> +#include <string.h> +#include <stdlib.h> +#include <inttypes.h> /* for __WORDSIZE */ + +int main( void ) +{ + pciinfo_t lst[MAX_PCI_DEVICES]; + unsigned i,num_pci; + int err; + err = pci_scan(lst,&num_pci); + if(err) + { + printf("Error occured during pci scan: %s\n",strerror(err)); + return EXIT_FAILURE; + } + else + { + printf(" Bus:card:func vend:dev base0 :base1 :base2 :baserom :irq:pin:gnt:lat\n"); + for(i=0;i<num_pci;i++) +#if __WORDSIZE > 32 + printf("%04X:%04X:%04X %04X:%04X %16X:%16X:%16X:%16X:%02X :%02X :%02X :%02X\n" +#else + printf("%04X:%04X:%04X %04X:%04X %08X:%08X:%08X:%08X:%02X :%02X :%02X :%02X\n" +#endif + ,lst[i].bus,lst[i].card,lst[i].func + ,lst[i].vendor,lst[i].device + ,lst[i].base0,lst[i].base1,lst[i].base2,lst[i].baserom + ,lst[i].irq,lst[i].ipin,lst[i].gnt,lst[i].lat); + printf("Additional info:\n"); + printf("================\n"); + printf("base3 :base4 :base5 :name (vendor)\n"); + for(i=0;i<num_pci;i++) + { + const char *vname,*dname; + dname = pci_device_name(lst[i].vendor,lst[i].device); + dname = dname ? dname : "Unknown chip"; + vname = pci_vendor_name(lst[i].vendor); + vname = vname ? vname : "Unknown chip"; + printf("%08X:%08X:%08X:%s (%s)\n" + ,lst[i].base3,lst[i].base4,lst[i].base5 + ,dname,vname); + } + } + return EXIT_SUCCESS; +} diff --git a/contrib/vidix/Makefile.am b/contrib/vidix/Makefile.am new file mode 100644 index 000000000..7f19e7ce8 --- /dev/null +++ b/contrib/vidix/Makefile.am @@ -0,0 +1,16 @@ +include $(top_srcdir)/misc/Makefile.common + +SUBDIRS = drivers + +AM_CFLAGS = $(DEFAULT_OCFLAGS) +AM_CPPFLAGS = -I$(top_srcdir)/src/video_out/vidix -I$(top_builddir)/src/video_out/libdha + +EXTRA_DIST = README vidix.txt + +noinst_HEADERS = fourcc.h vidix.h vidixlib.h + +noinst_LTLIBRARIES = libvidix.la + +libvidix_la_SOURCES = vidixlib.c +libvidix_la_LIBADD = $(DYNAMIC_LD_LIBS) $(top_builddir)/src/video_out/libdha/libdha.la + diff --git a/contrib/vidix/README b/contrib/vidix/README new file mode 100644 index 000000000..23bcaca30 --- /dev/null +++ b/contrib/vidix/README @@ -0,0 +1,7 @@ +VIDIX - Video Interface for *niX. +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +This library was designed and introduced as interface to userspace drivers +to provide DGA everywhere where it's possible (unline X11). +I hope that these drivers will be portable same as X11 (not only on *nix). + +For detail on how to develop new driver see vidix.txt diff --git a/contrib/vidix/drivers/Makefile.am b/contrib/vidix/drivers/Makefile.am new file mode 100644 index 000000000..db3adc078 --- /dev/null +++ b/contrib/vidix/drivers/Makefile.am @@ -0,0 +1,56 @@ +include $(top_srcdir)/misc/Makefile.common + +AM_CFLAGS = $(DEFAULT_OCFLAGS) +AM_CPPFLAGS = -I$(top_srcdir)/src/video_out/vidix \ + -I$(top_srcdir)/src/video_out/libdha -I$(top_builddir)/src/video_out/libdha +AM_LDFLAGS = $(xineplug_ldflags) + +EXTRA_DIST = genfb_vid.c + +noinst_HEADERS = mach64.h glint_regs.h pm3_regs.h radeon.h savage_regs.h \ + cyberblade_regs.h unichrome_regs.h sis_defs.h sis_regs.h + +vidix_LTLIBRARIES = \ + mach64_vid.la \ + mga_crtc2_vid.la \ + mga_vid.la \ + pm2_vid.la \ + pm3_vid.la \ + radeon_vid.la \ + rage128_vid.la \ + cyberblade_vid.la \ + unichrome_vid.la \ + nvidia_vid.la \ + sis_vid.la \ + savage_vid.la + +cyberblade_vid_la_SOURCES = cyberblade_vid.c + +mach64_vid_la_SOURCES = mach64_vid.c + +mga_crtc2_vid_la_SOURCES = mga_vid.c +mga_crtc2_vid_la_LIBADD = -lm +mga_crtc2_vid_la_CPPFLAGS = $(AM_CPPFLAGS) -DCRTC2 + +mga_vid_la_SOURCES = mga_vid.c +mga_vid_la_LIBADD = -lm + +nvidia_vid_la_SOURCES = nvidia_vid.c + +pm2_vid_la_SOURCES = pm2_vid.c + +pm3_vid_la_SOURCES = pm3_vid.c + +radeon_vid_la_SOURCES = radeon_vid.c +radeon_vid_la_LIBADD = -lm + +rage128_vid_la_SOURCES = radeon_vid.c +rage128_vid_la_LIBADD = -lm +rage128_vid_la_CPPFLAGS = $(AM_CPPFLAGS) -DRAGE128 + +savage_vid_la_SOURCES = savage_vid.c +savage_vid_la_LIBADD = -lm + +sis_vid_la_SOURCES = sis_vid.c sis_bridge.c + +unichrome_vid_la_SOURCES = unichrome_vid.c diff --git a/contrib/vidix/drivers/cyberblade_regs.h b/contrib/vidix/drivers/cyberblade_regs.h new file mode 100644 index 000000000..1bae61d4a --- /dev/null +++ b/contrib/vidix/drivers/cyberblade_regs.h @@ -0,0 +1,137 @@ +/* + * Copyright 1992-2000 by Alan Hourihane, Wigan, England. + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that + * copyright notice and this permission notice appear in supporting + * documentation, and that the name of Alan Hourihane not be used in + * advertising or publicity pertaining to distribution of the software without + * specific, written prior permission. Alan Hourihane makes no representations + * about the suitability of this software for any purpose. It is provided + * "as is" without express or implied warranty. + * + * ALAN HOURIHANE DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO + * EVENT SHALL ALAN HOURIHANE BE LIABLE FOR ANY SPECIAL, INDIRECT OR + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, + * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + * + * Author: Alan Hourihane, alanh@fairlite.demon.co.uk + */ +/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/trident/trident_regs.h,v 1.22 2002/01/11 13:06:30 alanh Exp $ */ + +#define DEBUG 1 + +#define NTSC 14.31818 +#define PAL 17.73448 + +/* General Registers */ +#define SPR 0x1F /* Software Programming Register (videoram) */ + +/* 3C4 */ +#define RevisionID 0x09 +#define ConfPort1 0x0C +#define ConfPort2 0x0C +#define NewMode2 0x0D +#define OldMode2 0x00 /* Should be 0x0D - dealt with in trident_dac.c */ +#define OldMode1 0x0E +#define NewMode1 0x0E +#define Protection 0x11 +#define MCLKLow 0x16 +#define MCLKHigh 0x17 +#define ClockLow 0x18 +#define ClockHigh 0x19 +#define SSetup 0x20 +#define SKey 0x37 +#define SPKey 0x57 + +/* 3x4 */ +#define Offset 0x13 +#define Underline 0x14 +#define CRTCMode 0x17 +#define CRTCModuleTest 0x1E +#define FIFOControl 0x20 +#define LinearAddReg 0x21 +#define DRAMTiming 0x23 +#define New32 0x23 +#define RAMDACTiming 0x25 +#define CRTHiOrd 0x27 +#define AddColReg 0x29 +#define InterfaceSel 0x2A +#define HorizOverflow 0x2B +#define GETest 0x2D +#define Performance 0x2F +#define GraphEngReg 0x36 +#define I2C 0x37 +#define PixelBusReg 0x38 +#define PCIReg 0x39 +#define DRAMControl 0x3A +#define MiscContReg 0x3C +#define CursorXLow 0x40 +#define CursorXHigh 0x41 +#define CursorYLow 0x42 +#define CursorYHigh 0x43 +#define CursorLocLow 0x44 +#define CursorLocHigh 0x45 +#define CursorXOffset 0x46 +#define CursorYOffset 0x47 +#define CursorFG1 0x48 +#define CursorFG2 0x49 +#define CursorFG3 0x4A +#define CursorFG4 0x4B +#define CursorBG1 0x4C +#define CursorBG2 0x4D +#define CursorBG3 0x4E +#define CursorBG4 0x4F +#define CursorControl 0x50 +#define PCIRetry 0x55 +#define PreEndControl 0x56 +#define PreEndFetch 0x57 +#define PCIMaster 0x60 +#define Enhancement0 0x62 +#define NewEDO 0x64 + +/* --- Additions by AMR for Vidix support --- */ +#define VideoWin1_HScale 0x80 +#define VideoWin1_VScale 0x82 +#define VideoWin1_Start 0x86 +#define VideoWin1_Stop 0x8a +#define Video_Flags 0x8e +#define VideoWin1_Y_BPR 0x90 +#define VideoWin1_Y_Offset 0x92 +#define Video_LineBufferThreshold 0x95 +#define Video_LineBufferLevel 0x96 +#define Video_Flags2 0x97 +/* --- */ + +#define TVinterface 0xC0 +#define TVMode 0xC1 +#define ClockControl 0xCF + + +/* 3CE */ +#define MiscExtFunc 0x0F +#define MiscIntContReg 0x2F +#define CyberControl 0x30 +#define CyberEnhance 0x31 +#define FPConfig 0x33 +#define VertStretch 0x52 +#define HorStretch 0x53 +#define BiosMode 0x5c +#define BiosNewMode1 0x5a +#define BiosNewMode2 0x5c +#define BiosReg 0x5d + +/* --- IO Macros by AMR --- */ + +#define CRINB(reg) (OUTPORT8(0x3d4,reg), INPORT8(0x3d5)) +#define SRINB(reg) (OUTPORT8(0x3c4,reg), INPORT8(0x3c5)) +#define CROUTB(reg,val) (OUTPORT8(0x3d4,reg), OUTPORT8(0x3d5,val)) +#define SROUTB(reg,val) (OUTPORT8(0x3c4,reg), OUTPORT8(0x3c5,val)) + +/* --- */ + + diff --git a/contrib/vidix/drivers/cyberblade_vid.c b/contrib/vidix/drivers/cyberblade_vid.c new file mode 100644 index 000000000..7a32ce7bd --- /dev/null +++ b/contrib/vidix/drivers/cyberblade_vid.c @@ -0,0 +1,649 @@ +/* + Driver for CyberBlade/i1 - Version 0.1.4 + + Copyright (C) 2002 by Alastair M. Robinson. + Official homepage: http://www.blackfiveservices.co.uk/EPIAVidix.shtml + + Based on Permedia 3 driver by MÃ¥ns RullgÃ¥rd + + Thanks to Gilles Frattini for bugfixes + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + Changes: + 18/01/03 + MMIO is no longer used, sidestepping cache issues on EPIA-800 + TV-Out modes are now better supported - this should be the end + of the magenta stripes :) + Brightness/Contrast controls disabled for the time being - they were + seriously degrading picture quality, especially with TV-Out. + + To Do: + Implement Hue/Saturation controls + Support / Test multiple frames + Test colour-key code more extensively +*/ + +#include <errno.h> +#include <stdio.h> +#include <stdlib.h> +#include <string.h> +#include <inttypes.h> +#include <unistd.h> + +#include "vidix.h" +#include "fourcc.h" +#include "libdha.h" +#include "pci_ids.h" +#include "pci_names.h" + + +#include "cyberblade_regs.h" + +pciinfo_t pci_info; + +char save_colourkey[6]; +char *cyberblade_mem; + +#ifdef DEBUG_LOGFILE +FILE *logfile=0; +#define LOGWRITE(x) {if(logfile) fprintf(logfile,x);} +#else +#define LOGWRITE(x) +#endif + +/* Helper functions for reading registers. */ + +#if 0 /* unused */ +static int CRINW(int reg) +{ + int result; + result=CRINB(reg); + result|=CRINB(reg+1)<<8; + return(result); +} +#endif + +static void CROUTW(int reg,int val) +{ + CROUTB(reg,val&255); + CROUTB(reg+1,(val>>8)&255); +} + +#if 0 /* unused */ +static int SRINW(int reg) +{ + int result; + result=SRINB(reg); + result|=SRINB(reg+1)<<8; + return(result); +} +#endif + +static void SROUTW(int reg,int val) +{ + SROUTB(reg,val&255); + SROUTB(reg+1,(val>>8)&255); +} + +#if 0 /* unused */ +static void DumpRegisters(void) +{ +#ifdef DEBUG_LOGFILE + int reg,val; + if(logfile) + { + LOGWRITE("CRTC Register Dump:\n") + for(reg=0;reg<256;++reg) + { + val=CRINB(reg); + fprintf(logfile,"CR0x%2x: 0x%2x\n",reg,val); + } + LOGWRITE("SR Register Dump:\n") + for(reg=0;reg<256;++reg) + { + val=SRINB(reg); + fprintf(logfile,"SR0x%2x: 0x%2x\n",reg,val); + } + } +#endif +} +#endif + +/* --- */ + +static vidix_capability_t cyberblade_cap = +{ + "Trident CyberBlade i1 driver", + "Alastair M. Robinson <blackfive@fakenhamweb.co.uk>", + TYPE_OUTPUT, + { 0, 0, 0, 0 }, + 1024, + 1024, + 4, + 4, + -1, + FLAG_UPSCALER|FLAG_DOWNSCALER, + VENDOR_TRIDENT, + -1, + { 0, 0, 0, 0 } +}; + + +unsigned int vixGetVersion(void) +{ + return(VIDIX_VERSION); +} + + +static unsigned short cyberblade_card_ids[] = +{ + DEVICE_TRIDENT_CYBERBLADE_I7, + DEVICE_TRIDENT_CYBERBLADE_I7D, + DEVICE_TRIDENT_CYBERBLADE_I1, + DEVICE_TRIDENT_CYBERBLADE_I12, + DEVICE_TRIDENT_CYBERBLADE_I13, + DEVICE_TRIDENT_CYBERBLADE_XPAI1 +}; + + +static int find_chip(unsigned chip_id) +{ + unsigned i; + for(i = 0;i < sizeof(cyberblade_card_ids)/sizeof(unsigned short);i++) + { + if(chip_id == cyberblade_card_ids[i]) return i; + } + return -1; +} + +int vixProbe(int verbose, int force) +{ + pciinfo_t lst[MAX_PCI_DEVICES]; + unsigned i,num_pci; + int err; + err = pci_scan(lst,&num_pci); + if(err) + { + printf("[cyberblade] Error occurred during pci scan: %s\n",strerror(err)); + return err; + } + else + { + err = ENXIO; + for(i=0; i < num_pci; i++) + { + if(lst[i].vendor == VENDOR_TRIDENT) + { + int idx; + const char *dname; + idx = find_chip(lst[i].device); + if(idx == -1) + continue; + dname = pci_device_name(VENDOR_TRIDENT, lst[i].device); + dname = dname ? dname : "Unknown chip"; + printf("[cyberblade] Found chip: %s\n", dname); + cyberblade_cap.device_id = lst[i].device; + err = 0; + memcpy(&pci_info, &lst[i], sizeof(pciinfo_t)); + break; + } + } + } + + if(err && verbose) printf("[cyberblade] Can't find chip\n"); + return err; +} + + +int vixInit(const char *args) +{ + cyberblade_mem = map_phys_mem(pci_info.base0, 0x800000); + enable_app_io(); + save_colourkey[0]=SRINB(0x50); + save_colourkey[1]=SRINB(0x51); + save_colourkey[2]=SRINB(0x52); + save_colourkey[3]=SRINB(0x54); + save_colourkey[4]=SRINB(0x55); + save_colourkey[5]=SRINB(0x56); +#ifdef DEBUG_LOGFILE + logfile=fopen("/tmp/cyberblade_vidix.log","w"); +#endif + return 0; +} + +void vixDestroy(void) +{ + int protect; +#ifdef DEBUG_LOGFILE + if(logfile) + fclose(logfile); +#endif + protect=SRINB(0x11); + SROUTB(0x11, 0x92); + CROUTB(0x8E, 0xc4); /* Disable overlay */ + SROUTB(0x50,save_colourkey[0]); + SROUTB(0x51,save_colourkey[1]); + SROUTB(0x52,save_colourkey[2]); + SROUTB(0x54,save_colourkey[3]); + SROUTB(0x55,save_colourkey[4]); + SROUTB(0x56,save_colourkey[5]); + SROUTB(0x11, protect); + disable_app_io(); + unmap_phys_mem(cyberblade_mem, 0x800000); +} + + +int vixGetCapability(vidix_capability_t *to) +{ + memcpy(to, &cyberblade_cap, sizeof(vidix_capability_t)); + return 0; +} + + +static int is_supported_fourcc(uint32_t fourcc) +{ + switch(fourcc) + { + case IMGFMT_YUY2: + case IMGFMT_YV12: + case IMGFMT_I420: + case IMGFMT_YVU9: + case IMGFMT_BGR16: + return 1; + default: + return 0; + } +} + +int vixQueryFourcc(vidix_fourcc_t *to) +{ + if(is_supported_fourcc(to->fourcc)) + { + to->depth = VID_DEPTH_1BPP | VID_DEPTH_2BPP | + VID_DEPTH_4BPP | VID_DEPTH_8BPP | + VID_DEPTH_12BPP| VID_DEPTH_15BPP| + VID_DEPTH_16BPP| VID_DEPTH_24BPP| + VID_DEPTH_32BPP; + to->flags = VID_CAP_EXPAND | VID_CAP_SHRINK | VID_CAP_COLORKEY; + return 0; + } + else + to->depth = to->flags = 0; + return ENOSYS; +} + + +static int frames[VID_PLAY_MAXFRAMES]; + +static vidix_grkey_t cyberblade_grkey; + +int vixGetGrKeys(vidix_grkey_t *grkey) +{ + memcpy(grkey, &cyberblade_grkey, sizeof(vidix_grkey_t)); + return(0); +} + +int vixSetGrKeys(const vidix_grkey_t *grkey) +{ + int pixfmt=CRINB(0x38); + int protect; + memcpy(&cyberblade_grkey, grkey, sizeof(vidix_grkey_t)); + + protect=SRINB(0x11); + SROUTB(0x11, 0x92); + + if(pixfmt&0x28) /* 32 or 24 bpp */ + { + SROUTB(0x50, cyberblade_grkey.ckey.blue); /* Colour Key */ + SROUTB(0x51, cyberblade_grkey.ckey.green); /* Colour Key */ + SROUTB(0x52, cyberblade_grkey.ckey.red); /* Colour Key */ + SROUTB(0x54, 0xff); /* Colour Key Mask */ + SROUTB(0x55, 0xff); /* Colour Key Mask */ + SROUTB(0x56, 0xff); /* Colour Key Mask */ + } + else + { + int tmp=((cyberblade_grkey.ckey.blue & 0xF8)>>3) + | ((cyberblade_grkey.ckey.green & 0xfc)<<3) + | ((cyberblade_grkey.ckey.red & 0xf8)<<8); + SROUTB(0x50, tmp&0xff); /* Colour Key */ + SROUTB(0x51, (tmp>>8)&0xff); /* Colour Key */ + SROUTB(0x52, 0); /* Colour Key */ + SROUTB(0x54, 0xff); /* Colour Key Mask */ + SROUTB(0x55, 0xff); /* Colour Key Mask */ + SROUTB(0x56, 0x00); /* Colour Key Mask */ + } + SROUTB(0x11,protect); + return(0); +} + + +vidix_video_eq_t equal = +{ + VEQ_CAP_BRIGHTNESS | VEQ_CAP_SATURATION | VEQ_CAP_HUE, + 300, 100, 0, 0, 0, 0, 0, 0 +}; + +int vixPlaybackGetEq( vidix_video_eq_t * eq) +{ + memcpy(eq,&equal,sizeof(vidix_video_eq_t)); + return 0; +} + +int vixPlaybackSetEq( const vidix_video_eq_t * eq) +{ + int br,sat,cr,protect; + if(eq->cap & VEQ_CAP_BRIGHTNESS) equal.brightness = eq->brightness; + if(eq->cap & VEQ_CAP_CONTRAST) equal.contrast = eq->contrast; + if(eq->cap & VEQ_CAP_SATURATION) equal.saturation = eq->saturation; + if(eq->cap & VEQ_CAP_HUE) equal.hue = eq->hue; + if(eq->cap & VEQ_CAP_RGB_INTENSITY) + { + equal.red_intensity = eq->red_intensity; + equal.green_intensity = eq->green_intensity; + equal.blue_intensity = eq->blue_intensity; + } + equal.flags = eq->flags; + + cr = (equal.contrast) * 31 / 2000; cr+=16; + if (cr < 0) cr = 0; if(cr > 7) cr = 7; + cr=cr<<4 | cr; + + br = (equal.brightness+1000) * 63 / 2000; + if (br < 0) br = 0; if(br > 63) br = 63; + if(br>32) br-=32; else br+=32; + + sat = (equal.saturation + 1000) * 16 / 2000; + if (sat < 0) sat = 0; if(sat > 31) sat = 31; + + protect=SRINB(0x11); + SROUTB(0x11, 0x92); + + SROUTB(0xBC,cr); + SROUTW(0xB0,(br<<10)|4); + + SROUTB(0x11, protect); + + return 0; +} + + +static int YOffs,UOffs,VOffs; + +int vixConfigPlayback(vidix_playback_t *info) +{ + int src_w, drw_w; + int src_h, drw_h; + int hscale,vscale; + long base0; + int y_pitch = 0, uv_pitch = 0; + int protect=0; + int layout=0; + unsigned int i; + + if(!is_supported_fourcc(info->fourcc)) + return -1; + + src_w = info->src.w; + src_h = info->src.h; + + drw_w = info->dest.w; + drw_h = info->dest.h; + + switch(info->fourcc) + { + case IMGFMT_YUY2: + case IMGFMT_BGR16: + y_pitch = (src_w*2 + 15) & ~15; + uv_pitch = 0; + YOffs=VOffs=UOffs=info->offset.y = info->offset.v = info->offset.u = 0; + info->frame_size = y_pitch*src_h; + layout=0x0; /* packed */ + break; + case IMGFMT_YV12: + case IMGFMT_I420: + y_pitch = (src_w+15) & ~15; + uv_pitch = ((src_w/2)+7) & ~7; + YOffs=info->offset.y = 0; + VOffs=info->offset.v = y_pitch*src_h; + UOffs=info->offset.u = info->offset.v+(uv_pitch)*(src_h/2); + info->frame_size = y_pitch*src_h + 2*uv_pitch*(src_h/2); + layout=0x1; /* planar, 4:1:1 */ + break; + case IMGFMT_YVU9: + y_pitch = (src_w+15) & ~15; + uv_pitch = ((src_w/4)+3) & ~3; + YOffs=info->offset.y = 0; + VOffs=info->offset.v = y_pitch*src_h; + UOffs=info->offset.u = info->offset.v+(uv_pitch)*(src_h/4); + info->frame_size = y_pitch*src_h + 2*uv_pitch*(src_h/4); + layout=0x51; /* planar, 16:1:1 */ + break; + } + + /* Assume we have 2 MB to play with */ + info->num_frames = 0x200000 / info->frame_size; + if(info->num_frames > VID_PLAY_MAXFRAMES) + info->num_frames = VID_PLAY_MAXFRAMES; + + /* Start at 6 MB. Let's hope it's not in use. */ + base0 = 0x600000; + info->dga_addr = cyberblade_mem + base0; + + info->dest.pitch.y = 16; + info->dest.pitch.u = 16; + info->dest.pitch.v = 16; + + for(i = 0; i < info->num_frames; i++) + { + info->offsets[i] = info->frame_size * i; + frames[i] = base0+info->offsets[i]; + } + + OUTPORT8(0x3d4,0x39); + OUTPORT8(0x3d5,INPORT(0x3d5)|1); + + SRINB(0x0b); /* Select new mode */ + + /* Unprotect hardware registers... */ + protect=SRINB(0x11); + SROUTB(0x11, 0x92); + + SROUTB(0x57, 0xc0); /* Playback key function */ + SROUTB(0x21, 0x34); /* Signature control */ + SROUTB(0x37, 0x30); /* Video key mode */ + + vixSetGrKeys(&cyberblade_grkey); + + /* compute_scale_factor(&src_w, &drw_w, &shrink, &zoom); */ + { + int HTotal,VTotal,HSync,VSync,Overflow,HDisp,VDisp; + int HWinStart,VWinStart; + int tx1,ty1,tx2,ty2; + + HTotal=CRINB(0x00); + HSync=CRINB(0x04); + VTotal=CRINB(0x06); + VSync=CRINB(0x10); + Overflow=CRINB(0x07); + HTotal <<=3; + HSync <<=3; + VTotal |= (Overflow & 1) <<8; + VTotal |= (Overflow & 0x20) <<4; + VTotal +=4; + VSync |= (Overflow & 4) <<6; + VSync |= (Overflow & 0x80) <<2; + + if(CRINB(0xd1)&0x80) + { + int TVHTotal,TVVTotal,TVHSyncStart,TVVSyncStart,TVOverflow; + LOGWRITE("[cyberblade] Using TV-CRTC\n"); + + HDisp=(1+CRINB(0x01))*8; + VDisp=1+CRINB(0x12); + Overflow=CRINB(0x07); + VDisp |= (Overflow & 2) <<7; + VDisp |= (Overflow & 0x40) << 3; + + TVHTotal=CRINB(0xe0)*8; + TVVTotal=CRINB(0xe6); + TVOverflow=CRINB(0xe7); + if(TVOverflow&0x20) TVVTotal|=512; + if(TVOverflow&0x01) TVVTotal|=256; + TVHTotal+=40; TVVTotal+=2; + + TVHSyncStart=CRINB(0xe4)*8; + TVVSyncStart=CRINB(0xf0); + if(TVOverflow&0x80) TVVSyncStart|=512; + if(TVOverflow&0x04) TVVSyncStart|=256; + + HWinStart=(TVHTotal-HDisp)&15; + HWinStart|=(HTotal-HDisp)&15; + HWinStart+=(TVHTotal-TVHSyncStart)-49; + } + else + { + LOGWRITE("[cyberblade] Using Standard CRTC\n"); + HWinStart=(HTotal-HSync)+15; + } + VWinStart=(VTotal-VSync)-8; + + printf("[cyberblade] HTotal: 0x%x, HSStart: 0x%x\n",HTotal,HSync); + printf(" VTotal: 0x%x, VStart: 0x%x\n",VTotal,VSync); + tx1=HWinStart+info->dest.x; + ty1=VWinStart+info->dest.y; + tx2=tx1+info->dest.w; + ty2=ty1+info->dest.h; + + CROUTW(0x86,tx1); + CROUTW(0x88,ty1); + CROUTW(0x8a,tx2); + CROUTW(0x8c,ty2+3); + } + + if(src_w==drw_w) + hscale=0; + else if(src_w<drw_w) + { + hscale=((src_w<<10)/(drw_w-2)) & 0x1fff; + } + else + { + hscale=0x8000 | ((((src_w/drw_w)-1)&7)<<10) | (((drw_w<<10)/src_w) & 0x3ff); + } + + vscale=(src_h<<10)/(drw_h); + if(drw_h<src_h) + vscale=0x8000|((drw_h<<10)/(src_h)); + + /* Write scale factors to hardware */ + + CROUTW(0x80,hscale); /* Horizontal Scale */ + CROUTW(0x82,vscale); /* Vertical Scale */ + + /* Now set the start address and data layout */ + { + int lb = (y_pitch+2) >> 2; + CROUTB(0x95, ((lb & 0x100)>>1) | 0x08 ); /* Linebuffer level bit 8 & threshold */ + CROUTB(0x96, (lb & 0xFF)); /* Linebuffer level */ + + CROUTB(0x97, 0x00); /* VDE Flags */ + CROUTB(0xBA, 0x00); /* Chroma key */ + CROUTB(0xBB, 0x00); /* Chroma key */ + CROUTB(0xBC, 0xFF); /* Chroma key */ + CROUTB(0xBD, 0xFF); /* Chroma key */ + CROUTB(0xBE, 0x04); /* Capture control */ + + if(src_w > 384) + layout|=4; /* 2x line buffers */ + SROUTB(0x97, layout); + + CROUTW(0x90,y_pitch); /* Y Bytes per row */ + SROUTW(0x9A,uv_pitch); /* UV Bytes per row */ + + switch(info->fourcc) + { + case IMGFMT_BGR16: + CROUTB(0x8F, 0x24); /* VDE Flags - Edge Recovery & CSC Bypass */ + CROUTB(0xBF, 0x02); /* Video format - RGB16 */ + SROUTB(0xBE, 0x0); /* HSCB disabled */ + break; + default: + CROUTB(0x8F, 0x20); /* VDE Flags - Edge Recovery */ + CROUTB(0xBF, 0x00); /* Video format - YUV */ + SROUTB(0xBE, 0x00); /* HSCB disable - was 0x03*/ + break; + } + + CROUTB(0x92, ((base0+info->offset.y) >> 3) &0xff); /* Lower 8 bits of start address */ + CROUTB(0x93, ((base0+info->offset.y) >> 11) &0xff); /* Mid 8 bits of start address */ + CROUTB(0x94, ((base0+info->offset.y) >> 19) &0xf); /* Upper 4 bits of start address */ + SROUTB(0x80, ((base0+info->offset.v) >> 3) &0xff); /* Lower 8 bits of start address */ + SROUTB(0x81, ((base0+info->offset.v) >> 11) &0xff); /* Mid 8 bits of start address */ + SROUTB(0x82, ((base0+info->offset.v) >> 19) &0xf); /* Upper 4 bits of start address */ + SROUTB(0x83, ((base0+info->offset.u) >> 3) &0xff); /* Lower 8 bits of start address */ + SROUTB(0x84, ((base0+info->offset.u) >> 11) &0xff); /* Mid 8 bits of start address */ + SROUTB(0x85, ((base0+info->offset.u) >> 19) &0xf); /* Upper 4 bits of start address */ + } + + vixPlaybackSetEq(&equal); + + /* Protect hardware registers again */ + SROUTB(0x11, protect); + return 0; +} + + +int vixPlaybackOn(void) +{ + LOGWRITE("Enable overlay\n"); + CROUTB(0x8E, 0xd4); /* VDE Flags*/ + + return 0; +} + + +int vixPlaybackOff(void) +{ + LOGWRITE("Disable overlay\n"); + CROUTB(0x8E, 0xc4); /* VDE Flags*/ + + return 0; +} + + +int vixPlaybackFrameSelect(unsigned int frame) +{ + int protect; + LOGWRITE("Frame select\n"); + protect=SRINB(0x11); + SROUTB(0x11, 0x92); + /* Set overlay address to that of selected frame */ + CROUTB(0x92, ((frames[frame]+YOffs) >> 3) &0xff); /* Lower 8 bits of start address */ + CROUTB(0x93, ((frames[frame]+YOffs) >> 11) &0xff); /* Mid 8 bits of start address */ + CROUTB(0x94, ((frames[frame]+YOffs) >> 19) &0xf); /* Upper 4 bits of start address */ + SROUTB(0x80, ((frames[frame]+VOffs) >> 3) &0xff); /* Lower 8 bits of start address */ + SROUTB(0x81, ((frames[frame]+VOffs) >> 11) &0xff); /* Mid 8 bits of start address */ + SROUTB(0x82, ((frames[frame]+VOffs) >> 19) &0xf); /* Upper 4 bits of start address */ + SROUTB(0x83, ((frames[frame]+UOffs) >> 3) &0xff); /* Lower 8 bits of start address */ + SROUTB(0x84, ((frames[frame]+UOffs) >> 11) &0xff); /* Mid 8 bits of start address */ + SROUTB(0x85, ((frames[frame]+UOffs) >> 19) &0xf); /* Upper 4 bits of start address */ + SROUTB(0x11, protect); + return 0; +} + + + diff --git a/contrib/vidix/drivers/genfb_vid.c b/contrib/vidix/drivers/genfb_vid.c new file mode 100644 index 000000000..eaf548438 --- /dev/null +++ b/contrib/vidix/drivers/genfb_vid.c @@ -0,0 +1,177 @@ +#include <errno.h> +#include <stdio.h> +#include <stdlib.h> +#include <string.h> +#include <math.h> +#include <inttypes.h> +#include <fcntl.h> + +#include "../vidix.h" +#include "../fourcc.h" +#include "../../libdha/libdha.h" +#include "../../libdha/pci_ids.h" +#include "../../libdha/pci_names.h" + +#define DEMO_DRIVER 1 +#define VIDIX_STATIC genfb_ + +#define GENFB_MSG "[genfb-demo-driver] " + +#if 0 /* these are unused. remove? */ +static int fd; + +static void *mmio_base = 0; +static void *mem_base = 0; +static int32_t overlay_offset = 0; +static uint32_t ram_size = 0; +#endif + +static int probed = 0; + +/* VIDIX exports */ + +static vidix_capability_t genfb_cap = +{ + "General Framebuffer", + "alex", + TYPE_OUTPUT, + { 0, 0, 0, 0 }, + 2048, + 2048, + 4, + 4, + -1, + FLAG_UPSCALER|FLAG_DOWNSCALER, + -1, + -1, + { 0, 0, 0, 0 } +}; + +unsigned int VIDIX_NAME(vixGetVersion)(void) +{ + return(VIDIX_VERSION); +} + +int VIDIX_NAME(vixProbe)(int verbose,int force) +{ +#if 0 + int err = 0; +#ifdef DEMO_DRIVER + err = ENOSYS; +#endif + + printf(GENFB_MSG"probe\n"); + + fd = open("/dev/fb0", O_RDWR); + if (fd < 0) + { + printf(GENFB_MSG"Error occured durint open: %s\n", strerror(errno)); + err = errno; + } + + probed = 1; + + return(err); +#else + pciinfo_t lst[MAX_PCI_DEVICES]; + unsigned i,num_pci; + int err; + err = pci_scan(lst,&num_pci); + if(err) + { + printf(GENFB_MSG"Error occured during pci scan: %s\n",strerror(err)); + return err; + } + else + { + err = ENXIO; + for(i=0;i<num_pci;i++) + { + if(verbose) + printf(GENFB_MSG" Found chip [%04X:%04X] '%s' '%s'\n" + ,lst[i].vendor + ,lst[i].device + ,pci_vendor_name(lst[i].vendor) + ,pci_device_name(lst[i].vendor,lst[i].device)); + } + } + return ENOSYS; +#endif +} + +int VIDIX_NAME(vixInit)(const char *args) +{ + printf(GENFB_MSG"init\n"); + + if (!probed) + { + printf(GENFB_MSG"Driver was not probed but is being initialized\n"); + return(EINTR); + } + + return(0); +} + +void VIDIX_NAME(vixDestroy)(void) +{ + printf(GENFB_MSG"destory\n"); + return; +} + +int VIDIX_NAME(vixGetCapability)(vidix_capability_t *to) +{ + memcpy(to, &genfb_cap, sizeof(vidix_capability_t)); + return(0); +} + +int VIDIX_NAME(vixQueryFourcc)(vidix_fourcc_t *to) +{ + printf(GENFB_MSG"query fourcc (%x)\n", to->fourcc); + + to->depth = VID_DEPTH_1BPP | VID_DEPTH_2BPP | + VID_DEPTH_4BPP | VID_DEPTH_8BPP | + VID_DEPTH_12BPP | VID_DEPTH_15BPP | + VID_DEPTH_16BPP | VID_DEPTH_24BPP | + VID_DEPTH_32BPP; + + to->flags = 0; + return(0); +} + +int VIDIX_NAME(vixConfigPlayback)(vidix_playback_t *info) +{ + printf(GENFB_MSG"config playback\n"); + + info->num_frames = 2; + info->frame_size = info->src.w*info->src.h+(info->src.w*info->src.h)/2; + info->dest.pitch.y = 32; + info->dest.pitch.u = info->dest.pitch.v = 16; + info->offsets[0] = 0; + info->offsets[1] = info->frame_size; + info->offset.y = 0; + info->offset.v = ((info->src.w+31) & ~31) * info->src.h; + info->offset.u = info->offset.v+((info->src.w+31) & ~31) * info->src.h/4; + info->dga_addr = malloc(info->num_frames*info->frame_size); + printf(GENFB_MSG"frame_size: %d, dga_addr: %p\n", + info->frame_size, info->dga_addr); + + return(0); +} + +int VIDIX_NAME(vixPlaybackOn)(void) +{ + printf(GENFB_MSG"playback on\n"); + return(0); +} + +int VIDIX_NAME(vixPlaybackOff)(void) +{ + printf(GENFB_MSG"playback off\n"); + return(0); +} + +int VIDIX_NAME(vixPlaybackFrameSelect)(unsigned int frame) +{ + printf(GENFB_MSG"frameselect: %d\n", frame); + return(0); +} diff --git a/contrib/vidix/drivers/glint_regs.h b/contrib/vidix/drivers/glint_regs.h new file mode 100644 index 000000000..f33accd3d --- /dev/null +++ b/contrib/vidix/drivers/glint_regs.h @@ -0,0 +1,1304 @@ +/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/glint/glint_regs.h,v 1.31 2001/12/08 16:01:52 alanh Exp $ */ + +/* + * glint register file + * + * Copyright by Stefan Dirsch, Dirk Hohndel, Alan Hourihane + * Authors: Alan Hourihane, <alanh@fairlite.demon.co.uk> + * Dirk Hohndel, <hohndel@suse.de> + * Stefan Dirsch, <sndirsch@suse.de> + * Simon P., <sim@suse.de> + * + * this work is sponsored by S.u.S.E. GmbH, Fuerth, Elsa GmbH, Aachen and + * Siemens Nixdorf Informationssysteme + * + */ + +#ifndef _GLINTREG_H_ +#define _GLINTREG_H_ + +/********************************************** +* GLINT 500TX Configuration Region Registers * +***********************************************/ + +/* Device Identification */ +#define CFGVendorId 0x0000 +#define PCI_VENDOR_3DLABS 0x3D3D +#define PCI_VENDOR_TI 0x104C +#define CFGDeviceId 0x0002 + +#define CFGRevisionId 0x08 +#define CFGClassCode 0x09 +#define CFGHeaderType 0x0E + +/* Device Control/Status */ +#define CFGCommand 0x04 +#define CFGStatus 0x06 + +/* Miscellaneous Functions */ +#define CFGBist 0x0f +#define CFGLatTimer 0x0d +#define CFGCacheLine 0x0c +#define CFGMaxLat 0x3f +#define CFGMinGrant 0x3e +#define CFGIntPin 0x3d +#define CFGIntLine 0x3c + +/* Base Adresses */ +#define CFGBaseAddr0 0x10 +#define CFGBaseAddr1 0x14 +#define CFGBaseAddr2 0x18 +#define CFGBaseAddr3 0x1C +#define CFGBaseAddr4 0x20 +#define CFGRomAddr 0x30 + + + +/********************************** + * GLINT 500TX Region 0 Registers * + **********************************/ + +/* Control Status Registers */ +#define ResetStatus 0x0000 +#define IntEnable 0x0008 +#define IntFlags 0x0010 +#define InFIFOSpace 0x0018 +#define OutFIFOWords 0x0020 +#define DMAAddress 0x0028 +#define DMACount 0x0030 +#define ErrorFlags 0x0038 +#define VClkCtl 0x0040 +#define TestRegister 0x0048 +#define Aperture0 0x0050 +#define Aperture1 0x0058 +#define DMAControl 0x0060 +#define FIFODis 0x0068 + +/* GLINT PerMedia Region 0 additional Registers */ +#define ChipConfig 0x0070 +#define SCLK_SEL_MASK (3 << 10) +#define SCLK_SEL_MCLK_HALF (3 << 10) +#define ByDMAControl 0x00D8 + +/* GLINT 500TX LocalBuffer Registers */ +#define LBMemoryCtl 0x1000 +#define LBNumBanksMask 0x00000001 +#define LBNumBanks1 (0) +#define LBNumBanks2 (1) +#define LBPageSizeMask 0x00000006 +#define LBPageSize256 (0<<1) +#define LBPageSize512 (1<<1) +#define LBPageSize1024 (2<<1) +#define LBPageSize2048 (3<<1) +#define LBRASCASLowMask 0x00000018 +#define LBRASCASLow2 (0<<3) +#define LBRASCASLow3 (1<<3) +#define LBRASCASLow4 (2<<3) +#define LBRASCASLow5 (3<<3) +#define LBRASPrechargeMask 0x00000060 +#define LBRASPrecharge2 (0<<5) +#define LBRASPrecharge3 (1<<5) +#define LBRASPrecharge4 (2<<5) +#define LBRASPrecharge5 (3<<5) +#define LBCASLowMask 0x00000180 +#define LBCASLow1 (0<<7) +#define LBCASLow2 (1<<7) +#define LBCASLow3 (2<<7) +#define LBCASLow4 (3<<7) +#define LBPageModeMask 0x00000200 +#define LBPageModeEnabled (0<<9) +#define LBPageModeDisabled (1<<9) +#define LBRefreshCountMask 0x0003fc00 +#define LBRefreshCountShift 10 + +#define LBMemoryEDO 0x1008 +#define LBEDOMask 0x00000001 +#define LBEDODisabled (0) +#define LBEDOEnabled (1) +#define LBEDOBankSizeMask 0x0000000e +#define LBEDOBankSizeDiabled (0<<1) +#define LBEDOBankSize256K (1<<1) +#define LBEDOBankSize512K (2<<1) +#define LBEDOBankSize1M (3<<1) +#define LBEDOBankSize2M (4<<1) +#define LBEDOBankSize4M (5<<1) +#define LBEDOBankSize8M (6<<1) +#define LBEDOBankSize16M (7<<1) +#define LBTwoPageDetectorMask 0x00000010 +#define LBSinglePageDetector (0<<4) +#define LBTwoPageDetector (1<<4) + +/* GLINT PerMedia Memory Control Registers */ +#define PMReboot 0x1000 +#define PMRomControl 0x1040 +#define PMBootAddress 0x1080 +#define PMMemConfig 0x10C0 + #define RowCharge8 1 << 10 + #define TimeRCD8 1 << 7 + #define TimeRC8 0x6 << 3 + #define TimeRP8 1 + #define CAS3Latency8 0 << 16 + #define BootAdress8 0x10 + #define NumberBanks8 0x3 << 29 + #define RefreshCount8 0x41 << 21 + #define TimeRASMin8 1 << 13 + #define DeadCycle8 1 << 17 + #define BankDelay8 0 << 18 + #define Burst1Cycle8 1 << 31 + #define SDRAM8 0 << 4 + + #define RowCharge6 1 << 10 + #define TimeRCD6 1 << 7 + #define TimeRC6 0x6 << 3 + #define TimeRP6 0x2 + #define CAS3Latency6 1 << 16 + #define BootAdress6 0x60 + #define NumberBanks6 0x2 << 29 + #define RefreshCount6 0x41 << 21 + #define TimeRASMin6 1 << 13 + #define DeadCycle6 1 << 17 + #define BankDelay6 0 << 18 + #define Burst1Cycle6 1 << 31 + #define SDRAM6 0 << 4 + + #define RowCharge4 0 << 10 + #define TimeRCD4 0 << 7 + #define TimeRC4 0x4 << 3 + #define TimeRP4 1 + #define CAS3Latency4 0 << 16 + #define BootAdress4 0x10 + #define NumberBanks4 1 << 29 + #define RefreshCount4 0x30 << 21 + #define TimeRASMin4 1 << 13 + #define DeadCycle4 0 << 17 + #define BankDelay4 0 << 18 + #define Burst1Cycle4 1 << 31 + #define SDRAM4 0 << 4 + +/* Permedia 2 Control */ +#define MemControl 0x1040 + +#define PMBypassWriteMask 0x1100 +#define PMFramebufferWriteMask 0x1140 +#define PMCount 0x1180 + +/* Framebuffer Registers */ +#define FBMemoryCtl 0x1800 +#define FBModeSel 0x1808 +#define FBGCWrMask 0x1810 +#define FBGCColorLower 0x1818 +#define FBTXMemCtl 0x1820 +#define FBWrMaskk 0x1830 +#define FBGCColorUpper 0x1838 + +/* Core FIFO */ +#define OutputFIFO 0x2000 + +/* 500TX Internal Video Registers */ +#define VTGHLimit 0x3000 +#define VTGHSyncStart 0x3008 +#define VTGHSyncEnd 0x3010 +#define VTGHBlankEnd 0x3018 +#define VTGVLimit 0x3020 +#define VTGVSyncStart 0x3028 +#define VTGVSyncEnd 0x3030 +#define VTGVBlankEnd 0x3038 +#define VTGHGateStart 0x3040 +#define VTGHGateEnd 0x3048 +#define VTGVGateStart 0x3050 +#define VTGVGateEnd 0x3058 +#define VTGPolarity 0x3060 +#define VTGFrameRowAddr 0x3068 +#define VTGVLineNumber 0x3070 +#define VTGSerialClk 0x3078 +#define VTGModeCtl 0x3080 + +/* Permedia Video Control Registers */ +#define PMScreenBase 0x3000 +#define PMScreenStride 0x3008 +#define PMHTotal 0x3010 +#define PMHgEnd 0x3018 +#define PMHbEnd 0x3020 +#define PMHsStart 0x3028 +#define PMHsEnd 0x3030 +#define PMVTotal 0x3038 +#define PMVbEnd 0x3040 +#define PMVsStart 0x3048 +#define PMVsEnd 0x3050 +#define PMVideoControl 0x3058 +#define PMInterruptLine 0x3060 +#define PMDDCData 0x3068 +#define DataIn (1<<0) +#define ClkIn (1<<1) +#define DataOut (1<<2) +#define ClkOut (1<<3) +#define PMLineCount 0x3070 +#define PMFifoControl 0x3078 + +/* Permedia 2 RAMDAC Registers */ +#define PM2DACWriteAddress 0x4000 +#define PM2DACIndexReg 0x4000 +#define PM2DACData 0x4008 +#define PM2DACReadMask 0x4010 +#define PM2DACReadAddress 0x4018 +#define PM2DACCursorColorAddress 0x4020 +#define PM2DACCursorColorData 0x4028 +#define PM2DACIndexData 0x4050 +#define PM2DACCursorData 0x4058 +#define PM2DACCursorXLsb 0x4060 +#define PM2DACCursorXMsb 0x4068 +#define PM2DACCursorYLsb 0x4070 +#define PM2DACCursorYMsb 0x4078 +#define PM2DACCursorControl 0x06 +#define PM2DACIndexCMR 0x18 +#define PM2DAC_TRUECOLOR 0x80 +#define PM2DAC_RGB 0x20 +#define PM2DAC_GRAPHICS 0x10 +#define PM2DAC_PACKED 0x09 +#define PM2DAC_8888 0x08 +#define PM2DAC_565 0x06 +#define PM2DAC_4444 0x05 +#define PM2DAC_5551 0x04 +#define PM2DAC_2321 0x03 +#define PM2DAC_2320 0x02 +#define PM2DAC_332 0x01 +#define PM2DAC_CI8 0x00 +#define PM2DACIndexMDCR 0x19 +#define PM2DACIndexPalettePage 0x1c +#define PM2DACIndexMCR 0x1e +#define PM2DACIndexClockAM 0x20 +#define PM2DACIndexClockAN 0x21 +#define PM2DACIndexClockAP 0x22 +#define PM2DACIndexClockBM 0x23 +#define PM2DACIndexClockBN 0x24 +#define PM2DACIndexClockBP 0x25 +#define PM2DACIndexClockCM 0x26 +#define PM2DACIndexClockCN 0x27 +#define PM2DACIndexClockCP 0x28 +#define PM2DACIndexClockStatus 0x29 +#define PM2DACIndexMemClockM 0x30 +#define PM2DACIndexMemClockN 0x31 +#define PM2DACIndexMemClockP 0x32 +#define PM2DACIndexMemClockStatus 0x33 +#define PM2DACIndexColorKeyControl 0x40 +#define PM2DACIndexColorKeyOverlay 0x41 +#define PM2DACIndexColorKeyRed 0x42 +#define PM2DACIndexColorKeyGreen 0x43 +#define PM2DACIndexColorKeyBlue 0x44 + +/* Permedia 2V extensions */ +#define PM2VDACRDMiscControl 0x000 +#define PM2VDACRDSyncControl 0x001 +#define PM2VDACRDDACControl 0x002 +#define PM2VDACRDPixelSize 0x003 +#define PM2VDACRDColorFormat 0x004 +#define PM2VDACRDCursorMode 0x005 +#define PM2VDACRDCursorXLow 0x007 +#define PM2VDACRDCursorXHigh 0x008 +#define PM2VDACRDCursorYLow 0x009 +#define PM2VDACRDCursorYHigh 0x00A +#define PM2VDACRDCursorHotSpotX 0x00B +#define PM2VDACRDCursorHotSpotY 0x00C +#define PM2VDACRDOverlayKey 0x00D +#define PM2VDACRDPan 0x00E +#define PM2VDACRDSense 0x00F +#define PM2VDACRDCheckControl 0x018 +#define PM2VDACIndexClockControl 0x200 +#define PM2VDACRDDClk0PreScale 0x201 +#define PM2VDACRDDClk0FeedbackScale 0x202 +#define PM2VDACRDDClk0PostScale 0x203 +#define PM2VDACRDDClk1PreScale 0x204 +#define PM2VDACRDDClk1FeedbackScale 0x205 +#define PM2VDACRDDClk1PostScale 0x206 +#define PM2VDACRDMClkControl 0x20D +#define PM2VDACRDMClkPreScale 0x20E +#define PM2VDACRDMClkFeedbackScale 0x20F +#define PM2VDACRDMClkPostScale 0x210 +#define PM2VDACRDCursorPalette 0x303 +#define PM2VDACRDCursorPattern 0x400 +#define PM2VDACIndexRegLow 0x4020 +#define PM2VDACIndexRegHigh 0x4028 +#define PM2VDACIndexData 0x4030 +#define PM2VDACRDIndexControl 0x4038 + +/* Permedia 2 Video Streams Unit Registers */ +#define VSBIntFlag (1<<8) +#define VSAIntFlag (1<<9) + +#define VSConfiguration 0x5800 +#define VS_UnitMode_ROM 0 +#define VS_UnitMode_AB8 3 +#define VS_UnitMode_Mask 7 +#define VS_GPBusMode_A (1<<3) +#define VS_HRefPolarityA (1<<9) +#define VS_VRefPolarityA (1<<10) +#define VS_VActivePolarityA (1<<11) +#define VS_UseFieldA (1<<12) +#define VS_FieldPolarityA (1<<13) +#define VS_FieldEdgeA (1<<14) +#define VS_VActiveVBIA (1<<15) +#define VS_InterlaceA (1<<16) +#define VS_ReverseDataA (1<<17) +#define VS_HRefPolarityB (1<<18) +#define VS_VRefPolarityB (1<<19) +#define VS_VActivePolarityB (1<<20) +#define VS_UseFieldB (1<<21) +#define VS_FieldPolarityB (1<<22) +#define VS_FieldEdgeB (1<<23) +#define VS_VActiveVBIB (1<<24) +#define VS_InterlaceB (1<<25) +#define VS_ColorSpaceB_RGB (1<<26) +#define VS_ReverseDataB (1<<27) +#define VS_DoubleEdgeB (1<<28) + +#define VSStatus 0x5808 +#define VS_FieldOne0A (1<<9) +#define VS_FieldOne1A (1<<10) +#define VS_FieldOne2A (1<<11) +#define VS_InvalidInterlaceA (1<<12) +#define VS_FieldOne0B (1<<17) +#define VS_FieldOne1B (1<<18) +#define VS_FieldOne2B (1<<19) +#define VS_InvalidInterlaceB (1<<20) + +#define VSSerialBusControl 0x5810 + +#define VSABase 0x5900 +#define VSA_Video (1<<0) +#define VSA_VBI (1<<1) +#define VSA_BufferCtl (1<<2) +#define VSA_MirrorX (1<<7) +#define VSA_MirrorY (1<<8) +#define VSA_Discard_None (0<<9) +#define VSA_Discard_FieldOne (1<<9) +#define VSA_Discard_FieldTwo (2<<9) +#define VSA_CombineFields (1<<11) +#define VSA_LockToStreamB (1<<12) +#define VSBBase 0x5A00 +#define VSB_Video (1<<0) +#define VSB_VBI (1<<1) +#define VSB_BufferCtl (1<<2) +#define VSB_CombineFields (1<<3) +#define VSB_RGBOrder (1<<11) +#define VSB_GammaCorrect (1<<12) +#define VSB_LockToStreamA (1<<13) + +#define VSControl 0x0000 +#define VSInterrupt 0x0008 +#define VSCurrentLine 0x0010 +#define VSVideoAddressHost 0x0018 +#define VSVideoAddressIndex 0x0020 +#define VSVideoAddress0 0x0028 +#define VSVideoAddress1 0x0030 +#define VSVideoAddress2 0x0038 +#define VSVideoStride 0x0040 +#define VSVideoStartLine 0x0048 +#define VSVideoEndLine 0x0050 +#define VSVideoStartData 0x0058 +#define VSVideoEndData 0x0060 +#define VSVBIAddressHost 0x0068 +#define VSVBIAddressIndex 0x0070 +#define VSVBIAddress0 0x0078 +#define VSVBIAddress1 0x0080 +#define VSVBIAddress2 0x0088 +#define VSVBIStride 0x0090 +#define VSVBIStartLine 0x0098 +#define VSVBIEndLine 0x00A0 +#define VSVBIStartData 0x00A8 +#define VSVBIEndData 0x00B0 +#define VSFifoControl 0x00B8 + +/********************************** + * GLINT Delta Region 0 Registers * + **********************************/ + +/* Control Status Registers */ +#define DResetStatus 0x0800 +#define DIntEnable 0x0808 +#define DIntFlags 0x0810 +#define DErrorFlags 0x0838 +#define DTestRegister 0x0848 +#define DFIFODis 0x0868 + + + +/********************************** + * GLINT Gamma Region 0 Registers * + **********************************/ + +/* Control Status Registers */ +#define GInFIFOSpace 0x0018 +#define GDMAAddress 0x0028 +#define GDMACount 0x0030 +#define GDMAControl 0x0060 +#define GOutDMA 0x0080 +#define GOutDMACount 0x0088 +#define GResetStatus 0x0800 +#define GIntEnable 0x0808 +#define GIntFlags 0x0810 +#define GErrorFlags 0x0838 +#define GTestRegister 0x0848 +#define GFIFODis 0x0868 + +#define GChipConfig 0x0870 +#define GChipAGPCapable 1 << 0 +#define GChipAGPSideband 1 << 1 +#define GChipMultiGLINTApMask 3 << 19 +#define GChipMultiGLINTAp_0M 0 << 19 +#define GChipMultiGLINTAp_16M 1 << 19 +#define GChipMultiGLINTAp_32M 2 << 19 +#define GChipMultiGLINTAp_64M 3 << 19 + +#define GCSRAperture 0x0878 +#define GCSRSecondaryGLINTMapEn 1 << 0 + +#define GPageTableAddr 0x0c00 +#define GPageTableLength 0x0c08 +#define GDelayTimer 0x0c38 +#define GCommandMode 0x0c40 +#define GCommandIntEnable 0x0c48 +#define GCommandIntFlags 0x0c50 +#define GCommandErrorFlags 0x0c58 +#define GCommandStatus 0x0c60 +#define GCommandFaultingAddr 0x0c68 +#define GVertexFaultingAddr 0x0c70 +#define GWriteFaultingAddr 0x0c88 +#define GFeedbackSelectCount 0x0c98 +#define GGammaProcessorMode 0x0cb8 +#define GVGAShadow 0x0d00 +#define GMultGLINTAperture 0x0d08 +#define GMultGLINT1 0x0d10 +#define GMultGLINT2 0x0d18 + +/************************ + * GLINT Core Registers * + ************************/ + +#define GLINT_TAG(major,offset) (((major) << 7) | ((offset) << 3)) +#define GLINT_TAG_ADDR(major,offset) (0x8000 | GLINT_TAG((major),(offset))) + +#define UNIT_DISABLE 0 +#define UNIT_ENABLE 1 + +#define StartXDom GLINT_TAG_ADDR(0x00,0x00) +#define dXDom GLINT_TAG_ADDR(0x00,0x01) +#define StartXSub GLINT_TAG_ADDR(0x00,0x02) +#define dXSub GLINT_TAG_ADDR(0x00,0x03) +#define StartY GLINT_TAG_ADDR(0x00,0x04) +#define dY GLINT_TAG_ADDR(0x00,0x05) +#define GLINTCount GLINT_TAG_ADDR(0x00,0x06) +#define Render GLINT_TAG_ADDR(0x00,0x07) + #define AreaStippleEnable 0x00001 + #define LineStippleEnable 0x00002 + #define ResetLineStipple 0x00004 + #define FastFillEnable 0x00008 + #define PrimitiveLine 0 + #define PrimitiveTrapezoid 0x00040 + #define PrimitivePoint 0x00080 + #define PrimitiveRectangle 0x000C0 + #define AntialiasEnable 0x00100 + #define AntialiasingQuality 0x00200 + #define UsePointTable 0x00400 + #define SyncOnBitMask 0x00800 + #define SyncOnHostData 0x01000 + #define TextureEnable 0x02000 + #define FogEnable 0x04000 + #define CoverageEnable 0x08000 + #define SubPixelCorrectionEnable 0x10000 + #define SpanOperation 0x40000 + #define XPositive 1<<21 + #define YPositive 1<<22 + + +#define ContinueNewLine GLINT_TAG_ADDR(0x00,0x08) +#define ContinueNewDom GLINT_TAG_ADDR(0x00,0x09) +#define ContinueNewSub GLINT_TAG_ADDR(0x00,0x0a) +#define Continue GLINT_TAG_ADDR(0x00,0x0b) +#define FlushSpan GLINT_TAG_ADDR(0x00,0x0c) +#define BitMaskPattern GLINT_TAG_ADDR(0x00,0x0d) + +#define PointTable0 GLINT_TAG_ADDR(0x01,0x00) +#define PointTable1 GLINT_TAG_ADDR(0x01,0x01) +#define PointTable2 GLINT_TAG_ADDR(0x01,0x02) +#define PointTable3 GLINT_TAG_ADDR(0x01,0x03) +#define RasterizerMode GLINT_TAG_ADDR(0x01,0x04) +#define RMMultiGLINT 1<<17 +#define BitMaskPackingEachScanline 1<<9 +#define ForceBackgroundColor 1<<6 +#define InvertBitMask 1<<1 +#define YLimits GLINT_TAG_ADDR(0x01,0x05) +#define ScanLineOwnership GLINT_TAG_ADDR(0x01,0x06) +#define WaitForCompletion GLINT_TAG_ADDR(0x01,0x07) +#define PixelSize GLINT_TAG_ADDR(0x01,0x08) +#define XLimits GLINT_TAG_ADDR(0x01,0x09) /* PM only */ + +#define RectangleOrigin GLINT_TAG_ADDR(0x01,0x0A) /* PM2 only */ +#define RectangleSize GLINT_TAG_ADDR(0x01,0x0B) /* PM2 only */ + +#define PackedDataLimits GLINT_TAG_ADDR(0x02,0x0a) /* PM only */ + +#define ScissorMode GLINT_TAG_ADDR(0x03,0x00) + #define SCI_USER 0x01 + #define SCI_SCREEN 0x02 + #define SCI_USERANDSCREEN 0x03 + +#define ScissorMinXY GLINT_TAG_ADDR(0x03,0x01) +#define ScissorMaxXY GLINT_TAG_ADDR(0x03,0x02) +#define ScreenSize GLINT_TAG_ADDR(0x03,0x03) +#define AreaStippleMode GLINT_TAG_ADDR(0x03,0x04) + /* 0: */ + /* NoMirrorY */ + /* NoMirrorX */ + /* NoInvertPattern */ + /* YAddress_1bit */ + /* XAddress_1bit */ + /* UNIT_DISABLE */ + + #define ASM_XAddress_2bit 1 << 1 + #define ASM_XAddress_3bit 2 << 1 + #define ASM_XAddress_4bit 3 << 1 + #define ASM_XAddress_5bit 4 << 1 + #define ASM_YAddress_2bit 1 << 4 + #define ASM_YAddress_3bit 2 << 4 + #define ASM_YAddress_4bit 3 << 4 + #define ASM_YAddress_5bit 4 << 4 + #define ASM_InvertPattern 1 << 17 + #define ASM_MirrorX 1 << 18 + #define ASM_MirrorY 1 << 19 + +#define LineStippleMode GLINT_TAG_ADDR(0x03,0x05) +#define LoadLineStippleCounters GLINT_TAG_ADDR(0x03,0x06) +#define UpdateLineStippleCounters GLINT_TAG_ADDR(0x03,0x07) +#define SaveLineStippleState GLINT_TAG_ADDR(0x03,0x08) +#define WindowOrigin GLINT_TAG_ADDR(0x03,0x09) + +#define AreaStipplePattern0 GLINT_TAG_ADDR(0x04,0x00) +#define AreaStipplePattern1 GLINT_TAG_ADDR(0x04,0x01) +#define AreaStipplePattern2 GLINT_TAG_ADDR(0x04,0x02) +#define AreaStipplePattern3 GLINT_TAG_ADDR(0x04,0x03) +#define AreaStipplePattern4 GLINT_TAG_ADDR(0x04,0x04) +#define AreaStipplePattern5 GLINT_TAG_ADDR(0x04,0x05) +#define AreaStipplePattern6 GLINT_TAG_ADDR(0x04,0x06) +#define AreaStipplePattern7 GLINT_TAG_ADDR(0x04,0x07) + +#define TextureAddressMode GLINT_TAG_ADDR(0x07,0x00) +#define SStart GLINT_TAG_ADDR(0x07,0x01) +#define dSdx GLINT_TAG_ADDR(0x07,0x02) +#define dSdyDom GLINT_TAG_ADDR(0x07,0x03) +#define TStart GLINT_TAG_ADDR(0x07,0x04) +#define dTdx GLINT_TAG_ADDR(0x07,0x05) +#define dTdyDom GLINT_TAG_ADDR(0x07,0x06) +#define QStart GLINT_TAG_ADDR(0x07,0x07) +#define dQdx GLINT_TAG_ADDR(0x07,0x08) +#define dQdyDom GLINT_TAG_ADDR(0x07,0x09) +#define LOD GLINT_TAG_ADDR(0x07,0x0A) +#define dSdy GLINT_TAG_ADDR(0x07,0x0B) +#define dTdy GLINT_TAG_ADDR(0x07,0x0C) +#define dQdy GLINT_TAG_ADDR(0x07,0x0D) + +#define TextureReadMode GLINT_TAG_ADDR(0x09,0x00) +#define TextureFormat GLINT_TAG_ADDR(0x09,0x01) + #define Texture_4_Components 3 << 3 + #define Texture_Texel 0 + +#define TextureCacheControl GLINT_TAG_ADDR(0x09,0x02) + #define TextureCacheControlEnable 2 + #define TextureCacheControlInvalidate 1 + +#define GLINTBorderColor GLINT_TAG_ADDR(0x09,0x05) + +#define TexelLUTIndex GLINT_TAG_ADDR(0x09,0x08) +#define TexelLUTData GLINT_TAG_ADDR(0x09,0x09) +#define TexelLUTAddress GLINT_TAG_ADDR(0x09,0x0A) +#define TexelLUTTransfer GLINT_TAG_ADDR(0x09,0x0B) +#define TextureFilterMode GLINT_TAG_ADDR(0x09,0x0C) +#define TextureChromaUpper GLINT_TAG_ADDR(0x09,0x0D) +#define TextureChromaLower GLINT_TAG_ADDR(0x09,0x0E) + +#define TxBaseAddr0 GLINT_TAG_ADDR(0x0A,0x00) +#define TxBaseAddr1 GLINT_TAG_ADDR(0x0A,0x01) +#define TxBaseAddr2 GLINT_TAG_ADDR(0x0A,0x02) +#define TxBaseAddr3 GLINT_TAG_ADDR(0x0A,0x03) +#define TxBaseAddr4 GLINT_TAG_ADDR(0x0A,0x04) +#define TxBaseAddr5 GLINT_TAG_ADDR(0x0A,0x05) +#define TxBaseAddr6 GLINT_TAG_ADDR(0x0A,0x06) +#define TxBaseAddr7 GLINT_TAG_ADDR(0x0A,0x07) +#define TxBaseAddr8 GLINT_TAG_ADDR(0x0A,0x08) +#define TxBaseAddr9 GLINT_TAG_ADDR(0x0A,0x09) +#define TxBaseAddr10 GLINT_TAG_ADDR(0x0A,0x0A) +#define TxBaseAddr11 GLINT_TAG_ADDR(0x0A,0x0B) + +#define PMTextureBaseAddress GLINT_TAG_ADDR(0x0b,0x00) +#define PMTextureMapFormat GLINT_TAG_ADDR(0x0b,0x01) +#define PMTextureDataFormat GLINT_TAG_ADDR(0x0b,0x02) + +#define Texel0 GLINT_TAG_ADDR(0x0c,0x00) +#define Texel1 GLINT_TAG_ADDR(0x0c,0x01) +#define Texel2 GLINT_TAG_ADDR(0x0c,0x02) +#define Texel3 GLINT_TAG_ADDR(0x0c,0x03) +#define Texel4 GLINT_TAG_ADDR(0x0c,0x04) +#define Texel5 GLINT_TAG_ADDR(0x0c,0x05) +#define Texel6 GLINT_TAG_ADDR(0x0c,0x06) +#define Texel7 GLINT_TAG_ADDR(0x0c,0x07) +#define Interp0 GLINT_TAG_ADDR(0x0c,0x08) +#define Interp1 GLINT_TAG_ADDR(0x0c,0x09) +#define Interp2 GLINT_TAG_ADDR(0x0c,0x0a) +#define Interp3 GLINT_TAG_ADDR(0x0c,0x0b) +#define Interp4 GLINT_TAG_ADDR(0x0c,0x0c) +#define TextureFilter GLINT_TAG_ADDR(0x0c,0x0d) +#define PMTextureReadMode GLINT_TAG_ADDR(0x0c,0x0e) +#define TexelLUTMode GLINT_TAG_ADDR(0x0c,0x0f) + +#define TextureColorMode GLINT_TAG_ADDR(0x0d,0x00) + #define TextureTypeOpenGL 0 + #define TextureTypeApple 1 << 4 + #define TextureKsDDA 1 << 5 /* only Apple-Mode */ + #define TextureKdDDA 1 << 6 /* only Apple-Mode */ + +#define TextureEnvColor GLINT_TAG_ADDR(0x0d,0x01) +#define FogMode GLINT_TAG_ADDR(0x0d,0x02) + /* 0: */ + /* FOG RGBA */ + /* UNIT_DISABLE */ + + #define FOG_CI 0x0002 + +#define FogColor GLINT_TAG_ADDR(0x0d,0x03) +#define FStart GLINT_TAG_ADDR(0x0d,0x04) +#define dFdx GLINT_TAG_ADDR(0x0d,0x05) +#define dFdyDom GLINT_TAG_ADDR(0x0d,0x06) +#define KsStart GLINT_TAG_ADDR(0x0d,0x09) +#define dKsdx GLINT_TAG_ADDR(0x0d,0x0a) +#define dKsdyDom GLINT_TAG_ADDR(0x0d,0x0b) +#define KdStart GLINT_TAG_ADDR(0x0d,0x0c) +#define dKdStart GLINT_TAG_ADDR(0x0d,0x0d) +#define dKddyDom GLINT_TAG_ADDR(0x0d,0x0e) + +#define RStart GLINT_TAG_ADDR(0x0f,0x00) +#define dRdx GLINT_TAG_ADDR(0x0f,0x01) +#define dRdyDom GLINT_TAG_ADDR(0x0f,0x02) +#define GStart GLINT_TAG_ADDR(0x0f,0x03) +#define dGdx GLINT_TAG_ADDR(0x0f,0x04) +#define dGdyDom GLINT_TAG_ADDR(0x0f,0x05) +#define BStart GLINT_TAG_ADDR(0x0f,0x06) +#define dBdx GLINT_TAG_ADDR(0x0f,0x07) +#define dBdyDom GLINT_TAG_ADDR(0x0f,0x08) +#define AStart GLINT_TAG_ADDR(0x0f,0x09) +#define dAdx GLINT_TAG_ADDR(0x0f,0x0a) +#define dAdyDom GLINT_TAG_ADDR(0x0f,0x0b) +#define ColorDDAMode GLINT_TAG_ADDR(0x0f,0x0c) + /* 0: */ + #define CDDA_FlatShading 0 + /* UNIT_DISABLE */ + #define CDDA_GouraudShading 0x0002 + + +#define ConstantColor GLINT_TAG_ADDR(0x0f,0x0d) +#define GLINTColor GLINT_TAG_ADDR(0x0f,0x0e) +#define AlphaTestMode GLINT_TAG_ADDR(0x10,0x00) +#define AntialiasMode GLINT_TAG_ADDR(0x10,0x01) +#define AlphaBlendMode GLINT_TAG_ADDR(0x10,0x02) + /* 0: */ + /* SrcZERO */ + /* DstZERO */ + /* ColorFormat8888 */ + /* AlphaBuffer present */ + /* ColorOrderBGR */ + /* TypeOpenGL */ + /* DstFBData */ + /* UNIT_DISABLE */ + + #define ABM_SrcONE 1 << 1 + #define ABM_SrcDST_COLOR 2 << 1 + #define ABM_SrcONE_MINUS_DST_COLOR 3 << 1 + #define ABM_SrcSRC_ALPHA 4 << 1 + #define ABM_SrcONE_MINUS_SRC_ALPHA 5 << 1 + #define ABM_SrcDST_ALPHA 6 << 1 + #define ABM_SrcONE_MINUS_DST_ALPHA 7 << 1 + #define ABM_SrcSRC_ALPHA_SATURATE 8 << 1 + #define ABM_DstONE 1 << 5 + #define ABM_DstSRC_COLOR 2 << 5 + #define ABM_DstONE_MINUS_SRC_COLOR 3 << 5 + #define ABM_DstSRC_ALPHA 4 << 5 + #define ABM_DstONE_MINUS_SRC_ALPHA 5 << 5 + #define ABM_DstDST_ALPHA 6 << 5 + #define ABM_DstONE_MINUS_DST_ALPHA 7 << 5 + #define ABM_ColorFormat5555 1 << 8 + #define ABM_ColorFormat4444 2 << 8 + #define ABM_ColorFormat4444_Front 3 << 8 + #define ABM_ColorFormat4444_Back 4 << 8 + #define ABM_ColorFormat332_Front 5 << 8 + #define ABM_ColorFormat332_Back 6 << 8 + #define ABM_ColorFormat121_Front 7 << 8 + #define ABM_ColorFormat121_Back 8 << 8 + #define ABM_ColorFormat555_Back 13 << 8 + #define ABM_ColorFormat_CI8 14 << 8 + #define ABM_ColorFormat_CI4 15 << 8 + #define ABM_NoAlphaBuffer 0x1000 + #define ABM_ColorOrderRGB 0x2000 + #define ABM_TypeQuickDraw3D 0x4000 + #define ABM_DstFBSourceData 0x8000 + +#define DitherMode GLINT_TAG_ADDR(0x10,0x03) + /* 0: */ + /* ColorOrder BGR */ + /* AlphaDitherDefault */ + /* ColorFormat8888 */ + /* TruncateMode */ + /* DitherDisable */ + /* UNIT_DISABLE */ + + #define DTM_DitherEnable 1 << 1 + #define DTM_ColorFormat5555 1 << 2 + #define DTM_ColorFormat4444 2 << 2 + #define DTM_ColorFormat4444_Front 3 << 2 + #define DTM_ColorFormat4444_Back 4 << 2 + #define DTM_ColorFormat332_Front 5 << 2 + #define DTM_ColorFormat332_Back 6 << 2 + #define DTM_ColorFormat121_Front 7 << 2 + #define DTM_ColorFormat121_Back 8 << 2 + #define DTM_ColorFormat555_Back 13 << 2 + #define DTM_ColorFormat_CI8 14 << 2 + #define DTM_ColorFormat_CI4 15 << 2 + #define DTM_ColorOrderRGB 1 << 10 + #define DTM_NoAlphaDither 1 << 14 + #define DTM_RoundMode 1 << 15 + +#define FBSoftwareWriteMask GLINT_TAG_ADDR(0x10,0x04) +#define LogicalOpMode GLINT_TAG_ADDR(0x10,0x05) + #define Use_ConstantFBWriteData 0x40 + + +#define FBWriteData GLINT_TAG_ADDR(0x10,0x06) +#define RouterMode GLINT_TAG_ADDR(0x10,0x08) + #define ROUTER_Depth_Texture 1 + #define ROUTER_Texture_Depth 0 + + +#define LBReadMode GLINT_TAG_ADDR(0x11,0x00) + /* 0: */ + /* SrcNoRead */ + /* DstNoRead */ + /* DataLBDefault */ + /* WinTopLeft */ + /* NoPatch */ + /* ScanlineInterval1 */ + + #define LBRM_SrcEnable 1 << 9 + #define LBRM_DstEnable 1 << 10 + #define LBRM_DataLBStencil 1 << 16 + #define LBRM_DataLBDepth 2 << 16 + #define LBRM_WinBottomLeft 1 << 18 + #define LBRM_DoPatch 1 << 19 + + #define LBRM_ScanlineInt2 1 << 20 + #define LBRM_ScanlineInt4 2 << 20 + #define LBRM_ScanlineInt8 3 << 20 + + +#define LBReadFormat GLINT_TAG_ADDR(0x11,0x01) + #define LBRF_DepthWidth15 0x03 /* only permedia */ + #define LBRF_DepthWidth16 0x00 + #define LBRF_DepthWidth24 0x01 + #define LBRF_DepthWidth32 0x02 + + #define LBRF_StencilWidth0 (0 << 2) + #define LBRF_StencilWidth4 (1 << 2) + #define LBRF_StencilWidth8 (2 << 2) + + #define LBRF_StencilPos16 (0 << 4) + #define LBRF_StencilPos20 (1 << 4) + #define LBRF_StencilPos24 (2 << 4) + #define LBRF_StencilPos28 (3 << 4) + #define LBRF_StencilPos32 (4 << 4) + + #define LBRF_FrameCount0 (0 << 7) + #define LBRF_FrameCount4 (1 << 7) + #define LBRF_FrameCount8 (2 << 7) + + #define LBRF_FrameCountPos16 (0 << 9) + #define LBRF_FrameCountPos20 (1 << 9) + #define LBRF_FrameCountPos24 (2 << 9) + #define LBRF_FrameCountPos28 (3 << 9) + #define LBRF_FrameCountPos32 (4 << 9) + #define LBRF_FrameCountPos36 (5 << 9) + #define LBRF_FrameCountPos40 (6 << 9) + + #define LBRF_GIDWidth0 (0 << 12) + #define LBRF_GIDWidth4 (1 << 12) + + #define LBRF_GIDPos16 (0 << 13) + #define LBRF_GIDPos20 (1 << 13) + #define LBRF_GIDPos24 (2 << 13) + #define LBRF_GIDPos28 (3 << 13) + #define LBRF_GIDPos32 (4 << 13) + #define LBRF_GIDPos36 (5 << 13) + #define LBRF_GIDPos40 (6 << 13) + #define LBRF_GIDPos44 (7 << 13) + #define LBRF_GIDPos48 (8 << 13) + + #define LBRF_Compact32 (1 << 17) + + + +#define LBSourceOffset GLINT_TAG_ADDR(0x11,0x02) +#define LBStencil GLINT_TAG_ADDR(0x11,0x05) +#define LBDepth GLINT_TAG_ADDR(0x11,0x06) +#define LBWindowBase GLINT_TAG_ADDR(0x11,0x07) +#define LBWriteMode GLINT_TAG_ADDR(0x11,0x08) + #define LBWM_WriteEnable 0x1 + #define LBWM_UpLoad_LBDepth 0x2 + #define LBWM_UpLoad_LBStencil 0x4 + +#define LBWriteFormat GLINT_TAG_ADDR(0x11,0x09) + + +#define TextureData GLINT_TAG_ADDR(0x11,0x0d) +#define TextureDownloadOffset GLINT_TAG_ADDR(0x11,0x0e) +#define LBWindowOffset GLINT_TAG_ADDR(0x11,0x0f) + +#define GLINTWindow GLINT_TAG_ADDR(0x13,0x00) + #define GWIN_UnitEnable (1 << 0) + #define GWIN_ForceLBUpdate (1 << 3) + #define GWIN_LBUpdateSourceREG (1 << 4) + #define GWIN_LBUpdateSourceLB (0 << 4) + #define GWIN_StencilFCP (1 << 17) + #define GWIN_DepthFCP (1 << 18) + #define GWIN_OverrideWriteFilter (1 << 19) + + /* ??? is this needed, set by permedia (2) modules */ + #define GWIN_DisableLBUpdate 0x40000 + +#define StencilMode GLINT_TAG_ADDR(0x13,0x01) +#define StencilData GLINT_TAG_ADDR(0x13,0x02) +#define GLINTStencil GLINT_TAG_ADDR(0x13,0x03) +#define DepthMode GLINT_TAG_ADDR(0x13,0x04) + /* 0: */ + /* WriteDisable */ + /* SrcCompFragment */ + /* CompFuncNEVER */ + /* UNIT_DISABLE */ + + #define DPM_WriteEnable 1 << 1 + #define DPM_SrcCompLBData 1 << 2 + #define DPM_SrcCompDregister 2 << 2 + #define DPM_SrcCompLBSourceData 3 << 2 + #define DPM_CompFuncLESS 1 << 4 + #define DPM_CompFuncEQUAL 2 << 4 + #define DPM_CompFuncLESS_OR_EQ 3 << 4 + #define DPM_CompFuncGREATER 4 << 4 + #define DPM_CompFuncNOT_EQ 5 << 4 + #define DPM_CompFuncGREATER_OR_EQ 6 << 4 + #define DPM_CompFuncALWAYS 7 << 4 + +#define GLINTDepth GLINT_TAG_ADDR(0x13,0x05) +#define ZStartU GLINT_TAG_ADDR(0x13,0x06) +#define ZStartL GLINT_TAG_ADDR(0x13,0x07) +#define dZdxU GLINT_TAG_ADDR(0x13,0x08) +#define dZdxL GLINT_TAG_ADDR(0x13,0x09) +#define dZdyDomU GLINT_TAG_ADDR(0x13,0x0a) +#define dZdyDomL GLINT_TAG_ADDR(0x13,0x0b) +#define FastClearDepth GLINT_TAG_ADDR(0x13,0x0c) + +#define FBReadMode GLINT_TAG_ADDR(0x15,0x00) + /* 0: */ + /* SrcNoRead */ + /* DstNoRead */ + /* DataFBDefault */ + /* WinTopLeft */ + /* ScanlineInterval1 */ + + #define FBRM_SrcEnable 1 << 9 + #define FBRM_DstEnable 1 << 10 + #define FBRM_DataFBColor 1 << 15 + #define FBRM_WinBottomLeft 1 << 16 + #define FBRM_Packed 1 << 19 + #define FBRM_ScanlineInt2 1 << 23 + #define FBRM_ScanlineInt4 2 << 23 + #define FBRM_ScanlineInt8 3 << 23 + + +#define FBSourceOffset GLINT_TAG_ADDR(0x15,0x01) +#define FBPixelOffset GLINT_TAG_ADDR(0x15,0x02) +#define FBColor GLINT_TAG_ADDR(0x15,0x03) +#define FBData GLINT_TAG_ADDR(0x15,0x04) +#define FBSourceData GLINT_TAG_ADDR(0x15,0x05) + +#define FBWindowBase GLINT_TAG_ADDR(0x15,0x06) +#define FBWriteMode GLINT_TAG_ADDR(0x15,0x07) + /* 0: */ + /* FBWM_NoColorUpload */ + /* FBWM_WriteDisable */ + #define FBWM_WriteEnable 1 + #define FBWM_UploadColor 1 << 3 +/* Permedia3 extensions */ + #define FBWM_Enable0 1 << 12 + +#define FBHardwareWriteMask GLINT_TAG_ADDR(0x15,0x08) +#define FBBlockColor GLINT_TAG_ADDR(0x15,0x09) +#define FBReadPixel GLINT_TAG_ADDR(0x15,0x0a) /* PM */ +#define PatternRamMode GLINT_TAG_ADDR(0x15,0x0f) + +#define PatternRamData0 GLINT_TAG_ADDR(0x16,0x00) +#define PatternRamData1 GLINT_TAG_ADDR(0x16,0x01) +#define PatternRamData2 GLINT_TAG_ADDR(0x16,0x02) +#define PatternRamData3 GLINT_TAG_ADDR(0x16,0x03) +#define PatternRamData4 GLINT_TAG_ADDR(0x16,0x04) +#define PatternRamData5 GLINT_TAG_ADDR(0x16,0x05) +#define PatternRamData6 GLINT_TAG_ADDR(0x16,0x06) +#define PatternRamData7 GLINT_TAG_ADDR(0x16,0x07) + +#define FilterMode GLINT_TAG_ADDR(0x18,0x00) + /* 0: */ + /* CullDepthTags */ + /* CullDepthData */ + /* CullStencilTags */ + /* CullStencilData */ + /* CullColorTag */ + /* CullColorData */ + /* CullSyncTag */ + /* CullSyncData */ + /* CullStatisticTag */ + /* CullStatisticData */ + + #define FM_PassDepthTags 0x0010 + #define FM_PassDepthData 0x0020 + #define FM_PassStencilTags 0x0040 + #define FM_PassStencilData 0x0080 + #define FM_PassColorTag 0x0100 + #define FM_PassColorData 0x0200 + #define FM_PassSyncTag 0x0400 + #define FM_PassSyncData 0x0800 + #define FM_PassStatisticTag 0x1000 + #define FM_PassStatisticData 0x2000 + +#define Sync_tag 0x0188 + +#define StatisticMode GLINT_TAG_ADDR(0x18,0x01) +#define MinRegion GLINT_TAG_ADDR(0x18,0x02) +#define MaxRegion GLINT_TAG_ADDR(0x18,0x03) +#define ResetPickResult GLINT_TAG_ADDR(0x18,0x04) +#define MitHitRegion GLINT_TAG_ADDR(0x18,0x05) +#define MaxHitRegion GLINT_TAG_ADDR(0x18,0x06) +#define PickResult GLINT_TAG_ADDR(0x18,0x07) +#define GlintSync GLINT_TAG_ADDR(0x18,0x08) + +#define FBBlockColorU GLINT_TAG_ADDR(0x18,0x0d) +#define FBBlockColorL GLINT_TAG_ADDR(0x18,0x0e) +#define SuspendUntilFrameBlank GLINT_TAG_ADDR(0x18,0x0f) + +#define KsRStart GLINT_TAG_ADDR(0x19,0x00) +#define dKsRdx GLINT_TAG_ADDR(0x19,0x01) +#define dKsRdyDom GLINT_TAG_ADDR(0x19,0x02) +#define KsGStart GLINT_TAG_ADDR(0x19,0x03) +#define dKsGdx GLINT_TAG_ADDR(0x19,0x04) +#define dKsGdyDom GLINT_TAG_ADDR(0x19,0x05) +#define KsBStart GLINT_TAG_ADDR(0x19,0x06) +#define dKsBdx GLINT_TAG_ADDR(0x19,0x07) +#define dKsBdyDom GLINT_TAG_ADDR(0x19,0x08) + +#define KdRStart GLINT_TAG_ADDR(0x1A,0x00) +#define dKdRdx GLINT_TAG_ADDR(0x1A,0x01) +#define dKdRdyDom GLINT_TAG_ADDR(0x1A,0x02) +#define KdGStart GLINT_TAG_ADDR(0x1A,0x03) +#define dKdGdx GLINT_TAG_ADDR(0x1A,0x04) +#define dKdGdyDom GLINT_TAG_ADDR(0x1A,0x05) +#define KdBStart GLINT_TAG_ADDR(0x1A,0x06) +#define dKdBdx GLINT_TAG_ADDR(0x1A,0x07) +#define dKdBdyDom GLINT_TAG_ADDR(0x1A,0x08) + +#define FBSourceBase GLINT_TAG_ADDR(0x1B,0x00) +#define FBSourceDelta GLINT_TAG_ADDR(0x1B,0x01) +#define Config GLINT_TAG_ADDR(0x1B,0x02) +#define CFBRM_SrcEnable 1<<0 +#define CFBRM_DstEnable 1<<1 +#define CFBRM_Packed 1<<2 +#define CWM_Enable 1<<3 +#define CCDDA_Enable 1<<4 +#define CLogOp_Enable 1<<5 +#define ContextDump GLINT_TAG_ADDR(0x1B,0x08) +#define ContextRestore GLINT_TAG_ADDR(0x1B,0x09) +#define ContextData GLINT_TAG_ADDR(0x1B,0x0a) + +#define TexelLUT0 GLINT_TAG_ADDR(0x1D,0x00) +#define TexelLUT1 GLINT_TAG_ADDR(0x1D,0x01) +#define TexelLUT2 GLINT_TAG_ADDR(0x1D,0x02) +#define TexelLUT3 GLINT_TAG_ADDR(0x1D,0x03) +#define TexelLUT4 GLINT_TAG_ADDR(0x1D,0x04) +#define TexelLUT5 GLINT_TAG_ADDR(0x1D,0x05) +#define TexelLUT6 GLINT_TAG_ADDR(0x1D,0x06) +#define TexelLUT7 GLINT_TAG_ADDR(0x1D,0x07) +#define TexelLUT8 GLINT_TAG_ADDR(0x1D,0x08) +#define TexelLUT9 GLINT_TAG_ADDR(0x1D,0x09) +#define TexelLUT10 GLINT_TAG_ADDR(0x1D,0x0A) +#define TexelLUT11 GLINT_TAG_ADDR(0x1D,0x0B) +#define TexelLUT12 GLINT_TAG_ADDR(0x1D,0x0C) +#define TexelLUT13 GLINT_TAG_ADDR(0x1D,0x0D) +#define TexelLUT14 GLINT_TAG_ADDR(0x1D,0x0E) +#define TexelLUT15 GLINT_TAG_ADDR(0x1D,0x0F) + +#define YUVMode GLINT_TAG_ADDR(0x1E,0x00) +#define ChromaUpper GLINT_TAG_ADDR(0x1E,0x01) +#define ChromaLower GLINT_TAG_ADDR(0x1E,0x02) +#define ChromaTestMode GLINT_TAG_ADDR(0x1E,0x03) +#define AlphaMapUpperBound GLINT_TAG_ADDR(0x1E,0x03) /* PM2 */ +#define AlphaMapLowerBound GLINT_TAG_ADDR(0x1E,0x04) /* PM2 */ + + +/****************************** + * GLINT Delta Core Registers * + ******************************/ + +#define V0FixedTag GLINT_TAG_ADDR(0x20,0x00) +#define V1FixedTag GLINT_TAG_ADDR(0x21,0x00) +#define V2FixedTag GLINT_TAG_ADDR(0x22,0x00) +#define V0FloatTag GLINT_TAG_ADDR(0x23,0x00) +#define V1FloatTag GLINT_TAG_ADDR(0x24,0x00) +#define V2FloatTag GLINT_TAG_ADDR(0x25,0x00) + +#define VPAR_s 0x00 +#define VPAR_t 0x08 +#define VPAR_q 0x10 +#define VPAR_Ks 0x18 +#define VPAR_Kd 0x20 + +/* have changed colors in ramdac ! +#define VPAR_R 0x28 +#define VPAR_G 0x30 +#define VPAR_B 0x38 +#define VPAR_A 0x40 +*/ +#define VPAR_B 0x28 +#define VPAR_G 0x30 +#define VPAR_R 0x38 +#define VPAR_A 0x40 + +#define VPAR_f 0x48 + +#define VPAR_x 0x50 +#define VPAR_y 0x58 +#define VPAR_z 0x60 + +#define DeltaModeTag GLINT_TAG_ADDR(0x26,0x00) + /* 0: */ + /* GLINT_300SX */ + + /* DeltaMode Register Bit Field Assignments */ + #define DM_GLINT_300SX 0x0000 + #define DM_GLINT_500TX 0x0001 + #define DM_PERMEDIA 0x0002 + #define DM_Depth_16BPP (1 << 2) + #define DM_Depth_24BPP (2 << 2) + #define DM_Depth_32BPP (3 << 2) + #define DM_FogEnable 0x0010 + #define DM_TextureEnable 0x0020 + #define DM_SmoothShadingEnable 0x0040 + #define DM_DepthEnable 0x0080 + #define DM_SpecularTextureEnable 0x0100 + #define DM_DiffuseTextureEnable 0x0200 + #define DM_SubPixelCorrectionEnable 0x0400 + #define DM_DiamondExit 0x0800 + #define DM_NoDraw 0x1000 + #define DM_ClampEnable 0x2000 + #define DM_ClampedTexParMode 0x4000 + #define DM_NormalizedTexParMode 0xC000 + + + #define DDCMD_AreaStrippleEnable 0x0001 + #define DDCMD_LineStrippleEnable 0x0002 + #define DDCMD_ResetLineStripple 1 << 2 + #define DDCMD_FastFillEnable 1 << 3 + /* 2 Bits reserved */ + #define DDCMD_PrimitiveType_Point 2 << 6 + #define DDCMD_PrimitiveType_Line 0 << 6 + #define DDCMD_PrimitiveType_Trapezoid 1 << 6 + #define DDCMD_AntialiasEnable 1 << 8 + #define DDCMD_AntialiasingQuality 1 << 9 + #define DDCMD_UsePointTable 1 << 10 + #define DDCMD_SyncOnBitMask 1 << 11 + #define DDCMD_SyncOnHostDate 1 << 12 + #define DDCMD_TextureEnable 1 << 13 + #define DDCMD_FogEnable 1 << 14 + #define DDCMD_CoverageEnable 1 << 15 + #define DDCMD_SubPixelCorrectionEnable 1 << 16 + + + +#define DrawTriangle GLINT_TAG_ADDR(0x26,0x01) +#define RepeatTriangle GLINT_TAG_ADDR(0x26,0x02) +#define DrawLine01 GLINT_TAG_ADDR(0x26,0x03) +#define DrawLine10 GLINT_TAG_ADDR(0x26,0x04) +#define RepeatLine GLINT_TAG_ADDR(0x26,0x05) +#define BroadcastMask GLINT_TAG_ADDR(0x26,0x0F) + +/* Permedia 3 - Accelerator Extensions */ +#define FillRectanglePosition 0x8348 +#define FillRender2D 0x8350 +#define FBDstReadBufAddr0 0xAE80 +#define FBDstReadBufOffset0 0xAEA0 +#define FBDstReadBufWidth0 0xAEC0 +#define FBDstReadMode 0xAEE0 +#define FBDRM_Enable0 1<<8 +#define FBDRM_Blocking 1<<24 +#define FBDstReadEnables 0xAEE8 +#define FBSrcReadMode 0xAF00 +#define FBSRM_Blocking 1<<11 +#define FBSrcReadBufAddr 0xAF08 +#define FBSrcReadBufOffset0 0xAF10 +#define FBSrcReadBufWidth 0xAF18 +#define FBWriteBufAddr0 0xB000 +#define FBWriteBufOffset0 0xB020 +#define FBWriteBufWidth0 0xB040 +#define FBBlockColorBack 0xB0A0 +#define ForegroundColor 0xB0C0 +#define BackgroundColor 0xB0C8 +#define RectanglePosition 0xB600 +#define Render2D 0xB640 + +/* Colorformats */ +#define BGR555 1 +#define BGR565 16 +#define CI8 14 +#define CI4 15 + +#ifdef DEBUG +#define GLINT_WRITE_REG(v,r) \ + GLINT_VERB_WRITE_REG(pGlint,v,r,__FILE__,__LINE__) +#define GLINT_READ_REG(r) \ + GLINT_VERB_READ_REG(pGlint,r,__FILE__,__LINE__) +#else + +#define GLINT_WRITE_REG(v,r) \ + MMIO_OUT32(pGlint->IOBase + pGlint->IOOffset,(unsigned long)(r), (v)) +#define GLINT_READ_REG(r) \ + MMIO_IN32(pGlint->IOBase + pGlint->IOOffset,(unsigned long)(r)) + +#endif /* DEBUG */ + +#define GLINT_WAIT(n) \ +do{ \ + if (pGlint->InFifoSpace>=(n)) \ + pGlint->InFifoSpace -= (n); \ + else { \ + int tmp; \ + while((tmp=GLINT_READ_REG(InFIFOSpace))<(n)); \ + /* Clamp value due to bugs in PM3 */ \ + if (tmp > pGlint->FIFOSize) \ + tmp = pGlint->FIFOSize; \ + pGlint->InFifoSpace = tmp - (n); \ + } \ +}while(0) + +#define GLINTDACDelay(x) do { \ + int delay = x; \ + unsigned char tmp; \ + while(delay--){tmp = GLINT_READ_REG(InFIFOSpace);}; \ + } while(0) + +#define GLINT_MASK_WRITE_REG(v,m,r) \ + GLINT_WRITE_REG((GLINT_READ_REG(r)&(m))|(v),r) + +#define GLINT_SLOW_WRITE_REG(v,r) \ +do{ \ + mem_barrier(); \ + GLINT_WAIT(pGlint->FIFOSize); \ + mem_barrier(); \ + GLINT_WRITE_REG(v,r); \ +}while(0) + +#define GLINT_SET_INDEX(index) \ +do{ \ + GLINT_SLOW_WRITE_REG(((index)>>8)&0xff,PM2VDACIndexRegHigh); \ + GLINT_SLOW_WRITE_REG((index)&0xff,PM2VDACIndexRegLow); \ +} while(0) + +#define REPLICATE(r) \ +{ \ + if (pScrn->bitsPerPixel == 16) { \ + r &= 0xFFFF; \ + r |= (r<<16); \ + } else \ + if (pScrn->bitsPerPixel == 8) { \ + r &= 0xFF; \ + r |= (r<<8); \ + r |= (r<<16); \ + } \ +} + +#ifndef XF86DRI +#define LOADROP(rop) \ +{ \ + if (pGlint->ROP != rop) { \ + GLINT_WRITE_REG(rop<<1|UNIT_ENABLE, LogicalOpMode); \ + pGlint->ROP = rop; \ + } \ +} +#else +#define LOADROP(rop) \ + { \ + GLINT_WRITE_REG(rop<<1|UNIT_ENABLE, LogicalOpMode); \ + pGlint->ROP = rop; \ + } +#endif + +#define CHECKCLIPPING \ +{ \ + if (pGlint->ClippingOn) { \ + pGlint->ClippingOn = FALSE; \ + GLINT_WAIT(1); \ + GLINT_WRITE_REG(0, ScissorMode); \ + } \ +} + +#ifndef XF86DRI +#define DO_PLANEMASK(planemask) \ +{ \ + if (planemask != pGlint->planemask) { \ + pGlint->planemask = planemask; \ + REPLICATE(planemask); \ + GLINT_WRITE_REG(planemask, FBHardwareWriteMask);\ + } \ +} +#else +#define DO_PLANEMASK(planemask) \ + { \ + pGlint->planemask = planemask; \ + REPLICATE(planemask); \ + GLINT_WRITE_REG(planemask, FBHardwareWriteMask);\ + } +#endif + +/* Permedia Save/Restore functions */ + +#define STOREREG(address,value) \ + pReg->glintRegs[address >> 3] = value; + +#define SAVEREG(address) \ + pReg->glintRegs[address >> 3] = GLINT_READ_REG(address); + +#define RESTOREREG(address) \ + GLINT_SLOW_WRITE_REG(pReg->glintRegs[address >> 3], address); + +#define STOREDAC(address,value) \ + pReg->DacRegs[address] = value; + +#define P2VOUT(address) \ + Permedia2vOutIndReg(pScrn, address, 0x00, pReg->DacRegs[address]); + +#define P2VIN(address) \ + pReg->DacRegs[address] = Permedia2vInIndReg(pScrn, address); + +/* RamDac Save/Restore functions, used by external DAC's */ + +#define STORERAMDAC(address,value) \ + ramdacReg->DacRegs[address] = value; + +/* Multi Chip access */ + +#define ACCESSCHIP1() \ + pGlint->IOOffset = 0; + +#define ACCESSCHIP2() \ + pGlint->IOOffset = 0x10000; + +#endif diff --git a/contrib/vidix/drivers/mach64.h b/contrib/vidix/drivers/mach64.h new file mode 100644 index 000000000..807efdb8d --- /dev/null +++ b/contrib/vidix/drivers/mach64.h @@ -0,0 +1,2611 @@ +/* + * mach64.h + * This software has been released under the terms of the GNU Public + * license. See http://www.gnu.org/copyleft/gpl.html for details. + * + * It's based on radeonfb, X11, GATOS sources +*/ + +#ifndef __MACH64_INCLUDED +#define __MACH64_INCLUDED 1 + +/* Note: this model of accessing to IO space is based on MMIO technology. +This means that this sources don't support ISA and VLB cards */ +#define BlockIOTag(val) (val) +#define IOPortTag(sparce,val) (val) + +/* MDA/[M]CGA/EGA/VGA I/O ports */ +#define GENVS 0x0102u /* Write (and Read on uC only) */ + +#define R_GENLPS 0x03b9u /* Read */ + +#define GENHP 0x03bfu + +#define ATTRX 0x03c0u +#define ATTRD 0x03c1u +#define GENS0 0x03c2u /* Read */ +#define GENMO 0x03c2u /* Write */ +#define GENENB 0x03c3u /* Read */ +#define SEQX 0x03c4u +#define SEQD 0x03c5u +#define VGA_DAC_MASK 0x03c6u +#define VGA_DAC_READ 0x03c7u +#define VGA_DAC_WRITE 0x03c8u +#define VGA_DAC_DATA 0x03c9u +#define R_GENFC 0x03cau /* Read */ +/* ? 0x03cbu */ +#define R_GENMO 0x03ccu /* Read */ +/* ? 0x03cdu */ +#define GRAX 0x03ceu +#define GRAD 0x03cfu + +#define GENB 0x03d9u + +#define GENLPS 0x03dcu /* Write */ +#define KCX 0x03ddu +#define KCD 0x03deu + +#define GENENA 0x46e8u /* Write */ + +/* I/O port base numbers */ +#define MonochromeIOBase 0x03b0u +#define ColourIOBase 0x03d0u + +/* Other MDA/[M]CGA/EGA/VGA I/O ports */ +/* ?(_IOBase) ((_IOBase) + 0x00u) */ /* CRTX synonym */ +/* ?(_IOBase) ((_IOBase) + 0x01u) */ /* CRTD synonym */ +/* ?(_IOBase) ((_IOBase) + 0x02u) */ /* CRTX synonym */ +/* ?(_IOBase) ((_IOBase) + 0x03u) */ /* CRTD synonym */ +#define CRTX(_IOBase) ((_IOBase) + 0x04u) +#define CRTD(_IOBase) ((_IOBase) + 0x05u) +/* ?(_IOBase) ((_IOBase) + 0x06u) */ +/* ?(_IOBase) ((_IOBase) + 0x07u) */ +#define GENMC(_IOBase) ((_IOBase) + 0x08u) +/* ?(_IOBase) ((_IOBase) + 0x09u) */ /* R_GENLPS/GENB */ +#define GENS1(_IOBase) ((_IOBase) + 0x0au) /* Read */ +#define GENFC(_IOBase) ((_IOBase) + 0x0au) /* Write */ +#define GENLPC(_IOBase) ((_IOBase) + 0x0bu) +/* ?(_IOBase) ((_IOBase) + 0x0cu) */ /* /GENLPS */ +/* ?(_IOBase) ((_IOBase) + 0x0du) */ /* /KCX */ +/* ?(_IOBase) ((_IOBase) + 0x0eu) */ /* /KCD */ +/* ?(_IOBase) ((_IOBase) + 0x0fu) */ /* GENHP/ */ + +/* 8514/A VESA approved register definitions */ +#define DISP_STAT 0x02e8u /* Read */ +#define SENSE 0x0001u /* Presumably belong here */ +#define VBLANK 0x0002u +#define HORTOG 0x0004u +#define H_TOTAL 0x02e8u /* Write */ +#define IBM_DAC_MASK 0x02eau +#define IBM_DAC_READ 0x02ebu +#define IBM_DAC_WRITE 0x02ecu +#define IBM_DAC_DATA 0x02edu +#define H_DISP 0x06e8u /* Write */ +#define H_SYNC_STRT 0x0ae8u /* Write */ +#define H_SYNC_WID 0x0ee8u /* Write */ +#define HSYNCPOL_POS 0x0000u +#define HSYNCPOL_NEG 0x0020u +#define H_POLARITY_POS HSYNCPOL_POS /* Sigh */ +#define H_POLARITY_NEG HSYNCPOL_NEG /* Sigh */ +#define V_TOTAL 0x12e8u /* Write */ +#define V_DISP 0x16e8u /* Write */ +#define V_SYNC_STRT 0x1ae8u /* Write */ +#define V_SYNC_WID 0x1ee8u /* Write */ +#define VSYNCPOL_POS 0x0000u +#define VSYNCPOL_NEG 0x0020u +#define V_POLARITY_POS VSYNCPOL_POS /* Sigh */ +#define V_POLARITY_NEG VSYNCPOL_NEG /* Sigh */ +#define DISP_CNTL 0x22e8u /* Write */ +#define ODDBNKENAB 0x0001u +#define MEMCFG_2 0x0000u +#define MEMCFG_4 0x0002u +#define MEMCFG_6 0x0004u +#define MEMCFG_8 0x0006u +#define DBLSCAN 0x0008u +#define INTERLACE 0x0010u +#define DISPEN_NC 0x0000u +#define DISPEN_ENAB 0x0020u +#define DISPEN_DISAB 0x0040u +#define R_H_TOTAL 0x26e8u /* Read */ +/* ? 0x2ae8u */ +/* ? 0x2ee8u */ +/* ? 0x32e8u */ +/* ? 0x36e8u */ +/* ? 0x3ae8u */ +/* ? 0x3ee8u */ +#define SUBSYS_STAT 0x42e8u /* Read */ +#define VBLNKFLG 0x0001u +#define PICKFLAG 0x0002u +#define INVALIDIO 0x0004u +#define GPIDLE 0x0008u +#define MONITORID_MASK 0x0070u +/* MONITORID_? 0x0000u */ +#define MONITORID_8507 0x0010u +#define MONITORID_8514 0x0020u +/* MONITORID_? 0x0030u */ +/* MONITORID_? 0x0040u */ +#define MONITORID_8503 0x0050u +#define MONITORID_8512 0x0060u +#define MONITORID_8513 0x0060u +#define MONITORID_NONE 0x0070u +#define _8PLANE 0x0080u +#define SUBSYS_CNTL 0x42e8u /* Write */ +#define RVBLNKFLG 0x0001u +#define RPICKFLAG 0x0002u +#define RINVALIDIO 0x0004u +#define RGPIDLE 0x0008u +#define IVBLNKFLG 0x0100u +#define IPICKFLAG 0x0200u +#define IINVALIDIO 0x0400u +#define IGPIDLE 0x0800u +#define CHPTEST_NC 0x0000u +#define CHPTEST_NORMAL 0x1000u +#define CHPTEST_ENAB 0x2000u +#define GPCTRL_NC 0x0000u +#define GPCTRL_ENAB 0x4000u +#define GPCTRL_RESET 0x8000u +#define ROM_PAGE_SEL 0x46e8u /* Write */ +#define ADVFUNC_CNTL 0x4ae8u /* Write */ +#define DISABPASSTHRU 0x0001u +#define CLOKSEL 0x0004u +/* ? 0x4ee8u */ +#define EXT_CONFIG_0 0x52e8u /* C & T 82C480 */ +#define EXT_CONFIG_1 0x56e8u /* C & T 82C480 */ +#define EXT_CONFIG_2 0x5ae8u /* C & T 82C480 */ +#define EXT_CONFIG_3 0x5ee8u /* C & T 82C480 */ +/* ? 0x62e8u */ +/* ? 0x66e8u */ +/* ? 0x6ae8u */ +/* ? 0x6ee8u */ +/* ? 0x72e8u */ +/* ? 0x76e8u */ +/* ? 0x7ae8u */ +/* ? 0x7ee8u */ +#define CUR_Y 0x82e8u +#define CUR_X 0x86e8u +#define DESTY_AXSTP 0x8ae8u /* Write */ +#define DESTX_DIASTP 0x8ee8u /* Write */ +#define ERR_TERM 0x92e8u +#define MAJ_AXIS_PCNT 0x96e8u /* Write */ +#define GP_STAT 0x9ae8u /* Read */ +#define GE_STAT 0x9ae8u /* Alias */ +#define DATARDY 0x0100u +#define DATA_READY DATARDY /* Alias */ +#define GPBUSY 0x0200u +#define CMD 0x9ae8u /* Write */ +#define WRTDATA 0x0001u +#define PLANAR 0x0002u +#define LASTPIX 0x0004u +#define LINETYPE 0x0008u +#define DRAW 0x0010u +#define INC_X 0x0020u +#define YMAJAXIS 0x0040u +#define INC_Y 0x0080u +#define PCDATA 0x0100u +#define _16BIT 0x0200u +#define CMD_NOP 0x0000u +#define CMD_OP_MSK 0xf000u +#define BYTSEQ 0x1000u +#define CMD_LINE 0x2000u +#define CMD_RECT 0x4000u +#define CMD_RECTV1 0x6000u +#define CMD_RECTV2 0x8000u +#define CMD_LINEAF 0xa000u +#define CMD_BITBLT 0xc000u +#define SHORT_STROKE 0x9ee8u /* Write */ +#define SSVDRAW 0x0010u +#define VECDIR_000 0x0000u +#define VECDIR_045 0x0020u +#define VECDIR_090 0x0040u +#define VECDIR_135 0x0060u +#define VECDIR_180 0x0080u +#define VECDIR_225 0x00a0u +#define VECDIR_270 0x00c0u +#define VECDIR_315 0x00e0u +#define BKGD_COLOR 0xa2e8u /* Write */ +#define FRGD_COLOR 0xa6e8u /* Write */ +#define WRT_MASK 0xaae8u /* Write */ +#define RD_MASK 0xaee8u /* Write */ +#define COLOR_CMP 0xb2e8u /* Write */ +#define BKGD_MIX 0xb6e8u /* Write */ +/* 0x001fu See MIX_* definitions below */ +#define BSS_BKGDCOL 0x0000u +#define BSS_FRGDCOL 0x0020u +#define BSS_PCDATA 0x0040u +#define BSS_BITBLT 0x0060u +#define FRGD_MIX 0xbae8u /* Write */ +/* 0x001fu See MIX_* definitions below */ +#define FSS_BKGDCOL 0x0000u +#define FSS_FRGDCOL 0x0020u +#define FSS_PCDATA 0x0040u +#define FSS_BITBLT 0x0060u +#define MULTIFUNC_CNTL 0xbee8u /* Write */ +#define MIN_AXIS_PCNT 0x0000u +#define SCISSORS_T 0x1000u +#define SCISSORS_L 0x2000u +#define SCISSORS_B 0x3000u +#define SCISSORS_R 0x4000u +#define M32_MEM_CNTL 0x5000u +#define HORCFG_4 0x0000u +#define HORCFG_5 0x0001u +#define HORCFG_8 0x0002u +#define HORCFG_10 0x0003u +#define VRTCFG_2 0x0000u +#define VRTCFG_4 0x0004u +#define VRTCFG_6 0x0008u +#define VRTCFG_8 0x000cu +#define BUFSWP 0x0010u +#define PATTERN_L 0x8000u +#define PATTERN_H 0x9000u +#define PIX_CNTL 0xa000u +#define PLANEMODE 0x0004u +#define COLCMPOP_F 0x0000u +#define COLCMPOP_T 0x0008u +#define COLCMPOP_GE 0x0010u +#define COLCMPOP_LT 0x0018u +#define COLCMPOP_NE 0x0020u +#define COLCMPOP_EQ 0x0028u +#define COLCMPOP_LE 0x0030u +#define COLCMPOP_GT 0x0038u +#define MIXSEL_FRGDMIX 0x0000u +#define MIXSEL_PATT 0x0040u +#define MIXSEL_EXPPC 0x0080u +#define MIXSEL_EXPBLT 0x00c0u +/* ? 0xc2e8u */ +/* ? 0xc6e8u */ +/* ? 0xcae8u */ +/* ? 0xcee8u */ +/* ? 0xd2e8u */ +/* ? 0xd6e8u */ +/* ? 0xdae8u */ +/* ? 0xdee8u */ +#define PIX_TRANS 0xe2e8u +/* ? 0xe6e8u */ +/* ? 0xeae8u */ +/* ? 0xeee8u */ +/* ? 0xf2e8u */ +/* ? 0xf6e8u */ +/* ? 0xfae8u */ +/* ? 0xfee8u */ + +/* ATI Mach8 & Mach32 register definitions */ +#define OVERSCAN_COLOR_8 0x02eeu /* Write */ /* Mach32 */ +#define OVERSCAN_BLUE_24 0x02efu /* Write */ /* Mach32 */ +#define OVERSCAN_GREEN_24 0x06eeu /* Write */ /* Mach32 */ +#define OVERSCAN_RED_24 0x06efu /* Write */ /* Mach32 */ +#define CURSOR_OFFSET_LO 0x0aeeu /* Write */ /* Mach32 */ +#define CURSOR_OFFSET_HI 0x0eeeu /* Write */ /* Mach32 */ +#define CONFIG_STATUS_1 0x12eeu /* Read */ +#define CLK_MODE 0x0001u /* Mach8 */ +#define BUS_16 0x0002u /* Mach8 */ +#define MC_BUS 0x0004u /* Mach8 */ +#define EEPROM_ENA 0x0008u /* Mach8 */ +#define DRAM_ENA 0x0010u /* Mach8 */ +#define MEM_INSTALLED 0x0060u /* Mach8 */ +#define ROM_ENA 0x0080u /* Mach8 */ +#define ROM_PAGE_ENA 0x0100u /* Mach8 */ +#define ROM_LOCATION 0xfe00u /* Mach8 */ +#define _8514_ONLY 0x0001u /* Mach32 */ +#define BUS_TYPE 0x000eu /* Mach32 */ +#define ISA_16_BIT 0x0000u /* Mach32 */ +#define EISA 0x0002u /* Mach32 */ +#define MICRO_C_16_BIT 0x0004u /* Mach32 */ +#define MICRO_C_8_BIT 0x0006u /* Mach32 */ +#define LOCAL_386SX 0x0008u /* Mach32 */ +#define LOCAL_386DX 0x000au /* Mach32 */ +#define LOCAL_486 0x000cu /* Mach32 */ +#define PCI 0x000eu /* Mach32 */ +#define MEM_TYPE 0x0070u /* Mach32 */ +#define CHIP_DIS 0x0080u /* Mach32 */ +#define TST_VCTR_ENA 0x0100u /* Mach32 */ +#define DACTYPE 0x0e00u /* Mach32 */ +#define MC_ADR_DECODE 0x1000u /* Mach32 */ +#define CARD_ID 0xe000u /* Mach32 */ +#define HORZ_CURSOR_POSN 0x12eeu /* Write */ /* Mach32 */ +#define CONFIG_STATUS_2 0x16eeu /* Read */ +#define SHARE_CLOCK 0x0001u /* Mach8 */ +#define HIRES_BOOT 0x0002u /* Mach8 */ +#define EPROM_16_ENA 0x0004u /* Mach8 */ +#define WRITE_PER_BIT 0x0008u /* Mach8 */ +#define FLASH_ENA 0x0010u /* Mach8 */ +#define SLOW_SEQ_EN 0x0001u /* Mach32 */ +#define MEM_ADDR_DIS 0x0002u /* Mach32 */ +#define ISA_16_ENA 0x0004u /* Mach32 */ +#define KOR_TXT_MODE_ENA 0x0008u /* Mach32 */ +#define LOCAL_BUS_SUPPORT 0x0030u /* Mach32 */ +#define LOCAL_BUS_CONFIG_2 0x0040u /* Mach32 */ +#define LOCAL_BUS_RD_DLY_ENA 0x0080u /* Mach32 */ +#define LOCAL_DAC_EN 0x0100u /* Mach32 */ +#define LOCAL_RDY_EN 0x0200u /* Mach32 */ +#define EEPROM_ADR_SEL 0x0400u /* Mach32 */ +#define GE_STRAP_SEL 0x0800u /* Mach32 */ +#define VESA_RDY 0x1000u /* Mach32 */ +#define Z4GB 0x2000u /* Mach32 */ +#define LOC2_MDRAM 0x4000u /* Mach32 */ +#define VERT_CURSOR_POSN 0x16eeu /* Write */ /* Mach32 */ +#define FIFO_TEST_DATA 0x1aeeu /* Read */ /* Mach32 */ +#define CURSOR_COLOR_0 0x1aeeu /* Write */ /* Mach32 */ +#define CURSOR_COLOR_1 0x1aefu /* Write */ /* Mach32 */ +#define HORZ_CURSOR_OFFSET 0x1eeeu /* Write */ /* Mach32 */ +#define VERT_CURSOR_OFFSET 0x1eefu /* Write */ /* Mach32 */ +#define PCI_CNTL 0x22eeu /* Mach32-PCI */ +#define CRT_PITCH 0x26eeu /* Write */ +#define CRT_OFFSET_LO 0x2aeeu /* Write */ +#define CRT_OFFSET_HI 0x2eeeu /* Write */ +#define LOCAL_CNTL 0x32eeu /* Mach32 */ +#define FIFO_OPT 0x36eeu /* Write */ /* Mach8 */ +#define MISC_OPTIONS 0x36eeu /* Mach32 */ +#define W_STATE_ENA 0x0000u /* Mach32 */ +#define HOST_8_ENA 0x0001u /* Mach32 */ +#define MEM_SIZE_ALIAS 0x000cu /* Mach32 */ +#define MEM_SIZE_512K 0x0000u /* Mach32 */ +#define MEM_SIZE_1M 0x0004u /* Mach32 */ +#define MEM_SIZE_2M 0x0008u /* Mach32 */ +#define MEM_SIZE_4M 0x000cu /* Mach32 */ +#define DISABLE_VGA 0x0010u /* Mach32 */ +#define _16_BIT_IO 0x0020u /* Mach32 */ +#define DISABLE_DAC 0x0040u /* Mach32 */ +#define DLY_LATCH_ENA 0x0080u /* Mach32 */ +#define TEST_MODE 0x0100u /* Mach32 */ +#define BLK_WR_ENA 0x0400u /* Mach32 */ +#define _64_DRAW_ENA 0x0800u /* Mach32 */ +#define FIFO_TEST_TAG 0x3aeeu /* Read */ /* Mach32 */ +#define EXT_CURSOR_COLOR_0 0x3aeeu /* Write */ /* Mach32 */ +#define EXT_CURSOR_COLOR_1 0x3eeeu /* Write */ /* Mach32 */ +#define MEM_BNDRY 0x42eeu /* Mach32 */ +#define MEM_PAGE_BNDRY 0x000fu /* Mach32 */ +#define MEM_BNDRY_ENA 0x0010u /* Mach32 */ +#define SHADOW_CTL 0x46eeu /* Write */ +#define CLOCK_SEL 0x4aeeu +/* DISABPASSTHRU 0x0001u See ADVFUNC_CNTL */ +#define VFIFO_DEPTH_1 0x0100u /* Mach32 */ +#define VFIFO_DEPTH_2 0x0200u /* Mach32 */ +#define VFIFO_DEPTH_3 0x0300u /* Mach32 */ +#define VFIFO_DEPTH_4 0x0400u /* Mach32 */ +#define VFIFO_DEPTH_5 0x0500u /* Mach32 */ +#define VFIFO_DEPTH_6 0x0600u /* Mach32 */ +#define VFIFO_DEPTH_7 0x0700u /* Mach32 */ +#define VFIFO_DEPTH_8 0x0800u /* Mach32 */ +#define VFIFO_DEPTH_9 0x0900u /* Mach32 */ +#define VFIFO_DEPTH_A 0x0a00u /* Mach32 */ +#define VFIFO_DEPTH_B 0x0b00u /* Mach32 */ +#define VFIFO_DEPTH_C 0x0c00u /* Mach32 */ +#define VFIFO_DEPTH_D 0x0d00u /* Mach32 */ +#define VFIFO_DEPTH_E 0x0e00u /* Mach32 */ +#define VFIFO_DEPTH_F 0x0f00u /* Mach32 */ +#define COMPOSITE_SYNC 0x1000u +/* ? 0x4eeeu */ +#define ROM_ADDR_1 0x52eeu +#define BIOS_BASE_SEGMENT 0x007fu /* Mach32 */ +/* ? 0xff80u */ /* Mach32 */ +#define ROM_ADDR_2 0x56eeu /* Sick ... */ +#define SHADOW_SET 0x5aeeu /* Write */ +#define MEM_CFG 0x5eeeu /* Mach32 */ +#define MEM_APERT_SEL 0x0003u /* Mach32 */ +#define MEM_APERT_PAGE 0x000cu /* Mach32 */ +#define MEM_APERT_LOC 0xfff0u /* Mach32 */ +#define EXT_GE_STATUS 0x62eeu /* Read */ /* Mach32 */ +#define HORZ_OVERSCAN 0x62eeu /* Write */ /* Mach32 */ +#define VERT_OVERSCAN 0x66eeu /* Write */ /* Mach32 */ +#define MAX_WAITSTATES 0x6aeeu +#define GE_OFFSET_LO 0x6eeeu /* Write */ +#define BOUNDS_LEFT 0x72eeu /* Read */ +#define GE_OFFSET_HI 0x72eeu /* Write */ +#define BOUNDS_TOP 0x76eeu /* Read */ +#define GE_PITCH 0x76eeu /* Write */ +#define BOUNDS_RIGHT 0x7aeeu /* Read */ +#define EXT_GE_CONFIG 0x7aeeu /* Write */ /* Mach32 */ +#define MONITOR_ALIAS 0x0007u /* Mach32 */ +/* MONITOR_? 0x0000u */ /* Mach32 */ +#define MONITOR_8507 0x0001u /* Mach32 */ +#define MONITOR_8514 0x0002u /* Mach32 */ +/* MONITOR_? 0x0003u */ /* Mach32 */ +/* MONITOR_? 0x0004u */ /* Mach32 */ +#define MONITOR_8503 0x0005u /* Mach32 */ +#define MONITOR_8512 0x0006u /* Mach32 */ +#define MONITOR_8513 0x0006u /* Mach32 */ +#define MONITOR_NONE 0x0007u /* Mach32 */ +#define ALIAS_ENA 0x0008u /* Mach32 */ +#define PIXEL_WIDTH_4 0x0000u /* Mach32 */ +#define PIXEL_WIDTH_8 0x0010u /* Mach32 */ +#define PIXEL_WIDTH_16 0x0020u /* Mach32 */ +#define PIXEL_WIDTH_24 0x0030u /* Mach32 */ +#define RGB16_555 0x0000u /* Mach32 */ +#define RGB16_565 0x0040u /* Mach32 */ +#define RGB16_655 0x0080u /* Mach32 */ +#define RGB16_664 0x00c0u /* Mach32 */ +#define MULTIPLEX_PIXELS 0x0100u /* Mach32 */ +#define RGB24 0x0000u /* Mach32 */ +#define RGBx24 0x0200u /* Mach32 */ +#define BGR24 0x0400u /* Mach32 */ +#define xBGR24 0x0600u /* Mach32 */ +#define DAC_8_BIT_EN 0x4000u /* Mach32 */ +#define ORDER_16BPP_565 RGB16_565 /* Mach32 */ +#define BOUNDS_BOTTOM 0x7eeeu /* Read */ +#define MISC_CNTL 0x7eeeu /* Write */ /* Mach32 */ +#define PATT_DATA_INDEX 0x82eeu +/* ? 0x86eeu */ +/* ? 0x8aeeu */ +#define R_EXT_GE_CONFIG 0x8eeeu /* Read */ /* Mach32 */ +#define PATT_DATA 0x8eeeu /* Write */ +#define R_MISC_CNTL 0x92eeu /* Read */ /* Mach32 */ +#define BRES_COUNT 0x96eeu +#define EXT_FIFO_STATUS 0x9aeeu /* Read */ +#define LINEDRAW_INDEX 0x9aeeu /* Write */ +/* ? 0x9eeeu */ +#define LINEDRAW_OPT 0xa2eeu +#define BOUNDS_RESET 0x0100u +#define CLIP_MODE_0 0x0000u /* Clip exception disabled */ +#define CLIP_MODE_1 0x0200u /* Line segments */ +#define CLIP_MODE_2 0x0400u /* Polygon boundary lines */ +#define CLIP_MODE_3 0x0600u /* Patterned lines */ +#define DEST_X_START 0xa6eeu /* Write */ +#define DEST_X_END 0xaaeeu /* Write */ +#define DEST_Y_END 0xaeeeu /* Write */ +#define R_H_TOTAL_DISP 0xb2eeu /* Read */ /* Mach32 */ +#define SRC_X_STRT 0xb2eeu /* Write */ +#define R_H_SYNC_STRT 0xb6eeu /* Read */ /* Mach32 */ +#define ALU_BG_FN 0xb6eeu /* Write */ +#define R_H_SYNC_WID 0xbaeeu /* Read */ /* Mach32 */ +#define ALU_FG_FN 0xbaeeu /* Write */ +#define SRC_X_END 0xbeeeu /* Write */ +#define R_V_TOTAL 0xc2eeu /* Read */ +#define SRC_Y_DIR 0xc2eeu /* Write */ +#define R_V_DISP 0xc6eeu /* Read */ /* Mach32 */ +#define EXT_SHORT_STROKE 0xc6eeu /* Write */ +#define R_V_SYNC_STRT 0xcaeeu /* Read */ /* Mach32 */ +#define SCAN_X 0xcaeeu /* Write */ +#define VERT_LINE_CNTR 0xceeeu /* Read */ /* Mach32 */ +#define DP_CONFIG 0xceeeu /* Write */ +#define READ_WRITE 0x0001u +#define DATA_WIDTH 0x0200u +#define DATA_ORDER 0x1000u +#define FG_COLOR_SRC_FG 0x2000u +#define FG_COLOR_SRC_BLIT 0x6000u +#define R_V_SYNC_WID 0xd2eeu /* Read */ +#define PATT_LENGTH 0xd2eeu /* Write */ +#define PATT_INDEX 0xd6eeu /* Write */ +#define READ_SRC_X 0xdaeeu /* Read */ /* Mach32 */ +#define EXT_SCISSOR_L 0xdaeeu /* Write */ +#define READ_SRC_Y 0xdeeeu /* Read */ /* Mach32 */ +#define EXT_SCISSOR_T 0xdeeeu /* Write */ +#define EXT_SCISSOR_R 0xe2eeu /* Write */ +#define EXT_SCISSOR_B 0xe6eeu /* Write */ +/* ? 0xeaeeu */ +#define DEST_COMP_FN 0xeeeeu /* Write */ +#define DEST_COLOR_CMP_MASK 0xf2eeu /* Write */ /* Mach32 */ +/* ? 0xf6eeu */ +#define CHIP_ID 0xfaeeu /* Read */ /* Mach32 */ +#define CHIP_CODE_0 0x001fu /* Mach32 */ +#define CHIP_CODE_1 0x03e0u /* Mach32 */ +#define CHIP_CLASS 0x0c00u /* Mach32 */ +#define CHIP_REV 0xf000u /* Mach32 */ +#define LINEDRAW 0xfeeeu /* Write */ + +/* ATI Mach64 register definitions */ +#define CRTC_H_TOTAL_DISP IOPortTag(0x00u, 0x00u) +# define CRTC_H_TOTAL 0x000001fful +/* ? 0x0000fe00ul */ +# define CRTC_H_DISP 0x01ff0000ul +/* ? 0xfe000000ul */ +#define CRTC_H_SYNC_STRT_WID IOPortTag(0x01u, 0x01u) +# define CRTC_H_SYNC_STRT 0x000000fful +# define CRTC_H_SYNC_DLY 0x00000700ul +/* ? 0x00000800ul */ +# define CRTC_H_SYNC_STRT_HI 0x00001000ul +/* ? 0x0000e000ul */ +# define CRTC_H_SYNC_WID 0x001f0000ul +# define CRTC_H_SYNC_POL 0x00200000ul +/* ? 0xffc00000ul */ +#define CRTC_V_TOTAL_DISP IOPortTag(0x02u, 0x02u) +# define CRTC_V_TOTAL 0x000007fful +/* ? 0x0000f800ul */ +# define CRTC_V_DISP 0x07ff0000ul +/* ? 0xf8000000ul */ +#define CRTC_V_SYNC_STRT_WID IOPortTag(0x03u, 0x03u) +# define CRTC_V_SYNC_STRT 0x000007fful +/* ? 0x0000f800ul */ +# define CRTC_V_SYNC_WID 0x001f0000ul +# define CRTC_V_SYNC_POL 0x00200000ul +/* ? 0xffc00000ul */ +#define CRTC_VLINE_CRNT_VLINE IOPortTag(0x04u, 0x04u) +#define CRTC_VLINE 0x000007fful +/* ? 0x0000f800ul */ +#define CRTC_CRNT_VLINE 0x07ff0000ul +/* ? 0xf8000000ul */ +#define CRTC_OFF_PITCH IOPortTag(0x05u, 0x05u) +# define CRTC_OFFSET 0x000ffffful +# define CRTC_OFFSET_VGA 0x0003fffful +# define CRTC_OFFSET_LOCK 0x00100000ul /* XC/XL */ +/* ? 0x00200000ul */ +# define CRTC_PITCH 0xffc00000ul +#define CRTC_INT_CNTL IOPortTag(0x06u, 0x06u) +# define CRTC_VBLANK 0x00000001ul +# define CRTC_VBLANK_INT_EN 0x00000002ul +# define CRTC_VBLANK_INT 0x00000004ul +# define CRTC_VLINE_INT_EN 0x00000008ul +# define CRTC_VLINE_INT 0x00000010ul +# define CRTC_VLINE_SYNC 0x00000020ul +# define CRTC_FRAME 0x00000040ul +# define CRTC_SNAPSHOT_INT_EN 0x00000080ul /* GTPro */ +# define CRTC_SNAPSHOT_INT 0x00000100ul /* GTPro */ +# define CRTC_I2C_INT_EN 0x00000200ul /* GTPro */ +# define CRTC_I2C_INT 0x00000400ul /* GTPro */ +# define CRTC2_VBLANK 0x00000800ul /* LTPro */ +# define CRTC2_VBLANK_INT_EN 0x00001000ul /* LTPro */ +# define CRTC2_VBLANK_INT 0x00002000ul /* LTPro */ +# define CRTC2_VLINE_INT_EN 0x00004000ul /* LTPro */ +# define CRTC2_VLINE_INT 0x00008000ul /* LTPro */ +# define CRTC_CAPBUF0_INT_EN 0x00010000ul /* VT/GT */ +# define CRTC_CAPBUF0_INT 0x00020000ul /* VT/GT */ +# define CRTC_CAPBUF1_INT_EN 0x00040000ul /* VT/GT */ +# define CRTC_CAPBUF1_INT 0x00080000ul /* VT/GT */ +# define CRTC_OVERLAY_EOF_INT_EN 0x00100000ul /* VT/GT */ +# define CRTC_OVERLAY_EOF_INT 0x00200000ul /* VT/GT */ +# define CRTC_ONESHOT_CAP_INT_EN 0x00400000ul /* VT/GT */ +# define CRTC_ONESHOT_CAP_INT 0x00800000ul /* VT/GT */ +# define CRTC_BUSMASTER_EOL_INT_EN 0x01000000ul /* VTB/GTB/LT */ +# define CRTC_BUSMASTER_EOL_INT 0x02000000ul /* VTB/GTB/LT */ +# define CRTC_GP_INT_EN 0x04000000ul /* VTB/GTB/LT */ +# define CRTC_GP_INT 0x08000000ul /* VTB/GTB/LT */ +# define CRTC2_VLINE_SYNC 0x10000000ul /* LTPro */ +# define CRTC_SNAPSHOT2_INT_EN 0x20000000ul /* LTPro */ +# define CRTC_SNAPSHOT2_INT 0x40000000ul /* LTPro */ +# define CRTC_VBLANK_BIT2_INT 0x80000000ul /* GTPro */ +# define CRTC_INT_ENS /* *** UPDATE ME *** */ \ + ( \ + CRTC_VBLANK_INT_EN | \ + CRTC_VLINE_INT_EN | \ + CRTC_SNAPSHOT_INT_EN | \ + CRTC_I2C_INT_EN | \ + CRTC2_VBLANK_INT_EN | \ + CRTC2_VLINE_INT_EN | \ + CRTC_CAPBUF0_INT_EN | \ + CRTC_CAPBUF1_INT_EN | \ + CRTC_OVERLAY_EOF_INT_EN | \ + CRTC_ONESHOT_CAP_INT_EN | \ + CRTC_BUSMASTER_EOL_INT_EN | \ + CRTC_GP_INT_EN | \ + CRTC_SNAPSHOT2_INT_EN | \ + 0 \ + ) +# define CRTC_INT_ACKS /* *** UPDATE ME *** */ \ + ( \ + CRTC_VBLANK_INT | \ + CRTC_VLINE_INT | \ + CRTC_SNAPSHOT_INT | \ + CRTC_I2C_INT | \ + CRTC2_VBLANK_INT | \ + CRTC2_VLINE_INT | \ + CRTC_CAPBUF0_INT | \ + CRTC_CAPBUF1_INT | \ + CRTC_OVERLAY_EOF_INT | \ + CRTC_ONESHOT_CAP_INT | \ + CRTC_BUSMASTER_EOL_INT | \ + CRTC_GP_INT | \ + CRTC_SNAPSHOT2_INT | \ + CRTC_VBLANK_BIT2_INT | \ + 0 \ + ) +#define CRTC_GEN_CNTL IOPortTag(0x07u, 0x07u) +# define CRTC_DBL_SCAN_EN 0x00000001ul +# define CRTC_INTERLACE_EN 0x00000002ul +# define CRTC_HSYNC_DIS 0x00000004ul +# define CRTC_VSYNC_DIS 0x00000008ul +# define CRTC_CSYNC_EN 0x00000010ul +# define CRTC_PIX_BY_2_EN 0x00000020ul +# define CRTC2_DBL_SCAN_EN 0x00000020ul /* LTPro */ +# define CRTC_DISPLAY_DIS 0x00000040ul +# define CRTC_VGA_XOVERSCAN 0x00000080ul +# define CRTC_PIX_WIDTH 0x00000700ul +# define CRTC_BYTE_PIX_ORDER 0x00000800ul +# define CRTC_VSYNC_INT_EN 0x00001000ul /* XC/XL */ +# define CRTC_VSYNC_INT 0x00002000ul /* XC/XL */ +# define CRTC_FIFO_OVERFILL 0x0000c000ul /* VT/GT */ +# define CRTC2_VSYNC_INT_EN 0x00004000ul /* XC/XL */ +# define CRTC2_VSYNC_INT 0x00008000ul /* XC/XL */ +# define CRTC_FIFO_LWM 0x000f0000ul +# define CRTC_HVSYNC_IO_DRIVE 0x00010000ul /* XC/XL */ +# define CRTC2_PIX_WIDTH 0x000e0000ul /* LTPro */ +# define CRTC_VGA_128KAP_PAGING 0x00100000ul /* VT/GT */ +# define CRTC_DISPREQ_ONLY 0x00200000ul /* VT/GT */ +# define CRTC_VFC_SYNC_TRISTATE 0x00200000ul /* VTB/GTB/LT */ +# define CRTC2_EN 0x00200000ul /* LTPro */ +# define CRTC_LOCK_REGS 0x00400000ul /* VT/GT */ +# define CRTC_SYNC_TRISTATE 0x00800000ul /* VT/GT */ +# define CRTC_EXT_DISP_EN 0x01000000ul +# define CRTC_EN 0x02000000ul +# define CRTC_DISP_REQ_EN 0x04000000ul +# define CRTC_VGA_LINEAR 0x08000000ul +# define CRTC_VSYNC_FALL_EDGE 0x10000000ul +# define CRTC_VGA_TEXT_132 0x20000000ul +# define CRTC_CNT_EN 0x40000000ul +# define CRTC_CUR_B_TEST 0x80000000ul +# define CRTC_INT_ENS_X /* *** UPDATE ME *** */ \ + ( \ + CRTC_VSYNC_INT_EN | \ + CRTC2_VSYNC_INT_EN | \ + 0 \ + ) +# define CRTC_INT_ACKS_X /* *** UPDATE ME *** */ \ + ( \ + CRTC_VSYNC_INT | \ + CRTC2_VSYNC_INT | \ + 0 \ + ) +#define DSP_CONFIG BlockIOTag(0x08u) /* VTB/GTB/LT */ +# define DSP_XCLKS_PER_QW 0x00003ffful +/* ? 0x00004000ul */ +# define DSP_FLUSH_WB 0x00008000ul +# define DSP_LOOP_LATENCY 0x000f0000ul +# define DSP_PRECISION 0x00700000ul +/* ? 0xff800000ul */ +#define DSP_ON_OFF BlockIOTag(0x09u) /* VTB/GTB/LT */ +# define DSP_OFF 0x000007fful +/* ? 0x0000f800ul */ +# define DSP_ON 0x07ff0000ul +/* ? 0xf8000000ul */ +#define TIMER_CONFIG BlockIOTag(0x0au) /* VTB/GTB/LT */ +#define MEM_BUF_CNTL BlockIOTag(0x0bu) /* VTB/GTB/LT */ +#define SHARED_CNTL BlockIOTag(0x0cu) /* VTB/GTB/LT */ +#define SHARED_MEM_CONFIG BlockIOTag(0x0du) /* VTB/GTB/LT */ +#define MEM_ADDR_CONFIG BlockIOTag(0x0du) /* GTPro */ +#define SHARED_CNTL_CTD BlockIOTag(0x0eu) /* CTD */ +/* ? 0x00fffffful */ +#define CTD_FIFO5 0x01000000ul +/* ? 0xfe000000ul */ +#define CRT_TRAP BlockIOTag(0x0eu) /* VTB/GTB/LT */ +#define DSTN_CONTROL BlockIOTag(0x0fu) /* LT */ +#define I2C_CNTL_0 BlockIOTag(0x0fu) /* GTPro */ +#define OVR_CLR IOPortTag(0x08u, 0x10u) +# define OVR_CLR_8 0x000000fful +# define OVR_CLR_B 0x0000ff00ul +# define OVR_CLR_G 0x00ff0000ul +# define OVR_CLR_R 0xff000000ul +#define OVR_WID_LEFT_RIGHT IOPortTag(0x09u, 0x11u) +# define OVR_WID_LEFT 0x0000003ful /* 0x0f on <LT */ +/* ? 0x0000ffc0ul */ +# define OVR_WID_RIGHT 0x003f0000ul /* 0x0f0000 on <LT */ +/* ? 0xffc00000ul */ +#define OVR_WID_TOP_BOTTOM IOPortTag(0x0au, 0x12u) +# define OVR_WID_TOP 0x000001fful /* 0x00ff on <LT */ +/* ? 0x0000fe00ul */ +# define OVR_WID_BOTTOM 0x01ff0000ul /* 0x00ff0000 on <LT */ +/* ? 0xfe000000ul */ +#define VGA_DSP_CONFIG BlockIOTag(0x13u) /* VTB/GTB/LT */ +# define VGA_DSP_XCLKS_PER_QW DSP_XCLKS_PER_QW +/* ? 0x000fc000ul */ +# define VGA_DSP_PREC_PCLKBY2 0x00700000ul +/* ? 0x00800000ul */ +# define VGA_DSP_PREC_PCLK 0x07000000ul +/* ? 0xf8000000ul */ +#define VGA_DSP_ON_OFF BlockIOTag(0x14u) /* VTB/GTB/LT */ +# define VGA_DSP_OFF DSP_OFF +/* ? 0x0000f800ul */ +# define VGA_DSP_ON DSP_ON +/* ? 0xf8000000ul */ +#define DSP2_CONFIG BlockIOTag(0x15u) /* LTPro */ +#define DSP2_ON_OFF BlockIOTag(0x16u) /* LTPro */ +#define EXT_CRTC_GEN_CNTL BlockIOTag(0x17u) /* VT-A4 (W) */ +#define CRTC2_OFF_PITCH BlockIOTag(0x17u) /* LTPro */ +#define CUR_CLR0 IOPortTag(0x0bu, 0x18u) +#define CUR_CLR1 IOPortTag(0x0cu, 0x19u) +/* These are for both CUR_CLR0 and CUR_CLR1 */ +# define CUR_CLR_I 0x000000fful +# define CUR_CLR_B 0x0000ff00ul +# define CUR_CLR_G 0x00ff0000ul +# define CUR_CLR_R 0xff000000ul +# define CUR_CLR (CUR_CLR_R | CUR_CLR_G | CUR_CLR_B) +#define CUR_OFFSET IOPortTag(0x0du, 0x1au) +#define CUR_HORZ_VERT_POSN IOPortTag(0x0eu, 0x1bu) +# define CUR_HORZ_POSN 0x000007fful +/* ? 0x0000f800ul */ +# define CUR_VERT_POSN 0x07ff0000ul +/* ? 0xf8000000ul */ +#define CUR_HORZ_VERT_OFF IOPortTag(0x0fu, 0x1cu) +# define CUR_HORZ_OFF 0x0000007ful +/* ? 0x0000ff80ul */ +# define CUR_VERT_OFF 0x007f0000ul +/* ? 0xff800000ul */ +#define CONFIG_PANEL BlockIOTag(0x1du) /* LT */ +# define PANEL_FORMAT 0x00000007ul +/* ? 0x00000008ul */ +# define PANEL_TYPE 0x000000f0ul +# define NO_OF_GREY 0x00000700ul +# define MOD_GEN 0x00001800ul +# define EXT_LVDS_CLK 0x00001800ul /* LTPro */ +# define BLINK_RATE 0x00006000ul +# define BLINK_RATE_PRO 0x00002000ul /* LTPro */ +# define DONT_SHADOW_HEND 0x00004000ul /* LTPro */ +# define DONT_USE_F32KHZ 0x00008000ul +# define LCD_IO_DRIVE 0x00008000ul /* XC/XL */ +# define FP_POL 0x00010000ul +# define LP_POL 0x00020000ul +# define DTMG_POL 0x00040000ul +# define SCK_POL 0x00080000ul +# define DITHER_SEL 0x00300000ul +# define INVERSE_VIDEO_EN 0x00400000ul +# define BL_CLK_SEL 0x01800000ul +# define BL_LEVEL 0x0e000000ul +# define BL_CLK_SEL_PRO 0x00800000ul /* LTPro */ +# define BL_LEVEL_PRO 0x03000000ul /* LTPro */ +# define BIAS_LEVEL_PRO 0x0c000000ul /* LTPro */ +# define HSYNC_DELAY 0xf0000000ul +#define TV_OUT_INDEX BlockIOTag(0x1du) /* LTPro */ +# define TV_REG_INDEX 0x000000fful +# define TV_ON 0x00000100ul +/* ? 0xfffffe00ul */ +#define GP_IO IOPortTag(0x1eu, 0x1eu) /* VT/GT */ +#define GP_IO_CNTL BlockIOTag(0x1fu) /* VT/GT */ +#define HW_DEBUG BlockIOTag(0x1fu) /* VTB/GTB/LT */ +# define FAST_SRCCOPY_DIS 0x00000001ul +# define BYPASS_SUBPIC_DBF 0x00000001ul /* XL/XC */ +# define SRC_AUTONA_FIX_DIS 0x00000002ul +# define SYNC_PD_EN 0x00000002ul /* Mobility */ +# define DISP_QW_FIX_DIS 0x00000004ul +# define GUIDST_WB_EXP_DIS 0x00000008ul +# define CYC_ALL_FIX_DIS 0x00000008ul /* GTPro */ +# define AGPPLL_FIX_EN 0x00000008ul /* Mobility */ +# define SRC_AUTONA_ALWAYS_EN 0x00000010ul +# define GUI_BEATS_HOST_P 0x00000010ul /* GTPro */ +# define DRV_CNTL_DQMB_WEB 0x00000020ul +# define FAST_FILL_SCISSOR_DIS 0x00000020ul /* GT2c/VT4 */ +# define INTER_BLIT_FIX_DIS 0x00000020ul /* GTPro */ +# define DRV_CNTL_MA 0x00000040ul +# define AUTO_BLKWRT_COLOR_DIS 0x00000040ul /* GT2c/VT4 */ +# define INTER_PRIM_DIS 0x00000040ul /* GTPro */ +# define DRV_CNTL_MD 0x00000080ul +# define CHG_DEV_ID 0x00000100ul +# define SRC_TRACK_DST_FIX_DIS 0x00000200ul +# define HCLK_FB_SKEW 0x00000380ul /* GT2c/VT4 */ +# define SRC_TRACK_DST_FIX_DIS_P 0x00000080ul /* GTPro */ +# define AUTO_BLKWRT_COLOR_DIS_P 0x00000100ul /* GTPro */ +# define INTER_LINE_OVERLAP_DIS 0x00000200ul /* GTPro */ +# define MEM_OE_PULLBACK 0x00000400ul +# define DBL_BUFFER_EN 0x00000400ul /* GTPro */ +# define MEM_WE_FIX_DIS 0x00000800ul +# define MEM_OE_PULLBACK_B 0x00000800ul /* GT2c/VT4 */ +# define CMDFIFO_SIZE_DIS_P 0x00000800ul /* GTPro */ +# define RD_EN_FIX_DIS 0x00001000ul +# define MEM_WE_FIX_DIS_B 0x00001000ul +# define AUTO_FF_DIS 0x00001000ul /* GTPro */ +# define CMDFIFO_SIZE_DIS 0x00002000ul /* GT2c/VT4 */ +# define AUTO_BLKWRT_DIS 0x00002000ul /* GTPro */ +# define GUI_BEATS_HOST 0x00004000ul /* GT2c/VT4 */ +# define ORED_INVLD_RB_CACHE 0x00004000ul /* GTPro */ +# define BLOCK_DBL_BUF 0x00008000ul /* GTPro */ +# define R2W_TURNAROUND_DELAY 0x00020000ul /* GT2c/VT4 */ +# define ENA_32BIT_DATA_BUS 0x00040000ul /* GT2c/VT4 */ +# define HCLK_FB_SKEW_P 0x00070000ul /* GTPro */ +# define ENA_FLASH_ROM 0x00080000ul /* GT2c/VT4 */ +# define DISABLE_SWITCH_FIX 0x00080000ul /* GTPro */ +# define MCLK_START_EN 0x00080000ul /* LTPro */ +# define SEL_VBLANK_BDL_BUF 0x00100000ul /* GTPro */ +# define CMDFIFO_64EN 0x00200000ul /* GTPro must be set if IDCT_EN */ +# define BM_FIX_DIS 0x00400000ul /* GTPro */ +# define Z_SWITCH_EN 0x00800000ul /* LTPro */ +# define FLUSH_HOST_WB 0x01000000ul /* GTPro */ +# define HW_DEBUG_WRITE_MSK_FIX_DIS 0x02000000ul /* LTPro */ +# define Z_NO_WRITE_EN 0x04000000ul /* LTPro */ +# define DISABLE_PCLK_RESET_P 0x08000000ul /* LTPro */ +# define PM_D3_SUPPORT_ENABLE_P 0x10000000ul /* LTPro */ +# define STARTCYCLE_FIX_ENABLE 0x20000000ul /* LTPro */ +# define DONT_RST_CHAREN 0x20000000ul /* XL/XC */ +# define C3_FIX_ENABLE 0x40000000ul /* LTPro */ +# define BM_HOSTRA_EN 0x40000000ul /* XL/XC */ +# define PKGBGAb 0x80000000ul /* XL/XC */ +# define AUTOEXP_HORZ_FIX 0x80000000ul /* Mobility */ +#define SCRATCH_REG0 IOPortTag(0x10u, 0x20u) +#define SCRATCH_REG1 IOPortTag(0x11u, 0x21u) +/* BIOS_BASE_SEGMENT 0x0000007ful */ /* As above */ +/* ? 0x00000f80ul */ +#define BIOS_INIT_DAC_SUBTYPE 0x0000f000ul +/* ? 0xffff0000ul */ +#define SCRATCH_REG2 BlockIOTag(0x22u) /* LT */ +#define SCRATCH_REG3 BlockIOTag(0x23u) /* GTPro */ +#define CLOCK_CNTL IOPortTag(0x12u, 0x24u) +# define CLOCK_BIT 0x00000004ul /* For ICS2595 */ +# define CLOCK_PULSE 0x00000008ul /* For ICS2595 */ +# define CLOCK_SELECT 0x0000000ful +# define CLOCK_DIVIDER 0x00000030ul +# define CLOCK_STROBE 0x00000040ul +# define CLOCK_DATA 0x00000080ul +/* ? 0x00000100ul */ +# define PLL_WR_EN 0x00000200ul /* For internal PLL */ +# define PLL_ADDR 0x0000fc00ul /* For internal PLL */ +# define PLL_DATA 0x00ff0000ul /* For internal PLL */ +/* ? 0xff000000ul */ +#define CONFIG_STAT64_1 BlockIOTag(0x25u) /* GTPro */ +# define CFG_SUBSYS_DEV_ID 0x000000fful +# define CFG_SUBSYS_VEN_ID 0x00ffff00ul +/* ? 0x1f000000ul */ +# define CFG_DIMM_TYPE 0xe0000000ul +# define CFG_PCI_SUBSYS_DEV_ID 0x0000fffful /* XC/XL */ +# define CFG_PCI_SUBSYS_VEN_ID 0xffff0000ul /* XC/XL */ +#define CONFIG_STAT64_2 BlockIOTag(0x26u) /* GTPro */ +# define CFG_DIMM_TYPE_3 0x00000001ul +/* ? 0x0000001eul */ +# define CFG_ROMWRTEN 0x00000020ul +# define CFG_AGPVCOGAIN 0x000000c0ul +# define CFG_PCI_TYPE 0x00000100ul +# define CFG_AGPSKEW 0x00000e00ul +# define CFG_X1CLKSKEW 0x00007000ul +# define CFG_PANEL_ID_P 0x000f8000ul /* LTPro */ +/* ? 0x00100000ul */ +# define CFG_PREFETCH_EN 0x00200000ul +# define CFG_ID_DISABLE 0x00400000ul +# define CFG_PRE_TESTEN 0x00800000ul +/* ? 0x01000000ul */ +# define CFG_PCI5VEN 0x02000000ul /* LTPro */ +# define CFG_VGA_DISABLE 0x04000000ul +# define CFG_ENINTB 0x08000000ul +/* ? 0x10000000ul */ +# define CFG_ROM_REMAP_2 0x20000000ul +# define CFG_IDSEL 0x40000000ul +/* ? 0x80000000ul */ +#define TV_OUT_DATA BlockIOTag(0x27u) /* LTPro */ +#define BUS_CNTL IOPortTag(0x13u, 0x28u) +# define BUS_WS 0x0000000ful +# define BUS_DBL_RESYNC 0x00000001ul /* VTB/GTB/LT */ +# define BUS_MSTR_RESET 0x00000002ul /* VTB/GTB/LT */ +# define BUS_FLUSH_BUF 0x00000004ul /* VTB/GTB/LT */ +# define BUS_STOP_REQ_DIS 0x00000008ul /* VTB/GTB/LT */ +# define BUS_ROM_WS 0x000000f0ul +# define BUS_APER_REG_DIS 0x00000010ul /* VTB/GTB/LT */ +# define BUS_EXTRA_PIPE_DIS 0x00000020ul /* VTB/GTB/LT */ +# define BUS_MASTER_DIS 0x00000040ul /* VTB/GTB/LT */ +# define BUS_ROM_WRT_EN 0x00000080ul /* GTPro */ +# define BUS_ROM_PAGE 0x00000f00ul +# define BUS_MINOR_REV_ID 0x00000700ul /* LTPro */ +# define BUS_EXT_REG_EN 0x08000000ul +/* First silicom - Prototype (A11) 0x00000000ul */ +/* Metal mask spin (A12 & A13) 0x00000100ul */ +/* All layer spin (A21) 0x00000200ul */ +/* Fast metal spin (A22) - Prod. 0x00000300ul */ +/* All layer spin (A31) 0x00000700ul */ +/* ? 0x00000800ul */ /* LTPro */ +# define BUS_CHIP_HIDDEN_REV 0x00000300ul /* XC/XL */ +/* ? 0x00001c00ul */ /* XC/XL */ +# define BUS_ROM_DIS 0x00001000ul +# define BUS_IO_16_EN 0x00002000ul /* GX */ +# define BUS_PCI_READ_RETRY_EN 0x00002000ul /* VTB/GTB/LT */ +# define BUS_DAC_SNOOP_EN 0x00004000ul +# define BUS_PCI_RETRY_EN 0x00008000ul /* VT/GT */ +# define BUS_PCI_WRT_RETRY_EN 0x00008000ul /* VTB/GTB/LT */ +# define BUS_FIFO_WS 0x000f0000ul +# define BUS_RETRY_WS 0x000f0000ul /* VTB/GTB/LT */ +# define BUS_FIFO_ERR_INT_EN 0x00100000ul +# define BUS_MSTR_RD_MULT 0x00100000ul /* VTB/GTB/LT */ +# define BUS_FIFO_ERR_INT 0x00200000ul +# define BUS_MSTR_RD_LINE 0x00200000ul /* VTB/GTB/LT */ +# define BUS_HOST_ERR_INT_EN 0x00400000ul +# define BUS_SUSPEND 0x00400000ul /* GTPro */ +# define BUS_HOST_ERR_INT 0x00800000ul +# define BUS_LAT16X 0x00800000ul /* GTPro */ +# define BUS_PCI_DAC_WS 0x07000000ul +# define BUS_RD_DISCARD_EN 0x01000000ul /* VTB/GTB/LT */ +# define BUS_RD_ABORT_EN 0x02000000ul /* VTB/GTB/LT */ +# define BUS_MSTR_WS 0x04000000ul /* VTB/GTB/LT */ +# define BUS_PCI_DAC_DLY 0x08000000ul +# define BUS_EXT_REG_EN 0x08000000ul /* VT/GT */ +# define BUS_PCI_MEMW_WS 0x10000000ul +# define BUS_MSTR_DISCONNECT_EN 0x10000000ul /* VTB/GTB/LT */ +# define BUS_PCI_BURST_DEC 0x20000000ul /* GX/CX */ +# define BUS_BURST 0x20000000ul /* 264xT */ +# define BUS_WRT_BURST 0x20000000ul /* VTB/GTB/LT */ +# define BUS_RDY_READ_DLY 0xc0000000ul +# define BUS_READ_BURST 0x40000000ul /* VTB/GTB/LT */ +# define BUS_RDY_READ_DLY_B 0x80000000ul /* VTB/GTB/LT */ +#define LCD_INDEX BlockIOTag(0x29u) /* LTPro */ +# define LCD_REG_INDEX 0x0000003ful +# define LCD_DISPLAY_DIS 0x00000100ul +# define LCD_SRC_SEL 0x00000200ul +# define LCD_SRC_SEL_CRTC1 0x00000000ul +# define LCD_SRC_SEL_CRTC2 0x00000200ul +# define LCD_CRTC2_DISPLAY_DIS 0x00000400ul +# define LCD_GUI_ACTIVE 0x00000800ul /* XC/XL */ +# define LCD_MONDET_SENSE 0x01000000ul /* XC/XL */ +# define LCD_MONDET_INT_POL 0x02000000ul /* XC/XL */ +# define LCD_MONDET_INT_EN 0x04000000ul /* XC/XL */ +# define LCD_MONDET_INT 0x08000000ul /* XC/XL */ +# define LCD_MONDET_EN 0x10000000ul /* XC/XL */ +# define LCD_EN_PL 0x20000000ul /* XC/XL */ +#define HFB_PITCH_ADDR BlockIOTag(0x2au) /* LT */ +#define LCD_DATA BlockIOTag(0x2au) /* LTPro */ +#define EXT_MEM_CNTL BlockIOTag(0x2bu) /* VTB/GTB/LT */ +#define MEM_CNTL IOPortTag(0x14u, 0x2cu) +# define CTL_MEM_SIZE 0x00000007ul +/* ? 0x00000008ul */ +# define CTL_MEM_REFRESH 0x00000078ul /* VT/GT */ +# define CTL_MEM_SIZEB 0x0000000ful /* VTB/GTB/LT */ +# define CTL_MEM_RD_LATCH_EN 0x00000010ul +# define CTL_MEM_RD_LATCH_DLY 0x00000020ul +# define CTL_MEM_LATENCY 0x00000030ul /* VTB/GTB/LT */ +# define CTL_MEM_SD_LATCH_EN 0x00000040ul +# define CTL_MEM_SD_LATCH_DLY 0x00000080ul +# define CTL_MEM_LATCH 0x000000c0ul /* VTB/GTB/LT */ +# define CTL_MEM_WDOE_CNTL 0x000000c0ul /* XC/XL */ +# define CTL_MEM_FULL_PLS 0x00000100ul +# define CTL_MEM_CYC_LNTH_AUX 0x00000180ul /* VT/GT */ +# define CTL_MEM_TRP 0x00000300ul /* VTB/GTB/LT */ +# define CTL_MEM_CYC_LNTH 0x00000600ul +# define CTL_MEM_REFRESH_RATE 0x00001800ul /* 264xT */ +# define CTL_MEM_TRCD 0x00000c00ul /* VTB/GTB/LT */ +# define CTL_MEM_WR_RDY_SEL 0x00000800ul /* GX/CX */ +# define CTL_MEM_EXT_RMW_CYC_EN 0x00001000ul /* GX/CX */ +# define CTL_MEM_TCRD 0x00001000ul /* VTB/GTB/LT */ +# define CTL_MEM_DLL_RESET 0x00002000ul /* VT/GT */ +# define CTL_MEM_TR2W 0x00002000ul /* GTPro */ +# define CTL_MEM_ACTV_PRE 0x0000c000ul /* VT/GT */ +# define CTL_MEM_CAS_PHASE 0x00004000ul /* GTPro */ +# define CTL_MEM_OE_PULLBACK 0x00008000ul /* GTPro */ +# define CTL_MEM_TWR 0x0000c000ul /* XC/XL */ +# define CTL_MEM_BNDRY 0x00030000ul +# define CTL_MEM_BNDRY_0K 0x00000000ul +# define CTL_MEM_BNDRY_256K 0x00010000ul +# define CTL_MEM_BNDRY_512K 0x00020000ul +# define CTL_MEM_BNDRY_1024K 0x00030000ul +# define CTL_MEM_DLL_GAIN_CNTL 0x00030000ul /* VT/GT */ +# define CTL_MEM_BNDRY_EN 0x00040000ul +# define CTL_MEM_SDRAM_RESET 0x00040000ul /* VT/GT */ +# define CTL_MEM_TRAS 0x00070000ul /* VTB/GTB/LT */ +# define CTL_MEM_TILE_SELECT 0x00180000ul /* VT/GT */ +# define CTL_MEM_REFRESH_DIS 0x00080000ul /* VTB/GTB/LT */ +# define CTL_MEM_LOW_LATENCY_MODE 0x00200000ul /* VT/GT */ +# define CTL_MEM_CDE_PULLBACK 0x00400000ul /* VT/GT */ +# define CTL_MEM_REFRESH_RATE_B 0x00f00000ul /* VTB/GTB/LT */ +# define CTL_MEM_PIX_WIDTH 0x07000000ul +# define CTL_MEM_LOWER_APER_ENDIAN 0x03000000ul /* VTB/GTB/LT */ +# define CTL_MEM_OE_SELECT 0x18000000ul /* VT/GT */ +# define CTL_MEM_UPPER_APER_ENDIAN 0x0c000000ul /* VTB/GTB/LT */ +/* ? 0xe0000000ul */ +# define CTL_MEM_PAGE_SIZE 0x30000000ul /* VTB/GTB/LT */ +#define MEM_VGA_WP_SEL IOPortTag(0x15u, 0x2du) +# define MEM_VGA_WPS0 0x0000fffful +# define MEM_VGA_WPS1 0xffff0000ul +#define MEM_VGA_RP_SEL IOPortTag(0x16u, 0x2eu) +# define MEM_VGA_RPS0 0x0000fffful +# define MEM_VGA_RPS1 0xffff0000ul +#define LT_GIO BlockIOTag(0x2fu) /* LT */ +#define I2C_CNTL_1 BlockIOTag(0x2fu) /* GTPro */ +#define DAC_REGS IOPortTag(0x17u, 0x30u) /* 4 separate bytes */ +# define M64_DAC_WRITE (DAC_REGS + 0) +# define M64_DAC_DATA (DAC_REGS + 1) +# define M64_DAC_MASK (DAC_REGS + 2) +# define M64_DAC_READ (DAC_REGS + 3) +#define DAC_CNTL IOPortTag(0x18u, 0x31u) +# define DAC_EXT_SEL 0x00000003ul +# define DAC_EXT_SEL_RS2 0x00000001ul +# define DAC_EXT_SEL_RS3 0x00000002ul +# define DAC_RANGE_CTL 0x00000003ul /* VTB/GTB/LT */ +# define DAC_BLANKING 0x00000004ul /* 264xT */ +# define DAC_CMP_DIS 0x00000008ul /* 264xT */ +# define DAC1_CLK_SEL 0x00000010ul /* LTPro */ +# define DAC_PALETTE_ACCESS_CNTL 0x00000020ul /* LTPro */ +# define DAC_PALETTE2_SNOOP_EN 0x00000040ul /* LTPro */ +# define DAC_CMP_OUTPUT 0x00000080ul /* 264xT */ +# define DAC_8BIT_EN 0x00000100ul +# define DAC_PIX_DLY 0x00000600ul +# define DAC_DIRECT 0x00000400ul /* VTB/GTB/LT */ +# define DAC_BLANK_ADJ 0x00001800ul +# define DAC_PAL_CLK_SEL 0x00000800ul /* VTB/GTB/LT */ +# define DAC_CRT_SENSE 0x00000800ul /* XC/XL */ +# define DAC_CRT_DETECTION_ON 0x00001000ul /* XC/XL */ +# define DAC_VGA_ADR_EN 0x00002000ul +# define DAC_FEA_CON_EN 0x00004000ul /* 264xT */ +# define DAC_PDMN 0x00008000ul /* 264xT */ +# define DAC_TYPE 0x00070000ul +/* ? 0x00f80000ul */ +# define DAC_MON_ID_STATE0 0x01000000ul /* GX-E+/CX */ +# define DAC_GIO_STATE_1 0x01000000ul /* 264xT */ +# define DAC_MON_ID_STATE1 0x02000000ul /* GX-E+/CX */ +# define DAC_GIO_STATE_0 0x02000000ul /* 264xT */ +# define DAC_MON_ID_STATE2 0x04000000ul /* GX-E+/CX */ +# define DAC_GIO_STATE_4 0x04000000ul /* 264xT */ +# define DAC_MON_ID_DIR0 0x08000000ul /* GX-E+/CX */ +# define DAC_GIO_DIR_1 0x08000000ul /* 264xT */ +# define DAC_MON_ID_DIR1 0x10000000ul /* GX-E+/CX */ +# define DAC_GIO_DIR_0 0x10000000ul /* 264xT */ +# define DAC_MON_ID_DIR2 0x20000000ul /* GX-E+/CX */ +# define DAC_GIO_DIR_4 0x20000000ul /* 264xT */ +# define DAC_MAN_CMP_STATE 0x40000000ul /* GX-E+ */ +# define DAC_RW_WS 0x80000000ul /* VT/GT */ +#define HORZ_STRETCHING BlockIOTag(0x32u) /* LT */ +# define HORZ_STRETCH_BLEND 0x00000ffful +# define HORZ_STRETCH_RATIO 0x0000fffful +# define HORZ_STRETCH_LOOP 0x00070000ul +# define HORZ_STRETCH_LOOP09 0x00000000ul +# define HORZ_STRETCH_LOOP11 0x00010000ul +# define HORZ_STRETCH_LOOP12 0x00020000ul +# define HORZ_STRETCH_LOOP14 0x00030000ul +# define HORZ_STRETCH_LOOP15 0x00040000ul +/* ? 0x00050000ul */ +/* ? 0x00060000ul */ +/* ? 0x00070000ul */ +/* ? 0x00080000ul */ +# define HORZ_PANEL_SIZE 0x0ff00000ul /* XC/XL */ +/* ? 0x10000000ul */ +# define AUTO_HORZ_RATIO 0x20000000ul /* XC/XL */ +# define HORZ_STRETCH_MODE 0x40000000ul +# define HORZ_STRETCH_EN 0x80000000ul +#define EXT_DAC_REGS BlockIOTag(0x32u) /* GTPro */ +#define VERT_STRETCHING BlockIOTag(0x33u) /* LT */ +# define VERT_STRETCH_RATIO0 0x000003fful +# define VERT_STRETCH_RATIO1 0x000ffc00ul +# define VERT_STRETCH_RATIO2 0x3ff00000ul +# define VERT_STRETCH_USE0 0x40000000ul +# define VERT_STRETCH_EN 0x80000000ul +#define GEN_TEST_CNTL IOPortTag(0x19u, 0x34u) +# define GEN_EE_DATA_OUT 0x00000001ul /* GX/CX */ +# define GEN_GIO2_DATA_OUT 0x00000001ul /* 264xT */ +# define GEN_EE_CLOCK 0x00000002ul /* GX/CX */ +/* ? 0x00000002ul */ /* 264xT */ +# define GEN_EE_CHIP_SEL 0x00000004ul /* GX/CX */ +# define GEN_GIO3_DATA_OUT 0x00000004ul /* 264xT */ +# define GEN_EE_DATA_IN 0x00000008ul /* GX/CX */ +# define GEN_GIO2_DATA_IN 0x00000008ul /* 264xT */ +# define GEN_EE_EN 0x00000010ul /* GX/CX */ +# define GEN_GIO2_ENABLE 0x00000010ul /* 264xT */ +# define GEN_ICON2_ENABLE 0x00000010ul /* XC/XL */ +# define GEN_OVR_OUTPUT_EN 0x00000020ul /* GX/CX */ +# define GEN_GIO2_WRITE 0x00000020ul /* 264xT */ +# define GEN_CUR2_ENABLE 0x00000020ul /* XC/XL */ +# define GEN_OVR_POLARITY 0x00000040ul /* GX/CX */ +# define GEN_ICON_ENABLE 0x00000040ul /* XC/XL */ +# define GEN_CUR_EN 0x00000080ul +# define GEN_GUI_EN 0x00000100ul /* GX/CX */ +# define GEN_GUI_RESETB 0x00000100ul /* 264xT */ +# define GEN_BLOCK_WR_EN 0x00000200ul /* GX */ +/* ? 0x00000200ul */ /* CX/264xT */ +# define GEN_SOFT_RESET 0x00000200ul /* VTB/GTB/LT */ +# define GEN_MEM_TRISTATE 0x00000400ul /* GTPro */ +/* ? 0x00000800ul */ +# define GEN_TEST_VECT_MODE 0x00003000ul /* VT/GT */ +/* ? 0x0000c000ul */ +# define GEN_TEST_FIFO_EN 0x00010000ul /* GX/CX */ +# define GEN_TEST_GUI_REGS_EN 0x00020000ul /* GX/CX */ +# define GEN_TEST_VECT_EN 0x00040000ul /* GX/CX */ +# define GEN_TEST_CRC_STR 0x00080000ul /* GX-C/-D */ +/* ? 0x00080000ul */ /* GX-E+/CX */ +# define GEN_TEST_MODE_T 0x000f0000ul /* 264xT */ +# define GEN_TEST_MODE 0x00700000ul /* GX/CX */ +# define GEN_TEST_CNT_EN 0x00100000ul /* 264xT */ +# define GEN_TEST_CRC_EN 0x00200000ul /* 264xT */ +/* ? 0x00400000ul */ /* 264xT */ +/* ? 0x00800000ul */ +# define GEN_TEST_MEM_WR 0x01000000ul /* GX-C/-D */ +# define GEN_TEST_MEM_STROBE 0x02000000ul /* GX-C/-D */ +# define GEN_TEST_DST_SS_EN 0x04000000ul /* GX/CX */ +# define GEN_TEST_DST_SS_STROBE 0x08000000ul /* GX/CX */ +# define GEN_TEST_SRC_SS_EN 0x10000000ul /* GX/CX */ +# define GEN_TEST_SRC_SS_STROBE 0x20000000ul /* GX/CX */ +# define GEN_TEST_CNT_VALUE 0x3f000000ul /* 264xT */ +# define GEN_TEST_CC_EN 0x40000000ul /* GX/CX */ +# define GEN_TEST_CC_STROBE 0x80000000ul /* GX/CX */ +/* ? 0xc0000000ul */ /* 264xT */ +# define GEN_DEBUG_MODE 0xff000000ul /* VTB/GTB/LT */ +# define GEN_DEBUG_MC_PARSER 0x2A000000ul /* Mobility pro */ +# define GEN_DEBUG_IDCT_PARSER 0x2B000000ul /* Mobility pro */ +# define GEN_DEBUG_MC_BUFFER 0x2C000000ul /* Mobility pro */ +# define GEN_DEBUG_IDCT_BUFFER 0x2E000000ul /* Mobility pro */ +# define GEN_DEBUG_IDCT1 0x90000000ul /* Mobility pro */ +# define GEN_DEBUG_IDCT2 0x91000000ul /* Mobility pro */ +# define GEN_DEBUG_IDCT3 0x92000000ul /* Mobility pro */ +#define LCD_GEN_CTRL BlockIOTag(0x35u) /* LT */ +# define CRT_ON 0x00000001ul +# define LCD_ON 0x00000002ul +# define HORZ_DIVBY2_EN 0x00000004ul +# define DONT_DS_ICON 0x00000008ul +# define LOCK_8DOT 0x00000010ul +# define ICON_ENABLE 0x00000020ul +# define DONT_SHADOW_VPAR 0x00000040ul +# define V2CLK_PM_EN 0x00000080ul +# define RST_FM 0x00000100ul +# define DISABLE_PCLK_RESET 0x00000200ul /* XC/XL */ +# define DIS_HOR_CRT_DIVBY2 0x00000400ul +# define SCLK_SEL 0x00000800ul +# define SCLK_DELAY 0x0000f000ul +# define TVCLK_PM_EN 0x00010000ul +# define VCLK_DAC_PM_EN 0x00020000ul +# define VCLK_LCD_OFF 0x00040000ul +# define SELECT_WAIT_4MS 0x00080000ul +# define XTALIN_PM_EN 0x00080000ul /* XC/XL */ +# define V2CLK_DAC_PM_EN 0x00100000ul +# define LVDS_EN 0x00200000ul +# define LVDS_PLL_EN 0x00400000ul +# define LVDS_PLL_RESET 0x00800000ul +# define LVDS_RESERVED_BITS 0x07000000ul +# define CRTC_RW_SELECT 0x08000000ul /* LTPro */ +# define USE_SHADOWED_VEND 0x10000000ul +# define USE_SHADOWED_ROWCUR 0x20000000ul +# define SHADOW_EN 0x40000000ul +# define SHADOW_RW_EN 0x80000000ul +#define CUSTOM_MACRO_CNTL BlockIOTag(0x35u) /* GTPro */ +# define IDCT_FIFO_EXTENSE 0x00000001ul +#define POWER_MANAGEMENT BlockIOTag(0x36u) /* LT */ +# define PWR_MGT_ON 0x00000001ul +# define PWR_MGT_MODE 0x00000006ul +# define AUTO_PWRUP_EN 0x00000008ul +# define ACTIVITY_PIN_ON 0x00000010ul +# define STANDBY_POL 0x00000020ul +# define SUSPEND_POL 0x00000040ul +# define SELF_REFRESH 0x00000080ul +# define ACTIVITY_PIN_EN 0x00000100ul +# define KEYBD_SNOOP 0x00000200ul +# define USE_F32KHZ 0x00000400ul /* LTPro */ +# define DONT_USE_XTALIN 0x00000400ul /* XC/XL */ +# define TRISTATE_MEM_EN 0x00000800ul /* LTPro */ +# define LCDENG_TEST_MODE 0x0000f000ul +# define STANDBY_COUNT 0x000f0000ul +# define SUSPEND_COUNT 0x00f00000ul +# define BAISON 0x01000000ul +# define BLON 0x02000000ul +# define DIGON 0x04000000ul +# define PM_D3_SUPPORT_ENABLE 0x08000000ul /* XC/XL */ +# define STANDBY_NOW 0x10000000ul +# define SUSPEND_NOW 0x20000000ul +# define PWR_MGT_STATUS 0xc0000000ul +#define CONFIG_CNTL IOPortTag(0x1au, 0x37u) +# define CFG_MEM_AP_SIZE 0x00000003ul +# define CFG_MEM_VGA_AP_EN 0x00000004ul +/* ? 0x00000008ul */ +# define CFG_MEM_AP_LOC 0x00003ff0ul +/* ? 0x0000c000ul */ +# define CFG_CARD_ID 0x00070000ul +# define CFG_VGA_DIS 0x00080000ul +/* ? 0x00f00000ul */ +# define CFG_CDE_WINDOW 0x3f000000ul /* VT/GT */ +/* ? 0xc0000000ul */ +#define CONFIG_CHIP_ID IOPortTag(0x1bu, 0x38u) /* Read */ +# define CFG_CHIP_TYPE0 0x000000fful +# define CFG_CHIP_TYPE1 0x0000ff00ul +# define CFG_CHIP_TYPE 0x0000fffful +# define CFG_CHIP_CLASS 0x00ff0000ul +# define CFG_CHIP_REV 0xff000000ul +# define CFG_CHIP_VERSION 0x07000000ul /* 264xT */ +# define CFG_CHIP_FOUNDRY 0x38000000ul /* 264xT */ +# define CFG_CHIP_REVISION 0xc0000000ul /* 264xT */ +#define CONFIG_STATUS64_0 IOPortTag(0x1cu, 0x39u) /* Read (R/W (264xT)) */ +# define CFG_BUS_TYPE 0x00000007ul /* GX/CX */ +# define CFG_MEM_TYPE_T 0x00000007ul /* 264xT */ +# define CFG_MEM_TYPE 0x00000038ul /* GX/CX */ +# define CFG_DUAL_CAS_EN_T 0x00000008ul /* 264xT */ +# define CFG_ROM_128K_EN 0x00000008ul /* VTB/GTB/LT */ +# define CFG_ROM_REMAP 0x00000008ul /* GTPro */ +# define CFG_VGA_EN_T 0x00000010ul /* VT/GT */ +# define CFG_CLOCK_EN 0x00000020ul /* 264xT */ +# define CFG_DUAL_CAS_EN 0x00000040ul /* GX/CX */ +# define CFG_VMC_SENSE 0x00000040ul /* VT/GT */ +# define CFG_SHARED_MEM_EN 0x00000040ul /* VTB/GTB/LT */ +# define CFG_LOCAL_BUS_OPTION 0x00000180ul /* GX/CX */ +# define CFG_VFC_SENSE 0x00000080ul /* VT/GT */ +# define CFG_INIT_DAC_TYPE 0x00000e00ul /* GX/CX */ +# define CFG_INIT_CARD_ID 0x00007000ul /* GX-C/-D */ +# define CFG_BLK_WR_SIZE 0x00001000ul /* GX-E+ */ +# define CFG_INT_QSF_EN 0x00002000ul /* GX-E+ */ +/* ? 0x00004000ul */ /* GX-E+ */ +/* ? 0x00007000ul */ /* CX */ +# define CFG_TRI_BUF_DIS 0x00008000ul /* GX/CX */ +# define CFG_BOARD_ID 0x0000ff00ul /* VT/GT */ +# define CFG_EXT_RAM_ADDR 0x003f0000ul /* GX/CX */ +# define CFG_PANEL_ID 0x001f0000ul /* LT */ +# define CFG_MACROVISION_EN 0x00200000ul /* GTPro */ +# define CFG_ROM_DIS 0x00400000ul /* GX/CX */ +# define CFG_PCI33EN 0x00400000ul /* GTPro */ +# define CFG_VGA_EN 0x00800000ul /* GX/CX */ +# define CFG_FULLAGP 0x00800000ul /* GTPro */ +# define CFG_ARITHMOS_ENABLE 0x00800000ul /* XC/XL */ +# define CFG_LOCAL_BUS_CFG 0x01000000ul /* GX/CX */ +# define CFG_CHIP_EN 0x02000000ul /* GX/CX */ +# define CFG_LOCAL_READ_DLY_DIS 0x04000000ul /* GX/CX */ +# define CFG_ROM_OPTION 0x08000000ul /* GX/CX */ +# define CFG_BUS_OPTION 0x10000000ul /* GX/CX */ +# define CFG_LOCAL_DAC_WR_EN 0x20000000ul /* GX/CX */ +# define CFG_VLB_RDY_DIS 0x40000000ul /* GX/CX */ +# define CFG_AP_4GBYTE_DIS 0x80000000ul /* GX/CX */ +#define CONFIG_STATUS64_1 IOPortTag(0x1du, 0x3au) /* Read */ +# define CFG_PCI_DAC_CFG 0x00000001ul /* GX/CX */ +/* ? 0x0000001eul */ /* GX/CX */ +# define CFG_1C8_IO_SEL 0x00000020ul /* GX/CX */ +/* ? 0xffffffc0ul */ /* GX/CX */ +# define CRC_SIG 0xfffffffful /* 264xT */ +#define MPP_CONFIG BlockIOTag(0x3bu) /* VTB/GTB/LT */ +#define MPP_STROBE_CONFIG BlockIOTag(0x3cu) /* VTB/GTB/LT */ +#define MPP_ADDR BlockIOTag(0x3du) /* VTB/GTB/LT */ +#define MPP_DATA BlockIOTag(0x3eu) /* VTB/GTB/LT */ +#define TVO_CNTL BlockIOTag(0x3fu) /* VTB/GTB/LT */ +/* GP_IO IOPortTag(0x1eu, 0x1eu) */ /* See above */ +/* CRTC_H_TOTAL_DISP IOPortTag(0x1fu, 0x00u) */ /* Duplicate */ +#define DST_OFF_PITCH BlockIOTag(0x40u) +# define DST_OFFSET 0x000ffffful +/* ? 0x00300000ul */ +# define DST_PITCH 0xffc00000ul +#define DST_X BlockIOTag(0x41u) +#define DST_Y BlockIOTag(0x42u) +#define DST_Y_X BlockIOTag(0x43u) +#define DST_WIDTH BlockIOTag(0x44u) +#define DST_HEIGHT BlockIOTag(0x45u) +#define DST_HEIGHT_WIDTH BlockIOTag(0x46u) +#define DST_X_WIDTH BlockIOTag(0x47u) +#define DST_BRES_LNTH BlockIOTag(0x48u) +#define DST_BRES_ERR BlockIOTag(0x49u) +#define DST_BRES_INC BlockIOTag(0x4au) +#define DST_BRES_DEC BlockIOTag(0x4bu) +#define DST_CNTL BlockIOTag(0x4cu) +# define DST_X_DIR 0x00000001ul +# define DST_Y_DIR 0x00000002ul +# define DST_Y_MAJOR 0x00000004ul +# define DST_X_TILE 0x00000008ul +# define DST_Y_TILE 0x00000010ul +# define DST_LAST_PEL 0x00000020ul +# define DST_POLYGON_EN 0x00000040ul +# define DST_24_ROT_EN 0x00000080ul +# define DST_24_ROT 0x00000700ul +# define DST_BRES_SIGN 0x00000800ul /* GX/CX */ +# define DST_BRES_ZERO 0x00000800ul /* CT */ +# define DST_POLYGON_RTEDGE_DIS 0x00001000ul /* CT */ +# define TRAIL_X_DIR 0x00002000ul /* GT */ +# define TRAP_FILL_DIR 0x00004000ul /* GT */ +# define TRAIL_BRES_SIGN 0x00008000ul /* GT */ +/* ? 0x00010000ul */ +# define BRES_SIGN_AUTO 0x00020000ul /* GT */ +/* ? 0x00040000ul */ +# define ALPHA_OVERLAP_ENB 0x00080000ul /* GTPro */ +# define SUB_PIX_ON 0x00100000ul /* GTPro */ +/* ? 0xffe00000ul */ +/* DST_Y_X BlockIOTag(0x4du) */ /* Duplicate */ +#define TRAIL_BRES_ERR BlockIOTag(0x4eu) /* GT */ +#define TRAIL_BRES_INC BlockIOTag(0x4fu) /* GT */ +#define TRAIL_BRES_DEC BlockIOTag(0x50u) /* GT */ +#define LEAD_BRES_LNTH BlockIOTag(0x51u) /* GT */ +#define Z_OFF_PITCH BlockIOTag(0x52u) /* GT */ +#define Z_CNTL BlockIOTag(0x53u) /* GT */ +#define ALPHA_TST_CNTL BlockIOTag(0x54u) /* GTPro */ +# define IDCT_EN 0x00008000UL +/* ? BlockIOTag(0x55u) */ +#define SECONDARY_STW_EXP BlockIOTag(0x56u) /* GTPro */ +#define SECONDARY_S_X_INC BlockIOTag(0x57u) /* GTPro */ +#define SECONDARY_S_Y_INC BlockIOTag(0x58u) /* GTPro */ +#define SECONDARY_S_START BlockIOTag(0x59u) /* GTPro */ +#define SECONDARY_W_X_INC BlockIOTag(0x5au) /* GTPro */ +#define SECONDARY_W_Y_INC BlockIOTag(0x5bu) /* GTPro */ +#define SECONDARY_W_START BlockIOTag(0x5cu) /* GTPro */ +#define SECONDARY_T_X_INC BlockIOTag(0x5du) /* GTPro */ +#define SECONDARY_T_Y_INC BlockIOTag(0x5eu) /* GTPro */ +#define SECONDARY_T_START BlockIOTag(0x5fu) /* GTPro */ +#define SRC_OFF_PITCH BlockIOTag(0x60u) +# define SRC_OFFSET 0x000ffffful +/* ? 0x00300000ul */ +# define SRC_PITCH 0xffc00000ul +#define SRC_X BlockIOTag(0x61u) +#define SRC_Y BlockIOTag(0x62u) +#define SRC_Y_X BlockIOTag(0x63u) +#define SRC_WIDTH1 BlockIOTag(0x64u) +#define SRC_HEIGHT1 BlockIOTag(0x65u) +#define SRC_HEIGHT1_WIDTH1 BlockIOTag(0x66u) +#define SRC_X_START BlockIOTag(0x67u) +#define SRC_Y_START BlockIOTag(0x68u) +#define SRC_Y_X_START BlockIOTag(0x69u) +#define SRC_WIDTH2 BlockIOTag(0x6au) +#define SRC_HEIGHT2 BlockIOTag(0x6bu) +#define SRC_HEIGHT2_WIDTH2 BlockIOTag(0x6cu) +#define SRC_CNTL BlockIOTag(0x6du) +# define SRC_PATT_EN 0x00000001ul +# define SRC_PATT_ROT_EN 0x00000002ul +# define SRC_LINEAR_EN 0x00000004ul +# define SRC_BYTE_ALIGN 0x00000008ul +# define SRC_LINE_X_DIR 0x00000010ul +# define SRC_8X8X8_BRUSH 0x00000020ul /* VTB/GTB */ +# define FAST_FILL_EN 0x00000040ul /* VTB/GTB */ +# define SRC_TRACK_DST 0x00000080ul /* VTB/GTB */ +# define BUS_MASTER_EN 0x00000100ul /* VTB/GTB */ +# define BUS_MASTER_SYNC 0x00000200ul /* VTB/GTB */ +# define BUS_MASTER_OP 0x00000c00ul /* VTB/GTB */ +# define BM_OP_FRAME_TO_SYSTEM (0 << 10) +# define BM_OP_SYSTEM_TO_FRAME (1 << 10) +# define BM_OP_REG_TO_SYSTEM (2 << 10) +# define BM_OP_SYSTEM_TO_REG (3 << 10) +# define SRC_8X8X8_BRUSH_LOADED 0x00001000ul /* VTB/GTB */ +# define COLOR_REG_WRITE_EN 0x00002000ul /* VTB/GTB */ +# define BLOCK_WRITE_EN 0x00004000ul /* VTB/GTB */ +/* ? 0xffff8000ul */ +/* ? BlockIOTag(0x6eu) */ +/* ? BlockIOTag(0x6fu) */ +#define SCALE_Y_OFF BlockIOTag(0x70u) /* GT */ +#define SCALE_OFF BlockIOTag(0x70u) /* GTPro */ +#define SECONDARY_SCALE_OFF BlockIOTag(0x70u) /* GTPro */ +#define TEX_0_OFF BlockIOTag(0x70u) /* GT */ +#define TEX_1_OFF BlockIOTag(0x71u) /* GT */ +#define TEX_2_OFF BlockIOTag(0x72u) /* GT */ +#define TEX_3_OFF BlockIOTag(0x73u) /* GT */ +#define TEX_4_OFF BlockIOTag(0x74u) /* GT */ +#define TEX_5_OFF BlockIOTag(0x75u) /* GT */ +#define TEX_6_OFF BlockIOTag(0x76u) /* GT */ +#define SCALE_WIDTH BlockIOTag(0x77u) /* GT */ +#define TEX_7_OFF BlockIOTag(0x77u) /* GT */ +#define SCALE_HEIGHT BlockIOTag(0x78u) /* GT */ +#define TEX_8_OFF BlockIOTag(0x78u) /* GT */ +#define TEX_9_OFF BlockIOTag(0x79u) /* GT */ +#define TEX_10_OFF BlockIOTag(0x7au) /* GT */ +#define S_Y_INC BlockIOTag(0x7bu) /* GT */ +#define SCALE_Y_PITCH BlockIOTag(0x7bu) /* GT */ +#define SCALE_X_INC BlockIOTag(0x7cu) /* GT */ +#define RED_X_INC BlockIOTag(0x7cu) /* GT */ +#define GREEN_X_INC BlockIOTag(0x7du) /* GT */ +#define SCALE_Y_INC BlockIOTag(0x7du) /* GT */ +#define SCALE_VACC BlockIOTag(0x7eu) /* GT */ +#define SCALE_3D_CNTL BlockIOTag(0x7fu) /* GT */ +# define SIGNED_DST_CLAMP 0x00008000UL /* MPEG's MC */ +#define HOST_DATA_0 BlockIOTag(0x80u) +#define HOST_DATA_1 BlockIOTag(0x81u) +#define HOST_DATA_2 BlockIOTag(0x82u) +#define HOST_DATA_3 BlockIOTag(0x83u) +#define HOST_DATA_4 BlockIOTag(0x84u) +#define HOST_DATA_5 BlockIOTag(0x85u) +#define HOST_DATA_6 BlockIOTag(0x86u) +#define HOST_DATA_7 BlockIOTag(0x87u) +#define HOST_DATA_8 BlockIOTag(0x88u) +#define HOST_DATA_9 BlockIOTag(0x89u) +#define HOST_DATA_A BlockIOTag(0x8au) +#define HOST_DATA_B BlockIOTag(0x8bu) +#define HOST_DATA_C BlockIOTag(0x8cu) +#define HOST_DATA_D BlockIOTag(0x8du) +#define HOST_DATA_E BlockIOTag(0x8eu) +#define HOST_DATA_F BlockIOTag(0x8fu) +#define HOST_CNTL BlockIOTag(0x90u) +#define HOST_BYTE_ALIGN 0x00000001ul +#define HOST_BIG_ENDIAN_EN 0x00000002ul /* GX-E/CT */ +/* ? 0xfffffffcul */ +#define BM_HOSTDATA BlockIOTag(0x91u) /* VTB/GTB write-only */ +#define BM_ADDR BlockIOTag(0x92u) /* VTB/GTB */ +# define GUIREG_ADDR 0x000000FFUL +# define GUIREG_COUNTER 0x003F0000UL +# define IDCT_FLAGS 0x60000000UL +# define IDCT_EOB 0x00000000UL +# define IDCT_TRIPLETS 0x20000000UL /* run, level, level */ +# define IDCT_AUTOINC 0x40000000UL +# define IDCT_STREAM 0x80000000UL +#define BM_DATA BlockIOTag(0x92u) /* VTB/GTB write-only */ +#define BM_GUI_TABLE_CMD BlockIOTag(0x93u) /* GTPro */ +# define CIRCULAR_BUF_SIZE_16KB (0 << 0) +# define CIRCULAR_BUF_SIZE_32KB (1 << 0) +# define CIRCULAR_BUF_SIZE_64KB (2 << 0) +# define CIRCULAR_BUF_SIZE_128KB (3 << 0) +# define LAST_DESCRIPTOR (1 << 31) +/* ? BlockIOTag(0x94u) */ +/* ? BlockIOTag(0x95u) */ +/* ? BlockIOTag(0x96u) */ +/* ? BlockIOTag(0x97u) */ +/* ? BlockIOTag(0x98u) */ +/* ? BlockIOTag(0x99u) */ +/* ? BlockIOTag(0x9au) */ +/* ? BlockIOTag(0x9bu) */ +/* ? BlockIOTag(0x9cu) */ +/* ? BlockIOTag(0x9du) */ +/* ? BlockIOTag(0x9eu) */ +/* ? BlockIOTag(0x9fu) */ +#define PAT_REG0 BlockIOTag(0xa0u) +#define PAT_REG1 BlockIOTag(0xa1u) +#define PAT_CNTL BlockIOTag(0xa2u) +# define PAT_MONO_EN 0x00000001ul +# define PAT_CLR_4x2_EN 0x00000002ul +# define PAT_CLR_8x1_EN 0x00000004ul +/* ? 0xfffffff8ul */ +/* ? BlockIOTag(0xa3u) */ +/* ? BlockIOTag(0xa4u) */ +/* ? BlockIOTag(0xa5u) */ +/* ? BlockIOTag(0xa6u) */ +/* ? BlockIOTag(0xa7u) */ +#define SC_LEFT BlockIOTag(0xa8u) +#define SC_RIGHT BlockIOTag(0xa9u) +#define SC_LEFT_RIGHT BlockIOTag(0xaau) +#define SC_TOP BlockIOTag(0xabu) +#define SC_BOTTOM BlockIOTag(0xacu) +#define SC_TOP_BOTTOM BlockIOTag(0xadu) +#define USR1_DST_OFF_PITCH BlockIOTag(0xaeu) /* LTPro */ +#define USR2_DST_OFF_PITCH BlockIOTag(0xafu) /* LTPro */ +#define DP_BKGD_CLR BlockIOTag(0xb0u) +#define DP_FRGD_CLR BlockIOTag(0xb1u) +#define DP_WRITE_MASK BlockIOTag(0xb2u) +#define DP_CHAIN_MASK BlockIOTag(0xb3u) +# define DP_CHAIN_1BPP 0x00000000ul /* Irrelevant */ +# define DP_CHAIN_4BPP 0x00008888ul +# define DP_CHAIN_8BPP 0x00008080ul +# define DP_CHAIN_8BPP_332 0x00009292ul +# define DP_CHAIN_15BPP_1555 0x00004210ul +# define DP_CHAIN_16BPP_565 0x00008410ul +# define DP_CHAIN_24BPP_888 0x00008080ul +# define DP_CHAIN_32BPP_8888 0x00008080ul +/* ? 0xffff0000ul */ +#define DP_PIX_WIDTH BlockIOTag(0xb4u) +# define DP_DST_PIX_WIDTH 0x0000000ful +# define COMPOSITE_PIX_WIDTH 0x000000f0ul /* GTPro */ +# define DP_SRC_PIX_WIDTH 0x00000f00ul +/* ? 0x00001000ul */ +# define DP_HOST_TRIPLE_EN 0x00002000ul /* GT2c/VT4 */ +# define DP_SRC_AUTONA_FIX_DIS 0x00004000ul /* GTB */ +# define DP_FAST_SRCCOPY_DIS 0x00008000ul /* GTB */ +# define DP_HOST_PIX_WIDTH 0x000f0000ul +# define DP_CI4_RGB_INDEX 0x00f00000ul /* GTB */ +# define DP_BYTE_PIX_ORDER 0x01000000ul +# define DP_CONVERSION_TEMP 0x02000000ul /* GTB */ +# define DP_CI4_RGB_LOW_NIBBLE 0x04000000ul /* GTB */ +# define DP_C14_RGB_HIGH_NIBBLE 0x08000000ul /* GTB */ +# define DP_SCALE_PIX_WIDTH 0xf0000000ul /* GTB */ +#define DP_MIX BlockIOTag(0xb5u) +# define BKGD_MIX_NOT_D (0 << 0) +# define BKGD_MIX_ZERO (1 << 0) +# define BKGD_MIX_ONE (2 << 0) +# define BKGD_MIX_D (3 << 0) +# define BKGD_MIX_NOT_S (4 << 0) +# define BKGD_MIX_D_XOR_S (5 << 0) +# define BKGD_MIX_NOT_D_XOR_S (6 << 0) +# define BKGD_MIX_S (7 << 0) +# define BKGD_MIX_NOT_D_OR_NOT_S (8 << 0) +# define BKGD_MIX_D_OR_NOT_S (9 << 0) +# define BKGD_MIX_NOT_D_OR_S (10 << 0) +# define BKGD_MIX_D_OR_S (11 << 0) +# define BKGD_MIX_D_AND_S (12 << 0) +# define BKGD_MIX_NOT_D_AND_S (13 << 0) +# define BKGD_MIX_D_AND_NOT_S (14 << 0) +# define BKGD_MIX_NOT_D_AND_NOT_S (15 << 0) +# define BKGD_MIX_D_PLUS_S_DIV2 (23 << 0) +# define FRGD_MIX_NOT_D (0 << 16) +# define FRGD_MIX_ZERO (1 << 16) +# define FRGD_MIX_ONE (2 << 16) +# define FRGD_MIX_D (3 << 16) +# define FRGD_MIX_NOT_S (4 << 16) +# define FRGD_MIX_D_XOR_S (5 << 16) +# define FRGD_MIX_NOT_D_XOR_S (6 << 16) +# define FRGD_MIX_S (7 << 16) +# define FRGD_MIX_NOT_D_OR_NOT_S (8 << 16) +# define FRGD_MIX_D_OR_NOT_S (9 << 16) +# define FRGD_MIX_NOT_D_OR_S (10 << 16) +# define FRGD_MIX_D_OR_S (11 << 16) +# define FRGD_MIX_D_AND_S (12 << 16) +# define FRGD_MIX_NOT_D_AND_S (13 << 16) +# define FRGD_MIX_D_AND_NOT_S (14 << 16) +# define FRGD_MIX_NOT_D_AND_NOT_S (15 << 16) +# define FRGD_MIX_D_PLUS_S_DIV2 (23 << 16) +#define DP_SRC BlockIOTag(0xb6u) +# define BKGD_SRC_BKGD_CLR (0 << 0) +# define BKGD_SRC_FRGD_CLR (1 << 0) +# define BKGD_SRC_HOST (2 << 0) +# define BKGD_SRC_BLIT (3 << 0) +# define BKGD_SRC_PATTERN (4 << 0) +# define BKGD_SRC_3D (5 << 0) +# define FRGD_SRC_BKGD_CLR (0 << 8) +# define FRGD_SRC_FRGD_CLR (1 << 8) +# define FRGD_SRC_HOST (2 << 8) +# define FRGD_SRC_BLIT (3 << 8) +# define FRGD_SRC_PATTERN (4 << 8) +# define FRGD_SRC_3D (5 << 8) +# define MONO_SRC_ONE (0 << 16) +# define MONO_SRC_PATTERN (1 << 16) +# define MONO_SRC_HOST (2 << 16) +# define MONO_SRC_BLIT (3 << 16) +#define DP_FRGD_CLR_MIX BlockIOTag(0xb7u) /* VTB/GTB */ +#define DP_FRGD_BKGD_CLR BlockIOTag(0xb8u) /* VTB/GTB */ +/* ? BlockIOTag(0xb9u) */ +#define DST_X_Y BlockIOTag(0xbau) /* VTB/GTB */ +#define DST_WIDTH_HEIGHT BlockIOTag(0xbbu) /* VTB/GTB */ +#define USR_DST_PITCH BlockIOTag(0xbcu) /* GTPro */ +/* ? BlockIOTag(0xbdu) */ +#define DP_SET_GUI_ENGINE2 BlockIOTag(0xbeu) /* GTPro */ +#define DP_SET_GUI_ENGINE BlockIOTag(0xbfu) /* VTB/GTB */ +#define CLR_CMP_CLR BlockIOTag(0xc0u) +#define CLR_CMP_MSK BlockIOTag(0xc1u) +#define CLR_CMP_CNTL BlockIOTag(0xc2u) +# define CLR_CMP_FN 0x00000007ul +# define CLR_CMP_FN_FALSE 0x00000000ul +# define CLR_CMP_FN_TRUE 0x00000001ul +/* ? 0x00000002ul */ +/* ? 0x00000003ul */ +# define CLR_CMP_FN_NOT_EQUAL 0x00000004ul +# define CLR_CMP_FN_EQUAL 0x00000005ul +/* ? 0x00000006ul */ +/* ? 0x00000007ul */ +/* ? 0x00fffff8ul */ +# define CLR_CMP_SRC 0x03000000ul +# define CLR_CMP_SRC_DST 0x00000000ul +# define CLR_CMP_SRC_2D 0x01000000ul +# define CLR_CMP_SRC_TEXEL 0x02000000ul +/* ? 0x03000000ul */ +/* ? 0xfc000000ul */ +/* ? BlockIOTag(0xc3u) */ +#define FIFO_STAT BlockIOTag(0xc4u) +# define FIFO_STAT_BITS 0x0000fffful +/* ? 0x7fff0000ul */ +# define FIFO_ERR 0x80000000ul +/* ? BlockIOTag(0xc5u) */ +/* ? BlockIOTag(0xc6u) */ +/* ? BlockIOTag(0xc7u) */ +#define CONTEXT_MASK BlockIOTag(0xc8u) +/* ? BlockIOTag(0xc9u) */ +/* ? BlockIOTag(0xcau) */ +#define CONTEXT_LOAD_CNTL BlockIOTag(0xcbu) +# define CONTEXT_LOAD_PTR 0x00007ffful +/* ? 0x00008000ul */ +# define CONTEXT_LOAD_CMD 0x00030000ul +# define CONTEXT_LOAD_NONE 0x00000000ul +# define CONTEXT_LOAD_ONLY 0x00010000ul +# define CONTEXT_LOAD_FILL 0x00020000ul +# define CONTEXT_LOAD_LINE 0x00030000ul +/* ? 0x7ffc0000ul */ +#define CONTEXT_LOAD_DIS 0x80000000ul +#define GUI_TRAJ_CNTL BlockIOTag(0xccu) +/* ? BlockIOTag(0xcdu) */ +#define GUI_STAT BlockIOTag(0xceu) +#define GUI_ACTIVE 0x00000001ul +/* ? 0x000000feul */ +#define DSTX_LT_SCISSOR_LEFT 0x00000100ul +#define DSTX_GT_SCISSOR_RIGHT 0x00000200ul +#define DSTY_LT_SCISSOR_TOP 0x00000400ul +#define DSTY_GT_SCISSOR_BOTTOM 0x00000800ul +/* ? 0x0000f000ul */ +#define GUI_FIFO 0x03ff0000ul /* VTB/GTB */ +/* ? 0xfc000000ul */ +/* ? BlockIOTag(0xcfu) */ +#define S_X_INC2 BlockIOTag(0xd0u) /* GTB */ +#define TEX_PALETTE_INDEX BlockIOTag(0xd0u) /* GTPro */ +#define S_Y_INC2 BlockIOTag(0xd1u) /* GTB */ +#define STW_EXP BlockIOTag(0xd1u) /* GTPro */ +#define S_XY_INC2 BlockIOTag(0xd2u) /* GTB */ +#define LOG_MAX_INC BlockIOTag(0xd2u) /* GTPro */ +#define S_XINC_START BlockIOTag(0xd3u) /* GTB */ +/* S_Y_INC BlockIOTag(0xd4u) */ /* Duplicate */ +/* SCALE_Y_PITCH BlockIOTag(0xd4u) */ /* Duplicate */ +#define S_START BlockIOTag(0xd5u) /* GTB */ +#define T_X_INC2 BlockIOTag(0xd6u) /* GTB */ +#define W_X_INC BlockIOTag(0xd6u) /* GTPro */ +#define T_Y_INC2 BlockIOTag(0xd7u) /* GTB */ +#define W_Y_INC BlockIOTag(0xd7u) /* GTPro */ +#define T_XY_INC2 BlockIOTag(0xd8u) /* GTB */ +#define W_START BlockIOTag(0xd8u) /* GTPro */ +#define T_XINC_START BlockIOTag(0xd9u) /* GTB */ +#define T_Y_INC BlockIOTag(0xdau) /* GTB */ +#define SECONDARY_SCALE_PITCH BlockIOTag(0xdau) /* GTPro */ +#define T_START BlockIOTag(0xdbu) /* GTB */ +#define TEX_SIZE_PITCH BlockIOTag(0xdcu) /* GTB */ +#define TEX_CNTL BlockIOTag(0xddu) /* GTPro */ +#define SECONDARY_TEX_OFFSET BlockIOTag(0xdeu) /* GTPro */ +#define TEX_PAL_WR BlockIOTag(0xdfu) /* GTB */ +#define TEX_PALETTE BlockIOTag(0xdfu) /* GTPro */ +#define SCALE_PITCH_BOTH BlockIOTag(0xe0u) /* GTPro */ +#define SECONDARY_SCALE_OFF_ACC BlockIOTag(0xe1u) /* GTPro */ +#define SCALE_OFF_ACC BlockIOTag(0xe2u) /* GTPro */ +#define SCALE_DST_Y_X BlockIOTag(0xe3u) /* GTPro */ +/* ? BlockIOTag(0xe4u) */ +/* ? BlockIOTag(0xe5u) */ +#define COMPOSITE_SHADOW_ID BlockIOTag(0xe6u) /* GTPro */ +#define SECONDARY_SCALE_X_INC BlockIOTag(0xe7u) /* GTPro */ +#define SPECULAR_RED_X_INC BlockIOTag(0xe7u) /* GTPro */ +#define SPECULAR_RED_Y_INC BlockIOTag(0xe8u) /* GTPro */ +#define SPECULAR_RED_START BlockIOTag(0xe9u) /* GTPro */ +#define SECONDARY_SCALE_HACC BlockIOTag(0xe9u) /* GTPro */ +#define SPECULAR_GREEN_X_INC BlockIOTag(0xeau) /* GTPro */ +#define SPECULAR_GREEN_Y_INC BlockIOTag(0xebu) /* GTPro */ +#define SPECULAR_GREEN_START BlockIOTag(0xecu) /* GTPro */ +#define SPECULAR_BLUE_X_INC BlockIOTag(0xedu) /* GTPro */ +#define SPECULAR_BLUE_Y_INC BlockIOTag(0xeeu) /* GTPro */ +#define SPECULAR_BLUE_START BlockIOTag(0xefu) /* GTPro */ +/* SCALE_X_INC BlockIOTag(0xf0u) */ /* Duplicate */ +/* RED_X_INC BlockIOTag(0xf0u) */ /* Duplicate */ +#define RED_Y_INC BlockIOTag(0xf1u) /* GTB */ +#define SCALE_HACC BlockIOTag(0xf2u) /* GTB */ +#define RED_START BlockIOTag(0xf2u) /* GTB */ +/* GREEN_X_INC BlockIOTag(0xf3u) */ /* Duplicate */ +/* SCALE_Y_INC BlockIOTag(0xf3u) */ /* Duplicate */ +#define GREEN_Y_INC BlockIOTag(0xf4u) /* GTB */ +#define SECONDARY_SCALE_Y_INC BlockIOTag(0xf4u) /* GTPro */ +#define SECONDARY_SCALE_VACC BlockIOTag(0xf5u) /* GTPro */ +#define GREEN_START BlockIOTag(0xf5u) /* GTB */ +#define BLUE_X_INC BlockIOTag(0xf6u) /* GTB */ +#define SCALE_XUV_INC BlockIOTag(0xf6u) /* GTB */ +#define BLUE_Y_INC BlockIOTag(0xf7u) /* GTB */ +#define BLUE_START BlockIOTag(0xf8u) /* GTB */ +#define SCALE_UV_HACC BlockIOTag(0xf8u) /* GTB */ +#define Z_X_INC BlockIOTag(0xf9u) /* GTB */ +#define Z_Y_INC BlockIOTag(0xfau) /* GTB */ +#define Z_START BlockIOTag(0xfbu) /* GTB */ +#define ALPHA_FOG_X_INC BlockIOTag(0xfcu) /* GTB */ +#define ALPHA_FOG_Y_INC BlockIOTag(0xfdu) /* GTB */ +#define ALPHA_FOG_START BlockIOTag(0xfeu) /* GTB */ +/* ? BlockIOTag(0xffu) */ +#define OVERLAY_Y_X_START BlockIOTag(0x100u) +# define OVERLAY_Y_START 0x000007FFUL +# define OVERLAY_X_START 0x07FF0000UL +# define OVERLAY_LOCK_START 0x80000000UL +#define OVERLAY_Y_X_END BlockIOTag(0x101u) +# define OVERLAY_Y_END 0x000007FFUL +# define OVERLAY_X_END 0x07FF0000UL +# define OVERLAY_LOCK_END 0x80000000UL +#define OVERLAY_VIDEO_KEY_CLR BlockIOTag(0x102u) +#define OVERLAY_VIDEO_KEY_MSK BlockIOTag(0x103u) +#define OVERLAY_GRAPHICS_KEY_CLR BlockIOTag(0x104u) +#define OVERLAY_GRAPHICS_KEY_MSK BlockIOTag(0x105u) +#define OVERLAY_KEY_CNTL BlockIOTag(0x106u) +# define VIDEO_KEY_FN_MASK 0x00000007L +# define VIDEO_KEY_FN_FALSE 0x00000000L +# define VIDEO_KEY_FN_TRUE 0x00000001L +# define VIDEO_KEY_FN_NE 0x00000004L +# define VIDEO_KEY_FN_EQ 0x00000005L // EQ and NE are exchanged relative to radeon +# define GRAPHIC_KEY_FN_MASK 0x00000070L +# define GRAPHIC_KEY_FN_FALSE 0x00000000L +# define GRAPHIC_KEY_FN_TRUE 0x00000010L +# define GRAPHIC_KEY_FN_NE 0x00000040L +# define GRAPHIC_KEY_FN_EQ 0x00000050L // EQ and NE are exchanged relative to radeon +# define CMP_MIX_MASK 0x00000100L +# define CMP_MIX_OR 0x00000000L +# define CMP_MIX_AND 0x00000100L +/* ? BlockIOTag(0x107u) */ +#define OVERLAY_SCALE_INC BlockIOTag(0x108u) +#define OVERLAY_SCALE_CNTL BlockIOTag(0x109u) +# define SCALE_PIX_EXPAND 0x00000001UL +# define SCALE_Y2R_TEMP 0x00000002UL +# define SCALE_HORZ_MODE 0x00000004UL +# define SCALE_VERT_MODE 0x00000008UL +# define SCALE_SIGNED_UV 0x00000010UL +# define SCALE_GAMMA_SEL_MSK 0x00000060UL +# define SCALE_GAMMA_SEL_BRIGHT 0x00000000UL +# define SCALE_GAMMA_SEL_G22 0x00000020UL +# define SCALE_GAMMA_SEL_G18 0x00000040UL +# define SCALE_GAMMA_SEL_G14 0x00000060UL +# define SCALE_SEL_DISP2 0x00000080UL /* pro only */ +# define SCALE_BANDWIDTH 0x04000000UL +# define SCALE_DIS_LIMIT 0x08000000UL +# define SCALE_CLK_FORCE_ON 0x20000000UL +# define OVERLAY_EN 0x40000000UL +# define SCALE_EN 0x80000000UL +#define SCALER_HEIGHT_WIDTH BlockIOTag(0x10au) +#define OVERLAY_TEST BlockIOTag(0x10bu) +# define SCALE_SUBPIC_ONLY 0x00000001UL +# define SCALE_Y2R_DIS 0x00000002UL +#define SCALER_THRESHOLD BlockIOTag(0x10cu) +#define SCALER_BUF0_OFFSET BlockIOTag(0x10du) /* VTB/GTB */ +#define SCALER_BUF1_OFFSET BlockIOTag(0x10eu) /* VTB/GTB */ +#define SCALER_BUF_PITCH BlockIOTag(0x10fu) /* VTB/GTB */ +#define CAPTURE_Y_X BlockIOTag(0x110u) +#define CAPTURE_START_END BlockIOTag(0x110u) /* VTB/GTB */ +#define CAPTURE_HEIGHT_WIDTH BlockIOTag(0x111u) +#define CAPTURE_X_WIDTH BlockIOTag(0x111u) /* VTB/GTB */ +#define VIDEO_FORMAT BlockIOTag(0x112u) +# define VIDEO_IN_MSK 0x0000000FUL +# define VIDEO_IN_VYUY422 0x0000000BUL +# define VIDEO_IN_YVYU422 0x0000000CUL +# define VIDEO_SIGNED_UV 0x00000010UL +# define SCALER_IN_MSK 0x000F0000UL +# define SCALER_IN_RGB15 0x00030000UL +# define SCALER_IN_RGB16 0x00040000UL +# define SCALER_IN_RGB32 0x00060000UL +# define SCALER_IN_YUV9 0x00090000UL +# define SCALER_IN_YUV12 0x000A0000UL +# define SCALER_IN_VYUY422 0x000B0000UL +# define SCALER_IN_YVYU422 0x000C0000UL +# define HOST_BYTE_SHIFT_EN 0x10000000UL +# define HOST_YUV_APER 0x20000000UL +# define HOST_MEM_MODE_MSK 0xC0000000UL +# define HOST_MEM_MODE_NORMAL 0x00000000UL +# define HOST_MEM_MODE_Y 0x40000000UL +# define HOST_MEM_MODE_U 0x80000000UL +# define HOST_MEM_MODE_V 0xC0000000UL +#define VIDEO_CONFIG BlockIOTag(0x113u) +#define VBI_START_END BlockIOTag(0x113u) /* VTB/GTB */ +#define CAPTURE_CONFIG BlockIOTag(0x114u) +#define TRIG_CNTL BlockIOTag(0x115u) +#define VIDEO_SYNC_TEST BlockIOTag(0x116u) +#define OVERLAY_EXCLUSIVE_HORZ BlockIOTag(0x116u) /* VTB/GTB */ +# define EXCLUSIVE_HORZ_START 0x000000FFUL +# define EXCLUSIVE_HORZ_END 0x0000FF00UL +# define EXCLUSIVE_BACK_PORSH 0x00FF0000UL +# define EXCLUSIVE_EN 0x80000000UL +#define EXT_CRTC_GEN_CNTL_R BlockIOTag(0x117u) /* VT-A4 (R) */ +#define OVERLAY_EXCLUSIVE_VERT BlockIOTag(0x117u) /* VTB/GTB */ +# define EXCLUSIVE_VERT_START 0x000007FFUL +# define EXCLUSIVE_VERT_END 0x07FF0000UL +#define VMC_CONFIG BlockIOTag(0x118u) +#define VBI_WIDTH BlockIOTag(0x118u) /* VTB/GTB */ +#define VMC_STATUS BlockIOTag(0x119u) +#define CAPTURE_DEBUG BlockIOTag(0x119u) /* VTB/GTB */ +#define VMC_CMD BlockIOTag(0x11au) +#define VIDEO_SYNC_TEST_B BlockIOTag(0x11au) /* VTB/GTB */ +# define TEST_CRTC_OVLSOF 0x00000001UL +# define TEST_CRTC_VOVLEN 0x00000002UL +# define TEST_VID_SOF 0x00000100UL +# define TEST_VID_EOF 0x00000200UL +# define TEST_VID_EOL 0x00000400UL +# define TEST_VID_FIELD 0x00000800UL +# define TEST_END_OF_VBI 0x00001000UL +# define TEST_BUSMASTER_EOL 0x00002000UL +# define TEST_SYNC_EN 0x80000000UL +#define VMC_ARG0 BlockIOTag(0x11bu) +#define VMC_ARG1 BlockIOTag(0x11cu) +#define SNAPSHOT_VH_COUNTS BlockIOTag(0x11cu) /* GTPro */ +#define VMC_SNOOP_ARG0 BlockIOTag(0x11du) +#define SNAPSHOT_F_COUNT BlockIOTag(0x11du) /* GTPro */ +#define VMC_SNOOP_ARG1 BlockIOTag(0x11eu) +#define N_VIF_COUNT BlockIOTag(0x11eu) /* GTPro */ +#define SNAPSHOT_VIF_COUNT BlockIOTag(0x11fu) /* GTPro */ +#define BUF0_OFFSET BlockIOTag(0x120u) +#define CAPTURE_BUF0_OFFSET BlockIOTag(0x120u) /* VTB/GTB */ +#define CAPTURE_BUF1_OFFSET BlockIOTag(0x121u) /* VTB/GTB */ +#define ONESHOT_BUF_OFFSET BlockIOTag(0x122u) /* VTB/GTB */ +#define BUF0_PITCH BlockIOTag(0x123u) +/* ? BlockIOTag(0x124u) */ +/* ? BlockIOTag(0x125u) */ +#define BUF1_OFFSET BlockIOTag(0x126u) +/* ? BlockIOTag(0x127u) */ +/* ? BlockIOTag(0x128u) */ +#define BUF1_PITCH BlockIOTag(0x129u) +/* ? BlockIOTag(0x12au) */ +#define BUF0_CAP_ODD_OFFSET BlockIOTag(0x12bu) +#define BUF1_CAP_ODD_OFFSET BlockIOTag(0x12cu) +#define SNAPSHOT2_VH_COUNTS BlockIOTag(0x12cu) /* LTPro */ +#define SNAPSHOT2_F_COUNT BlockIOTag(0x12du) /* LTPro */ +#define N_VIF2_COUNT BlockIOTag(0x12eu) /* LTPro */ +#define SNAPSHOT2_VIF_COUNT BlockIOTag(0x12fu) /* LTPro */ +#define VMC_STRM_DATA_0 BlockIOTag(0x130u) +/* MPP_CONFIG BlockIOTag(0x130u) */ /* See 0x3bu */ +#define VMC_STRM_DATA_1 BlockIOTag(0x131u) +/* MPP_STROBE_SEQ BlockIOTag(0x131u) */ /* See 0x3cu */ +#define VMC_STRM_DATA_2 BlockIOTag(0x132u) +/* MPP_ADDR BlockIOTag(0x132u) */ /* See 0x3du */ +#define VMC_STRM_DATA_3 BlockIOTag(0x133u) +/* MPP_DATA BlockIOTag(0x133u) */ /* See 0x3eu */ +#define VMC_STRM_DATA_4 BlockIOTag(0x134u) +#define VMC_STRM_DATA_5 BlockIOTag(0x135u) +#define VMC_STRM_DATA_6 BlockIOTag(0x136u) +#define VMC_STRM_DATA_7 BlockIOTag(0x137u) +#define VMC_STRM_DATA_8 BlockIOTag(0x138u) +#define VMC_STRM_DATA_9 BlockIOTag(0x139u) +#define VMC_STRM_DATA_A BlockIOTag(0x13au) +#define VMC_STRM_DATA_B BlockIOTag(0x13bu) +#define VMC_STRM_DATA_C BlockIOTag(0x13cu) +#define VMC_STRM_DATA_D BlockIOTag(0x13du) +#define VMC_STRM_DATA_E BlockIOTag(0x13eu) +#define VMC_STRM_DATA_F BlockIOTag(0x13fu) +/* TVO_CNTL BlockIOTag(0x140u) */ /* See 0x3fu */ +/* ? BlockIOTag(0x141u) */ +/* ? BlockIOTag(0x142u) */ +/* ? BlockIOTag(0x143u) */ +/* ? BlockIOTag(0x144u) */ +/* ? BlockIOTag(0x145u) */ +/* ? BlockIOTag(0x146u) */ +/* ? BlockIOTag(0x147u) */ +/* ? BlockIOTag(0x148u) */ +/* ? BlockIOTag(0x149u) */ +/* ? BlockIOTag(0x14au) */ +/* ? BlockIOTag(0x14bu) */ +/* ? BlockIOTag(0x14cu) */ +/* ? BlockIOTag(0x14du) */ +/* ? BlockIOTag(0x14eu) */ +/* ? BlockIOTag(0x14fu) */ +/* ? BlockIOTag(0x150u) */ +#define CRT_HORZ_VERT_LOAD BlockIOTag(0x151u) /* VTB/GTB */ +#define AGP_BASE BlockIOTag(0x152u) /* GTPro */ +#define AGP_CNTL BlockIOTag(0x153u) /* GTPro */ +#define SCALER_COLOUR_CNTL BlockIOTag(0x154u) /* GTPro */ +# define COLOUR_BRIGHTNESS 0x0000007FUL +# define COLOUR_SATURATION_U 0x00001F00UL +# define COLOUR_SATURATION_V 0x001F0000UL +# define SCALER_VERT_ADJ_UV 0x0FE00000UL +/*# define SCALER_VERT_ADJ_UV 0x0F000000UL (need testing) */ +# define SCALER_HORZ_ADJ_UV 0xF0000000UL +#define SCALER_H_COEFF0 BlockIOTag(0x155u) /* GTPro */ +#define SCALER_H_COEFF1 BlockIOTag(0x156u) /* GTPro */ +#define SCALER_H_COEFF2 BlockIOTag(0x157u) /* GTPro */ +#define SCALER_H_COEFF3 BlockIOTag(0x158u) /* GTPro */ +#define SCALER_H_COEFF4 BlockIOTag(0x159u) /* GTPro */ +/* ? BlockIOTag(0x15au) */ +/* ? BlockIOTag(0x15bu) */ +#define GUI_CMDFIFO_DEBUG BlockIOTag(0x15cu) /* GT2c/VT4 */ +#define GUI_CMDFIFO_DATA BlockIOTag(0x15du) /* GT2c/VT4 */ +#define GUI_CNTL BlockIOTag(0x15eu) /* GT2c/VT4 */ +# define CMDFIFO_SIZE_MASK 0x00000003ul +# define CMDFIFO_SIZE_192 0x00000000ul +# define CMDFIFO_SIZE_128 0x00000001ul +# define CMDFIFO_SIZE_64 0x00000002ul +/* ? 0x0000fffcul */ +# define IDCT_PRSR_MODE 0x00010000ul /* XL/XC */ +# define IDCT_BLOCK_GUI_INITIATOR 0x00020000ul /* XL/XC */ +/* ? 0xfffc0000ul */ +/* ? BlockIOTag(0x15fu) */ +/* BUS MASTERING */ +#define BM_FRAME_BUF_OFFSET BlockIOTag(0x160u) /* VTB/GTB read-only */ +#define BM_SYSTEM_MEM_ADDR BlockIOTag(0x161u) /* VTB/GTB read-only */ +#define BM_COMMAND BlockIOTag(0x162u) /* VTB/GTB read-only */ +# define BM_CMD_BYTE_COUNT 0x00001FFFUL +# define BM_CMD_HOLD_OFFSET 0x40000000UL +# define BM_CMD_EOL 0x80000000UL +#define BM_STATUS BlockIOTag(0x163u) /* VTB/GTB read-only */ +/* ? BlockIOTag(0x164u) */ +/* ? BlockIOTag(0x165u) */ +/* ? BlockIOTag(0x166u) */ +/* ? BlockIOTag(0x167u) */ +/* ? BlockIOTag(0x168u) */ +/* ? BlockIOTag(0x169u) */ +/* ? BlockIOTag(0x16au) */ +/* ? BlockIOTag(0x16bu) */ +/* ? BlockIOTag(0x16cu) */ +/* ? BlockIOTag(0x16du) */ +#define BM_GUI_TABLE BlockIOTag(0x16eu) /* VTB/GTB */ +#define BM_SYSTEM_TABLE BlockIOTag(0x16fu) /* VTB/GTB */ +# define DMA_GUI_COMMAND__BYTE_COUNT_MASK 0x001ffff0 +# define DMA_GUI_COMMAND__HOLD_VIDEO_OFFSET 0x40000000 +# define DMA_GUI_COMMAND__EOL 0x80000000 +# define SYSTEM_TRIGGER_MASK 0x7 +# define SYSTEM_TRIGGER_SYSTEM_TO_VIDEO 0x0 +# define SYSTEM_TRIGGER_VIDEO_TO_SYSTEM 0x1 +# define SYSTEM_TRIGGER_VIDEO_TO_SYSTEM_AFTER_BUF0_READY 0x2 +# define SYSTEM_TRIGGER_VIDEO_TO_SYSTEM_AFTER_BUF1_READY 0x3 +# define SYSTEM_TRIGGER_VIDEO_TO_SYSTEM_AFTER_SNAPSHOT_READY 0x4 +# define SYSTEM_TRIGGER_SYSTEM_TO_MPP 0x5 +/* ? BlockIOTag(0x170u) */ +/* ? BlockIOTag(0x171u) */ +/* ? BlockIOTag(0x172u) */ +/* ? BlockIOTag(0x173u) */ +/* ? BlockIOTag(0x174u) */ +#define SCALER_BUF0_OFFSET_V BlockIOTag(0x175u) /* GTPro */ +#define SCALER_BUF0_OFFSET_U BlockIOTag(0x176u) /* GTPro */ +#define SCALER_BUF1_OFFSET_V BlockIOTag(0x177u) /* GTPro */ +#define SCALER_BUF1_OFFSET_U BlockIOTag(0x178u) /* GTPro */ +/* ? BlockIOTag(0x179u) */ +/* ? BlockIOTag(0x17au) */ +/* ? BlockIOTag(0x17bu) */ +/* ? BlockIOTag(0x17cu) */ +/* ? BlockIOTag(0x17du) */ +/* ? BlockIOTag(0x17eu) */ +/* ? BlockIOTag(0x17fu) */ +/* ? BlockIOTag(0x180u) */ +/* ? BlockIOTag(0x181u) */ +/* ? BlockIOTag(0x182u) */ +/* ? BlockIOTag(0x183u) */ +/* ? BlockIOTag(0x184u) */ +/* ? BlockIOTag(0x185u) */ +/* ? BlockIOTag(0x186u) */ +/* ? BlockIOTag(0x187u) */ +/* ? BlockIOTag(0x188u) */ +/* ? BlockIOTag(0x189u) */ +/* ? BlockIOTag(0x18au) */ +/* ? BlockIOTag(0x18bu) */ +/* ? BlockIOTag(0x18cu) */ +/* ? BlockIOTag(0x18du) */ +/* ? BlockIOTag(0x18eu) */ +/* ? BlockIOTag(0x18fu) */ +#define VERTEX_1_S BlockIOTag(0x190u) /* GTPro */ +#define VERTEX_1_T BlockIOTag(0x191u) /* GTPro */ +#define VERTEX_1_W BlockIOTag(0x192u) /* GTPro */ +#define VERTEX_1_SPEC_ARGB BlockIOTag(0x193u) /* GTPro */ +#define VERTEX_1_Z BlockIOTag(0x194u) /* GTPro */ +#define VERTEX_1_ARGB BlockIOTag(0x195u) /* GTPro */ +#define VERTEX_1_X_Y BlockIOTag(0x196u) /* GTPro */ +#define ONE_OVER_AREA BlockIOTag(0x197u) /* GTPro */ +#define VERTEX_2_S BlockIOTag(0x198u) /* GTPro */ +#define VERTEX_2_T BlockIOTag(0x199u) /* GTPro */ +#define VERTEX_2_W BlockIOTag(0x19au) /* GTPro */ +#define VERTEX_2_SPEC_ARGB BlockIOTag(0x19bu) /* GTPro */ +#define VERTEX_2_Z BlockIOTag(0x19cu) /* GTPro */ +#define VERTEX_2_ARGB BlockIOTag(0x19du) /* GTPro */ +#define VERTEX_2_X_Y BlockIOTag(0x19eu) /* GTPro */ +/* ONE_OVER_AREA BlockIOTag(0x19fu) */ /* Duplicate */ +#define VERTEX_3_S BlockIOTag(0x1a0u) /* GTPro */ +#define VERTEX_3_T BlockIOTag(0x1a1u) /* GTPro */ +#define VERTEX_3_W BlockIOTag(0x1a2u) /* GTPro */ +#define VERTEX_3_SPEC_ARGB BlockIOTag(0x1a3u) /* GTPro */ +#define VERTEX_3_Z BlockIOTag(0x1a4u) /* GTPro */ +#define VERTEX_3_ARGB BlockIOTag(0x1a5u) /* GTPro */ +#define VERTEX_3_X_Y BlockIOTag(0x1a6u) /* GTPro */ +/* ONE_OVER_AREA BlockIOTag(0x1a7u) */ /* Duplicate */ +#define VERTEX_3_SECONDARY_S BlockIOTag(0x1a8u) /* GTPro */ +#define VERTEX_3_SECONDARY_T BlockIOTag(0x1a9u) /* GTPro */ +#define VERTEX_3_SECONDARY_W BlockIOTag(0x1aau) /* GTPro */ +/* VERTEX_1_S BlockIOTag(0x1abu) */ /* Duplicate */ +/* VERTEX_1_T BlockIOTag(0x1acu) */ /* Duplicate */ +/* VERTEX_1_W BlockIOTag(0x1adu) */ /* Duplicate */ +/* VERTEX_2_S BlockIOTag(0x1aeu) */ /* Duplicate */ +/* VERTEX_2_T BlockIOTag(0x1afu) */ /* Duplicate */ +/* VERTEX_2_W BlockIOTag(0x1b0u) */ /* Duplicate */ +/* VERTEX_3_S BlockIOTag(0x1b1u) */ /* Duplicate */ +/* VERTEX_3_T BlockIOTag(0x1b2u) */ /* Duplicate */ +/* VERTEX_3_W BlockIOTag(0x1b3u) */ /* Duplicate */ +/* VERTEX_1_SPEC_ARGB BlockIOTag(0x1b4u) */ /* Duplicate */ +/* VERTEX_2_SPEC_ARGB BlockIOTag(0x1b5u) */ /* Duplicate */ +/* VERTEX_3_SPEC_ARGB BlockIOTag(0x1b6u) */ /* Duplicate */ +/* VERTEX_1_Z BlockIOTag(0x1b7u) */ /* Duplicate */ +/* VERTEX_2_Z BlockIOTag(0x1b8u) */ /* Duplicate */ +/* VERTEX_3_Z BlockIOTag(0x1b9u) */ /* Duplicate */ +/* VERTEX_1_ARGB BlockIOTag(0x1bau) */ /* Duplicate */ +/* VERTEX_2_ARGB BlockIOTag(0x1bbu) */ /* Duplicate */ +/* VERTEX_3_ARGB BlockIOTag(0x1bcu) */ /* Duplicate */ +/* VERTEX_1_X_Y BlockIOTag(0x1bdu) */ /* Duplicate */ +/* VERTEX_2_X_Y BlockIOTag(0x1beu) */ /* Duplicate */ +/* VERTEX_3_X_Y BlockIOTag(0x1bfu) */ /* Duplicate */ +#define ONE_OVER_AREA_UC BlockIOTag(0x1c0u) /* GTPro */ +#define SETUP_CNTL BlockIOTag(0x1c1u) /* GTPro */ +/* ? BlockIOTag(0x1c2u) */ +/* ? BlockIOTag(0x1c3u) */ +/* ? BlockIOTag(0x1c4u) */ +/* ? BlockIOTag(0x1c5u) */ +/* ? BlockIOTag(0x1c6u) */ +/* ? BlockIOTag(0x1c7u) */ +/* ? BlockIOTag(0x1c8u) */ +/* ? BlockIOTag(0x1c9u) */ +#define VERTEX_1_SECONDARY_S BlockIOTag(0x1cau) /* GTPro */ +#define VERTEX_1_SECONDARY_T BlockIOTag(0x1cbu) /* GTPro */ +#define VERTEX_1_SECONDARY_W BlockIOTag(0x1ccu) /* GTPro */ +#define VERTEX_2_SECONDARY_S BlockIOTag(0x1cdu) /* GTPro */ +#define VERTEX_2_SECONDARY_T BlockIOTag(0x1ceu) /* GTPro */ +#define VERTEX_2_SECONDARY_W BlockIOTag(0x1cfu) /* GTPro */ +/* IDCT and DVD's subpicture direct support (Rage Mobility only) */ +#define SUBPIC_CNTL BlockIOTag(0x1d0u) +# define SUBPIC_ON 0x00000001UL +# define BTN_HLI_ON 0x00000002UL +# define SP_HORZ_MODE 0x00000010UL +# define SP_VERT_MODE 0x00000020UL +# define SP_ODD_FIELD 0x00000100UL +# define SP_BUF_SELECT 0x00000200UL +# define SP_NO_R_EDGE_BLEND 0x00000400UL +#define SUBPIC_DEFCOLON BlockIOTag(0x1d1u) +# define BKGD_PIX_CON 0x0000000FUL +# define PATT_PIX_CON 0x000000F0UL +# define EMPH_PIX1_CON 0x00000F00UL +# define EMPH_PIX2_CON 0x0000F000UL +# define BKGD_PIX_CLR 0x000F0000UL +# define PATT_PIX_CLR 0x00F00000UL +# define EMPH_PIX1_CLR 0x0F000000UL +# define EMPH_PIX2_CLR 0xF0000000UL +/* ? BlockIOTag(0x1d2u) */ +#define SUBPIC_Y_X_START BlockIOTag(0x1d3u) +#define SUBPIC_Y_X_END BlockIOTag(0x1d4u) +#define SUBPIC_V_INC BlockIOTag(0x1d5u) +#define SUBPIC_H_INC BlockIOTag(0x1d6u) +#define SUBPIC_BUF0_OFFSET BlockIOTag(0x1d7u) +#define SUBPIC_BUF1_OFFSET BlockIOTag(0x1d8u) +#define SUBPIC_LC0_OFFSET BlockIOTag(0x1d9u) +#define SUBPIC_LC1_OFFSET BlockIOTag(0x1dau) +#define SUBPIC_PITCH BlockIOTag(0x1dbu) +# define SUBPIC_BUF_PITCH 0x00000FC0UL +# define SUBPIC_LC_PITCH 0x0FC00000UL +#define SUBPIC_BTN_HLI_COLCON BlockIOTag(0x1dcu) +# define BTN_HLI_BKGD_PIX_CON 0x0000000FUL +# define BTN_HLI_PATT_PIX_CON 0x000000F0UL +# define BTN_HLI_EMPH_PIX1_CON 0x00000F00UL +# define BTN_HLI_EMPH_PIX2_CON 0x0000F000UL +# define BTN_HLI_BKGD_PIX_CLR 0x000F0000UL +# define BTN_HLI_PATT_PIX_CLR 0x00F00000UL +# define BTN_HLI_EMPH_PIX1_CLR 0x0F000000UL +# define BTN_HLI_EMPH_PIX2_CLR 0xF0000000UL +#define SUBPIC_BTN_Y_X_START BlockIOTag(0x1ddu) +#define SUBPIC_BTN_Y_X_END BlockIOTag(0x1deu) +#define SUBPIC_H_ACCUM_INIT BlockIOTag(0x1dfu) +#define IDCT_RUNS BlockIOTag(0x1e0u) +# define IDCT_RUNS_3 0x000000FFUL +# define IDCT_RUNS_2 0x0000FF00UL +# define IDCT_RUNS_1 0x00FF0000UL +# define IDCT_RUNS_0 0xFF000000UL +#define IDCT_LEVELS BlockIOTag(0x1e1u) +# define IDCT_LEVELS_HI 0x0000FFFFUL +# define IDCT_LEVELS_LO 0xFFFF0000UL +#define IDCT_RESERVE_REGISTER1 BlockIOTag(0x1e2u) +#define IDCT_RESERVE_REGISTER2 BlockIOTag(0x1e3u) +/* ? BlockIOTag(0x1e4u) */ +/* ? BlockIOTag(0x1e5u) */ +#define SUBPIC_V_ACCUM_INIT BlockIOTag(0x1e6u) +#define SUBPIC_PALETTE_INDEX BlockIOTag(0x1e7u) +#define SUBPIC_PALETTE_DATA BlockIOTag(0x1e8u) +/* ? BlockIOTag(0x1e9u) */ +/* ? BlockIOTag(0x1eau) */ +/* ? BlockIOTag(0x1ebu) */ +/* ? BlockIOTag(0x1ecu) */ +/* ? BlockIOTag(0x1edu) */ +/* ? BlockIOTag(0x1eeu) */ +#define IDCT_CONTROL BlockIOTag(0x1efu) +# define IDCT_LUMA_RD_FORMAT_MSK 0x00000003UL +# define IDCT_LUMA_RD_FORMAT_0123 0x00000000UL +# define IDCT_LUMA_RD_FORMAT_0246 0x00000001UL +# define IDCT_LUMA_RD_FORMAT_0819 0x00000002UL +# define IDCT_CHROMA_RD_FMT_MSK 0x0000000CUL +# define IDCT_CHROMA_RD_FMT_0123 0x00000000UL +# define IDCT_CHROMA_RD_FMT_0246 0x00000004UL +# define IDCT_CHROMA_RD_FMT_0819 0x00000008UL +# define IDCT_CTL_SCAN_PATTERN 0x00000010UL +# define IDCT_CTL_INTRA 0x00000020UL +# define IDCT_CTL_FLUSH 0x00000040UL +# define IDCT_CTL_PASSTHRU 0x00000080UL +# define IDCT_CTL_SW_RESET 0x00000100UL +# define IDCT_CONST_REQ 0x00000200UL +# define IDCT_SCRAMBLE 0x00000400UL +/* ? BlockIOTag(0x1f0u) */ +/* ? BlockIOTag(0x1f1u) */ +/* ? BlockIOTag(0x1f2u) */ +/* ? BlockIOTag(0x1f3u) */ +/* ? BlockIOTag(0x1f4u) */ +/* ? BlockIOTag(0x1f5u) */ +/* ? BlockIOTag(0x1f6u) */ +/* ? BlockIOTag(0x1f7u) */ +/* ? BlockIOTag(0x1f8u) */ +/* ? BlockIOTag(0x1f9u) */ +/* ? BlockIOTag(0x1fau) */ +/* ? BlockIOTag(0x1fbu) */ +/* ? BlockIOTag(0x1fcu) */ +/* ? BlockIOTag(0x1fdu) */ +/* ? BlockIOTag(0x1feu) */ +/* ? BlockIOTag(0x1ffu) */ + +/* Definitions for MEM_CNTL's CTL_MEM_?????_APER_ENDIAN fields */ +#define CTL_MEM_APER_BYTE_ENDIAN 0x00u +#define CTL_MEM_APER_WORD_ENDIAN 0x01u +#define CTL_MEM_APER_LONG_ENDIAN 0x02u +/* ? 0x03u */ + +/* Definitions for an ICS2595's programme word */ +#define ICS2595_CLOCK 0x000001f0ul +#define ICS2595_FB_DIV 0x0001fe00ul /* Feedback divider */ +#define ICS2595_POST_DIV 0x000c0000ul /* Post-divider */ +#define ICS2595_STOP 0x00300000ul /* Stop bits */ +#define ICS2595_TOGGLE (ICS2595_POST_DIV | ICS2595_STOP) + +/* Definitions for internal PLL registers on a 264xT */ +#define PLL_MPLL_CNTL 0x00u +#define MPLL_PC_GAIN 0x07u +#define MPLL_VC_GAIN 0x18u +#define MPLL_D_CYC 0x60u +#define MPLL_RANGE 0x80u +#define VPLL_CNTL 0x01u +#define VPLL_PC_GAIN 0x07u +#define VPLL_VC_GAIN 0x18u +#define VPLL_D_CYC 0x60u +#define VPLL_RANGE 0x80u +#define PLL_REF_DIV 0x02u +#define PLL_GEN_CNTL 0x03u +#define PLL_OVERRIDE 0x01u +#define PLL_SLEEP 0x01u /* GTPro */ +#define PLL_MCLK_RESET 0x02u +#define PLL_OSC_EN 0x04u +#define PLL_EXT_CLK_EN 0x08u +#define PLL_MCLK_SRC_SEL 0x70u +#define PLL_EXT_CLK_CNTL 0x80u /* CT/ET */ +#define PLL_DLL_PWDN 0x80u /* VTB/GTB/LT */ +#define PLL_MCLK_FB_DIV 0x04u +#define PLL_VCLK_CNTL 0x05u +#define PLL_VCLK_SRC_SEL 0x03u +#define PLL_VCLK_RESET 0x04u +#define PLL_VCLK_INVERT 0x08u +#define PLL_ECP_DIV 0x30u /* VT/GT */ +#define PLL_ERATE_GT_XRATE 0x40u /* VT/GT */ +#define PLL_SCALER_LOCK_EN 0x80u /* VT/GT */ +#define PLL_VCLK_POST_DIV 0x06u +#define PLL_VCLK0_POST_DIV 0x03u +#define PLL_VCLK1_POST_DIV 0x0cu +#define PLL_VCLK2_POST_DIV 0x30u +#define PLL_VCLK3_POST_DIV 0xc0u +#define PLL_VCLK0_FB_DIV 0x07u +#define PLL_VCLK1_FB_DIV 0x08u +#define PLL_VCLK2_FB_DIV 0x09u +#define PLL_VCLK3_FB_DIV 0x0au +#define PLL_XCLK_CNTL 0x0bu /* VT/GT */ +#define PLL_XCLK_MCLK_RATIO 0x03u +#define PLL_XCLK_SRC_SEL 0x07u /* VTB/GTB/LT */ +#define PLL_MFB_TIMES_4_2B 0x08u +#define PLL_VCLK0_XDIV 0x10u +#define PLL_VCLK1_XDIV 0x20u +#define PLL_VCLK2_XDIV 0x40u +#define PLL_VCLK3_XDIV 0x80u +#define PLL_FCP_CNTL 0x0cu /* VT/GT */ +#define PLL_FCP_POST_DIV 0x0fu +#define PLL_FCP_SRC_SEL 0x70u +#define PLL_DCLK_BY2_EN 0x80u +#define PLL_DLL_CNTL 0x0cu /* VTB/GTB/LT */ +#define PLL_DLL_REF_SRC 0x03u +#define PLL_DLL_FB_SRC 0x0cu +#define PLL_DLL_GAIN 0x30u +#define PLL_DLL_RESET 0x40u +#define PLL_DLL_HCLK_OUT_EN 0x80u +#define PLL_VFC_CNTL 0x0du /* VT/GT */ +#define PLL_DCLK_INVB 0x01u +#define PLL_DCLKBY2_EN 0x02u +#define PLL_VFC_2PHASE 0x04u +#define PLL_VFC_DELAY 0x18u +#define PLL_VFC_DCLKBY2_SHIFT 0x20u +/* ? 0x40u */ +#define PLL_TST_SRC_SEL_BIT5 0x80u /* VTB/GTB/LT */ +#define PLL_TEST_CNTL 0x0eu +#define PLL_TST_SRC_SEL 0x1fu +#define PLL_TST_DIVIDERS 0x20u +#define PLL_TST_MASK_READ 0x40u +#define PLL_TST_ANALOG_MON_EN 0x80u +#define PLL_TEST_COUNT 0x0fu +#define PLL_LVDSPLL_CNTL0 0x10u /* LT */ +#define PLL_FPDI_NS_TIMING 0x01u +#define PLL_CURR_LEVEL 0x0eu +#define PLL_LVDS_TEST_MODE 0xf0u +#define PLL_LVDSPLL_CNTL1 0x11u /* LT */ +#define PLL_LPPL_RANGE 0x01u +#define PLL_LPLL_DUTY 0x06u +#define PLL_LPLL_VC_GAIN 0x18u +#define PLL_LPLL_CP_GAIN 0xe0u +#define PLL_AGP1_CNTL 0x12u /* GTPro */ +#define PLL_AGP2_CNTL 0x13u /* GTPro */ +#define PLL_DLL2_CNTL 0x14u /* GTPro */ +#define PLL_SCLK_FB_DIV 0x15u /* GTPro */ +#define PLL_SPLL_CNTL1 0x16u /* GTPro */ +#define PLL_SPLL_CNTL2 0x17u /* GTPro */ +#define PLL_APLL_STRAPS 0x18u /* GTPro */ +#define PLL_EXT_VPLL_CNTL 0x19u /* GTPro */ +#define PLL_EXT_VPLL_REF_SRC 0x03u +#define PLL_EXT_VPLL_EN 0x04u +#define PLL_EXT_VPLL_VGA_EN 0x08u +#define PLL_EXT_VPLL_INSYNC 0x10u +/* ? 0x60u */ +#define PLL_EXT_V2PLL_EN 0x80u +#define PLL_EXT_VPLL_REF_DIV 0x1au /* GTPro */ +#define PLL_EXT_VPLL_FB_DIV 0x1bu /* GTPro */ +#define PLL_EXT_VPLL_MSB 0x1cu /* GTPro */ +#define PLL_HTOTAL_CNTL 0x1du /* GTPro */ +#define PLL_BYTE_CLK_CNTL 0x1eu /* GTPro */ +#define PLL_TV_REF_DIV 0x1fu /* LTPro */ +#define PLL_TV_FB_DIV 0x20u /* LTPro */ +#define PLL_TV_CNTL 0x21u /* LTPro */ +#define PLL_TV_GEN_CNTL 0x22u /* LTPro */ +#define PLL_V2_CNTL 0x23u /* LTPro */ +#define PLL_V2_GEN_CNTL 0x24u /* LTPro */ +#define PLL_V2_REF_DIV 0x25u /* LTPro */ +#define PLL_V2_FB_DIV 0x26u /* LTPro */ +#define PLL_V2_MSB 0x27u /* LTPro */ +#define PLL_HTOTAL2_CNTL 0x28u /* LTPro */ +#define PLL_YCLK_CNTL 0x29u /* XC/XL */ +#define PM_DYN_CLK_CNTL 0x2au /* XC/XL */ +/* ? 0x2bu */ +/* ? 0x2cu */ +/* ? 0x2du */ +/* ? 0x2eu */ +/* ? 0x2fu */ +/* ? 0x30u */ +/* ? 0x31u */ +/* ? 0x32u */ +/* ? 0x33u */ +/* ? 0x34u */ +/* ? 0x35u */ +/* ? 0x36u */ +/* ? 0x37u */ +/* ? 0x38u */ +/* ? 0x39u */ +/* ? 0x3au */ +/* ? 0x3bu */ +/* ? 0x3cu */ +/* ? 0x3du */ +/* ? 0x3eu */ +/* ? 0x3fu */ + +/* Definitions for an LTPro's 32-bit LCD registers */ +#define LCD_CONFIG_PANEL 0x00u /* See LT's CONFIG_PANEL (0x1d) */ +#define LCD_GEN_CNTL 0x01u /* See LT's LCD_GEN_CTRL (0x35) */ +#define LCD_DSTN_CONTROL 0x02u /* See LT's DSTN_CONTROL (0x1f) */ +#define LCD_HFB_PITCH_ADDR 0x03u /* See LT's HFB_PITCH_ADDR (0x2a) */ +#define LCD_HORZ_STRETCHING 0x04u /* See LT's HORZ_STRETCHING (0x32) */ +#define LCD_VERT_STRETCHING 0x05u /* See LT's VERT_STRETCHING (0x33) */ +#define LCD_EXT_VERT_STRETCH 0x06u +#define VERT_STRETCH_RATIO3 0x000003fful +#define FORCE_DAC_DATA 0x000000fful +#define FORCE_DAC_DATA_SEL 0x00000300ul +#define VERT_STRETCH_MODE 0x00000400ul +#define VERT_PANEL_SIZE 0x003ff800ul +#define AUTO_VERT_RATIO 0x00400000ul +#define USE_AUTO_FP_POS 0x00800000ul +#define USE_AUTO_LCD_VSYNC 0x01000000ul +/* ? 0xfe000000ul */ +#define LCD_LT_GIO 0x07u /* See LT's LT_GIO (0x2f) */ +#define LCD_POWER_MANAGEMENT 0x08u /* See LT's POWER_MANAGEMENT (0x36) */ +#define LCD_ZVGPIO 0x09u +#define LCD_ICON_CLR0 0x0au /* XC/XL */ +#define LCD_ICON_CLR1 0x0bu /* XC/XL */ +#define LCD_ICON_OFFSET 0x0cu /* XC/XL */ +#define LCD_ICON_HORZ_VERT_POSN 0x0du /* XC/XL */ +#define LCD_ICON_HORZ_VERT_OFF 0x0eu /* XC/XL */ +#define LCD_ICON2_CLR0 0x0fu /* XC/XL */ +#define LCD_ICON2_CLR1 0x10u /* XC/XL */ +#define LCD_ICON2_OFFSET 0x11u /* XC/XL */ +#define LCD_ICON2_HORZ_VERT_POSN 0x12u /* XC/XL */ +#define LCD_ICON2_HORZ_VERT_OFF 0x13u /* XC/XL */ +#define LCD_MISC_CNTL 0x14u /* XC/XL */ +#define BL_MOD_LEVEL 0x000000fful +#define BIAS_MOD_LEVEL 0x0000ff00ul +#define BLMOD_EN 0x00010000ul +#define BIASMOD_EN 0x00020000ul +/* ? 0x00040000ul */ +#define PWRSEQ_MODE 0x00080000ul +#define APC_EN 0x00100000ul +#define MONITOR_DET_EN 0x00200000ul +#define FORCE_DAC_DATA_SEL_X 0x00c00000ul +#define FORCE_DAC_DATA_X 0xff000000ul +#define LCD_TMDS_CNTL 0x15u /* XC/XL */ +#define LCD_TMDS_SYNC_CHAR_SETA 0x16u /* XC/XL */ +#define LCD_TMDS_SYNC_CHAR_SETB 0x17u /* XC/XL */ +#define LCD_TMDS_SRC 0x18u /* XC/XL */ +#define LCD_PLTSTBLK_CNTL 0x19u /* XC/XL */ +#define LCD_SYNC_GEN_CNTL 0x1au /* XC/XL */ +#define LCD_PATTERN_GEN_SEED 0x1bu /* XC/XL */ +#define LCD_APC_CNTL 0x1cu /* XC/XL */ +#define LCD_POWER_MANAGEMENT_2 0x1du /* XC/XL */ +#define LCD_XCLK_DISP_PM_EN 0x00000001ul +#define LCD_XCLK_DISP2_PM_EN 0x00000002ul /* Mobility */ +#define LCD_XCLK_VID_PM_EN 0x00000004ul +#define LCD_XCLK_SCL_PM_EN 0x00000008ul +#define LCD_XCLK_GUI_PM_EN 0x00000010ul +#define LCD_XCLK_SUB_PM_EN 0x00000020ul +/* ? 0x000000c0ul */ +#define LCD_MCLK_PM_EN 0x00000100ul +#define LCD_SS_EN 0x00000200ul +#define LCD_BLON_DIGON_EN 0x00000400ul +/* ? 0x00000800ul */ +#define LCD_PM_DYN_XCLK_SYNC 0x00003000ul +#define LCD_SEL_W4MS 0x00004000ul +/* ? 0x00008000ul */ +#define LCD_PM_DYN_XCLK_EN 0x00010000ul +#define LCD_PM_XCLK_ALWAYS 0x00020000ul +#define LCD_PM_DYN_XCLK_STATUS 0x00040000ul +#define LCD_PCI_ACC_DIS 0x00080000ul +#define LCD_PM_DYN_XCLK_DISP 0x00100000ul +#define LCD_PM_DYN_XCLK_DISP2 0x00200000ul /* Mobility */ +#define LCD_PM_DYN_XCLK_VID 0x00400000ul +#define LCD_PM_DYN_XCLK_HFB 0x00800000ul +#define LCD_PM_DYN_XCLK_SCL 0x01000000ul +#define LCD_PM_DYN_XCLK_SUB 0x02000000ul +#define LCD_PM_DYN_XCLK_GUI 0x04000000ul +#define LCD_PM_DYN_XCLK_HOST 0x08000000ul +/* ? 0xf0000000ul */ +#define LCD_PRI_ERR_PATTERN 0x1eu /* XC/XL */ +#define LCD_CUR_ERR_PATTERN 0x1fu /* XC/XL */ +#define LCD_PLTSTBLK_RPT 0x20u /* XC/XL */ +#define LCD_SYNC_RPT 0x21u /* XC/XL */ +#define LCD_CRC_PATTERN_RPT 0x22u /* XC/XL */ +#define LCD_PL_TRANSMITTER_CNTL 0x23u /* XC/XL */ +#define LCD_PL_PLL_CNTL 0x24u /* XC/XL */ +#define LCD_ALPHA_BLENDING 0x25u /* XC/XL */ +#define LCD_PORTRAIT_GEN_CNTL 0x26u /* XC/XL */ +#define LCD_APC_CTRL_IO 0x27u /* XC/XL */ +#define LCD_TEST_IO 0x28u /* XC/XL */ +/* ? 0x29u */ +#define LCD_DP1_MEM_ACCESS 0x2au /* XC/XL */ +#define LCD_DP0_MEM_ACCESS 0x2bu /* XC/XL */ +#define LCD_DP0_DEBUG_A 0x2cu /* XC/XL */ +#define LCD_DP0_DEBUG_B 0x2du /* XC/XL */ +#define LCD_DP1_DEBUG_A 0x2eu /* XC/XL */ +#define LCD_DP1_DEBUG_B 0x2fu /* XC/XL */ +#define LCD_DPCTRL_DEBUG_A 0x30u /* XC/XL */ +#define LCD_DPCTRL_DEBUG_B 0x31u /* XC/XL */ +#define LCD_MEMBLK_DEBUG 0x32u /* XC/XL */ +#define LCD_APC_LUT_AB 0x33u /* XC/XL */ +#define LCD_APC_LUT_CD 0x34u /* XC/XL */ +#define LCD_APC_LUT_EF 0x35u /* XC/XL */ +#define LCD_APC_LUT_GH 0x36u /* XC/XL */ +#define LCD_APC_LUT_IJ 0x37u /* XC/XL */ +#define LCD_APC_LUT_KL 0x38u /* XC/XL */ +#define LCD_APC_LUT_MN 0x39u /* XC/XL */ +#define LCD_APC_LUT_OP 0x3au /* XC/XL */ +/* ? 0x3bu */ +/* ? 0x3cu */ +/* ? 0x3du */ +/* ? 0x3eu */ +/* ? 0x3fu */ + +/* Definitions for an LTPro's TV registers */ +/* ? 0x00u */ +/* ? 0x01u */ +/* ? 0x02u */ +/* ? 0x03u */ +/* ? 0x04u */ +/* ? 0x05u */ +/* ? 0x06u */ +/* ? 0x07u */ +/* ? 0x08u */ +/* ? 0x09u */ +/* ? 0x0au */ +/* ? 0x0bu */ +/* ? 0x0cu */ +/* ? 0x0du */ +/* ? 0x0eu */ +/* ? 0x0fu */ +#define TV_MASTER_CNTL 0x10u +/* ? 0x11u */ +#define TV_RGB_CNTL 0x12u +/* ? 0x13u */ +#define TV_SYNC_CNTL 0x14u +/* ? 0x15u */ +/* ? 0x16u */ +/* ? 0x17u */ +/* ? 0x18u */ +/* ? 0x19u */ +/* ? 0x1au */ +/* ? 0x1bu */ +/* ? 0x1cu */ +/* ? 0x1du */ +/* ? 0x1eu */ +/* ? 0x1fu */ +#define TV_HTOTAL 0x20u +#define TV_HDISP 0x21u +#define TV_HSIZE 0x22u +#define TV_HSTART 0x23u +#define TV_HCOUNT 0x24u +#define TV_VTOTAL 0x25u +#define TV_VDISP 0x26u +#define TV_VCOUNT 0x27u +#define TV_FTOTAL 0x28u +#define TV_FCOUNT 0x29u +#define TV_FRESTART 0x2au +#define TV_HRESTART 0x2bu +#define TV_VRESTART 0x2cu +/* ? 0x2du */ +/* ? 0x2eu */ +/* ? 0x2fu */ +/* ? 0x30u */ +/* ? 0x31u */ +/* ? 0x32u */ +/* ? 0x33u */ +/* ? 0x34u */ +/* ? 0x35u */ +/* ? 0x36u */ +/* ? 0x37u */ +/* ? 0x38u */ +/* ? 0x39u */ +/* ? 0x3au */ +/* ? 0x3bu */ +/* ? 0x3cu */ +/* ? 0x3du */ +/* ? 0x3eu */ +/* ? 0x3fu */ +/* ? 0x40u */ +/* ? 0x41u */ +/* ? 0x42u */ +/* ? 0x43u */ +/* ? 0x44u */ +/* ? 0x45u */ +/* ? 0x46u */ +/* ? 0x47u */ +/* ? 0x48u */ +/* ? 0x49u */ +/* ? 0x4au */ +/* ? 0x4bu */ +/* ? 0x4cu */ +/* ? 0x4du */ +/* ? 0x4eu */ +/* ? 0x4fu */ +/* ? 0x50u */ +/* ? 0x51u */ +/* ? 0x52u */ +/* ? 0x53u */ +/* ? 0x54u */ +/* ? 0x55u */ +/* ? 0x56u */ +/* ? 0x57u */ +/* ? 0x58u */ +/* ? 0x59u */ +/* ? 0x5au */ +/* ? 0x5bu */ +/* ? 0x5cu */ +/* ? 0x5du */ +/* ? 0x5eu */ +/* ? 0x5fu */ +#define TV_HOST_READ_DATA 0x60u +#define TV_HOST_WRITE_DATA 0x61u +#define TV_HOST_RD_WT_CNTL 0x62u +/* ? 0x63u */ +/* ? 0x64u */ +/* ? 0x65u */ +/* ? 0x66u */ +/* ? 0x67u */ +/* ? 0x68u */ +/* ? 0x69u */ +/* ? 0x6au */ +/* ? 0x6bu */ +/* ? 0x6cu */ +/* ? 0x6du */ +/* ? 0x6eu */ +/* ? 0x6fu */ +#define TV_VSCALER_CNTL 0x70u +#define TV_TIMING_CNTL 0x71u +#define TV_GAMMA_CNTL 0x72u +#define TV_Y_FALL_CNTL 0x73u +#define TV_Y_RISE_CNTL 0x74u +#define TV_Y_SAW_TOOTH_CNTL 0x75u +/* ? 0x76u */ +/* ? 0x77u */ +/* ? 0x78u */ +/* ? 0x79u */ +/* ? 0x7au */ +/* ? 0x7bu */ +/* ? 0x7cu */ +/* ? 0x7du */ +/* ? 0x7eu */ +/* ? 0x7fu */ +#define TV_MODULATOR_CNTL1 0x80u +#define TV_MODULATOR_CNTL2 0x81u +/* ? 0x82u */ +/* ? 0x83u */ +/* ? 0x84u */ +/* ? 0x85u */ +/* ? 0x86u */ +/* ? 0x87u */ +/* ? 0x88u */ +/* ? 0x89u */ +/* ? 0x8au */ +/* ? 0x8bu */ +/* ? 0x8cu */ +/* ? 0x8du */ +/* ? 0x8eu */ +/* ? 0x8fu */ +#define TV_PRE_DAC_MUX_CNTL 0x90u +/* ? 0x91u */ +/* ? 0x92u */ +/* ? 0x93u */ +/* ? 0x94u */ +/* ? 0x95u */ +/* ? 0x96u */ +/* ? 0x97u */ +/* ? 0x98u */ +/* ? 0x99u */ +/* ? 0x9au */ +/* ? 0x9bu */ +/* ? 0x9cu */ +/* ? 0x9du */ +/* ? 0x9eu */ +/* ? 0x9fu */ +#define TV_DAC_CNTL 0xa0u +/* ? 0xa1u */ +/* ? 0xa2u */ +/* ? 0xa3u */ +/* ? 0xa4u */ +/* ? 0xa5u */ +/* ? 0xa6u */ +/* ? 0xa7u */ +/* ? 0xa8u */ +/* ? 0xa9u */ +/* ? 0xaau */ +/* ? 0xabu */ +/* ? 0xacu */ +/* ? 0xadu */ +/* ? 0xaeu */ +/* ? 0xafu */ +#define TV_CRC_CNTL 0xb0u +#define TV_VIDEO_PORT_SIG 0xb1u +/* ? 0xb2u */ +/* ? 0xb3u */ +/* ? 0xb4u */ +/* ? 0xb5u */ +/* ? 0xb6u */ +/* ? 0xb7u */ +#define TV_VBI_CC_CNTL 0xb8u +#define TV_VBI_EDS_CNTL 0xb9u +#define TV_VBI_20BIT_CNTL 0xbau +/* ? 0xbbu */ +/* ? 0xbcu */ +#define TV_VBI_DTO_CNTL 0xbdu +#define TV_VBI_LEVEL_CNTL 0xbeu +/* ? 0xbfu */ +#define TV_UV_ADR 0xc0u +#define TV_FIFO_TEST_CNTL 0xc1u +/* ? 0xc2u */ +/* ? 0xc3u */ +/* ? 0xc4u */ +/* ? 0xc5u */ +/* ? 0xc6u */ +/* ? 0xc7u */ +/* ? 0xc8u */ +/* ? 0xc9u */ +/* ? 0xcau */ +/* ? 0xcbu */ +/* ? 0xccu */ +/* ? 0xcdu */ +/* ? 0xceu */ +/* ? 0xcfu */ +/* ? 0xd0u */ +/* ? 0xd1u */ +/* ? 0xd2u */ +/* ? 0xd3u */ +/* ? 0xd4u */ +/* ? 0xd5u */ +/* ? 0xd6u */ +/* ? 0xd7u */ +/* ? 0xd8u */ +/* ? 0xd9u */ +/* ? 0xdau */ +/* ? 0xdbu */ +/* ? 0xdcu */ +/* ? 0xddu */ +/* ? 0xdeu */ +/* ? 0xdfu */ +/* ? 0xe0u */ +/* ? 0xe1u */ +/* ? 0xe2u */ +/* ? 0xe3u */ +/* ? 0xe4u */ +/* ? 0xe5u */ +/* ? 0xe6u */ +/* ? 0xe7u */ +/* ? 0xe8u */ +/* ? 0xe9u */ +/* ? 0xeau */ +/* ? 0xebu */ +/* ? 0xecu */ +/* ? 0xedu */ +/* ? 0xeeu */ +/* ? 0xefu */ +/* ? 0xf0u */ +/* ? 0xf1u */ +/* ? 0xf2u */ +/* ? 0xf3u */ +/* ? 0xf4u */ +/* ? 0xf5u */ +/* ? 0xf6u */ +/* ? 0xf7u */ +/* ? 0xf8u */ +/* ? 0xf9u */ +/* ? 0xfau */ +/* ? 0xfbu */ +/* ? 0xfcu */ +/* ? 0xfdu */ +/* ? 0xfeu */ +/* ? 0xffu */ + +/* Miscellaneous */ + +/* Current X, Y & Dest X, Y mask */ +#define COORD_MASK 0x07ffu + +/* Pixel widths */ +#define PIX_WIDTH_1BPP 0x00u +#define PIX_WIDTH_4BPP 0x01u /* CRTC2: 8bpp */ +#define PIX_WIDTH_8BPP 0x02u /* CRTC2: Undefined */ +#define PIX_WIDTH_15BPP 0x03u +#define PIX_WIDTH_16BPP 0x04u +#define PIX_WIDTH_24BPP 0x05u +#define PIX_WIDTH_32BPP 0x06u +#define PIX_WIDTH_YUV422 0x07u /* CRTC2 only */ + +/* Source definitions */ +#define SRC_BKGD 0x00u +#define SRC_FRGD 0x01u +#define SRC_HOST 0x02u +#define SRC_BLIT 0x03u +#define SRC_PATTERN 0x04u +#define SRC_SCALER_3D 0x05u +/* ? 0x06u */ +/* ? 0x07u */ + +/* The Mixes */ +#define MIX_MASK 0x001fu + +#define MIX_NOT_DST 0x0000u +#define MIX_0 0x0001u +#define MIX_1 0x0002u +#define MIX_DST 0x0003u +#define MIX_NOT_SRC 0x0004u +#define MIX_XOR 0x0005u +#define MIX_XNOR 0x0006u +#define MIX_SRC 0x0007u +#define MIX_NAND 0x0008u +#define MIX_NOT_SRC_OR_DST 0x0009u +#define MIX_SRC_OR_NOT_DST 0x000au +#define MIX_OR 0x000bu +#define MIX_AND 0x000cu +#define MIX_SRC_AND_NOT_DST 0x000du +#define MIX_NOT_SRC_AND_DST 0x000eu +#define MIX_NOR 0x000fu + +#define MIX_MIN 0x0010u +#define MIX_DST_MINUS_SRC 0x0011u +#define MIX_SRC_MINUS_DST 0x0012u +#define MIX_PLUS 0x0013u +#define MIX_MAX 0x0014u +#define MIX_HALF__DST_MINUS_SRC 0x0015u +#define MIX_HALF__SRC_MINUS_DST 0x0016u +#define MIX_AVERAGE 0x0017u +#define MIX_DST_MINUS_SRC_SAT 0x0018u +#define MIX_SRC_MINUS_DST_SAT 0x001au +#define MIX_HALF__DST_MINUS_SRC_SAT 0x001cu +#define MIX_HALF__SRC_MINUS_DST_SAT 0x001eu +#define MIX_AVERAGE_SAT 0x001fu +#define MIX_FN_PAINT MIX_SRC + + +#endif diff --git a/contrib/vidix/drivers/mach64_vid.c b/contrib/vidix/drivers/mach64_vid.c new file mode 100644 index 000000000..02447af19 --- /dev/null +++ b/contrib/vidix/drivers/mach64_vid.c @@ -0,0 +1,1390 @@ +/* + mach64_vid - VIDIX based video driver for Mach64 and 3DRage chips + Copyrights 2002 Nick Kurshev. This file is based on sources from + GATOS (gatos.sf.net) and X11 (www.xfree86.org) + Licence: GPL + WARNING: THIS DRIVER IS IN BETTA STAGE +*/ +#include <errno.h> +#include <stdio.h> +#include <stdlib.h> +#include <string.h> +#include <math.h> +#include <inttypes.h> +#include <fcntl.h> +#include <limits.h> +#include <sys/mman.h> /* for m(un)lock */ +#ifdef HAVE_MALLOC_H +#include <malloc.h> +#ifdef HAVE_MEMALIGN +#define MACH64_ENABLE_BM 1 +#endif +#endif + +#include "vidix.h" +#include "fourcc.h" +#include "libdha.h" +#include "pci_ids.h" +#include "pci_names.h" +#include "bswap.h" + +#include "mach64.h" + +#define UNUSED(x) ((void)(x)) /**< Removes warning about unused arguments */ + +#define VIDIX_STATIC mach64_ + +#ifdef MACH64_ENABLE_BM + +#define cpu_to_le32(a) (a) +#define VIRT_TO_CARD(a,b,c) bm_virt_to_bus(a,b,c) +#pragma pack(1) +typedef struct +{ + uint32_t framebuf_offset; + uint32_t sys_addr; + uint32_t command; + uint32_t reserved; +} bm_list_descriptor; +#pragma pack() +static void *mach64_dma_desc_base[64]; +static unsigned long bus_addr_dma_desc = 0; +static unsigned long *dma_phys_addrs; +#endif + +static void *mach64_mmio_base = 0; +static void *mach64_mem_base = 0; +static int32_t mach64_overlay_offset = 0; +static uint32_t mach64_ram_size = 0; +static uint32_t mach64_buffer_base[64][3]; +static int num_mach64_buffers=-1; +static int supports_planar=0; +static int supports_colour_adj=0; +static int supports_idct=0; +static int supports_subpic=0; +static int supports_lcd_v_stretch=0; + +pciinfo_t pci_info; +static int probed = 0; +static int __verbose = 0; + +#define VERBOSE_LEVEL 2 + +typedef struct bes_registers_s +{ + /* base address of yuv framebuffer */ + uint32_t yuv_base; + uint32_t fourcc; + /* YUV BES registers */ + uint32_t reg_load_cntl; + uint32_t scale_inc; + uint32_t y_x_start; + uint32_t y_x_end; + uint32_t vid_buf_pitch; + uint32_t height_width; + + uint32_t scale_cntl; + uint32_t exclusive_horz; + uint32_t auto_flip_cntl; + uint32_t filter_cntl; + uint32_t key_cntl; + uint32_t test; + /* Configurable stuff */ + + int brightness; + int saturation; + + int ckey_on; + uint32_t graphics_key_clr; + uint32_t graphics_key_msk; + + int deinterlace_on; + uint32_t deinterlace_pattern; + +} bes_registers_t; + +static bes_registers_t besr; + +typedef struct video_registers_s +{ + const char * sname; + uint32_t name; + uint32_t value; +}video_registers_t; + +static bes_registers_t besr; + +/* Graphic keys */ +static vidix_grkey_t mach64_grkey; + +#define DECLARE_VREG(name) { #name, name, 0 } +static video_registers_t vregs[] = +{ + DECLARE_VREG(OVERLAY_SCALE_INC), + DECLARE_VREG(OVERLAY_Y_X_START), + DECLARE_VREG(OVERLAY_Y_X_END), + DECLARE_VREG(OVERLAY_SCALE_CNTL), + DECLARE_VREG(OVERLAY_EXCLUSIVE_HORZ), + DECLARE_VREG(OVERLAY_EXCLUSIVE_VERT), + DECLARE_VREG(OVERLAY_TEST), + DECLARE_VREG(SCALER_BUF_PITCH), + DECLARE_VREG(SCALER_HEIGHT_WIDTH), + DECLARE_VREG(SCALER_BUF0_OFFSET), + DECLARE_VREG(SCALER_BUF0_OFFSET_U), + DECLARE_VREG(SCALER_BUF0_OFFSET_V), + DECLARE_VREG(SCALER_BUF1_OFFSET), + DECLARE_VREG(SCALER_BUF1_OFFSET_U), + DECLARE_VREG(SCALER_BUF1_OFFSET_V), + DECLARE_VREG(SCALER_H_COEFF0), + DECLARE_VREG(SCALER_H_COEFF1), + DECLARE_VREG(SCALER_H_COEFF2), + DECLARE_VREG(SCALER_H_COEFF3), + DECLARE_VREG(SCALER_H_COEFF4), + DECLARE_VREG(SCALER_COLOUR_CNTL), + DECLARE_VREG(SCALER_THRESHOLD), + DECLARE_VREG(VIDEO_FORMAT), + DECLARE_VREG(VIDEO_CONFIG), + DECLARE_VREG(VIDEO_SYNC_TEST), + DECLARE_VREG(VIDEO_SYNC_TEST_B), + DECLARE_VREG(BUS_CNTL), + DECLARE_VREG(SRC_CNTL), + DECLARE_VREG(GUI_STAT), + DECLARE_VREG(BM_ADDR), + DECLARE_VREG(BM_DATA), + DECLARE_VREG(BM_HOSTDATA), + DECLARE_VREG(BM_GUI_TABLE_CMD), + DECLARE_VREG(BM_FRAME_BUF_OFFSET), + DECLARE_VREG(BM_SYSTEM_MEM_ADDR), + DECLARE_VREG(BM_COMMAND), + DECLARE_VREG(BM_STATUS), + DECLARE_VREG(BM_GUI_TABLE), + DECLARE_VREG(BM_SYSTEM_TABLE), + DECLARE_VREG(AGP_BASE), + DECLARE_VREG(AGP_CNTL), + DECLARE_VREG(CRTC_INT_CNTL) +}; + +/* VIDIX exports */ + +/* MMIO space*/ +#define GETREG(TYPE,PTR,OFFZ) (*((volatile TYPE*)((PTR)+(OFFZ)))) +#define SETREG(TYPE,PTR,OFFZ,VAL) (*((volatile TYPE*)((PTR)+(OFFZ))))=VAL + +#define INREG8(addr) GETREG(uint8_t,(uint32_t)mach64_mmio_base,((addr)^0x100)<<2) +#define OUTREG8(addr,val) SETREG(uint8_t,(uint32_t)mach64_mmio_base,((addr)^0x100)<<2,val) +static inline uint32_t INREG (uint32_t addr) { + uint32_t tmp = GETREG(uint32_t,(uint32_t)mach64_mmio_base,((addr)^0x100)<<2); + return le2me_32(tmp); +} +#define OUTREG(addr,val) SETREG(uint32_t,(uint32_t)mach64_mmio_base,((addr)^0x100)<<2,le2me_32(val)) + +#define OUTREGP(addr,val,mask) \ + do { \ + unsigned int _tmp = INREG(addr); \ + _tmp &= (mask); \ + _tmp |= (val); \ + OUTREG(addr, _tmp); \ + } while (0) + +static __inline__ int ATIGetMach64LCDReg(int _Index) +{ + OUTREG8(LCD_INDEX, _Index); + return INREG(LCD_DATA); +} + +static __inline__ uint32_t INPLL(uint32_t addr) +{ + uint32_t res; + uint32_t in; + + in= INREG(CLOCK_CNTL); + in &= ~((PLL_WR_EN | PLL_ADDR)); //clean some stuff + OUTREG(CLOCK_CNTL, in | (addr<<10)); + + /* read the register value */ + res = (INREG(CLOCK_CNTL)>>16)&0xFF; + return res; +} + +static __inline__ void OUTPLL(uint32_t addr,uint32_t val) +{ +//FIXME buggy but its not used + /* write addr byte */ + OUTREG8(CLOCK_CNTL + 1, (addr << 2) | PLL_WR_EN); + /* write the register value */ + OUTREG(CLOCK_CNTL + 2, val); + OUTREG8(CLOCK_CNTL + 1, (addr << 2) & ~PLL_WR_EN); +} + +#define OUTPLLP(addr,val,mask) \ + do { \ + unsigned int _tmp = INPLL(addr); \ + _tmp &= (mask); \ + _tmp |= (val); \ + OUTPLL(addr, _tmp); \ + } while (0) + +static void mach64_engine_reset( void ) +{ + /* Kill off bus mastering with extreme predjudice... */ + OUTREG(BUS_CNTL, INREG(BUS_CNTL) | BUS_MASTER_DIS); + OUTREG(CRTC_INT_CNTL,INREG(CRTC_INT_CNTL)&~(CRTC_BUSMASTER_EOL_INT|CRTC_BUSMASTER_EOL_INT_EN)); + /* Reset engine -- This is accomplished by setting bit 8 of the GEN_TEST_CNTL + register high, then low (per the documentation, it's on high to low transition + that the GUI engine gets reset...) */ + OUTREG( GEN_TEST_CNTL, INREG( GEN_TEST_CNTL ) | GEN_GUI_EN ); + OUTREG( GEN_TEST_CNTL, INREG( GEN_TEST_CNTL ) & ~GEN_GUI_EN ); +} + +static void mach64_fifo_wait(unsigned n) +{ + while ((INREG(FIFO_STAT) & 0xffff) > ((uint32_t)(0x8000 >> n))); +} + +static void mach64_wait_for_idle( void ) +{ + unsigned i; + mach64_fifo_wait(16); + for (i=0; i<2000000; i++) if((INREG(GUI_STAT) & GUI_ACTIVE) == 0) break; + if((INREG(GUI_STAT) & 1) != 0) mach64_engine_reset(); /* due card lookup */ +} + +static void mach64_wait_vsync( void ) +{ + int i; + + for(i=0; i<2000000; i++) + if( (INREG(CRTC_INT_CNTL)&CRTC_VBLANK)==0 ) break; + for(i=0; i<2000000; i++) + if( (INREG(CRTC_INT_CNTL)&CRTC_VBLANK) ) break; + +} + +static vidix_capability_t mach64_cap = +{ + "BES driver for Mach64/3DRage cards", + "Nick Kurshev and Michael Niedermayer", + TYPE_OUTPUT, + { 0, 0, 0, 0 }, + 2048, + 2048, + 4, + 4, + -1, + FLAG_UPSCALER|FLAG_DOWNSCALER, + VENDOR_ATI, + -1, + { 0, 0, 0, 0 } +}; + +static uint32_t mach64_vid_get_dbpp( void ) +{ + uint32_t dbpp,retval; + dbpp = (INREG(CRTC_GEN_CNTL)>>8)& 0x7; + switch(dbpp) + { + case 1: retval = 4; break; + case 2: retval = 8; break; + case 3: retval = 15; break; + case 4: retval = 16; break; + case 5: retval = 24; break; + default: retval=32; break; + } + return retval; +} + +static int mach64_is_dbl_scan( void ) +{ + return INREG(CRTC_GEN_CNTL) & CRTC_DBL_SCAN_EN; +} + +static int mach64_is_interlace( void ) +{ + return INREG(CRTC_GEN_CNTL) & CRTC_INTERLACE_EN; +} + +static uint32_t mach64_get_xres( void ) +{ + /* FIXME: currently we extract that from CRTC!!!*/ + uint32_t xres,h_total; + h_total = INREG(CRTC_H_TOTAL_DISP); + xres = (h_total >> 16) & 0xffff; + return (xres + 1)*8; +} + +static uint32_t mach64_get_yres( void ) +{ + /* FIXME: currently we extract that from CRTC!!!*/ + uint32_t yres,v_total; + v_total = INREG(CRTC_V_TOTAL_DISP); + yres = (v_total >> 16) & 0xffff; + return yres + 1; +} + +// returns the verical stretch factor in 16.16 +static int mach64_get_vert_stretch(void) +{ + int lcd_index; + int vert_stretching; + int ext_vert_stretch; + int ret; + int yres= mach64_get_yres(); + + if(!supports_lcd_v_stretch){ + if(__verbose>0) printf("[mach64] vertical stretching not supported\n"); + return 1<<16; + } + + lcd_index= INREG(LCD_INDEX); + + vert_stretching= ATIGetMach64LCDReg(LCD_VERT_STRETCHING); + if(!(vert_stretching&VERT_STRETCH_EN)) ret= 1<<16; + else + { + int panel_size; + + ext_vert_stretch= ATIGetMach64LCDReg(LCD_EXT_VERT_STRETCH); + panel_size= (ext_vert_stretch&VERT_PANEL_SIZE)>>11; + panel_size++; + + ret= ((yres<<16) + (panel_size>>1))/panel_size; + } + +// lcd_gen_ctrl = ATIGetMach64LCDReg(LCD_GEN_CNTL); + + OUTREG(LCD_INDEX, lcd_index); + + if(__verbose>0) printf("[mach64] vertical stretching factor= %d\n", ret); + + return ret; +} + +static void mach64_vid_make_default() +{ + mach64_fifo_wait(5); + OUTREG(SCALER_COLOUR_CNTL,0x00101000); + + besr.ckey_on=0; + besr.graphics_key_msk=0; + besr.graphics_key_clr=0; + + OUTREG(OVERLAY_GRAPHICS_KEY_MSK, besr.graphics_key_msk); + OUTREG(OVERLAY_GRAPHICS_KEY_CLR, besr.graphics_key_clr); + OUTREG(OVERLAY_KEY_CNTL,VIDEO_KEY_FN_TRUE|GRAPHIC_KEY_FN_EQ|CMP_MIX_AND); + +} + +static void mach64_vid_dump_regs( void ) +{ + size_t i; + printf("[mach64] *** Begin of DRIVER variables dump ***\n"); + printf("[mach64] mach64_mmio_base=%p\n",mach64_mmio_base); + printf("[mach64] mach64_mem_base=%p\n",mach64_mem_base); + printf("[mach64] mach64_overlay_off=%08X\n",mach64_overlay_offset); + printf("[mach64] mach64_ram_size=%08X\n",mach64_ram_size); + printf("[mach64] video mode: %ux%u@%u\n",mach64_get_xres(),mach64_get_yres(),mach64_vid_get_dbpp()); + printf("[mach64] *** Begin of OV0 registers dump ***\n"); + for(i=0;i<sizeof(vregs)/sizeof(video_registers_t);i++) + { + mach64_wait_for_idle(); + mach64_fifo_wait(2); + printf("[mach64] %s = %08X\n",vregs[i].sname,INREG(vregs[i].name)); + } + printf("[mach64] *** End of OV0 registers dump ***\n"); +} + + +unsigned int VIDIX_NAME(vixGetVersion)(void) +{ + return(VIDIX_VERSION); +} + +typedef struct ati_chip_id_s +{ + unsigned short id; + unsigned short is_agp; +}ati_chip_id_t; + +static ati_chip_id_t ati_card_ids[] = +{ + { DEVICE_ATI_215CT_MACH64_CT, 0 }, + { DEVICE_ATI_210888CX_MACH64_CX, 0 }, + { DEVICE_ATI_210888ET_MACH64_ET, 0 }, + { DEVICE_ATI_MACH64_VT, 0 }, + { DEVICE_ATI_210888GX_MACH64_GX, 0 }, + { DEVICE_ATI_264LT_MACH64_LT, 0 }, + { DEVICE_ATI_264VT_MACH64_VT, 0 }, + { DEVICE_ATI_264VT3_MACH64_VT3, 0 }, + { DEVICE_ATI_264VT4_MACH64_VT4, 0 }, + /**/ + { DEVICE_ATI_3D_RAGE_PRO, 1 }, + { DEVICE_ATI_3D_RAGE_PRO2, 1 }, + { DEVICE_ATI_3D_RAGE_PRO3, 0 }, + { DEVICE_ATI_3D_RAGE_PRO4, 0 }, + { DEVICE_ATI_RAGE_XC, 0 }, + { DEVICE_ATI_RAGE_XL_AGP, 1 }, + { DEVICE_ATI_RAGE_XC_AGP, 1 }, + { DEVICE_ATI_RAGE_XL, 0 }, + { DEVICE_ATI_3D_RAGE_PRO5, 0 }, + { DEVICE_ATI_3D_RAGE_PRO6, 0 }, + { DEVICE_ATI_RAGE_XL2, 0 }, + { DEVICE_ATI_RAGE_XC2, 0 }, + { DEVICE_ATI_3D_RAGE_I_II, 0 }, + { DEVICE_ATI_3D_RAGE_II, 0 }, + { DEVICE_ATI_3D_RAGE_IIC, 1 }, + { DEVICE_ATI_3D_RAGE_IIC2, 0 }, + { DEVICE_ATI_3D_RAGE_IIC3, 0 }, + { DEVICE_ATI_3D_RAGE_IIC4, 1 }, + { DEVICE_ATI_3D_RAGE_LT, 1 }, + { DEVICE_ATI_3D_RAGE_LT2, 1 }, + { DEVICE_ATI_3D_RAGE_LT_G, 0 }, + { DEVICE_ATI_3D_RAGE_LT3, 0 }, + { DEVICE_ATI_RAGE_MOBILITY_P_M, 1 }, + { DEVICE_ATI_RAGE_MOBILITY_L, 1 }, + { DEVICE_ATI_3D_RAGE_LT4, 0 }, + { DEVICE_ATI_3D_RAGE_LT5, 0 }, + { DEVICE_ATI_RAGE_MOBILITY_P_M2, 0 }, + { DEVICE_ATI_RAGE_MOBILITY_L2, 0 } +}; + +static int is_agp; + +static int find_chip(unsigned chip_id) +{ + unsigned i; + for(i = 0;i < sizeof(ati_card_ids)/sizeof(ati_chip_id_t);i++) + { + if(chip_id == ati_card_ids[i].id) return i; + } + return -1; +} + +int VIDIX_NAME(vixProbe)(int verbose,int force) +{ + pciinfo_t lst[MAX_PCI_DEVICES]; + unsigned i,num_pci; + int err; + __verbose = verbose; + err = pci_scan(lst,&num_pci); + if(err) + { + printf("[mach64] Error occured during pci scan: %s\n",strerror(err)); + return err; + } + else + { + err = ENXIO; + for(i=0;i<num_pci;i++) + { + if(lst[i].vendor == VENDOR_ATI) + { + int idx; + const char *dname; + idx = find_chip(lst[i].device); + if(idx == -1 && force == PROBE_NORMAL) continue; + dname = pci_device_name(VENDOR_ATI,lst[i].device); + dname = dname ? dname : "Unknown chip"; + printf("[mach64] Found chip: %s\n",dname); + if(force > PROBE_NORMAL) + { + printf("[mach64] Driver was forced. Was found %sknown chip\n",idx == -1 ? "un" : ""); + if(idx == -1) + printf("[mach64] Assuming it as Mach64\n"); + } + if(idx != -1) is_agp = ati_card_ids[idx].is_agp; + mach64_cap.device_id = lst[i].device; + err = 0; + memcpy(&pci_info,&lst[i],sizeof(pciinfo_t)); + probed=1; + break; + } + } + } + if(err && verbose) printf("[mach64] Can't find chip\n"); + return err; +} + +static void reset_regs( void ) +{ + size_t i; + for(i=0;i<sizeof(vregs)/sizeof(video_registers_t);i++) + { + mach64_fifo_wait(2); + OUTREG(vregs[i].name,0); + } +} + +typedef struct saved_regs_s +{ + uint32_t overlay_video_key_clr; + uint32_t overlay_video_key_msk; + uint32_t overlay_graphics_key_clr; + uint32_t overlay_graphics_key_msk; + uint32_t overlay_key_cntl; + uint32_t bus_cntl; +}saved_regs_t; +static saved_regs_t savreg; + +static void save_regs( void ) +{ + mach64_fifo_wait(6); + savreg.overlay_video_key_clr = INREG(OVERLAY_VIDEO_KEY_CLR); + savreg.overlay_video_key_msk = INREG(OVERLAY_VIDEO_KEY_MSK); + savreg.overlay_graphics_key_clr = INREG(OVERLAY_GRAPHICS_KEY_CLR); + savreg.overlay_graphics_key_msk = INREG(OVERLAY_GRAPHICS_KEY_MSK); + savreg.overlay_key_cntl = INREG(OVERLAY_KEY_CNTL); + savreg.bus_cntl = INREG(BUS_CNTL); +} + +static void restore_regs( void ) +{ + mach64_fifo_wait(6); + OUTREG(OVERLAY_VIDEO_KEY_CLR,savreg.overlay_video_key_clr); + OUTREG(OVERLAY_VIDEO_KEY_MSK,savreg.overlay_video_key_msk); + OUTREG(OVERLAY_GRAPHICS_KEY_CLR,savreg.overlay_graphics_key_clr); + OUTREG(OVERLAY_GRAPHICS_KEY_MSK,savreg.overlay_graphics_key_msk); + OUTREG(OVERLAY_KEY_CNTL,savreg.overlay_key_cntl); + OUTREG(BUS_CNTL,savreg.bus_cntl|BUS_MASTER_DIS); +} + +static int forced_irq=INT_MAX; + +#ifdef MACH64_ENABLE_BM +static int can_use_irq=0; +static int irq_installed=0; + +static void init_irq(void) +{ + irq_installed=1; + if(forced_irq != INT_MAX) pci_info.irq=forced_irq; + if(hwirq_install(pci_info.bus,pci_info.card,pci_info.func, + 2,CRTC_INT_CNTL,CRTC_BUSMASTER_EOL_INT) == 0) + { + can_use_irq=1; + if(__verbose) printf("[mach64] Will use %u irq line\n",pci_info.irq); + } + else + if(__verbose) printf("[mach64] Can't initialize irq handling: %s\n" + "[mach64]irq_param: line=%u pin=%u gnt=%u lat=%u\n" + ,strerror(errno) + ,pci_info.irq,pci_info.ipin,pci_info.gnt,pci_info.lat); +} +#endif + +int VIDIX_NAME(vixInit)(const char *args) +{ + int err; +#ifdef MACH64_ENABLE_BM + unsigned i; +#endif + if(!probed) + { + printf("[mach64] Driver was not probed but is being initializing\n"); + return EINTR; + } + if(__verbose>0) printf("[mach64] version %d args='%s'\n", VIDIX_VERSION,args); + if(args) + if(strncmp(args,"irq=",4) == 0) + { + forced_irq=atoi(&args[4]); + if(__verbose>0) printf("[mach64] forcing IRQ to %u\n",forced_irq); + } + + if((mach64_mmio_base = map_phys_mem(pci_info.base2,0x4000))==(void *)-1) return ENOMEM; + mach64_wait_for_idle(); + mach64_ram_size = INREG(MEM_CNTL) & CTL_MEM_SIZEB; + if (mach64_ram_size < 8) mach64_ram_size = (mach64_ram_size + 1) * 512; + else if (mach64_ram_size < 12) mach64_ram_size = (mach64_ram_size - 3) * 1024; + else mach64_ram_size = (mach64_ram_size - 7) * 2048; + mach64_ram_size *= 0x400; /* KB -> bytes */ + if((mach64_mem_base = map_phys_mem(pci_info.base0,mach64_ram_size))==(void *)-1) return ENOMEM; + memset(&besr,0,sizeof(bes_registers_t)); + printf("[mach64] Video memory = %uMb\n",mach64_ram_size/0x100000); + err = mtrr_set_type(pci_info.base0,mach64_ram_size,MTRR_TYPE_WRCOMB); + if(!err) printf("[mach64] Set write-combining type of video memory\n"); + + save_regs(); + /* check if planar formats are supported */ + supports_planar=0; + mach64_wait_for_idle(); + mach64_fifo_wait(2); + if(INREG(SCALER_BUF0_OFFSET_U)) supports_planar=1; + else + { + OUTREG(SCALER_BUF0_OFFSET_U, -1); + + mach64_wait_vsync(); + mach64_wait_for_idle(); + mach64_fifo_wait(2); + + if(INREG(SCALER_BUF0_OFFSET_U)) supports_planar=1; + } + printf("[mach64] Planar YUV formats are %s supported\n",supports_planar?"":"not"); + supports_colour_adj=0; + OUTREG(SCALER_COLOUR_CNTL,-1); + if(INREG(SCALER_COLOUR_CNTL)) supports_colour_adj=1; + supports_idct=0; + OUTREG(IDCT_CONTROL,-1); + if(INREG(IDCT_CONTROL)) supports_idct=1; + OUTREG(IDCT_CONTROL,0); + printf("[mach64] IDCT is %s supported\n",supports_idct?"":"not"); + supports_subpic=0; + OUTREG(SUBPIC_CNTL,-1); + if(INREG(SUBPIC_CNTL)) supports_subpic=1; + OUTREG(SUBPIC_CNTL,0); + printf("[mach64] subpictures are %s supported\n",supports_subpic?"":"not"); + if( mach64_cap.device_id==DEVICE_ATI_RAGE_MOBILITY_P_M + || mach64_cap.device_id==DEVICE_ATI_RAGE_MOBILITY_P_M2 + || mach64_cap.device_id==DEVICE_ATI_RAGE_MOBILITY_L + || mach64_cap.device_id==DEVICE_ATI_RAGE_MOBILITY_L2) + supports_lcd_v_stretch=1; + else + supports_lcd_v_stretch=0; + + reset_regs(); + mach64_vid_make_default(); + if(__verbose > VERBOSE_LEVEL) mach64_vid_dump_regs(); +#ifdef MACH64_ENABLE_BM + if(!(INREG(BUS_CNTL) & BUS_MASTER_DIS)) + OUTREG(BUS_CNTL,INREG(BUS_CNTL)|BUS_MSTR_RESET); + if(bm_open() == 0) + { + mach64_cap.flags |= FLAG_DMA | FLAG_EQ_DMA; + if((dma_phys_addrs = malloc(mach64_ram_size*sizeof(unsigned long)/4096)) == 0) + { + out_mem: + printf("[mach64] Can't allocate temporary buffer for DMA\n"); + mach64_cap.flags &= ~FLAG_DMA & ~FLAG_EQ_DMA; + return 0; + } + /* + WARNING: We MUST have continigous descriptors!!! + But: (720*720*2(YUV422)*16(sizeof(bm_descriptor)))/4096=4050 + Thus one 4K page is far enough to describe max movie size. + */ + for(i=0;i<64;i++) + if((mach64_dma_desc_base[i] = memalign(4096,mach64_ram_size*sizeof(bm_list_descriptor)/4096)) == 0) + goto out_mem; +#if 0 + if(!is_agp) + { + long tst; + if(pci_config_read(pci_info.bus,pci_info.card,pci_info.func,4,4,&pci_command) == 0) + pci_config_write(pci_info.bus,pci_info.card,pci_info.func,4,4,pci_command|0x14); + pci_config_read(pci_info.bus,pci_info.card,pci_info.func,4,4,&tst); + } +#endif + } + else + if(__verbose) printf("[mach64] Can't initialize busmastering: %s\n",strerror(errno)); +#endif + return 0; +} + +void VIDIX_NAME(vixDestroy)(void) +{ +#ifdef MACH64_ENABLE_BM + unsigned i; +#endif + restore_regs(); +#ifdef MACH64_ENABLE_BM + mach64_engine_reset(); +#endif + unmap_phys_mem(mach64_mem_base,mach64_ram_size); + unmap_phys_mem(mach64_mmio_base,0x4000); +#ifdef MACH64_ENABLE_BM + bm_close(); + if(can_use_irq && irq_installed) hwirq_uninstall(pci_info.bus,pci_info.card,pci_info.func); + if(dma_phys_addrs) free(dma_phys_addrs); + for(i=0;i<64;i++) + { + if(mach64_dma_desc_base[i]) free(mach64_dma_desc_base[i]); + } +#endif +} + +int VIDIX_NAME(vixGetCapability)(vidix_capability_t *to) +{ + memcpy(to, &mach64_cap, sizeof(vidix_capability_t)); + return 0; +} + +static unsigned mach64_query_pitch(unsigned fourcc,const vidix_yuv_t *spitch) +{ + unsigned pitch,spy,spv,spu; + spy = spv = spu = 0; + switch(spitch->y) + { + case 16: + case 32: + case 64: + case 128: + case 256: spy = spitch->y; break; + default: break; + } + switch(spitch->u) + { + case 16: + case 32: + case 64: + case 128: + case 256: spu = spitch->u; break; + default: break; + } + switch(spitch->v) + { + case 16: + case 32: + case 64: + case 128: + case 256: spv = spitch->v; break; + default: break; + } + switch(fourcc) + { + /* 4:2:0 */ + case IMGFMT_IYUV: + case IMGFMT_YV12: + case IMGFMT_I420: + if(spy > 16 && spu == spy/2 && spv == spy/2) pitch = spy; + else pitch = 32; + break; + case IMGFMT_YVU9: + if(spy > 32 && spu == spy/4 && spv == spy/4) pitch = spy; + else pitch = 64; + break; + default: + if(spy >= 16) pitch = spy; + else pitch = 16; + break; + } + return pitch; +} + +static void mach64_compute_framesize(vidix_playback_t *info) +{ + unsigned pitch,awidth; + pitch = mach64_query_pitch(info->fourcc,&info->src.pitch); + switch(info->fourcc) + { + case IMGFMT_I420: + case IMGFMT_YV12: + case IMGFMT_IYUV: + awidth = (info->src.w + (pitch-1)) & ~(pitch-1); + info->frame_size = awidth*(info->src.h+info->src.h/2); + break; + case IMGFMT_YVU9: + awidth = (info->src.w + (pitch-1)) & ~(pitch-1); + info->frame_size = awidth*(info->src.h+info->src.h/8); + break; +// case IMGFMT_RGB32: + case IMGFMT_BGR32: + awidth = (info->src.w*4 + (pitch-1)) & ~(pitch-1); + info->frame_size = (awidth*info->src.h); + break; + /* YUY2 YVYU, RGB15, RGB16 */ + default: + awidth = (info->src.w*2 + (pitch-1)) & ~(pitch-1); + info->frame_size = (awidth*info->src.h); + break; + } + info->frame_size+=256; // so we have some space for alignment & such + info->frame_size&=~16; +} + +static void mach64_vid_stop_video( void ) +{ + mach64_fifo_wait(14); + OUTREG(OVERLAY_SCALE_CNTL, 0x80000000); + OUTREG(OVERLAY_EXCLUSIVE_HORZ, 0); + OUTREG(OVERLAY_EXCLUSIVE_VERT, 0); + OUTREG(SCALER_H_COEFF0, 0x00002000); + OUTREG(SCALER_H_COEFF1, 0x0D06200D); + OUTREG(SCALER_H_COEFF2, 0x0D0A1C0D); + OUTREG(SCALER_H_COEFF3, 0x0C0E1A0C); + OUTREG(SCALER_H_COEFF4, 0x0C14140C); + OUTREG(VIDEO_FORMAT, 0xB000B); + OUTREG(OVERLAY_TEST, 0x0); +} + +static void mach64_vid_display_video( void ) +{ + uint32_t vf,sc,width; + mach64_fifo_wait(14); + + OUTREG(OVERLAY_Y_X_START, besr.y_x_start); + OUTREG(OVERLAY_Y_X_END, besr.y_x_end); + OUTREG(OVERLAY_SCALE_INC, besr.scale_inc); + OUTREG(SCALER_BUF_PITCH, besr.vid_buf_pitch); + OUTREG(SCALER_HEIGHT_WIDTH, besr.height_width); + OUTREG(SCALER_BUF0_OFFSET, mach64_buffer_base[0][0]); + OUTREG(SCALER_BUF0_OFFSET_U, mach64_buffer_base[0][1]); + OUTREG(SCALER_BUF0_OFFSET_V, mach64_buffer_base[0][2]); + OUTREG(SCALER_BUF1_OFFSET, mach64_buffer_base[0][0]); + OUTREG(SCALER_BUF1_OFFSET_U, mach64_buffer_base[0][1]); + OUTREG(SCALER_BUF1_OFFSET_V, mach64_buffer_base[0][2]); + mach64_wait_vsync(); + width = (besr.height_width >> 16 & 0x03FF); + sc = SCALE_EN | OVERLAY_EN | + SCALE_BANDWIDTH | /* reset bandwidth status */ + SCALE_PIX_EXPAND | /* dynamic range correct */ + SCALE_Y2R_TEMP; /* use the equal temparature for every component of RGB */ + /* Force clocks of scaler. */ + if(width > 360 && !supports_planar && !mach64_is_interlace()) + sc |= SCALE_CLK_FORCE_ON; + /* Do we need that? And how we can improve the quality of 3dRageII scaler ? + 3dRageII+ (non pro) is really crapped HW :( + ^^^^^^^^^^^^^^^^^^^ + !!SCALER_WIDTH <= 360 provides full scaling functionality !!!!!!!!!!!!! + !!360 < SCALER_WIDTH <= 720 provides scaling with vertical replication (crap) + !!SCALER_WIDTH > 720 is illegal. (no comments) + + As for me - I would prefer to limit movie's width with 360 but it provides only + half of picture but with perfect quality. (NK) */ + mach64_fifo_wait(10); + OUTREG(OVERLAY_SCALE_CNTL, sc); + mach64_wait_for_idle(); + + switch(besr.fourcc) + { + /* BGR formats */ + case IMGFMT_BGR15: vf = SCALER_IN_RGB15; break; + case IMGFMT_BGR16: vf = SCALER_IN_RGB16; break; + case IMGFMT_BGR32: vf = SCALER_IN_RGB32; break; + /* 4:2:0 */ + case IMGFMT_IYUV: + case IMGFMT_I420: + case IMGFMT_YV12: vf = SCALER_IN_YUV12; break; + /* 4:1:0 */ + case IMGFMT_YVU9: vf = SCALER_IN_YUV9; break; + /* 4:2:2 */ + case IMGFMT_YVYU: + case IMGFMT_UYVY: vf = SCALER_IN_YVYU422; break; + case IMGFMT_YUY2: + default: vf = SCALER_IN_VYUY422; break; + } + OUTREG(VIDEO_FORMAT,vf); + if(__verbose > VERBOSE_LEVEL) mach64_vid_dump_regs(); +} + +/* Goal of this function: hide RGB background and provide black screen around movie. + Useful in '-vo fbdev:vidix -fs -zoom' mode. + Reverse effect to colorkey */ +static void mach64_vid_exclusive( void ) +{ + unsigned screenw,screenh; + screenw = mach64_get_xres(); + screenh = mach64_get_yres(); + OUTREG(OVERLAY_EXCLUSIVE_VERT,(((screenh-1)<<16)&EXCLUSIVE_VERT_END)); + OUTREG(OVERLAY_EXCLUSIVE_HORZ,(((screenw/8+1)<<8)&EXCLUSIVE_HORZ_END)|EXCLUSIVE_EN); +} + +static void mach64_vid_non_exclusive( void ) +{ + OUTREG(OVERLAY_EXCLUSIVE_HORZ,0); +} + +static int mach64_vid_init_video( vidix_playback_t *config ) +{ + uint32_t src_w,src_h,dest_w,dest_h,pitch,h_inc,v_inc,left,leftUV,top,ecp,y_pos; + int is_420,best_pitch,mpitch; + int src_offset_y, src_offset_u, src_offset_v; + unsigned int i; + + mach64_vid_stop_video(); +/* warning, if left or top are != 0 this will fail, as the framesize is too small then */ + left = config->src.x; + top = config->src.y; + src_h = config->src.h; + src_w = config->src.w; + is_420 = 0; + if(config->fourcc == IMGFMT_YV12 || + config->fourcc == IMGFMT_I420 || + config->fourcc == IMGFMT_IYUV) is_420 = 1; + best_pitch = mach64_query_pitch(config->fourcc,&config->src.pitch); + mpitch = best_pitch-1; + switch(config->fourcc) + { + case IMGFMT_YVU9: + /* 4:2:0 */ + case IMGFMT_IYUV: + case IMGFMT_YV12: + case IMGFMT_I420: pitch = (src_w + mpitch) & ~mpitch; + config->dest.pitch.y = + config->dest.pitch.u = + config->dest.pitch.v = best_pitch; + besr.vid_buf_pitch= pitch; + break; + /* RGB 4:4:4:4 */ + case IMGFMT_RGB32: + case IMGFMT_BGR32: pitch = (src_w*4 + mpitch) & ~mpitch; + config->dest.pitch.y = + config->dest.pitch.u = + config->dest.pitch.v = best_pitch; + besr.vid_buf_pitch= pitch>>2; + break; + /* 4:2:2 */ + default: /* RGB15, RGB16, YVYU, UYVY, YUY2 */ + pitch = ((src_w*2) + mpitch) & ~mpitch; + config->dest.pitch.y = + config->dest.pitch.u = + config->dest.pitch.v = best_pitch; + besr.vid_buf_pitch= pitch>>1; + break; + } + dest_w = config->dest.w; + dest_h = config->dest.h; + besr.fourcc = config->fourcc; + ecp = (INPLL(PLL_VCLK_CNTL) & PLL_ECP_DIV) >> 4; +#if 0 +{ +int i; +for(i=0; i<32; i++){ + printf("%X ", INPLL(i)); +} +} +#endif + if(__verbose>0) printf("[mach64] ecp: %d\n", ecp); + v_inc = src_h * mach64_get_vert_stretch(); + + if(mach64_is_interlace()) v_inc<<=1; + if(mach64_is_dbl_scan() ) v_inc>>=1; + v_inc/= dest_h; + v_inc>>=4; // convert 16.16 -> 4.12 + + h_inc = (src_w << (12+ecp)) / dest_w; + /* keep everything in 4.12 */ + config->offsets[0] = 0; + for(i=1; i<config->num_frames; i++) + config->offsets[i] = config->offsets[i-1] + config->frame_size; + + /*FIXME the left / top stuff is broken (= zoom a src rectangle from a larger one) + 1. the framesize isnt known as the outer src rectangle dimensions arent known + 2. the mach64 needs aligned addresses so it cant work anyway + -> so we could shift the outer buffer to compensate that but that would mean + alignment problems for the code which writes into it + */ + + if(is_420) + { + config->offset.y= 0; + config->offset.u= (pitch*src_h + 15)&~15; + config->offset.v= (config->offset.u + (pitch*src_h>>2) + 15)&~15; + + src_offset_y= config->offset.y + top*pitch + left; + src_offset_u= config->offset.u + (top*pitch>>2) + (left>>1); + src_offset_v= config->offset.v + (top*pitch>>2) + (left>>1); + + if(besr.fourcc == IMGFMT_I420 || besr.fourcc == IMGFMT_IYUV) + { + uint32_t tmp; + tmp = config->offset.u; + config->offset.u = config->offset.v; + config->offset.v = tmp; + src_offset_u=config->offset.u; + src_offset_v=config->offset.v; + } + } + else if(besr.fourcc == IMGFMT_YVU9) + { + config->offset.y= 0; + config->offset.u= (pitch*src_h + 15)&~15; + config->offset.v= (config->offset.u + (pitch*src_h>>4) + 15)&~15; + + src_offset_y= config->offset.y + top*pitch + left; + src_offset_u= config->offset.u + (top*pitch>>4) + (left>>1); + src_offset_v= config->offset.v + (top*pitch>>4) + (left>>1); + } + else if(besr.fourcc == IMGFMT_BGR32) + { + config->offset.y = config->offset.u = config->offset.v = 0; + src_offset_y= src_offset_u= src_offset_v= top*pitch + (left << 2); + } + else + { + config->offset.y = config->offset.u = config->offset.v = 0; + src_offset_y= src_offset_u= src_offset_v= top*pitch + (left << 1); + } + + num_mach64_buffers= config->num_frames; + for(i=0; i<config->num_frames; i++) + { + mach64_buffer_base[i][0]= (mach64_overlay_offset + config->offsets[i] + src_offset_y)&~15; + mach64_buffer_base[i][1]= (mach64_overlay_offset + config->offsets[i] + src_offset_u)&~15; + mach64_buffer_base[i][2]= (mach64_overlay_offset + config->offsets[i] + src_offset_v)&~15; + } + + leftUV = (left >> 17) & 15; + left = (left >> 16) & 15; + besr.scale_inc = ( h_inc << 16 ) | v_inc; + y_pos = config->dest.y; + if(mach64_is_dbl_scan()) y_pos*=2; + else + if(mach64_is_interlace()) y_pos/=2; + besr.y_x_start = y_pos | (config->dest.x << 16); + y_pos =config->dest.y + dest_h; + if(mach64_is_dbl_scan()) y_pos*=2; + else + if(mach64_is_interlace()) y_pos/=2; + besr.y_x_end = y_pos | ((config->dest.x + dest_w) << 16); + besr.height_width = ((src_w - left)<<16) | (src_h - top); + return 0; +} + +static int is_supported_fourcc(uint32_t fourcc) +{ + switch(fourcc) + { + case IMGFMT_YV12: + case IMGFMT_I420: + case IMGFMT_YVU9: + case IMGFMT_IYUV: + return supports_planar; + case IMGFMT_YUY2: + case IMGFMT_UYVY: + case IMGFMT_BGR15: + case IMGFMT_BGR16: + case IMGFMT_BGR32: + return 1; + default: + return 0; + } +} + +int VIDIX_NAME(vixQueryFourcc)(vidix_fourcc_t *to) +{ + if(is_supported_fourcc(to->fourcc)) + { + to->depth = VID_DEPTH_1BPP | VID_DEPTH_2BPP | + VID_DEPTH_4BPP | VID_DEPTH_8BPP | + VID_DEPTH_12BPP| VID_DEPTH_15BPP| + VID_DEPTH_16BPP| VID_DEPTH_24BPP| + VID_DEPTH_32BPP; + to->flags = VID_CAP_EXPAND | VID_CAP_SHRINK | VID_CAP_COLORKEY; + return 0; + } + else to->depth = to->flags = 0; + return ENOSYS; +} + +int VIDIX_NAME(vixConfigPlayback)(vidix_playback_t *info) +{ + unsigned rgb_size,nfr; + uint32_t mach64_video_size; + if(!is_supported_fourcc(info->fourcc)) return ENOSYS; + if(info->src.h > 720 || info->src.w > 720) + { + printf("[mach64] Can't apply width or height > 720\n"); + return EINVAL; + } + if(info->num_frames>VID_PLAY_MAXFRAMES) info->num_frames=VID_PLAY_MAXFRAMES; + + mach64_compute_framesize(info); + rgb_size = mach64_get_xres()*mach64_get_yres()*((mach64_vid_get_dbpp()+7)/8); + nfr = info->num_frames; + mach64_video_size = mach64_ram_size; + for(;nfr>0;nfr--) + { + mach64_overlay_offset = mach64_video_size - info->frame_size*nfr; + mach64_overlay_offset &= 0xffff0000; + if(mach64_overlay_offset >= (int)rgb_size ) break; + } + if(nfr <= 3) + { + nfr = info->num_frames; + for(;nfr>0;nfr--) + { + mach64_overlay_offset = mach64_video_size - info->frame_size*nfr; + mach64_overlay_offset &= 0xffff0000; + if(mach64_overlay_offset>=0) break; + } + } + if(nfr <= 0) return EINVAL; + info->num_frames=nfr; + num_mach64_buffers = info->num_frames; + info->dga_addr = (char *)mach64_mem_base + mach64_overlay_offset; + mach64_vid_init_video(info); + return 0; +} + +int VIDIX_NAME(vixPlaybackOn)(void) +{ + int err; + unsigned dw,dh; + dw = (besr.y_x_end >> 16) - (besr.y_x_start >> 16); + dh = (besr.y_x_end & 0xFFFF) - (besr.y_x_start & 0xFFFF); + if(dw == mach64_get_xres() || dh == mach64_get_yres()) mach64_vid_exclusive(); + else mach64_vid_non_exclusive(); + mach64_vid_display_video(); + err = INREG(SCALER_BUF_PITCH) == besr.vid_buf_pitch ? 0 : EINTR; + if(err) + { + printf("[mach64] *** Internal fatal error ***: Detected pitch corruption\n" + "[mach64] Try decrease number of buffers\n"); + } + return err; +} + +int VIDIX_NAME(vixPlaybackOff)(void) +{ + mach64_vid_stop_video(); + return 0; +} + +int VIDIX_NAME(vixPlaybackFrameSelect)(unsigned int frame) +{ + uint32_t off[6]; + int i; + int last_frame= (frame-1+num_mach64_buffers) % num_mach64_buffers; + /* + buf3-5 always should point onto second buffer for better + deinterlacing and TV-in + */ + if(num_mach64_buffers==1) return 0; + for(i=0; i<3; i++) + { + off[i] = mach64_buffer_base[frame][i]; + off[i+3]= mach64_buffer_base[last_frame][i]; + } + if(__verbose > VERBOSE_LEVEL) printf("mach64_vid: flip_page = %u\n",frame); + +#if 0 // delay routine so the individual frames can be ssen better +{ +volatile int i=0; +for(i=0; i<10000000; i++); +} +#endif + + mach64_wait_for_idle(); + mach64_fifo_wait(7); + + OUTREG(SCALER_BUF0_OFFSET, off[0]); + OUTREG(SCALER_BUF0_OFFSET_U, off[1]); + OUTREG(SCALER_BUF0_OFFSET_V, off[2]); + OUTREG(SCALER_BUF1_OFFSET, off[3]); + OUTREG(SCALER_BUF1_OFFSET_U, off[4]); + OUTREG(SCALER_BUF1_OFFSET_V, off[5]); + if(num_mach64_buffers==2) mach64_wait_vsync(); //only wait for vsync if we do double buffering + + if(__verbose > VERBOSE_LEVEL) mach64_vid_dump_regs(); + return 0; +} + +vidix_video_eq_t equal = +{ + VEQ_CAP_BRIGHTNESS | VEQ_CAP_SATURATION + , + 0, 0, 0, 0, 0, 0, 0, 0 }; + +int VIDIX_NAME(vixPlaybackGetEq)( vidix_video_eq_t * eq) +{ + memcpy(eq,&equal,sizeof(vidix_video_eq_t)); + if(!supports_colour_adj) eq->cap = VEQ_CAP_BRIGHTNESS; + return 0; +} + +int VIDIX_NAME(vixPlaybackSetEq)( const vidix_video_eq_t * eq) +{ + int br,sat; + if(eq->cap & VEQ_CAP_BRIGHTNESS) equal.brightness = eq->brightness; + if(eq->cap & VEQ_CAP_CONTRAST) equal.contrast = eq->contrast; + if(eq->cap & VEQ_CAP_SATURATION) equal.saturation = eq->saturation; + if(eq->cap & VEQ_CAP_HUE) equal.hue = eq->hue; + if(eq->cap & VEQ_CAP_RGB_INTENSITY) + { + equal.red_intensity = eq->red_intensity; + equal.green_intensity = eq->green_intensity; + equal.blue_intensity = eq->blue_intensity; + } + if(supports_colour_adj) + { + equal.flags = eq->flags; + br = equal.brightness * 64 / 1000; + if(br < -64) br = -64; if(br > 63) br = 63; + sat = (equal.saturation + 1000) * 16 / 1000; + if(sat < 0) sat = 0; if(sat > 31) sat = 31; + OUTREG(SCALER_COLOUR_CNTL, (br & 0x7f) | (sat << 8) | (sat << 16)); + } + else + { + unsigned gamma; + br = equal.brightness * 3 / 1000; + if(br < 0) br = 0; + switch(br) + { + default:gamma = SCALE_GAMMA_SEL_BRIGHT; break; + case 1: gamma = SCALE_GAMMA_SEL_G14; break; + case 2: gamma = SCALE_GAMMA_SEL_G18; break; + case 3: gamma = SCALE_GAMMA_SEL_G22; break; + } + OUTREG(OVERLAY_SCALE_CNTL,(INREG(OVERLAY_SCALE_CNTL) & ~SCALE_GAMMA_SEL_MSK) | gamma); + } + return 0; +} + +int VIDIX_NAME(vixGetGrKeys)(vidix_grkey_t *grkey) +{ + memcpy(grkey, &mach64_grkey, sizeof(vidix_grkey_t)); + return(0); +} + +int VIDIX_NAME(vixSetGrKeys)(const vidix_grkey_t *grkey) +{ + memcpy(&mach64_grkey, grkey, sizeof(vidix_grkey_t)); + + if(mach64_grkey.ckey.op == CKEY_TRUE) + { + besr.ckey_on=1; + + switch(mach64_vid_get_dbpp()) + { + case 15: + besr.graphics_key_msk=0x7FFF; + besr.graphics_key_clr= + ((mach64_grkey.ckey.blue &0xF8)>>3) + | ((mach64_grkey.ckey.green&0xF8)<<2) + | ((mach64_grkey.ckey.red &0xF8)<<7); + break; + case 16: + besr.graphics_key_msk=0xFFFF; + besr.graphics_key_clr= + ((mach64_grkey.ckey.blue &0xF8)>>3) + | ((mach64_grkey.ckey.green&0xFC)<<3) + | ((mach64_grkey.ckey.red &0xF8)<<8); + break; + case 24: + besr.graphics_key_msk=0xFFFFFF; + besr.graphics_key_clr= + ((mach64_grkey.ckey.blue &0xFF)) + | ((mach64_grkey.ckey.green&0xFF)<<8) + | ((mach64_grkey.ckey.red &0xFF)<<16); + break; + case 32: + besr.graphics_key_msk=0xFFFFFF; + besr.graphics_key_clr= + ((mach64_grkey.ckey.blue &0xFF)) + | ((mach64_grkey.ckey.green&0xFF)<<8) + | ((mach64_grkey.ckey.red &0xFF)<<16); + break; + default: + besr.ckey_on=0; + besr.graphics_key_msk=0; + besr.graphics_key_clr=0; + } + } + else + { + besr.ckey_on=0; + besr.graphics_key_msk=0; + besr.graphics_key_clr=0; + } + + mach64_fifo_wait(4); + OUTREG(OVERLAY_GRAPHICS_KEY_MSK, besr.graphics_key_msk); + OUTREG(OVERLAY_GRAPHICS_KEY_CLR, besr.graphics_key_clr); +// OUTREG(OVERLAY_VIDEO_KEY_MSK, 0); +// OUTREG(OVERLAY_VIDEO_KEY_CLR, 0); + if(besr.ckey_on) + OUTREG(OVERLAY_KEY_CNTL,VIDEO_KEY_FN_TRUE|GRAPHIC_KEY_FN_EQ|CMP_MIX_AND); + else + OUTREG(OVERLAY_KEY_CNTL,VIDEO_KEY_FN_TRUE|GRAPHIC_KEY_FN_TRUE|CMP_MIX_AND); + + return(0); +} + +#ifdef MACH64_ENABLE_BM +static int mach64_setup_frame( vidix_dma_t * dmai ) +{ + if(mach64_overlay_offset + dmai->dest_offset + dmai->size > mach64_ram_size) return E2BIG; + if(dmai->idx > VID_PLAY_MAXFRAMES-1) dmai->idx=0; + if(!(dmai->internal[dmai->idx] && (dmai->flags & BM_DMA_FIXED_BUFFS))) + { + bm_list_descriptor * list = (bm_list_descriptor *)mach64_dma_desc_base[dmai->idx]; + unsigned long dest_ptr; + unsigned i,n,count; + int retval; + n = dmai->size / 4096; + if(dmai->size % 4096) n++; + if((retval = VIRT_TO_CARD(dmai->src,dmai->size,dma_phys_addrs)) != 0) return retval; + dmai->internal[dmai->idx] = mach64_dma_desc_base[dmai->idx]; + dest_ptr = dmai->dest_offset; + count = dmai->size; +#if 0 +printf("MACH64_DMA_REQUEST va=%X size=%X\n",dmai->src,dmai->size); +#endif + for(i=0;i<n;i++) + { + list[i].framebuf_offset = mach64_overlay_offset + dest_ptr; /* offset within of video memory */ + list[i].sys_addr = dma_phys_addrs[i]; + list[i].command = (count > 4096 ? 4096 : (count | DMA_GUI_COMMAND__EOL)); + list[i].reserved = 0; +#if 0 +printf("MACH64_DMA_TABLE[%i] fboff=%X pa=%X cmd=%X rsrvd=%X\n",i,list[i].framebuf_offset,list[i].sys_addr,list[i].command,list[i].reserved); +#endif + dest_ptr += 4096; + count -= 4096; + } + cpu_flush(list,4096); + } + return 0; +} + +static int mach64_transfer_frame( unsigned long ba_dma_desc,int sync_mode ) +{ + uint32_t crtc_int; + mach64_wait_for_idle(); + mach64_fifo_wait(4); + OUTREG(BUS_CNTL,(INREG(BUS_CNTL)|BUS_EXT_REG_EN)&(~BUS_MASTER_DIS)); + crtc_int = INREG(CRTC_INT_CNTL); + if(sync_mode && can_use_irq) OUTREG(CRTC_INT_CNTL,crtc_int|CRTC_BUSMASTER_EOL_INT|CRTC_BUSMASTER_EOL_INT_EN); + else OUTREG(CRTC_INT_CNTL,crtc_int|CRTC_BUSMASTER_EOL_INT); + OUTREG(BM_SYSTEM_TABLE,ba_dma_desc|SYSTEM_TRIGGER_SYSTEM_TO_VIDEO); + if(__verbose > VERBOSE_LEVEL) mach64_vid_dump_regs(); +#if 0 + mach64_fifo_wait(4); + mach64_fifo_wait(16); + printf("MACH64_DMA_DBG: bm_fb_off=%08X bm_sysmem_addr=%08X bm_cmd=%08X bm_status=%08X bm_agp_base=%08X bm_agp_cntl=%08X\n", + INREG(BM_FRAME_BUF_OFFSET), + INREG(BM_SYSTEM_MEM_ADDR), + INREG(BM_COMMAND), + INREG(BM_STATUS), + INREG(AGP_BASE), + INREG(AGP_CNTL)); +#endif + return 0; +} + +int VIDIX_NAME(vixQueryDMAStatus)( void ) +{ + int bm_off; + unsigned crtc_int_cntl; + mach64_wait_for_idle(); + mach64_fifo_wait(2); + crtc_int_cntl = INREG(CRTC_INT_CNTL); + bm_off = crtc_int_cntl & CRTC_BUSMASTER_EOL_INT; +// if(bm_off) OUTREG(CRTC_INT_CNTL,crtc_int_cntl | CRTC_BUSMASTER_EOL_INT); + return bm_off?0:1; +} + +int VIDIX_NAME(vixPlaybackCopyFrame)( vidix_dma_t * dmai ) +{ + int retval,sync_mode; + if(!(dmai->flags & BM_DMA_FIXED_BUFFS)) if(bm_lock_mem(dmai->src,dmai->size) != 0) return errno; + sync_mode = (dmai->flags & BM_DMA_SYNC) == BM_DMA_SYNC; + if(sync_mode) + { + if(!irq_installed) init_irq(); + /* burn CPU instead of PCI bus here */ + while(vixQueryDMAStatus()!=0){ + if(can_use_irq) hwirq_wait(pci_info.irq); + else usleep(0); /* ugly but may help */ + } + } + mach64_engine_reset(); + retval = mach64_setup_frame(dmai); + VIRT_TO_CARD(mach64_dma_desc_base[dmai->idx],1,&bus_addr_dma_desc); + if(retval == 0) retval = mach64_transfer_frame(bus_addr_dma_desc,sync_mode); + if(!(dmai->flags & BM_DMA_FIXED_BUFFS)) bm_unlock_mem(dmai->src,dmai->size); + return retval; +} +#endif diff --git a/contrib/vidix/drivers/mga_vid.c b/contrib/vidix/drivers/mga_vid.c new file mode 100644 index 000000000..eed2b9e65 --- /dev/null +++ b/contrib/vidix/drivers/mga_vid.c @@ -0,0 +1,1567 @@ +/* + * Matrox MGA driver + * + * ported to VIDIX by Alex Beregszaszi + * + * YUY2 support (see config.format) added by A'rpi/ESP-team + * double buffering added by A'rpi/ESP-team + * + * Brightness/contrast support by Nick Kurshev/Dariush Pietrzak (eyck) and me + * + * Fixed Brightness/Contrast + * Rewrite or read/write kabi@users.sf.net + * + * TODO: + * * fix memory size detection (current reading pci userconfig isn't + * working as requested - returns the max avail. ram on arch?) + * * translate all non-english comments to english + */ + +/* + * Original copyright: + * + * mga_vid.c + * + * Copyright (C) 1999 Aaron Holtzman + * + * Module skeleton based on gutted agpgart module by Jeff Hartmann + * <slicer@ionet.net> + * + * Matrox MGA G200/G400 YUV Video Interface module Version 0.1.0 + * + * BES == Back End Scaler + * + * This software has been released under the terms of the GNU Public + * license. See http://www.gnu.org/copyleft/gpl.html for details. + */ + +//#define CRTC2 + +// Set this value, if autodetection fails! (video ram size in megabytes) +//#define MGA_MEMORY_SIZE 16 + +/* No irq support in userspace implemented yet, do not enable this! */ +/* disable irq */ +#undef MGA_ALLOW_IRQ + +#define MGA_VSYNC_POS 2 + +#undef MGA_PCICONFIG_MEMDETECT + +#define MGA_DEFAULT_FRAMES 64 + +#define BES + +#ifdef MGA_TV +#undef BES +#define CRTC2 +#endif + +#include <errno.h> +#include <stdio.h> +#include <stdlib.h> +#include <string.h> +#include <math.h> +#include <inttypes.h> + +#include "vidix.h" +#include "fourcc.h" +#include "libdha.h" +#include "pci_ids.h" +#include "pci_names.h" + +#if !defined(ENOTSUP) && defined(EOPNOTSUPP) +#define ENOTSUP EOPNOTSUPP +#endif + +#ifdef CRTC2 +#define VIDIX_STATIC mga_crtc2_ +#define MGA_MSG "[mga_crtc2]" +#else +#define VIDIX_STATIC mga_ +#define MGA_MSG "[mga]" +#endif + +/* from radeon_vid */ +#define GETREG(TYPE,PTR,OFFZ) (*((volatile TYPE*)((PTR)+(OFFZ)))) +#define SETREG(TYPE,PTR,OFFZ,VAL) (*((volatile TYPE*)((PTR)+(OFFZ))))=VAL + +#define readb(addr) GETREG(uint8_t,(uint32_t)(mga_mmio_base + addr),0) +#define writeb(addr, val) SETREG(uint8_t,(uint32_t)(mga_mmio_base + addr),0,val) +#define readl(addr) GETREG(uint32_t,(uint32_t)(mga_mmio_base + addr),0) +#define writel(addr, val) SETREG(uint32_t,(uint32_t)(mga_mmio_base + addr),0,val) + +static int mga_verbose = 0; + +/* for device detection */ +static int probed = 0; +static pciinfo_t pci_info; + +/* internal booleans */ +static int mga_vid_in_use = 0; +static int is_g400 = 0; +static int vid_src_ready = 0; +static int vid_overlay_on = 0; + +/* mapped physical addresses */ +static uint8_t *mga_mmio_base = 0; +static uint8_t* mga_mem_base = 0; + +static int mga_src_base = 0; /* YUV buffer position in video memory */ + +static uint32_t mga_ram_size = 0; /* how much megabytes videoram we have */ + +/* Graphic keys */ +static vidix_grkey_t mga_grkey; + +static int colkey_saved = 0; +static int colkey_on = 0; +static unsigned char colkey_color[4]; +static unsigned char colkey_mask[4]; + +/* for IRQ */ +static int mga_irq = -1; + +static int mga_next_frame = 0; + +static vidix_capability_t mga_cap = +{ +#ifdef CRTC2 + "Matrox MGA G200/G4x0/G5x0 YUV Video - with second-head support", +#else + "Matrox MGA G200/G4x0/G5x0 YUV Video", +#endif + "Aaron Holtzman, Arpad Gereoffy, Alex Beregszaszi, Nick Kurshev", + TYPE_OUTPUT, + { 0, 0, 0, 0 }, + 2048, + 2048, + 4, + 4, + -1, + FLAG_UPSCALER | FLAG_DOWNSCALER | FLAG_EQUALIZER, + VENDOR_MATROX, + -1, /* will be set in VIDIX_NAME(vixProbe) */ + { 0, 0, 0, 0} +}; + +/* MATROX BES registers */ +typedef struct bes_registers_s +{ + //BES Control + uint32_t besctl; + //BES Global control + uint32_t besglobctl; + //Luma control (brightness and contrast) + uint32_t beslumactl; + //Line pitch + uint32_t bespitch; + + //Buffer A-1 Chroma 3 plane org + uint32_t besa1c3org; + //Buffer A-1 Chroma org + uint32_t besa1corg; + //Buffer A-1 Luma org + uint32_t besa1org; + + //Buffer A-2 Chroma 3 plane org + uint32_t besa2c3org; + //Buffer A-2 Chroma org + uint32_t besa2corg; + //Buffer A-2 Luma org + uint32_t besa2org; + + //Buffer B-1 Chroma 3 plane org + uint32_t besb1c3org; + //Buffer B-1 Chroma org + uint32_t besb1corg; + //Buffer B-1 Luma org + uint32_t besb1org; + + //Buffer B-2 Chroma 3 plane org + uint32_t besb2c3org; + //Buffer B-2 Chroma org + uint32_t besb2corg; + //Buffer B-2 Luma org + uint32_t besb2org; + + //BES Horizontal coord + uint32_t beshcoord; + //BES Horizontal inverse scaling [5.14] + uint32_t beshiscal; + //BES Horizontal source start [10.14] (for scaling) + uint32_t beshsrcst; + //BES Horizontal source ending [10.14] (for scaling) + uint32_t beshsrcend; + //BES Horizontal source last + uint32_t beshsrclst; + + + //BES Vertical coord + uint32_t besvcoord; + //BES Vertical inverse scaling [5.14] + uint32_t besviscal; + //BES Field 1 vertical source last position + uint32_t besv1srclst; + //BES Field 1 weight start + uint32_t besv1wght; + //BES Field 2 vertical source last position + uint32_t besv2srclst; + //BES Field 2 weight start + uint32_t besv2wght; + +} bes_registers_t; +static bes_registers_t regs; + +#ifdef CRTC2 +typedef struct crtc2_registers_s +{ + uint32_t c2ctl; + uint32_t c2datactl; + uint32_t c2misc; + uint32_t c2hparam; + uint32_t c2hsync; + uint32_t c2offset; + uint32_t c2pl2startadd0; + uint32_t c2pl2startadd1; + uint32_t c2pl3startadd0; + uint32_t c2pl3startadd1; + uint32_t c2preload; + uint32_t c2spicstartadd0; + uint32_t c2spicstartadd1; + uint32_t c2startadd0; + uint32_t c2startadd1; + uint32_t c2subpiclut; + uint32_t c2vcount; + uint32_t c2vparam; + uint32_t c2vsync; +} crtc2_registers_t; +static crtc2_registers_t cregs; +static crtc2_registers_t cregs_save; +#endif + +//All register offsets are converted to word aligned offsets (32 bit) +//because we want all our register accesses to be 32 bits +#define VCOUNT 0x1e20 + +#define PALWTADD 0x3c00 // Index register for X_DATAREG port +#define X_DATAREG 0x3c0a + +#define XMULCTRL 0x19 +#define BPP_8 0x00 +#define BPP_15 0x01 +#define BPP_16 0x02 +#define BPP_24 0x03 +#define BPP_32_DIR 0x04 +#define BPP_32_PAL 0x07 + +#define XCOLMSK 0x40 +#define X_COLKEY 0x42 +#define XKEYOPMODE 0x51 +#define XCOLMSK0RED 0x52 +#define XCOLMSK0GREEN 0x53 +#define XCOLMSK0BLUE 0x54 +#define XCOLKEY0RED 0x55 +#define XCOLKEY0GREEN 0x56 +#define XCOLKEY0BLUE 0x57 + +#ifdef CRTC2 +/*CRTC2 registers*/ +#define XMISCCTRL 0x1e +#define C2CTL 0x3c10 +#define C2DATACTL 0x3c4c +#define C2MISC 0x3c44 +#define C2HPARAM 0x3c14 +#define C2HSYNC 0x3c18 +#define C2OFFSET 0x3c40 +#define C2PL2STARTADD0 0x3c30 // like BESA1CORG +#define C2PL2STARTADD1 0x3c34 // like BESA2CORG +#define C2PL3STARTADD0 0x3c38 // like BESA1C3ORG +#define C2PL3STARTADD1 0x3c3c // like BESA2C3ORG +#define C2PRELOAD 0x3c24 +#define C2SPICSTARTADD0 0x3c54 +#define C2SPICSTARTADD1 0x3c58 +#define C2STARTADD0 0x3c28 // like BESA1ORG +#define C2STARTADD1 0x3c2c // like BESA2ORG +#define C2SUBPICLUT 0x3c50 +#define C2VCOUNT 0x3c48 +#define C2VPARAM 0x3c1c +#define C2VSYNC 0x3c20 +#endif /* CRTC2 */ + +// Backend Scaler registers +#define BESCTL 0x3d20 +#define BESGLOBCTL 0x3dc0 +#define BESLUMACTL 0x3d40 +#define BESPITCH 0x3d24 + +#define BESA1C3ORG 0x3d60 +#define BESA1CORG 0x3d10 +#define BESA1ORG 0x3d00 + +#define BESA2C3ORG 0x3d64 +#define BESA2CORG 0x3d14 +#define BESA2ORG 0x3d04 + +#define BESB1C3ORG 0x3d68 +#define BESB1CORG 0x3d18 +#define BESB1ORG 0x3d08 + +#define BESB2C3ORG 0x3d6C +#define BESB2CORG 0x3d1C +#define BESB2ORG 0x3d0C + +#define BESHCOORD 0x3d28 +#define BESHISCAL 0x3d30 +#define BESHSRCEND 0x3d3C +#define BESHSRCLST 0x3d50 +#define BESHSRCST 0x3d38 +#define BESV1WGHT 0x3d48 +#define BESV2WGHT 0x3d4c +#define BESV1SRCLST 0x3d54 +#define BESV2SRCLST 0x3d58 +#define BESVISCAL 0x3d34 +#define BESVCOORD 0x3d2c +#define BESSTATUS 0x3dc4 + +#define CRTCX 0x1fd4 +#define CRTCD 0x1fd5 +#define IEN 0x1e1c +#define ICLEAR 0x1e18 +#define STATUS 0x1e14 +#define CRTCEXTX 0x1fde +#define CRTCEXTD 0x1fdf + + +#ifdef CRTC2 +static void crtc2_frame_sel(int frame) +{ + switch(frame) { + case 0: + cregs.c2pl2startadd0=regs.besa1corg; + cregs.c2pl3startadd0=regs.besa1c3org; + cregs.c2startadd0=regs.besa1org; + break; + case 1: + cregs.c2pl2startadd0=regs.besa2corg; + cregs.c2pl3startadd0=regs.besa2c3org; + cregs.c2startadd0=regs.besa2org; + break; + case 2: + cregs.c2pl2startadd0=regs.besb1corg; + cregs.c2pl3startadd0=regs.besb1c3org; + cregs.c2startadd0=regs.besb1org; + break; + case 3: + cregs.c2pl2startadd0=regs.besb2corg; + cregs.c2pl3startadd0=regs.besb2c3org; + cregs.c2startadd0=regs.besb2org; + break; + } + writel(C2STARTADD0, cregs.c2startadd0); + writel(C2PL2STARTADD0, cregs.c2pl2startadd0); + writel(C2PL3STARTADD0, cregs.c2pl3startadd0); +} +#endif + +int VIDIX_NAME(vixPlaybackFrameSelect)(unsigned int frame) +{ + mga_next_frame = frame; + if (mga_verbose>1) printf(MGA_MSG" frameselect: %d\n", mga_next_frame); +#if MGA_ALLOW_IRQ + if (mga_irq == -1) +#endif + { +#ifdef BES + //we don't need the vcount protection as we're only hitting + //one register (and it doesn't seem to be double buffered) + regs.besctl = (regs.besctl & ~0x07000000) + (mga_next_frame << 25); + writel(BESCTL, regs.besctl); + + // writel( regs.besglobctl + ((readl(VCOUNT)+2)<<16), + writel(BESGLOBCTL, regs.besglobctl + (MGA_VSYNC_POS<<16)); +#endif +#ifdef CRTC2 + crtc2_frame_sel(mga_next_frame); +#endif + } + + return(0); +} + + +static void mga_vid_write_regs(int restore) +{ +#ifdef BES + //Make sure internal registers don't get updated until we're done + writel(BESGLOBCTL, (readl(VCOUNT)-1)<<16); + + // color or coordinate keying + + if (restore && colkey_saved) + { + // restore it + colkey_saved = 0; + + // Set color key registers: + writeb(PALWTADD, XKEYOPMODE); + writeb(X_DATAREG, colkey_on); + + writeb(PALWTADD, XCOLKEY0RED); + writeb(X_DATAREG, colkey_color[0]); + writeb(PALWTADD, XCOLKEY0GREEN); + writeb(X_DATAREG, colkey_color[1]); + writeb(PALWTADD, XCOLKEY0BLUE); + writeb(X_DATAREG, colkey_color[2]); + writeb(PALWTADD, X_COLKEY); + writeb(X_DATAREG, colkey_color[3]); + + writeb(PALWTADD, XCOLMSK0RED); + writeb(X_DATAREG, colkey_mask[0]); + writeb(PALWTADD, XCOLMSK0GREEN); + writeb(X_DATAREG, colkey_mask[1]); + writeb(PALWTADD, XCOLMSK0BLUE); + writeb(X_DATAREG, colkey_mask[2]); + writeb(PALWTADD, XCOLMSK); + writeb(X_DATAREG, colkey_mask[3]); + + printf(MGA_MSG" Restored colorkey (ON: %d %02X:%02X:%02X)\n", + colkey_on,colkey_color[0],colkey_color[1],colkey_color[2]); + + } else if (!colkey_saved) { + // save it + colkey_saved=1; + // Get color key registers: + writeb(PALWTADD, XKEYOPMODE); + colkey_on = readb(X_DATAREG) & 1; + + writeb(PALWTADD, XCOLKEY0RED); + colkey_color[0]=(unsigned char)readb(X_DATAREG); + writeb(PALWTADD, XCOLKEY0GREEN); + colkey_color[1]=(unsigned char)readb(X_DATAREG); + writeb(PALWTADD, XCOLKEY0BLUE); + colkey_color[2]=(unsigned char)readb(X_DATAREG); + writeb(PALWTADD, X_COLKEY); + colkey_color[3]=(unsigned char)readb(X_DATAREG); + + writeb(PALWTADD, XCOLMSK0RED); + colkey_mask[0]=(unsigned char)readb(X_DATAREG); + writeb(PALWTADD, XCOLMSK0GREEN); + colkey_mask[1]=(unsigned char)readb(X_DATAREG); + writeb(PALWTADD, XCOLMSK0BLUE); + colkey_mask[2]=(unsigned char)readb(X_DATAREG); + writeb(PALWTADD, XCOLMSK); + colkey_mask[3]=(unsigned char)readb(X_DATAREG); + + printf(MGA_MSG" Saved colorkey (ON: %d %02X:%02X:%02X)\n", + colkey_on,colkey_color[0],colkey_color[1],colkey_color[2]); + } + + if (!restore) + { + writeb(PALWTADD, XKEYOPMODE); + writeb(X_DATAREG, (mga_grkey.ckey.op == CKEY_TRUE)); + if ( mga_grkey.ckey.op == CKEY_TRUE ) + { + uint32_t r=0, g=0, b=0; + + writeb(PALWTADD, XMULCTRL); + switch (readb(X_DATAREG)) + { + case BPP_8: + /* Need to look up the color index, just using + color 0 for now. */ + break; + case BPP_15: + r = mga_grkey.ckey.red >> 3; + g = mga_grkey.ckey.green >> 3; + b = mga_grkey.ckey.blue >> 3; + break; + case BPP_16: + r = mga_grkey.ckey.red >> 3; + g = mga_grkey.ckey.green >> 2; + b = mga_grkey.ckey.blue >> 3; + break; + case BPP_24: + case BPP_32_DIR: + case BPP_32_PAL: + r = mga_grkey.ckey.red; + g = mga_grkey.ckey.green; + b = mga_grkey.ckey.blue; + break; + } + + // Disable color keying on alpha channel + writeb(PALWTADD, XCOLMSK); + writeb(X_DATAREG, 0x00); + writeb(PALWTADD, X_COLKEY); + writeb(X_DATAREG, 0x00); + + + // Set up color key registers + writeb(PALWTADD, XCOLKEY0RED); + writeb(X_DATAREG, r); + writeb(PALWTADD, XCOLKEY0GREEN); + writeb(X_DATAREG, g); + writeb(PALWTADD, XCOLKEY0BLUE); + writeb(X_DATAREG, b); + + // Set up color key mask registers + writeb(PALWTADD, XCOLMSK0RED); + writeb(X_DATAREG, 0xff); + writeb(PALWTADD, XCOLMSK0GREEN); + writeb(X_DATAREG, 0xff); + writeb(PALWTADD, XCOLMSK0BLUE); + writeb(X_DATAREG, 0xff); + } + } + + // Backend Scaler + writel(BESCTL, regs.besctl); + if (is_g400) + writel(BESLUMACTL, regs.beslumactl); + writel(BESPITCH, regs.bespitch); + + writel(BESA1ORG, regs.besa1org); + writel(BESA1CORG, regs.besa1corg); + writel(BESA2ORG, regs.besa2org); + writel(BESA2CORG, regs.besa2corg); + writel(BESB1ORG, regs.besb1org); + writel(BESB1CORG, regs.besb1corg); + writel(BESB2ORG, regs.besb2org); + writel(BESB2CORG, regs.besb2corg); + if(is_g400) + { + writel(BESA1C3ORG, regs.besa1c3org); + writel(BESA2C3ORG, regs.besa2c3org); + writel(BESB1C3ORG, regs.besb1c3org); + writel(BESB2C3ORG, regs.besb2c3org); + } + + writel(BESHCOORD, regs.beshcoord); + writel(BESHISCAL, regs.beshiscal); + writel(BESHSRCST, regs.beshsrcst); + writel(BESHSRCEND, regs.beshsrcend); + writel(BESHSRCLST, regs.beshsrclst); + + writel(BESVCOORD, regs.besvcoord); + writel(BESVISCAL, regs.besviscal); + + writel(BESV1SRCLST, regs.besv1srclst); + writel(BESV1WGHT, regs.besv1wght); + writel(BESV2SRCLST, regs.besv2srclst); + writel(BESV2WGHT, regs.besv2wght); + + //update the registers somewhere between 1 and 2 frames from now. + writel(BESGLOBCTL, regs.besglobctl + ((readl(VCOUNT)+2)<<16)); + + if (mga_verbose > 1) + { + printf(MGA_MSG" wrote BES registers\n"); + printf(MGA_MSG" BESCTL = 0x%08x\n", readl(BESCTL)); + printf(MGA_MSG" BESGLOBCTL = 0x%08x\n", readl(BESGLOBCTL)); + printf(MGA_MSG" BESSTATUS= 0x%08x\n", readl(BESSTATUS)); + } +#endif + +#ifdef CRTC2 +#if 0 + if (cregs_save.c2ctl == 0) + { + //int i; + cregs_save.c2ctl = readl(C2CTL); + cregs_save.c2datactl = readl(C2DATACTL); + cregs_save.c2misc = readl(C2MISC); + + //for (i = 0; i <= 8; i++) { writeb(CRTCEXTX, i); printf("CRTCEXT%d %x\n", i, readb(CRTCEXTD)); } + //printf("c2ctl:0x%08x c2datactl:0x%08x\n", cregs_save.c2ctl, cregs_save.c2datactl); + //printf("c2misc:0x%08x\n", readl(C2MISC)); + //printf("c2ctl:0x%08x c2datactl:0x%08x\n", cregs.c2ctl, cregs.c2datactl); + } + if (restore) + { + writel(C2CTL, cregs_save.c2ctl); + writel(C2DATACTL, cregs_save.c2datactl); + writel(C2MISC, cregs_save.c2misc); + return; + } +#endif + // writel(C2CTL, cregs.c2ctl); + + writel(C2CTL, ((readl(C2CTL) & ~0x03e00000) + (cregs.c2ctl & 0x03e00000))); + writel(C2DATACTL, ((readl(C2DATACTL) & ~0x000000ff) + (cregs.c2datactl & 0x000000ff))); + // ctrc2 + // disable CRTC2 acording to specs + // writel(C2CTL, cregs.c2ctl & 0xfffffff0); + // je to treba ??? + // writeb(XMISCCTRL, (readb(XMISCCTRL) & 0x19) | 0xa2); // MAFC - mfcsel & vdoutsel + // writeb(XMISCCTRL, (readb(XMISCCTRL) & 0x19) | 0x92); + // writeb(XMISCCTRL, (readb(XMISCCTRL) & ~0xe9) + 0xa2); + writel(C2DATACTL, cregs.c2datactl); +// writel(C2HPARAM, cregs.c2hparam); + writel(C2HSYNC, cregs.c2hsync); +// writel(C2VPARAM, cregs.c2vparam); + writel(C2VSYNC, cregs.c2vsync); + //xx + //writel(C2MISC, cregs.c2misc); + + if (mga_verbose > 1) printf(MGA_MSG" c2offset = %d\n", cregs.c2offset); + + writel(C2OFFSET, cregs.c2offset); + writel(C2STARTADD0, cregs.c2startadd0); + // writel(C2STARTADD1, cregs.c2startadd1); + writel(C2PL2STARTADD0, cregs.c2pl2startadd0); + // writel(C2PL2STARTADD1, cregs.c2pl2startadd1); + writel(C2PL3STARTADD0, cregs.c2pl3startadd0); + // writel(C2PL3STARTADD1, cregs.c2pl3startadd1); + writel(C2SPICSTARTADD0, cregs.c2spicstartadd0); + + //xx + //writel(C2SPICSTARTADD1, cregs.c2spicstartadd1); + + //set Color Lookup Table for Subpicture Layer + { + unsigned char r, g, b, y, cb, cr; + int i; + for (i = 0; i < 16; i++) { + + r = (i & 0x8) ? 0xff : 0x00; + g = (i & 0x4) ? ((i & 0x2) ? 0xff : 0xaa) : ((i & 0x2) ? 0x55 : 0x00); + b = (i & 0x1) ? 0xff : 0x00; + + y = ((r * 16829 + g * 33039 + b * 6416 + 0x8000) >> 16) + 16; + cb = ((r * -9714 + g * -19071 + b * 28784 + 0x8000) >> 16) + 128; + cr = ((r * 28784 + g * -24103 + b * -4681 + 0x8000) >> 16) + 128; + + cregs.c2subpiclut = (cr << 24) | (cb << 16) | (y << 8) | i; + writel(C2SUBPICLUT, cregs.c2subpiclut); + } + } + + //writel(C2PRELOAD, cregs.c2preload); + + // finaly enable everything +// writel(C2CTL, cregs.c2ctl); + // printf("c2ctl:0x%08x c2datactl:0x%08x\n",readl(C2CTL), readl(C2DATACTL)); + // printf("c2misc:0x%08x\n", readl(C2MISC)); +#endif +} + +#ifdef MGA_ALLOW_IRQ +static void enable_irq() +{ + long int cc; + + cc = readl(IEN); + // printf("*** !!! IRQREG = %d\n", (int)(cc&0xff)); + + writeb(CRTCX, 0x11); + + writeb(CRTCD, 0x20); /* clear 0, enable off */ + writeb(CRTCD, 0x00); /* enable on */ + writeb(CRTCD, 0x10); /* clear = 1 */ + + writel(BESGLOBCTL, regs.besglobctl); + + return; +} + +static void disable_irq() +{ + writeb(CRTCX, 0x11); + writeb(CRTCD, 0x20); /* clear 0, enable off */ + + return; +} + +void mga_handle_irq(int irq, void *dev_id/*, struct pt_regs *pregs*/) { + // static int frame=0; + // static int counter=0; + long int cc; + // if ( ! mga_enabled_flag ) return; + + // printf("vcount = %d\n",readl(VCOUNT)); + + //printf("mga_interrupt #%d\n", irq); + + if ( irq != -1 ) { + + cc = readl(STATUS); + if ( ! (cc & 0x10) ) return; /* vsyncpen */ + // debug_irqcnt++; + } + + // if ( debug_irqignore ) { + // debug_irqignore = 0; + + /* + if ( mga_conf_deinterlace ) { + if ( mga_first_field ) { + // printf("mga_interrupt first field\n"); + if ( syncfb_interrupt() ) + mga_first_field = 0; + } else { + // printf("mga_interrupt second field\n"); + mga_select_buffer( mga_current_field | 2 ); + mga_first_field = 1; + } + } else { + syncfb_interrupt(); + } + */ + + // frame=(frame+1)&1; + regs.besctl = (regs.besctl & ~0x07000000) + (mga_next_frame << 25); + writel(BESCTL, regs.besctl); + +#ifdef CRTC2 + crtc2_frame_sel(mga_next_frame); +#endif + +#if 0 + ++counter; + if(!(counter&63)){ + printf("mga irq counter = %d\n",counter); + } +#endif + + // } else { + // debug_irqignore = 1; + // } + + if ( irq != -1 ) { + writeb(CRTCX, 0x11); + writeb(CRTCD, 0); + writeb(CRTCD, 0x10); + } + + //writel(BESGLOBCTL, regs.besglobctl); + +} +#endif /* MGA_ALLOW_IRQ */ + +int VIDIX_NAME(vixConfigPlayback)(vidix_playback_t *config) +{ + unsigned int i; + int x, y, sw, sh, dw, dh; + int besleft, bestop, ifactor, ofsleft, ofstop, baseadrofs, weight, weights; +#ifdef CRTC2 +#define right_margin 0 +#define left_margin 18 +#define hsync_len 46 +#define lower_margin 10 +#define vsync_len 4 +#define upper_margin 39 + + unsigned int hdispend = (config->src.w + 31) & ~31; + unsigned int hsyncstart = hdispend + (right_margin & ~7); + unsigned int hsyncend = hsyncstart + (hsync_len & ~7); + unsigned int htotal = hsyncend + (left_margin & ~7); + unsigned int vdispend = config->src.h; + unsigned int vsyncstart = vdispend + lower_margin; + unsigned int vsyncend = vsyncstart + vsync_len; + unsigned int vtotal = vsyncend + upper_margin; +#endif + + if ((config->num_frames < 1) || (config->num_frames > MGA_DEFAULT_FRAMES)) + { + printf(MGA_MSG" illegal num_frames: %d, setting to %d\n", + config->num_frames, MGA_DEFAULT_FRAMES); + config->num_frames = MGA_DEFAULT_FRAMES; + } + for(;config->num_frames>0;config->num_frames--) + { + /*FIXME: this driver can use more frames but we need to apply + some tricks to avoid RGB-memory hits*/ + mga_src_base = ((mga_ram_size/2)*0x100000-(config->num_frames+1)*config->frame_size); + mga_src_base &= (~0xFFFF); /* 64k boundary */ + if(mga_src_base>=0) break; + } + if (mga_verbose > 1) printf(MGA_MSG" YUV buffer base: 0x%x\n", mga_src_base); + + config->dga_addr = mga_mem_base + mga_src_base; + + x = config->dest.x; + y = config->dest.y; + sw = config->src.w; + sh = config->src.h; + dw = config->dest.w; + dh = config->dest.h; + + if (mga_verbose) printf(MGA_MSG" Setting up a %dx%d-%dx%d video window (src %dx%d) format %X\n", + dw, dh, x, y, sw, sh, config->fourcc); + + if ((sw < 4) || (sh < 4) || (dw < 4) || (dh < 4)) + { + printf(MGA_MSG" Invalid src/dest dimensions\n"); + return(EINVAL); + } + + //FIXME check that window is valid and inside desktop + + // printf(MGA_MSG" vcount = %d\n", readl(VCOUNT)); + + sw += sw & 1; + switch(config->fourcc) + { + case IMGFMT_I420: + case IMGFMT_IYUV: + case IMGFMT_YV12: + sh+=sh&1; + config->dest.pitch.y=config->dest.pitch.u=config->dest.pitch.v=32; + config->frame_size = ((sw + 31) & ~31) * sh + (((sw + 31) & ~31) * sh) / 2; + break; + case IMGFMT_YUY2: + case IMGFMT_UYVY: + config->dest.pitch.y=16; + config->dest.pitch.u=config->dest.pitch.v=0; + config->frame_size = ((sw + 8) & ~8) * sh * 2; + break; + default: + printf(MGA_MSG" Unsupported pixel format: %x\n", config->fourcc); + return(ENOTSUP); + } + + config->offsets[0] = 0; + // config->offsets[1] = config->frame_size; + // config->offsets[2] = 2*config->frame_size; + // config->offsets[3] = 3*config->frame_size; + for (i = 1; i < config->num_frames+2; i++) + config->offsets[i] = i*config->frame_size; + + config->offset.y=0; + config->offset.v=((sw + 31) & ~31) * sh; + config->offset.u=config->offset.v+((sw + 31) & ~31) * sh /4; + + //FIXME figure out a better way to allocate memory on card + //allocate 2 megs + //mga_src_base = mga_mem_base + (MGA_VIDMEM_SIZE-2) * 0x100000; + //mga_src_base = (MGA_VIDMEM_SIZE-3) * 0x100000; + + + /* for G200 set Interleaved UV planes */ + if (!is_g400) + config->flags = VID_PLAY_INTERLEAVED_UV | INTERLEAVING_UV; + + //Setup the BES registers for a three plane 4:2:0 video source + + regs.besglobctl = 0; + + switch(config->fourcc) + { + case IMGFMT_YV12: + case IMGFMT_I420: + case IMGFMT_IYUV: + regs.besctl = 1 // BES enabled + + (0<<6) // even start polarity + + (1<<10) // x filtering enabled + + (1<<11) // y filtering enabled + + (1<<16) // chroma upsampling + + (1<<17) // 4:2:0 mode + + (1<<18); // dither enabled +#if 0 + if(is_g400) + { + //zoom disabled, zoom filter disabled, 420 3 plane format, proc amp + //disabled, rgb mode disabled + regs.besglobctl = (1<<5); + } + else + { + //zoom disabled, zoom filter disabled, Cb samples in 0246, Cr + //in 1357, BES register update on besvcnt + regs.besglobctl = 0; + } +#endif + break; + + case IMGFMT_YUY2: + regs.besctl = 1 // BES enabled + + (0<<6) // even start polarity + + (1<<10) // x filtering enabled + + (1<<11) // y filtering enabled + + (1<<16) // chroma upsampling + + (0<<17) // 4:2:2 mode + + (1<<18); // dither enabled + + regs.besglobctl = 0; // YUY2 format selected + break; + + case IMGFMT_UYVY: + regs.besctl = 1 // BES enabled + + (0<<6) // even start polarity + + (1<<10) // x filtering enabled + + (1<<11) // y filtering enabled + + (1<<16) // chroma upsampling + + (0<<17) // 4:2:2 mode + + (1<<18); // dither enabled + + regs.besglobctl = 1<<6; // UYVY format selected + break; + + } + + //Disable contrast and brightness control + regs.besglobctl |= (1<<5) + (1<<7); + // we want to preserver these across restarts + //regs.beslumactl = (0x0 << 16) + 0x80; + + //Setup destination window boundaries + besleft = x > 0 ? x : 0; + bestop = y > 0 ? y : 0; + regs.beshcoord = (besleft<<16) + (x + dw-1); + regs.besvcoord = (bestop<<16) + (y + dh-1); + + //Setup source dimensions + regs.beshsrclst = (sw - 1) << 16; + switch(config->fourcc) + { + case IMGFMT_YV12: + case IMGFMT_I420: + case IMGFMT_IYUV: + regs.bespitch = (sw + 31) & ~31; + break; + case IMGFMT_YUY2: + case IMGFMT_UYVY: + regs.bespitch = (sw + 8) & ~8; + break; + } + + //Setup horizontal scaling + ifactor = ((sw-1)<<14)/(dw-1); + ofsleft = besleft - x; + + regs.beshiscal = ifactor<<2; + regs.beshsrcst = (ofsleft*ifactor)<<2; + regs.beshsrcend = regs.beshsrcst + (((dw - ofsleft - 1) * ifactor) << 2); + + //Setup vertical scaling + ifactor = ((sh-1)<<14)/(dh-1); + ofstop = bestop - y; + + regs.besviscal = ifactor<<2; + + baseadrofs = ((ofstop*regs.besviscal)>>16)*regs.bespitch; + //frame_size = ((sw + 31) & ~31) * sh + (((sw + 31) & ~31) * sh) / 2; + regs.besa1org = (uint32_t) mga_src_base + baseadrofs; + regs.besa2org = (uint32_t) mga_src_base + baseadrofs + 1*config->frame_size; + regs.besb1org = (uint32_t) mga_src_base + baseadrofs + 2*config->frame_size; + regs.besb2org = (uint32_t) mga_src_base + baseadrofs + 3*config->frame_size; + + if (config->fourcc == IMGFMT_YV12 + || config->fourcc == IMGFMT_IYUV + || config->fourcc == IMGFMT_I420) + { + // planar YUV frames: + if (is_g400) + baseadrofs = (((ofstop*regs.besviscal)/4)>>16)*regs.bespitch; + else + baseadrofs = (((ofstop*regs.besviscal)/2)>>16)*regs.bespitch; + + if (config->fourcc == IMGFMT_YV12){ + regs.besa1corg = (uint32_t) mga_src_base + baseadrofs + regs.bespitch * sh ; + regs.besa2corg = (uint32_t) mga_src_base + baseadrofs + 1*config->frame_size + regs.bespitch * sh; + regs.besb1corg = (uint32_t) mga_src_base + baseadrofs + 2*config->frame_size + regs.bespitch * sh; + regs.besb2corg = (uint32_t) mga_src_base + baseadrofs + 3*config->frame_size + regs.bespitch * sh; + regs.besa1c3org = regs.besa1corg + ((regs.bespitch * sh) / 4); + regs.besa2c3org = regs.besa2corg + ((regs.bespitch * sh) / 4); + regs.besb1c3org = regs.besb1corg + ((regs.bespitch * sh) / 4); + regs.besb2c3org = regs.besb2corg + ((regs.bespitch * sh) / 4); + } else { + regs.besa1c3org = (uint32_t) mga_src_base + baseadrofs + regs.bespitch * sh ; + regs.besa2c3org = (uint32_t) mga_src_base + baseadrofs + 1*config->frame_size + regs.bespitch * sh; + regs.besb1c3org = (uint32_t) mga_src_base + baseadrofs + 2*config->frame_size + regs.bespitch * sh; + regs.besb2c3org = (uint32_t) mga_src_base + baseadrofs + 3*config->frame_size + regs.bespitch * sh; + regs.besa1corg = regs.besa1c3org + ((regs.bespitch * sh) / 4); + regs.besa2corg = regs.besa2c3org + ((regs.bespitch * sh) / 4); + regs.besb1corg = regs.besb1c3org + ((regs.bespitch * sh) / 4); + regs.besb2corg = regs.besb2c3org + ((regs.bespitch * sh) / 4); + } + } + + weight = ofstop * (regs.besviscal >> 2); + weights = weight < 0 ? 1 : 0; + regs.besv2wght = regs.besv1wght = (weights << 16) + ((weight & 0x3FFF) << 2); + regs.besv2srclst = regs.besv1srclst = sh - 1 - (((ofstop * regs.besviscal) >> 16) & 0x03FF); + +#ifdef CRTC2 + // pridat hlavni registry - tj. casovani ... + + + switch(config->fourcc){ + case IMGFMT_YV12: + case IMGFMT_I420: + case IMGFMT_IYUV: + cregs.c2ctl = 1 // CRTC2 enabled + + (1<<1) // external clock + + (0<<2) // external clock + + (1<<3) // pixel clock enable - not needed ??? + + (0<<4) // high priority req + + (1<<5) // high priority req + + (0<<6) // high priority req + + (1<<8) // high priority req max + + (0<<9) // high priority req max + + (0<<10) // high priority req max + + (0<<20) // CRTC1 to DAC + + (1<<21) // 420 mode + + (1<<22) // 420 mode + + (1<<23) // 420 mode + + (0<<24) // single chroma line for 420 mode - need to be corrected + + (0<<25) /*/ interlace mode - need to be corrected*/ + + (0<<26) // field legth polariry + + (0<<27) // field identification polariry + + (1<<28) // VIDRST detection mode + + (0<<29) // VIDRST detection mode + + (1<<30) // Horizontal counter preload + + (1<<31) // Vertical counter preload + ; + cregs.c2datactl = 1 // disable dither - propably not needed, we are already in YUV mode + + (1<<1) // Y filter enable + + (1<<2) // CbCr filter enable + + (1<<3) // subpicture enable (enabled) + + (0<<4) // NTSC enable (disabled - PAL) + + (0<<5) // C2 static subpicture enable (disabled) + + (0<<6) // C2 subpicture offset division (disabled) + + (0<<7) // 422 subformat selection ! + /* + (0<<8) // 15 bpp high alpha + + (0<<9) // 15 bpp high alpha + + (0<<10) // 15 bpp high alpha + + (0<<11) // 15 bpp high alpha + + (0<<12) // 15 bpp high alpha + + (0<<13) // 15 bpp high alpha + + (0<<14) // 15 bpp high alpha + + (0<<15) // 15 bpp high alpha + + (0<<16) // 15 bpp low alpha + + (0<<17) // 15 bpp low alpha + + (0<<18) // 15 bpp low alpha + + (0<<19) // 15 bpp low alpha + + (0<<20) // 15 bpp low alpha + + (0<<21) // 15 bpp low alpha + + (0<<22) // 15 bpp low alpha + + (0<<23) // 15 bpp low alpha + + (0<<24) // static subpicture key + + (0<<25) // static subpicture key + + (0<<26) // static subpicture key + + (0<<27) // static subpicture key + + (0<<28) // static subpicture key + */ ; + break; + + case IMGFMT_YUY2: + cregs.c2ctl = 1 // CRTC2 enabled + + (1<<1) // external clock + + (0<<2) // external clock + + (1<<3) // pixel clock enable - not needed ??? + + (0<<4) // high priority req - acc to spec + + (1<<5) // high priority req + + (0<<6) // high priority req + // 7 reserved + + (1<<8) // high priority req max + + (0<<9) // high priority req max + + (0<<10) // high priority req max + // 11-19 reserved + + (0<<20) // CRTC1 to DAC + + (1<<21) // 422 mode + + (0<<22) // 422 mode + + (1<<23) // 422 mode + + (0<<24) // single chroma line for 420 mode - need to be corrected + + (0<<25) /*/ interlace mode - need to be corrected*/ + + (0<<26) // field legth polariry + + (0<<27) // field identification polariry + + (1<<28) // VIDRST detection mode + + (0<<29) // VIDRST detection mode + + (1<<30) // Horizontal counter preload + + (1<<31) // Vertical counter preload + ; + cregs.c2datactl = 1 // disable dither - propably not needed, we are already in YUV mode + + (1<<1) // Y filter enable + + (1<<2) // CbCr filter enable + + (1<<3) // subpicture enable (enabled) + + (0<<4) // NTSC enable (disabled - PAL) + + (0<<5) // C2 static subpicture enable (disabled) + + (0<<6) // C2 subpicture offset division (disabled) + + (0<<7) // 422 subformat selection ! + /* + (0<<8) // 15 bpp high alpha + + (0<<9) // 15 bpp high alpha + + (0<<10) // 15 bpp high alpha + + (0<<11) // 15 bpp high alpha + + (0<<12) // 15 bpp high alpha + + (0<<13) // 15 bpp high alpha + + (0<<14) // 15 bpp high alpha + + (0<<15) // 15 bpp high alpha + + (0<<16) // 15 bpp low alpha + + (0<<17) // 15 bpp low alpha + + (0<<18) // 15 bpp low alpha + + (0<<19) // 15 bpp low alpha + + (0<<20) // 15 bpp low alpha + + (0<<21) // 15 bpp low alpha + + (0<<22) // 15 bpp low alpha + + (0<<23) // 15 bpp low alpha + + (0<<24) // static subpicture key + + (0<<25) // static subpicture key + + (0<<26) // static subpicture key + + (0<<27) // static subpicture key + + (0<<28) // static subpicture key + */ ; + break; + + case IMGFMT_UYVY: + cregs.c2ctl = 1 // CRTC2 enabled + + (1<<1) // external clock + + (0<<2) // external clock + + (1<<3) // pixel clock enable - not needed ??? + + (0<<4) // high priority req + + (1<<5) // high priority req + + (0<<6) // high priority req + + (1<<8) // high priority req max + + (0<<9) // high priority req max + + (0<<10) // high priority req max + + (0<<20) // CRTC1 to DAC + + (1<<21) // 422 mode + + (0<<22) // 422 mode + + (1<<23) // 422 mode + + (1<<24) // single chroma line for 420 mode - need to be corrected + + (1<<25) /*/ interlace mode - need to be corrected*/ + + (0<<26) // field legth polariry + + (0<<27) // field identification polariry + + (1<<28) // VIDRST detection mode + + (0<<29) // VIDRST detection mode + + (1<<30) // Horizontal counter preload + + (1<<31) // Vertical counter preload + ; + cregs.c2datactl = 0 // enable dither - propably not needed, we are already in YUV mode + + (1<<1) // Y filter enable + + (1<<2) // CbCr filter enable + + (1<<3) // subpicture enable (enabled) + + (0<<4) // NTSC enable (disabled - PAL) + + (0<<5) // C2 static subpicture enable (disabled) + + (0<<6) // C2 subpicture offset division (disabled) + + (1<<7) // 422 subformat selection ! + /* + (0<<8) // 15 bpp high alpha + + (0<<9) // 15 bpp high alpha + + (0<<10) // 15 bpp high alpha + + (0<<11) // 15 bpp high alpha + + (0<<12) // 15 bpp high alpha + + (0<<13) // 15 bpp high alpha + + (0<<14) // 15 bpp high alpha + + (0<<15) // 15 bpp high alpha + + (0<<16) // 15 bpp low alpha + + (0<<17) // 15 bpp low alpha + + (0<<18) // 15 bpp low alpha + + (0<<19) // 15 bpp low alpha + + (0<<20) // 15 bpp low alpha + + (0<<21) // 15 bpp low alpha + + (0<<22) // 15 bpp low alpha + + (0<<23) // 15 bpp low alpha + + (0<<24) // static subpicture key + + (0<<25) // static subpicture key + + (0<<26) // static subpicture key + + (0<<27) // static subpicture key + + (0<<28) // static subpicture key + */ ; + break; + } + + cregs.c2hparam=((hdispend - 8) << 16) | (htotal - 8); + cregs.c2hsync=((hsyncend - 8) << 16) | (hsyncstart - 8); + + cregs.c2misc=0 // CRTCV2 656 togg f0 + +(0<<1) // CRTCV2 656 togg f0 + +(0<<2) // CRTCV2 656 togg f0 + +(0<<4) // CRTCV2 656 togg f1 + +(0<<5) // CRTCV2 656 togg f1 + +(0<<6) // CRTCV2 656 togg f1 + +(0<<8) // Hsync active high + +(0<<9) // Vsync active high + // 16-27 c2vlinecomp - nevim co tam dat + ; + cregs.c2offset=(regs.bespitch << 1); + + cregs.c2pl2startadd0=regs.besa1corg; + //cregs.c2pl2startadd1=regs.besa2corg; + cregs.c2pl3startadd0=regs.besa1c3org; + //cregs.c2pl3startadd1=regs.besa2c3org; + + cregs.c2preload=(vsyncstart << 16) | (hsyncstart); // from + + memset(config->dga_addr + config->offsets[config->num_frames], 0, config->frame_size); // clean spic area + cregs.c2spicstartadd0=(uint32_t) mga_src_base + baseadrofs + config->num_frames*config->frame_size; + //cregs.c2spicstartadd1=0; // not used + + cregs.c2startadd0=regs.besa1org; + //cregs.c2startadd1=regs.besa2org; + + cregs.c2subpiclut=0; //not used + + cregs.c2vparam=((vdispend - 1) << 16) | (vtotal - 1); + cregs.c2vsync=((vsyncend - 1) << 16) | (vsyncstart - 1); +#endif /* CRTC2 */ + + mga_vid_write_regs(0); + return(0); +} + +int VIDIX_NAME(vixPlaybackOn)(void) +{ + if (mga_verbose) printf(MGA_MSG" playback on\n"); + + vid_src_ready = 1; + if(vid_overlay_on) + { + regs.besctl |= 1; + mga_vid_write_regs(0); + } +#ifdef MGA_ALLOW_IRQ + if (mga_irq != -1) + enable_irq(); +#endif + mga_next_frame=0; + + return(0); +} + +int VIDIX_NAME(vixPlaybackOff)(void) +{ + if (mga_verbose) printf(MGA_MSG" playback off\n"); + + vid_src_ready = 0; +#ifdef MGA_ALLOW_IRQ + if (mga_irq != -1) + disable_irq(); +#endif + regs.besctl &= ~1; + regs.besglobctl &= ~(1<<6); /* UYVY format selected */ + mga_vid_write_regs(0); + + return(0); +} + +int VIDIX_NAME(vixProbe)(int verbose,int force) +{ + pciinfo_t lst[MAX_PCI_DEVICES]; + unsigned int i, num_pci; + int err; + + if (verbose) printf(MGA_MSG" probe\n"); + + mga_verbose = verbose; + + is_g400 = -1; + + err = pci_scan(lst, &num_pci); + if (err) + { + printf(MGA_MSG" Error occured during pci scan: %s\n", strerror(err)); + return(err); + } + + if (mga_verbose) + printf(MGA_MSG" found %d pci devices\n", num_pci); + + for (i = 0; i < num_pci; i++) + { + if (mga_verbose > 1) + printf(MGA_MSG" pci[%d] vendor: %d device: %d\n", + i, lst[i].vendor, lst[i].device); + if (lst[i].vendor == VENDOR_MATROX) + { + switch(lst[i].device) + { + case DEVICE_MATROX_MGA_G550_AGP: + printf(MGA_MSG" Found MGA G550\n"); + is_g400 = 1; + goto card_found; + case DEVICE_MATROX_MGA_G400_AGP: + printf(MGA_MSG" Found MGA G400/G450\n"); + is_g400 = 1; + goto card_found; +#ifndef CRTC2 + case DEVICE_MATROX_MGA_G200_AGP: + printf(MGA_MSG" Found MGA G200 AGP\n"); + is_g400 = 0; + goto card_found; + case DEVICE_MATROX_MGA_G200: + printf(MGA_MSG" Found MGA G200 PCI\n"); + is_g400 = 0; + goto card_found; +#endif + } + } + } + + if (is_g400 == -1) + { + if(verbose) + printf(MGA_MSG" Can't find chip\n\n"); + return(ENXIO); + } + +card_found: + probed = 1; + memcpy(&pci_info, &lst[i], sizeof(pciinfo_t)); + + mga_cap.device_id = pci_info.device; /* set device id in capabilites */ + + return(0); +} + +int VIDIX_NAME(vixInit)(const char *args) +{ + unsigned int card_option = 0; + int err; + + /* reset Brightness & Constrast here */ + regs.beslumactl = (0x0 << 16) + 0x80; + + if (mga_verbose) printf(MGA_MSG" init\n"); + + mga_vid_in_use = 0; + + if (!probed) + { + printf(MGA_MSG" driver was not probed but is being initializing\n"); + return(EINTR); + } + +#ifdef MGA_PCICONFIG_MEMDETECT + pci_config_read(pci_info.bus, pci_info.card, pci_info.func, + 0x40, 4, &card_option); + if (mga_verbose > 1) printf(MGA_MSG" OPTION word: 0x%08X mem: 0x%02X %s\n", card_option, + (card_option>>10)&0x17, ((card_option>>14)&1)?"SGRAM":"SDRAM"); +#endif + + if (mga_ram_size) + { + printf(MGA_MSG" RAMSIZE forced to %d MB\n", mga_ram_size); + } + else + { +#ifdef MGA_MEMORY_SIZE + mga_ram_size = MGA_MEMORY_SIZE; + printf(MGA_MSG" hard-coded RAMSIZE is %d MB\n", (unsigned int) mga_ram_size); +#else + if (is_g400) + { + switch((card_option>>10)&0x17) + { + // SDRAM: + case 0x00: + case 0x04: mga_ram_size = 16; break; + case 0x03: mga_ram_size = 32; break; + // SGRAM: + case 0x10: + case 0x14: mga_ram_size = 32; break; + case 0x11: + case 0x12: mga_ram_size = 16; break; + default: + mga_ram_size = 16; + printf(MGA_MSG" Couldn't detect RAMSIZE, assuming 16MB!\n"); + } + } + else + { + switch((card_option>>10)&0x17) + { + // case 0x10: + // case 0x13: mga_ram_size = 8; break; + default: mga_ram_size = 8; + } + } + +#if 0 + // printf("List resources -----------\n"); + for(temp=0;temp<DEVICE_COUNT_RESOURCE;temp++){ + struct resource *res=&pci_dev->resource[temp]; + if(res->flags){ + int size=(1+res->end-res->start)>>20; + printf("res %d: start: 0x%X end: 0x%X (%d MB) flags=0x%X\n",temp,res->start,res->end,size,res->flags); + if(res->flags&(IORESOURCE_MEM|IORESOURCE_PREFETCH)){ + if(size>mga_ram_size && size<=64) mga_ram_size=size; + } + } + } +#endif + + printf(MGA_MSG" detected RAMSIZE is %d MB\n", (unsigned int) mga_ram_size); +#endif + } + + if (mga_ram_size) + { + if ((mga_ram_size < 4) || (mga_ram_size > 64)) + { + printf(MGA_MSG" invalid RAMSIZE: %d MB\n", mga_ram_size); + return(EINVAL); + } + } + + if (mga_verbose > 1) printf(MGA_MSG" hardware addresses: mmio: 0x%lx, framebuffer: 0x%lx\n", + pci_info.base1, pci_info.base0); + + mga_mmio_base = map_phys_mem(pci_info.base1,0x4000); + mga_mem_base = map_phys_mem(pci_info.base0,mga_ram_size*1024*1024); + + if (mga_verbose > 1) printf(MGA_MSG" MMIO at %p, IRQ: %d, framebuffer: %p\n", + mga_mmio_base, mga_irq, mga_mem_base); + err = mtrr_set_type(pci_info.base0,mga_ram_size*1024*1024,MTRR_TYPE_WRCOMB); + if(!err) printf(MGA_MSG" Set write-combining type of video memory\n"); +#ifdef MGA_ALLOW_IRQ + if (mga_irq != -1) + { + int tmp = request_irq(mga_irq, mga_handle_irq, SA_INTERRUPT | SA_SHIRQ, "Syncfb Time Base", &mga_irq); + if (tmp) + { + printf("syncfb (mga): cannot register irq %d (Err: %d)\n", mga_irq, tmp); + mga_irq=-1; + } + else + { + printf("syncfb (mga): registered irq %d\n", mga_irq); + } + } + else + { + printf("syncfb (mga): No valid irq was found\n"); + mga_irq=-1; + } +#else + printf(MGA_MSG" IRQ support disabled\n"); + mga_irq=-1; +#endif +#ifdef CRTC2 + memset(&cregs_save, 0, sizeof(cregs_save)); +#endif + return(0); +} + +void VIDIX_NAME(vixDestroy)(void) +{ + if (mga_verbose) printf(MGA_MSG" destroy\n"); + + /* FIXME turn off BES */ + vid_src_ready = 0; + regs.besctl &= ~1; + regs.besglobctl &= ~(1<<6); // UYVY format selected + // mga_config.colkey_on=0; //!!! + mga_vid_write_regs(1); + mga_vid_in_use = 0; + +#ifdef MGA_ALLOW_IRQ + if (mga_irq != -1) + free_irq(mga_irq, &mga_irq); +#endif + + if (mga_mmio_base) + unmap_phys_mem(mga_mmio_base, 0x4000); + if (mga_mem_base) + unmap_phys_mem(mga_mem_base, mga_ram_size); + return; +} + +int VIDIX_NAME(vixQueryFourcc)(vidix_fourcc_t *to) +{ + int supports=0; + if (mga_verbose) printf(MGA_MSG" query fourcc (%x)\n", to->fourcc); + + switch(to->fourcc) + { + case IMGFMT_YV12: + case IMGFMT_IYUV: + case IMGFMT_I420: + supports = is_g400 ? 1 : 0; + case IMGFMT_NV12: + supports = is_g400 ? 0 : 1; + case IMGFMT_YUY2: + case IMGFMT_UYVY: + supports = 1; + break; + default: + supports = 0; + } + + if(!supports) + { + to->depth = to->flags = 0; + return(ENOTSUP); + } + to->depth = VID_DEPTH_12BPP | + VID_DEPTH_15BPP | VID_DEPTH_16BPP | + VID_DEPTH_24BPP | VID_DEPTH_32BPP; + to->flags = VID_CAP_EXPAND | VID_CAP_SHRINK | VID_CAP_COLORKEY; + return(0); +} + +unsigned int VIDIX_NAME(vixGetVersion)(void) +{ + return(VIDIX_VERSION); +} + +int VIDIX_NAME(vixGetCapability)(vidix_capability_t *to) +{ + memcpy(to, &mga_cap, sizeof(vidix_capability_t)); + return(0); +} + +int VIDIX_NAME(vixGetGrKeys)(vidix_grkey_t *grkey) +{ + memcpy(grkey, &mga_grkey, sizeof(vidix_grkey_t)); + return(0); +} + +int VIDIX_NAME(vixSetGrKeys)(const vidix_grkey_t *grkey) +{ + memcpy(&mga_grkey, grkey, sizeof(vidix_grkey_t)); + return(0); +} + +int VIDIX_NAME(vixPlaybackSetEq)( const vidix_video_eq_t * eq) +{ + uint32_t luma; + float factor = 255.0 / 2000; + + /* contrast and brightness control isn't supported on G200 - alex */ + if (!is_g400) + { + if (mga_verbose) printf(MGA_MSG" equalizer isn't supported with G200\n"); + return(ENOTSUP); + } + + luma = regs.beslumactl; + + if (eq->cap & VEQ_CAP_BRIGHTNESS) + { + luma &= 0xffff; + luma |= (((int)(eq->brightness * factor) & 0xff) << 16); + } + if (eq->cap & VEQ_CAP_CONTRAST) + { + luma &= 0xffff << 16; + luma |= ((int)((eq->contrast + 1000) * factor) & 0xff); + } + + regs.beslumactl = luma; +#ifdef BES + writel(BESLUMACTL, regs.beslumactl); +#endif + return(0); +} + +int VIDIX_NAME(vixPlaybackGetEq)( vidix_video_eq_t * eq) +{ + float factor = 2000.0 / 255; + + /* contrast and brightness control isn't supported on G200 - alex */ + if (!is_g400) + { + if (mga_verbose) printf(MGA_MSG" equalizer isn't supported with G200\n"); + return(ENOTSUP); + } + + // BESLUMACTL is WO only registr! + // this will not work: regs.beslumactl = readl(BESLUMACTL); + eq->brightness = ((signed char)((regs.beslumactl >> 16) & 0xff)) * factor; + eq->contrast = (regs.beslumactl & 0xFF) * factor - 1000; + eq->cap = VEQ_CAP_BRIGHTNESS | VEQ_CAP_CONTRAST; + + return(0); +} diff --git a/contrib/vidix/drivers/nvidia_vid.c b/contrib/vidix/drivers/nvidia_vid.c new file mode 100644 index 000000000..34fa27cb7 --- /dev/null +++ b/contrib/vidix/drivers/nvidia_vid.c @@ -0,0 +1,976 @@ +/* + nvidia_vid - VIDIX based video driver for NVIDIA chips + Copyrights 2003 - 2004 Sascha Sommer. This file is based on sources from + RIVATV (rivatv.sf.net) + Licence: GPL + WARNING: THIS DRIVER IS IN BETA STAGE + + multi buffer support and TNT2 fixes by Dmitry Baryshkov +*/ + + +#include <errno.h> +#include <stdio.h> +#include <stdlib.h> +#include <string.h> +#include <inttypes.h> +#include <unistd.h> + + +#include "vidix.h" +#include "fourcc.h" +#include "libdha.h" +#include "pci_ids.h" +#include "pci_names.h" +#include "bswap.h" + + +pciinfo_t pci_info; + + +#define MAX_FRAMES 3 +#define NV04_BES_SIZE 1024*2000*4 + + +static vidix_capability_t nvidia_cap = { + "NVIDIA RIVA OVERLAY DRIVER", + "Sascha Sommer <saschasommer@freenet.de>", + TYPE_OUTPUT, + { 0, 0, 0, 0 }, + 2046, + 2046, + 4, + 4, + -1, + FLAG_UPSCALER|FLAG_DOWNSCALER, + VENDOR_NVIDIA2, + -1, + { 0, 0, 0, 0 } +}; + + +unsigned int vixGetVersion(void){ + return(VIDIX_VERSION); +} + + +#define NV_ARCH_03 0x03 +#define NV_ARCH_04 0x04 +#define NV_ARCH_10 0x10 +#define NV_ARCH_20 0x20 +#define NV_ARCH_30 0x30 + +struct nvidia_cards { + unsigned short chip_id; + unsigned short arch; +}; + +static struct nvidia_cards nvidia_card_ids[] = { + /*NV03*/ + {DEVICE_NVIDIA2_RIVA128, NV_ARCH_03}, + {DEVICE_NVIDIA2_RIVA128ZX,NV_ARCH_03}, + /*NV04*/ + {DEVICE_NVIDIA_NV4_RIVA_TNT,NV_ARCH_04}, + {DEVICE_NVIDIA_NV5_RIVA_TNT2,NV_ARCH_04}, + {DEVICE_NVIDIA_NV5_RIVA_TNT22,NV_ARCH_04}, + {DEVICE_NVIDIA_NV5_RIVA_TNT23,NV_ARCH_04}, + {DEVICE_NVIDIA_NV6_VANTA,NV_ARCH_04}, + {DEVICE_NVIDIA_NV6_VANTA2,NV_ARCH_04}, + {DEVICE_NVIDIA2_TNT,NV_ARCH_04}, + {DEVICE_NVIDIA2_TNT2,NV_ARCH_04}, + {DEVICE_NVIDIA2_VTNT2,NV_ARCH_04}, + {DEVICE_NVIDIA2_UTNT2 ,NV_ARCH_04}, + {DEVICE_NVIDIA2_ITNT2,NV_ARCH_04}, + {DEVICE_NVIDIA_NV5_ALADDIN_TNT2,NV_ARCH_30}, + /*NV10*/ + {DEVICE_NVIDIA_NV18_GEFORCE_PCX,NV_ARCH_10}, + {DEVICE_NVIDIA_NV10_GEFORCE_256,NV_ARCH_10}, + {DEVICE_NVIDIA_NV10DDR_GEFORCE_256,NV_ARCH_10}, + {DEVICE_NVIDIA_NV10GL_QUADRO,NV_ARCH_10}, + {DEVICE_NVIDIA_NV11_GEFORCE2_MX_MX,NV_ARCH_10}, + {DEVICE_NVIDIA_NV11DDR_GEFORCE2_MX,NV_ARCH_10}, + {DEVICE_NVIDIA_NV11_GEFORCE2_GO,NV_ARCH_10}, + {DEVICE_NVIDIA_NV11GL_QUADRO2_MXR_EX,NV_ARCH_10}, + {DEVICE_NVIDIA_NV15_GEFORCE2_GTS_PRO,NV_ARCH_10}, + {DEVICE_NVIDIA_NV15DDR_GEFORCE2_TI,NV_ARCH_10}, + {DEVICE_NVIDIA_NV15BR_GEFORCE2_ULTRA,NV_ARCH_10}, + {DEVICE_NVIDIA_NV15GL_QUADRO2_PRO,NV_ARCH_10}, + {DEVICE_NVIDIA_NV17_GEFORCE4_MX,NV_ARCH_10}, + {DEVICE_NVIDIA_NV17_GEFORCE4_MX2,NV_ARCH_10}, + {DEVICE_NVIDIA_NV17_GEFORCE4_MX3,NV_ARCH_10}, + {DEVICE_NVIDIA_NV17_GEFORCE4_MX4,NV_ARCH_10}, + {DEVICE_NVIDIA_NV17_GEFORCE4_440,NV_ARCH_10}, + {DEVICE_NVIDIA_NV17_GEFORCE4_420,NV_ARCH_10}, + {DEVICE_NVIDIA_NV17_GEFORCE4_4202,NV_ARCH_10}, + {DEVICE_NVIDIA_NV17GL_QUADRO4_550,NV_ARCH_10}, + {DEVICE_NVIDIA_NV17_GEFORCE4_4402,NV_ARCH_10}, + {DEVICE_NVIDIA_NV17GL_QUADRO4_200_400,NV_ARCH_10}, + {DEVICE_NVIDIA_NV17GL_QUADRO4_5502,NV_ARCH_10}, + {DEVICE_NVIDIA_NV17GL_QUADRO4_5503,NV_ARCH_10}, + {DEVICE_NVIDIA_NV17_GEFORCE4_410,NV_ARCH_10}, + {DEVICE_NVIDIA_NV18_GEFORCE4_MX,NV_ARCH_10}, + {DEVICE_NVIDIA_NV18_GEFORCE4_MX2,NV_ARCH_10}, + {DEVICE_NVIDIA_NV18_GEFORCE4_MX3,NV_ARCH_10}, + {DEVICE_NVIDIA_NV18_GEFORCE4_MX4,NV_ARCH_10}, + {DEVICE_NVIDIA_NV18M_GEFORCE4_448,NV_ARCH_10}, + {DEVICE_NVIDIA_NV18M_GEFORCE4_488,NV_ARCH_10}, + {DEVICE_NVIDIA_NV18GL_QUADRO4_580,NV_ARCH_10}, + {DEVICE_NVIDIA_NV18GL_QUADRO4_NVS,NV_ARCH_10}, + {DEVICE_NVIDIA_NV18GL_QUADRO4_380,NV_ARCH_10}, + {DEVICE_NVIDIA_NV18M_GEFORCE4_4482,NV_ARCH_10}, + {DEVICE_NVIDIA_NVCRUSH11_GEFORCE2_MX,NV_ARCH_10}, + {DEVICE_NVIDIA_NFORCE2_AGP_DIFFERENT,NV_ARCH_10}, + {DEVICE_NVIDIA_NFORCE2_AGP,NV_ARCH_10}, + {DEVICE_NVIDIA_NV18_GEFORCE4_MX5,NV_ARCH_10}, + /*NV20*/ + {DEVICE_NVIDIA_NV20_GEFORCE3,NV_ARCH_20}, + {DEVICE_NVIDIA_NV20_GEFORCE3_TI,NV_ARCH_20}, + {DEVICE_NVIDIA_NV20_GEFORCE3_TI2,NV_ARCH_20}, + {DEVICE_NVIDIA_NV20DCC_QUADRO_DCC,NV_ARCH_20}, + {DEVICE_NVIDIA_NV25_GEFORCE4_TI,NV_ARCH_20}, + {DEVICE_NVIDIA_NV25_GEFORCE4_TI2,NV_ARCH_20}, + {DEVICE_NVIDIA_NV25_GEFORCE4_TI3,NV_ARCH_20}, + {DEVICE_NVIDIA_NV25_GEFORCE4_TI4,NV_ARCH_20}, + {DEVICE_NVIDIA_NV25GL_QUADRO4_900,NV_ARCH_20}, + {DEVICE_NVIDIA_NV25GL_QUADRO4_750,NV_ARCH_20}, + {DEVICE_NVIDIA_NV25GL_QUADRO4_700,NV_ARCH_20}, + {DEVICE_NVIDIA_NV28_GEFORCE4_TI,NV_ARCH_20}, + {DEVICE_NVIDIA_NV28_GEFORCE4_TI2,NV_ARCH_20}, + {DEVICE_NVIDIA_NV28_GEFORCE4_TI3,NV_ARCH_20}, + {DEVICE_NVIDIA_NV28_GEFORCE4_TI4,NV_ARCH_20}, + {DEVICE_NVIDIA_NV28GL_QUADRO4_980,NV_ARCH_20}, + {DEVICE_NVIDIA_NV28GL_QUADRO4_780,NV_ARCH_20}, + {DEVICE_NVIDIA_NV28GLM_QUADRO4_700,NV_ARCH_20}, + /*NV30*/ + {DEVICE_NVIDIA_NV30_GEFORCE_FX,NV_ARCH_30}, + {DEVICE_NVIDIA_NV30_GEFORCE_FX2,NV_ARCH_30}, + {DEVICE_NVIDIA_NV30_GEFORCE_FX3,NV_ARCH_30}, + {DEVICE_NVIDIA_NV30GL_QUADRO_FX,NV_ARCH_30}, + {DEVICE_NVIDIA_NV30GL_QUADRO_FX2,NV_ARCH_30}, + {DEVICE_NVIDIA_NV31_GEFORCE_FX,NV_ARCH_30}, + {DEVICE_NVIDIA_NV31_GEFORCE_FX2,NV_ARCH_30}, + {DEVICE_NVIDIA_NV31,NV_ARCH_30}, + {DEVICE_NVIDIA_NV31_GEFORCE_FX3,NV_ARCH_30}, + {DEVICE_NVIDIA_NV312,NV_ARCH_30}, + {DEVICE_NVIDIA_NV313,NV_ARCH_30}, + {DEVICE_NVIDIA_NV31M_GEFORCE_FX,NV_ARCH_30}, + {DEVICE_NVIDIA_NV31M_GEFORCE_FX2,NV_ARCH_30}, + {DEVICE_NVIDIA_NVIDIA_QUADRO_FX,NV_ARCH_30}, + {DEVICE_NVIDIA_NV314,NV_ARCH_30}, + {DEVICE_NVIDIA_NV315,NV_ARCH_30}, + {DEVICE_NVIDIA_NV316,NV_ARCH_30}, + {DEVICE_NVIDIA_NV34_GEFORCE_FX,NV_ARCH_30}, + {DEVICE_NVIDIA_NV34_GEFORCE_FX2,NV_ARCH_30}, + {DEVICE_NVIDIA_NV34_GEFORCE_FX3,NV_ARCH_30}, + {DEVICE_NVIDIA_NV34_GEFORCE_FX4,NV_ARCH_30}, + {DEVICE_NVIDIA_NV34M_GEFORCE_FX,NV_ARCH_30}, + {DEVICE_NVIDIA_NV34M_GEFORCE_FX2,NV_ARCH_30}, + {DEVICE_NVIDIA_NV34_GEFORCE_FX5,NV_ARCH_30}, + {DEVICE_NVIDIA_NV34_GEFORCE_FX6,NV_ARCH_30}, + {DEVICE_NVIDIA_NV34M_GEFORCE_FX3,NV_ARCH_30}, + {DEVICE_NVIDIA_NV34M_GEFORCE_FX4,NV_ARCH_30}, + {DEVICE_NVIDIA_NV34GL_QUADRO_NVS,NV_ARCH_30}, + {DEVICE_NVIDIA_NV34GL_QUADRO_FX,NV_ARCH_30}, + {DEVICE_NVIDIA_NV34GLM_GEFORCE_FX,NV_ARCH_30}, + {DEVICE_NVIDIA_NV34_GEFORCE_FX7,NV_ARCH_30}, + {DEVICE_NVIDIA_NV34,NV_ARCH_30}, + {DEVICE_NVIDIA_NV35_GEFORCE_FX,NV_ARCH_30}, + {DEVICE_NVIDIA_NV35_GEFORCE_FX2,NV_ARCH_30}, + {DEVICE_NVIDIA_NV35_GEFORCE_FX3,NV_ARCH_30}, + {DEVICE_NVIDIA_NV38_GEFORCE_FX,NV_ARCH_30}, + {DEVICE_NVIDIA_NV35_GEFORCE_FX4,NV_ARCH_30}, + {DEVICE_NVIDIA_NV35GL_QUADRO_FX,NV_ARCH_30}, + {DEVICE_NVIDIA_NV35GL_QUADRO_FX2,NV_ARCH_30}, + {DEVICE_NVIDIA_NV36_1_GEFORCE_FX,NV_ARCH_30}, + {DEVICE_NVIDIA_NV36_2_GEFORCE_FX,NV_ARCH_30}, + {DEVICE_NVIDIA_NV36_GEFORCE_FX,NV_ARCH_30}, + {DEVICE_NVIDIA_NV36_4_GEFORCE_FX,NV_ARCH_30}, + {DEVICE_NVIDIA_NV36_5,NV_ARCH_30}, + {DEVICE_NVIDIA_NV36_GEFORCE_FX2,NV_ARCH_30}, + {DEVICE_NVIDIA_NV36_GEFORCE_FX3,NV_ARCH_30}, + {DEVICE_NVIDIA_NV36,NV_ARCH_30}, + {DEVICE_NVIDIA_NV362,NV_ARCH_30}, + {DEVICE_NVIDIA_NV36_QUADRO_FX,NV_ARCH_30}, + {DEVICE_NVIDIA_NV36GL_QUADRO_FX,NV_ARCH_30}, + {DEVICE_NVIDIA_NV36GL,NV_ARCH_30}, + {DEVICE_NVIDIA_NV36_GEFORCE_PCX,NV_ARCH_30}, + {DEVICE_NVIDIA_NV35_GEFORCE_PCX,NV_ARCH_30}, + {DEVICE_NVIDIA_NV37GL_QUADRO_FX,NV_ARCH_30}, + {DEVICE_NVIDIA_NV37GL_QUADRO_FX2,NV_ARCH_30}, + {DEVICE_NVIDIA_NV38GL_QUADRO_FX,NV_ARCH_30}, + /* FIXME are they different? */ + {DEVICE_NVIDIA_NV40_GEFORCE_6800,NV_ARCH_30}, + {DEVICE_NVIDIA_NV40_GEFORCE_68002,NV_ARCH_30}, + {DEVICE_NVIDIA_NV40_2,NV_ARCH_30}, + {DEVICE_NVIDIA_NV40_3,NV_ARCH_30}, + {DEVICE_NVIDIA_NV40_GEFORCE_68003,NV_ARCH_30}, + {DEVICE_NVIDIA_NV40GL,NV_ARCH_30}, + {DEVICE_NVIDIA_NV40GL_QUADRO_FX,NV_ARCH_30}, + {DEVICE_NVIDIA_NV41_0,NV_ARCH_30}, + {DEVICE_NVIDIA_NV41_1,NV_ARCH_30}, + {DEVICE_NVIDIA_NV41_2,NV_ARCH_30}, + {DEVICE_NVIDIA_NV41_8,NV_ARCH_30}, + {DEVICE_NVIDIA_NV41GL,NV_ARCH_30}, + {DEVICE_NVIDIA_NV40_GEFORCE_6800_GEFORCE,NV_ARCH_30}, + {DEVICE_NVIDIA_NV43_GEFORCE_6600_GEFORCE,NV_ARCH_30}, + {DEVICE_NVIDIA_NV43_GEFORCE_6600,NV_ARCH_30}, + {DEVICE_NVIDIA_NV45GL_QUADRO_FX,NV_ARCH_30}, + {DEVICE_NVIDIA_NV40_GEFORCE_68004,NV_ARCH_30} +}; + + +static int find_chip(unsigned chip_id){ + unsigned i; + for(i = 0;i < sizeof(nvidia_card_ids)/sizeof(struct nvidia_cards);i++) + { + if(chip_id == nvidia_card_ids[i].chip_id)return i; + } + return -1; +} + +int vixProbe(int verbose, int force){ + pciinfo_t lst[MAX_PCI_DEVICES]; + unsigned i,num_pci; + int err; + + if (force) + printf("[nvidia_vid]: warning: forcing not supported yet!\n"); + err = pci_scan(lst,&num_pci); + if(err){ + printf("[nvidia_vid] Error occurred during pci scan: %s\n",strerror(err)); + return err; + } + else { + err = ENXIO; + for(i=0; i < num_pci; i++){ + if(lst[i].vendor == VENDOR_NVIDIA2 || lst[i].vendor == VENDOR_NVIDIA){ + int idx; + const char *dname; + idx = find_chip(lst[i].device); + if(idx == -1) + continue; + dname = pci_device_name(lst[i].vendor, lst[i].device); + dname = dname ? dname : "Unknown chip"; + printf("[nvidia_vid] Found chip: %s\n", dname); + nvidia_cap.device_id = lst[i].device; + err = 0; + memcpy(&pci_info, &lst[i], sizeof(pciinfo_t)); + break; + } + } + } + if(err && verbose) printf("[nvidia_vid] Can't find chip\n"); + return err; +} + + + + +/* + * PCI-Memory IO access macros. + */ +#define VID_WR08(p,i,val) (((uint8_t *)(p))[(i)]=(val)) +#define VID_RD08(p,i) (((uint8_t *)(p))[(i)]) + +#define VID_WR32(p,i,val) (((uint32_t *)(p))[(i)/4]=(val)) +#define VID_RD32(p,i) (((uint32_t *)(p))[(i)/4]) + +#ifndef USE_RMW_CYCLES +/* + * Can be used to inhibit READ-MODIFY-WRITE cycles. On by default. + */ + +#define MEM_BARRIER() __asm__ __volatile__ ("" : : : "memory") + +#undef VID_WR08 +#define VID_WR08(p,i,val) ({ MEM_BARRIER(); ((uint8_t *)(p))[(i)]=(val); }) +#undef VID_RD08 +#define VID_RD08(p,i) ({ MEM_BARRIER(); ((uint8_t *)(p))[(i)]; }) + +#undef VID_WR32 +#define VID_WR32(p,i,val) ({ MEM_BARRIER(); ((uint32_t *)(p))[(i)/4]=(val); }) +#undef VID_RD32 +#define VID_RD32(p,i) ({ MEM_BARRIER(); ((uint32_t *)(p))[(i)/4]; }) +#endif /* USE_RMW_CYCLES */ + +#define VID_AND32(p,i,val) VID_WR32(p,i,VID_RD32(p,i)&(val)) +#define VID_OR32(p,i,val) VID_WR32(p,i,VID_RD32(p,i)|(val)) +#define VID_XOR32(p,i,val) VID_WR32(p,i,VID_RD32(p,i)^(val)) + + + + + + +struct rivatv_chip { + volatile uint32_t *PMC; /* general control */ + volatile uint32_t *PME; /* multimedia port */ + volatile uint32_t *PFB; /* framebuffer control */ + volatile uint32_t *PVIDEO; /* overlay control */ + volatile uint8_t *PCIO; /* SVGA (CRTC, ATTR) registers */ + volatile uint8_t *PVIO; /* SVGA (MISC, GRAPH, SEQ) registers */ + volatile uint32_t *PRAMIN; /* instance memory */ + volatile uint32_t *PRAMHT; /* hash table */ + volatile uint32_t *PRAMFC; /* fifo context table */ + volatile uint32_t *PRAMRO; /* fifo runout table */ + volatile uint32_t *PFIFO; /* fifo control region */ + volatile uint32_t *FIFO; /* fifo channels (USER) */ + volatile uint32_t *PGRAPH; /* graphics engine */ + + unsigned long fbsize; /* framebuffer size */ + int arch; /* compatible NV_ARCH_XX define */ + int realarch; /* real architecture */ + void (* lock) (struct rivatv_chip *, int); +}; +typedef struct rivatv_chip rivatv_chip; + + +struct rivatv_info { + unsigned int use_colorkey; + unsigned int colorkey; /* saved xv colorkey*/ + unsigned int vidixcolorkey; /*currently used colorkey*/ + unsigned int depth; + unsigned int format; + unsigned int pitch; + unsigned int width,height; + unsigned int d_width,d_height; /*scaled width && height*/ + unsigned int wx,wy; /*window x && y*/ + unsigned int screen_x; /*screen width*/ + unsigned int screen_y; /*screen height*/ + unsigned long buffer_size; /* size of the image buffer */ + struct rivatv_chip chip; /* NV architecture structure */ + void* video_base; /* virtual address of control region */ + void* control_base; /* virtual address of fb region */ + unsigned long picture_base; /* direct pointer to video picture */ + unsigned long picture_offset; /* offset of video picture in frame buffer */ +// struct rivatv_dma dma; /* DMA structure */ + unsigned int cur_frame; + unsigned int num_frames; /* number of buffers */ + int bps; /* bytes per line */ +}; +typedef struct rivatv_info rivatv_info; + +//framebuffer size funcs +static unsigned long rivatv_fbsize_nv03 (struct rivatv_chip *chip){ + if (VID_RD32 (chip->PFB, 0) & 0x00000020) { + if (((VID_RD32 (chip->PMC, 0) & 0xF0) == 0x20) + && ((VID_RD32 (chip->PMC, 0) & 0x0F) >= 0x02)) { + /* SDRAM 128 ZX. */ + return ((1 << (VID_RD32 (chip->PFB, 0) & 0x03)) * 1024 * 1024); + } + else { + return 1024 * 1024 * 8; + } + } + else { + /* SGRAM 128. */ + switch (chip->PFB[0x00000000] & 0x00000003) { + case 0: + return 1024 * 1024 * 8; + break; + case 2: + return 1024 * 1024 * 4; + break; + default: + return 1024 * 1024 * 2; + break; + } + } +} +static unsigned long rivatv_fbsize_nv04 (struct rivatv_chip *chip){ + if (VID_RD32 (chip->PFB, 0) & 0x00000100) { + return ((VID_RD32 (chip->PFB, 0) >> 12) & 0x0F) * 1024 * 1024 * 2 + + 1024 * 1024 * 2; + } else { + switch (VID_RD32 (chip->PFB, 0) & 0x00000003) { + case 0: + return 1024 * 1024 * 32; + break; + case 1: + return 1024 * 1024 * 4; + break; + case 2: + return 1024 * 1024 * 8; + break; + case 3: + default: + return 1024 * 1024 * 16; + break; + } + } +} + +static unsigned long rivatv_fbsize_nv10 (struct rivatv_chip *chip){ + return ((VID_RD32 (chip->PFB, 0x20C) >> 20) & 0x000000FF) * 1024 * 1024; +} + +//lock funcs +static void rivatv_lock_nv03 (struct rivatv_chip *chip, int LockUnlock){ + VID_WR08 (chip->PVIO, 0x3C4, 0x06); + VID_WR08 (chip->PVIO, 0x3C5, LockUnlock ? 0x99 : 0x57); +} + +static void rivatv_lock_nv04 (struct rivatv_chip *chip, int LockUnlock){ + VID_WR08 (chip->PCIO, 0x3C4, 0x06); + VID_WR08 (chip->PCIO, 0x3C5, LockUnlock ? 0x99 : 0x57); + VID_WR08 (chip->PCIO, 0x3D4, 0x1F); + VID_WR08 (chip->PCIO, 0x3D5, LockUnlock ? 0x99 : 0x57); +} + + + + +/* Enable PFB (Framebuffer), PVIDEO (Overlay unit) and PME (Mediaport) if neccessary. */ +static void rivatv_enable_PMEDIA (struct rivatv_info *info){ + uint32_t reg; + + /* switch off interrupts once for a while */ +// VID_WR32 (info->chip.PME, 0x200140, 0x00); +// VID_WR32 (info->chip.PMC, 0x000140, 0x00); + + reg = VID_RD32 (info->chip.PMC, 0x000200); + + /* NV3 (0x10100010): NV03_PMC_ENABLE_PMEDIA, NV03_PMC_ENABLE_PFB, NV03_PMC_ENABLE_PVIDEO */ + + if ((reg & 0x10100010) != 0x10100010) { + printf("PVIDEO and PFB disabled, enabling...\n"); + VID_OR32 (info->chip.PMC, 0x000200, 0x10100010); + } + + /* save the current colorkey */ + switch (info->chip.arch ) { + case NV_ARCH_10: + case NV_ARCH_20: + case NV_ARCH_30: + /* NV_PVIDEO_COLOR_KEY */ + info->colorkey = VID_RD32 (info->chip.PVIDEO, 0xB00); + break; + case NV_ARCH_03: + case NV_ARCH_04: + /* NV_PVIDEO_KEY */ + info->colorkey = VID_RD32 (info->chip.PVIDEO, 0x240); + break; + } + + + /* re-enable interrupts again */ +// VID_WR32 (info->chip.PMC, 0x000140, 0x01); +// VID_WR32 (info->chip.PME, 0x200140, 0x01); +} + +/* Stop overlay video. */ +static void rivatv_overlay_stop (struct rivatv_info *info) { + switch (info->chip.arch ) { + case NV_ARCH_10: + case NV_ARCH_20: + case NV_ARCH_30: + /* NV_PVIDEO_COLOR_KEY */ + /* Xv-Extension-Hack: Restore previously saved value. */ + VID_WR32 (info->chip.PVIDEO, 0xB00, info->colorkey); + /* NV_PVIDEO_STOP */ + VID_OR32 (info->chip.PVIDEO, 0x704, 0x11); + /* NV_PVIDEO_BUFFER */ + VID_AND32 (info->chip.PVIDEO, 0x700, ~0x11); + /* NV_PVIDEO_INTR_EN_BUFFER */ +// VID_AND32 (info->chip.PVIDEO, 0x140, ~0x11); + break; + case NV_ARCH_03: + case NV_ARCH_04: + /* NV_PVIDEO_KEY */ + VID_WR32 (info->chip.PVIDEO, 0x240, info->colorkey); + /* NV_PVIDEO_OVERLAY_VIDEO_OFF */ + VID_AND32 (info->chip.PVIDEO, 0x244, ~0x01); + /* NV_PVIDEO_INTR_EN_0_NOTIFY */ +// VID_AND32 (info->chip.PVIDEO, 0x140, ~0x01); + /* NV_PVIDEO_OE_STATE */ + VID_WR32 (info->chip.PVIDEO, 0x224, 0); + /* NV_PVIDEO_SU_STATE */ + VID_WR32 (info->chip.PVIDEO, 0x228, 0); + /* NV_PVIDEO_RM_STATE */ + VID_WR32 (info->chip.PVIDEO, 0x22C, 0); + break; + } +} + +/* Get pan offset of the physical screen. */ +static uint32_t rivatv_overlay_pan (struct rivatv_info *info){ + uint32_t pan; + info->chip.lock (&info->chip, 0); + VID_WR08 (info->chip.PCIO, 0x3D4, 0x0D); + pan = VID_RD08 (info->chip.PCIO, 0x3D5); + VID_WR08 (info->chip.PCIO, 0x3D4, 0x0C); + pan |= VID_RD08 (info->chip.PCIO, 0x3D5) << 8; + VID_WR08 (info->chip.PCIO, 0x3D4, 0x19); + pan |= (VID_RD08 (info->chip.PCIO, 0x3D5) & 0x1F) << 16; + VID_WR08 (info->chip.PCIO, 0x3D4, 0x2D); + pan |= (VID_RD08 (info->chip.PCIO, 0x3D5) & 0x60) << 16; + return pan << 2; +} + +/* Compute and set colorkey depending on the colour depth. */ +static void rivatv_overlay_colorkey (rivatv_info* info, unsigned int chromakey){ + uint32_t r, g, b, key = 0; + + r = (chromakey & 0x00FF0000) >> 16; + g = (chromakey & 0x0000FF00) >> 8; + b = chromakey & 0x000000FF; + switch (info->depth) { + case 15: + key = ((r >> 3) << 10) | ((g >> 3) << 5) | ((b >> 3)); +#ifndef WIN32 + key = key | 0x00008000; +#endif + break; + case 16: // XXX unchecked + key = ((r >> 3) << 11) | ((g >> 2) << 5) | ((b >> 3)); +#ifndef WIN32 + key = key | 0x00008000; +#endif + break; + case 24: // XXX unchecked, maybe swap order of masking - FIXME Can the card be in 24 bit mode anyway? + key = (chromakey & 0x00FFFFFF) | 0x00800000; + break; + case 32: + key = chromakey; +#ifndef WIN32 + key = key | 0x80000000; +#endif + break; + } + //printf("[nvidia_vid] depth=%d %08X \n", info->depth, chromakey); + switch (info->chip.arch) { + case NV_ARCH_10: + case NV_ARCH_20: + case NV_ARCH_30: + VID_WR32 (info->chip.PVIDEO, 0xB00, key); + break; + case NV_ARCH_03: + case NV_ARCH_04: + VID_WR32 (info->chip.PVIDEO, 0x240, key); + break; + } +} + +static void nv_getscreenproperties(struct rivatv_info *info){ + uint32_t bpp=0; + info->chip.lock(&info->chip, 0); + /*get screen depth*/ + VID_WR08(info->chip.PCIO, 0x03D4,0x28); + bpp = VID_RD08(info->chip.PCIO,0x03D5)&0x3; + if(bpp==3)bpp=4; + if((bpp == 2) && (info->chip.PVIDEO[0x00000600/4] & 0x00001000) == 0x0)info->depth=15; + else info->depth = bpp*8; + /*get screen width*/ + VID_WR08(info->chip.PCIO, 0x03D4, 0x1); + info->screen_x = (1 + VID_RD08(info->chip.PCIO, 0x3D5)) * 8; + /*get screen height*/ + /* get first 8 bits in VT_DISPLAY_END*/ + VID_WR08(info->chip.PCIO, 0x03D4, 0x12); + info->screen_y = VID_RD08(info->chip.PCIO,0x03D5); + VID_WR08(info->chip.PCIO,0x03D4,0x07); + /* get 9th bit in CRTC_OVERFLOW*/ + info->screen_y |= (VID_RD08(info->chip.PCIO,0x03D5) &0x02)<<7; + /* and the 10th in CRTC_OVERFLOW*/ + info->screen_y |=(VID_RD08(info->chip.PCIO,0x03D5) &0x40)<<3; + ++info->screen_y; +} + + + + +/* Start overlay video. */ +static void rivatv_overlay_start (struct rivatv_info *info,int bufno){ + uint32_t base, size, offset, xscale, yscale, pan; + uint32_t value; + int x=info->wx?info->wx:8, y=info->wy?info->wy:8; + int lwidth=info->d_width, lheight=info->d_height; + int bps; + int i; + + size = info->buffer_size; + base = info->picture_offset; + offset = bufno*size; + /*update depth & dimensions here because it may change with vo vesa or vo fbdev*/ + nv_getscreenproperties(info); + + if(info->depth){ +// bps = info->screen_x * ((info->depth+1)/8); + /* get pan offset of the physical screen */ + pan = rivatv_overlay_pan (info); + /* adjust window position depending on the pan offset */ + bps = 0; + info->chip.lock (&info->chip, 0); + for (i = 0; (i < 1024) && (bps == 0); i++) + { + if (info->chip.arch != NV_ARCH_03) + bps = info->chip.PGRAPH[0x00000670/4]; + else + bps = info->chip.PGRAPH[0x00000650/4]; + } + if (bps == 0) + { + fprintf(stderr, "[nvidia_vid] reading bps returned 0!!!\n"); + if (info->bps != 0) + bps = info->bps; + } + else + { + info->bps = bps; + } + + if (bps != 0) + { + x = info->wx - (pan % bps) * 8 / info->depth; + y = info->wy - (pan / bps); + } + } + + /* adjust negative output window variables */ + if (x < 0) { + lwidth = info->d_width + x; + offset += (-x * info->width / info->d_width) << 1; +// offset += (-window->x * port->vld_width / window->width) << 1; + x = 0; + } + if (y < 0) { + lheight = info->d_height + y; + offset += (-y * info->height / info->d_height * info->width) << 1; +// offset += (-window->y * port->vld_height / window->height * port->org_width) << 1; + y = 0; + } + + switch (info->chip.arch) { + case NV_ARCH_10: + case NV_ARCH_20: + case NV_ARCH_30: + + /* NV_PVIDEO_BASE */ + VID_WR32 (info->chip.PVIDEO, 0x900 + 0, base + offset); + //VID_WR32 (info->chip.PVIDEO, 0x900 + 4, base); + /* NV_PVIDEO_LIMIT */ + VID_WR32 (info->chip.PVIDEO, 0x908 + 0, base + offset + size - 1); + //VID_WR32 (info->chip.PVIDEO, 0x908 + 4, base + size - 1); + + /* extra code for NV20 && NV30 architectures */ + if (info->chip.arch == NV_ARCH_20 || info->chip.arch == NV_ARCH_30) { + VID_WR32 (info->chip.PVIDEO, 0x800 + 0, base + offset); + //VID_WR32 (info->chip.PVIDEO, 0x800 + 4, base); + VID_WR32 (info->chip.PVIDEO, 0x808 + 0, base + offset + size - 1); + //VID_WR32 (info->chip.PVIDEO, 0x808 + 4, base + size - 1); + } + + /* NV_PVIDEO_LUMINANCE */ + VID_WR32 (info->chip.PVIDEO, 0x910 + 0, 0x00001000); + //VID_WR32 (info->chip.PVIDEO, 0x910 + 4, 0x00001000); + /* NV_PVIDEO_CHROMINANCE */ + VID_WR32 (info->chip.PVIDEO, 0x918 + 0, 0x00001000); + //VID_WR32 (info->chip.PVIDEO, 0x918 + 4, 0x00001000); + + /* NV_PVIDEO_OFFSET */ + VID_WR32 (info->chip.PVIDEO, 0x920 + 0, 0x0); + //VID_WR32 (info->chip.PVIDEO, 0x920 + 4, offset + pitch); + /* NV_PVIDEO_SIZE_IN */ + VID_WR32 (info->chip.PVIDEO, 0x928 + 0, ((info->height) << 16) | info->width); + //VID_WR32 (info->chip.PVIDEO, 0x928 + 4, ((port->org_height/2) << 16) | port->org_width); + /* NV_PVIDEO_POINT_IN */ + VID_WR32 (info->chip.PVIDEO, 0x930 + 0, 0x00000000); + //VID_WR32 (info->chip.PVIDEO, 0x930 + 4, 0x00000000); + /* NV_PVIDEO_DS_DX_RATIO */ + VID_WR32 (info->chip.PVIDEO, 0x938 + 0, (info->width << 20) / info->d_width); + //VID_WR32 (info->chip.PVIDEO, 0x938 + 4, (port->org_width << 20) / window->width); + /* NV_PVIDEO_DT_DY_RATIO */ + VID_WR32 (info->chip.PVIDEO, 0x940 + 0, ((info->height) << 20) / info->d_height); + //VID_WR32 (info->chip.PVIDEO, 0x940 + 4, ((port->org_height/2) << 20) / window->height); + + /* NV_PVIDEO_POINT_OUT */ + VID_WR32 (info->chip.PVIDEO, 0x948 + 0, ((y + 0) << 16) | x); + //VID_WR32 (info->chip.PVIDEO, 0x948 + 4, ((y + 0) << 16) | x); + /* NV_PVIDEO_SIZE_OUT */ + VID_WR32 (info->chip.PVIDEO, 0x950 + 0, (lheight << 16) | lwidth); + //VID_WR32 (info->chip.PVIDEO, 0x950 + 4, (height << 16) | width); + + /* NV_PVIDEO_FORMAT */ + value = info->pitch; + if(info->use_colorkey)value |= 1 << 20; + if(info->format == IMGFMT_YUY2)value |= 1 << 16; + VID_WR32 (info->chip.PVIDEO, 0x958 + 0, value); + //VID_WR32 (info->chip.PVIDEO, 0x958 + 4, (pitch << 1) | 0x00100000); + + /* NV_PVIDEO_INTR_EN_BUFFER */ +// VID_OR32 (info->chip.PVIDEO, 0x140, 0x01/*0x11*/); + /* NV_PVIDEO_STOP */ + VID_WR32 (info->chip.PVIDEO, 0x704,0x0); + /* NV_PVIDEO_BUFFER */ + VID_WR32 (info->chip.PVIDEO, 0x700, 0x01/*0x11*/); + break; + + case NV_ARCH_03: + case NV_ARCH_04: + + + /* NV_PVIDEO_OE_STATE */ + VID_WR32 (info->chip.PVIDEO, 0x224, 0); + /* NV_PVIDEO_SU_STATE */ + VID_WR32 (info->chip.PVIDEO, 0x228, 0); + /* NV_PVIDEO_RM_STATE */ + VID_WR32 (info->chip.PVIDEO, 0x22C, 0); + + /* NV_PVIDEO_BUFF0_START_ADDRESS */ + VID_WR32 (info->chip.PVIDEO, 0x20C + 0, base + offset + 0); + VID_WR32 (info->chip.PVIDEO, 0x20C + 4, base + offset + 0); + /* NV_PVIDEO_BUFF0_PITCH_LENGTH */ + VID_WR32 (info->chip.PVIDEO, 0x214 + 0, info->pitch); + VID_WR32 (info->chip.PVIDEO, 0x214 + 4, info->pitch); + + /* NV_PVIDEO_WINDOW_START */ + VID_WR32 (info->chip.PVIDEO, 0x230, (y << 16) | x); + /* NV_PVIDEO_WINDOW_SIZE */ + VID_WR32 (info->chip.PVIDEO, 0x234, (lheight << 16) | lwidth); + /* NV_PVIDEO_STEP_SIZE */ + yscale = ((info->height - 1) << 11) / (info->d_height - 1); + xscale = ((info->width - 1) << 11) / (info->d_width - 1); + VID_WR32 (info->chip.PVIDEO, 0x200, (yscale << 16) | xscale); + + /* NV_PVIDEO_RED_CSC_OFFSET */ + VID_WR32 (info->chip.PVIDEO, 0x280, 0x69); + /* NV_PVIDEO_GREEN_CSC_OFFSET */ + VID_WR32 (info->chip.PVIDEO, 0x284, 0x3e); + /* NV_PVIDEO_BLUE_CSC_OFFSET */ + VID_WR32 (info->chip.PVIDEO, 0x288, 0x89); + /* NV_PVIDEO_CSC_ADJUST */ + VID_WR32 (info->chip.PVIDEO, 0x28C, 0x00000); /* No colour correction! */ + + /* NV_PVIDEO_CONTROL_Y (BLUR_ON, LINE_HALF) */ + VID_WR32 (info->chip.PVIDEO, 0x204, 0x001); + /* NV_PVIDEO_CONTROL_X (WEIGHT_HEAVY, SHARPENING_ON, SMOOTHING_ON) */ + VID_WR32 (info->chip.PVIDEO, 0x208, 0x111); /*directx overlay 0x110 */ + + /* NV_PVIDEO_FIFO_BURST_LENGTH */ + VID_WR32 (info->chip.PVIDEO, 0x23C, 0x03); + /* NV_PVIDEO_FIFO_THRES_SIZE */ + VID_WR32 (info->chip.PVIDEO, 0x238, 0x38); /*windows uses 0x40*/ + + /* NV_PVIDEO_BUFF0_OFFSET */ + VID_WR32 (info->chip.PVIDEO, 0x21C + 0, 0); + VID_WR32 (info->chip.PVIDEO, 0x21C + 4, 0); + + /* NV_PVIDEO_INTR_EN_0_NOTIFY_ENABLED */ +// VID_OR32 (info->chip.PVIDEO, 0x140, 0x01); + + /* NV_PVIDEO_OVERLAY (KEY_ON, VIDEO_ON, FORMAT_CCIR) */ + value = 0x1; /*video on*/ + if(info->format==IMGFMT_YUY2)value |= 0x100; + if(info->use_colorkey)value |=0x10; + VID_WR32 (info->chip.PVIDEO, 0x244, value); + + /* NV_PVIDEO_SU_STATE */ + VID_XOR32 (info->chip.PVIDEO, 0x228, 1 << 16); + break; + } + /*set colorkey*/ + rivatv_overlay_colorkey(info,info->vidixcolorkey); + +} + + + + + + + +static rivatv_info* info; + + + + +int vixInit(const char *args){ + int mtrr; + info = (rivatv_info*)calloc(1,sizeof(rivatv_info)); + info->control_base = map_phys_mem(pci_info.base0, 0x00C00000 + 0x00008000); + info->chip.arch = nvidia_card_ids[find_chip(pci_info.device)].arch; + printf("[nvidia_vid] arch %x register base %x\n",info->chip.arch,(unsigned int)info->control_base); + info->chip.PFIFO = (uint32_t *) (info->control_base + 0x00002000); + info->chip.FIFO = (uint32_t *) (info->control_base + 0x00800000); + info->chip.PMC = (uint32_t *) (info->control_base + 0x00000000); + info->chip.PFB = (uint32_t *) (info->control_base + 0x00100000); + info->chip.PME = (uint32_t *) (info->control_base + 0x00000000); + info->chip.PCIO = (uint8_t *) (info->control_base + 0x00601000); + info->chip.PVIO = (uint8_t *) (info->control_base + 0x000C0000); + info->chip.PGRAPH = (uint32_t *) (info->control_base + 0x00400000); + /* setup chip specific functions */ + switch (info->chip.arch) { + case NV_ARCH_03: + info->chip.lock = rivatv_lock_nv03; + info->chip.fbsize = rivatv_fbsize_nv03 (&info->chip); + info->chip.PVIDEO = (uint32_t *) (info->control_base + 0x00680000); + break; + case NV_ARCH_04: + info->chip.lock = rivatv_lock_nv04; + info->chip.fbsize = rivatv_fbsize_nv04 (&info->chip); + info->chip.PRAMIN = (uint32_t *) (info->control_base + 0x00700000); + info->chip.PVIDEO = (uint32_t *) (info->control_base + 0x00680000); + break; + case NV_ARCH_10: + case NV_ARCH_20: + case NV_ARCH_30: + info->chip.lock = rivatv_lock_nv04; + info->chip.fbsize = rivatv_fbsize_nv10 (&info->chip); + info->chip.PRAMIN = (uint32_t *) (info->control_base + 0x00700000); + info->chip.PVIDEO = (uint32_t *) (info->control_base + 0x00008000); + break; + } + switch (info->chip.arch) { + case NV_ARCH_03: + { + /* This maps framebuffer @6MB, thus 2MB are left for video. */ + info->video_base = map_phys_mem(pci_info.base1, info->chip.fbsize); + /* This may trash your screen for resolutions greater than 1024x768, sorry. */ + info->picture_offset = 1024*768* 4 * ((info->chip.fbsize > 4194304)?2:1); + info->picture_base = (uint32_t) info->video_base + info->picture_offset; + info->chip.PRAMIN = (uint32_t *) (info->video_base + 0x00C00000); + break; + } + case NV_ARCH_04: + case NV_ARCH_10: + case NV_ARCH_20: + case NV_ARCH_30: + { + info->video_base = map_phys_mem(pci_info.base1, info->chip.fbsize); + info->picture_offset = info->chip.fbsize - NV04_BES_SIZE; +// info->picture_base = (unsigned long)map_phys_mem(pci_info.base1+info->picture_offset,NV04_BES_SIZE); + info->picture_base = (uint32_t) info->video_base + info->picture_offset; + break; + } + } + + printf("[nvidia_vid] detected memory size %u MB\n",(uint32_t)(info->chip.fbsize /1024/1024)); + + if ((mtrr = mtrr_set_type(pci_info.base1, info->chip.fbsize, MTRR_TYPE_WRCOMB))!= 0) + printf("[nvidia_vid] unable to setup MTRR: %s\n", strerror(mtrr)); + else + printf("[nvidia_vid] MTRR set up\n"); + + nv_getscreenproperties(info); + if(!info->depth)printf("[nvidia_vid] text mode: %ux%u\n",info->screen_x,info->screen_y); + else printf("[nvidia_vid] video mode: %ux%u@%u\n",info->screen_x,info->screen_y, info->depth); + + + rivatv_enable_PMEDIA(info); + info->cur_frame = 0; + info->use_colorkey = 0; + + return 0; +} + +void vixDestroy(void){ + unmap_phys_mem(info->control_base ,0x00C00000 + 0x00008000); + unmap_phys_mem(info->video_base, info->chip.fbsize); + free(info); +} + +int vixGetCapability(vidix_capability_t *to){ + memcpy(to, &nvidia_cap, sizeof(vidix_capability_t)); + return 0; +} + +inline static int is_supported_fourcc(uint32_t fourcc) +{ + if (fourcc == IMGFMT_UYVY || fourcc == IMGFMT_YUY2) + return 1; + else + return 0; +} + +int vixQueryFourcc(vidix_fourcc_t *to){ + if(is_supported_fourcc(to->fourcc)){ + to->depth = VID_DEPTH_1BPP | VID_DEPTH_2BPP | + VID_DEPTH_4BPP | VID_DEPTH_8BPP | + VID_DEPTH_12BPP| VID_DEPTH_15BPP| + VID_DEPTH_16BPP| VID_DEPTH_24BPP| + VID_DEPTH_32BPP; + to->flags = VID_CAP_EXPAND | VID_CAP_SHRINK | VID_CAP_COLORKEY; + return 0; + } + else to->depth = to->flags = 0; + return ENOSYS; +} + +int vixConfigPlayback(vidix_playback_t *vinfo){ + uint32_t i; + printf("called %s\n", __FUNCTION__); + if (! is_supported_fourcc(vinfo->fourcc)) + return ENOSYS; + + info->width = vinfo->src.w; + info->height = vinfo->src.h; + + info->d_width = vinfo->dest.w; + info->d_height = vinfo->dest.h; + info->wx = vinfo->dest.x; + info->wy = vinfo->dest.y; + info->format = vinfo->fourcc; + + printf("[nvidia_vid] setting up a %dx%d-%dx%d video window (src %dx%d), format 0x%X\n", + info->d_width, info->d_height, info->wx, info->wy, info->width, info->height, vinfo->fourcc); + + + vinfo->dga_addr=(void*)(info->picture_base); + + switch (vinfo->fourcc) + { + case IMGFMT_YUY2: + case IMGFMT_UYVY: + + vinfo->dest.pitch.y = 16; + vinfo->dest.pitch.u = 0; + vinfo->dest.pitch.v = 0; + + vinfo->offset.y = 0; + vinfo->offset.v = 0; + vinfo->offset.u = 0; + info->pitch = ((info->width << 1) + (vinfo->dest.pitch.y-1)) & ~(vinfo->dest.pitch.y-1); + vinfo->frame_size = info->pitch * info->height; + break; + } + info->buffer_size = vinfo->frame_size; + info->num_frames = vinfo->num_frames= (info->chip.fbsize - info->picture_offset)/vinfo->frame_size; + if(vinfo->num_frames > MAX_FRAMES)vinfo->num_frames = MAX_FRAMES; +// vinfo->num_frames = 1; +// printf("[nvidia_vid] Number of frames %i\n",vinfo->num_frames); + for(i=0;i <vinfo->num_frames;i++)vinfo->offsets[i] = vinfo->frame_size*i; + return 0; +} + +int vixPlaybackOn(void){ + rivatv_overlay_start(info,info->cur_frame); + return 0; +} + +int vixPlaybackOff(void){ + rivatv_overlay_stop(info); + return 0; +} + +int vixSetGrKeys( const vidix_grkey_t * grkey){ + if (grkey->ckey.op == CKEY_FALSE) + { + info->use_colorkey = 0; + printf("[nvidia_vid] colorkeying disabled\n"); + } + else { + info->use_colorkey = 1; + info->vidixcolorkey = ((grkey->ckey.red<<16)|(grkey->ckey.green<<8)|grkey->ckey.blue); + printf("[nvidia_vid] set colorkey 0x%x\n",info->vidixcolorkey); + } + if(info->d_width && info->d_height)rivatv_overlay_start(info,0); + return 0; +} + +int vixPlaybackFrameSelect(unsigned int frame){ +// printf("selecting buffer %d\n", frame); + rivatv_overlay_start(info, frame); + if (info->num_frames >= 1) + info->cur_frame = frame/*(frame+1)%info->num_frames*/; + return 0; +} + diff --git a/contrib/vidix/drivers/pm2_vid.c b/contrib/vidix/drivers/pm2_vid.c new file mode 100644 index 000000000..075b178de --- /dev/null +++ b/contrib/vidix/drivers/pm2_vid.c @@ -0,0 +1,357 @@ +/** + Driver for 3DLabs Permedia 2. + + Copyright (C) 2002 MÃ¥ns RullgÃ¥rd + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +**/ + +#include <errno.h> +#include <stdio.h> +#include <stdlib.h> +#include <string.h> +#include <inttypes.h> +#include <sys/types.h> +#include <unistd.h> + +#include "vidix.h" +#include "fourcc.h" +#include "libdha.h" +#include "pci_ids.h" +#include "pci_names.h" + +#include "glint_regs.h" + +#define VIDIX_STATIC pm2_ + +/* MBytes of video memory to use */ +#define PM2_VIDMEM 6 + +#if 0 +#define TRACE_ENTER() fprintf(stderr, "%s: enter\n", __FUNCTION__) +#define TRACE_EXIT() fprintf(stderr, "%s: exit\n", __FUNCTION__) +#else +#define TRACE_ENTER() +#define TRACE_EXIT() +#endif + +#define WRITE_REG(offset,val) \ + *(volatile u_long *)(((u_char *)(pm2_reg_base)) + offset) = (val) +#define READ_REG(offset) \ + *(volatile unsigned long *)(((unsigned char *)(pm2_reg_base)) + offset) + +pciinfo_t pci_info; + +void *pm2_reg_base; +void *pm2_mem; + +int pm2_vidmem = PM2_VIDMEM; + +static vidix_capability_t pm2_cap = +{ + "3DLabs Permedia2 driver", + "MÃ¥ns RullgÃ¥rd <mru@users.sf.net>", + TYPE_OUTPUT, + { 0, 0, 0, 0 }, + 2048, + 2048, + 4, + 4, + -1, + FLAG_UPSCALER|FLAG_DOWNSCALER, + VENDOR_3DLABS, + -1, + { 0, 0, 0, 0 } +}; + + +unsigned int VIDIX_NAME(vixGetVersion)(void) +{ + return(VIDIX_VERSION); +} + +static u_int pm2_card_ids[] = +{ + (VENDOR_3DLABS << 16) | DEVICE_3DLABS_PERMEDIA2, + (VENDOR_TEXAS << 16) | DEVICE_TEXAS_TVP4020_PERMEDIA_2 +}; + +static int find_chip(u_int vendor, u_int chip_id) +{ + u_int vci = (vendor << 16) | chip_id; + unsigned i; + for(i = 0; i < sizeof(pm2_card_ids)/sizeof(u_int); i++){ + if(vci == pm2_card_ids[i]) return i; + } + return -1; +} + +int VIDIX_NAME(vixProbe)(int verbose, int force) +{ + pciinfo_t lst[MAX_PCI_DEVICES]; + unsigned i,num_pci; + int err; + + err = pci_scan(lst,&num_pci); + if(err) + { + printf("[pm2] Error occured during pci scan: %s\n",strerror(err)); + return err; + } + else + { + err = ENXIO; + for(i=0; i < num_pci; i++) + { + int idx; + const char *dname; + idx = find_chip(lst[i].vendor, lst[i].device); + if(idx == -1) + continue; + dname = pci_device_name(lst[i].vendor, lst[i].device); + dname = dname ? dname : "Unknown chip"; + printf("[pm2] Found chip: %s\n", dname); + pm2_cap.device_id = lst[i].device; + err = 0; + memcpy(&pci_info, &lst[i], sizeof(pciinfo_t)); + break; + } + } + if(err && verbose) printf("[pm2] Can't find chip.\n"); + return err; +} + +#define PRINT_REG(reg) \ +{ \ + long _foo = READ_REG(reg); \ + printf("[pm2] " #reg " (%x) = %#lx (%li)\n", reg, _foo, _foo); \ +} + +int VIDIX_NAME(vixInit)(const char *args) +{ + char *vm; + pm2_reg_base = map_phys_mem(pci_info.base0, 0x10000); + pm2_mem = map_phys_mem(pci_info.base1, 1 << 23); + if((vm = getenv("PM2_VIDMEM"))){ + pm2_vidmem = strtol(vm, NULL, 0); + } + return 0; +} + +void VIDIX_NAME(vixDestroy)(void) +{ + unmap_phys_mem(pm2_reg_base, 0x10000); + unmap_phys_mem(pm2_mem, 1 << 23); +} + +int VIDIX_NAME(vixGetCapability)(vidix_capability_t *to) +{ + memcpy(to, &pm2_cap, sizeof(vidix_capability_t)); + return 0; +} + +static int is_supported_fourcc(uint32_t fourcc) +{ + switch(fourcc){ + case IMGFMT_YUY2: + return 1; + default: + return 0; + } +} + +int VIDIX_NAME(vixQueryFourcc)(vidix_fourcc_t *to) +{ + if(is_supported_fourcc(to->fourcc)) + { + to->depth = VID_DEPTH_1BPP | VID_DEPTH_2BPP | + VID_DEPTH_4BPP | VID_DEPTH_8BPP | + VID_DEPTH_12BPP| VID_DEPTH_15BPP| + VID_DEPTH_16BPP| VID_DEPTH_24BPP| + VID_DEPTH_32BPP; + to->flags = VID_CAP_EXPAND | VID_CAP_SHRINK | VID_CAP_COLORKEY; + return 0; + } + else to->depth = to->flags = 0; + return ENOSYS; +} + +#define FORMAT_YUV422 ((1 << 6) | 3 | (1 << 4)) + +#define PPROD(a,b,c) (a | (b << 3) | (c << 6)) + +static u_int ppcodes[][2] = { + {0, 0}, + {32, PPROD(1, 0, 0)}, + {64, PPROD(1, 1, 0)}, + {96, PPROD(1, 1, 1)}, + {128, PPROD(2, 1, 1)}, + {160, PPROD(2, 2, 1)}, + {192, PPROD(2, 2, 2)}, + {224, PPROD(3, 2, 1)}, + {256, PPROD(3, 2, 2)}, + {288, PPROD(3, 3, 1)}, + {320, PPROD(3, 3, 2)}, + {384, PPROD(3, 3, 3)}, + {416, PPROD(4, 3, 1)}, + {448, PPROD(4, 3, 2)}, + {512, PPROD(4, 3, 3)}, + {544, PPROD(4, 4, 1)}, + {576, PPROD(4, 4, 2)}, + {640, PPROD(4, 4, 3)}, + {768, PPROD(4, 4, 4)}, + {800, PPROD(5, 4, 1)}, + {832, PPROD(5, 4, 2)}, + {896, PPROD(5, 4, 3)}, + {1024, PPROD(5, 4, 4)}, + {1056, PPROD(5, 5, 1)}, + {1088, PPROD(5, 5, 2)}, + {1152, PPROD(5, 5, 3)}, + {1280, PPROD(5, 5, 4)}, + {1536, PPROD(5, 5, 5)}, + {1568, PPROD(6, 5, 1)}, + {1600, PPROD(6, 5, 2)}, + {1664, PPROD(6, 5, 3)}, + {1792, PPROD(6, 5, 4)}, + {2048, PPROD(6, 5, 5)} +}; + +static int frames[VID_PLAY_MAXFRAMES]; + +int VIDIX_NAME(vixConfigPlayback)(vidix_playback_t *info) +{ + u_int src_w, drw_w; + u_int src_h, drw_h; + long base0; + u_int stride, sstr; + u_int format; + unsigned int i; + u_int ppcode = 0, sppc = 0; + u_int pitch = 0; + + TRACE_ENTER(); + + switch(info->fourcc){ + case IMGFMT_YUY2: + format = FORMAT_YUV422; + break; + default: + return -1; + } + + src_w = info->src.w; + src_h = info->src.h; + + drw_w = info->dest.w; + drw_h = info->dest.h; + + sstr = READ_REG(PMScreenStride) * 2; + + stride = 0; + for(i = 1; i < sizeof(ppcodes) / sizeof(ppcodes[0]); i++){ + if((!stride) && (ppcodes[i][0] >= src_w)){ + stride = ppcodes[i][0]; + ppcode = ppcodes[i][1]; + pitch = ppcodes[i][0] - ppcodes[i-1][0]; + } + if(ppcodes[i][0] == sstr) + sppc = ppcodes[i][1]; + } + + if(!stride) + return -1; + + info->num_frames = pm2_vidmem*1024*1024 / (stride * src_h * 2); + if(info->num_frames > VID_PLAY_MAXFRAMES) + info->num_frames = VID_PLAY_MAXFRAMES; + + /* Use end of video memory. Assume the card has 8 MB */ + base0 = (8 - pm2_vidmem)*1024*1024; + info->dga_addr = pm2_mem + base0; + + info->dest.pitch.y = pitch*2; + info->dest.pitch.u = 0; + info->dest.pitch.v = 0; + info->offset.y = 0; + info->offset.v = 0; + info->offset.u = 0; + info->frame_size = stride * src_h * 2; + + for(i = 0; i < info->num_frames; i++){ + info->offsets[i] = info->frame_size * i; + frames[i] = (base0 + info->offsets[i]) >> 1; + } + + WRITE_REG(WindowOrigin, 0); + WRITE_REG(dY, 1 << 16); + WRITE_REG(RasterizerMode, 0); + WRITE_REG(ScissorMode, 0); + WRITE_REG(AreaStippleMode, 0); + WRITE_REG(StencilMode, 0); + WRITE_REG(TextureAddressMode, 1); + + WRITE_REG(dSdyDom, 0); + WRITE_REG(dTdx, 0); + + WRITE_REG(PMTextureMapFormat, (1 << 19) | ppcode); + WRITE_REG(PMTextureDataFormat, format); + WRITE_REG(PMTextureReadMode, (1 << 17) | /* FilterMode */ + (11 << 13) | (11 << 9) /* TextureSize log2 */ | 1); + WRITE_REG(ColorDDAMode, 0); + WRITE_REG(TextureColorMode, (0 << 4) /* RGB */ | (3 << 1) /* Copy */ | 1); + WRITE_REG(AlphaBlendMode, 0); + WRITE_REG(DitherMode, (1 << 10) | 1); + WRITE_REG(LogicalOpMode, 0); + WRITE_REG(FBReadMode, sppc); + WRITE_REG(FBHardwareWriteMask, 0xFFFFFFFF); + WRITE_REG(FBWriteMode, 1); + WRITE_REG(YUVMode, 1); + + WRITE_REG(SStart, 0); + WRITE_REG(TStart, 0); + + WRITE_REG(dSdx, (src_w << 20) / drw_w); + WRITE_REG(dTdyDom, (src_h << 20) / drw_h); + WRITE_REG(RectangleOrigin, info->dest.x | (info->dest.y << 16)); + WRITE_REG(RectangleSize, (drw_h << 16) | drw_w); + + TRACE_EXIT(); + return 0; +} + +int VIDIX_NAME(vixPlaybackOn)(void) +{ + TRACE_ENTER(); + + TRACE_EXIT(); + return 0; +} + +int VIDIX_NAME(vixPlaybackOff)(void) +{ + WRITE_REG(YUVMode, 0); + WRITE_REG(TextureColorMode, 0); + WRITE_REG(TextureAddressMode, 0); + WRITE_REG(TextureReadMode, 0); + return 0; +} + +int VIDIX_NAME(vixPlaybackFrameSelect)(unsigned int frame) +{ + WRITE_REG(PMTextureBaseAddress, frames[frame]); + WRITE_REG(Render, PrimitiveRectangle | XPositive | YPositive | + TextureEnable); + return 0; +} diff --git a/contrib/vidix/drivers/pm3_regs.h b/contrib/vidix/drivers/pm3_regs.h new file mode 100644 index 000000000..44cc92dca --- /dev/null +++ b/contrib/vidix/drivers/pm3_regs.h @@ -0,0 +1,1253 @@ +/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/glint/pm3_regs.h,v 1.9 2001/11/20 00:09:15 alanh Exp $ */ + +/* + * glint register file + * + * Copyright by Sven Luther + * Authors: Sven Luther, <luther@dpt-info.u-strasbg.fr> + * Thomas Witzel, <twitzel@nmr.mgh.harvard.edu> + * + * this work is sponsored by Appian Graphics. + * + */ + +#ifndef _PM3_REG_H_ +#define _PM3_REG_H_ + +#define PM3FIFOSize 120 + +#define PM3Tag(r) ((r>>3)&0x7ff) + +#define PM3OutputFIFO 0x2000 + +/********************************************** +* GLINT Permedia3 Control Status registers * +***********************************************/ +/* Control Status Registers */ +#define PM3ResetStatus 0x0000 +#define PM3IntEnable 0x0008 +#define PM3IntFlags 0x0010 +#define PM3InFIFOSpace 0x0018 +#define PM3OutFIFOWords 0x0020 +#define PM3DMAAddress 0x0028 +#define PM3DMACount 0x0030 +#define PM3ErrorFlags 0x0038 +#define PM3VClkCtl 0x0040 +#define PM3TestRegister 0x0048 +#define PM3Aperture0 0x0050 +#define PM3Aperture1 0x0058 +#define PM3DMAControl 0x0060 +#define PM3FIFODis 0x0068 +#define PM3ChipConfig 0x0070 +#define PM3AGPControl 0x0078 + +#define PM3GPOutDMAAddress 0x0080 +#define PM3PCIFeedbackCount 0x0088 +#define PM3PCIAbortStatus 0x0090 +#define PM3PCIAbortAddress 0x0098 + +#define PM3PCIPLLStatus 0x00f0 + +#define PM3HostTextureAddress 0x0100 +#define PM3TextureDownloadControl 0x0108 +#define PM3TextureOperation 0x0110 +#define PM3LogicalTexturePage 0x0118 +#define PM3TexDMAAddress 0x0120 +#define PM3TexFIFOSpace 0x0128 + +/********************************************** +* GLINT Permedia3 Region 0 Bypass Controls * +***********************************************/ +#define PM3ByAperture1Mode 0x0300 + #define PM3ByApertureMode_BYTESWAP_ABCD (0<<0) + #define PM3ByApertureMode_BYTESWAP_BADC (1<<0) + #define PM3ByApertureMode_BYTESWAP_CDAB (2<<0) + #define PM3ByApertureMode_BYTESWAP_DCBA (3<<0) + #define PM3ByApertureMode_PATCH_DISABLE (0<<2) + #define PM3ByApertureMode_PATCH_ENABLE (1<<2) + #define PM3ByApertureMode_FORMAT_RAW (0<<3) + #define PM3ByApertureMode_FORMAT_YUYV (1<<3) + #define PM3ByApertureMode_FORMAT_UYVY (2<<3) + #define PM3ByApertureMode_PIXELSIZE_8BIT (0<<5) + #define PM3ByApertureMode_PIXELSIZE_16BIT (1<<5) + #define PM3ByApertureMode_PIXELSIZE_32BIT (2<<5) + #define PM3ByApertureMode_EFFECTIVE_STRIDE_1024 (0<<7) + #define PM3ByApertureMode_EFFECTIVE_STRIDE_2048 (1<<7) + #define PM3ByApertureMode_EFFECTIVE_STRIDE_4096 (2<<7) + #define PM3ByApertureMode_EFFECTIVE_STRIDE_8192 (3<<7) + #define PM3ByApertureMode_PATCH_OFFSET_X(off) (((off)&7f)<<9) + #define PM3ByApertureMode_PATCH_OFFSET_Y(off) (((off)&7f)<<16) + #define PM3ByApertureMode_FRAMEBUFFER (0<<21) + #define PM3ByApertureMode_LOCALBUFFER (1<<21) + #define PM3ByApertureMode_DOUBLE_WRITE_OFF (0<<22) + #define PM3ByApertureMode_DOUBLE_WRITE_1MB (1<<22) + #define PM3ByApertureMode_DOUBLE_WRITE_2MB (2<<22) + #define PM3ByApertureMode_DOUBLE_WRITE_4MB (3<<22) + #define PM3ByApertureMode_DOUBLE_WRITE_8MB (4<<22) + #define PM3ByApertureMode_DOUBLE_WRITE_16MB (5<<22) + #define PM3ByApertureMode_DOUBLE_WRITE_32MB (6<<22) +#define PM3Aperture1Stride 0x0308 +#define PM3Aperture1YStart 0x0310 +#define PM3Aperture1UStart 0x0318 +#define PM3Aperture1VStart 0x0320 + +#define PM3ByAperture2Mode 0x0328 +#define PM3Aperture2Stride 0x0330 +#define PM3Aperture2YStart 0x0338 +#define PM3Aperture2UStart 0x0340 +#define PM3Aperture2VStart 0x0348 + +#define PM3ByDMAReadCommandBase 0x0378 +#define PM3ByDMAReadCommandCount 0x0380 +#define PM3ByDMAReadMode 0x0350 + #define PM3ByDMAReadMode_ByteSwap_NONE (0<<0) + #define PM3ByDMAReadMode_ByteSwap_BYTE (1<<0) + #define PM3ByDMAReadMode_ByteSwap_HWORD (2<<0) + #define PM3ByDMAReadMode_ByteSwap_FULL (3<<0) + #define PM3ByDMAReadMode_PatchEnable (1<<2) + #define PM3ByDMAReadMode_Format_RAW (0<<3) + #define PM3ByDMAReadMode_Format_YUYV (1<<3) + #define PM3ByDMAReadMode_Format_UYVY (2<<3) + #define PM3ByDMAReadMode_PixelSize(s) (((s>>4)&3)<<5) + #define PM3ByDMAReadMode_EffectiveStride(s) ((s&3)<<7) + #define PM3ByDMAReadMode_PatchOffsetX(x) ((x&0x3f)<<9) + #define PM3ByDMAReadMode_PatchOffsetY(y) ((y&0x3f)<<16) + #define PM3ByDMAReadMode_Buffer_FB (0<<21) + #define PM3ByDMAReadMode_Buffer_LB (1<<21) + #define PM3ByDMAReadMode_Active (1<<22) + #define PM3ByDMAReadMode_MemType_PCI (0<<23) + #define PM3ByDMAReadMode_MemType_AGP (1<<23) + #define PM3ByDMAReadMode_Burst(b) ((b&7)<<24) + #define PM3ByDMAReadMode_Align (1<<27) +#define PM3ByDMAReadStride 0x0358 +#define PM3ByDMAReadUStart 0x0368 +#define PM3ByDMAReadVStart 0x0370 +#define PM3ByDMAReadYStart 0x0360 + + +/********************************************** +* GLINT Permedia3 Memory Control (0x1000) * +***********************************************/ +#define PM3MemCounter 0x1000 +#define PM3MemBypassWriteMask 0x1008 +#define PM3MemScratch 0x1010 +#define PM3LocalMemCaps 0x1018 + #define PM3LocalMemCaps_NoWriteMask (1<<28) +#define PM3LocalMemTimings 0x1020 +#define PM3LocalMemControl 0x1028 +#define PM3LocalMemRefresh 0x1030 +#define PM3LocalMemPowerDown 0x1038 +#define PM3RemoteMemControl 0x1100 + +/********************************************** +* GLINT Permedia3 Video Control (0x3000) * +***********************************************/ + +#define PM3ScreenBase 0x3000 +#define PM3ScreenStride 0x3008 +#define PM3HTotal 0x3010 +#define PM3HgEnd 0x3018 +#define PM3HbEnd 0x3020 +#define PM3HsStart 0x3028 +#define PM3HsEnd 0x3030 +#define PM3VTotal 0x3038 +#define PM3VbEnd 0x3040 +#define PM3VsStart 0x3048 +#define PM3VsEnd 0x3050 +#define PM3VideoControl 0x3058 + #define PM3VideoControl_DISABLE (0<<0) + #define PM3VideoControl_ENABLE (1<<0) + #define PM3VideoControl_BLANK_ACTIVE_HIGH (0<<1) + #define PM3VideoControl_BLANK_ACTIVE_LOW (1<<1) + #define PM3VideoControl_LINE_DOUBLE_OFF (0<<2) + #define PM3VideoControl_LINE_DOUBLE_ON (1<<2) + #define PM3VideoControl_HSYNC_FORCE_HIGH (0<<3) + #define PM3VideoControl_HSYNC_ACTIVE_HIGH (1<<3) + #define PM3VideoControl_HSYNC_FORCE_LOW (2<<3) + #define PM3VideoControl_HSYNC_ACTIVE_LOW (3<<3) + #define PM3VideoControl_VSYNC_FORCE_HIGH (0<<5) + #define PM3VideoControl_VSYNC_ACTIVE_HIGH (1<<5) + #define PM3VideoControl_VSYNC_FORCE_LOW (2<<5) + #define PM3VideoControl_VSYNC_ACTIVE_LOW (3<<5) + #define PM3VideoControl_BYTE_DOUBLE_OFF (0<<7) + #define PM3VideoControl_BYTE_DOUBLE_ON (1<<7) + #define PM3VideoControl_BUFFER_SWAP_SYNCON_FRAMEBLANK (0<<9) + #define PM3VideoControl_BUFFER_SWAP_FREE_RUNNING (1<<9) + #define PM3VideoControl_BUFFER_SWAP_LIMITETO_FRAMERATE (2<<9) + #define PM3VideoControl_STEREO_DISABLE (0<<11) + #define PM3VideoControl_STEREO_ENABLE (1<<11) + #define PM3VideoControl_RIGHT_EYE_ACTIVE_HIGH (0<<12) + #define PM3VideoControl_RIGHT_EYE_ACTIVE_LOW (1<<12) + #define PM3VideoControl_VIDEO_EXT_LOW (0<<14) + #define PM3VideoControl_VIDEO_EXT_HIGH (1<<14) + #define PM3VideoControl_SYNC_MODE_INDEPENDENT (0<<16) + #define PM3VideoControl_SYNC_MODE_SYNCTO_VSA (1<<16) + #define PM3VideoControl_SYNC_MODE_SYNCTO_VSB (2<<16) + #define PM3VideoControl_PATCH_DISABLE (0<<18) + #define PM3VideoControl_PATCH_ENABLE (1<<18) + #define PM3VideoControl_PIXELSIZE_8BIT (0<<19) + #define PM3VideoControl_PIXELSIZE_16BIT (1<<19) + #define PM3VideoControl_PIXELSIZE_32BIT (2<<19) + #define PM3VideoControl_DISPLAY_DISABLE (0<<21) + #define PM3VideoControl_DISPLAY_ENABLE (1<<21) + #define PM3VideoControl_PATCH_OFFSET_X(off) (((off)&0x3f)<<22) + #define PM3VideoControl_PATCH_OFFSET_Y(off) (((off)&0x3f)<<28) +#define PM3InterruptLine 0x3060 +#define PM3DisplayData 0x3068 +#define PM3VerticalLineCount 0x3070 +#define PM3FifoControl 0x3078 +#define PM3ScreenBaseRight 0x3080 +#define PM3MiscControl 0x3088 + +#define PM3VideoOverlayUpdate 0x3100 + #define PM3VideoOverlayUpdate_DISABLE (0<<0) + #define PM3VideoOverlayUpdate_ENABLE (1<<0) +#define PM3VideoOverlayMode 0x3108 + #define PM3VideoOverlayMode_DISABLE (0<<0) + #define PM3VideoOverlayMode_ENABLE (1<<0) + #define PM3VideoOverlayMode_BUFFERSYNC_MANUAL (0<<1) + #define PM3VideoOverlayMode_BUFFERSYNC_VIDEOSTREAMA (1<<1) + #define PM3VideoOverlayMode_BUFFERSYNC_VIDEOSTREAMB (2<<1) + #define PM3VideoOverlayMode_FIELDPOLARITY_NORMAL (0<<4) + #define PM3VideoOverlayMode_FIELDPOLARITY_INVERT (1<<4) + #define PM3VideoOverlayMode_PIXELSIZE_8BIT (0<<5) + #define PM3VideoOverlayMode_PIXELSIZE_16BIT (1<<5) + #define PM3VideoOverlayMode_PIXELSIZE_32BIT (2<<5) + #define PM3VideoOverlayMode_COLORFORMAT_RGB8888 ((0<<7)|(1<<12)|(2<<5)) + #define PM3VideoOverlayMode_COLORFORMAT_RGB4444 ((1<<7)|(1<<12)|(1<<5)) + #define PM3VideoOverlayMode_COLORFORMAT_RGB5551 ((2<<7)|(1<<12)|(1<<5)) + #define PM3VideoOverlayMode_COLORFORMAT_RGB565 ((3<<7)|(1<<12)|(1<<5)) + #define PM3VideoOverlayMode_COLORFORMAT_RGB332 ((4<<7)|(1<<12)|(0<<5)) + #define PM3VideoOverlayMode_COLORFORMAT_BGR8888 ((0<<7)|(2<<5)) + #define PM3VideoOverlayMode_COLORFORMAT_BGR4444 ((1<<7)|(1<<5)) + #define PM3VideoOverlayMode_COLORFORMAT_BGR5551 ((2<<7)|(1<<5)) + #define PM3VideoOverlayMode_COLORFORMAT_BGR565 ((3<<7)|(1<<5)) + #define PM3VideoOverlayMode_COLORFORMAT_BGR332 ((4<<7)|(0<<5)) + #define PM3VideoOverlayMode_COLORFORMAT_CI8 ((5<<7)|(1<<12)|(0<<5)) + #define PM3VideoOverlayMode_COLORFORMAT_VUY444 ((2<<10)|(1<<12)|(2<<5)) + #define PM3VideoOverlayMode_COLORFORMAT_YUV444 ((2<<10)|(2<<5)) + #define PM3VideoOverlayMode_COLORFORMAT_VUY422 ((1<<10)|(1<<12)|(1<<5)) + #define PM3VideoOverlayMode_COLORFORMAT_YUV422 ((1<<10)|(1<<5)) + #define PM3VideoOverlayMode_COLORORDER_BGR (0<<12) + #define PM3VideoOverlayMode_COLORORDER_RGB (1<<12) + #define PM3VideoOverlayMode_LINEARCOLOREXT_OFF (0<<13) + #define PM3VideoOverlayMode_LINEARCOLOREXT_ON (1<<13) + #define PM3VideoOverlayMode_FILTER_MASK (3<<14) + #define PM3VideoOverlayMode_FILTER_OFF (0<<14) + #define PM3VideoOverlayMode_FILTER_FULL (1<<14) + #define PM3VideoOverlayMode_FILTER_PARTIAL (2<<14) + #define PM3VideoOverlayMode_DEINTERLACE_OFF (0<<16) + #define PM3VideoOverlayMode_DEINTERLACE_BOB (1<<16) + #define PM3VideoOverlayMode_PATCHMODE_OFF (0<<18) + #define PM3VideoOverlayMode_PATCHMODE_ON (1<<18) + #define PM3VideoOverlayMode_FLIP_VIDEO (0<<20) + #define PM3VideoOverlayMode_FLIP_VIDEOSTREAMA (1<<20) + #define PM3VideoOverlayMode_FLIP_VIDEOSTREAMB (2<<20) + #define PM3VideoOverlayMode_MIRROR_MASK (3<<23) + #define PM3VideoOverlayMode_MIRRORX_OFF (0<<23) + #define PM3VideoOverlayMode_MIRRORX_ON (1<<23) + #define PM3VideoOverlayMode_MIRRORY_OFF (0<<24) + #define PM3VideoOverlayMode_MIRRORY_ON (1<<24) +#define PM3VideoOverlayFifoControl 0x3110 +#define PM3VideoOverlayIndex 0x3118 +#define PM3VideoOverlayBase 0x3120 +#define PM3VideoOverlayBase0 0x3120 +#define PM3VideoOverlayBase1 0x3128 +#define PM3VideoOverlayBase2 0x3130 +#define PM3VideoOverlayStride 0x3138 + #define PM3VideoOverlayStride_STRIDE(s) (((s)&0xfff)<<0) +#define PM3VideoOverlayWidth 0x3140 + #define PM3VideoOverlayWidth_WIDTH(w) (((w)&0xfff)<<0) +#define PM3VideoOverlayHeight 0x3148 + #define PM3VideoOverlayHeight_HEIGHT(h) (((h)&0xfff)<<0) +#define PM3VideoOverlayOrigin 0x3150 + #define PM3VideoOverlayOrigin_XORIGIN(x) (((x)&0xfff)<<0) + #define PM3VideoOverlayOrigin_YORIGIN(y) (((y)&0xfff)<<16) +#define PM3VideoOverlayShrinkXDelta 0x3158 + #define PM3VideoOverlayShrinkXDelta_NONE (1<<16) + #define PM3VideoOverlayShrinkXDelta_DELTA(s,d) \ + ((((s)<<16)/(d))&0x0ffffff0) +#define PM3VideoOverlayZoomXDelta 0x3160 + #define PM3VideoOverlayZoomXDelta_NONE (1<<16) + #define PM3VideoOverlayZoomXDelta_DELTA(s,d) \ + ((((s)<<16)/(d))&0x0001fff0) +#define PM3VideoOverlayYDelta 0x3168 + #define PM3VideoOverlayYDelta_NONE (1<<16) + #define PM3VideoOverlayYDelta_DELTA(s,d) \ + ((((s)<<16)/(d))&0x0ffffff0) +#define PM3VideoOverlayFieldOffset 0x3170 +#define PM3VideoOverlayStatus 0x3178 + +/********************************************** +* GLINT Permedia3 RAMDAC Registers (0x4000) * +***********************************************/ +/* Direct Registers */ +#define PM3RD_PaletteWriteAddress 0x4000 +#define PM3RD_PaletteData 0x4008 +#define PM3RD_PixelMask 0x4010 +#define PM3RD_PaletteReadAddress 0x4018 + +#define PM3RD_IndexLow 0x4020 +#define PM3RD_IndexHigh 0x4028 +#define PM3RD_IndexedData 0x4030 +#define PM3RD_IndexControl 0x4038 + #define PM3RD_IndexControl_AUTOINCREMENT_ENABLE (1<<0) + #define PM3RD_IndexControl_AUTOINCREMENT_DISABLE (0<<0) + +/* Indirect Registers */ +#define PM3RD_MiscControl 0x000 + #define PM3RD_MiscControl_HIGHCOLOR_RES_DISABLE (0<<0) + #define PM3RD_MiscControl_HIGHCOLOR_RES_ENABLE (1<<0) + #define PM3RD_MiscControl_PIXELDOUBLE_DISABLE (0<<1) + #define PM3RD_MiscControl_PIXELDOUBLE_ENABLE (1<<1) + #define PM3RD_MiscControl_LASTREAD_ADDR_DISABLE (0<<2) + #define PM3RD_MiscControl_LASTREAD_ADDR_ENABLE (1<<2) + #define PM3RD_MiscControl_DIRECTCOLOR_DISABLE (0<<3) + #define PM3RD_MiscControl_DIRECTCOLOR_ENABLE (1<<3) + #define PM3RD_MiscControl_OVERLAY_DISABLE (0<<4) + #define PM3RD_MiscControl_OVERLAY_ENABLE (1<<4) + #define PM3RD_MiscControl_PIXELDOUBLE_BUFFER_DISABLE (0<<5) + #define PM3RD_MiscControl_PIXELDOUBLE_BUFFER_ENABLE (1<<5) + #define PM3RD_MiscControl_VSB_OUTPUT_DISABLE (0<<6) + #define PM3RD_MiscControl_VSB_OUTPUT_ENABLE (1<<6) + #define PM3RD_MiscControl_STEREODOUBLE_BUFFER_DISABLE (0<<7) + #define PM3RD_MiscControl_STEREODOUBLE_BUFFER_ENABLE (1<<7) +#define PM3RD_SyncControl 0x001 + #define PM3RD_SyncControl_HSYNC_ACTIVE_LOW (0<<0) + #define PM3RD_SyncControl_HSYNC_ACTIVE_HIGH (1<<0) + #define PM3RD_SyncControl_HSYNC_FORCE_ACTIVE (3<<0) + #define PM3RD_SyncControl_HSYNC_FORCE_INACTIVE (4<<0) + #define PM3RD_SyncControl_HSYNC_TRI_STATE (2<<0) + #define PM3RD_SyncControl_VSYNC_ACTIVE_LOW (0<<3) + #define PM3RD_SyncControl_VSYNC_ACTIVE_HIGH (1<<3) + #define PM3RD_SyncControl_VSYNC_TRI_STATE (2<<3) + #define PM3RD_SyncControl_VSYNC_FORCE_ACTIVE (3<<3) + #define PM3RD_SyncControl_VSYNC_FORCE_INACTIVE (4<<3) + #define PM3RD_SyncControl_HSYNC_OVERRIDE_SETBY_HSYNC (0<<6) + #define PM3RD_SyncControl_HSYNC_OVERRIDE_FORCE_HIGH (1<<6) + #define PM3RD_SyncControl_VSYNC_OVERRIDE_SETBY_VSYNC (0<<7) + #define PM3RD_SyncControl_VSYNC_OVERRIDE_FORCE_HIGH (1<<7) +#define PM3RD_DACControl 0x002 + #define PM3RD_DACControl_DAC_POWER_ON (0<<0) + #define PM3RD_DACControl_DAC_POWER_OFF (1<<0) + #define PM3RD_DACControl_SYNC_ON_GREEN_DISABLE (0<<3) + #define PM3RD_DACControl_SYNC_ON_GREEN_ENABLE (1<<3) + #define PM3RD_DACControl_BLANK_RED_DAC_DISABLE (0<<4) + #define PM3RD_DACControl_BLANK_RED_DAC_ENABLE (1<<4) + #define PM3RD_DACControl_BLANK_GREEN_DAC_DISABLE (0<<5) + #define PM3RD_DACControl_BLANK_GREEN_DAC_ENABLE (1<<5) + #define PM3RD_DACControl_BLANK_BLUE_DAC_DISABLE (0<<6) + #define PM3RD_DACControl_BLANK_BLUE_DAC_ENABLE (1<<6) + #define PM3RD_DACControl_BLANK_PEDESTAL_DISABLE (0<<7) + #define PM3RD_DACControl_BLANK_PEDESTAL_ENABLE (1<<7) +#define PM3RD_PixelSize 0x003 + #define PM3RD_PixelSize_24_BIT_PIXELS (4<<0) + #define PM3RD_PixelSize_32_BIT_PIXELS (2<<0) + #define PM3RD_PixelSize_16_BIT_PIXELS (1<<0) + #define PM3RD_PixelSize_8_BIT_PIXELS (0<<0) +#define PM3RD_ColorFormat 0x004 + #define PM3RD_ColorFormat_LINEAR_COLOR_EXT_ENABLE (1<<6) + #define PM3RD_ColorFormat_LINEAR_COLOR_EXT_DISABLE (0<<6) + #define PM3RD_ColorFormat_COLOR_ORDER_BLUE_LOW (1<<5) + #define PM3RD_ColorFormat_COLOR_ORDER_RED_LOW (0<<5) + #define PM3RD_ColorFormat_COLOR_FORMAT_MASK (0x1f<<0) + #define PM3RD_ColorFormat_8888_COLOR (0<<0) + #define PM3RD_ColorFormat_5551_FRONT_COLOR (1<<0) + #define PM3RD_ColorFormat_4444_COLOR (2<<0) + #define PM3RD_ColorFormat_332_FRONT_COLOR (5<<0) + #define PM3RD_ColorFormat_332_BACK_COLOR (6<<0) + #define PM3RD_ColorFormat_2321_FRONT_COLOR (9<<0) + #define PM3RD_ColorFormat_2321_BACK_COLOR (10<<0) + #define PM3RD_ColorFormat_232_FRONTOFF_COLOR (11<<0) + #define PM3RD_ColorFormat_232_BACKOFF_COLOR (12<<0) + #define PM3RD_ColorFormat_5551_BACK_COLOR (13<<0) + #define PM3RD_ColorFormat_CI8_COLOR (14<<0) + #define PM3RD_ColorFormat_565_FRONT_COLOR (16<<0) + #define PM3RD_ColorFormat_565_BACK_COLOR (17<<0) +#define PM3RD_CursorMode 0x005 + #define PM3RD_CursorMode_CURSOR_DISABLE (0<<0) + #define PM3RD_CursorMode_CURSOR_ENABLE (1<<0) + #define PM3RD_CursorMode_FORMAT_64x64_2BPE_P0123 (0<<2) + #define PM3RD_CursorMode_FORMAT_32x32_2BPE_P0 (1<<2) + #define PM3RD_CursorMode_FORMAT_32x32_2BPE_P1 (2<<2) + #define PM3RD_CursorMode_FORMAT_32x32_2BPE_P2 (3<<2) + #define PM3RD_CursorMode_FORMAT_32x32_2BPE_P3 (4<<2) + #define PM3RD_CursorMode_FORMAT_32x32_4BPE_P01 (5<<2) + #define PM3RD_CursorMode_FORMAT_32x32_4BPE_P23 (6<<2) + #define PM3RD_CursorMode_TYPE_MS (0<<4) + #define PM3RD_CursorMode_TYPE_X (1<<4) + #define PM3RD_CursorMode_REVERSE_PIXEL_ORDER_DISABLE (0<<6) + #define PM3RD_CursorMode_REVERSE_PIXEL_ORDER_ENABLE (1<<6) + #define PM3RD_CursorMode_REVERSE_PIXEL_ORDER_3_COLOR (2<<6) + #define PM3RD_CursorMode_REVERSE_PIXEL_ORDER_15_COLOR (3<<6) +#define PM3RD_CursorControl 0x006 + #define PM3RD_CursorControl_DOUBLE_X_DISABLED (0<<0) + #define PM3RD_CursorControl_DOUBLE_X_ENABLED (1<<0) + #define PM3RD_CursorControl_DOUBLE_Y_DISABLED (0<<1) + #define PM3RD_CursorControl_DOUBLE_Y_ENABLED (1<<1) + #define PM3RD_CursorControl_READBACK_POS_DISABLED (0<<2) + #define PM3RD_CursorControl_READBACK_POS_ENABLED (1<<2) + +#define PM3RD_CursorXLow 0x007 +#define PM3RD_CursorXHigh 0x008 +#define PM3RD_CursorYLow 0x009 +#define PM3RD_CursorYHigh 0x00a +#define PM3RD_CursorHotSpotX 0x00b +#define PM3RD_CursorHotSpotY 0x00c +#define PM3RD_OverlayKey 0x00d +#define PM3RD_Pan 0x00e + #define PM3RD_Pan_DISABLE (0<<0) + #define PM3RD_Pan_ENABLE (1<<0) + #define PM3RD_Pan_GATE_DISABLE (0<<1) + #define PM3RD_Pan_GATE_ENABLE (1<<1) +#define PM3RD_Sense 0x00f + +#define PM3RD_CheckControl 0x018 + #define PM3RD_CheckControl_PIXEL_DISABLED (0<<0) + #define PM3RD_CheckControl_PIXEL_ENABLED (1<<0) + #define PM3RD_CheckControl_LUT_DISABLED (0<<1) + #define PM3RD_CheckControl_LUT_ENABLED (1<<1) +#define PM3RD_CheckPixelRed 0x019 +#define PM3RD_CheckPixelGreen 0x01a +#define PM3RD_CheckPixelBlue 0x01b +#define PM3RD_CheckLUTRed 0x01c +#define PM3RD_CheckLUTGreen 0x01d +#define PM3RD_CheckLUTBlue 0x01e +#define PM3RD_Scratch 0x01f + +#define PM3RD_VideoOverlayControl 0x020 + #define PM3RD_VideoOverlayControl_DISABLE (0<<0) + #define PM3RD_VideoOverlayControl_ENABLE (1<<0) + #define PM3RD_VideoOverlayControl_MODE_MASK (3<<1) + #define PM3RD_VideoOverlayControl_MODE_MAINKEY (0<<1) + #define PM3RD_VideoOverlayControl_MODE_OVERLAYKEY (1<<1) + #define PM3RD_VideoOverlayControl_MODE_ALWAYS (2<<1) + #define PM3RD_VideoOverlayControl_MODE_BLEND (3<<1) + #define PM3RD_VideoOverlayControl_DIRECTCOLOR_DISABLED (0<<3) + #define PM3RD_VideoOverlayControl_DIRECTCOLOR_ENABLED (1<<3) + #define PM3RD_VideoOverlayControl_BLENDSRC_MAIN (0<<4) + #define PM3RD_VideoOverlayControl_BLENDSRC_REGISTER (1<<4) + #define PM3RD_VideoOverlayControl_KEY_COLOR (0<<5) + #define PM3RD_VideoOverlayControl_KEY_ALPHA (1<<5) +#define PM3RD_VideoOverlayXStartLow 0x021 +#define PM3RD_VideoOverlayXStartHigh 0x022 +#define PM3RD_VideoOverlayYStartLow 0x023 +#define PM3RD_VideoOverlayYStartHigh 0x024 +#define PM3RD_VideoOverlayXEndLow 0x025 +#define PM3RD_VideoOverlayXEndHigh 0x026 +#define PM3RD_VideoOverlayYEndLow 0x027 +#define PM3RD_VideoOverlayYEndHigh 0x028 +#define PM3RD_VideoOverlayKeyR 0x029 +#define PM3RD_VideoOverlayKeyG 0x02a +#define PM3RD_VideoOverlayKeyB 0x02b +#define PM3RD_VideoOverlayBlend 0x02c + #define PM3RD_VideoOverlayBlend_FACTOR_0_PERCENT (0<<6) + #define PM3RD_VideoOverlayBlend_FACTOR_25_PERCENT (1<<6) + #define PM3RD_VideoOverlayBlend_FACTOR_75_PERCENT (2<<6) + #define PM3RD_VideoOverlayBlend_FACTOR_100_PERCENT (3<<6) + +#define PM3RD_DClkSetup1 0x1f0 +#define PM3RD_DClkSetup2 0x1f1 +#define PM3RD_KClkSetup1 0x1f2 +#define PM3RD_KClkSetup2 0x1f3 + +#define PM3RD_DClkControl 0x200 + #define PM3RD_DClkControl_SOURCE_PLL (0<<4) + #define PM3RD_DClkControl_SOURCE_VSA (1<<4) + #define PM3RD_DClkControl_SOURCE_VSB (2<<4) + #define PM3RD_DClkControl_SOURCE_EXT (3<<4) + #define PM3RD_DClkControl_STATE_RUN (2<<2) + #define PM3RD_DClkControl_STATE_HIGH (1<<2) + #define PM3RD_DClkControl_STATE_LOW (0<<2) + #define PM3RD_DClkControl_LOCKED (1<<1) + #define PM3RD_DClkControl_NOT_LOCKED (0<<1) + #define PM3RD_DClkControl_ENABLE (1<<0) + #define PM3RD_DClkControl_DISABLE (0<<0) +#define PM3RD_DClk0PreScale 0x201 +#define PM3RD_DClk0FeedbackScale 0x202 +#define PM3RD_DClk0PostScale 0x203 +#define PM3RD_DClk1PreScale 0x204 +#define PM3RD_DClk1FeedbackScale 0x205 +#define PM3RD_DClk1PostScale 0x206 +#define PM3RD_DClk2PreScale 0x207 +#define PM3RD_DClk2FeedbackScale 0x208 +#define PM3RD_DClk2PostScale 0x209 +#define PM3RD_DClk3PreScale 0x20a +#define PM3RD_DClk3FeedbackScale 0x20b +#define PM3RD_DClk3PostScale 0x20c +#define PM3RD_KClkControl 0x20d + #define PM3RD_KClkControl_DISABLE (0<<0) + #define PM3RD_KClkControl_ENABLE (1<<0) + #define PM3RD_KClkControl_NOT_LOCKED (0<<1) + #define PM3RD_KClkControl_LOCKED (1<<1) + #define PM3RD_KClkControl_STATE_LOW (0<<2) + #define PM3RD_KClkControl_STATE_HIGH (1<<2) + #define PM3RD_KClkControl_STATE_RUN (2<<2) + #define PM3RD_KClkControl_STATE_LOW_POWER (3<<2) + #define PM3RD_KClkControl_SOURCE_PCLK (0<<4) + #define PM3RD_KClkControl_SOURCE_HALF_PCLK (1<<4) + #define PM3RD_KClkControl_SOURCE_PLL (2<<4) +#define PM3RD_KClkPreScale 0x20e +#define PM3RD_KClkFeedbackScale 0x20f +#define PM3RD_KClkPostScale 0x210 +#define PM3RD_MClkControl 0x211 + #define PM3RD_MClkControl_DISABLE (0<<0) + #define PM3RD_MClkControl_ENABLE (1<<0) + #define PM3RD_MClkControl_NOT_LOCKED (0<<1) + #define PM3RD_MClkControl_LOCKED (1<<1) + #define PM3RD_MClkControl_STATE_LOW (0<<2) + #define PM3RD_MClkControl_STATE_HIGH (1<<2) + #define PM3RD_MClkControl_STATE_RUN (2<<2) + #define PM3RD_MClkControl_STATE_LOW_POWER (3<<2) + #define PM3RD_MClkControl_SOURCE_PCLK (0<<4) + #define PM3RD_MClkControl_SOURCE_HALF_PCLK (1<<4) + #define PM3RD_MClkControl_SOURCE_HALF_EXT (3<<4) + #define PM3RD_MClkControl_SOURCE_EXT (4<<4) + #define PM3RD_MClkControl_SOURCE_HALF_KCLK (5<<4) + #define PM3RD_MClkControl_SOURCE_KCLK (6<<4) +#define PM3RD_MClkPreScale 0x212 +#define PM3RD_MClkFeedbackScale 0x213 +#define PM3RD_MClkPostScale 0x214 +#define PM3RD_SClkControl 0x215 + #define PM3RD_SClkControl_DISABLE (0<<0) + #define PM3RD_SClkControl_ENABLE (1<<0) + #define PM3RD_SClkControl_NOT_LOCKED (0<<1) + #define PM3RD_SClkControl_LOCKED (1<<1) + #define PM3RD_SClkControl_STATE_LOW (0<<2) + #define PM3RD_SClkControl_STATE_HIGH (1<<2) + #define PM3RD_SClkControl_STATE_RUN (2<<2) + #define PM3RD_SClkControl_STATE_LOW_POWER (3<<2) + #define PM3RD_SClkControl_SOURCE_PCLK (0<<4) + #define PM3RD_SClkControl_SOURCE_HALF_PCLK (1<<4) + #define PM3RD_SClkControl_SOURCE_HALF_EXT (3<<4) + #define PM3RD_SClkControl_SOURCE_EXT (4<<4) + #define PM3RD_SClkControl_SOURCE_HALF_KCLK (5<<4) + #define PM3RD_SClkControl_SOURCE_KCLK (6<<4) +#define PM3RD_SClkPreScale 0x216 +#define PM3RD_SClkFeedbackScale 0x217 +#define PM3RD_SClkPostScale 0x218 + +#define PM3RD_CursorPalette(p) (0x303+(p)) +#define PM3RD_CursorPattern(p) (0x400+(p)) +/****************************************************** +* GLINT Permedia3 Video Streaming Registers (0x5000) * +*******************************************************/ + +#define PM3VSConfiguration 0x5800 + +/********************************************** +* GLINT Permedia3 Core Registers (0x8000+) * +***********************************************/ +#define PM3AALineWidth 0x94c0 +#define PM3AAPointsize 0x94a0 +#define PM3AlphaBlendAlphaMode 0xafa8 +#define PM3AlphaBlendAlphaModeAnd 0xad30 +#define PM3AlphaBlendAlphaModeOr 0xad38 +#define PM3AlphaBlendColorMode 0xafa0 +#define PM3AlphaBlendColorModeAnd 0xacb0 +#define PM3AlphaBlendColorModeOr 0xacb8 +#define PM3AlphaDestColor 0xaf88 +#define PM3AlphaSourceColor 0xaf80 +#define PM3AlphaTestMode 0x8800 +#define PM3AlphaTestModeAnd 0xabf0 +#define PM3AlphaTestModeOr 0xabf8 +#define PM3AntialiasMode 0x8808 +#define PM3AntialiasModeAnd 0xac00 +#define PM3AntialiasModeOr 0xac08 +#define PM3AreaStippleMode 0x81a0 +/* ... */ +#define PM3BackgroundColor 0xb0c8 +#define PM3BasePageOfWorkingSet 0xb4c8 +/* ... */ +#define PM3ChromaTestMode 0x8f18 +/* ... */ +#define PM3ColorDDAMode 0x87e0 +#define PM3ColorDDAModeAnd 0xabe0 +#define PM3ColorDDAModeOr 0xabe8 +#define PM3CommandInterrupt 0xa990 +#define PM3ConstantColorDDA 0xafb0 + #define PM3ConstantColorDDA_R(r) ((r)&0xff) + #define PM3ConstantColorDDA_G(g) (((g)&0xff)<<8) + #define PM3ConstantColorDDA_B(b) (((b)&0xff)<<16) + #define PM3ConstantColorDDA_A(a) (((a)&0xff)<<24) +#define PM3ContextData 0x8dd0 +#define PM3ContextDump 0x8dc0 +#define PM3ContextRestore 0x8dc8 +#define PM3Continue 0x8058 +#define PM3ContinueNewDom 0x8048 +#define PM3ContinueNewLine 0x8040 +#define PM3ContinueNewSub 0x8050 +#define PM3Count 0x8030 +/* ... */ +#define PM3DeltaControl 0x9350 +#define PM3DeltaControlAnd 0xab20 +#define PM3DeltaControlOr 0xab28 +#define PM3DeltaMode 0x9300 +#define PM3DeltaModeAnd 0xaad0 +#define PM3DeltaModeOr 0xaad8 + +#define PM3DepthMode 0x89a0 +/* ... */ +#define PM3DitherMode 0x8818 +#define PM3DitherModeAnd 0xacd0 +#define PM3DitherModeOr 0xacd8 +/* ... */ +#define PM3DMARectangleRead 0xa9a8 + #define PM3DMARectangleRead_Width(w) (w&0xfff) + #define PM3DMARectangleRead_Height(h) ((h&0xfff)<<12) + #define PM3DMARectangleRead_PixelSize(s) ((s&0x3)<<24) + #define PM3DMARectangleRead_Pack (1<<26) + #define PM3DMARectangleRead_ByteSwap(b) ((b&0x3)<<27) + #define PM3DMARectangleRead_Alignment (1<<30) +#define PM3DMARectangleReadAddress 0xa9b0 +#define PM3DMARectangleReadLinePitch 0xa9b8 +#define PM3DMARectangleReadTarget 0xa9c0 +/* ... */ +#define PM3DownloadAddress 0xb0d0 +#define PM3DownloadData 0xb0d8 +/* ... */ +#define PM3dBdx 0x87b8 +#define PM3dBdyDom 0x87c0 +#define PM3dGdx 0x87a0 +#define PM3dGdyDom 0x87a8 +#define PM3dQdx 0x83c0 +#define PM3dQdyDom 0x83c8 +#define PM3dRdx 0x8788 +#define PM3dRdyDom 0x8790 +#define PM3dSdx 0x8390 +#define PM3dSdy 0x83d8 +#define PM3dSdyDom 0x8398 +#define PM3dTdx 0x83a8 +#define PM3dTdy 0x83e0 +#define PM3dTdyDom 0x83b0 +#define PM3dXDom 0x8008 +#define PM3dXSub 0x8018 +#define PM3dY 0x8028 +/* ... */ +#define PM3FBBlockColor 0x8ac8 +#define PM3FBBlockColor0 0xb060 +#define PM3FBBlockColor1 0xb068 +#define PM3FBBlockColor2 0xb070 +#define PM3FBBlockColor3 0xb078 +#define PM3FBBlockColorBack 0xb0a0 +#define PM3FBBlockColorBack0 0xb080 +#define PM3FBBlockColorBack1 0xb088 +#define PM3FBBlockColorBack2 0xb090 +#define PM3FBBlockColorBack3 0xb098 +#define PM3FBColor 0x8a98 +#define PM3FBDestReadBufferAddr0 0xae80 +#define PM3FBDestReadBufferAddr1 0xae88 +#define PM3FBDestReadBufferAddr2 0xae90 +#define PM3FBDestReadBufferAddr3 0xae98 +#define PM3FBDestReadBufferOffset0 0xaea0 +#define PM3FBDestReadBufferOffset1 0xaea8 +#define PM3FBDestReadBufferOffset2 0xaeb0 +#define PM3FBDestReadBufferOffset3 0xaeb8 + #define PM3FBDestReadBufferOffset_XOffset(x) ((x)&0xffff) + #define PM3FBDestReadBufferOffset_YOffset(y) (((y)&0xffff)<<16) +#define PM3FBDestReadBufferWidth0 0xaec0 +#define PM3FBDestReadBufferWidth1 0xaec8 +#define PM3FBDestReadBufferWidth2 0xaed0 +#define PM3FBDestReadBufferWidth3 0xaed8 + #define PM3FBDestReadBufferWidth_Width(w) ((w)&0x0fff) + +#define PM3FBDestReadEnables 0xaee8 +#define PM3FBDestReadEnablesAnd 0xad20 +#define PM3FBDestReadEnablesOr 0xad28 + #define PM3FBDestReadEnables_E(e) ((e)&0xff) + #define PM3FBDestReadEnables_E0 (1<<0) + #define PM3FBDestReadEnables_E1 (1<<1) + #define PM3FBDestReadEnables_E2 (1<<2) + #define PM3FBDestReadEnables_E3 (1<<3) + #define PM3FBDestReadEnables_E4 (1<<4) + #define PM3FBDestReadEnables_E5 (1<<5) + #define PM3FBDestReadEnables_E6 (1<<6) + #define PM3FBDestReadEnables_E7 (1<<7) + #define PM3FBDestReadEnables_R(r) (((r)&0xff)<<8) + #define PM3FBDestReadEnables_R0 (1<<8) + #define PM3FBDestReadEnables_R1 (1<<9) + #define PM3FBDestReadEnables_R2 (1<<10) + #define PM3FBDestReadEnables_R3 (1<<11) + #define PM3FBDestReadEnables_R4 (1<<12) + #define PM3FBDestReadEnables_R5 (1<<13) + #define PM3FBDestReadEnables_R6 (1<<14) + #define PM3FBDestReadEnables_R7 (1<<15) + #define PM3FBDestReadEnables_ReferenceAlpha(a) (((a)&0xff)<<24) + +#define PM3FBDestReadMode 0xaee0 +#define PM3FBDestReadModeAnd 0xac90 +#define PM3FBDestReadModeOr 0xac98 + #define PM3FBDestReadMode_ReadDisable (0<<0) + #define PM3FBDestReadMode_ReadEnable (1<<0) + #define PM3FBDestReadMode_StripePitch(sp) (((sp)&0x7)<<2) + #define PM3FBDestReadMode_StripeHeight(sh) (((sh)&0x7)<<7) + #define PM3FBDestReadMode_Enable0 (1<<8) + #define PM3FBDestReadMode_Enable1 (1<<9) + #define PM3FBDestReadMode_Enable2 (1<<10) + #define PM3FBDestReadMode_Enable3 (1<<11) + #define PM3FBDestReadMode_Layout0(l) (((l)&0x3)<<12) + #define PM3FBDestReadMode_Layout1(l) (((l)&0x3)<<14) + #define PM3FBDestReadMode_Layout2(l) (((l)&0x3)<<16) + #define PM3FBDestReadMode_Layout3(l) (((l)&0x3)<<18) + #define PM3FBDestReadMode_Origin0 (1<<20) + #define PM3FBDestReadMode_Origin1 (1<<21) + #define PM3FBDestReadMode_Origin2 (1<<22) + #define PM3FBDestReadMode_Origin3 (1<<23) + #define PM3FBDestReadMode_Blocking (1<<24) + #define PM3FBDestReadMode_UseReadEnabled (1<<26) + #define PM3FBDestReadMode_AlphaFiltering (1<<27) + +#define PM3FBHardwareWriteMask 0x8ac0 +#define PM3FBSoftwareWriteMask 0x8820 +#define PM3FBData 0x8aa0 +#define PM3FBSourceData 0x8aa8 +#define PM3FBSourceReadBufferAddr 0xaf08 +#define PM3FBSourceReadBufferOffset 0xaf10 + #define PM3FBSourceReadBufferOffset_XOffset(x) ((x)&0xffff) + #define PM3FBSourceReadBufferOffset_YOffset(y) (((y)&0xffff)<<16) +#define PM3FBSourceReadBufferWidth 0xaf18 + #define PM3FBSourceReadBufferWidth_Width(w) ((w)&0x0fff) +#define PM3FBSourceReadMode 0xaf00 +#define PM3FBSourceReadModeAnd 0xaca0 +#define PM3FBSourceReadModeOr 0xaca8 + #define PM3FBSourceReadMode_ReadDisable (0<<0) + #define PM3FBSourceReadMode_ReadEnable (1<<0) + #define PM3FBSourceReadMode_StripePitch(sp) (((sp)&0x7)<<2) + #define PM3FBSourceReadMode_StripeHeight(sh) (((sh)&0x7)<<7) + #define PM3FBSourceReadMode_Layout(l) (((l)&0x3)<<8) + #define PM3FBSourceReadMode_Origin (1<<10) + #define PM3FBSourceReadMode_Blocking (1<<11) + #define PM3FBSourceReadMode_UseTexelCoord (1<<13) + #define PM3FBSourceReadMode_WrapXEnable (1<<14) + #define PM3FBSourceReadMode_WrapYEnable (1<<15) + #define PM3FBSourceReadMode_WrapX(w) (((w)&0xf)<<16) + #define PM3FBSourceReadMode_WrapY(w) (((w)&0xf)<<20) + #define PM3FBSourceReadMode_ExternalSourceData (1<<24) +#define PM3FBWriteBufferAddr0 0xb000 +#define PM3FBWriteBufferAddr1 0xb008 +#define PM3FBWriteBufferAddr2 0xb010 +#define PM3FBWriteBufferAddr3 0xb018 + +#define PM3FBWriteBufferOffset0 0xb020 +#define PM3FBWriteBufferOffset1 0xb028 +#define PM3FBWriteBufferOffset2 0xb030 +#define PM3FBWriteBufferOffset3 0xb038 + #define PM3FBWriteBufferOffset_XOffset(x) ((x)&0xffff) + #define PM3FBWriteBufferOffset_YOffset(y) (((y)&0xffff)<<16) + +#define PM3FBWriteBufferWidth0 0xb040 +#define PM3FBWriteBufferWidth1 0xb048 +#define PM3FBWriteBufferWidth2 0xb050 +#define PM3FBWriteBufferWidth3 0xb058 + #define PM3FBWriteBufferWidth_Width(w) ((w)&0x0fff) + +#define PM3FBWriteMode 0x8ab8 +#define PM3FBWriteModeAnd 0xacf0 +#define PM3FBWriteModeOr 0xacf8 + #define PM3FBWriteMode_WriteDisable 0<<0 + #define PM3FBWriteMode_WriteEnable 1<<0 + #define PM3FBWriteMode_Replicate 1<<4 + #define PM3FBWriteMode_OpaqueSpan 1<<5 + #define PM3FBWriteMode_StripePitch(p) (((p)&0x7)<<6) + #define PM3FBWriteMode_StripeHeight(h) (((h)&0x7)<<9) + #define PM3FBWriteMode_Enable0 1<<12 + #define PM3FBWriteMode_Enable1 1<<13 + #define PM3FBWriteMode_Enable2 1<<14 + #define PM3FBWriteMode_Enable3 1<<15 + #define PM3FBWriteMode_Layout0(l) (((l)&0x3)<<16) + #define PM3FBWriteMode_Layout1(l) (((l)&0x3)<<18) + #define PM3FBWriteMode_Layout2(l) (((l)&0x3)<<20) + #define PM3FBWriteMode_Layout3(l) (((l)&0x3)<<22) + #define PM3FBWriteMode_Origin0 1<<24 + #define PM3FBWriteMode_Origin1 1<<25 + #define PM3FBWriteMode_Origin2 1<<26 + #define PM3FBWriteMode_Origin3 1<<27 + +#define PM3FogMode 0x8690 +#define PM3ForegroundColor 0xb0c0 +/* ... */ +#define PM3GIDMode 0xb538 +#define PM3GIDModeAnd 0xb5b0 +#define PM3GIDModeOr 0xb5b8 +/* ... */ +#define PM3HeadPhysicalPageAllocation0 0xb480 +#define PM3HeadPhysicalPageAllocation1 0xb488 +#define PM3HeadPhysicalPageAllocation2 0xb490 +#define PM3HeadPhysicalPageAllocation3 0xb498 +/* ... */ +#define PM3LBDestReadBufferAddr 0xb510 +#define PM3LBDestReadBufferOffset 0xb518 +#define PM3LBDestReadEnables 0xb508 +#define PM3LBDestReadEnablesAnd 0xb590 +#define PM3LBDestReadEnablesOr 0xb598 +#define PM3LBDestReadMode 0xb500 +#define PM3LBDestReadModeAnd 0xb580 +#define PM3LBDestReadModeOr 0xb588 + #define PM3LBDestReadMode_Disable (0<<0) + #define PM3LBDestReadMode_Enable (1<<0) + #define PM3LBDestReadMode_StripePitch(p) (((p)&0x7)<<2) + #define PM3LBDestReadMode_StripeHeight(h) (((h)&0x7)<<5) + #define PM3LBDestReadMode_Layout (1<<8) + #define PM3LBDestReadMode_Origin (1<<9) + #define PM3LBDestReadMode_UserReadEnables (1<<10) + #define PM3LBDestReadMode_Packed16 (1<<11) + #define PM3LBDestReadMode_Width(w) (((w)&0xfff)<<12) +#define PM3LBReadFormat 0x8888 + #define PM3LBReadFormat_DepthWidth(w) (((w)&0x3)<<0) + #define PM3LBReadFormat_StencilWidth(w) (((w)&0xf)<<2) + #define PM3LBReadFormat_StencilPosition(p) (((p)&0x1f)<<6) + #define PM3LBReadFormat_FCPWidth(w) (((w)&0xf)<<11) + #define PM3LBReadFormat_FCPPosition(p) (((p)&0x1f)<<15) + #define PM3LBReadFormat_GIDWidth(w) (((w)&0x7)<<20) + #define PM3LBReadFormat_GIDPosition(p) (((p)&0x1f)<<23) +#define PM3LBSourceReadBufferAddr 0xb528 +#define PM3LBSourceReadBufferOffset 0xb530 +#define PM3LBSourceReadMode 0xb520 +#define PM3LBSourceReadModeAnd 0xb5a0 +#define PM3LBSourceReadModeOr 0xb5a8 + #define PM3LBSourceReadMode_Enable (1<<0) + #define PM3LBSourceReadMode_StripePitch(p) (((p)&0x7)<<2) + #define PM3LBSourceReadMode_StripeHeight(h) (((h)&0x7)<<5) + #define PM3LBSourceReadMode_Layout (1<<8) + #define PM3LBSourceReadMode_Origin (1<<9) + #define PM3LBSourceReadMode_Packed16 (1<<10) + #define PM3LBSourceReadMode_Width(w) (((w)&0xfff)<<11) +#define PM3LBStencil 0x88a8 +#define PM3LBWriteBufferAddr 0xb540 +#define PM3LBWriteBufferOffset 0xb548 +#define PM3LBWriteFormat 0x88c8 + #define PM3LBWriteFormat_DepthWidth(w) (((w)&0x3)<<0) + #define PM3LBWriteFormat_StencilWidth(w) (((w)&0xf)<<2) + #define PM3LBWriteFormat_StencilPosition(p) (((p)&0x1f)<<6) + #define PM3LBWriteFormat_GIDWidth(w) (((w)&0x7)<<20) + #define PM3LBWriteFormat_GIDPosition(p) (((p)&0x1f)<<23) +#define PM3LBWriteMode 0x88c0 +#define PM3LBWriteModeAnd 0xac80 +#define PM3LBWriteModeOr 0xac88 + #define PM3LBWriteMode_WriteDisable (0<<0) + #define PM3LBWriteMode_WriteEnable (1<<0) + #define PM3LBWriteMode_StripePitch(p) (((p)&0x7)<<3) + #define PM3LBWriteMode_StripeHeight(h) (((h)&0x7)<<6) + #define PM3LBWriteMode_Layout (1<<9) + #define PM3LBWriteMode_Origin (1<<10) + #define PM3LBWriteMode_Packed16 (1<<11) + #define PM3LBWriteMode_Width(w) (((w)&0xfff)<<12) +/* ... */ +#define PM3LineStippleMode 0x81a8 +#define PM3LineStippleModeAnd 0xabc0 +#define PM3LineStippleModeOr 0xabc8 +#define PM3LoadLineStippleCounters 0x81b0 +/* ... */ +#define PM3LogicalOpMode 0x8828 +#define PM3LogicalOpModeAnd 0xace0 +#define PM3LogicalOpModeOr 0xace8 + #define PM3LogicalOpMode_Disable (0<<0) + #define PM3LogicalOpMode_Enable (1<<0) + #define PM3LogicalOpMode_LogicOp(op) (((op)&0xf)<<1) + #define PM3LogicalOpMode_UseConstantWriteData_Disable (0<<5) + #define PM3LogicalOpMode_UseConstantWriteData_Enable (1<<5) + #define PM3LogicalOpMode_Background_Disable (0<<6) + #define PM3LogicalOpMode_Background_Enable (1<<6) + #define PM3LogicalOpMode_Background_LogicOp(op) (((op)&0xf)<<7) + #define PM3LogicalOpMode_UseConstantSource_Disable (0<<11) + #define PM3LogicalOpMode_UseConstantSource_Enable (1<<11) + +#define PM3LogicalTexturePageAddr 0xb4d0 +#define PM3LogicalTexturePageTableLength 0xb4d8 +/* ... */ +#define PM3LUT 0x8e80 +/* ... */ +#define PM3LUT 0x8e80 +#define PM3LUTAddress 0x84d0 +#define PM3LUTData 0x84c8 +#define PM3LUTIndex 0x84c0 +#define PM3LUTMode 0xb378 +#define PM3LUTModeAnd 0xad70 +#define PM3LUTModeOr 0xad78 +#define PM3LUTTransfer 0x84d8 +/* ... */ +#define PM3PhysicalPageAllocationTableAddr 0xb4c0 +/* ... */ +#define PM3PixelSize 0x80c0 + #define PM3PixelSize_GLOBAL_32BIT (0<<0) + #define PM3PixelSize_GLOBAL_16BIT (1<<0) + #define PM3PixelSize_GLOBAL_8BIT (2<<0) + #define PM3PixelSize_RASTERIZER_32BIT (0<<2) + #define PM3PixelSize_RASTERIZER_16BIT (1<<2) + #define PM3PixelSize_RASTERIZER_8BIT (2<<2) + #define PM3PixelSize_SCISSOR_AND_STIPPLE_32BIT (0<<4) + #define PM3PixelSize_SCISSOR_AND_STIPPLE_16BIT (1<<4) + #define PM3PixelSize_SCISSOR_AND_STIPPLE_8BIT (2<<4) + #define PM3PixelSize_TEXTURE_32BIT (0<<6) + #define PM3PixelSize_TEXTURE_16BIT (1<<6) + #define PM3PixelSize_TEXTURE_8BIT (2<<6) + #define PM3PixelSize_LUT_32BIT (0<<8) + #define PM3PixelSize_LUT_16BIT (1<<8) + #define PM3PixelSize_LUT_8BIT (2<<8) + #define PM3PixelSize_FRAMEBUFFER_32BIT (0<<10) + #define PM3PixelSize_FRAMEBUFFER_16BIT (1<<10) + #define PM3PixelSize_FRAMEBUFFER_8BIT (2<<10) + #define PM3PixelSize_LOGICAL_OP_32BIT (0<<12) + #define PM3PixelSize_LOGICAL_OP_16BIT (1<<12) + #define PM3PixelSize_LOGICAL_OP_8BIT (2<<12) + #define PM3PixelSize_LOCALBUFFER_32BIT (0<<14) + #define PM3PixelSize_LOCALBUFFER_16BIT (1<<14) + #define PM3PixelSize_LOCALBUFFER_8BIT (2<<14) + #define PM3PixelSize_SETUP_32BIT (0<<16) + #define PM3PixelSize_SETUP_16BIT (1<<16) + #define PM3PixelSize_SETUP_8BIT (2<<16) + #define PM3PixelSize_GLOBAL (0<<31) + #define PM3PixelSize_INDIVIDUAL (1<<31) +/* ... */ +#define PM3QStart 0x83b8 + +#define PM3Render 0x8038 + #define PM3Render_AreaStipple_Disable (0<<0) + #define PM3Render_AreaStipple_Enable (1<<0) + #define PM3Render_LineStipple_Disable (0<<1) + #define PM3Render_LineStipple_Enable (1<<1) + #define PM3Render_ResetLine_Disable (0<<2) + #define PM3Render_ResetLine_Enable (1<<2) + #define PM3Render_FastFill_Disable (0<<3) + #define PM3Render_FastFill_Enable (1<<3) + #define PM3Render_Primitive_Line (0<<6) + #define PM3Render_Primitive_Trapezoid (1<<6) + #define PM3Render_Primitive_Point (2<<6) + #define PM3Render_Antialias_Disable (0<<8) + #define PM3Render_Antialias_Enable (1<<8) + #define PM3Render_Antialias_SubPixelRes_4x4 (0<<9) + #define PM3Render_Antialias_SubPixelRes_8x8 (1<<9) + #define PM3Render_UsePointTable_Disable (0<<10) + #define PM3Render_UsePointTable_Enable (1<<10) + #define PM3Render_SyncOnbitMask_Disable (0<<11) + #define PM3Render_SyncOnBitMask_Enable (1<<11) + #define PM3Render_SyncOnHostData_Disable (0<<12) + #define PM3Render_SyncOnHostData_Enable (1<<12) + #define PM3Render_Texture_Disable (0<<13) + #define PM3Render_Texture_Enable (1<<13) + #define PM3Render_Fog_Disable (0<<14) + #define PM3Render_Fog_Enable (1<<14) + #define PM3Render_Coverage_Disable (0<<15) + #define PM3Render_Coverage_Enable (1<<15) + #define PM3Render_SubPixelCorrection_Disable (0<<16) + #define PM3Render_SubPixelCorrection_Enable (1<<16) + #define PM3Render_SpanOperation_Disable (0<<18) + #define PM3Render_SpanOperation_Enable (1<<18) + #define PM3Render_FBSourceRead_Disable (0<<27) + #define PM3Render_FBSourceRead_Enable (1<<27) +#define PM3RasterizerMode 0x80a0 +#define PM3RasterizerModeAnd 0xaba0 +#define PM3RasterizerModeOr 0xabb8 +#define PM3RectangleHeight 0x94e0 +#define PM3RepeatLine 0x9328 +#define PM3ResetPickResult 0x8c20 +#define PM3RLEMask 0x8c48 +#define PM3RouterMode 0x8840 +#define PM3RStart 0x8780 +#define PM3S1Start 0x8400 +#define PM3aveLineStippleCounters 0x81c0 +#define PM3ScissorMaxXY 0x8190 +#define PM3ScissorMinXY 0x8188 +#define PM3ScissorMode 0x8180 +#define PM3ScissorModeAnd 0xabb0 +#define PM3ScissorModeOr 0xabb8 +#define PM3ScreenSize 0x8198 +#define PM3Security 0x8908 +#define PM3SetLogicalTexturePage 0xb360 +#define PM3SizeOfFramebuffer 0xb0a8 +#define PM3SStart 0x8388 +#define PM3StartXDom 0x8000 +#define PM3StartXSub 0x8010 +#define PM3StartY 0x8020 +/* ... */ +#define PM3SpanColorMask 0x8168 + +#define PM3StencilMode 0x8988 +/* ... */ +#define PM3TailPhysicalPageAllocation0 0xb4a0 +#define PM3TailPhysicalPageAllocation1 0xb4a8 +#define PM3TailPhysicalPageAllocation2 0xb4b0 +#define PM3TailPhysicalPageAllocation3 0xb4b8 +/* ... */ +#define PM3TextureApplicationMode 0x8680 +#define PM3TextureApplicationModeAnd 0xac50 +#define PM3TextureApplicationModeOr 0xac58 +#define PM3TextureBaseAddr0 0x8500 +#define PM3TextureBaseAddr1 0x8508 +#define PM3TextureBaseAddr2 0x8510 +#define PM3TextureBaseAddr3 0x8518 +#define PM3TextureBaseAddr4 0x8520 +#define PM3TextureBaseAddr5 0x8528 +#define PM3TextureBaseAddr6 0x8530 +#define PM3TextureBaseAddr7 0x8538 +#define PM3TextureBaseAddr8 0x8540 +#define PM3TextureBaseAddr9 0x8548 +#define PM3TextureBaseAddr10 0x8550 +#define PM3TextureBaseAddr11 0x8558 +#define PM3TextureBaseAddr12 0x8560 +#define PM3TextureBaseAddr13 0x8568 +#define PM3TextureBaseAddr14 0x8570 +#define PM3TextureBaseAddr15 0x8578 +#define PM3TextureCacheControl 0x8490 +#define PM3TextureChromaLower0 0x84f0 +#define PM3TextureChromaLower1 0x8608 +#define PM3TextureChromaUpper0 0x84e8 +#define PM3TextureChromaUpper1 0x8600 +#define PM3TextureCompositeAlphaMode0 0xb310 +#define PM3TextureCompositeAlphaMode0And 0xb390 +#define PM3TextureCompositeAlphaMode0Or 0xb398 +#define PM3TextureCompositeAlphaMode1 0xb320 +#define PM3TextureCompositeAlphaMode1And 0xb3b0 +#define PM3TextureCompositeAlphaMode1Or 0xb3b8 +#define PM3TextureCompositeColorMode0 0xb308 +#define PM3TextureCompositeColorMode0And 0xb380 +#define PM3TextureCompositeColorMode0Or 0xb388 +#define PM3TextureCompositeColorMode1 0xb318 +#define PM3TextureCompositeColorMode1And 0xb3a0 +#define PM3TextureCompositeColorMode1Or 0xb3a8 +#define PM3TextureCompositeFactor0 0xb328 +#define PM3TextureCompositeFactor1 0xb330 +#define PM3TextureCompositeMode 0xb300 +#define PM3TextureCoordMode 0x8380 +#define PM3TextureCoordModeAnd 0xac20 +#define PM3TextureCoordModeOr 0xac28 +#define PM3TextureData 0x88e8 +/* +#define PM3TextureDownloadControl 0x0108 +*/ +#define PM3TextureDownloadOffset 0x88f0 +#define PM3TextureEnvColor 0x8688 +#define PM3TextureFilterMode 0x84e0 +#define PM3TextureFilterModeAnd 0xad50 +#define PM3TextureFilterModeOr 0xad58 +#define PM3TextureIndexMode0 0xb338 +#define PM3TextureIndexMode0And 0xb3c0 +#define PM3TextureIndexMode0Or 0xb3c8 +#define PM3TextureIndexMode1 0xb340 +#define PM3TextureIndexMode1And 0xb3d0 +#define PM3TextureIndexMode1Or 0xb3d8 +#define PM3TextureLODBiasS 0x8450 +#define PM3TextureLODBiasT 0x8458 +/* ... */ +#define PM3TextureMapSize 0xb428 +#define PM3TextureMapWidth0 0x8580 +#define PM3TextureMapWidth1 0x8588 + #define PM3TextureMapWidth_Width(w) ((w&0xfff)<<0) + #define PM3TextureMapWidth_BorderLayout (1<<12) + #define PM3TextureMapWidth_Layout_Linear (0<<13) + #define PM3TextureMapWidth_Layout_Patch64 (1<<13) + #define PM3TextureMapWidth_Layout_Patch32_2 (2<<13) + #define PM3TextureMapWidth_Layout_Patch2 (3<<13) + #define PM3TextureMapWidth_HostTexture (1<<15) +#define PM3TextureReadMode0 0xb400 +#define PM3TextureReadMode0And 0xac30 +#define PM3TextureReadMode0Or 0xac38 +#define PM3TextureReadMode1 0xb408 +#define PM3TextureReadMode1And 0xad40 +#define PM3TextureReadMode1Or 0xad48 + +#define PM3TouchLogicalPage 0xb370 + #define PM3TouchLogicalPage_Page(p) (p&0xffff) + #define PM3TouchLogicalPage_Count(c) ((c&0x3fff)<<16) + #define PM3TouchLogicalPage_Mode(m) ((m&0x3)<<30) + +#define PM3TStart 0x83a0 + +#define PM3UpdateLogicalTextureInfo 0xb368 + #define PM3UpdateLogicalTextureInfo_Length(l) ((l)&0x1ff) + #define PM3UpdateLogicalTextureInfo_MemoryPool(m) (((m)&0x3)<<9) + #define PM3UpdateLogicalTextureInfo_VirtualHostPage (1<<11) + #define PM3UpdateLogicalTextureInfo_HostPage(p) (((p)&0xfffff)<<12) + +/* ... */ +#define PM3WaitForCompletion 0x80b8 +#define PM3Window 0x8980 + #define PM3Window_ForceLBUpdate (1<<3) + #define PM3Window_LBUpdateSource (1<<4) + #define PM3Window_FrameCount(c) (((c)&0xff)<<9) + #define PM3Window_StencilFCP (1<<17) + #define PM3Window_DepthFCP (1<<18) + #define PM3Window_OverrideWriteFiltering (1<<19) +#define PM3WindowAnd 0xab80 +#define PM3WindowOr 0xab88 +#define PM3WindowOrigin 0x81c8 +#define PM3XBias 0x9480 +#define PM3YBias 0x9488 +#define PM3YLimits 0x80a8 +#define PM3YUVMode 0x8f00 +#define PM3ZFogBias 0x86b8 +#define PM3ZStart 0xadd8 +#define PM3ZStartL 0x89b8 +#define PM3ZStartU 0x89b0 + + +/********************************************** +* GLINT Permedia3 2D setup Unit * +***********************************************/ +#define PM3Config2D 0xb618 + #define PM3Config2D_OpaqueSpan (1<<0) + #define PM3Config2D_MultiRXBlit (1<<1) + #define PM3Config2D_UserScissorEnable (1<<2) + #define PM3Config2D_FBDestReadEnable (1<<3) + #define PM3Config2D_AlphaBlendEnable (1<<4) + #define PM3Config2D_DitherEnable (1<<5) + #define PM3Config2D_ForegroundROPEnable (1<<6) + #define PM3Config2D_ForegroundROP(rop) (((rop)&0xf)<<7) + #define PM3Config2D_BackgroundROPEnable (1<<11) + #define PM3Config2D_BackgroundROP(rop) (((rop)&0xf)<<12) + #define PM3Config2D_UseConstantSource (1<<16) + #define PM3Config2D_FBWriteEnable (1<<17) + #define PM3Config2D_Blocking (1<<18) + #define PM3Config2D_ExternalSourceData (1<<19) + #define PM3Config2D_LUTModeEnable (1<<20) +#define PM3DownloadGlyphwidth 0xb658 + #define PM3DownloadGlyphwidth_GlyphWidth(gw) ((gw)&0xffff) +#define PM3DownloadTarget 0xb650 + #define PM3DownloadTarget_TagName(tag) ((tag)&0x1fff) +#define PM3GlyphData 0xb660 +#define PM3GlyphPosition 0xb608 + #define PM3GlyphPosition_XOffset(x) ((x)&0xffff) + #define PM3GlyphPosition_YOffset(y) (((y)&0xffff)<<16) +#define PM3Packed4Pixels 0xb668 +#define PM3Packed8Pixels 0xb630 +#define PM3Packed16Pixels 0xb638 +#define PM3RectanglePosition 0xb600 + #define PM3RectanglePosition_XOffset(x) ((x)&0xffff) + #define PM3RectanglePosition_YOffset(y) (((y)&0xffff)<<16) +#define PM3Render2D 0xb640 + #define PM3Render2D_Width(w) ((w)&0x0fff) + #define PM3Render2D_Operation_Normal (0<<12) + #define PM3Render2D_Operation_SyncOnHostData (1<<12) + #define PM3Render2D_Operation_SyncOnBitMask (2<<12) + #define PM3Render2D_Operation_PatchOrderRendering (3<<12) + #define PM3Render2D_FBSourceReadEnable (1<<14) + #define PM3Render2D_SpanOperation (1<<15) + #define PM3Render2D_Height(h) (((h)&0x0fff)<<16) + #define PM3Render2D_XPositive (1<<28) + #define PM3Render2D_YPositive (1<<29) + #define PM3Render2D_AreaStippleEnable (1<<30) + #define PM3Render2D_TextureEnable (1<<31) +#define PM3Render2DGlyph 0xb648 + #define PM3Render2DGlyph_Width(w) ((w)&0x7f) + #define PM3Render2DGlyph_Height(h) (((h)&0x7f)<<7) + #define PM3Render2DGlyph_XOffset(x) (((x)&0x1ff)<<14) + #define PM3Render2DGlyph_YOffset(y) (((y)&0x1ff)<<23) +#define PM3RenderPatchOffset 0xb610 + #define PM3RenderPatchOffset_XOffset(x) ((x)&0xffff) + #define PM3RenderPatchOffset_YOffset(y) (((y)&0xffff)<<16) +#define PM3RLCount 0xb678 + #define PM3RLCount_Count(c) ((c)&0x0fff) +#define PM3RLData 0xb670 + +/********************************************** +* GLINT Permedia3 Alias Register * +***********************************************/ +#define PM3FillBackgroundColor 0x8330 +#define PM3FillConfig2D0 0x8338 +#define PM3FillConfig2D1 0x8360 + #define PM3FillConfig2D_OpaqueSpan 1<<0 + #define PM3FillConfig2D_MultiRXBlit 1<<1 + #define PM3FillConfig2D_UserScissorEnable 1<<2 + #define PM3FillConfig2D_FBDestReadEnable 1<<3 + #define PM3FillConfig2D_AlphaBlendEnable 1<<4 + #define PM3FillConfig2D_DitherEnable 1<<5 + #define PM3FillConfig2D_ForegroundROPEnable 1<<6 + #define PM3FillConfig2D_ForegroundROP(rop) (((rop)&0xf)<<7) + #define PM3FillConfig2D_BackgroundROPEnable 1<<11 + #define PM3FillConfig2D_BackgroundROP(rop) (((rop)&0xf)<<12) + #define PM3FillConfig2D_UseConstantSource 1<<16 + #define PM3FillConfig2D_FBWriteEnable 1<<17 + #define PM3FillConfig2D_Blocking 1<<18 + #define PM3FillConfig2D_ExternalSourceData 1<<19 + #define PM3FillConfig2D_LUTModeEnable 1<<20 +#define PM3FillFBDestReadBufferAddr 0x8310 +#define PM3FillFBSourceReadBufferAddr 0x8308 +#define PM3FillFBSourceReadBufferOffset 0x8340 + #define PM3FillFBSourceReadBufferOffset_XOffset(x) ((x)&0xffff) + #define PM3FillFBSourceReadBufferOffset_YOffset(y) (((y)&0xffff)<<16) +#define PM3FillFBWriteBufferAddr 0x8300 +#define PM3FillForegroundColor0 0x8328 +#define PM3FillForegroundColor1 0x8358 +#define PM3FillGlyphPosition 0x8368 + #define PM3FillGlyphPosition_XOffset(x) ((x)&0xffff) + #define PM3FillGlyphPosition_YOffset(y) (((y)&0xffff)<<16) +#define PM3FillRectanglePosition 0x8348 + #define PM3FillRectanglePosition_XOffset(x) ((x)&0xffff) + #define PM3FillRectanglePosition_YOffset(y) (((y)&0xffff)<<16) + +/********************************************** +* GLINT Permedia3 Macros * +***********************************************/ + +#ifdef __alpha__ +#define mem_barrier() asm volatile ("mb" : : : "memory") +#define write_mem_barrier() asm volatile ("wmb" : : : "memory") +#else +#define mem_barrier() +#define write_mem_barrier() +#endif + +extern void *pm3_reg_base; + +#define WRITE_REG(offset,val) \ + do { \ + write_mem_barrier(); \ + *(volatile uint32_t *) \ + (((unsigned char *)(pm3_reg_base)) + offset) = (val); \ + } while(0) + +static inline uint32_t +READ_REG(uint32_t offset) +{ + mem_barrier(); + return *(volatile uint32_t *)(((unsigned char *)(pm3_reg_base)) + offset); +} + +#define UPDATE_SET_REG(offset,val) \ + { \ + unsigned long temp; \ + temp = READ_REG(offset); \ + WRITE_REG(offset,temp|(val)); \ + } + +#define UPDATE_CLEAR_REG(offset,val) \ + { \ + unsigned long temp; \ + temp = READ_REG(offset); \ + WRITE_REG(offset,temp&(~(val))); \ + } + +#define WAIT_FIFO(n) while(READ_REG(PM3InFIFOSpace) < (n)) + +#define RAMDAC_DELAY(x) do { \ + int delay = x; \ + unsigned char tmp; \ + while(delay--){tmp = READ_REG(PM3InFIFOSpace);}; \ +} while(0) + +#define SLOW_WRITE_REG(v,r) \ +do{ \ + RAMDAC_DELAY(5); \ + WRITE_REG(v,r); \ + RAMDAC_DELAY(5); \ +}while(0) + +#define RAMDAC_SET_INDEX(index) \ +{ \ + SLOW_WRITE_REG (PM3RD_IndexHigh,(index>>8)&0xff); \ + SLOW_WRITE_REG (PM3RD_IndexLow,index&0xff); \ +} + +#define RAMDAC_SET_REG(index, data) \ +{ \ + RAMDAC_SET_INDEX(index); \ + SLOW_WRITE_REG(PM3RD_IndexedData, data); \ +} + +#define RAMDAC_GET_REG(index, temp) \ +{ \ + RAMDAC_SET_INDEX(index); \ + temp = READ_REG(PM3RD_IndexedData); \ +} + +#endif /* _PM3_REG_H_ */ diff --git a/contrib/vidix/drivers/pm3_vid.c b/contrib/vidix/drivers/pm3_vid.c new file mode 100644 index 000000000..72a6523b3 --- /dev/null +++ b/contrib/vidix/drivers/pm3_vid.c @@ -0,0 +1,573 @@ +/** + Driver for 3DLabs GLINT R3 and Permedia3 chips. + + Copyright (C) 2002, 2003 MÃ¥ns RullgÃ¥rd + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +**/ + +#include <errno.h> +#include <stdio.h> +#include <stdlib.h> +#include <string.h> +#include <inttypes.h> +#include <unistd.h> +#include <sys/mman.h> + +#include "vidix.h" +#include "fourcc.h" +#include "libdha.h" +#include "pci_ids.h" +#include "pci_names.h" + +#include "pm3_regs.h" + +#define VIDIX_STATIC pm3_ + +/* MBytes of video memory to use */ +#define PM3_VIDMEM 24 + +#if 0 +#define TRACE_ENTER() fprintf(stderr, "%s: enter\n", __FUNCTION__) +#define TRACE_EXIT() fprintf(stderr, "%s: exit\n", __FUNCTION__) +#else +#define TRACE_ENTER() +#define TRACE_EXIT() +#endif + +static pciinfo_t pci_info; + +void *pm3_reg_base; +static void *pm3_mem; + +static int pm3_vidmem = PM3_VIDMEM; +static int pm3_blank = 0; +static int pm3_dma = 0; + +static int pm3_ckey_red, pm3_ckey_green, pm3_ckey_blue; + +static u_int page_size; + +static vidix_capability_t pm3_cap = +{ + "3DLabs GLINT R3/Permedia3 driver", + "MÃ¥ns RullgÃ¥rd <mru@users.sf.net>", + TYPE_OUTPUT, + { 0, 0, 0, 0 }, + 2048, + 2048, + 4, + 4, + -1, + FLAG_UPSCALER | FLAG_DOWNSCALER, + VENDOR_3DLABS, + -1, + { 0, 0, 0, 0 } +}; + + +unsigned int VIDIX_NAME(vixGetVersion)(void) +{ + return(VIDIX_VERSION); +} + +static unsigned short pm3_card_ids[] = +{ + DEVICE_3DLABS_GLINT_R3 +}; + +static int find_chip(unsigned chip_id) +{ + unsigned i; + for(i = 0;i < sizeof(pm3_card_ids)/sizeof(unsigned short);i++) + { + if(chip_id == pm3_card_ids[i]) return i; + } + return -1; +} + +int VIDIX_NAME(vixProbe)(int verbose, int force) +{ + pciinfo_t lst[MAX_PCI_DEVICES]; + unsigned i,num_pci; + int err; + + err = pci_scan(lst,&num_pci); + if(err) + { + printf("[pm3] Error occured during pci scan: %s\n",strerror(err)); + return err; + } + else + { + err = ENXIO; + for(i=0; i < num_pci; i++) + { + if(lst[i].vendor == VENDOR_3DLABS) + { + int idx; + const char *dname; + idx = find_chip(lst[i].device); + if(idx == -1) + continue; + dname = pci_device_name(VENDOR_3DLABS, lst[i].device); + dname = dname ? dname : "Unknown chip"; + printf("[pm3] Found chip: %s with IRQ %i\n", + dname, lst[i].irq); + pm3_cap.device_id = lst[i].device; + err = 0; + memcpy(&pci_info, &lst[i], sizeof(pciinfo_t)); + break; + } + } + } + if(err && verbose) printf("[pm3] Can't find chip\n"); + return err; +} + +#define PRINT_REG(reg) \ +{ \ + long _foo = READ_REG(reg); \ + printf("[pm3] " #reg " (%x) = %#lx (%li)\n", reg, _foo, _foo); \ +} + +int VIDIX_NAME(vixInit)(const char *args) +{ + if(args != NULL){ + char *ac = strdup(args), *s, *opt; + + opt = strtok_r(ac, ",", &s); + while(opt){ + char *a = strchr(opt, '='); + + if(a) + *a++ = 0; + if(!strcmp(opt, "mem")){ + if(a) + pm3_vidmem = strtol(a, NULL, 0); + } else if(!strcmp(opt, "blank")){ + pm3_blank = a? strtol(a, NULL, 0): 1; + } + + opt = strtok_r(NULL, ",", &s); + } + + free(ac); + } + + pm3_reg_base = map_phys_mem(pci_info.base0, 0x20000); + pm3_mem = map_phys_mem(pci_info.base1, 0x2000000); + + if(bm_open() == 0){ + fprintf(stderr, "[pm3] DMA available.\n"); + pm3_cap.flags |= FLAG_DMA | FLAG_SYNC_DMA; + page_size = sysconf(_SC_PAGESIZE); + hwirq_install(pci_info.bus, pci_info.card, pci_info.func, + 0, PM3IntFlags, -1); + WRITE_REG(PM3IntEnable, (1 << 7)); + pm3_dma = 1; + } + + RAMDAC_GET_REG(PM3RD_VideoOverlayKeyR, pm3_ckey_red); + RAMDAC_GET_REG(PM3RD_VideoOverlayKeyG, pm3_ckey_green); + RAMDAC_GET_REG(PM3RD_VideoOverlayKeyB, pm3_ckey_blue); + + return 0; +} + +void VIDIX_NAME(vixDestroy)(void) +{ + if(pm3_dma) + WRITE_REG(PM3IntEnable, 0); + + RAMDAC_SET_REG(PM3RD_VideoOverlayKeyR, pm3_ckey_red); + RAMDAC_SET_REG(PM3RD_VideoOverlayKeyG, pm3_ckey_green); + RAMDAC_SET_REG(PM3RD_VideoOverlayKeyB, pm3_ckey_blue); + + unmap_phys_mem(pm3_reg_base, 0x20000); + unmap_phys_mem(pm3_mem, 0x2000000); + hwirq_uninstall(pci_info.bus, pci_info.card, pci_info.func); + bm_close(); +} + +int VIDIX_NAME(vixGetCapability)(vidix_capability_t *to) +{ + memcpy(to, &pm3_cap, sizeof(vidix_capability_t)); + return 0; +} + +static int is_supported_fourcc(uint32_t fourcc) +{ + switch(fourcc){ + case IMGFMT_YUY2: + case IMGFMT_UYVY: + return 1; + default: + return 0; + } +} + +int VIDIX_NAME(vixQueryFourcc)(vidix_fourcc_t *to) +{ + if(is_supported_fourcc(to->fourcc)) + { + to->depth = VID_DEPTH_1BPP | VID_DEPTH_2BPP | + VID_DEPTH_4BPP | VID_DEPTH_8BPP | + VID_DEPTH_12BPP| VID_DEPTH_15BPP| + VID_DEPTH_16BPP| VID_DEPTH_24BPP| + VID_DEPTH_32BPP; + to->flags = VID_CAP_EXPAND | VID_CAP_SHRINK | VID_CAP_COLORKEY; + return 0; + } + else to->depth = to->flags = 0; + return ENOSYS; +} + +static int frames[VID_PLAY_MAXFRAMES], vid_base; +static int overlay_mode, overlay_control, video_control, int_enable; +static int rdoverlay_mode; +static int src_w, drw_w; +static int src_h, drw_h; +static int drw_x, drw_y; + +#define FORMAT_RGB8888 PM3VideoOverlayMode_COLORFORMAT_RGB8888 +#define FORMAT_RGB4444 PM3VideoOverlayMode_COLORFORMAT_RGB4444 +#define FORMAT_RGB5551 PM3VideoOverlayMode_COLORFORMAT_RGB5551 +#define FORMAT_RGB565 PM3VideoOverlayMode_COLORFORMAT_RGB565 +#define FORMAT_RGB332 PM3VideoOverlayMode_COLORFORMAT_RGB332 +#define FORMAT_BGR8888 PM3VideoOverlayMode_COLORFORMAT_BGR8888 +#define FORMAT_BGR4444 PM3VideoOverlayMode_COLORFORMAT_BGR4444 +#define FORMAT_BGR5551 PM3VideoOverlayMode_COLORFORMAT_BGR5551 +#define FORMAT_BGR565 PM3VideoOverlayMode_COLORFORMAT_BGR565 +#define FORMAT_BGR332 PM3VideoOverlayMode_COLORFORMAT_BGR332 +#define FORMAT_CI8 PM3VideoOverlayMode_COLORFORMAT_CI8 +#define FORMAT_VUY444 PM3VideoOverlayMode_COLORFORMAT_VUY444 +#define FORMAT_YUV444 PM3VideoOverlayMode_COLORFORMAT_YUV444 +#define FORMAT_VUY422 PM3VideoOverlayMode_COLORFORMAT_VUY422 +#define FORMAT_YUV422 PM3VideoOverlayMode_COLORFORMAT_YUV422 + +/* Notice, have to check that we dont overflow the deltas here ... */ +static void +compute_scale_factor(int* src_w, int* dst_w, + u_int* shrink_delta, u_int* zoom_delta) +{ + /* NOTE: If we don't return reasonable values here then the video + * unit can potential shut off and won't display an image until re-enabled. + * Seems as though the zoom_delta is o.k, and I've not had the problem. + * The 'shrink_delta' is prone to this the most - FIXME ! */ + + if (*src_w >= *dst_w) { + *src_w &= ~0x3; + *dst_w &= ~0x3; + *shrink_delta = (((*src_w << 16) / *dst_w) + 0x0f) & 0x0ffffff0; + *zoom_delta = 1<<16; + if ( ((*shrink_delta * *dst_w) >> 16) & 0x03 ) + *shrink_delta += 0x10; + } else { + *src_w &= ~0x3; + *dst_w &= ~0x3; + *zoom_delta = (((*src_w << 16) / *dst_w) + 0x0f) & 0x0001fff0; + *shrink_delta = 1<<16; + if ( ((*zoom_delta * *dst_w) >> 16) & 0x03 ) + *zoom_delta += 0x10; + } +} + +static void +pm3_setup_overlay(vidix_playback_t *info) +{ + u_int shrink, zoom; + int format = 0; + int filter = 0; + int sw = src_w; + + switch(info->fourcc){ + case IMGFMT_YUY2: + format = FORMAT_YUV422; + break; + case IMGFMT_UYVY: + format = FORMAT_VUY422; + break; + } + + compute_scale_factor(&sw, &drw_w, &shrink, &zoom); + + WAIT_FIFO(9); + WRITE_REG(PM3VideoOverlayBase0, vid_base >> 1); + WRITE_REG(PM3VideoOverlayStride, PM3VideoOverlayStride_STRIDE(src_w)); + WRITE_REG(PM3VideoOverlayWidth, PM3VideoOverlayWidth_WIDTH(sw)); + WRITE_REG(PM3VideoOverlayHeight, PM3VideoOverlayHeight_HEIGHT(src_h)); + WRITE_REG(PM3VideoOverlayOrigin, 0); + + /* Scale the source to the destinationsize */ + if (src_w == drw_w) { + WRITE_REG(PM3VideoOverlayShrinkXDelta, 1<<16); + WRITE_REG(PM3VideoOverlayZoomXDelta, 1<<16); + } else { + WRITE_REG(PM3VideoOverlayShrinkXDelta, shrink); + WRITE_REG(PM3VideoOverlayZoomXDelta, zoom); + filter = PM3VideoOverlayMode_FILTER_PARTIAL; + } + if (src_h == drw_h) { + WRITE_REG(PM3VideoOverlayYDelta, PM3VideoOverlayYDelta_NONE); + } else { + WRITE_REG(PM3VideoOverlayYDelta, + PM3VideoOverlayYDelta_DELTA(src_h, drw_h)); + filter = PM3VideoOverlayMode_FILTER_FULL; + } + + WRITE_REG(PM3VideoOverlayIndex, 0); + + /* Now set the ramdac video overlay region and mode */ + RAMDAC_SET_REG(PM3RD_VideoOverlayXStartLow, (drw_x & 0xff)); + RAMDAC_SET_REG(PM3RD_VideoOverlayXStartHigh, (drw_x & 0xf00)>>8); + RAMDAC_SET_REG(PM3RD_VideoOverlayXEndLow, (drw_x+drw_w) & 0xff); + RAMDAC_SET_REG(PM3RD_VideoOverlayXEndHigh, + ((drw_x+drw_w) & 0xf00)>>8); + RAMDAC_SET_REG(PM3RD_VideoOverlayYStartLow, (drw_y & 0xff)); + RAMDAC_SET_REG(PM3RD_VideoOverlayYStartHigh, (drw_y & 0xf00)>>8); + RAMDAC_SET_REG(PM3RD_VideoOverlayYEndLow, (drw_y+drw_h) & 0xff); + RAMDAC_SET_REG(PM3RD_VideoOverlayYEndHigh, + ((drw_y+drw_h) & 0xf00)>>8); + + overlay_mode = + 1 << 5 | + format | + filter | + PM3VideoOverlayMode_BUFFERSYNC_MANUAL | + PM3VideoOverlayMode_FLIP_VIDEO; + + overlay_control = + PM3RD_VideoOverlayControl_KEY_COLOR | + PM3RD_VideoOverlayControl_DIRECTCOLOR_ENABLED; +} + +extern int +VIDIX_NAME(vixSetGrKeys)(const vidix_grkey_t *key) +{ + if(key->ckey.op == CKEY_TRUE){ + RAMDAC_SET_REG(PM3RD_VideoOverlayKeyR, key->ckey.red); + RAMDAC_SET_REG(PM3RD_VideoOverlayKeyG, key->ckey.green); + RAMDAC_SET_REG(PM3RD_VideoOverlayKeyB, key->ckey.blue); + rdoverlay_mode = PM3RD_VideoOverlayControl_MODE_MAINKEY; + } else { + rdoverlay_mode = PM3RD_VideoOverlayControl_MODE_ALWAYS; + } + RAMDAC_SET_REG(PM3RD_VideoOverlayControl, + overlay_control | rdoverlay_mode); + + return 0; +} + +extern int +VIDIX_NAME(vixGetGrKeys)(vidix_grkey_t *key) +{ + RAMDAC_GET_REG(PM3RD_VideoOverlayKeyR, key->ckey.red); + RAMDAC_GET_REG(PM3RD_VideoOverlayKeyG, key->ckey.green); + RAMDAC_GET_REG(PM3RD_VideoOverlayKeyB, key->ckey.blue); + return 0; +} + +extern int +VIDIX_NAME(vixConfigPlayback)(vidix_playback_t *info) +{ + unsigned int i; + u_int frame_size; + u_int vidmem_size; + u_int max_frames; + + TRACE_ENTER(); + + src_w = info->src.w; + src_h = info->src.h; + drw_w = info->dest.w; + drw_h = info->dest.h; + drw_x = info->dest.x; + drw_y = info->dest.y; + + frame_size = src_w * src_h * 2; + vidmem_size = pm3_vidmem*1024*1024; + max_frames = vidmem_size / frame_size; + if(max_frames > VID_PLAY_MAXFRAMES) + max_frames = VID_PLAY_MAXFRAMES; + + src_h--; /* ugh */ + + if(info->num_frames > max_frames) + info->num_frames = max_frames; + vidmem_size = info->num_frames * frame_size; + + /* Use end of video memory. Assume the card has 32 MB */ + vid_base = 32*1024*1024 - vidmem_size; + info->dga_addr = pm3_mem + vid_base; + + info->dest.pitch.y = 2; + info->dest.pitch.u = 0; + info->dest.pitch.v = 0; + info->offset.y = 0; + info->offset.v = 0; + info->offset.u = 0; + info->frame_size = frame_size; + + for(i = 0; i < info->num_frames; i++){ + info->offsets[i] = frame_size * i; + frames[i] = (vid_base + info->offsets[i]) >> 1; + } + + pm3_setup_overlay(info); + + video_control = READ_REG(PM3VideoControl); + int_enable = READ_REG(PM3IntEnable); + + TRACE_EXIT(); + return 0; +} + +int VIDIX_NAME(vixPlaybackOn)(void) +{ + TRACE_ENTER(); + + WRITE_REG(PM3VideoOverlayMode, + overlay_mode | PM3VideoOverlayMode_ENABLE); + overlay_control |= PM3RD_VideoOverlayControl_ENABLE; + RAMDAC_SET_REG(PM3RD_VideoOverlayControl, + overlay_control | rdoverlay_mode); + WRITE_REG(PM3VideoOverlayUpdate, PM3VideoOverlayUpdate_ENABLE); + + if(pm3_blank) + WRITE_REG(PM3VideoControl, + video_control | PM3VideoControl_DISPLAY_ENABLE); + + TRACE_EXIT(); + return 0; +} + +int VIDIX_NAME(vixPlaybackOff)(void) +{ + overlay_control &= ~PM3RD_VideoOverlayControl_ENABLE; + RAMDAC_SET_REG(PM3RD_VideoOverlayControl, + PM3RD_VideoOverlayControl_DISABLE); + WRITE_REG(PM3VideoOverlayMode, + PM3VideoOverlayMode_DISABLE); + + if(video_control) + WRITE_REG(PM3VideoControl, + video_control & ~PM3VideoControl_DISPLAY_ENABLE); + + return 0; +} + +int VIDIX_NAME(vixPlaybackFrameSelect)(unsigned int frame) +{ + WRITE_REG(PM3VideoOverlayBase0, frames[frame]); + + return 0; +} + +struct pm3_bydma_cmd { + uint32_t bus_addr; + uint32_t fb_addr; + uint32_t mask; + uint32_t count; +}; + +struct pm3_bydma_frame { + struct pm3_bydma_cmd *cmds; + u_long bus_addr; + uint32_t count; +}; + +static struct pm3_bydma_frame * +pm3_setup_bydma(vidix_dma_t *dma, struct pm3_bydma_frame *bdf) +{ + u_int size = dma->size; + u_int pages = (size + page_size-1) / page_size; + unsigned long baddr[pages]; + u_int i; + uint32_t dest; + + if(bm_virt_to_bus(dma->src, dma->size, baddr)) + return NULL; + + if(!bdf){ + bdf = malloc(sizeof(*bdf)); + bdf->cmds = valloc(pages * sizeof(struct pm3_bydma_cmd)); + if(dma->flags & BM_DMA_FIXED_BUFFS){ + mlock(bdf->cmds, page_size); + } + } + + dest = vid_base + dma->dest_offset; + for(i = 0; i < pages; i++, dest += page_size, size -= page_size){ + bdf->cmds[i].bus_addr = baddr[i]; + bdf->cmds[i].fb_addr = dest; + bdf->cmds[i].mask = ~0; + bdf->cmds[i].count = ((size > page_size)? page_size: size) / 16; + } + + bdf->count = pages; + + if(bm_virt_to_bus(bdf->cmds, page_size, &bdf->bus_addr) != 0){ + free(bdf->cmds); + free(bdf); + return NULL; + } + + return bdf; +} + +extern int +VIDIX_NAME(vixPlaybackCopyFrame)(vidix_dma_t *dma) +{ + u_int frame = dma->idx; + struct pm3_bydma_frame *bdf; + + bdf = dma->internal[frame]; + if(!bdf || !(dma->flags & BM_DMA_FIXED_BUFFS)) + bdf = pm3_setup_bydma(dma, bdf); + if(!bdf) + return -1; + + if(!dma->internal[frame]) + dma->internal[frame] = bdf; + + if(dma->flags & BM_DMA_SYNC){ + hwirq_wait(pci_info.irq); + } + + WAIT_FIFO(3); + WRITE_REG(PM3ByDMAReadCommandBase, bdf->bus_addr); + WRITE_REG(PM3ByDMAReadCommandCount, bdf->count); + WRITE_REG(PM3ByDMAReadMode, + PM3ByDMAReadMode_ByteSwap_NONE | + PM3ByDMAReadMode_Format_RAW | + PM3ByDMAReadMode_PixelSize(16) | + PM3ByDMAReadMode_Active | + PM3ByDMAReadMode_Burst(7) | + PM3ByDMAReadMode_Align); + + if(dma->flags & BM_DMA_BLOCK){ + hwirq_wait(pci_info.irq); + } + + return 0; +} + +extern int +VIDIX_NAME(vixQueryDMAStatus)(void) +{ + uint32_t bdm = READ_REG(PM3ByDMAReadMode); + return (bdm & PM3ByDMAReadMode_Active)? 1: 0; +} diff --git a/contrib/vidix/drivers/radeon.h b/contrib/vidix/drivers/radeon.h new file mode 100644 index 000000000..090fbf8df --- /dev/null +++ b/contrib/vidix/drivers/radeon.h @@ -0,0 +1,2221 @@ +/* + * radeon.h + * This software has been released under the terms of the GNU Public + * license. See http://www.gnu.org/copyleft/gpl.html for details. + * + * This collection of definition was written by Nick Kurshev + * It's based on radeonfb, X11, GATOS sources + * and partly compatible with Rage128 set (in OV0, CAP0, CAP1 parts) +*/ + +#ifndef _RADEON_H +#define _RADEON_H + +#define RADEON_REGSIZE 0x4000 +#define MM_INDEX 0x0000 +/* MM_INDEX bit constants */ +# define MM_APER 0x80000000 +#define MM_DATA 0x0004 +#define BUS_CNTL 0x0030 +/* BUS_CNTL bit constants */ +# define BUS_DBL_RESYNC 0x00000001 +# define BUS_MSTR_RESET 0x00000002 +# define BUS_FLUSH_BUF 0x00000004 +# define BUS_STOP_REQ_DIS 0x00000008 +# define BUS_ROTATION_DIS 0x00000010 +# define BUS_MASTER_DIS 0x00000040 +# define BUS_ROM_WRT_EN 0x00000080 +# define BUS_DIS_ROM 0x00001000 +# define BUS_PCI_READ_RETRY_EN 0x00002000 +# define BUS_AGP_AD_STEPPING_EN 0x00004000 +# define BUS_PCI_WRT_RETRY_EN 0x00008000 +# define BUS_MSTR_RD_MULT 0x00100000 +# define BUS_MSTR_RD_LINE 0x00200000 +# define BUS_SUSPEND 0x00400000 +# define LAT_16X 0x00800000 +# define BUS_RD_DISCARD_EN 0x01000000 +# define BUS_RD_ABORT_EN 0x02000000 +# define BUS_MSTR_WS 0x04000000 +# define BUS_PARKING_DIS 0x08000000 +# define BUS_MSTR_DISCONNECT_EN 0x10000000 +# define BUS_WRT_BURST 0x20000000 +# define BUS_READ_BURST 0x40000000 +# define BUS_RDY_READ_DLY 0x80000000 +#define HI_STAT 0x004C +#define BUS_CNTL1 0x0034 +# define BUS_WAIT_ON_LOCK_EN (1 << 4) +#define I2C_CNTL_0 0x0090 +# define I2C_DONE (1<<0) +# define I2C_NACK (1<<1) +# define I2C_HALT (1<<2) +# define I2C_SOFT_RST (1<<5) +# define I2C_DRIVE_EN (1<<6) +# define I2C_DRIVE_SEL (1<<7) +# define I2C_START (1<<8) +# define I2C_STOP (1<<9) +# define I2C_RECEIVE (1<<10) +# define I2C_ABORT (1<<11) +# define I2C_GO (1<<12) +# define I2C_SEL (1<<16) +# define I2C_EN (1<<17) +#define I2C_CNTL_1 0x0094 +#define I2C_DATA 0x0098 +#define CONFIG_CNTL 0x00E0 +/* CONFIG_CNTL bit constants */ +# define CFG_VGA_RAM_EN 0x00000100 +#ifdef RAGE128 +#define GEN_RESET_CNTL 0x00f0 +# define SOFT_RESET_GUI 0x00000001 +# define SOFT_RESET_VCLK 0x00000100 +# define SOFT_RESET_PCLK 0x00000200 +# define SOFT_RESET_ECP 0x00000400 +# define SOFT_RESET_DISPENG_XCLK 0x00000800 +# define SOFT_RESET_MEMCTLR_XCLK 0x00001000 +#endif +#define CONFIG_MEMSIZE 0x00F8 +#define CONFIG_APER_0_BASE 0x0100 +#define CONFIG_APER_1_BASE 0x0104 +#define CONFIG_APER_SIZE 0x0108 +#define CONFIG_REG_1_BASE 0x010C +#define CONFIG_REG_APER_SIZE 0x0110 +#define PAD_AGPINPUT_DELAY 0x0164 +#define PAD_CTLR_STRENGTH 0x0168 +#define PAD_CTLR_UPDATE 0x016C +#define AGP_CNTL 0x0174 +# define AGP_APER_SIZE_256MB (0x00 << 0) +# define AGP_APER_SIZE_128MB (0x20 << 0) +# define AGP_APER_SIZE_64MB (0x30 << 0) +# define AGP_APER_SIZE_32MB (0x38 << 0) +# define AGP_APER_SIZE_16MB (0x3c << 0) +# define AGP_APER_SIZE_8MB (0x3e << 0) +# define AGP_APER_SIZE_4MB (0x3f << 0) +# define AGP_APER_SIZE_MASK (0x3f << 0) +#define AMCGPIO_A_REG 0x01a0 +#define AMCGPIO_EN_REG 0x01a8 +#define AMCGPIO_MASK 0x0194 +#define AMCGPIO_Y_REG 0x01a4 +/*#define BM_STATUS 0x0160*/ +#define MPP_TB_CONFIG 0x01c0 /* ? */ +#define MPP_GP_CONFIG 0x01c8 /* ? */ +#define VENDOR_ID 0x0F00 +#define DEVICE_ID 0x0F02 +#define COMMAND 0x0F04 +#define STATUS 0x0F06 +#define REVISION_ID 0x0F08 +#define REGPROG_INF 0x0F09 +#define SUB_CLASS 0x0F0A +#define CACHE_LINE 0x0F0C +#define LATENCY 0x0F0D +#define HEADER 0x0F0E +#define BIST 0x0F0F +#define REG_MEM_BASE 0x0F10 +#define REG_IO_BASE 0x0F14 +#define REG_REG_BASE 0x0F18 +#define ADAPTER_ID 0x0F2C +#define BIOS_ROM 0x0F30 +#define CAPABILITIES_PTR 0x0F34 +#define INTERRUPT_LINE 0x0F3C +#define INTERRUPT_PIN 0x0F3D +#define MIN_GRANT 0x0F3E +#define MAX_LATENCY 0x0F3F +#define ADAPTER_ID_W 0x0F4C +#define PMI_CAP_ID 0x0F50 +#define PMI_NXT_CAP_PTR 0x0F51 +#define PMI_PMC_REG 0x0F52 +#define PM_STATUS 0x0F54 +#define PMI_DATA 0x0F57 +#define AGP_CAP_ID 0x0F58 +#define AGP_STATUS 0x0F5C +# define AGP_1X_MODE 0x01 +# define AGP_2X_MODE 0x02 +# define AGP_4X_MODE 0x04 +# define AGP_MODE_MASK 0x07 +#define AGP_COMMAND 0x0F60 + +/* Video muxer unit */ +#define VIDEOMUX_CNTL 0x0190 +#define VIPPAD_MASK 0x0198 +#define VIPPAD1_A 0x01AC +#define VIPPAD1_EN 0x01B0 +#define VIPPAD1_Y 0x01B4 + +#define AIC_CTRL 0x01D0 +#define AIC_STAT 0x01D4 +#define AIC_PT_BASE 0x01D8 +#define AIC_LO_ADDR 0x01DC +#define AIC_HI_ADDR 0x01E0 +#define AIC_TLB_ADDR 0x01E4 +#define AIC_TLB_DATA 0x01E8 +#define DAC_CNTL 0x0058 +/* DAC_CNTL bit constants */ +# define DAC_RANGE_CNTL_MSK 0x00000003 +# define DAC_RANGE_PAL 0x00000000 +# define DAC_RANGE_NTSC 0x00000001 +# define DAC_RANGE_PS2 0x00000002 +# define DAC_BLANKING 0x00000004 +# define DAC_CMP_EN 0x00000008 +# define DAC_CMP_OUTPUT 0x00000080 +# define DAC_8BIT_EN 0x00000100 +# define DAC_4BPP_PIX_ORDER 0x00000200 +# define DAC_TVO_EN 0x00000400 +# define DAC_TVO_OVR_EXCL 0x00000800 +# define DAC_TVO_16BPP_DITH_EN 0x00001000 +# define DAC_VGA_ADR_EN (1 << 13) +# define DAC_PWDN (1 << 15) +# define DAC_CRC_EN 0x00080000 +# define DAC_MASK_ALL (0xff << 24) +# define DAC_RANGE_CNTL (3 << 0) +#define DAC_CNTL2 0x007c +/* DAC_CNTL2 bit constants */ +# define DAC2_DAC_CLK_SEL (1 << 0) +# define DAC2_DAC2_CLK_SEL (1 << 1) +# define DAC2_PALETTE_ACC_CTL (1 << 5) +#define TV_DAC_CNTL 0x088c +/* TV_DAC_CNTL bit constants */ +# define TV_DAC_STD_MASK 0x0300 +# define TV_DAC_RDACPD (1 << 24) +# define TV_DAC_GDACPD (1 << 25) +# define TV_DAC_BDACPD (1 << 26) +#define CRTC_GEN_CNTL 0x0050 +/* CRTC_GEN_CNTL bit constants */ +# define CRTC_DBL_SCAN_EN 0x00000001 +# define CRTC_INTERLACE_EN (1 << 1) +# define CRTC_CSYNC_EN (1 << 4) +# define CRTC_CUR_EN 0x00010000 +# define CRTC_CUR_MODE_MASK (7 << 17) +# define CRTC_ICON_EN (1 << 20) +# define CRTC_EXT_DISP_EN (1 << 24) +# define CRTC_EN (1 << 25) +# define CRTC_DISP_REQ_EN_B (1 << 26) +#define CRTC2_GEN_CNTL 0x03f8 +/* CRTC2_GEN_CNTL bit constants */ +# define CRTC2_DBL_SCAN_EN (1 << 0) +# define CRTC2_INTERLACE_EN (1 << 1) +# define CRTC2_SYNC_TRISTAT (1 << 4) +# define CRTC2_HSYNC_TRISTAT (1 << 5) +# define CRTC2_VSYNC_TRISTAT (1 << 6) +# define CRTC2_CRT2_ON (1 << 7) +# define CRTC2_ICON_EN (1 << 15) +# define CRTC2_CUR_EN (1 << 16) +# define CRTC2_CUR_MODE_MASK (7 << 20) +# define CRTC2_DISP_DIS (1 << 23) +# define CRTC2_EN (1 << 25) +# define CRTC2_DISP_REQ_EN_B (1 << 26) +# define CRTC2_HSYNC_DIS (1 << 28) +# define CRTC2_VSYNC_DIS (1 << 29) +#define MEM_CNTL 0x0140 +/* MEM_CNTL bit constants */ +# define MEM_CTLR_STATUS_IDLE 0x00000000 +# define MEM_CTLR_STATUS_BUSY 0x00100000 +# define MEM_SEQNCR_STATUS_IDLE 0x00000000 +# define MEM_SEQNCR_STATUS_BUSY 0x00200000 +# define MEM_ARBITER_STATUS_IDLE 0x00000000 +# define MEM_ARBITER_STATUS_BUSY 0x00400000 +# define MEM_REQ_UNLOCK 0x00000000 +# define MEM_REQ_LOCK 0x00800000 +#define EXT_MEM_CNTL 0x0144 +#define MC_AGP_LOCATION 0x014C +#define MEM_IO_CNTL_A0 0x0178 +#define MEM_INIT_LATENCY_TIMER 0x0154 +#define MEM_SDRAM_MODE_REG 0x0158 +#define AGP_BASE 0x0170 +#ifdef RAGE128 +#define PCI_GART_PAGE 0x017c +#define PC_NGUI_MODE 0x0180 +#define PC_NGUI_CTLSTAT 0x0184 +# define PC_FLUSH_GUI (3 << 0) +# define PC_RI_GUI (1 << 2) +# define PC_FLUSH_ALL 0x00ff +# define PC_BUSY (1 << 31) +#define PC_MISC_CNTL 0x0188 +#else +#define MEM_IO_CNTL_A1 0x017C +#define MEM_IO_CNTL_B0 0x0180 +#define MEM_IO_CNTL_B1 0x0184 +#define MC_DEBUG 0x0188 +#endif +#define MC_STATUS 0x0150 +#define MEM_IO_OE_CNTL 0x018C +#define MC_FB_LOCATION 0x0148 +#define HOST_PATH_CNTL 0x0130 +#define MEM_VGA_WP_SEL 0x0038 +#define MEM_VGA_RP_SEL 0x003C +#define HDP_DEBUG 0x0138 +#define SW_SEMAPHORE 0x013C +#define SURFACE_CNTL 0x0B00 +/* SURFACE_CNTL bit constants */ +# define SURF_TRANSLATION_DIS (1 << 8) +# define NONSURF_AP0_SWP_16BPP (1 << 20) +# define NONSURF_AP0_SWP_32BPP (2 << 20) +#define SURFACE0_LOWER_BOUND 0x0B04 +#define SURFACE1_LOWER_BOUND 0x0B14 +#define SURFACE2_LOWER_BOUND 0x0B24 +#define SURFACE3_LOWER_BOUND 0x0B34 +#define SURFACE4_LOWER_BOUND 0x0B44 +#define SURFACE5_LOWER_BOUND 0x0B54 +#define SURFACE6_LOWER_BOUND 0x0B64 +#define SURFACE7_LOWER_BOUND 0x0B74 +#define SURFACE0_UPPER_BOUND 0x0B08 +#define SURFACE1_UPPER_BOUND 0x0B18 +#define SURFACE2_UPPER_BOUND 0x0B28 +#define SURFACE3_UPPER_BOUND 0x0B38 +#define SURFACE4_UPPER_BOUND 0x0B48 +#define SURFACE5_UPPER_BOUND 0x0B58 +#define SURFACE6_UPPER_BOUND 0x0B68 +#define SURFACE7_UPPER_BOUND 0x0B78 +#define SURFACE0_INFO 0x0B0C +#define SURFACE1_INFO 0x0B1C +#define SURFACE2_INFO 0x0B2C +#define SURFACE3_INFO 0x0B3C +#define SURFACE4_INFO 0x0B4C +#define SURFACE5_INFO 0x0B5C +#define SURFACE6_INFO 0x0B6C +#define SURFACE7_INFO 0x0B7C +#define SURFACE_ACCESS_FLAGS 0x0BF8 +#define SURFACE_ACCESS_CLR 0x0BFC +#define GEN_INT_CNTL 0x0040 +#define GEN_INT_STATUS 0x0044 +# define VSYNC_INT_AK (1 << 2) +# define VSYNC_INT (1 << 2) +#define CRTC_EXT_CNTL 0x0054 +/* CRTC_EXT_CNTL bit constants */ +# define CRTC_VGA_XOVERSCAN (1 << 0) +# define VGA_ATI_LINEAR 0x00000008 +# define VGA_128KAP_PAGING 0x00000010 +# define XCRT_CNT_EN (1 << 6) +# define CRTC_HSYNC_DIS (1 << 8) +# define CRTC_VSYNC_DIS (1 << 9) +# define CRTC_DISPLAY_DIS (1 << 10) +# define CRTC_SYNC_TRISTAT (1 << 11) +# define CRTC_CRT_ON (1 << 15) +#define CRTC_EXT_CNTL_DPMS_BYTE 0x0055 +# define CRTC_HSYNC_DIS_BYTE (1 << 0) +# define CRTC_VSYNC_DIS_BYTE (1 << 1) +# define CRTC_DISPLAY_DIS_BYTE (1 << 2) +#define RB3D_CNTL 0x1C3C +#define WAIT_UNTIL 0x1720 +# define EVENT_CRTC_OFFSET 0x00000001 +# define EVENT_RE_CRTC_VLINE 0x00000002 +# define EVENT_FE_CRTC_VLINE 0x00000004 +# define EVENT_CRTC_VLINE 0x00000008 +# define EVENT_BM_VIP0_IDLE 0x00000010 +# define EVENT_BM_VIP1_IDLE 0x00000020 +# define EVENT_BM_VIP2_IDLE 0x00000040 +# define EVENT_BM_VIP3_IDLE 0x00000080 +# define EVENT_BM_VIDCAP_IDLE 0x00000100 +# define EVENT_BM_GUI_IDLE 0x00000200 +# define EVENT_CMDFIFO 0x00000400 +# define EVENT_OV0_FLIP 0x00000800 +# define EVENT_CMDFIFO_ENTRIES 0x07F00000 +#define ISYNC_CNTL 0x1724 +#define RBBM_GUICNTL 0x172C +#define RBBM_STATUS 0x0E40 +# define RBBM_FIFOCNT_MASK 0x007f +# define RBBM_ACTIVE (1 << 31) +#define RBBM_STATUS_alt_1 0x1740 +#define RBBM_CNTL 0x00EC +#define RBBM_CNTL_alt_1 0x0E44 +#define RBBM_SOFT_RESET 0x00F0 +/* RBBM_SOFT_RESET bit constants */ +# define SOFT_RESET_CP (1 << 0) +# define SOFT_RESET_HI (1 << 1) +# define SOFT_RESET_SE (1 << 2) +# define SOFT_RESET_RE (1 << 3) +# define SOFT_RESET_PP (1 << 4) +# define SOFT_RESET_E2 (1 << 5) +# define SOFT_RESET_RB (1 << 6) +# define SOFT_RESET_HDP (1 << 7) +#define RBBM_SOFT_RESET_alt_1 0x0E48 +#define NQWAIT_UNTIL 0x0E50 +#define RBBM_DEBUG 0x0E6C +#define RBBM_CMDFIFO_ADDR 0x0E70 +#define RBBM_CMDFIFO_DATAL 0x0E74 +#define RBBM_CMDFIFO_DATAH 0x0E78 +#define RBBM_CMDFIFO_STAT 0x0E7C +#define CRTC_STATUS 0x005C +/* CRTC_STATUS bit constants */ +# define CRTC_VBLANK 0x00000001 +# define CRTC_VBLANK_SAVE ( 1 << 1) +#define GPIO_VGA_DDC 0x0060 +#define GPIO_DVI_DDC 0x0064 +#define GPIO_MONID 0x0068 +#define PALETTE_INDEX 0x00B0 +#define PALETTE_DATA 0x00B4 +#define PALETTE_30_DATA 0x00B8 +#define CRTC_H_TOTAL_DISP 0x0200 +# define CRTC_H_TOTAL (0x03ff << 0) +# define CRTC_H_TOTAL_SHIFT 0 +# define CRTC_H_DISP (0x01ff << 16) +# define CRTC_H_DISP_SHIFT 16 +#define CRTC2_H_TOTAL_DISP 0x0300 +# define CRTC2_H_TOTAL (0x03ff << 0) +# define CRTC2_H_TOTAL_SHIFT 0 +# define CRTC2_H_DISP (0x01ff << 16) +# define CRTC2_H_DISP_SHIFT 16 +#define CRTC_H_SYNC_STRT_WID 0x0204 +# define CRTC_H_SYNC_STRT_PIX (0x07 << 0) +# define CRTC_H_SYNC_STRT_CHAR (0x3ff << 3) +# define CRTC_H_SYNC_STRT_CHAR_SHIFT 3 +# define CRTC_H_SYNC_WID (0x3f << 16) +# define CRTC_H_SYNC_WID_SHIFT 16 +# define CRTC_H_SYNC_POL (1 << 23) +#define CRTC2_H_SYNC_STRT_WID 0x0304 +# define CRTC2_H_SYNC_STRT_PIX (0x07 << 0) +# define CRTC2_H_SYNC_STRT_CHAR (0x3ff << 3) +# define CRTC2_H_SYNC_STRT_CHAR_SHIFT 3 +# define CRTC2_H_SYNC_WID (0x3f << 16) +# define CRTC2_H_SYNC_WID_SHIFT 16 +# define CRTC2_H_SYNC_POL (1 << 23) +#define CRTC_V_TOTAL_DISP 0x0208 +# define CRTC_V_TOTAL (0x07ff << 0) +# define CRTC_V_TOTAL_SHIFT 0 +# define CRTC_V_DISP (0x07ff << 16) +# define CRTC_V_DISP_SHIFT 16 +#define CRTC2_V_TOTAL_DISP 0x0308 +# define CRTC2_V_TOTAL (0x07ff << 0) +# define CRTC2_V_TOTAL_SHIFT 0 +# define CRTC2_V_DISP (0x07ff << 16) +# define CRTC2_V_DISP_SHIFT 16 +#define CRTC_V_SYNC_STRT_WID 0x020C +# define CRTC_V_SYNC_STRT (0x7ff << 0) +# define CRTC_V_SYNC_STRT_SHIFT 0 +# define CRTC_V_SYNC_WID (0x1f << 16) +# define CRTC_V_SYNC_WID_SHIFT 16 +# define CRTC_V_SYNC_POL (1 << 23) +#define CRTC2_V_SYNC_STRT_WID 0x030C +# define CRTC2_V_SYNC_STRT (0x7ff << 0) +# define CRTC2_V_SYNC_STRT_SHIFT 0 +# define CRTC2_V_SYNC_WID (0x1f << 16) +# define CRTC2_V_SYNC_WID_SHIFT 16 +# define CRTC2_V_SYNC_POL (1 << 23) +#define CRTC_VLINE_CRNT_VLINE 0x0210 +# define CRTC_CRNT_VLINE_MASK (0x7ff << 16) +#define CRTC2_VLINE_CRNT_VLINE 0x0310 +#define CRTC_CRNT_FRAME 0x0214 +#define CRTC2_CRNT_FRAME 0x0314 +#define CRTC_GUI_TRIG_VLINE 0x0218 +#define CRTC2_GUI_TRIG_VLINE 0x0318 +#define CRTC_DEBUG 0x021C +#define CRTC2_DEBUG 0x031C +#define CRTC_OFFSET_RIGHT 0x0220 +#define CRTC_OFFSET 0x0224 +#define CRTC2_OFFSET 0x0324 +#define CRTC_OFFSET_CNTL 0x0228 +# define CRTC_TILE_EN (1 << 15) +#define CRTC2_OFFSET_CNTL 0x0328 +# define CRTC2_TILE_EN (1 << 15) +#define CRTC_PITCH 0x022C +#define CRTC2_PITCH 0x032C +#define TMDS_CRC 0x02a0 +#define OVR_CLR 0x0230 +#define OVR_WID_LEFT_RIGHT 0x0234 +#define OVR_WID_TOP_BOTTOM 0x0238 +#define DISPLAY_BASE_ADDR 0x023C +#define SNAPSHOT_VH_COUNTS 0x0240 +#define SNAPSHOT_F_COUNT 0x0244 +#define N_VIF_COUNT 0x0248 +#define SNAPSHOT_VIF_COUNT 0x024C +#define FP_CRTC_H_TOTAL_DISP 0x0250 +#define FP_CRTC2_H_TOTAL_DISP 0x0350 +#define FP_CRTC_V_TOTAL_DISP 0x0254 +#define FP_CRTC2_V_TOTAL_DISP 0x0354 +# define FP_CRTC_H_TOTAL_MASK 0x000003ff +# define FP_CRTC_H_DISP_MASK 0x01ff0000 +# define FP_CRTC_V_TOTAL_MASK 0x00000fff +# define FP_CRTC_V_DISP_MASK 0x0fff0000 +# define FP_H_SYNC_STRT_CHAR_MASK 0x00001ff8 +# define FP_H_SYNC_WID_MASK 0x003f0000 +# define FP_V_SYNC_STRT_MASK 0x00000fff +# define FP_V_SYNC_WID_MASK 0x001f0000 +# define FP_CRTC_H_TOTAL_SHIFT 0x00000000 +# define FP_CRTC_H_DISP_SHIFT 0x00000010 +# define FP_CRTC_V_TOTAL_SHIFT 0x00000000 +# define FP_CRTC_V_DISP_SHIFT 0x00000010 +# define FP_H_SYNC_STRT_CHAR_SHIFT 0x00000003 +# define FP_H_SYNC_WID_SHIFT 0x00000010 +# define FP_V_SYNC_STRT_SHIFT 0x00000000 +# define FP_V_SYNC_WID_SHIFT 0x00000010 +#define CRT_CRTC_H_SYNC_STRT_WID 0x0258 +#define CRT_CRTC_V_SYNC_STRT_WID 0x025C +#define CUR_OFFSET 0x0260 +#define CUR_HORZ_VERT_POSN 0x0264 +#define CUR_HORZ_VERT_OFF 0x0268 +/* CUR_OFFSET, CUR_HORZ_VERT_POSN, CUR_HORZ_VERT_OFF bit constants */ +# define CUR_LOCK 0x80000000 +#define CUR_CLR0 0x026C +#define CUR_CLR1 0x0270 +#define CUR2_OFFSET 0x0360 +#define CUR2_HORZ_VERT_POSN 0x0364 +#define CUR2_HORZ_VERT_OFF 0x0368 +# define CUR2_LOCK (1 << 31) +#define CUR2_CLR0 0x036c +#define CUR2_CLR1 0x0370 +#define FP_HORZ_VERT_ACTIVE 0x0278 +#define CRTC_MORE_CNTL 0x027C +#define DAC_EXT_CNTL 0x0280 +#define FP_GEN_CNTL 0x0284 +/* FP_GEN_CNTL bit constants */ +# define FP_FPON (1 << 0) +# define FP_TMDS_EN (1 << 2) +# define FP_EN_TMDS (1 << 7) +# define FP_DETECT_SENSE (1 << 8) +# define FP_SEL_CRTC2 (1 << 13) +# define FP_CRTC_DONT_SHADOW_HPAR (1 << 15) +# define FP_CRTC_DONT_SHADOW_VPAR (1 << 16) +# define FP_CRTC_DONT_SHADOW_HEND (1 << 17) +# define FP_CRTC_USE_SHADOW_VEND (1 << 18) +# define FP_RMX_HVSYNC_CONTROL_EN (1 << 20) +# define FP_DFP_SYNC_SEL (1 << 21) +# define FP_CRTC_LOCK_8DOT (1 << 22) +# define FP_CRT_SYNC_SEL (1 << 23) +# define FP_USE_SHADOW_EN (1 << 24) +# define FP_CRT_SYNC_ALT (1 << 26) +#define FP2_GEN_CNTL 0x0288 +/* FP2_GEN_CNTL bit constants */ +# define FP2_FPON (1 << 0) +# define FP2_TMDS_EN (1 << 2) +# define FP2_EN_TMDS (1 << 7) +# define FP2_DETECT_SENSE (1 << 8) +# define FP2_SEL_CRTC2 (1 << 13) +# define FP2_FP_POL (1 << 16) +# define FP2_LP_POL (1 << 17) +# define FP2_SCK_POL (1 << 18) +# define FP2_LCD_CNTL_MASK (7 << 19) +# define FP2_PAD_FLOP_EN (1 << 22) +# define FP2_CRC_EN (1 << 23) +# define FP2_CRC_READ_EN (1 << 24) +#define FP_HORZ_STRETCH 0x028C +#define FP_HORZ2_STRETCH 0x038C +# define HORZ_STRETCH_RATIO_MASK 0xffff +# define HORZ_STRETCH_RATIO_MAX 4096 +# define HORZ_PANEL_SIZE (0x1ff << 16) +# define HORZ_PANEL_SHIFT 16 +# define HORZ_STRETCH_PIXREP (0 << 25) +# define HORZ_STRETCH_BLEND (1 << 26) +# define HORZ_STRETCH_ENABLE (1 << 25) +# define HORZ_AUTO_RATIO (1 << 27) +# define HORZ_FP_LOOP_STRETCH (0x7 << 28) +# define HORZ_AUTO_RATIO_INC (1 << 31) +#define FP_VERT_STRETCH 0x0290 +#define FP_VERT2_STRETCH 0x0390 +# define VERT_PANEL_SIZE (0xfff << 12) +# define VERT_PANEL_SHIFT 12 +# define VERT_STRETCH_RATIO_MASK 0xfff +# define VERT_STRETCH_RATIO_SHIFT 0 +# define VERT_STRETCH_RATIO_MAX 4096 +# define VERT_STRETCH_ENABLE (1 << 25) +# define VERT_STRETCH_LINEREP (0 << 26) +# define VERT_STRETCH_BLEND (1 << 26) +# define VERT_AUTO_RATIO_EN (1 << 27) +# define VERT_STRETCH_RESERVED 0xf1000000 +#define FP_H_SYNC_STRT_WID 0x02C4 +#define FP_H2_SYNC_STRT_WID 0x03C4 +#define FP_V_SYNC_STRT_WID 0x02C8 +#define FP_V2_SYNC_STRT_WID 0x03C8 +#define LVDS_GEN_CNTL 0x02d0 +# define LVDS_ON (1 << 0) +# define LVDS_DISPLAY_DIS (1 << 1) +# define LVDS_PANEL_TYPE (1 << 2) +# define LVDS_PANEL_FORMAT (1 << 3) +# define LVDS_EN (1 << 7) +# define LVDS_DIGON (1 << 18) +# define LVDS_BLON (1 << 19) +# define LVDS_SEL_CRTC2 (1 << 23) +#define LVDS_PLL_CNTL 0x02d4 +# define HSYNC_DELAY_SHIFT 28 +# define HSYNC_DELAY_MASK (0xf << 28) +#define AUX_WINDOW_HORZ_CNTL 0x02D8 +#define AUX_WINDOW_VERT_CNTL 0x02DC +#define DDA_CONFIG 0x02e0 +#define DDA_ON_OFF 0x02e4 + +#define GRPH_BUFFER_CNTL 0x02F0 +#define VGA_BUFFER_CNTL 0x02F4 + +/* first overlay unit (there is only one) */ + +#define OV0_Y_X_START 0x0400 +#define OV0_Y_X_END 0x0404 +#define OV0_PIPELINE_CNTL 0x0408 +#define OV0_EXCLUSIVE_HORZ 0x0408 +# define EXCL_HORZ_START_MASK 0x000000ff +# define EXCL_HORZ_END_MASK 0x0000ff00 +# define EXCL_HORZ_BACK_PORCH_MASK 0x00ff0000 +# define EXCL_HORZ_EXCLUSIVE_EN 0x80000000 +#define OV0_EXCLUSIVE_VERT 0x040C +# define EXCL_VERT_START_MASK 0x000003ff +# define EXCL_VERT_END_MASK 0x03ff0000 +#define OV0_REG_LOAD_CNTL 0x0410 +# define REG_LD_CTL_LOCK 0x00000001L +# define REG_LD_CTL_VBLANK_DURING_LOCK 0x00000002L +# define REG_LD_CTL_STALL_GUI_UNTIL_FLIP 0x00000004L +# define REG_LD_CTL_LOCK_READBACK 0x00000008L +#define OV0_SCALE_CNTL 0x0420 +# define SCALER_PIX_EXPAND 0x00000001L +# define SCALER_Y2R_TEMP 0x00000002L +#ifdef RAGE128 +# define SCALER_HORZ_PICK_NEAREST 0x00000003L +# define SCALER_VERT_PICK_NEAREST 0x00000004L +#else +# define SCALER_HORZ_PICK_NEAREST 0x00000004L +# define SCALER_VERT_PICK_NEAREST 0x00000008L +#endif +# define SCALER_SIGNED_UV 0x00000010L +# define SCALER_GAMMA_SEL_MASK 0x00000060L +# define SCALER_GAMMA_SEL_BRIGHT 0x00000000L +# define SCALER_GAMMA_SEL_G22 0x00000020L +# define SCALER_GAMMA_SEL_G18 0x00000040L +# define SCALER_GAMMA_SEL_G14 0x00000060L +# define SCALER_COMCORE_SHIFT_UP_ONE 0x00000080L +# define SCALER_SURFAC_FORMAT 0x00000f00L +# define SCALER_SOURCE_UNK0 0x00000000L /* 2 bpp ??? */ +# define SCALER_SOURCE_UNK1 0x00000100L /* 4 bpp ??? */ +# define SCALER_SOURCE_UNK2 0x00000200L /* 8 bpp ??? */ +# define SCALER_SOURCE_15BPP 0x00000300L +# define SCALER_SOURCE_16BPP 0x00000400L +/*# define SCALER_SOURCE_24BPP 0x00000500L*/ +# define SCALER_SOURCE_32BPP 0x00000600L +# define SCALER_SOURCE_UNK3 0x00000700L /* 8BPP_RGB332 ??? */ +# define SCALER_SOURCE_UNK4 0x00000800L /* 8BPP_Y8 ??? */ +# define SCALER_SOURCE_YUV9 0x00000900L /* 8BPP_RGB8 */ +# define SCALER_SOURCE_YUV12 0x00000A00L +# define SCALER_SOURCE_VYUY422 0x00000B00L +# define SCALER_SOURCE_YVYU422 0x00000C00L +# define SCALER_SOURCE_UNK5 0x00000D00L /* ??? */ +# define SCALER_SOURCE_UNK6 0x00000E00L /* 32BPP_AYUV444 */ +# define SCALER_SOURCE_UNK7 0x00000F00L /* 16BPP_ARGB4444 */ +# define SCALER_ADAPTIVE_DEINT 0x00001000L +# define R200_SCALER_TEMPORAL_DEINT 0x00002000L +# define SCALER_UNKNOWN_FLAG1 0x00004000L /* ??? */ +# define SCALER_SMART_SWITCH 0x00008000L +#ifdef RAGE128 +# define SCALER_BURST_PER_PLANE 0x00ff0000L +#else +# define SCALER_BURST_PER_PLANE 0x007f0000L +#endif +# define SCALER_DOUBLE_BUFFER 0x01000000L +# define SCALER_UNKNOWN_FLAG3 0x02000000L /* ??? */ +# define SCALER_UNKNOWN_FLAG4 0x04000000L /* ??? */ +# define SCALER_DIS_LIMIT 0x08000000L +# define SCALER_PRG_LOAD_START 0x10000000L +# define SCALER_INT_EMU 0x20000000L +# define SCALER_ENABLE 0x40000000L +# define SCALER_SOFT_RESET 0x80000000L +#define OV0_V_INC 0x0424 +#define OV0_P1_V_ACCUM_INIT 0x0428 +# define OV0_P1_MAX_LN_IN_PER_LN_OUT 0x00000003L +# define OV0_P1_V_ACCUM_INIT_MASK 0x01ff8000L +#define OV0_P23_V_ACCUM_INIT 0x042C +# define OV0_P23_MAX_LN_IN_PER_LN_OUT 0x00000003L +# define OV0_P23_V_ACCUM_INIT_MASK 0x01ff8000L +#define OV0_P1_BLANK_LINES_AT_TOP 0x0430 +# define P1_BLNK_LN_AT_TOP_M1_MASK 0x00000fffL +# define P1_ACTIVE_LINES_M1 0x0fff0000L +#define OV0_P23_BLANK_LINES_AT_TOP 0x0434 +# define P23_BLNK_LN_AT_TOP_M1_MASK 0x000007ffL +# define P23_ACTIVE_LINES_M1 0x07ff0000L +#ifndef RAGE128 +#define OV0_BASE_ADDR 0x043C +#endif +#define OV0_VID_BUF0_BASE_ADRS 0x0440 +# define VIF_BUF0_PITCH_SEL 0x00000001L +# define VIF_BUF0_TILE_ADRS 0x00000002L +# define VIF_BUF0_BASE_ADRS_MASK 0x03fffff0L +# define VIF_BUF0_1ST_LINE_LSBS_MASK 0x48000000L +#define OV0_VID_BUF1_BASE_ADRS 0x0444 +# define VIF_BUF1_PITCH_SEL 0x00000001L +# define VIF_BUF1_TILE_ADRS 0x00000002L +# define VIF_BUF1_BASE_ADRS_MASK 0x03fffff0L +# define VIF_BUF1_1ST_LINE_LSBS_MASK 0x48000000L +#define OV0_VID_BUF2_BASE_ADRS 0x0448 +# define VIF_BUF2_PITCH_SEL 0x00000001L +# define VIF_BUF2_TILE_ADRS 0x00000002L +# define VIF_BUF2_BASE_ADRS_MASK 0x03fffff0L +# define VIF_BUF2_1ST_LINE_LSBS_MASK 0x48000000L +#define OV0_VID_BUF3_BASE_ADRS 0x044C +# define VIF_BUF3_PITCH_SEL 0x00000001L +# define VIF_BUF3_TILE_ADRS 0x00000002L +# define VIF_BUF3_BASE_ADRS_MASK 0x03fffff0L +# define VIF_BUF3_1ST_LINE_LSBS_MASK 0x48000000L +#define OV0_VID_BUF4_BASE_ADRS 0x0450 +# define VIF_BUF4_PITCH_SEL 0x00000001L +# define VIF_BUF4_TILE_ADRS 0x00000002L +# define VIF_BUF4_BASE_ADRS_MASK 0x03fffff0L +# define VIF_BUF4_1ST_LINE_LSBS_MASK 0x48000000L +#define OV0_VID_BUF5_BASE_ADRS 0x0454 +# define VIF_BUF5_PITCH_SEL 0x00000001L +# define VIF_BUF5_TILE_ADRS 0x00000002L +# define VIF_BUF5_BASE_ADRS_MASK 0x03fffff0L +# define VIF_BUF5_1ST_LINE_LSBS_MASK 0x48000000L +#define OV0_VID_BUF_PITCH0_VALUE 0x0460 +#define OV0_VID_BUF_PITCH1_VALUE 0x0464 +#define OV0_AUTO_FLIP_CNTL 0x0470 +# define OV0_AUTO_FLIP_CNTL_SOFT_BUF_NUM 0x00000007 +# define OV0_AUTO_FLIP_CNTL_SOFT_REPEAT_FIELD 0x00000008 +# define OV0_AUTO_FLIP_CNTL_SOFT_BUF_ODD 0x00000010 +# define OV0_AUTO_FLIP_CNTL_IGNORE_REPEAT_FIELD 0x00000020 +# define OV0_AUTO_FLIP_CNTL_SOFT_EOF_TOGGLE 0x00000040 +# define OV0_AUTO_FLIP_CNTL_VID_PORT_SELECT 0x00000300 +# define OV0_AUTO_FLIP_CNTL_P1_FIRST_LINE_EVEN 0x00010000 +# define OV0_AUTO_FLIP_CNTL_SHIFT_EVEN_DOWN 0x00040000 +# define OV0_AUTO_FLIP_CNTL_SHIFT_ODD_DOWN 0x00080000 +# define OV0_AUTO_FLIP_CNTL_FIELD_POL_SOURCE 0x00800000 +#define OV0_DEINTERLACE_PATTERN 0x0474 +#define OV0_SUBMIT_HISTORY 0x0478 +#define OV0_H_INC 0x0480 +#define OV0_STEP_BY 0x0484 +#define OV0_P1_H_ACCUM_INIT 0x0488 +#define OV0_P23_H_ACCUM_INIT 0x048C +#define OV0_P1_X_START_END 0x0494 +#define OV0_P2_X_START_END 0x0498 +#define OV0_P3_X_START_END 0x049C +#define OV0_FILTER_CNTL 0x04A0 +# define FILTER_PROGRAMMABLE_COEF 0x00000000 +# define FILTER_HARD_SCALE_HORZ_Y 0x00000001 +# define FILTER_HARD_SCALE_HORZ_UV 0x00000002 +# define FILTER_HARD_SCALE_VERT_Y 0x00000004 +# define FILTER_HARD_SCALE_VERT_UV 0x00000008 +# define FILTER_HARDCODED_COEF 0x0000000F +# define FILTER_COEF_MASK 0x0000000F +/* When bit is set hard coded coefficients are used. */ + +/* + Top quality 4x4-tap filtered vertical and horizontal scaler. + It allows up to 64:1 upscaling and downscaling without + performance or quality degradation. +*/ +#define OV0_FOUR_TAP_COEF_0 0x04B0 +# define OV0_FOUR_TAP_PHASE_0_TAP_0 0x0000000F +# define OV0_FOUR_TAP_PHASE_0_TAP_1 0x00007F00 +# define OV0_FOUR_TAP_PHASE_0_TAP_2 0x007F0000 +# define OV0_FOUR_TAP_PHASE_0_TAP_3 0x0F000000 +#define OV0_FOUR_TAP_COEF_1 0x04B4 +# define OV0_FOUR_TAP_PHASE_1_5_TAP_0 0x0000000F +# define OV0_FOUR_TAP_PHASE_1_5_TAP_1 0x00007F00 +# define OV0_FOUR_TAP_PHASE_1_5_TAP_2 0x007F0000 +# define OV0_FOUR_TAP_PHASE_1_5_TAP_3 0x0F000000 +#define OV0_FOUR_TAP_COEF_2 0x04B8 +# define OV0_FOUR_TAP_PHASE_2_6_TAP_0 0x0000000F +# define OV0_FOUR_TAP_PHASE_2_6_TAP_1 0x00007F00 +# define OV0_FOUR_TAP_PHASE_2_6_TAP_2 0x007F0000 +# define OV0_FOUR_TAP_PHASE_2_6_TAP_3 0x0F000000 +#define OV0_FOUR_TAP_COEF_3 0x04BC +# define OV0_FOUR_TAP_PHASE_3_7_TAP_0 0x0000000F +# define OV0_FOUR_TAP_PHASE_3_7_TAP_1 0x00007F00 +# define OV0_FOUR_TAP_PHASE_3_7_TAP_2 0x007F0000 +# define OV0_FOUR_TAP_PHASE_3_7_TAP_3 0x0F000000 +#define OV0_FOUR_TAP_COEF_4 0x04C0 +# define OV0_FOUR_TAP_PHASE_4_TAP_0 0x0000000F +# define OV0_FOUR_TAP_PHASE_4_TAP_1 0x00007F00 +# define OV0_FOUR_TAP_PHASE_4_TAP_2 0x007F0000 +# define OV0_FOUR_TAP_PHASE_4_TAP_3 0x0F000000 +/* 0th_tap means that the left most of top most pixel in a set of four will + be multiplied by this coefficient. */ + +#define OV0_FLAG_CNTL 0x04DC +#ifdef RAGE128 +#define OV0_COLOUR_CNTL 0x04E0 +# define COLOUR_CNTL_BRIGHTNESS 0x0000007F +# define COLOUR_CNTL_SATURATION 0x001F1F00 +#else +/* NB: radeons have no COLOUR_CNTL register */ +#define OV0_SLICE_CNTL 0x04E0 +# define SLICE_CNTL_DISABLE 0x40000000 +#endif +/* Video and graphics keys allow alpha blending, color correction + and many other video effects */ +#define OV0_VID_KEY_CLR 0x04E4 +#define OV0_VID_KEY_MSK 0x04E8 +#define OV0_GRAPHICS_KEY_CLR 0x04EC +#define OV0_GRAPHICS_KEY_MSK 0x04F0 +#define OV0_KEY_CNTL 0x04F4 +#ifdef RAGE128 +# define VIDEO_KEY_FN_MASK 0x00000007L +# define VIDEO_KEY_FN_FALSE 0x00000000L +# define VIDEO_KEY_FN_TRUE 0x00000001L +# define VIDEO_KEY_FN_EQ 0x00000004L +# define VIDEO_KEY_FN_NE 0x00000005L +# define GRAPHIC_KEY_FN_MASK 0x00000070L +# define GRAPHIC_KEY_FN_FALSE 0x00000000L +# define GRAPHIC_KEY_FN_TRUE 0x00000010L +# define GRAPHIC_KEY_FN_EQ 0x00000040L +# define GRAPHIC_KEY_FN_NE 0x00000050L +#else +# define VIDEO_KEY_FN_MASK 0x00000003L +# define VIDEO_KEY_FN_FALSE 0x00000000L +# define VIDEO_KEY_FN_TRUE 0x00000001L +# define VIDEO_KEY_FN_EQ 0x00000002L +# define VIDEO_KEY_FN_NE 0x00000003L +# define GRAPHIC_KEY_FN_MASK 0x00000030L +# define GRAPHIC_KEY_FN_FALSE 0x00000000L +# define GRAPHIC_KEY_FN_TRUE 0x00000010L +# define GRAPHIC_KEY_FN_EQ 0x00000020L +# define GRAPHIC_KEY_FN_NE 0x00000030L +#endif +# define CMP_MIX_MASK 0x00000100L +# define CMP_MIX_OR 0x00000000L +# define CMP_MIX_AND 0x00000100L +#define OV0_TEST 0x04F8 +# define OV0_SCALER_Y2R_DISABLE 0x00000001L +# define OV0_SUBPIC_ONLY 0x00000008L +# define OV0_EXTENSE 0x00000010L +# define OV0_SWAP_UV 0x00000020L +#define OV0_COL_CONV 0x04FC +# define OV0_CB_TO_B 0x0000007FL +# define OV0_CB_TO_G 0x0000FF00L +# define OV0_CR_TO_G 0x00FF0000L +# define OV0_CR_TO_R 0x7F000000L +# define OV0_NEW_COL_CONV 0x80000000L +#define OV0_LIN_TRANS_A 0x0D20 +#define OV0_LIN_TRANS_B 0x0D24 +#define OV0_LIN_TRANS_C 0x0D28 +#define OV0_LIN_TRANS_D 0x0D2C +#define OV0_LIN_TRANS_E 0x0D30 +#define OV0_LIN_TRANS_F 0x0D34 +#define OV0_GAMMA_0_F 0x0D40 +#define OV0_GAMMA_10_1F 0x0D44 +#define OV0_GAMMA_20_3F 0x0D48 +#define OV0_GAMMA_40_7F 0x0D4C +/* These registers exist on R200 only */ +#define OV0_GAMMA_80_BF 0x0E00 +#define OV0_GAMMA_C0_FF 0x0E04 +#define OV0_GAMMA_100_13F 0x0E08 +#define OV0_GAMMA_140_17F 0x0E0C +#define OV0_GAMMA_180_1BF 0x0E10 +#define OV0_GAMMA_1C0_1FF 0x0E14 +#define OV0_GAMMA_200_23F 0x0E18 +#define OV0_GAMMA_240_27F 0x0E1C +#define OV0_GAMMA_280_2BF 0x0E20 +#define OV0_GAMMA_2C0_2FF 0x0E24 +#define OV0_GAMMA_300_33F 0x0E28 +#define OV0_GAMMA_340_37F 0x0E2C +/* End of R200 specific definitions */ +#define OV0_GAMMA_380_3BF 0x0D50 +#define OV0_GAMMA_3C0_3FF 0x0D54 + +/* + IDCT ENGINE: + It's MPEG-2 hardware decoder which incorporates run-level decode, de-zigzag + and IDCT into an IDCT engine to complement the motion compensation engine. +*/ +#define IDCT_RUNS 0x1F80 +#define IDCT_LEVELS 0x1F84 +#define IDCT_AUTH_CONTROL 0x1F88 +#define IDCT_AUTH 0x1F8C +#define IDCT_CONTROL 0x1FBC + +#define SE_MC_SRC2_CNTL 0x19D4 +# define SECONDARY_SCALE_HACC 0x00001FFFL +# define SECONDARY_SCALE_VACC 0x0FFF0000L +# define SECONDARY_SCALE_PICTH_ADJ 0xC0000000L +#define SE_MC_SRC1_CNTL 0x19D8 +# define SCALE_HACC 0x00001FFFL +# define SCALE_VACC 0x0FFF0000L +# define IDCT_EN 0x10000000L +# define SECONDARY_TEX_EN 0x20000000L +# define SCALE_PICTH_ADJ 0xC0000000L +#define SE_MC_DST_CNTL 0x19DC +# define DST_Y 0x00003FFFL +# define DST_X 0x3FFF0000L +# define DST_PITCH_ADJ 0xC0000000L +#define SE_MC_CNTL_START 0x19E0 +# define SCALE_OFFSET_PTR 0x0000000FL +# define DST_OFFSET 0x00FFFFF0L +# define ALPHA_EN 0x01000000L +# define SECONDARY_OFFSET_PTR 0x1E000000L +# define MC_DST_HEIGHT_WIDTH 0xE0000000L +#ifndef RAGE128 +#define SE_MC_BUF_BASE 0x19E4 +#define PP_MC_CONTEXT 0x19E8 +#define PP_MISC 0x1C14 +#endif +/* + SUBPICTURE UNIT: + Decompressing, scaling and alpha blending the compressed bitmap on the fly. + Provide optimal DVD subpicture qualtity. +*/ +#define SUBPIC_CNTL 0x0540 +#define SUBPIC_DEFCOLCON 0x0544 +#define SUBPIC_Y_X_START 0x054C +#define SUBPIC_Y_X_END 0x0550 +#define SUBPIC_V_INC 0x0554 +#define SUBPIC_H_INC 0x0558 +#define SUBPIC_BUF0_OFFSET 0x055C +#define SUBPIC_BUF1_OFFSET 0x0560 +#define SUBPIC_LC0_OFFSET 0x0564 +#define SUBPIC_LC1_OFFSET 0x0568 +#define SUBPIC_PITCH 0x056C +#define SUBPIC_BTN_HLI_COLCON 0x0570 +#define SUBPIC_BTN_HLI_Y_X_START 0x0574 +#define SUBPIC_BTN_HLI_Y_X_END 0x0578 +#define SUBPIC_PALETTE_INDEX 0x057C +#define SUBPIC_PALETTE_DATA 0x0580 +#define SUBPIC_H_ACCUM_INIT 0x0584 +#define SUBPIC_V_ACCUM_INIT 0x0588 + +#define CP_RB_BASE 0x0700 +#define CP_RB_CNTL 0x0704 +#define CP_RB_RPTR_ADDR 0x070C +#define CP_RB_RPTR 0x0710 +#define CP_RB_WPTR 0x0714 +#define CP_RB_WPTR_DELAY 0x0718 +#define CP_IB_BASE 0x0738 +#define CP_IB_BUFSZ 0x073C +#define CP_CSQ_CNTL 0x0740 +#define SCRATCH_UMSK 0x0770 +#define SCRATCH_ADDR 0x0774 +#ifndef RAGE128 +#define DMA_GUI_TABLE_ADDR 0x0780 +# define DMA_GUI_COMMAND__BYTE_COUNT_MASK 0x001fffff +# define DMA_GUI_COMMAND__INTDIS 0x40000000 +# define DMA_GUI_COMMAND__EOL 0x80000000 +#define DMA_GUI_SRC_ADDR 0x0784 +#define DMA_GUI_DST_ADDR 0x0788 +#define DMA_GUI_COMMAND 0x078C +#define DMA_GUI_STATUS 0x0790 +#define DMA_GUI_ACT_DSCRPTR 0x0794 +#define DMA_VID_TABLE_ADDR 0x07A0 +#define DMA_VID_SRC_ADDR 0x07A4 +#define DMA_VID_DST_ADDR 0x07A8 +#define DMA_VID_COMMAND 0x07AC +#define DMA_VID_STATUS 0x07B0 +#define DMA_VID_ACT_DSCRPTR 0x07B4 +#endif +#define CP_ME_CNTL 0x07D0 +#define CP_ME_RAM_ADDR 0x07D4 +#define CP_ME_RAM_RADDR 0x07D8 +#define CP_ME_RAM_DATAH 0x07DC +#define CP_ME_RAM_DATAL 0x07E0 +#define CP_CSQ_ADDR 0x07F0 +#define CP_CSQ_DATA 0x07F4 +#define CP_CSQ_STAT 0x07F8 + +#define DISP_MISC_CNTL 0x0D00 +# define SOFT_RESET_GRPH_PP (1 << 0) +#define DAC_MACRO_CNTL 0x0D04 +#define DISP_PWR_MAN 0x0D08 +#define DISP_TEST_DEBUG_CNTL 0x0D10 +#define DISP_HW_DEBUG 0x0D14 +#define DAC_CRC_SIG1 0x0D18 +#define DAC_CRC_SIG2 0x0D1C + +/* first capture unit */ + +#define VID_BUFFER_CONTROL 0x0900 +#define CAP_INT_CNTL 0x0908 +#define CAP_INT_STATUS 0x090C +#define FCP_CNTL 0x0910 +# define FCP_CNTL__PCICLK 0 +# define FCP_CNTL__PCLK 1 +# define FCP_CNTL__PCLKb 2 +# define FCP_CNTL__HREF 3 +# define FCP_CNTL__GND 4 +# define FCP_CNTL__HREFb 5 + +#define CAP0_BUF0_OFFSET 0x0920 +#define CAP0_BUF1_OFFSET 0x0924 +#define CAP0_BUF0_EVEN_OFFSET 0x0928 +#define CAP0_BUF1_EVEN_OFFSET 0x092C +#define CAP0_BUF_PITCH 0x0930 +#define CAP0_V_WINDOW 0x0934 +#define CAP0_H_WINDOW 0x0938 +#define CAP0_VBI0_OFFSET 0x093C +#define CAP0_VBI1_OFFSET 0x0940 +#define CAP0_VBI_V_WINDOW 0x0944 +#define CAP0_VBI_H_WINDOW 0x0948 +#define CAP0_PORT_MODE_CNTL 0x094C +#define CAP0_TRIG_CNTL 0x0950 +#define CAP0_DEBUG 0x0954 +#define CAP0_CONFIG 0x0958 +# define CAP0_CONFIG_CONTINUOS 0x00000001 +# define CAP0_CONFIG_START_FIELD_EVEN 0x00000002 +# define CAP0_CONFIG_START_BUF_GET 0x00000004 +# define CAP0_CONFIG_START_BUF_SET 0x00000008 +# define CAP0_CONFIG_BUF_TYPE_ALT 0x00000010 +# define CAP0_CONFIG_BUF_TYPE_FRAME 0x00000020 +# define CAP0_CONFIG_ONESHOT_MODE_FRAME 0x00000040 +# define CAP0_CONFIG_BUF_MODE_DOUBLE 0x00000080 +# define CAP0_CONFIG_BUF_MODE_TRIPLE 0x00000100 +# define CAP0_CONFIG_MIRROR_EN 0x00000200 +# define CAP0_CONFIG_ONESHOT_MIRROR_EN 0x00000400 +# define CAP0_CONFIG_VIDEO_SIGNED_UV 0x00000800 +# define CAP0_CONFIG_ANC_DECODE_EN 0x00001000 +# define CAP0_CONFIG_VBI_EN 0x00002000 +# define CAP0_CONFIG_SOFT_PULL_DOWN_EN 0x00004000 +# define CAP0_CONFIG_VIP_EXTEND_FLAG_EN 0x00008000 +# define CAP0_CONFIG_FAKE_FIELD_EN 0x00010000 +# define CAP0_CONFIG_ODD_ONE_MORE_LINE 0x00020000 +# define CAP0_CONFIG_EVEN_ONE_MORE_LINE 0x00040000 +# define CAP0_CONFIG_HORZ_DIVIDE_2 0x00080000 +# define CAP0_CONFIG_HORZ_DIVIDE_4 0x00100000 +# define CAP0_CONFIG_VERT_DIVIDE_2 0x00200000 +# define CAP0_CONFIG_VERT_DIVIDE_4 0x00400000 +# define CAP0_CONFIG_FORMAT_BROOKTREE 0x00000000 +# define CAP0_CONFIG_FORMAT_CCIR656 0x00800000 +# define CAP0_CONFIG_FORMAT_ZV 0x01000000 +# define CAP0_CONFIG_FORMAT_VIP 0x01800000 +# define CAP0_CONFIG_FORMAT_TRANSPORT 0x02000000 +# define CAP0_CONFIG_HORZ_DECIMATOR 0x04000000 +# define CAP0_CONFIG_VIDEO_IN_YVYU422 0x00000000 +# define CAP0_CONFIG_VIDEO_IN_VYUY422 0x20000000 +# define CAP0_CONFIG_VBI_DIVIDE_2 0x40000000 +# define CAP0_CONFIG_VBI_DIVIDE_4 0x80000000 +#define CAP0_ANC_ODD_OFFSET 0x095C +#define CAP0_ANC_EVEN_OFFSET 0x0960 +#define CAP0_ANC_H_WINDOW 0x0964 +#define CAP0_VIDEO_SYNC_TEST 0x0968 +#define CAP0_ONESHOT_BUF_OFFSET 0x096C +#define CAP0_BUF_STATUS 0x0970 +#ifdef RAGE128 +#define CAP0_DWNSC_XRATIO 0x0978 +#define CAP0_XSHARPNESS 0x097C +#else +/* #define CAP0_DWNSC_XRATIO 0x0978 */ +/* #define CAP0_XSHARPNESS 0x097C */ +#endif +#define CAP0_VBI2_OFFSET 0x0980 +#define CAP0_VBI3_OFFSET 0x0984 +#define CAP0_ANC2_OFFSET 0x0988 +#define CAP0_ANC3_OFFSET 0x098C + +/* second capture unit */ + +#define CAP1_BUF0_OFFSET 0x0990 +#define CAP1_BUF1_OFFSET 0x0994 +#define CAP1_BUF0_EVEN_OFFSET 0x0998 +#define CAP1_BUF1_EVEN_OFFSET 0x099C + +#define CAP1_BUF_PITCH 0x09A0 +#define CAP1_V_WINDOW 0x09A4 +#define CAP1_H_WINDOW 0x09A8 +#define CAP1_VBI_ODD_OFFSET 0x09AC +#define CAP1_VBI_EVEN_OFFSET 0x09B0 +#define CAP1_VBI_V_WINDOW 0x09B4 +#define CAP1_VBI_H_WINDOW 0x09B8 +#define CAP1_PORT_MODE_CNTL 0x09BC +#define CAP1_TRIG_CNTL 0x09C0 +#define CAP1_DEBUG 0x09C4 +#define CAP1_CONFIG 0x09C8 +#define CAP1_ANC_ODD_OFFSET 0x09CC +#define CAP1_ANC_EVEN_OFFSET 0x09D0 +#define CAP1_ANC_H_WINDOW 0x09D4 +#define CAP1_VIDEO_SYNC_TEST 0x09D8 +#define CAP1_ONESHOT_BUF_OFFSET 0x09DC +#define CAP1_BUF_STATUS 0x09E0 +#define CAP1_DWNSC_XRATIO 0x09E8 +#define CAP1_XSHARPNESS 0x09EC + +#define DISP_MERGE_CNTL 0x0D60 +#define DISP_OUTPUT_CNTL 0x0D64 +# define DISP_DAC_SOURCE_MASK 0x03 +# define DISP_DAC_SOURCE_CRTC2 0x01 +#define DISP_LIN_TRANS_GRPH_A 0x0D80 +#define DISP_LIN_TRANS_GRPH_B 0x0D84 +#define DISP_LIN_TRANS_GRPH_C 0x0D88 +#define DISP_LIN_TRANS_GRPH_D 0x0D8C +#define DISP_LIN_TRANS_GRPH_E 0x0D90 +#define DISP_LIN_TRANS_GRPH_F 0x0D94 +#define DISP_LIN_TRANS_VID_A 0x0D98 +#define DISP_LIN_TRANS_VID_B 0x0D9C +#define DISP_LIN_TRANS_VID_C 0x0DA0 +#define DISP_LIN_TRANS_VID_D 0x0DA4 +#define DISP_LIN_TRANS_VID_E 0x0DA8 +#define DISP_LIN_TRANS_VID_F 0x0DAC +#define RMX_HORZ_FILTER_0TAP_COEF 0x0DB0 +#define RMX_HORZ_FILTER_1TAP_COEF 0x0DB4 +#define RMX_HORZ_FILTER_2TAP_COEF 0x0DB8 +#define RMX_HORZ_PHASE 0x0DBC +#define DAC_EMBEDDED_SYNC_CNTL 0x0DC0 +#define DAC_BROAD_PULSE 0x0DC4 +#define DAC_SKEW_CLKS 0x0DC8 +#define DAC_INCR 0x0DCC +#define DAC_NEG_SYNC_LEVEL 0x0DD0 +#define DAC_POS_SYNC_LEVEL 0x0DD4 +#define DAC_BLANK_LEVEL 0x0DD8 +#define CLOCK_CNTL_INDEX 0x0008 +/* CLOCK_CNTL_INDEX bit constants */ +# define PLL_WR_EN 0x00000080 +# define PLL_DIV_SEL (3 << 8) +# define PLL2_DIV_SEL_MASK ~(3 << 8) +#define CLOCK_CNTL_DATA 0x000C +#define CP_RB_CNTL 0x0704 +#define CP_RB_BASE 0x0700 +#define CP_RB_RPTR_ADDR 0x070C +#define CP_RB_RPTR 0x0710 +#define CP_RB_WPTR 0x0714 +#define CP_RB_WPTR_DELAY 0x0718 +#define CP_IB_BASE 0x0738 +#define CP_IB_BUFSZ 0x073C +#define SCRATCH_REG0 0x15E0 +#define GUI_SCRATCH_REG0 0x15E0 +#define SCRATCH_REG1 0x15E4 +#define GUI_SCRATCH_REG1 0x15E4 +#define SCRATCH_REG2 0x15E8 +#define GUI_SCRATCH_REG2 0x15E8 +#define SCRATCH_REG3 0x15EC +#define GUI_SCRATCH_REG3 0x15EC +#define SCRATCH_REG4 0x15F0 +#define GUI_SCRATCH_REG4 0x15F0 +#define SCRATCH_REG5 0x15F4 +#define GUI_SCRATCH_REG5 0x15F4 +#define SCRATCH_UMSK 0x0770 +#define SCRATCH_ADDR 0x0774 +#define DP_BRUSH_FRGD_CLR 0x147C +#define DP_BRUSH_BKGD_CLR 0x1478 +#define DST_LINE_START 0x1600 +#define DST_LINE_END 0x1604 +#define SRC_OFFSET 0x15AC +#define SRC_PITCH 0x15B0 +#define SRC_TILE 0x1704 +#define SRC_PITCH_OFFSET 0x1428 +#define SRC_X 0x1414 +#define SRC_Y 0x1418 +#define DST_WIDTH_X 0x1588 +#define DST_HEIGHT_WIDTH_8 0x158C +#define SRC_X_Y 0x1590 +#define SRC_Y_X 0x1434 +#define DST_Y_X 0x1438 +#define DST_WIDTH_HEIGHT 0x1598 +#define DST_HEIGHT_WIDTH 0x143c +#ifdef RAGE128 +#define GUI_STAT 0x1740 +# define GUI_FIFOCNT_MASK 0x0fff +# define PM4_BUSY (1 << 16) +# define MICRO_BUSY (1 << 17) +# define FPU_BUSY (1 << 18) +# define VC_BUSY (1 << 19) +# define IDCT_BUSY (1 << 20) +# define ENG_EV_BUSY (1 << 21) +# define SETUP_BUSY (1 << 22) +# define EDGE_WALK_BUSY (1 << 23) +# define ADDRESSING_BUSY (1 << 24) +# define ENG_3D_BUSY (1 << 25) +# define ENG_2D_SM_BUSY (1 << 26) +# define ENG_2D_BUSY (1 << 27) +# define GUI_WB_BUSY (1 << 28) +# define CACHE_BUSY (1 << 29) +# define GUI_ACTIVE (1 << 31) +#endif +#define SRC_CLUT_ADDRESS 0x1780 +#define SRC_CLUT_DATA 0x1784 +#define SRC_CLUT_DATA_RD 0x1788 +#define HOST_DATA0 0x17C0 +#define HOST_DATA1 0x17C4 +#define HOST_DATA2 0x17C8 +#define HOST_DATA3 0x17CC +#define HOST_DATA4 0x17D0 +#define HOST_DATA5 0x17D4 +#define HOST_DATA6 0x17D8 +#define HOST_DATA7 0x17DC +#define HOST_DATA_LAST 0x17E0 +#define DP_SRC_ENDIAN 0x15D4 +#define DP_SRC_FRGD_CLR 0x15D8 +#define DP_SRC_BKGD_CLR 0x15DC +#define DP_WRITE_MASK 0x16cc +#define SC_LEFT 0x1640 +#define SC_RIGHT 0x1644 +#define SC_TOP 0x1648 +#define SC_BOTTOM 0x164C +#define SRC_SC_RIGHT 0x1654 +#define SRC_SC_BOTTOM 0x165C +#define DP_CNTL 0x16C0 +/* DP_CNTL bit constants */ +# define DST_X_RIGHT_TO_LEFT 0x00000000 +# define DST_X_LEFT_TO_RIGHT 0x00000001 +# define DST_Y_BOTTOM_TO_TOP 0x00000000 +# define DST_Y_TOP_TO_BOTTOM 0x00000002 +# define DST_X_MAJOR 0x00000000 +# define DST_Y_MAJOR 0x00000004 +# define DST_X_TILE 0x00000008 +# define DST_Y_TILE 0x00000010 +# define DST_LAST_PEL 0x00000020 +# define DST_TRAIL_X_RIGHT_TO_LEFT 0x00000000 +# define DST_TRAIL_X_LEFT_TO_RIGHT 0x00000040 +# define DST_TRAP_FILL_RIGHT_TO_LEFT 0x00000000 +# define DST_TRAP_FILL_LEFT_TO_RIGHT 0x00000080 +# define DST_BRES_SIGN 0x00000100 +# define DST_HOST_BIG_ENDIAN_EN 0x00000200 +# define DST_POLYLINE_NONLAST 0x00008000 +# define DST_RASTER_STALL 0x00010000 +# define DST_POLY_EDGE 0x00040000 +#define DP_CNTL_XDIR_YDIR_YMAJOR 0x16D0 +/* DP_CNTL_XDIR_YDIR_YMAJOR bit constants (short version of DP_CNTL) */ +# define DST_X_MAJOR_S 0x00000000 +# define DST_Y_MAJOR_S 0x00000001 +# define DST_Y_BOTTOM_TO_TOP_S 0x00000000 +# define DST_Y_TOP_TO_BOTTOM_S 0x00008000 +# define DST_X_RIGHT_TO_LEFT_S 0x00000000 +# define DST_X_LEFT_TO_RIGHT_S 0x80000000 +#define DP_DATATYPE 0x16C4 +/* DP_DATATYPE bit constants */ +# define DST_8BPP 0x00000002 +# define DST_15BPP 0x00000003 +# define DST_16BPP 0x00000004 +# define DST_24BPP 0x00000005 +# define DST_32BPP 0x00000006 +# define DST_8BPP_RGB332 0x00000007 +# define DST_8BPP_Y8 0x00000008 +# define DST_8BPP_RGB8 0x00000009 +# define DST_16BPP_VYUY422 0x0000000b +# define DST_16BPP_YVYU422 0x0000000c +# define DST_32BPP_AYUV444 0x0000000e +# define DST_16BPP_ARGB4444 0x0000000f +# define BRUSH_SOLIDCOLOR 0x00000d00 +# define SRC_MONO 0x00000000 +# define SRC_MONO_LBKGD 0x00010000 +# define SRC_DSTCOLOR 0x00030000 +# define BYTE_ORDER_MSB_TO_LSB 0x00000000 +# define BYTE_ORDER_LSB_TO_MSB 0x40000000 +# define DP_CONVERSION_TEMP 0x80000000 +# define HOST_BIG_ENDIAN_EN (1 << 29) +#define DP_MIX 0x16C8 +/* DP_MIX bit constants */ +# define DP_SRC_RECT 0x00000200 +# define DP_SRC_HOST 0x00000300 +# define DP_SRC_HOST_BYTEALIGN 0x00000400 +#define DP_WRITE_MSK 0x16CC +#define DP_XOP 0x17F8 +#define CLR_CMP_CLR_SRC 0x15C4 +#define CLR_CMP_CLR_DST 0x15C8 +#define CLR_CMP_CNTL 0x15C0 +/* CLR_CMP_CNTL bit constants */ +# define COMPARE_SRC_FALSE 0x00000000 +# define COMPARE_SRC_TRUE 0x00000001 +# define COMPARE_SRC_NOT_EQUAL 0x00000004 +# define COMPARE_SRC_EQUAL 0x00000005 +# define COMPARE_SRC_EQUAL_FLIP 0x00000007 +# define COMPARE_DST_FALSE 0x00000000 +# define COMPARE_DST_TRUE 0x00000100 +# define COMPARE_DST_NOT_EQUAL 0x00000400 +# define COMPARE_DST_EQUAL 0x00000500 +# define COMPARE_DESTINATION 0x00000000 +# define COMPARE_SOURCE 0x01000000 +# define COMPARE_SRC_AND_DST 0x02000000 +#define CLR_CMP_MSK 0x15CC +#define DSTCACHE_MODE 0x1710 +#define DSTCACHE_CTLSTAT 0x1714 +/* DSTCACHE_CTLSTAT bit constants */ +# define RB2D_DC_FLUSH (3 << 0) +# define RB2D_DC_FLUSH_ALL 0xf +# define RB2D_DC_BUSY (1 << 31) +#define DEFAULT_OFFSET 0x16e0 +#define DEFAULT_PITCH_OFFSET 0x16E0 +#define DEFAULT_SC_BOTTOM_RIGHT 0x16E8 +/* DEFAULT_SC_BOTTOM_RIGHT bit constants */ +# define DEFAULT_SC_RIGHT_MAX (0x1fff << 0) +# define DEFAULT_SC_BOTTOM_MAX (0x1fff << 16) +#define DP_GUI_MASTER_CNTL 0x146C +/* DP_GUI_MASTER_CNTL bit constants */ +# define GMC_SRC_PITCH_OFFSET_DEFAULT 0x00000000 +# define GMC_SRC_PITCH_OFFSET_LEAVE 0x00000001 +# define GMC_DST_PITCH_OFFSET_DEFAULT 0x00000000 +# define GMC_DST_PITCH_OFFSET_LEAVE 0x00000002 +# define GMC_SRC_CLIP_DEFAULT 0x00000000 +# define GMC_SRC_CLIP_LEAVE 0x00000004 +# define GMC_DST_CLIP_DEFAULT 0x00000000 +# define GMC_DST_CLIP_LEAVE 0x00000008 +# define GMC_BRUSH_8x8MONO 0x00000000 +# define GMC_BRUSH_8x8MONO_LBKGD 0x00000010 +# define GMC_BRUSH_8x1MONO 0x00000020 +# define GMC_BRUSH_8x1MONO_LBKGD 0x00000030 +# define GMC_BRUSH_1x8MONO 0x00000040 +# define GMC_BRUSH_1x8MONO_LBKGD 0x00000050 +# define GMC_BRUSH_32x1MONO 0x00000060 +# define GMC_BRUSH_32x1MONO_LBKGD 0x00000070 +# define GMC_BRUSH_32x32MONO 0x00000080 +# define GMC_BRUSH_32x32MONO_LBKGD 0x00000090 +# define GMC_BRUSH_8x8COLOR 0x000000a0 +# define GMC_BRUSH_8x1COLOR 0x000000b0 +# define GMC_BRUSH_1x8COLOR 0x000000c0 +# define GMC_BRUSH_SOLID_COLOR 0x000000d0 +# define GMC_DST_8BPP 0x00000200 +# define GMC_DST_15BPP 0x00000300 +# define GMC_DST_16BPP 0x00000400 +# define GMC_DST_24BPP 0x00000500 +# define GMC_DST_32BPP 0x00000600 +# define GMC_DST_8BPP_RGB332 0x00000700 +# define GMC_DST_8BPP_Y8 0x00000800 +# define GMC_DST_8BPP_RGB8 0x00000900 +# define GMC_DST_16BPP_VYUY422 0x00000b00 +# define GMC_DST_16BPP_YVYU422 0x00000c00 +# define GMC_DST_32BPP_AYUV444 0x00000e00 +# define GMC_DST_16BPP_ARGB4444 0x00000f00 +# define GMC_SRC_MONO 0x00000000 +# define GMC_SRC_MONO_LBKGD 0x00001000 +# define GMC_SRC_DSTCOLOR 0x00003000 +# define GMC_BYTE_ORDER_MSB_TO_LSB 0x00000000 +# define GMC_BYTE_ORDER_LSB_TO_MSB 0x00004000 +# define GMC_DP_CONVERSION_TEMP_9300 0x00008000 +# define GMC_DP_CONVERSION_TEMP_6500 0x00000000 +# define GMC_DP_SRC_RECT 0x02000000 +# define GMC_DP_SRC_HOST 0x03000000 +# define GMC_DP_SRC_HOST_BYTEALIGN 0x04000000 +# define GMC_3D_FCN_EN_CLR 0x00000000 +# define GMC_3D_FCN_EN_SET 0x08000000 +# define GMC_DST_CLR_CMP_FCN_LEAVE 0x00000000 +# define GMC_DST_CLR_CMP_FCN_CLEAR 0x10000000 +# define GMC_AUX_CLIP_LEAVE 0x00000000 +# define GMC_AUX_CLIP_CLEAR 0x20000000 +# define GMC_WRITE_MASK_LEAVE 0x00000000 +# define GMC_WRITE_MASK_SET 0x40000000 +# define GMC_CLR_CMP_CNTL_DIS (1 << 28) +# define GMC_SRC_DATATYPE_COLOR (3 << 12) +# define ROP3_S 0x00cc0000 +# define ROP3_SRCCOPY 0x00cc0000 +# define ROP3_P 0x00f00000 +# define ROP3_PATCOPY 0x00f00000 +# define DP_SRC_SOURCE_MASK (7 << 24) +# define GMC_BRUSH_NONE (15 << 4) +# define DP_SRC_SOURCE_MEMORY (2 << 24) +# define GMC_BRUSH_SOLIDCOLOR 0x000000d0 +#define SC_TOP_LEFT 0x16EC +#define SC_BOTTOM_RIGHT 0x16F0 +#define SRC_SC_BOTTOM_RIGHT 0x16F4 +#define RB2D_DSTCACHE_CTLSTAT 0x342C +#define RB2D_DSTCACHE_MODE 0x3428 + +#define BASE_CODE 0x0f0b/*0x0f08*/ +#define RADEON_BIOS_0_SCRATCH 0x0010 +#define RADEON_BIOS_1_SCRATCH 0x0014 +#define RADEON_BIOS_2_SCRATCH 0x0018 +#define RADEON_BIOS_3_SCRATCH 0x001c +#define RADEON_BIOS_4_SCRATCH 0x0020 +#define RADEON_BIOS_5_SCRATCH 0x0024 +#define RADEON_BIOS_6_SCRATCH 0x0028 +#define RADEON_BIOS_7_SCRATCH 0x002c + + +#define CLK_PIN_CNTL 0x0001 +#define PPLL_CNTL 0x0002 +# define PPLL_RESET (1 << 0) +# define PPLL_SLEEP (1 << 1) +# define PPLL_ATOMIC_UPDATE_EN (1 << 16) +# define PPLL_VGA_ATOMIC_UPDATE_EN (1 << 17) +# define PPLL_ATOMIC_UPDATE_VSYNC (1 << 18) +#define PPLL_REF_DIV 0x0003 +# define PPLL_REF_DIV_MASK 0x03ff +# define PPLL_ATOMIC_UPDATE_R (1 << 15) /* same as _W */ +# define PPLL_ATOMIC_UPDATE_W (1 << 15) /* same as _R */ +#define PPLL_DIV_0 0x0004 +#define PPLL_DIV_1 0x0005 +#define PPLL_DIV_2 0x0006 +#define PPLL_DIV_3 0x0007 +#define VCLK_ECP_CNTL 0x0008 +# define VCLK_SRC_SEL_MASK 0x03 +# define VCLK_SRC_SEL_CPUCLK 0x00 +# define VCLK_SRC_SEL_PSCANCLK 0x01 +# define VCLK_SRC_SEL_BYTECLK 0x02 +# define VCLK_SRC_SEL_PPLLCLK 0x03 +#define HTOTAL_CNTL 0x0009 +#define HTOTAL2_CNTL 0x002e /* PLL */ +#define M_SPLL_REF_FB_DIV 0x000a +#define AGP_PLL_CNTL 0x000b +#define SPLL_CNTL 0x000c +#define SCLK_CNTL 0x000d +# define DYN_STOP_LAT_MASK 0x00007ff8 +# define CP_MAX_DYN_STOP_LAT 0x0008 +# define SCLK_FORCEON_MASK 0xffff8000 +#define SCLK_MORE_CNTL 0x0035 /* PLL */ +# define SCLK_MORE_FORCEON 0x0700 +#define MPLL_CNTL 0x000e +#ifdef RAGE128 +#define MCLK_CNTL 0x000f /* PLL */ +# define FORCE_GCP (1 << 16) +# define FORCE_PIPE3D_CP (1 << 17) +# define FORCE_RCP (1 << 18) +#else +#define MCLK_CNTL 0x0012 +/* MCLK_CNTL bit constants */ +# define FORCEON_MCLKA (1 << 16) +# define FORCEON_MCLKB (1 << 17) +# define FORCEON_YCLKA (1 << 18) +# define FORCEON_YCLKB (1 << 19) +# define FORCEON_MC (1 << 20) +# define FORCEON_AIC (1 << 21) +#endif +#define PLL_TEST_CNTL 0x0013 +#define P2PLL_CNTL 0x002a /* P2PLL */ +# define P2PLL_RESET (1 << 0) +# define P2PLL_SLEEP (1 << 1) +# define P2PLL_ATOMIC_UPDATE_EN (1 << 16) +# define P2PLL_VGA_ATOMIC_UPDATE_EN (1 << 17) +# define P2PLL_ATOMIC_UPDATE_VSYNC (1 << 18) +#define P2PLL_DIV_0 0x002c +# define P2PLL_FB0_DIV_MASK 0x07ff +# define P2PLL_POST0_DIV_MASK 0x00070000 +#define P2PLL_REF_DIV 0x002B /* PLL */ +# define P2PLL_REF_DIV_MASK 0x03ff +# define P2PLL_ATOMIC_UPDATE_R (1 << 15) /* same as _W */ +# define P2PLL_ATOMIC_UPDATE_W (1 << 15) /* same as _R */ +#define PIXCLKS_CNTL 0x002d +# define PIX2CLK_SRC_SEL_MASK 0x03 +# define PIX2CLK_SRC_SEL_CPUCLK 0x00 +# define PIX2CLK_SRC_SEL_PSCANCLK 0x01 +# define PIX2CLK_SRC_SEL_BYTECLK 0x02 +# define PIX2CLK_SRC_SEL_P2PLLCLK 0x03 + +/* masks */ + +#define CONFIG_MEMSIZE_MASK 0x1f000000 +#define MEM_CFG_TYPE 0x40000000 +#define DST_OFFSET_MASK 0x003fffff +#define DST_PITCH_MASK 0x3fc00000 +#define DEFAULT_TILE_MASK 0xc0000000 +#define PPLL_DIV_SEL_MASK 0x00000300 +#define PPLL_FB3_DIV_MASK 0x000007ff +#define PPLL_POST3_DIV_MASK 0x00070000 + +/* BUS MASTERING */ +#ifdef RAGE128 +#define BM_FRAME_BUF_OFFSET 0xA00 +#define BM_SYSTEM_MEM_ADDR 0xA04 +#define BM_COMMAND 0xA08 +# define BM_INTERRUPT_DIS 0x08000000 +# define BM_TRANSFER_DEST_REG 0x10000000 +# define BM_FORCE_TO_PCI 0x20000000 +# define BM_FRAME_OFFSET_HOLD 0x40000000 +# define BM_END_OF_LIST 0x80000000 +#define BM_STATUS 0xA0c +#define BM_QUEUE_STATUS 0xA10 +#define BM_QUEUE_FREE_STATUS 0xA14 +#define BM_CHUNK_0_VAL 0xA18 +# define BM_PTR_FORCE_TO_PCI 0x00200000 +# define BM_PM4_RD_FORCE_TO_PCI 0x00400000 +# define BM_GLOBAL_FORCE_TO_PCI 0x00800000 +# define BM_VIP3_NOCHUNK 0x10000000 +# define BM_VIP2_NOCHUNK 0x20000000 +# define BM_VIP1_NOCHUNK 0x40000000 +# define BM_VIP0_NOCHUNK 0x80000000 +#define BM_CHUNK_1_VAL 0xA1C +#define BM_VIP0_BUF 0xA20 +# define SYSTEM_TRIGGER_SYSTEM_TO_VIDEO 0x0 +# define SYSTEM_TRIGGER_VIDEO_TO_SYSTEM 0x1 +#define BM_VIP0_ACTIVE 0xA24 +#define BM_VIP1_BUF 0xA30 +#define BM_VIP1_ACTIVE 0xA34 +#define BM_VIP2_BUF 0xA40 +#define BM_VIP2_ACTIVE 0xA44 +#define BM_VIP3_BUF 0xA50 +#define BM_VIP3_ACTIVE 0xA54 +#define BM_VIDCAP_BUF0 0xA60 +#define BM_VIDCAP_BUF1 0xA64 +#define BM_VIDCAP_BUF2 0xA68 +#define BM_VIDCAP_ACTIVE 0xA6c +#define BM_GUI 0xA80 +#define BM_ABORT 0xA88 +#endif +/* RAGE THEATER REGISTERS */ + +#define DMA_VIPH0_COMMAND 0x0A00 +#define DMA_VIPH1_COMMAND 0x0A04 +#define DMA_VIPH2_COMMAND 0x0A08 +#define DMA_VIPH3_COMMAND 0x0A0C +#define DMA_VIPH_STATUS 0x0A10 +#define DMA_VIPH_CHUNK_0 0x0A18 +#define DMA_VIPH_CHUNK_1_VAL 0x0A1C +#define DMA_VIP0_TABLE_ADDR 0x0A20 +#define DMA_VIPH0_ACTIVE 0x0A24 +#define DMA_VIP1_TABLE_ADDR 0x0A30 +#define DMA_VIPH1_ACTIVE 0x0A34 +#define DMA_VIP2_TABLE_ADDR 0x0A40 +#define DMA_VIPH2_ACTIVE 0x0A44 +#define DMA_VIP3_TABLE_ADDR 0x0A50 +#define DMA_VIPH3_ACTIVE 0x0A54 +#define DMA_VIPH_ABORT 0x0A88 + +#define VIPH_CH0_DATA 0x0c00 +#define VIPH_CH1_DATA 0x0c04 +#define VIPH_CH2_DATA 0x0c08 +#define VIPH_CH3_DATA 0x0c0c +#define VIPH_CH0_ADDR 0x0c10 +#define VIPH_CH1_ADDR 0x0c14 +#define VIPH_CH2_ADDR 0x0c18 +#define VIPH_CH3_ADDR 0x0c1c +#define VIPH_CH0_SBCNT 0x0c20 +#define VIPH_CH1_SBCNT 0x0c24 +#define VIPH_CH2_SBCNT 0x0c28 +#define VIPH_CH3_SBCNT 0x0c2c +#define VIPH_CH0_ABCNT 0x0c30 +#define VIPH_CH1_ABCNT 0x0c34 +#define VIPH_CH2_ABCNT 0x0c38 +#define VIPH_CH3_ABCNT 0x0c3c +#define VIPH_CONTROL 0x0c40 +#define VIPH_DV_LAT 0x0c44 +#define VIPH_BM_CHUNK 0x0c48 +#define VIPH_DV_INT 0x0c4c +#define VIPH_TIMEOUT_STAT 0x0c50 + +#define VIPH_REG_DATA 0x0084 +#define VIPH_REG_ADDR 0x0080 + +/* Address Space Rage Theatre Registers (VIP Access) */ +#define VIP_VIP_VENDOR_DEVICE_ID 0x0000 +#define VIP_VIP_SUB_VENDOR_DEVICE_ID 0x0004 +#define VIP_VIP_COMMAND_STATUS 0x0008 +#define VIP_VIP_REVISION_ID 0x000c +#define VIP_HW_DEBUG 0x0010 +#define VIP_SW_SCRATCH 0x0014 +#define VIP_I2C_CNTL_0 0x0020 +#define VIP_I2C_CNTL_1 0x0024 +#define VIP_I2C_DATA 0x0028 +#define VIP_INT_CNTL 0x002c +#define VIP_GPIO_INOUT 0x0030 +#define VIP_GPIO_CNTL 0x0034 +#define VIP_CLKOUT_GPIO_CNTL 0x0038 +#define VIP_RIPINTF_PORT_CNTL 0x003c +#define VIP_ADC_CNTL 0x0400 +#define VIP_ADC_DEBUG 0x0404 +#define VIP_STANDARD_SELECT 0x0408 +#define VIP_THERMO2BIN_STATUS 0x040c +#define VIP_COMB_CNTL0 0x0440 +#define VIP_COMB_CNTL1 0x0444 +#define VIP_COMB_CNTL2 0x0448 +#define VIP_COMB_LINE_LENGTH 0x044c +#define VIP_NOISE_CNTL0 0x0450 +#define VIP_HS_PLINE 0x0480 +#define VIP_HS_DTOINC 0x0484 +#define VIP_HS_PLLGAIN 0x0488 +#define VIP_HS_MINMAXWIDTH 0x048c +#define VIP_HS_GENLOCKDELAY 0x0490 +#define VIP_HS_WINDOW_LIMIT 0x0494 +#define VIP_HS_WINDOW_OC_SPEED 0x0498 +#define VIP_HS_PULSE_WIDTH 0x049c +#define VIP_HS_PLL_ERROR 0x04a0 +#define VIP_HS_PLL_FS_PATH 0x04a4 +#define VIP_SG_BLACK_GATE 0x04c0 +#define VIP_SG_SYNCTIP_GATE 0x04c4 +#define VIP_SG_UVGATE_GATE 0x04c8 +#define VIP_LP_AGC_CLAMP_CNTL0 0x0500 +#define VIP_LP_AGC_CLAMP_CNTL1 0x0504 +#define VIP_LP_BRIGHTNESS 0x0508 +#define VIP_LP_CONTRAST 0x050c +#define VIP_LP_SLICE_LIMIT 0x0510 +#define VIP_LP_WPA_CNTL0 0x0514 +#define VIP_LP_WPA_CNTL1 0x0518 +#define VIP_LP_BLACK_LEVEL 0x051c +#define VIP_LP_SLICE_LEVEL 0x0520 +#define VIP_LP_SYNCTIP_LEVEL 0x0524 +#define VIP_LP_VERT_LOCKOUT 0x0528 +#define VIP_VS_DETECTOR_CNTL 0x0540 +#define VIP_VS_BLANKING_CNTL 0x0544 +#define VIP_VS_FIELD_ID_CNTL 0x0548 +#define VIP_VS_COUNTER_CNTL 0x054c +#define VIP_VS_FRAME_TOTAL 0x0550 +#define VIP_VS_LINE_COUNT 0x0554 +#define VIP_CP_PLL_CNTL0 0x0580 +#define VIP_CP_PLL_CNTL1 0x0584 +#define VIP_CP_HUE_CNTL 0x0588 +#define VIP_CP_BURST_GAIN 0x058c +#define VIP_CP_AGC_CNTL 0x0590 +#define VIP_CP_ACTIVE_GAIN 0x0594 +#define VIP_CP_PLL_STATUS0 0x0598 +#define VIP_CP_PLL_STATUS1 0x059c +#define VIP_CP_PLL_STATUS2 0x05a0 +#define VIP_CP_PLL_STATUS3 0x05a4 +#define VIP_CP_PLL_STATUS4 0x05a8 +#define VIP_CP_PLL_STATUS5 0x05ac +#define VIP_CP_PLL_STATUS6 0x05b0 +#define VIP_CP_PLL_STATUS7 0x05b4 +#define VIP_CP_DEBUG_FORCE 0x05b8 +#define VIP_CP_VERT_LOCKOUT 0x05bc +#define VIP_H_ACTIVE_WINDOW 0x05c0 +#define VIP_V_ACTIVE_WINDOW 0x05c4 +#define VIP_H_VBI_WINDOW 0x05c8 +#define VIP_V_VBI_WINDOW 0x05cc +#define VIP_VBI_CONTROL 0x05d0 +#define VIP_DECODER_DEBUG_CNTL 0x05d4 +#define VIP_SINGLE_STEP_DATA 0x05d8 +#define VIP_MASTER_CNTL 0x0040 +#define VIP_RGB_CNTL 0x0048 +#define VIP_CLKOUT_CNTL 0x004c +#define VIP_SYNC_CNTL 0x0050 +#define VIP_I2C_CNTL 0x0054 +#define VIP_HTOTAL 0x0080 +#define VIP_HDISP 0x0084 +#define VIP_HSIZE 0x0088 +#define VIP_HSTART 0x008c +#define VIP_HCOUNT 0x0090 +#define VIP_VTOTAL 0x0094 +#define VIP_VDISP 0x0098 +#define VIP_VCOUNT 0x009c +#define VIP_VFTOTAL 0x00a0 +#define VIP_DFCOUNT 0x00a4 +#define VIP_DFRESTART 0x00a8 +#define VIP_DHRESTART 0x00ac +#define VIP_DVRESTART 0x00b0 +#define VIP_SYNC_SIZE 0x00b4 +#define VIP_TV_PLL_FINE_CNTL 0x00b8 +#define VIP_CRT_PLL_FINE_CNTL 0x00bc +#define VIP_TV_PLL_CNTL 0x00c0 +#define VIP_CRT_PLL_CNTL 0x00c4 +#define VIP_PLL_CNTL0 0x00c8 +#define VIP_PLL_TEST_CNTL 0x00cc +#define VIP_CLOCK_SEL_CNTL 0x00d0 +#define VIP_VIN_PLL_CNTL 0x00d4 +#define VIP_VIN_PLL_FINE_CNTL 0x00d8 +#define VIP_AUD_PLL_CNTL 0x00e0 +#define VIP_AUD_PLL_FINE_CNTL 0x00e4 +#define VIP_AUD_CLK_DIVIDERS 0x00e8 +#define VIP_AUD_DTO_INCREMENTS 0x00ec +#define VIP_L54_PLL_CNTL 0x00f0 +#define VIP_L54_PLL_FINE_CNTL 0x00f4 +#define VIP_L54_DTO_INCREMENTS 0x00f8 +#define VIP_PLL_CNTL1 0x00fc +#define VIP_FRAME_LOCK_CNTL 0x0100 +#define VIP_SYNC_LOCK_CNTL 0x0104 +#define VIP_TVO_SYNC_PAT_ACCUM 0x0108 +#define VIP_TVO_SYNC_THRESHOLD 0x010c +#define VIP_TVO_SYNC_PAT_EXPECT 0x0110 +#define VIP_DELAY_ONE_MAP_A 0x0114 +#define VIP_DELAY_ONE_MAP_B 0x0118 +#define VIP_DELAY_ZERO_MAP_A 0x011c +#define VIP_DELAY_ZERO_MAP_B 0x0120 +#define VIP_TVO_DATA_DELAY_A 0x0140 +#define VIP_TVO_DATA_DELAY_B 0x0144 +#define VIP_HOST_READ_DATA 0x0180 +#define VIP_HOST_WRITE_DATA 0x0184 +#define VIP_HOST_RD_WT_CNTL 0x0188 +#define VIP_VSCALER_CNTL1 0x01c0 +#define VIP_TIMING_CNTL 0x01c4 +#define VIP_VSCALER_CNTL2 0x01c8 +#define VIP_Y_FALL_CNTL 0x01cc +#define VIP_Y_RISE_CNTL 0x01d0 +#define VIP_Y_SAW_TOOTH_CNTL 0x01d4 +#define VIP_UPSAMP_AND_GAIN_CNTL 0x01e0 +#define VIP_GAIN_LIMIT_SETTINGS 0x01e4 +#define VIP_LINEAR_GAIN_SETTINGS 0x01e8 +#define VIP_MODULATOR_CNTL1 0x0200 +#define VIP_MODULATOR_CNTL2 0x0204 +#define VIP_MV_MODE_CNTL 0x0208 +#define VIP_MV_STRIPE_CNTL 0x020c +#define VIP_MV_LEVEL_CNTL1 0x0210 +#define VIP_MV_LEVEL_CNTL2 0x0214 +#define VIP_PRE_DAC_MUX_CNTL 0x0240 +#define VIP_TV_DAC_CNTL 0x0280 +#define VIP_CRC_CNTL 0x02c0 +#define VIP_VIDEO_PORT_SIG 0x02c4 +#define VIP_VBI_CC_CNTL 0x02c8 +#define VIP_VBI_EDS_CNTL 0x02cc +#define VIP_VBI_20BIT_CNTL 0x02d0 +#define VIP_VBI_DTO_CNTL 0x02d4 +#define VIP_VBI_LEVEL_CNTL 0x02d8 +#define VIP_UV_ADR 0x0300 +#define VIP_MV_STATUS 0x0330 +#define VIP_UPSAMP_COEFF0_0 0x0340 +#define VIP_UPSAMP_COEFF0_1 0x0344 +#define VIP_UPSAMP_COEFF0_2 0x0348 +#define VIP_UPSAMP_COEFF1_0 0x034c +#define VIP_UPSAMP_COEFF1_1 0x0350 +#define VIP_UPSAMP_COEFF1_2 0x0354 +#define VIP_UPSAMP_COEFF2_0 0x0358 +#define VIP_UPSAMP_COEFF2_1 0x035c +#define VIP_UPSAMP_COEFF2_2 0x0360 +#define VIP_UPSAMP_COEFF3_0 0x0364 +#define VIP_UPSAMP_COEFF3_1 0x0368 +#define VIP_UPSAMP_COEFF3_2 0x036c +#define VIP_UPSAMP_COEFF4_0 0x0370 +#define VIP_UPSAMP_COEFF4_1 0x0374 +#define VIP_UPSAMP_COEFF4_2 0x0378 +#define VIP_TV_DTO_INCREMENTS 0x0390 +#define VIP_CRT_DTO_INCREMENTS 0x0394 +#define VIP_VSYNC_DIFF_CNTL 0x03a0 +#define VIP_VSYNC_DIFF_LIMITS 0x03a4 +#define VIP_VSYNC_DIFF_RD_DATA 0x03a8 +#define VIP_SCALER_IN_WINDOW 0x0618 +#define VIP_SCALER_OUT_WINDOW 0x061c +#define VIP_H_SCALER_CONTROL 0x0600 +#define VIP_V_SCALER_CONTROL 0x0604 +#define VIP_V_DEINTERLACE_CONTROL 0x0608 +#define VIP_VBI_SCALER_CONTROL 0x060c +#define VIP_DVS_PORT_CTRL 0x0610 +#define VIP_DVS_PORT_READBACK 0x0614 +#define VIP_FIFOA_CONFIG 0x0800 +#define VIP_FIFOB_CONFIG 0x0804 +#define VIP_FIFOC_CONFIG 0x0808 +#define VIP_SPDIF_PORT_CNTL 0x080c +#define VIP_SPDIF_CHANNEL_STAT 0x0810 +#define VIP_SPDIF_AC3_PREAMBLE 0x0814 +#define VIP_I2S_TRANSMIT_CNTL 0x0818 +#define VIP_I2S_RECEIVE_CNTL 0x081c +#define VIP_SPDIF_TX_CNT_REG 0x0820 +#define VIP_IIS_TX_CNT_REG 0x0824 + +/* Status defines */ +#define VIP_BUSY 0 +#define VIP_IDLE 1 +#define VIP_RESET 2 + +#define VIPH_TIMEOUT_STAT__VIPH_REG_STAT 0x00000010 +#define VIPH_TIMEOUT_STAT__VIPH_REG_AK 0x00000010 +#define VIPH_TIMEOUT_STAT__VIPH_REGR_DIS 0x01000000 +#define TEST_DEBUG_CNTL__TEST_DEBUG_OUT_EN 0x00000001 + +#define RT_ATI_ID 0x4D541002 + +/* Register/Field values: */ +#define RT_COMP0 0x0 +#define RT_COMP1 0x1 +#define RT_COMP2 0x2 +#define RT_YF_COMP3 0x3 +#define RT_YR_COMP3 0x4 +#define RT_YCF_COMP4 0x5 +#define RT_YCR_COMP4 0x6 + +/* Video standard defines */ +#define RT_NTSC 0x0 +#define RT_PAL 0x1 +#define RT_SECAM 0x2 +#define extNONE 0x0000 +#define extNTSC 0x0100 +#define extRsvd 0x0200 +#define extPAL 0x0300 +#define extPAL_M 0x0400 +#define extPAL_N 0x0500 +#define extSECAM 0x0600 +#define extPAL_NCOMB 0x0700 +#define extNTSC_J 0x0800 +#define extNTSC_443 0x0900 +#define extPAL_BGHI 0x0A00 +#define extPAL_60 0x0B00 + /* these are used in MSP3430 */ +#define extPAL_DK1 0x0C00 +#define extPAL_AUTO 0x0D00 + +#define RT_FREF_2700 6 +#define RT_FREF_2950 5 + +#define RT_COMPOSITE 0x0 +#define RT_SVIDEO 0x1 + +#define RT_NORM_SHARPNESS 0x03 +#define RT_HIGH_SHARPNESS 0x0F + +#define RT_HUE_PAL_DEF 0x00 + +#define RT_DECINTERLACED 0x1 +#define RT_DECNONINTERLACED 0x0 + +#define NTSC_LINES 525 +#define PAL_SECAM_LINES 625 + +#define RT_ASYNC_ENABLE 0x0 +#define RT_ASYNC_DISABLE 0x1 +#define RT_ASYNC_RESET 0x1 + +#define RT_VINRST_ACTIVE 0x0 +#define RT_VINRST_RESET 0x1 +#define RT_L54RST_RESET 0x1 + +#define RT_REF_CLK 0x0 +#define RT_PLL_VIN_CLK 0x1 + +#define RT_VIN_ASYNC_RST 0x20 +#define RT_DVS_ASYNC_RST 0x80 + +#define RT_ADC_ENABLE 0x0 +#define RT_ADC_DISABLE 0x1 + +#define RT_DVSDIR_IN 0x0 +#define RT_DVSDIR_OUT 0x1 + +#define RT_DVSCLK_HIGH 0x0 +#define RT_DVSCLK_LOW 0x1 + +#define RT_DVSCLK_SEL_8FS 0x0 +#define RT_DVSCLK_SEL_27MHZ 0x1 + +#define RT_DVS_CONTSTREAM 0x1 +#define RT_DVS_NONCONTSTREAM 0x0 + +#define RT_DVSDAT_HIGH 0x0 +#define RT_DVSDAT_LOW 0x1 + +#define RT_ADC_CNTL_DEFAULT 0x03252338 + +/* COMB_CNTL0 FILTER SETTINGS FOR DIFFERENT STANDARDS: */ +#define RT_NTSCM_COMB_CNTL0_COMPOSITE 0x09438090 +#define RT_NTSCM_COMB_CNTL0_SVIDEO 0x48540000 + +#define RT_PAL_COMB_CNTL0_COMPOSITE 0x09438090 +#define RT_PAL_COMB_CNTL0_SVIDEO 0x40348090 + +#define RT_SECAM_COMB_CNTL0_COMPOSITE 0xD0108090 /* instead of orig 0xD0088090 - eric*/ +#define RT_SECAM_COMB_CNTL0_SVIDEO 0x50148090 + +#define RT_PALN_COMB_CNTL0_COMPOSITE 0x09438090 +#define RT_PALN_COMB_CNTL0_SVIDEO 0x40348090 + +#define RT_PALM_COMB_CNTL0_COMPOSITE 0x09438090 +#define RT_PALM_COMB_CNTL0_SVIDEO 0x40348090 +/* End of filter settings. */ + +/* COMB_CNTL1 FILTER SETTINGS FOR DIFFERENT STANDARDS: */ +#define RT_NTSCM_COMB_CNTL1_COMPOSITE 0x00000010 +#define RT_NTSCM_COMB_CNTL1_SVIDEO 0x00000081 + +#define RT_PAL_COMB_CNTL1_COMPOSITE 0x00000010 +#define RT_PAL_COMB_CNTL1_SVIDEO 0x000000A1 + +#define RT_SECAM_COMB_CNTL1_COMPOSITE 0x00000091 +#define RT_SECAM_COMB_CNTL1_SVIDEO 0x00000081 + +#define RT_PALN_COMB_CNTL1_COMPOSITE 0x00000010 +#define RT_PALN_COMB_CNTL1_SVIDEO 0x000000A1 + +#define RT_PALM_COMB_CNTL1_COMPOSITE 0x00000010 +#define RT_PALM_COMB_CNTL1_SVIDEO 0x000000A1 +/* End of filter settings. */ + +/* COMB_CNTL2 FILTER SETTINGS FOR DIFFERENT STANDARDS: */ +#define RT_NTSCM_COMB_CNTL2_COMPOSITE 0x16161010 +#define RT_NTSCM_COMB_CNTL2_SVIDEO 0xFFFFFFFF + +#define RT_PAL_COMB_CNTL2_COMPOSITE 0x06080102 /* instead of 0x16161010 - Ivo */ +#define RT_PAL_COMB_CNTL2_SVIDEO 0x06080102 + +#define RT_SECAM_COMB_CNTL2_COMPOSITE 0xffffffff /* instead of 0x06080102 - eric */ +#define RT_SECAM_COMB_CNTL2_SVIDEO 0x06080102 + +#define RT_PALN_COMB_CNTL2_COMPOSITE 0x06080102 +#define RT_PALN_COMB_CNTL2_SVIDEO 0x06080102 + +#define RT_PALM_COMB_CNTL2_COMPOSITE 0x06080102 +#define RT_PALM_COMB_CNTL2_SVIDEO 0x06080102 +/* End of filter settings. */ + +/* COMB_LINE_LENGTH FILTER SETTINGS FOR DIFFERENT STANDARDS: */ +#define RT_NTSCM_COMB_LENGTH_COMPOSITE 0x0718038A +#define RT_NTSCM_COMB_LENGTH_SVIDEO 0x0718038A + +#define RT_PAL_COMB_LENGTH_COMPOSITE 0x08DA046B +#define RT_PAL_COMB_LENGTH_SVIDEO 0x08DA046B + +#define RT_SECAM_COMB_LENGTH_COMPOSITE 0x08DA046A +#define RT_SECAM_COMB_LENGTH_SVIDEO 0x08DA046A + +#define RT_PALN_COMB_LENGTH_COMPOSITE 0x07260391 +#define RT_PALN_COMB_LENGTH_SVIDEO 0x07260391 + +#define RT_PALM_COMB_LENGTH_COMPOSITE 0x07160389 +#define RT_PALM_COMB_LENGTH_SVIDEO 0x07160389 +/* End of filter settings. */ + +/* LP_AGC_CLAMP_CNTL0 */ +#define RT_NTSCM_SYNCTIP_REF0 0x00000037 +#define RT_NTSCM_SYNCTIP_REF1 0x00000029 +#define RT_NTSCM_CLAMP_REF 0x0000003B +#define RT_NTSCM_PEAKWHITE 0x000000FF +#define RT_NTSCM_VBI_PEAKWHITE 0x000000C2 + +#define RT_NTSCM_WPA_THRESHOLD 0x00000406 +#define RT_NTSCM_WPA_TRIGGER_LO 0x000000B3 + +#define RT_NTSCM_WPA_TRIGGER_HIGH 0x0000021B + +#define RT_NTSCM_LP_LOCKOUT_START 0x00000206 +#define RT_NTSCM_LP_LOCKOUT_END 0x00000021 +#define RT_NTSCM_CH_DTO_INC 0x00400000 +#define RT_NTSCM_CH_PLL_SGAIN 0x00000001 +#define RT_NTSCM_CH_PLL_FGAIN 0x00000002 + +#define RT_NTSCM_CR_BURST_GAIN 0x0000007A +#define RT_NTSCM_CB_BURST_GAIN 0x000000AC + +#define RT_NTSCM_CH_HEIGHT 0x000000CD +#define RT_NTSCM_CH_KILL_LEVEL 0x000000C0 +#define RT_NTSCM_CH_AGC_ERROR_LIM 0x00000002 +#define RT_NTSCM_CH_AGC_FILTER_EN 0x00000000 +#define RT_NTSCM_CH_AGC_LOOP_SPEED 0x00000000 + +#define RT_NTSCM_CRDR_ACTIVE_GAIN 0x0000007A +#define RT_NTSCM_CBDB_ACTIVE_GAIN 0x000000AC + +#define RT_NTSCM_VERT_LOCKOUT_START 0x00000207 +#define RT_NTSCM_VERT_LOCKOUT_END 0x0000000E + +#define RT_NTSCJ_SYNCTIP_REF0 0x00000004 +#define RT_NTSCJ_SYNCTIP_REF1 0x00000012 +#define RT_NTSCJ_CLAMP_REF 0x0000003B +#define RT_NTSCJ_PEAKWHITE 0x000000CB +#define RT_NTSCJ_VBI_PEAKWHITE 0x000000C2 +#define RT_NTSCJ_WPA_THRESHOLD 0x000004B0 +#define RT_NTSCJ_WPA_TRIGGER_LO 0x000000B4 +#define RT_NTSCJ_WPA_TRIGGER_HIGH 0x0000021C +#define RT_NTSCJ_LP_LOCKOUT_START 0x00000206 +#define RT_NTSCJ_LP_LOCKOUT_END 0x00000021 + +#define RT_NTSCJ_CR_BURST_GAIN 0x00000071 +#define RT_NTSCJ_CB_BURST_GAIN 0x0000009F +#define RT_NTSCJ_CH_HEIGHT 0x000000CD +#define RT_NTSCJ_CH_KILL_LEVEL 0x000000C0 +#define RT_NTSCJ_CH_AGC_ERROR_LIM 0x00000002 +#define RT_NTSCJ_CH_AGC_FILTER_EN 0x00000000 +#define RT_NTSCJ_CH_AGC_LOOP_SPEED 0x00000000 + +#define RT_NTSCJ_CRDR_ACTIVE_GAIN 0x00000071 +#define RT_NTSCJ_CBDB_ACTIVE_GAIN 0x0000009F +#define RT_NTSCJ_VERT_LOCKOUT_START 0x00000207 +#define RT_NTSCJ_VERT_LOCKOUT_END 0x0000000E + +#define RT_PAL_SYNCTIP_REF0 0x37 /* instead of 0x00000004 - Ivo */ +#define RT_PAL_SYNCTIP_REF1 0x26 /* instead of 0x0000000F - Ivo */ +#define RT_PAL_CLAMP_REF 0x0000003B +#define RT_PAL_PEAKWHITE 0xFF /* instead of 0x000000C1 - Ivo */ +#define RT_PAL_VBI_PEAKWHITE 0xC6 /* instead of 0x000000C7 - Ivo */ +#define RT_PAL_WPA_THRESHOLD 0x59C /* instead of 0x000006A4 - Ivo */ + +#define RT_PAL_WPA_TRIGGER_LO 0x00000096 +#define RT_PAL_WPA_TRIGGER_HIGH 0x000001C2 +#define RT_PAL_LP_LOCKOUT_START 0x00000263 +#define RT_PAL_LP_LOCKOUT_END 0x0000002C + +#define RT_PAL_CH_DTO_INC 0x00400000 +#define RT_PAL_CH_PLL_SGAIN 1 /* instead of 0x00000002 - Ivo */ +#define RT_PAL_CH_PLL_FGAIN 2 /* instead of 0x00000001 - Ivo */ +#define RT_PAL_CR_BURST_GAIN 0x0000007A +#define RT_PAL_CB_BURST_GAIN 0x000000AB +#define RT_PAL_CH_HEIGHT 0x0000009C +#define RT_PAL_CH_KILL_LEVEL 4 /* instead of 0x00000090 - Ivo */ +#define RT_PAL_CH_AGC_ERROR_LIM 1 /* instead of 0x00000002 - Ivo */ +#define RT_PAL_CH_AGC_FILTER_EN 1 /* instead of 0x00000000 - Ivo */ +#define RT_PAL_CH_AGC_LOOP_SPEED 0x00000000 + +#define RT_PAL_CRDR_ACTIVE_GAIN 0x9E /* instead of 0x0000007A - Ivo */ +#define RT_PAL_CBDB_ACTIVE_GAIN 0xDF /* instead of 0x000000AB - Ivo */ +#define RT_PAL_VERT_LOCKOUT_START 0x00000269 +#define RT_PAL_VERT_LOCKOUT_END 0x00000012 + +#define RT_SECAM_SYNCTIP_REF0 0x37 /* instead of 0x00000004 - Ivo */ +#define RT_SECAM_SYNCTIP_REF1 0x26 /* instead of 0x0000000F - Ivo */ +#define RT_SECAM_CLAMP_REF 0x0000003B +#define RT_SECAM_PEAKWHITE 0xFF /* instead of 0x000000C1 - Ivo */ +#define RT_SECAM_VBI_PEAKWHITE 0xC6 /* instead of 0x000000C7 - Ivo */ +#define RT_SECAM_WPA_THRESHOLD 0x57A /* instead of 0x6A4, instead of 0x0000059C is Ivo's value , -eric*/ + +#define RT_SECAM_WPA_TRIGGER_LO 0x96 /* instead of 0x0000026B - eric */ +#define RT_SECAM_WPA_TRIGGER_HIGH 0x000001C2 +#define RT_SECAM_LP_LOCKOUT_START 0x263 /* instead of 0x0000026B - eric */ +#define RT_SECAM_LP_LOCKOUT_END 0x2b /* instead of 0x0000002C -eric */ + +#define RT_SECAM_CH_DTO_INC 0x003E7A28 +#define RT_SECAM_CH_PLL_SGAIN 0x4 /* instead of 0x00000006 -Volodya */ +#define RT_SECAM_CH_PLL_FGAIN 0x7 /* instead of 0x00000006 -Volodya */ + +#define RT_SECAM_CR_BURST_GAIN 0x1FF /* instead of 0x00000200 -Volodya */ +#define RT_SECAM_CB_BURST_GAIN 0x1FF /* instead of 0x00000200 -Volodya */ +#define RT_SECAM_CH_HEIGHT 0x00000066 +#define RT_SECAM_CH_KILL_LEVEL 0x00000060 +#define RT_SECAM_CH_AGC_ERROR_LIM 0x00000003 +#define RT_SECAM_CH_AGC_FILTER_EN 0x00000000 +#define RT_SECAM_CH_AGC_LOOP_SPEED 0x00000000 + +#define RT_SECAM_CRDR_ACTIVE_GAIN 0x11B /* instead of 0x00000200 - eric */ +#define RT_SECAM_CBDB_ACTIVE_GAIN 0x15A /* instead of 0x00000200 - eric */ +#define RT_SECAM_VERT_LOCKOUT_START 0x00000269 +#define RT_SECAM_VERT_LOCKOUT_END 0x00000012 + +#define RT_PAL_VS_FIELD_BLANK_END 0x2A /* instead of 0x0000002C - Ivo*/ +#define RT_NTSCM_VS_FIELD_BLANK_END 0x0000000A + +#define RT_NTSCM_FIELD_IDLOCATION 0x00000105 +#define RT_PAL_FIELD_IDLOCATION 0x00000137 + +#define RT_NTSCM_H_ACTIVE_START 0x00000070 +#define RT_NTSCM_H_ACTIVE_END 0x00000363 + +#define RT_PAL_H_ACTIVE_START 0x0000009A +#define RT_PAL_H_ACTIVE_END 0x00000439 + +#define RT_NTSCM_V_ACTIVE_START ((22-4)*2+1) +#define RT_NTSCM_V_ACTIVE_END ((22+240-4)*2+1) + +#define RT_PAL_V_ACTIVE_START 0x2E /* instead of 0x00000023 (Same as SECAM) - Ivo */ +#define RT_PAL_V_ACTIVE_END 0x269 /* instead of 0x00000262 - Ivo */ + +/* VBI */ +#define RT_NTSCM_H_VBI_WIND_START 0x00000049 +#define RT_NTSCM_H_VBI_WIND_END 0x00000366 + +#define RT_PAL_H_VBI_WIND_START 0x00000084 +#define RT_PAL_H_VBI_WIND_END 0x0000041F + +#define RT_NTSCM_V_VBI_WIND_START fld_V_VBI_WIND_START_def +#define RT_NTSCM_V_VBI_WIND_END fld_V_VBI_WIND_END_def + +#define RT_PAL_V_VBI_WIND_START 0x8 /* instead of 0x0000000B - Ivo */ +#define RT_PAL_V_VBI_WIND_END 0x2D /* instead of 0x00000022 - Ivo */ + +#define RT_VBI_CAPTURE_EN 0x00000001 /* Enable */ +#define RT_VBI_CAPTURE_DIS 0x00000000 /* Disable */ +#define RT_RAW_CAPTURE 0x00000002 /* Use raw Video Capture. */ + +#define RT_NTSCM_VSYNC_INT_TRIGGER 0x2AA +#define RT_PALSEM_VSYNC_INT_TRIGGER 0x353 + +#define RT_NTSCM_VSYNC_INT_HOLD 0x17 +#define RT_PALSEM_VSYNC_INT_HOLD 0x1C + +#define RT_NTSCM_VS_FIELD_BLANK_START 0x206 +#define RT_PALSEM_VS_FIELD_BLANK_START 0x26D /* instead of 0x26C - Ivo */ + +#define RT_FIELD_FLIP_EN 0x4 +#define RT_V_FIELD_FLIP_INVERTED 0x2000 + +#define RT_NTSCM_H_IN_START 0x70 +#define RT_PAL_H_IN_START 154 /* instead of 144 - Ivo */ +#define RT_SECAM_H_IN_START 0x91 /* instead of 0x9A, Ivo value is 154, instead of 144 - Volodya, - eric */ +#define RT_NTSC_H_ACTIVE_SIZE 744 +#define RT_PAL_H_ACTIVE_SIZE 928 /* instead of 927 - Ivo */ +#define RT_SECAM_H_ACTIVE_SIZE 932 /* instead of 928, instead of 927 - Ivo, - eric */ +#define RT_NTSCM_V_IN_START (0x23) +#define RT_PAL_V_IN_START 44 /* instead of (45-6) - Ivo */ +#define RT_SECAM_V_IN_START 0x2C /* instead of (45-6) - Volodya */ +#define RT_NTSCM_V_ACTIVE_SIZE 480 +#define RT_PAL_V_ACTIVE_SIZE 572 /* instead of 575 - Ivo */ +#define RT_SECAM_V_ACTIVE_SIZE 570 /* instead of 572, instead of 575 - Ivo, - eric */ + +#define RT_NTSCM_WIN_CLOSE_LIMIT 0x4D +#define RT_NTSCJ_WIN_CLOSE_LIMIT 0x4D +#define RT_NTSC443_WIN_CLOSE_LIMIT 0x5F +#define RT_PALM_WIN_CLOSE_LIMIT 0x4D +#define RT_PALN_WIN_CLOSE_LIMIT 0x5F +#define RT_SECAM_WIN_CLOSE_LIMIT 0xC7 /* instead of 0x5F - eric */ + +#define RT_NTSCM_VS_FIELD_BLANK_START 0x206 + +#define RT_NTSCM_HS_PLL_SGAIN 0x5 +#define RT_NTSCM_HS_PLL_FGAIN 0x7 + +#define RT_NTSCM_H_OUT_WIND_WIDTH 0x2F4 +#define RT_NTSCM_V_OUT_WIND_HEIGHT 0xF0 + +#define TV 0x1 +#define LINEIN 0x2 +#define MUTE 0x3 + +#define DEC_COMPOSITE 0 +#define DEC_SVIDEO 1 +#define DEC_TUNER 2 + +#define DEC_NTSC 0 +#define DEC_PAL 1 +#define DEC_SECAM 2 +#define DEC_NTSC_J 8 + +#define DEC_SMOOTH 0 +#define DEC_SHARP 1 + +/* RT Register Field Defaults: */ +#define fld_tmpReg1_def 0x00000000 +#define fld_tmpReg2_def 0x00000001 +#define fld_tmpReg3_def 0x00000002 + +#define fld_LP_CONTRAST_def 0x0000006e +#define fld_LP_BRIGHTNESS_def 0x00003ff0 +#define fld_CP_HUE_CNTL_def 0x00000000 +#define fld_LUMA_FILTER_def 0x00000001 +#define fld_H_SCALE_RATIO_def 0x00010000 +#define fld_H_SHARPNESS_def 0x00000000 + +#define fld_V_SCALE_RATIO_def 0x00000800 +#define fld_V_DEINTERLACE_ON_def 0x00000001 +#define fld_V_BYPSS_def 0x00000000 +#define fld_V_DITHER_ON_def 0x00000001 +#define fld_EVENF_OFFSET_def 0x00000000 +#define fld_ODDF_OFFSET_def 0x00000000 + +#define fld_INTERLACE_DETECTED_def 0x00000000 + +#define fld_VS_LINE_COUNT_def 0x00000000 +#define fld_VS_DETECTED_LINES_def 0x00000000 +#define fld_VS_ITU656_VB_def 0x00000000 + +#define fld_VBI_CC_DATA_def 0x00000000 +#define fld_VBI_CC_WT_def 0x00000000 +#define fld_VBI_CC_WT_ACK_def 0x00000000 +#define fld_VBI_CC_HOLD_def 0x00000000 +#define fld_VBI_DECODE_EN_def 0x00000000 + +#define fld_VBI_CC_DTO_P_def 0x00001802 +#define fld_VBI_20BIT_DTO_P_def 0x0000155c + +#define fld_VBI_CC_LEVEL_def 0x0000003f +#define fld_VBI_20BIT_LEVEL_def 0x00000059 +#define fld_VBI_CLK_RUNIN_GAIN_def 0x0000010f + +#define fld_H_VBI_WIND_START_def 0x00000041 +#define fld_H_VBI_WIND_END_def 0x00000366 + +#define fld_V_VBI_WIND_START_def 0x0D +#define fld_V_VBI_WIND_END_def 0x24 + +#define fld_VBI_20BIT_DATA0_def 0x00000000 +#define fld_VBI_20BIT_DATA1_def 0x00000000 +#define fld_VBI_20BIT_WT_def 0x00000000 +#define fld_VBI_20BIT_WT_ACK_def 0x00000000 +#define fld_VBI_20BIT_HOLD_def 0x00000000 + +#define fld_VBI_CAPTURE_ENABLE_def 0x00000000 + +#define fld_VBI_EDS_DATA_def 0x00000000 +#define fld_VBI_EDS_WT_def 0x00000000 +#define fld_VBI_EDS_WT_ACK_def 0x00000000 +#define fld_VBI_EDS_HOLD_def 0x00000000 + +#define fld_VBI_SCALING_RATIO_def 0x00010000 +#define fld_VBI_ALIGNER_ENABLE_def 0x00000000 + +#define fld_H_ACTIVE_START_def 0x00000070 +#define fld_H_ACTIVE_END_def 0x000002f0 + +#define fld_V_ACTIVE_START_def ((22-4)*2+1) +#define fld_V_ACTIVE_END_def ((22+240-4)*2+2) + +#define fld_CH_HEIGHT_def 0x000000CD +#define fld_CH_KILL_LEVEL_def 0x000000C0 +#define fld_CH_AGC_ERROR_LIM_def 0x00000002 +#define fld_CH_AGC_FILTER_EN_def 0x00000000 +#define fld_CH_AGC_LOOP_SPEED_def 0x00000000 + +#define fld_HUE_ADJ_def 0x00000000 + +#define fld_STANDARD_SEL_def 0x00000000 +#define fld_STANDARD_YC_def 0x00000000 + +#define fld_ADC_PDWN_def 0x00000001 +#define fld_INPUT_SELECT_def 0x00000000 + +#define fld_ADC_PREFLO_def 0x00000003 +#define fld_H_SYNC_PULSE_WIDTH_def 0x00000000 +#define fld_HS_GENLOCKED_def 0x00000000 +#define fld_HS_SYNC_IN_WIN_def 0x00000000 + +#define fld_VIN_ASYNC_RST_def 0x00000001 +#define fld_DVS_ASYNC_RST_def 0x00000001 + +/* Vendor IDs: */ +#define fld_VIP_VENDOR_ID_def 0x00001002 +#define fld_VIP_DEVICE_ID_def 0x00004d54 +#define fld_VIP_REVISION_ID_def 0x00000001 + +/* AGC Delay Register */ +#define fld_BLACK_INT_START_def 0x00000031 +#define fld_BLACK_INT_LENGTH_def 0x0000000f + +#define fld_UV_INT_START_def 0x0000003b +#define fld_U_INT_LENGTH_def 0x0000000f +#define fld_V_INT_LENGTH_def 0x0000000f +#define fld_CRDR_ACTIVE_GAIN_def 0x0000007a +#define fld_CBDB_ACTIVE_GAIN_def 0x000000ac + +#define fld_DVS_DIRECTION_def 0x00000000 +#define fld_DVS_VBI_CARD8_SWAP_def 0x00000000 +#define fld_DVS_CLK_SELECT_def 0x00000000 +#define fld_CONTINUOUS_STREAM_def 0x00000000 +#define fld_DVSOUT_CLK_DRV_def 0x00000001 +#define fld_DVSOUT_DATA_DRV_def 0x00000001 + +#define fld_COMB_CNTL0_def 0x09438090 +#define fld_COMB_CNTL1_def 0x00000010 + +#define fld_COMB_CNTL2_def 0x16161010 +#define fld_COMB_LENGTH_def 0x0718038A + +#define fld_SYNCTIP_REF0_def 0x00000037 +#define fld_SYNCTIP_REF1_def 0x00000029 +#define fld_CLAMP_REF_def 0x0000003B +#define fld_AGC_PEAKWHITE_def 0x000000FF +#define fld_VBI_PEAKWHITE_def 0x000000D2 + +#define fld_WPA_THRESHOLD_def 0x000003B0 + +#define fld_WPA_TRIGGER_LO_def 0x000000B4 +#define fld_WPA_TRIGGER_HIGH_def 0x0000021C + +#define fld_LOCKOUT_START_def 0x00000206 +#define fld_LOCKOUT_END_def 0x00000021 + +#define fld_CH_DTO_INC_def 0x00400000 +#define fld_PLL_SGAIN_def 0x00000001 +#define fld_PLL_FGAIN_def 0x00000002 + +#define fld_CR_BURST_GAIN_def 0x0000007a +#define fld_CB_BURST_GAIN_def 0x000000ac + +#define fld_VERT_LOCKOUT_START_def 0x00000207 +#define fld_VERT_LOCKOUT_END_def 0x0000000E + +#define fld_H_IN_WIND_START_def 0x00000070 +#define fld_V_IN_WIND_START_def 0x00000027 + +#define fld_H_OUT_WIND_WIDTH_def 0x000002f4 + +#define fld_V_OUT_WIND_WIDTH_def 0x000000f0 + +#define fld_HS_LINE_TOTAL_def 0x0000038E + +#define fld_MIN_PULSE_WIDTH_def 0x0000002F +#define fld_MAX_PULSE_WIDTH_def 0x00000046 + +#define fld_WIN_CLOSE_LIMIT_def 0x0000004D +#define fld_WIN_OPEN_LIMIT_def 0x000001B7 + +#define fld_VSYNC_INT_TRIGGER_def 0x000002AA + +#define fld_VSYNC_INT_HOLD_def 0x0000001D + +#define fld_VIN_M0_def 0x00000039 +#define fld_VIN_N0_def 0x0000014c +#define fld_MNFLIP_EN_def 0x00000000 +#define fld_VIN_P_def 0x00000006 +#define fld_REG_CLK_SEL_def 0x00000000 + +#define fld_VIN_M1_def 0x00000000 +#define fld_VIN_N1_def 0x00000000 +#define fld_VIN_DRIVER_SEL_def 0x00000000 +#define fld_VIN_MNFLIP_REQ_def 0x00000000 +#define fld_VIN_MNFLIP_DONE_def 0x00000000 +#define fld_TV_LOCK_TO_VIN_def 0x00000000 +#define fld_TV_P_FOR_WINCLK_def 0x00000004 + +#define fld_VINRST_def 0x00000001 +#define fld_VIN_CLK_SEL_def 0x00000000 + +#define fld_VS_FIELD_BLANK_START_def 0x00000206 + +#define fld_VS_FIELD_BLANK_END_def 0x0000000A + +/*#define fld_VS_FIELD_IDLOCATION_def 0x00000105 */ +#define fld_VS_FIELD_IDLOCATION_def 0x00000001 +#define fld_VS_FRAME_TOTAL_def 0x00000217 + +#define fld_SYNC_TIP_START_def 0x00000372 +#define fld_SYNC_TIP_LENGTH_def 0x0000000F + +#define fld_GAIN_FORCE_DATA_def 0x00000000 +#define fld_GAIN_FORCE_EN_def 0x00000000 +#define fld_I_CLAMP_SEL_def 0x00000003 +#define fld_I_AGC_SEL_def 0x00000001 +#define fld_EXT_CLAMP_CAP_def 0x00000001 +#define fld_EXT_AGC_CAP_def 0x00000001 +#define fld_DECI_DITHER_EN_def 0x00000001 +#define fld_ADC_PREFHI_def 0x00000000 +#define fld_ADC_CH_GAIN_SEL_def 0x00000001 + +#define fld_HS_PLL_SGAIN_def 0x00000003 + +#define fld_NREn_def 0x00000000 +#define fld_NRGainCntl_def 0x00000000 +#define fld_NRBWTresh_def 0x00000000 +#define fld_NRGCTresh_def 0x00000000 +#define fld_NRCoefDespeclMode_def 0x00000000 + +#define fld_GPIO_5_OE_def 0x00000000 +#define fld_GPIO_6_OE_def 0x00000000 + +#define fld_GPIO_5_OUT_def 0x00000000 +#define fld_GPIO_6_OUT_def 0x00000000 + +/* End of field default values. */ + +#endif /* RADEON_H */ diff --git a/contrib/vidix/drivers/radeon_vid.c b/contrib/vidix/drivers/radeon_vid.c new file mode 100644 index 000000000..de4e66194 --- /dev/null +++ b/contrib/vidix/drivers/radeon_vid.c @@ -0,0 +1,3366 @@ +/* + radeon_vid - VIDIX based video driver for Radeon and Rage128 chips + Copyrights 2002 Nick Kurshev. This file is based on sources from + GATOS (gatos.sf.net) and X11 (www.xfree86.org) + Licence: GPL +*/ + +#include <errno.h> +#include <stdio.h> +#include <stdlib.h> +#include <string.h> +#include <math.h> +#include <inttypes.h> +#include <sys/types.h> +#include <sys/mman.h> +#include "bswap.h" +#include "pci_ids.h" +#include "pci_names.h" +#include "vidix.h" +#include "fourcc.h" +#include "libdha.h" +#include "radeon.h" + +#ifdef RAGE128 +#define RADEON_MSG "[rage128]" +#define X_ADJUST 0 +#else +#define RADEON_MSG "[radeon]" +#define X_ADJUST (((besr.chip_flags&R_OVL_SHIFT)==R_OVL_SHIFT)?8:0) +#ifndef RADEON +#define RADEON +#endif +#endif + +#define RADEON_ASSERT(msg) printf(RADEON_MSG"################# FATAL:"msg); + +#ifdef RAGE128 +#define VIDIX_STATIC rage128_ +#else +#define VIDIX_STATIC radeo_ +#endif + +//#undef RADEON_ENABLE_BM /* unfinished stuff. May corrupt your filesystem ever */ +#define RADEON_ENABLE_BM 1 + +#ifdef RADEON_ENABLE_BM +static void * radeon_dma_desc_base = 0; +static unsigned long bus_addr_dma_desc = 0; +static unsigned long *dma_phys_addrs = 0; +#pragma pack(1) +typedef struct +{ + uint32_t framebuf_offset; + uint32_t sys_addr; + uint32_t command; + uint32_t reserved; +} bm_list_descriptor; +#pragma pack() +#endif + +#define VERBOSE_LEVEL 0 +static int __verbose = 0; +typedef struct bes_registers_s +{ + /* base address of yuv framebuffer */ + uint32_t yuv_base; + uint32_t fourcc; + uint32_t surf_id; + int load_prg_start; + int horz_pick_nearest; + int vert_pick_nearest; + int swap_uv; /* for direct support of bgr fourccs */ + uint32_t dest_bpp; + /* YUV BES registers */ + uint32_t reg_load_cntl; + uint32_t h_inc; + uint32_t step_by; + uint32_t y_x_start; + uint32_t y_x_end; + uint32_t v_inc; + uint32_t p1_blank_lines_at_top; + uint32_t p23_blank_lines_at_top; + uint32_t vid_buf_pitch0_value; + uint32_t vid_buf_pitch1_value; + uint32_t p1_x_start_end; + uint32_t p2_x_start_end; + uint32_t p3_x_start_end; + uint32_t base_addr; + uint32_t vid_buf_base_adrs_y[VID_PLAY_MAXFRAMES]; + uint32_t vid_buf_base_adrs_u[VID_PLAY_MAXFRAMES]; + uint32_t vid_buf_base_adrs_v[VID_PLAY_MAXFRAMES]; + uint32_t vid_nbufs; + + uint32_t p1_v_accum_init; + uint32_t p1_h_accum_init; + uint32_t p23_v_accum_init; + uint32_t p23_h_accum_init; + uint32_t scale_cntl; + uint32_t exclusive_horz; + uint32_t auto_flip_cntl; + uint32_t filter_cntl; + uint32_t four_tap_coeff[5]; + uint32_t key_cntl; + uint32_t test; + /* Configurable stuff */ + int double_buff; + + int brightness; + int saturation; + + uint32_t graphics_key_clr; + uint32_t graphics_key_msk; + uint32_t ckey_cntl; + + int deinterlace_on; + uint32_t deinterlace_pattern; + unsigned chip_flags; +} bes_registers_t; + +typedef struct video_registers_s +{ + const char * sname; + uint32_t name; + uint32_t value; +}video_registers_t; + +static bes_registers_t besr; +#define DECLARE_VREG(name) { #name, name, 0 } +static video_registers_t vregs[] = +{ + DECLARE_VREG(VIDEOMUX_CNTL), + DECLARE_VREG(VIPPAD_MASK), + DECLARE_VREG(VIPPAD1_A), + DECLARE_VREG(VIPPAD1_EN), + DECLARE_VREG(VIPPAD1_Y), + DECLARE_VREG(OV0_Y_X_START), + DECLARE_VREG(OV0_Y_X_END), + DECLARE_VREG(OV0_PIPELINE_CNTL), + DECLARE_VREG(OV0_EXCLUSIVE_HORZ), + DECLARE_VREG(OV0_EXCLUSIVE_VERT), + DECLARE_VREG(OV0_REG_LOAD_CNTL), + DECLARE_VREG(OV0_SCALE_CNTL), + DECLARE_VREG(OV0_V_INC), + DECLARE_VREG(OV0_P1_V_ACCUM_INIT), + DECLARE_VREG(OV0_P23_V_ACCUM_INIT), + DECLARE_VREG(OV0_P1_BLANK_LINES_AT_TOP), + DECLARE_VREG(OV0_P23_BLANK_LINES_AT_TOP), +#ifdef RADEON + DECLARE_VREG(OV0_BASE_ADDR), +#endif + DECLARE_VREG(OV0_VID_BUF0_BASE_ADRS), + DECLARE_VREG(OV0_VID_BUF1_BASE_ADRS), + DECLARE_VREG(OV0_VID_BUF2_BASE_ADRS), + DECLARE_VREG(OV0_VID_BUF3_BASE_ADRS), + DECLARE_VREG(OV0_VID_BUF4_BASE_ADRS), + DECLARE_VREG(OV0_VID_BUF5_BASE_ADRS), + DECLARE_VREG(OV0_VID_BUF_PITCH0_VALUE), + DECLARE_VREG(OV0_VID_BUF_PITCH1_VALUE), + DECLARE_VREG(OV0_AUTO_FLIP_CNTL), + DECLARE_VREG(OV0_DEINTERLACE_PATTERN), + DECLARE_VREG(OV0_SUBMIT_HISTORY), + DECLARE_VREG(OV0_H_INC), + DECLARE_VREG(OV0_STEP_BY), + DECLARE_VREG(OV0_P1_H_ACCUM_INIT), + DECLARE_VREG(OV0_P23_H_ACCUM_INIT), + DECLARE_VREG(OV0_P1_X_START_END), + DECLARE_VREG(OV0_P2_X_START_END), + DECLARE_VREG(OV0_P3_X_START_END), + DECLARE_VREG(OV0_FILTER_CNTL), + DECLARE_VREG(OV0_FOUR_TAP_COEF_0), + DECLARE_VREG(OV0_FOUR_TAP_COEF_1), + DECLARE_VREG(OV0_FOUR_TAP_COEF_2), + DECLARE_VREG(OV0_FOUR_TAP_COEF_3), + DECLARE_VREG(OV0_FOUR_TAP_COEF_4), + DECLARE_VREG(OV0_FLAG_CNTL), +#ifdef RAGE128 + DECLARE_VREG(OV0_COLOUR_CNTL), +#else + DECLARE_VREG(OV0_SLICE_CNTL), +#endif + DECLARE_VREG(OV0_VID_KEY_CLR), + DECLARE_VREG(OV0_VID_KEY_MSK), + DECLARE_VREG(OV0_GRAPHICS_KEY_CLR), + DECLARE_VREG(OV0_GRAPHICS_KEY_MSK), + DECLARE_VREG(OV0_KEY_CNTL), + DECLARE_VREG(OV0_TEST), + DECLARE_VREG(OV0_LIN_TRANS_A), + DECLARE_VREG(OV0_LIN_TRANS_B), + DECLARE_VREG(OV0_LIN_TRANS_C), + DECLARE_VREG(OV0_LIN_TRANS_D), + DECLARE_VREG(OV0_LIN_TRANS_E), + DECLARE_VREG(OV0_LIN_TRANS_F), + DECLARE_VREG(OV0_GAMMA_0_F), + DECLARE_VREG(OV0_GAMMA_10_1F), + DECLARE_VREG(OV0_GAMMA_20_3F), + DECLARE_VREG(OV0_GAMMA_40_7F), + DECLARE_VREG(OV0_GAMMA_380_3BF), + DECLARE_VREG(OV0_GAMMA_3C0_3FF), + DECLARE_VREG(SUBPIC_CNTL), + DECLARE_VREG(SUBPIC_DEFCOLCON), + DECLARE_VREG(SUBPIC_Y_X_START), + DECLARE_VREG(SUBPIC_Y_X_END), + DECLARE_VREG(SUBPIC_V_INC), + DECLARE_VREG(SUBPIC_H_INC), + DECLARE_VREG(SUBPIC_BUF0_OFFSET), + DECLARE_VREG(SUBPIC_BUF1_OFFSET), + DECLARE_VREG(SUBPIC_LC0_OFFSET), + DECLARE_VREG(SUBPIC_LC1_OFFSET), + DECLARE_VREG(SUBPIC_PITCH), + DECLARE_VREG(SUBPIC_BTN_HLI_COLCON), + DECLARE_VREG(SUBPIC_BTN_HLI_Y_X_START), + DECLARE_VREG(SUBPIC_BTN_HLI_Y_X_END), + DECLARE_VREG(SUBPIC_PALETTE_INDEX), + DECLARE_VREG(SUBPIC_PALETTE_DATA), + DECLARE_VREG(SUBPIC_H_ACCUM_INIT), + DECLARE_VREG(SUBPIC_V_ACCUM_INIT), + DECLARE_VREG(IDCT_RUNS), + DECLARE_VREG(IDCT_LEVELS), + DECLARE_VREG(IDCT_AUTH_CONTROL), + DECLARE_VREG(IDCT_AUTH), + DECLARE_VREG(IDCT_CONTROL), +#ifdef RAGE128 + DECLARE_VREG(BM_FRAME_BUF_OFFSET), + DECLARE_VREG(BM_SYSTEM_MEM_ADDR), + DECLARE_VREG(BM_COMMAND), + DECLARE_VREG(BM_STATUS), + DECLARE_VREG(BM_QUEUE_STATUS), + DECLARE_VREG(BM_QUEUE_FREE_STATUS), + DECLARE_VREG(BM_CHUNK_0_VAL), + DECLARE_VREG(BM_CHUNK_1_VAL), + DECLARE_VREG(BM_VIP0_BUF), + DECLARE_VREG(BM_VIP0_ACTIVE), + DECLARE_VREG(BM_VIP1_BUF), + DECLARE_VREG(BM_VIP1_ACTIVE), + DECLARE_VREG(BM_VIP2_BUF), + DECLARE_VREG(BM_VIP2_ACTIVE), + DECLARE_VREG(BM_VIP3_BUF), + DECLARE_VREG(BM_VIP3_ACTIVE), + DECLARE_VREG(BM_VIDCAP_BUF0), + DECLARE_VREG(BM_VIDCAP_BUF1), + DECLARE_VREG(BM_VIDCAP_BUF2), + DECLARE_VREG(BM_VIDCAP_ACTIVE), + DECLARE_VREG(BM_GUI), + DECLARE_VREG(BM_ABORT) +#else + DECLARE_VREG(DMA_GUI_TABLE_ADDR), + DECLARE_VREG(DMA_GUI_SRC_ADDR), + DECLARE_VREG(DMA_GUI_DST_ADDR), + DECLARE_VREG(DMA_GUI_COMMAND), + DECLARE_VREG(DMA_GUI_STATUS), + DECLARE_VREG(DMA_GUI_ACT_DSCRPTR), + DECLARE_VREG(DMA_VID_SRC_ADDR), + DECLARE_VREG(DMA_VID_DST_ADDR), + DECLARE_VREG(DMA_VID_COMMAND), + DECLARE_VREG(DMA_VID_STATUS), + DECLARE_VREG(DMA_VID_ACT_DSCRPTR), +#endif +}; + +#define R_FAMILY 0x000000FF +#define R_100 0x00000001 +#define R_120 0x00000002 +#define R_150 0x00000003 +#define R_200 0x00000004 +#define R_250 0x00000005 +#define R_280 0x00000006 +#define R_300 0x00000007 +#define R_350 0x00000008 +#define R_370 0x00000010 +#define R_380 0x00000020 +#define R_420 0x00000040 +#define R_OVL_SHIFT 0x00000100 +#define R_INTEGRATED 0x00000200 +#define R_PCIE 0x00000400 + +typedef struct ati_card_ids_s +{ + unsigned short id; + unsigned flags; +}ati_card_ids_t; + +static const ati_card_ids_t ati_card_ids[] = +{ +#ifdef RAGE128 + /* + This driver should be compatible with Rage128 (pro) chips. + (include adaptive deinterlacing!!!). + Moreover: the same logic can be used with Mach64 chips. + (I mean: mach64xx, 3d rage, 3d rage IIc, 3D rage pro, 3d rage mobility). + but they are incompatible by i/o ports. So if enthusiasts will want + then they can redefine OUTREG and INREG macros and redefine OV0_* + constants. Also it seems that mach64 chips supports only: YUY2, YV12, UYVY + fourccs (422 and 420 formats only). + */ +/* Rage128 Pro GL */ + { DEVICE_ATI_RAGE_128_PA_PRO, 0 }, + { DEVICE_ATI_RAGE_128_PB_PRO, 0 }, + { DEVICE_ATI_RAGE_128_PC_PRO, 0 }, + { DEVICE_ATI_RAGE_128_PD_PRO, 0 }, + { DEVICE_ATI_RAGE_128_PE_PRO, 0 }, + { DEVICE_ATI_RAGE_128_PF_PRO, 0 }, +/* Rage128 Pro VR */ + { DEVICE_ATI_RAGE_128_PG_PRO, 0 }, + { DEVICE_ATI_RAGE_128_PH_PRO, 0 }, + { DEVICE_ATI_RAGE_128_PI_PRO, 0 }, + { DEVICE_ATI_RAGE_128_PJ_PRO, 0 }, + { DEVICE_ATI_RAGE_128_PK_PRO, 0 }, + { DEVICE_ATI_RAGE_128_PL_PRO, 0 }, + { DEVICE_ATI_RAGE_128_PM_PRO, 0 }, + { DEVICE_ATI_RAGE_128_PN_PRO, 0 }, + { DEVICE_ATI_RAGE_128_PO_PRO, 0 }, + { DEVICE_ATI_RAGE_128_PP_PRO, 0 }, + { DEVICE_ATI_RAGE_128_PQ_PRO, 0 }, + { DEVICE_ATI_RAGE_128_PR_PRO, 0 }, + { DEVICE_ATI_RAGE_128_PS_PRO, 0 }, + { DEVICE_ATI_RAGE_128_PT_PRO, 0 }, + { DEVICE_ATI_RAGE_128_PU_PRO, 0 }, + { DEVICE_ATI_RAGE_128_PV_PRO, 0 }, + { DEVICE_ATI_RAGE_128_PW_PRO, 0 }, + { DEVICE_ATI_RAGE_128_PX_PRO, 0 }, +/* Rage128 GL */ + { DEVICE_ATI_RAGE_128_RE_SG, 0 }, + { DEVICE_ATI_RAGE_128_RF_SG, 0 }, + { DEVICE_ATI_RAGE_128_RG, 0 }, + { DEVICE_ATI_RAGE_128_RK_VR, 0 }, + { DEVICE_ATI_RAGE_128_RL_VR, 0 }, + { DEVICE_ATI_RAGE_128_SE_4X, 0 }, + { DEVICE_ATI_RAGE_128_SF_4X, 0 }, + { DEVICE_ATI_RAGE_128_SG_4X, 0 }, + { DEVICE_ATI_RAGE_128_SH, 0 }, + { DEVICE_ATI_RAGE_128_SK_4X, 0 }, + { DEVICE_ATI_RAGE_128_SL_4X, 0 }, + { DEVICE_ATI_RAGE_128_SM_4X, 0 }, + { DEVICE_ATI_RAGE_128_4X, 0 }, + { DEVICE_ATI_RAGE_128_PRO, 0 }, + { DEVICE_ATI_RAGE_128_PRO2, 0 }, + { DEVICE_ATI_RAGE_128_PRO3, 0 }, +/* these seem to be based on rage 128 instead of mach64 */ + { DEVICE_ATI_RAGE_MOBILITY_M3, 0 }, + { DEVICE_ATI_RAGE_MOBILITY_M32, 0 }, +#else +/* Radeon1 (indeed: Rage 256 Pro ;) */ + { DEVICE_ATI_RADEON_R100_QD, R_100|R_OVL_SHIFT }, + { DEVICE_ATI_RADEON_R100_QE, R_100|R_OVL_SHIFT }, + { DEVICE_ATI_RADEON_R100_QF, R_100|R_OVL_SHIFT }, + { DEVICE_ATI_RADEON_R100_QG, R_100|R_OVL_SHIFT }, + { DEVICE_ATI_RADEON_IGP_320, R_150|R_OVL_SHIFT|R_INTEGRATED }, + { DEVICE_ATI_RADEON_MOBILITY_U1, R_150|R_OVL_SHIFT|R_INTEGRATED }, + { DEVICE_ATI_RADEON_RV100_QY, R_120|R_OVL_SHIFT }, + { DEVICE_ATI_RADEON_RV100_QZ, R_120|R_OVL_SHIFT }, + { DEVICE_ATI_RADEON_MOBILITY_M7, R_150|R_OVL_SHIFT }, + { DEVICE_ATI_RADEON_RV200_LX, R_150|R_OVL_SHIFT }, + { DEVICE_ATI_RADEON_MOBILITY_M6, R_120|R_OVL_SHIFT }, + { DEVICE_ATI_RADEON_MOBILITY_M62, R_120|R_OVL_SHIFT }, +/* Radeon2 (indeed: Rage 512 Pro ;) */ + { DEVICE_ATI_R200_BB_RADEON, R_200 }, + { DEVICE_ATI_R200_BC_RADEON, R_200 }, + { DEVICE_ATI_RADEON_R200_QH, R_200 }, + { DEVICE_ATI_RADEON_R200_QI, R_200 }, + { DEVICE_ATI_RADEON_R200_QJ, R_200 }, + { DEVICE_ATI_RADEON_R200_QK, R_200 }, + { DEVICE_ATI_RADEON_R200_QL, R_200 }, + { DEVICE_ATI_RADEON_R200_QM, R_200 }, + { DEVICE_ATI_RADEON_R200_QN, R_200 }, + { DEVICE_ATI_RADEON_R200_QO, R_200 }, + { DEVICE_ATI_RADEON_R200_QH2, R_200 }, + { DEVICE_ATI_RADEON_R200_QI2, R_200 }, + { DEVICE_ATI_RADEON_R200_QJ2, R_200 }, + { DEVICE_ATI_RADEON_R200_QK2, R_200 }, + { DEVICE_ATI_RADEON_R200_QL2, R_200 }, + { DEVICE_ATI_RADEON_RV200_QW, R_150|R_OVL_SHIFT }, + { DEVICE_ATI_RADEON_RV200_QX, R_150|R_OVL_SHIFT }, + { DEVICE_ATI_RADEON_IGP330_340_350,R_200|R_INTEGRATED }, + { DEVICE_ATI_RADEON_IGP_330M_340M_350M,R_200|R_INTEGRATED }, + { DEVICE_ATI_RADEON_RV250_IG, R_250|R_OVL_SHIFT }, + { DEVICE_ATI_RADEON_7000_IGP, R_250|R_OVL_SHIFT|R_INTEGRATED }, + { DEVICE_ATI_RADEON_MOBILITY_7000, R_250|R_OVL_SHIFT|R_INTEGRATED }, + { DEVICE_ATI_RADEON_RV250_ID, R_250|R_OVL_SHIFT }, + { DEVICE_ATI_RADEON_RV250_IE, R_250|R_OVL_SHIFT }, + { DEVICE_ATI_RADEON_RV250_IF, R_250|R_OVL_SHIFT }, + { DEVICE_ATI_RADEON_RV250_IG, R_250|R_OVL_SHIFT }, + { DEVICE_ATI_RADEON_R250_LD, R_250|R_OVL_SHIFT }, + { DEVICE_ATI_RADEON_R250_LE, R_250|R_OVL_SHIFT }, + { DEVICE_ATI_RADEON_R250_LF, R_250|R_OVL_SHIFT }, + { DEVICE_ATI_RADEON_R250_LG, R_250|R_OVL_SHIFT }, + { DEVICE_ATI_RV280_RADEON_92003, R_280 }, + { DEVICE_ATI_RV280_RADEON_92004, R_280 }, + { DEVICE_ATI_RV280_RADEON_92005, R_280 }, +/* Radeon3 (indeed: Rage 1024 Pro ;) */ + { DEVICE_ATI_R300_AG_FIREGL, R_300 }, + { DEVICE_ATI_RADEON_R300_ND, R_300 }, + { DEVICE_ATI_RADEON_R300_NE, R_300 }, + { DEVICE_ATI_RADEON_R300_NG, R_300 }, + { DEVICE_ATI_R300_AD_RADEON, R_300 }, + { DEVICE_ATI_R300_AE_RADEON, R_300 }, + { DEVICE_ATI_R300_AF_RADEON, R_300 }, + { DEVICE_ATI_RADEON_9100_IGP2, R_300|R_OVL_SHIFT|R_INTEGRATED }, + { DEVICE_ATI_RS300M_AGP_RADEON, R_300|R_INTEGRATED }, + { DEVICE_ATI_R350_AH_RADEON, R_350 }, + { DEVICE_ATI_R350_AI_RADEON, R_350 }, + { DEVICE_ATI_R350_AJ_RADEON, R_350 }, + { DEVICE_ATI_R350_AK_FIRE, R_350 }, + { DEVICE_ATI_RADEON_R350_RADEON2, R_350 }, + { DEVICE_ATI_RADEON_R350_RADEON3, R_350 }, + { DEVICE_ATI_RV350_NJ_RADEON, R_350 }, + { DEVICE_ATI_R350_NK_FIRE, R_350 }, + { DEVICE_ATI_RV350_AP_RADEON, R_350 }, + { DEVICE_ATI_RV350_AQ_RADEON, R_350 }, + { DEVICE_ATI_RV350_AR_RADEON, R_350 }, + { DEVICE_ATI_RV350_AS_RADEON, R_350 }, + { DEVICE_ATI_RV350_AT_FIRE, R_350 }, + { DEVICE_ATI_RV350_AU_FIRE, R_350 }, + { DEVICE_ATI_RV350_AV_FIRE, R_350 }, + { DEVICE_ATI_RV350_AW_FIRE, R_350 }, + { DEVICE_ATI_RV350_MOBILITY_RADEON, R_350 }, + { DEVICE_ATI_RV350_NF_RADEON, R_300 }, + { DEVICE_ATI_RV350_NJ_RADEON, R_300 }, + { DEVICE_ATI_M10_NQ_RADEON, R_350 }, + { DEVICE_ATI_RV350_MOBILITY_RADEON2, R_350 }, + { DEVICE_ATI_M10_NS_RADEON, R_350 }, + { DEVICE_ATI_M10_NT_FIREGL, R_350 }, + { DEVICE_ATI_M11_NV_FIREGL, R_350 }, + { DEVICE_ATI_RV370_5B60_RADEON, R_370|R_PCIE }, + { DEVICE_ATI_RV370_5B62_RADEON, R_370|R_PCIE }, + { DEVICE_ATI_RV370_5B64_FIREGL, R_370|R_PCIE }, + { DEVICE_ATI_RV370_5B65_FIREGL, R_370|R_PCIE }, + { DEVICE_ATI_RV380_0X3E50_RADEON, R_380|R_PCIE }, + { DEVICE_ATI_RV380_0X3E54_FIREGL, R_380|R_PCIE }, + { DEVICE_ATI_RV380_RADEON_X600, R_380|R_PCIE }, + { DEVICE_ATI_R420_JH_RADEON, R_420|R_PCIE }, + { DEVICE_ATI_R420_JI_RADEON, R_420|R_PCIE }, + { DEVICE_ATI_R420_JJ_RADEON, R_420|R_PCIE }, + { DEVICE_ATI_R420_JK_RADEON, R_420|R_PCIE }, + { DEVICE_ATI_R420_JL_RADEON, R_420|R_PCIE }, + { DEVICE_ATI_R420_JM_FIREGL, R_420|R_PCIE }, + { DEVICE_ATI_M18_JN_RADEON, R_420|R_PCIE }, + { DEVICE_ATI_R420_JP_RADEON, R_420|R_PCIE }, + { DEVICE_ATI_R420_JM_FIREGL, R_420|R_PCIE }, + { DEVICE_ATI_R423_5F57_RADEON, R_420|R_PCIE } +#endif +}; + + +static void * radeon_mmio_base = 0; +static void * radeon_mem_base = 0; +static int32_t radeon_overlay_off = 0; +static uint32_t radeon_ram_size = 0; + +#define GETREG(TYPE,PTR,OFFZ) (*((volatile TYPE*)((PTR)+(OFFZ)))) +#define SETREG(TYPE,PTR,OFFZ,VAL) (*((volatile TYPE*)((PTR)+(OFFZ))))=VAL + +#define INREG8(addr) GETREG(uint8_t,(uint32_t)(radeon_mmio_base),addr) +#define OUTREG8(addr,val) SETREG(uint8_t,(uint32_t)(radeon_mmio_base),addr,val) +static inline uint32_t INREG (uint32_t addr) { + uint32_t tmp = GETREG(uint32_t,(uint32_t)(radeon_mmio_base),addr); + return le2me_32(tmp); +} +#define OUTREG(addr,val) SETREG(uint32_t,(uint32_t)(radeon_mmio_base),addr,le2me_32(val)) +#define OUTREGP(addr,val,mask) \ + do { \ + unsigned int _tmp = INREG(addr); \ + _tmp &= (mask); \ + _tmp |= (val); \ + OUTREG(addr, _tmp); \ + } while (0) + + +static __inline__ uint32_t INPLL(uint32_t addr) +{ + OUTREG8(CLOCK_CNTL_INDEX, addr & 0x0000001f); + return (INREG(CLOCK_CNTL_DATA)); +} + +#define OUTPLL(addr,val) OUTREG8(CLOCK_CNTL_INDEX, (addr & 0x0000001f) | 0x00000080); \ + OUTREG(CLOCK_CNTL_DATA, val) +#define OUTPLLP(addr,val,mask) \ + do { \ + unsigned int _tmp = INPLL(addr); \ + _tmp &= (mask); \ + _tmp |= (val); \ + OUTPLL(addr, _tmp); \ + } while (0) + +static uint32_t radeon_vid_get_dbpp( void ) +{ + uint32_t dbpp,retval; + dbpp = (INREG(CRTC_GEN_CNTL)>>8)& 0xF; + switch(dbpp) + { + case DST_8BPP: retval = 8; break; + case DST_15BPP: retval = 15; break; + case DST_16BPP: retval = 16; break; + case DST_24BPP: retval = 24; break; + default: retval=32; break; + } + return retval; +} + +static int radeon_is_dbl_scan( void ) +{ + return (INREG(CRTC_GEN_CNTL))&CRTC_DBL_SCAN_EN; +} + +static int radeon_is_interlace( void ) +{ + return (INREG(CRTC_GEN_CNTL))&CRTC_INTERLACE_EN; +} + +static uint32_t radeon_get_xres( void ) +{ + /* FIXME: currently we extract that from CRTC!!!*/ + uint32_t xres,h_total; + h_total = INREG(CRTC_H_TOTAL_DISP); + xres = (h_total >> 16) & 0xffff; + return (xres + 1)*8; +} + +static uint32_t radeon_get_yres( void ) +{ + /* FIXME: currently we extract that from CRTC!!!*/ + uint32_t yres,v_total; + v_total = INREG(CRTC_V_TOTAL_DISP); + yres = (v_total >> 16) & 0xffff; + return yres + 1; +} + +static void radeon_wait_vsync(void) +{ + int i; + + OUTREG(GEN_INT_STATUS, VSYNC_INT_AK); + for (i = 0; i < 2000000; i++) + { + if (INREG(GEN_INT_STATUS) & VSYNC_INT) break; + } +} + +#ifdef RAGE128 +static void _radeon_engine_idle(void); +static void _radeon_fifo_wait(unsigned); +#define radeon_engine_idle() _radeon_engine_idle() +#define radeon_fifo_wait(entries) _radeon_fifo_wait(entries) +/* Flush all dirty data in the Pixel Cache to memory. */ +static __inline__ void radeon_engine_flush ( void ) +{ + unsigned i; + + OUTREGP(PC_NGUI_CTLSTAT, PC_FLUSH_ALL, ~PC_FLUSH_ALL); + for (i = 0; i < 2000000; i++) { + if (!(INREG(PC_NGUI_CTLSTAT) & PC_BUSY)) break; + } +} + +/* Reset graphics card to known state. */ +static void radeon_engine_reset( void ) +{ + uint32_t clock_cntl_index; + uint32_t mclk_cntl; + uint32_t gen_reset_cntl; + + radeon_engine_flush(); + + clock_cntl_index = INREG(CLOCK_CNTL_INDEX); + mclk_cntl = INPLL(MCLK_CNTL); + + OUTPLL(MCLK_CNTL, mclk_cntl | FORCE_GCP | FORCE_PIPE3D_CP); + + gen_reset_cntl = INREG(GEN_RESET_CNTL); + + OUTREG(GEN_RESET_CNTL, gen_reset_cntl | SOFT_RESET_GUI); + INREG(GEN_RESET_CNTL); + OUTREG(GEN_RESET_CNTL, + gen_reset_cntl & (uint32_t)(~SOFT_RESET_GUI)); + INREG(GEN_RESET_CNTL); + + OUTPLL(MCLK_CNTL, mclk_cntl); + OUTREG(CLOCK_CNTL_INDEX, clock_cntl_index); + OUTREG(GEN_RESET_CNTL, gen_reset_cntl); +} +#else + +static __inline__ void radeon_engine_flush ( void ) +{ + int i; + + /* initiate flush */ + OUTREGP(RB2D_DSTCACHE_CTLSTAT, RB2D_DC_FLUSH_ALL, + ~RB2D_DC_FLUSH_ALL); + + for (i=0; i < 2000000; i++) { + if (!(INREG(RB2D_DSTCACHE_CTLSTAT) & RB2D_DC_BUSY)) + break; + } +} + +static void _radeon_engine_idle(void); +static void _radeon_fifo_wait(unsigned); +#define radeon_engine_idle() _radeon_engine_idle() +#define radeon_fifo_wait(entries) _radeon_fifo_wait(entries) + +static void radeon_engine_reset( void ) +{ + uint32_t clock_cntl_index, mclk_cntl, rbbm_soft_reset; + + radeon_engine_flush (); + + clock_cntl_index = INREG(CLOCK_CNTL_INDEX); + mclk_cntl = INPLL(MCLK_CNTL); + + OUTPLL(MCLK_CNTL, (mclk_cntl | + FORCEON_MCLKA | + FORCEON_MCLKB | + FORCEON_YCLKA | + FORCEON_YCLKB | + FORCEON_MC | + FORCEON_AIC)); + rbbm_soft_reset = INREG(RBBM_SOFT_RESET); + + OUTREG(RBBM_SOFT_RESET, rbbm_soft_reset | + SOFT_RESET_CP | + SOFT_RESET_HI | + SOFT_RESET_SE | + SOFT_RESET_RE | + SOFT_RESET_PP | + SOFT_RESET_E2 | + SOFT_RESET_RB | + SOFT_RESET_HDP); + INREG(RBBM_SOFT_RESET); + OUTREG(RBBM_SOFT_RESET, rbbm_soft_reset & (uint32_t) + ~(SOFT_RESET_CP | + SOFT_RESET_HI | + SOFT_RESET_SE | + SOFT_RESET_RE | + SOFT_RESET_PP | + SOFT_RESET_E2 | + SOFT_RESET_RB | + SOFT_RESET_HDP)); + INREG(RBBM_SOFT_RESET); + + OUTPLL(MCLK_CNTL, mclk_cntl); + OUTREG(CLOCK_CNTL_INDEX, clock_cntl_index); + OUTREG(RBBM_SOFT_RESET, rbbm_soft_reset); + + return; +} +#endif +static void radeon_engine_restore( void ) +{ +#ifndef RAGE128 + int pitch64; + uint32_t xres,yres,bpp; + radeon_fifo_wait(1); + xres = radeon_get_xres(); + yres = radeon_get_yres(); + bpp = radeon_vid_get_dbpp(); + /* turn of all automatic flushing - we'll do it all */ + OUTREG(RB2D_DSTCACHE_MODE, 0); + + pitch64 = ((xres * (bpp / 8) + 0x3f)) >> 6; + + radeon_fifo_wait(1); + OUTREG(DEFAULT_OFFSET, (INREG(DEFAULT_OFFSET) & 0xC0000000) | + (pitch64 << 22)); + + radeon_fifo_wait(1); +#if defined(WORDS_BIGENDIAN) + OUTREGP(DP_DATATYPE, + HOST_BIG_ENDIAN_EN, ~HOST_BIG_ENDIAN_EN); +#else + OUTREGP(DP_DATATYPE, 0, ~HOST_BIG_ENDIAN_EN); +#endif + + radeon_fifo_wait(1); + OUTREG(DEFAULT_SC_BOTTOM_RIGHT, (DEFAULT_SC_RIGHT_MAX + | DEFAULT_SC_BOTTOM_MAX)); + radeon_fifo_wait(1); + OUTREG(DP_GUI_MASTER_CNTL, (INREG(DP_GUI_MASTER_CNTL) + | GMC_BRUSH_SOLID_COLOR + | GMC_SRC_DATATYPE_COLOR)); + + radeon_fifo_wait(7); + OUTREG(DST_LINE_START, 0); + OUTREG(DST_LINE_END, 0); + OUTREG(DP_BRUSH_FRGD_CLR, 0xffffffff); + OUTREG(DP_BRUSH_BKGD_CLR, 0x00000000); + OUTREG(DP_SRC_FRGD_CLR, 0xffffffff); + OUTREG(DP_SRC_BKGD_CLR, 0x00000000); + OUTREG(DP_WRITE_MASK, 0xffffffff); + + radeon_engine_idle(); +#endif +} +#ifdef RAGE128 +static void _radeon_fifo_wait (unsigned entries) +{ + unsigned i; + + for(;;) + { + for (i=0; i<2000000; i++) + if ((INREG(GUI_STAT) & GUI_FIFOCNT_MASK) >= entries) + return; + radeon_engine_reset(); + radeon_engine_restore(); + } +} + +static void _radeon_engine_idle ( void ) +{ + unsigned i; + + /* ensure FIFO is empty before waiting for idle */ + radeon_fifo_wait (64); + for(;;) + { + for (i=0; i<2000000; i++) { + if ((INREG(GUI_STAT) & GUI_ACTIVE) == 0) { + radeon_engine_flush (); + return; + } + } + radeon_engine_reset(); + radeon_engine_restore(); + } +} +#else +static void _radeon_fifo_wait (unsigned entries) +{ + unsigned i; + + for(;;) + { + for (i=0; i<2000000; i++) + if ((INREG(RBBM_STATUS) & RBBM_FIFOCNT_MASK) >= entries) + return; + radeon_engine_reset(); + radeon_engine_restore(); + } +} +static void _radeon_engine_idle ( void ) +{ + int i; + + /* ensure FIFO is empty before waiting for idle */ + radeon_fifo_wait (64); + for(;;) + { + for (i=0; i<2000000; i++) { + if (((INREG(RBBM_STATUS) & RBBM_ACTIVE)) == 0) { + radeon_engine_flush (); + return; + } + } + radeon_engine_reset(); + radeon_engine_restore(); + } +} +#endif + +#ifndef RAGE128 +/* Reference color space transform data */ +typedef struct tagREF_TRANSFORM +{ + float RefLuma; + float RefRCb; + float RefRCr; + float RefGCb; + float RefGCr; + float RefBCb; + float RefBCr; +} REF_TRANSFORM; + +/* Parameters for ITU-R BT.601 and ITU-R BT.709 colour spaces */ +REF_TRANSFORM trans[2] = +{ + {1.1678, 0.0, 1.6007, -0.3929, -0.8154, 2.0232, 0.0}, /* BT.601 */ + {1.1678, 0.0, 1.7980, -0.2139, -0.5345, 2.1186, 0.0} /* BT.709 */ +}; +/**************************************************************************** + * SetTransform * + * Function: Calculates and sets color space transform from supplied * + * reference transform, gamma, brightness, contrast, hue and * + * saturation. * + * Inputs: bright - brightness * + * cont - contrast * + * sat - saturation * + * hue - hue * + * red_intensity - intense of red component * + * green_intensity - intense of green component * + * blue_intensity - intense of blue component * + * ref - index to the table of refernce transforms * + * Outputs: NONE * + ****************************************************************************/ + +static void radeon_set_transform(float bright, float cont, float sat, + float hue, float red_intensity, + float green_intensity,float blue_intensity, + unsigned ref) +{ + float OvHueSin, OvHueCos; + float CAdjLuma, CAdjOff; + float RedAdj,GreenAdj,BlueAdj; + float CAdjRCb, CAdjRCr; + float CAdjGCb, CAdjGCr; + float CAdjBCb, CAdjBCr; + float OvLuma, OvROff, OvGOff, OvBOff; + float OvRCb, OvRCr; + float OvGCb, OvGCr; + float OvBCb, OvBCr; + float Loff = 64.0; + float Coff = 512.0f; + + uint32_t dwOvLuma, dwOvROff, dwOvGOff, dwOvBOff; + uint32_t dwOvRCb, dwOvRCr; + uint32_t dwOvGCb, dwOvGCr; + uint32_t dwOvBCb, dwOvBCr; + + if (ref >= 2) return; + + OvHueSin = sin((double)hue); + OvHueCos = cos((double)hue); + + CAdjLuma = cont * trans[ref].RefLuma; + CAdjOff = cont * trans[ref].RefLuma * bright * 1023.0; + RedAdj = cont * trans[ref].RefLuma * red_intensity * 1023.0; + GreenAdj = cont * trans[ref].RefLuma * green_intensity * 1023.0; + BlueAdj = cont * trans[ref].RefLuma * blue_intensity * 1023.0; + + CAdjRCb = sat * -OvHueSin * trans[ref].RefRCr; + CAdjRCr = sat * OvHueCos * trans[ref].RefRCr; + CAdjGCb = sat * (OvHueCos * trans[ref].RefGCb - OvHueSin * trans[ref].RefGCr); + CAdjGCr = sat * (OvHueSin * trans[ref].RefGCb + OvHueCos * trans[ref].RefGCr); + CAdjBCb = sat * OvHueCos * trans[ref].RefBCb; + CAdjBCr = sat * OvHueSin * trans[ref].RefBCb; + +#if 0 /* default constants */ + CAdjLuma = 1.16455078125; + + CAdjRCb = 0.0; + CAdjRCr = 1.59619140625; + CAdjGCb = -0.39111328125; + CAdjGCr = -0.8125; + CAdjBCb = 2.01708984375; + CAdjBCr = 0; +#endif + OvLuma = CAdjLuma; + OvRCb = CAdjRCb; + OvRCr = CAdjRCr; + OvGCb = CAdjGCb; + OvGCr = CAdjGCr; + OvBCb = CAdjBCb; + OvBCr = CAdjBCr; + OvROff = RedAdj + CAdjOff - + OvLuma * Loff - (OvRCb + OvRCr) * Coff; + OvGOff = GreenAdj + CAdjOff - + OvLuma * Loff - (OvGCb + OvGCr) * Coff; + OvBOff = BlueAdj + CAdjOff - + OvLuma * Loff - (OvBCb + OvBCr) * Coff; +#if 0 /* default constants */ + OvROff = -888.5; + OvGOff = 545; + OvBOff = -1104; +#endif + + dwOvROff = ((int)(OvROff * 2.0)) & 0x1fff; + dwOvGOff = (int)(OvGOff * 2.0) & 0x1fff; + dwOvBOff = (int)(OvBOff * 2.0) & 0x1fff; + /* Whatever docs say about R200 having 3.8 format instead of 3.11 + as in Radeon is a lie */ +#if 0 + if(!IsR200) + { +#endif + dwOvLuma =(((int)(OvLuma * 2048.0))&0x7fff)<<17; + dwOvRCb = (((int)(OvRCb * 2048.0))&0x7fff)<<1; + dwOvRCr = (((int)(OvRCr * 2048.0))&0x7fff)<<17; + dwOvGCb = (((int)(OvGCb * 2048.0))&0x7fff)<<1; + dwOvGCr = (((int)(OvGCr * 2048.0))&0x7fff)<<17; + dwOvBCb = (((int)(OvBCb * 2048.0))&0x7fff)<<1; + dwOvBCr = (((int)(OvBCr * 2048.0))&0x7fff)<<17; +#if 0 + } + else + { + dwOvLuma = (((int)(OvLuma * 256.0))&0x7ff)<<20; + dwOvRCb = (((int)(OvRCb * 256.0))&0x7ff)<<4; + dwOvRCr = (((int)(OvRCr * 256.0))&0x7ff)<<20; + dwOvGCb = (((int)(OvGCb * 256.0))&0x7ff)<<4; + dwOvGCr = (((int)(OvGCr * 256.0))&0x7ff)<<20; + dwOvBCb = (((int)(OvBCb * 256.0))&0x7ff)<<4; + dwOvBCr = (((int)(OvBCr * 256.0))&0x7ff)<<20; + } +#endif + OUTREG(OV0_LIN_TRANS_A, dwOvRCb | dwOvLuma); + OUTREG(OV0_LIN_TRANS_B, dwOvROff | dwOvRCr); + OUTREG(OV0_LIN_TRANS_C, dwOvGCb | dwOvLuma); + OUTREG(OV0_LIN_TRANS_D, dwOvGOff | dwOvGCr); + OUTREG(OV0_LIN_TRANS_E, dwOvBCb | dwOvLuma); + OUTREG(OV0_LIN_TRANS_F, dwOvBOff | dwOvBCr); +} + +/* Gamma curve definition */ +typedef struct +{ + unsigned int gammaReg; + unsigned int gammaSlope; + unsigned int gammaOffset; +}GAMMA_SETTINGS; + +/* Recommended gamma curve parameters */ +GAMMA_SETTINGS r200_def_gamma[18] = +{ + {OV0_GAMMA_0_F, 0x100, 0x0000}, + {OV0_GAMMA_10_1F, 0x100, 0x0020}, + {OV0_GAMMA_20_3F, 0x100, 0x0040}, + {OV0_GAMMA_40_7F, 0x100, 0x0080}, + {OV0_GAMMA_80_BF, 0x100, 0x0100}, + {OV0_GAMMA_C0_FF, 0x100, 0x0100}, + {OV0_GAMMA_100_13F, 0x100, 0x0200}, + {OV0_GAMMA_140_17F, 0x100, 0x0200}, + {OV0_GAMMA_180_1BF, 0x100, 0x0300}, + {OV0_GAMMA_1C0_1FF, 0x100, 0x0300}, + {OV0_GAMMA_200_23F, 0x100, 0x0400}, + {OV0_GAMMA_240_27F, 0x100, 0x0400}, + {OV0_GAMMA_280_2BF, 0x100, 0x0500}, + {OV0_GAMMA_2C0_2FF, 0x100, 0x0500}, + {OV0_GAMMA_300_33F, 0x100, 0x0600}, + {OV0_GAMMA_340_37F, 0x100, 0x0600}, + {OV0_GAMMA_380_3BF, 0x100, 0x0700}, + {OV0_GAMMA_3C0_3FF, 0x100, 0x0700} +}; + +GAMMA_SETTINGS r100_def_gamma[6] = +{ + {OV0_GAMMA_0_F, 0x100, 0x0000}, + {OV0_GAMMA_10_1F, 0x100, 0x0020}, + {OV0_GAMMA_20_3F, 0x100, 0x0040}, + {OV0_GAMMA_40_7F, 0x100, 0x0080}, + {OV0_GAMMA_380_3BF, 0x100, 0x0100}, + {OV0_GAMMA_3C0_3FF, 0x100, 0x0100} +}; + +static void make_default_gamma_correction( void ) +{ + size_t i; + if((besr.chip_flags & R_100)==R_100|| + (besr.chip_flags & R_120)==R_120|| + (besr.chip_flags & R_150)==R_150){ + OUTREG(OV0_LIN_TRANS_A, 0x12A00000); + OUTREG(OV0_LIN_TRANS_B, 0x199018FE); + OUTREG(OV0_LIN_TRANS_C, 0x12A0F9B0); + OUTREG(OV0_LIN_TRANS_D, 0xF2F0043B); + OUTREG(OV0_LIN_TRANS_E, 0x12A02050); + OUTREG(OV0_LIN_TRANS_F, 0x0000174E); + for(i=0; i<6; i++){ + OUTREG(r100_def_gamma[i].gammaReg, + (r100_def_gamma[i].gammaSlope<<16) | + r100_def_gamma[i].gammaOffset); + } + } + else{ + OUTREG(OV0_LIN_TRANS_A, 0x12a20000); + OUTREG(OV0_LIN_TRANS_B, 0x198a190e); + OUTREG(OV0_LIN_TRANS_C, 0x12a2f9da); + OUTREG(OV0_LIN_TRANS_D, 0xf2fe0442); + OUTREG(OV0_LIN_TRANS_E, 0x12a22046); + OUTREG(OV0_LIN_TRANS_F, 0x175f); + /* Default Gamma, + Of 18 segments for gamma cure, all segments in R200 are programmable, + while only lower 4 and upper 2 segments are programmable in Radeon*/ + for(i=0; i<18; i++){ + OUTREG(r200_def_gamma[i].gammaReg, + (r200_def_gamma[i].gammaSlope<<16) | + r200_def_gamma[i].gammaOffset); + } + } +} +#endif + +static void radeon_vid_make_default(void) +{ +#ifdef RAGE128 + besr.saturation = 0x0F; + besr.brightness = 0; + OUTREG(OV0_COLOUR_CNTL,0x000F0F00UL); /* Default brihgtness and saturation for Rage128 */ +#else + make_default_gamma_correction(); +#endif + besr.deinterlace_pattern = 0x900AAAAA; + OUTREG(OV0_DEINTERLACE_PATTERN,besr.deinterlace_pattern); + besr.deinterlace_on=1; + besr.double_buff=1; + besr.graphics_key_msk=0; + besr.graphics_key_clr=0; + besr.ckey_cntl = VIDEO_KEY_FN_TRUE|GRAPHIC_KEY_FN_TRUE|CMP_MIX_AND; +} + + +unsigned VIDIX_NAME(vixGetVersion)( void ) { return VIDIX_VERSION; } + + +static int find_chip(unsigned chip_id) +{ + unsigned i; + for(i = 0;i < sizeof(ati_card_ids)/sizeof(ati_card_ids_t);i++) + { + if(chip_id == ati_card_ids[i].id) return i; + } + return -1; +} + +static pciinfo_t pci_info; +static int probed=0; + +vidix_capability_t def_cap = +{ +#ifdef RAGE128 + "BES driver for rage128 cards", +#else + "BES driver for radeon cards", +#endif + "Nick Kurshev", + TYPE_OUTPUT | TYPE_FX, + { 0, 0, 0, 0 }, + 2048, + 2048, + 4, + 4, + -1, + FLAG_UPSCALER | FLAG_DOWNSCALER | FLAG_EQUALIZER, + VENDOR_ATI, + 0, + { 0, 0, 0, 0} +}; + + +int VIDIX_NAME(vixProbe)( int verbose,int force ) +{ + pciinfo_t lst[MAX_PCI_DEVICES]; + unsigned i,num_pci; + int err; + __verbose = verbose; + err = pci_scan(lst,&num_pci); + if(err) + { + printf(RADEON_MSG" Error occured during pci scan: %s\n",strerror(err)); + return err; + } + else + { + err = ENXIO; + for(i=0;i<num_pci;i++) + { + if(lst[i].vendor == VENDOR_ATI) + { + int idx; + const char *dname; + idx = find_chip(lst[i].device); + if(idx == -1 && force == PROBE_NORMAL) continue; + dname = pci_device_name(VENDOR_ATI,lst[i].device); + dname = dname ? dname : "Unknown chip"; + printf(RADEON_MSG" Found chip: %s\n",dname); + memset(&besr,0,sizeof(bes_registers_t)); + if(force > PROBE_NORMAL) + { + printf(RADEON_MSG" Driver was forced. Was found %sknown chip\n",idx == -1 ? "un" : ""); + if(idx == -1) +#ifdef RAGE128 + printf(RADEON_MSG" Assuming it as Rage128\n"); +#else + printf(RADEON_MSG" Assuming it as Radeon1\n"); +#endif + besr.chip_flags=R_100|R_OVL_SHIFT; + } + if(idx != -1) besr.chip_flags=ati_card_ids[idx].flags; + def_cap.device_id = lst[i].device; + err = 0; + memcpy(&pci_info,&lst[i],sizeof(pciinfo_t)); + probed=1; + break; + } + } + } + if(err && verbose) printf(RADEON_MSG" Can't find chip\n"); + return err; +} + +#ifndef RAGE128 +enum radeon_montype +{ + MT_NONE, + MT_CRT, /* CRT-(cathode ray tube) analog monitor. (15-pin VGA connector) */ + MT_LCD, /* Liquid Crystal Display */ + MT_DFP, /* DFP-digital flat panel monitor. (24-pin DVI-I connector) */ + MT_CTV, /* Composite TV out (not in VE) */ + MT_STV /* S-Video TV out (probably in VE only) */ +}; + +typedef struct radeon_info_s +{ + int hasCRTC2; + int crtDispType; + int dviDispType; +}rinfo_t; + +static rinfo_t rinfo; + +static char * GET_MON_NAME(int type) +{ + char *pret; + switch(type) + { + case MT_NONE: pret = "no"; break; + case MT_CRT: pret = "CRT"; break; + case MT_DFP: pret = "DFP"; break; + case MT_LCD: pret = "LCD"; break; + case MT_CTV: pret = "CTV"; break; + case MT_STV: pret = "STV"; break; + default: pret = "Unknown"; + } + return pret; +} + +static void radeon_get_moninfo (rinfo_t *rinfo) +{ + unsigned int tmp; + + tmp = INREG(RADEON_BIOS_4_SCRATCH); + + if (rinfo->hasCRTC2) { + /* primary DVI port */ + if (tmp & 0x08) + rinfo->dviDispType = MT_DFP; + else if (tmp & 0x4) + rinfo->dviDispType = MT_LCD; + else if (tmp & 0x200) + rinfo->dviDispType = MT_CRT; + else if (tmp & 0x10) + rinfo->dviDispType = MT_CTV; + else if (tmp & 0x20) + rinfo->dviDispType = MT_STV; + + /* secondary CRT port */ + if (tmp & 0x2) + rinfo->crtDispType = MT_CRT; + else if (tmp & 0x800) + rinfo->crtDispType = MT_DFP; + else if (tmp & 0x400) + rinfo->crtDispType = MT_LCD; + else if (tmp & 0x1000) + rinfo->crtDispType = MT_CTV; + else if (tmp & 0x2000) + rinfo->crtDispType = MT_STV; + } else { + rinfo->dviDispType = MT_NONE; + + tmp = INREG(FP_GEN_CNTL); + + if (tmp & FP_EN_TMDS) + rinfo->crtDispType = MT_DFP; + else + rinfo->crtDispType = MT_CRT; + } +} +#endif + +typedef struct saved_regs_s +{ + uint32_t ov0_vid_key_clr; + uint32_t ov0_vid_key_msk; + uint32_t ov0_graphics_key_clr; + uint32_t ov0_graphics_key_msk; + uint32_t ov0_key_cntl; +}saved_regs_t; +static saved_regs_t savreg; + +static void save_regs( void ) +{ + radeon_fifo_wait(6); + savreg.ov0_vid_key_clr = INREG(OV0_VID_KEY_CLR); + savreg.ov0_vid_key_msk = INREG(OV0_VID_KEY_MSK); + savreg.ov0_graphics_key_clr = INREG(OV0_GRAPHICS_KEY_CLR); + savreg.ov0_graphics_key_msk = INREG(OV0_GRAPHICS_KEY_MSK); + savreg.ov0_key_cntl = INREG(OV0_KEY_CNTL); +} + +static void restore_regs( void ) +{ + radeon_fifo_wait(6); + OUTREG(OV0_VID_KEY_CLR,savreg.ov0_vid_key_clr); + OUTREG(OV0_VID_KEY_MSK,savreg.ov0_vid_key_msk); + OUTREG(OV0_GRAPHICS_KEY_CLR,savreg.ov0_graphics_key_clr); + OUTREG(OV0_GRAPHICS_KEY_MSK,savreg.ov0_graphics_key_msk); + OUTREG(OV0_KEY_CNTL,savreg.ov0_key_cntl); +} + +int VIDIX_NAME(vixInit)( const char *args ) +{ + int err; + if(!probed) + { + printf(RADEON_MSG" Driver was not probed but is being initializing\n"); + return EINTR; + } + if((radeon_mmio_base = map_phys_mem(pci_info.base2,0xFFFF))==(void *)-1) return ENOMEM; + radeon_ram_size = INREG(CONFIG_MEMSIZE); + /* mem size is bits [28:0], mask off the rest. Range: from 1Mb up to 512 Mb */ + radeon_ram_size &= CONFIG_MEMSIZE_MASK; +#ifdef RADEON + /* according to XFree86 4.2.0, some production M6's return 0 for 8MB */ + if (radeon_ram_size == 0 && + (def_cap.device_id == DEVICE_ATI_RADEON_MOBILITY_M6 || + def_cap.device_id == DEVICE_ATI_RADEON_MOBILITY_M62)) + { + printf(RADEON_MSG" Workarounding buggy Radeon Mobility M6 (0 vs. 8MB ram)\n"); + radeon_ram_size = 8192*1024; + } +#else + /* Rage Mobility (rage128) also has memsize bug */ + if (radeon_ram_size == 0 && + (def_cap.device_id == DEVICE_ATI_RAGE_MOBILITY_M3 || + def_cap.device_id == DEVICE_ATI_RAGE_MOBILITY_M32)) + { + printf(RADEON_MSG" Workarounding buggy Rage Mobility M3 (0 vs. 8MB ram)\n"); + radeon_ram_size = 8192*1024; + } +#endif + if((radeon_mem_base = map_phys_mem(pci_info.base0,radeon_ram_size))==(void *)-1) return ENOMEM; + radeon_vid_make_default(); + printf(RADEON_MSG" Video memory = %uMb\n",radeon_ram_size/0x100000); + err = mtrr_set_type(pci_info.base0,radeon_ram_size,MTRR_TYPE_WRCOMB); + if(!err) printf(RADEON_MSG" Set write-combining type of video memory\n"); +#ifndef RAGE128 + { + memset(&rinfo,0,sizeof(rinfo_t)); + if((besr.chip_flags&R_100) != R_100) rinfo.hasCRTC2 = 1; + + radeon_get_moninfo(&rinfo); + if(rinfo.hasCRTC2) { + printf(RADEON_MSG" DVI port has %s monitor connected\n",GET_MON_NAME(rinfo.dviDispType)); + printf(RADEON_MSG" CRT port has %s monitor connected\n",GET_MON_NAME(rinfo.crtDispType)); + } + else + printf(RADEON_MSG" CRT port has %s monitor connected\n",GET_MON_NAME(rinfo.crtDispType)); + } +#endif +#ifdef RADEON_ENABLE_BM + if(bm_open() == 0) + { + if((dma_phys_addrs = malloc(radeon_ram_size*sizeof(unsigned long)/4096)) != 0) + def_cap.flags |= FLAG_DMA | FLAG_EQ_DMA; + else + printf(RADEON_MSG" Can't allocate temopary buffer for DMA\n"); + } + else + if(__verbose) printf(RADEON_MSG" Can't initialize busmastering: %s\n",strerror(errno)); +#endif + save_regs(); + return 0; +} + +void VIDIX_NAME(vixDestroy)( void ) +{ + restore_regs(); + unmap_phys_mem(radeon_mem_base,radeon_ram_size); + unmap_phys_mem(radeon_mmio_base,0xFFFF); + bm_close(); +} + +int VIDIX_NAME(vixGetCapability)(vidix_capability_t *to) +{ + memcpy(to,&def_cap,sizeof(vidix_capability_t)); + return 0; +} + +/* + Full list of fourcc which are supported by Win2K radeon driver: + YUY2, UYVY, DDES, OGLT, OGL2, OGLS, OGLB, OGNT, OGNZ, OGNS, + IF09, YVU9, IMC4, M2IA, IYUV, VBID, DXT1, DXT2, DXT3, DXT4, DXT5 +*/ +typedef struct fourcc_desc_s +{ + uint32_t fourcc; + unsigned max_srcw; +}fourcc_desc_t; + +fourcc_desc_t supported_fourcc[] = +{ + { IMGFMT_Y800, 1567 }, + { IMGFMT_YVU9, 1567 }, + { IMGFMT_IF09, 1567 }, + { IMGFMT_YV12, 1567 }, + { IMGFMT_I420, 1567 }, + { IMGFMT_IYUV, 1567 }, + { IMGFMT_UYVY, 1551 }, + { IMGFMT_YUY2, 1551 }, + { IMGFMT_YVYU, 1551 }, + { IMGFMT_RGB15, 1551 }, + { IMGFMT_BGR15, 1551 }, + { IMGFMT_RGB16, 1551 }, + { IMGFMT_BGR16, 1551 }, + { IMGFMT_RGB32, 775 }, + { IMGFMT_BGR32, 775 } +}; + +__inline__ static int is_supported_fourcc(uint32_t fourcc,unsigned srcw) +{ + unsigned i; + for(i=0;i<sizeof(supported_fourcc)/sizeof(fourcc_desc_t);i++) + { + if(fourcc==supported_fourcc[i].fourcc && + srcw <=supported_fourcc[i].max_srcw) return 1; + } + return 0; +} + +int VIDIX_NAME(vixQueryFourcc)(vidix_fourcc_t *to) +{ + if(is_supported_fourcc(to->fourcc,to->srcw)) + { + to->depth = VID_DEPTH_1BPP | VID_DEPTH_2BPP | + VID_DEPTH_4BPP | VID_DEPTH_8BPP | + VID_DEPTH_12BPP| VID_DEPTH_15BPP| + VID_DEPTH_16BPP| VID_DEPTH_24BPP| + VID_DEPTH_32BPP; + to->flags = VID_CAP_EXPAND | VID_CAP_SHRINK | VID_CAP_COLORKEY; + return 0; + } + else to->depth = to->flags = 0; + return ENOSYS; +} + +static double H_scale_ratio; +static void radeon_vid_dump_regs( void ) +{ + size_t i; + printf(RADEON_MSG"*** Begin of DRIVER variables dump ***\n"); + printf(RADEON_MSG"radeon_mmio_base=%p\n",radeon_mmio_base); + printf(RADEON_MSG"radeon_mem_base=%p\n",radeon_mem_base); + printf(RADEON_MSG"radeon_overlay_off=%08X\n",radeon_overlay_off); + printf(RADEON_MSG"radeon_ram_size=%08X\n",radeon_ram_size); + printf(RADEON_MSG"video mode: %ux%u@%u\n",radeon_get_xres(),radeon_get_yres(),radeon_vid_get_dbpp()); + printf(RADEON_MSG"H_scale_ratio=%8.2f\n",H_scale_ratio); + printf(RADEON_MSG"*** Begin of OV0 registers dump ***\n"); + for(i=0;i<sizeof(vregs)/sizeof(video_registers_t);i++) + printf(RADEON_MSG"%s = %08X\n",vregs[i].sname,INREG(vregs[i].name)); + printf(RADEON_MSG"*** End of OV0 registers dump ***\n"); +} + +static void radeon_vid_stop_video( void ) +{ + radeon_engine_idle(); + OUTREG(OV0_SCALE_CNTL, SCALER_SOFT_RESET); + OUTREG(OV0_EXCLUSIVE_HORZ, 0); + OUTREG(OV0_AUTO_FLIP_CNTL, 0); /* maybe */ + OUTREG(OV0_FILTER_CNTL, FILTER_HARDCODED_COEF); +#ifdef RAGE128 + OUTREG(OV0_KEY_CNTL, GRAPHIC_KEY_FN_NE); +#else + OUTREG(OV0_KEY_CNTL, GRAPHIC_KEY_FN_EQ); +#endif + OUTREG(OV0_TEST, 0); +} + +static void radeon_vid_display_video( void ) +{ + int bes_flags; + radeon_fifo_wait(2); + OUTREG(OV0_REG_LOAD_CNTL, REG_LD_CTL_LOCK); + radeon_engine_idle(); + while(!(INREG(OV0_REG_LOAD_CNTL)®_LD_CTL_LOCK_READBACK)); + radeon_fifo_wait(15); + + /* Shutdown capturing */ + OUTREG(FCP_CNTL, FCP_CNTL__GND); + OUTREG(CAP0_TRIG_CNTL, 0); + + OUTREG(VID_BUFFER_CONTROL, (1<<16) | 0x01); + OUTREG(DISP_TEST_DEBUG_CNTL, 0); + + OUTREG(OV0_AUTO_FLIP_CNTL,OV0_AUTO_FLIP_CNTL_SOFT_BUF_ODD); + + if(besr.deinterlace_on) OUTREG(OV0_DEINTERLACE_PATTERN,besr.deinterlace_pattern); +#ifdef RAGE128 + OUTREG(OV0_COLOUR_CNTL, (besr.brightness & 0x7f) | + (besr.saturation << 8) | + (besr.saturation << 16)); +#endif + radeon_fifo_wait(2); + OUTREG(OV0_GRAPHICS_KEY_MSK, besr.graphics_key_msk); + OUTREG(OV0_GRAPHICS_KEY_CLR, besr.graphics_key_clr); + OUTREG(OV0_KEY_CNTL,besr.ckey_cntl); + + OUTREG(OV0_H_INC, besr.h_inc); + OUTREG(OV0_STEP_BY, besr.step_by); + OUTREG(OV0_Y_X_START, besr.y_x_start); + OUTREG(OV0_Y_X_END, besr.y_x_end); + OUTREG(OV0_V_INC, besr.v_inc); + OUTREG(OV0_P1_BLANK_LINES_AT_TOP, besr.p1_blank_lines_at_top); + OUTREG(OV0_P23_BLANK_LINES_AT_TOP, besr.p23_blank_lines_at_top); + OUTREG(OV0_VID_BUF_PITCH0_VALUE, besr.vid_buf_pitch0_value); + OUTREG(OV0_VID_BUF_PITCH1_VALUE, besr.vid_buf_pitch1_value); + OUTREG(OV0_P1_X_START_END, besr.p1_x_start_end); + OUTREG(OV0_P2_X_START_END, besr.p2_x_start_end); + OUTREG(OV0_P3_X_START_END, besr.p3_x_start_end); +#ifdef RADEON + OUTREG(OV0_BASE_ADDR, besr.base_addr); +#endif + OUTREG(OV0_VID_BUF0_BASE_ADRS, besr.vid_buf_base_adrs_y[0]); + OUTREG(OV0_VID_BUF1_BASE_ADRS, besr.vid_buf_base_adrs_v[0]); + OUTREG(OV0_VID_BUF2_BASE_ADRS, besr.vid_buf_base_adrs_u[0]); + radeon_fifo_wait(9); + OUTREG(OV0_VID_BUF3_BASE_ADRS, besr.vid_buf_base_adrs_y[0]); + OUTREG(OV0_VID_BUF4_BASE_ADRS, besr.vid_buf_base_adrs_v[0]); + OUTREG(OV0_VID_BUF5_BASE_ADRS, besr.vid_buf_base_adrs_u[0]); + OUTREG(OV0_P1_V_ACCUM_INIT, besr.p1_v_accum_init); + OUTREG(OV0_P1_H_ACCUM_INIT, besr.p1_h_accum_init); + OUTREG(OV0_P23_H_ACCUM_INIT, besr.p23_h_accum_init); + OUTREG(OV0_P23_V_ACCUM_INIT, besr.p23_v_accum_init); + + bes_flags = SCALER_ENABLE | + SCALER_SMART_SWITCH | + SCALER_Y2R_TEMP | + SCALER_PIX_EXPAND; + if(besr.double_buff) bes_flags |= SCALER_DOUBLE_BUFFER; + if(besr.deinterlace_on) bes_flags |= SCALER_ADAPTIVE_DEINT; + if(besr.horz_pick_nearest) bes_flags |= SCALER_HORZ_PICK_NEAREST; + if(besr.vert_pick_nearest) bes_flags |= SCALER_VERT_PICK_NEAREST; +#ifdef RAGE128 + bes_flags |= SCALER_BURST_PER_PLANE; +#endif + bes_flags |= (besr.surf_id << 8) & SCALER_SURFAC_FORMAT; + if(besr.load_prg_start) bes_flags |= SCALER_PRG_LOAD_START; + OUTREG(OV0_SCALE_CNTL, bes_flags); +#ifndef RAGE128 + if(rinfo.hasCRTC2 && + (rinfo.dviDispType == MT_CTV || rinfo.dviDispType == MT_STV)) + { + /* TODO: suppress scaler output to CRTC here and enable TVO only */ + } +#endif + radeon_fifo_wait(6); + OUTREG(OV0_FILTER_CNTL,besr.filter_cntl); + OUTREG(OV0_FOUR_TAP_COEF_0,besr.four_tap_coeff[0]); + OUTREG(OV0_FOUR_TAP_COEF_1,besr.four_tap_coeff[1]); + OUTREG(OV0_FOUR_TAP_COEF_2,besr.four_tap_coeff[2]); + OUTREG(OV0_FOUR_TAP_COEF_3,besr.four_tap_coeff[3]); + OUTREG(OV0_FOUR_TAP_COEF_4,besr.four_tap_coeff[4]); + if(besr.swap_uv) OUTREG(OV0_TEST,INREG(OV0_TEST)|OV0_SWAP_UV); + OUTREG(OV0_REG_LOAD_CNTL, 0); + if(__verbose > VERBOSE_LEVEL) printf(RADEON_MSG"we wanted: scaler=%08X\n",bes_flags); + if(__verbose > VERBOSE_LEVEL) radeon_vid_dump_regs(); +} + +/* Goal of this function: hide RGB background and provide black screen around movie. + Useful in '-vo fbdev:vidix -fs -zoom' mode. + Reverse effect to colorkey */ +#ifdef RAGE128 +static void radeon_vid_exclusive( void ) +{ +/* this function works only with Rage128. + Radeon should has something the same */ + unsigned screenw,screenh; + screenw = radeon_get_xres(); + screenh = radeon_get_yres(); + radeon_fifo_wait(2); + OUTREG(OV0_EXCLUSIVE_VERT,(((screenh-1)<<16)&EXCL_VERT_END_MASK)); + OUTREG(OV0_EXCLUSIVE_HORZ,(((screenw/8+1)<<8)&EXCL_HORZ_END_MASK)|EXCL_HORZ_EXCLUSIVE_EN); +} + +static void radeon_vid_non_exclusive( void ) +{ + OUTREG(OV0_EXCLUSIVE_HORZ,0); +} +#endif + +static unsigned radeon_query_pitch(unsigned fourcc,const vidix_yuv_t *spitch) +{ + unsigned pitch,spy,spv,spu; + spy = spv = spu = 0; + switch(spitch->y) + { + case 16: + case 32: + case 64: + case 128: + case 256: spy = spitch->y; break; + default: break; + } + switch(spitch->u) + { + case 16: + case 32: + case 64: + case 128: + case 256: spu = spitch->u; break; + default: break; + } + switch(spitch->v) + { + case 16: + case 32: + case 64: + case 128: + case 256: spv = spitch->v; break; + default: break; + } + switch(fourcc) + { + /* 4:2:0 */ + case IMGFMT_IYUV: + case IMGFMT_YV12: + case IMGFMT_I420: + if(spy > 16 && spu == spy/2 && spv == spy/2) pitch = spy; + else pitch = 32; + break; + case IMGFMT_IF09: + case IMGFMT_YVU9: + if(spy >= 64 && spu == spy/4 && spv == spy/4) pitch = spy; + else pitch = 64; + break; + default: + if(spy >= 16) pitch = spy; + else pitch = 16; + break; + } + return pitch; +} + +static void Calc_H_INC_STEP_BY ( + int fieldvalue_OV0_SURFACE_FORMAT, + double H_scale_ratio, + int DisallowFourTapVertFiltering, + int DisallowFourTapUVVertFiltering, + uint32_t *val_OV0_P1_H_INC, + uint32_t *val_OV0_P1_H_STEP_BY, + uint32_t *val_OV0_P23_H_INC, + uint32_t *val_OV0_P23_H_STEP_BY, + int *P1GroupSize, + int *P1StepSize, + int *P23StepSize ) +{ + + double ClocksNeededFor16Pixels; + + switch (fieldvalue_OV0_SURFACE_FORMAT) + { + case 3: + case 4: /*16BPP (ARGB1555 and RGB565) */ + /* All colour components are fetched in pairs */ + *P1GroupSize = 2; + /* We don't support four tap in this mode because G's are split between two bytes. In theory we could support it if */ + /* we saved part of the G when fetching the R, and then filter the G, followed by the B in the following cycles. */ + if (H_scale_ratio>=.5) + { + /* We are actually generating two pixels (but 3 colour components) per tick. Thus we don't have to skip */ + /* until we reach .5. P1 and P23 are the same. */ + *val_OV0_P1_H_INC = (uint16_t)((1/(H_scale_ratio)) * (1<<0xc) + 0.5); + *val_OV0_P1_H_STEP_BY = 1; + *val_OV0_P23_H_INC = (uint16_t)((1/(H_scale_ratio)) * (1<<0xc) + 0.5); + *val_OV0_P23_H_STEP_BY = 1; + *P1StepSize = 1; + *P23StepSize = 1; + } + else if (H_scale_ratio>=.25) + { + /* Step by two */ + *val_OV0_P1_H_INC = (uint16_t)((1/(H_scale_ratio*2)) * (1<<0xc) + 0.5); + *val_OV0_P1_H_STEP_BY = 2; + *val_OV0_P23_H_INC = (uint16_t)((1/(H_scale_ratio*2)) * (1<<0xc) + 0.5); + *val_OV0_P23_H_STEP_BY = 2; + *P1StepSize = 2; + *P23StepSize = 2; + } + else if (H_scale_ratio>=.125) + { + /* Step by four */ + *val_OV0_P1_H_INC = (uint16_t)((1/(H_scale_ratio*4)) * (1<<0xc) + 0.5); + *val_OV0_P1_H_STEP_BY = 3; + *val_OV0_P23_H_INC = (uint16_t)((1/(H_scale_ratio*4)) * (1<<0xc) + 0.5); + *val_OV0_P23_H_STEP_BY = 3; + *P1StepSize = 4; + *P23StepSize = 4; + } + else if (H_scale_ratio>=.0625) + { + /* Step by eight */ + *val_OV0_P1_H_INC = (uint16_t)((1/(H_scale_ratio*8)) * (1<<0xc) + 0.5); + *val_OV0_P1_H_STEP_BY = 4; + *val_OV0_P23_H_INC = (uint16_t)((1/(H_scale_ratio*8)) * (1<<0xc) + 0.5); + *val_OV0_P23_H_STEP_BY = 4; + *P1StepSize = 8; + *P23StepSize = 8; + } + else if (H_scale_ratio>=0.03125) + { + /* Step by sixteen */ + *val_OV0_P1_H_INC = (uint16_t)((1/(H_scale_ratio*16)) * (1<<0xc) + 0.5); + *val_OV0_P1_H_STEP_BY = 5; + *val_OV0_P23_H_INC = (uint16_t)((1/(H_scale_ratio*16)) * (1<<0xc) + 0.5); + *val_OV0_P23_H_STEP_BY = 5; + *P1StepSize = 16; + *P23StepSize = 16; + } + else + { + H_scale_ratio=0.03125; + *val_OV0_P1_H_INC = (uint16_t)((1/(H_scale_ratio*16)) * (1<<0xc) + 0.5); + *val_OV0_P1_H_STEP_BY = 5; + *val_OV0_P23_H_INC = (uint16_t)((1/(H_scale_ratio*16)) * (1<<0xc) + 0.5); + *val_OV0_P23_H_STEP_BY = 5; + *P1StepSize = 16; + *P23StepSize = 16; + } + break; + case 6: /*32BPP RGB */ + if (H_scale_ratio>=1.5 && !DisallowFourTapVertFiltering) + { + /* All colour components are fetched in pairs */ + *P1GroupSize = 2; + /* With four tap filtering, we can generate two colour components every clock, or two pixels every three */ + /* clocks. This means that we will have four tap filtering when scaling 1.5 or more. */ + *val_OV0_P1_H_INC = (uint16_t)((1/(H_scale_ratio)) * (1<<0xc) + 0.5); + *val_OV0_P1_H_STEP_BY = 0; + *val_OV0_P23_H_INC = (uint16_t)((1/(H_scale_ratio)) * (1<<0xc) + 0.5); + *val_OV0_P23_H_STEP_BY = 0; + *P1StepSize = 1; + *P23StepSize = 1; + } + else if (H_scale_ratio>=0.75) + { + /* Four G colour components are fetched at once */ + *P1GroupSize = 4; + /* R and B colour components are fetched in pairs */ + /* With two tap filtering, we can generate four colour components every clock. */ + /* This means that we will have two tap filtering when scaling 1.0 or more. */ + *val_OV0_P1_H_INC = (uint16_t)((1/(H_scale_ratio)) * (1<<0xc) + 0.5); + *val_OV0_P1_H_STEP_BY = 1; + *val_OV0_P23_H_INC = (uint16_t)((1/(H_scale_ratio)) * (1<<0xc) + 0.5); + *val_OV0_P23_H_STEP_BY = 1; + *P1StepSize = 1; + *P23StepSize = 1; + } + else if (H_scale_ratio>=0.375) + { + /* Step by two. */ + /* Four G colour components are fetched at once */ + *P1GroupSize = 4; + /* R and B colour components are fetched in pairs */ + *val_OV0_P1_H_INC = (uint16_t)((1/(H_scale_ratio*2)) * (1<<0xc) + 0.5); + *val_OV0_P1_H_STEP_BY = 2; + *val_OV0_P23_H_INC = (uint16_t)((1/(H_scale_ratio*2)) * (1<<0xc) + 0.5); + *val_OV0_P23_H_STEP_BY = 2; + *P1StepSize = 2; + *P23StepSize = 2; + } + else if (H_scale_ratio>=0.25) + { + /* Step by two. */ + /* Four G colour components are fetched at once */ + *P1GroupSize = 4; + /* R and B colour components are fetched in pairs */ + *val_OV0_P1_H_INC = (uint16_t)((1/(H_scale_ratio*2)) * (1<<0xc) + 0.5); + *val_OV0_P1_H_STEP_BY = 2; + *val_OV0_P23_H_INC = (uint16_t)((1/(H_scale_ratio*4)) * (1<<0xc) + 0.5); + *val_OV0_P23_H_STEP_BY = 3; + *P1StepSize = 2; + *P23StepSize = 4; + } + else if (H_scale_ratio>=0.1875) + { + /* Step by four */ + /* Four G colour components are fetched at once */ + *P1GroupSize = 4; + /* R and B colour components are fetched in pairs */ + *val_OV0_P1_H_INC = (uint16_t)((1/(H_scale_ratio*4)) * (1<<0xc) + 0.5); + *val_OV0_P1_H_STEP_BY = 3; + *val_OV0_P23_H_INC = (uint16_t)((1/(H_scale_ratio*4)) * (1<<0xc) + 0.5); + *val_OV0_P23_H_STEP_BY = 3; + *P1StepSize = 4; + *P23StepSize = 4; + } + else if (H_scale_ratio>=0.125) + { + /* Step by four */ + /* Four G colour components are fetched at once */ + *P1GroupSize = 4; + /* R and B colour components are fetched in pairs */ + *val_OV0_P1_H_INC = (uint16_t)((1/(H_scale_ratio*4)) * (1<<0xc) + 0.5); + *val_OV0_P1_H_STEP_BY = 3; + *val_OV0_P23_H_INC = (uint16_t)((1/(H_scale_ratio*8)) * (1<<0xc) + 0.5); + *val_OV0_P23_H_STEP_BY = 4; + *P1StepSize = 4; + *P23StepSize = 8; + } + else if (H_scale_ratio>=0.09375) + { + /* Step by eight */ + /* Four G colour components are fetched at once */ + *P1GroupSize = 4; + /* R and B colour components are fetched in pairs */ + *val_OV0_P1_H_INC = (uint16_t)((1/(H_scale_ratio*8)) * (1<<0xc) + 0.5); + *val_OV0_P1_H_STEP_BY = 4; + *val_OV0_P23_H_INC = (uint16_t)((1/(H_scale_ratio*8)) * (1<<0xc) + 0.5); + *val_OV0_P23_H_STEP_BY = 4; + *P1StepSize = 8; + *P23StepSize = 8; + } + else if (H_scale_ratio>=0.0625) + { + /* Step by eight */ + /* Four G colour components are fetched at once */ + *P1GroupSize = 4; + /* R and B colour components are fetched in pairs */ + *val_OV0_P1_H_INC = (uint16_t)((1/(H_scale_ratio*16)) * (1<<0xc) + 0.5); + *val_OV0_P1_H_STEP_BY = 5; + *val_OV0_P23_H_INC = (uint16_t)((1/(H_scale_ratio*16)) * (1<<0xc) + 0.5); + *val_OV0_P23_H_STEP_BY = 5; + *P1StepSize = 16; + *P23StepSize = 16; + } + else + { + H_scale_ratio=0.0625; + *P1GroupSize = 4; + *val_OV0_P1_H_INC = (uint16_t)((1/(H_scale_ratio*16)) * (1<<0xc) + 0.5); + *val_OV0_P1_H_STEP_BY = 5; + *val_OV0_P23_H_INC = (uint16_t)((1/(H_scale_ratio*16)) * (1<<0xc) + 0.5); + *val_OV0_P23_H_STEP_BY = 5; + *P1StepSize = 16; + *P23StepSize = 16; + } + break; + case 9: + /*ToDo_Active: In mode 9 there is a possibility that HScale ratio may be set to an illegal value, so we have extra conditions in the if statement. For consistancy, these conditions be added to the other modes as well. */ + /* four tap on both (unless Y is too wide) */ + if ((H_scale_ratio>=(ClocksNeededFor16Pixels=8+2+2) / 16.0) && + ((uint16_t)((1/(H_scale_ratio)) * (1<<0xc) + 0.5)<=0x3000) && + ((uint16_t)((1/(H_scale_ratio*4)) * (1<<0xc) + 0.5)<=0x2000) && + !DisallowFourTapVertFiltering && !DisallowFourTapUVVertFiltering) + { /*0.75 */ + /* Colour components are fetched in pairs */ + *P1GroupSize = 2; + *val_OV0_P1_H_INC = (uint16_t)((1/(H_scale_ratio)) * (1<<0xc) + 0.5); + *val_OV0_P1_H_STEP_BY = 0; + *val_OV0_P23_H_INC = (uint16_t)((1/(H_scale_ratio*4)) * (1<<0xc) + 0.5); + *val_OV0_P23_H_STEP_BY = 0; + *P1StepSize = 1; + *P23StepSize = 1; + } + /* two tap on Y (because it is too big for four tap), four tap on UV */ + else if ((H_scale_ratio>=(ClocksNeededFor16Pixels=4+2+2) / 16.0) && + ((uint16_t)((1/(H_scale_ratio)) * (1<<0xc) + 0.5)<=0x3000) && + ((uint16_t)((1/(H_scale_ratio*4)) * (1<<0xc) + 0.5)<=0x2000) && + DisallowFourTapVertFiltering && !DisallowFourTapUVVertFiltering) + { /*0.75 */ + *P1GroupSize = 4; + *val_OV0_P1_H_INC = (uint16_t)((1/(H_scale_ratio)) * (1<<0xc) + 0.5); + *val_OV0_P1_H_STEP_BY = 1; + *val_OV0_P23_H_INC = (uint16_t)((1/(H_scale_ratio*4)) * (1<<0xc) + 0.5); + *val_OV0_P23_H_STEP_BY = 0; + *P1StepSize = 1; + *P23StepSize = 1; + } + /* We scale the Y with the four tap filters, but UV's are generated + with dual two tap configuration. */ + else if ((H_scale_ratio>=(ClocksNeededFor16Pixels=8+1+1) / 16.0) && + ((uint16_t)((1/(H_scale_ratio)) * (1<<0xc) + 0.5)<=0x3000) && + ((uint16_t)((1/(H_scale_ratio*4)) * (1<<0xc) + 0.5)<=0x2000) && + !DisallowFourTapVertFiltering) + { /*0.625 */ + *P1GroupSize = 2; + *val_OV0_P1_H_INC = (uint16_t)((1/(H_scale_ratio)) * (1<<0xc) + 0.5); + *val_OV0_P1_H_STEP_BY = 0; + *val_OV0_P23_H_INC = (uint16_t)((1/(H_scale_ratio*4)) * (1<<0xc) + 0.5); + *val_OV0_P23_H_STEP_BY = 1; + *P1StepSize = 1; + *P23StepSize = 1; + } + /* We scale the Y, U, and V with the two tap filters */ + else if ((H_scale_ratio>=(ClocksNeededFor16Pixels=4+1+1) / 16.0) && + ((uint16_t)((1/(H_scale_ratio)) * (1<<0xc) + 0.5)<=0x3000) && + ((uint16_t)((1/(H_scale_ratio*4)) * (1<<0xc) + 0.5)<=0x2000)) + { /*0.375 */ + *P1GroupSize = 4; + *val_OV0_P1_H_INC = (uint16_t)((1/(H_scale_ratio)) * (1<<0xc) + 0.5); + *val_OV0_P1_H_STEP_BY = 1; + *val_OV0_P23_H_INC = (uint16_t)((1/(H_scale_ratio*4)) * (1<<0xc) + 0.5); + *val_OV0_P23_H_STEP_BY = 1; + *P1StepSize = 1; + *P23StepSize = 1; + } + /* We scale step the U and V by two to allow more bandwidth for fetching Y's, + thus we won't drop Y's yet. */ + else if ((H_scale_ratio>=(ClocksNeededFor16Pixels=4+.5+.5) / 16.0) && + ((uint16_t)((1/(H_scale_ratio)) * (1<<0xc) + 0.5)<=0x3000) && + ((uint16_t)((1/(H_scale_ratio*4*2)) * (1<<0xc) + 0.5)<=0x2000)) + { /*>=0.3125 and >.333333~ */ + *P1GroupSize = 4; + *val_OV0_P1_H_INC = (uint16_t)((1/(H_scale_ratio)) * (1<<0xc) + 0.5); + *val_OV0_P1_H_STEP_BY = 1; + *val_OV0_P23_H_INC = (uint16_t)((1/(H_scale_ratio*4*2)) * (1<<0xc) + 0.5); + *val_OV0_P23_H_STEP_BY = 2; + *P1StepSize = 1; + *P23StepSize = 2; + } + /* We step the Y, U, and V by two. */ + else if ((H_scale_ratio>=(ClocksNeededFor16Pixels=2+.5+.5) / 16.0) && + ((uint16_t)((1/(H_scale_ratio*2)) * (1<<0xc) + 0.5)<=0x3000) && + ((uint16_t)((1/(H_scale_ratio*4*2)) * (1<<0xc) + 0.5)<=0x2000)) + { + *P1GroupSize = 4; + *val_OV0_P1_H_INC = (uint16_t)((1/(H_scale_ratio*2)) * (1<<0xc) + 0.5); + *val_OV0_P1_H_STEP_BY = 2; + *val_OV0_P23_H_INC = (uint16_t)((1/(H_scale_ratio*4*2)) * (1<<0xc) + 0.5); + *val_OV0_P23_H_STEP_BY = 2; + *P1StepSize = 2; + *P23StepSize = 2; + } + /* We step the Y by two and the U and V by four. */ + else if ((H_scale_ratio>=(ClocksNeededFor16Pixels=2+.25+.25) / 16.0) && + ((uint16_t)((1/(H_scale_ratio)) * (1<<0xc) + 0.5)<=0x3000) && + ((uint16_t)((1/(H_scale_ratio*4*4)) * (1<<0xc) + 0.5)<=0x2000)) + { + *P1GroupSize = 4; + *val_OV0_P1_H_INC = (uint16_t)((1/(H_scale_ratio*2)) * (1<<0xc) + 0.5); + *val_OV0_P1_H_STEP_BY = 2; + *val_OV0_P23_H_INC = (uint16_t)((1/(H_scale_ratio*4*4)) * (1<<0xc) + 0.5); + *val_OV0_P23_H_STEP_BY = 3; + *P1StepSize = 2; + *P23StepSize = 4; + } + /* We step the Y, U, and V by four. */ + else if ((H_scale_ratio>=(ClocksNeededFor16Pixels=1+.25+.25) / 16.0) && + ((uint16_t)((1/(H_scale_ratio*4)) * (1<<0xc) + 0.5)<=0x3000) && + ((uint16_t)((1/(H_scale_ratio*4*4)) * (1<<0xc) + 0.5)<=0x2000)) + { + *P1GroupSize = 4; + *val_OV0_P1_H_INC = (uint16_t)((1/(H_scale_ratio*4)) * (1<<0xc) + 0.5); + *val_OV0_P1_H_STEP_BY = 3; + *val_OV0_P23_H_INC = (uint16_t)((1/(H_scale_ratio*4*4)) * (1<<0xc) + 0.5); + *val_OV0_P23_H_STEP_BY = 3; + *P1StepSize = 4; + *P23StepSize = 4; + } + /* We would like to step the Y by four and the U and V by eight, but we can't mix step by 3 and step by 4 for packed modes */ + + /* We step the Y, U, and V by eight. */ + else if ((H_scale_ratio>=(ClocksNeededFor16Pixels=.5+.125+.125) / 16.0) && + ((uint16_t)((1/(H_scale_ratio*8)) * (1<<0xc) + 0.5)<=0x3000) && + ((uint16_t)((1/(H_scale_ratio*4*8)) * (1<<0xc) + 0.5)<=0x2000)) + { + *P1GroupSize = 4; + *val_OV0_P1_H_INC = (uint16_t)((1/(H_scale_ratio*8)) * (1<<0xc) + 0.5); + *val_OV0_P1_H_STEP_BY = 4; + *val_OV0_P23_H_INC = (uint16_t)((1/(H_scale_ratio*4*8)) * (1<<0xc) + 0.5); + *val_OV0_P23_H_STEP_BY = 4; + *P1StepSize = 8; + *P23StepSize = 8; + } + /* We step the Y by eight and the U and V by sixteen. */ + else if ((H_scale_ratio>=(ClocksNeededFor16Pixels=.5+.0625+.0625) / 16.0) && + ((uint16_t)((1/(H_scale_ratio*8)) * (1<<0xc) + 0.5)<=0x3000) && + ((uint16_t)((1/(H_scale_ratio*4*16)) * (1<<0xc) + 0.5)<=0x2000)) + { + *P1GroupSize = 4; + *val_OV0_P1_H_INC = (uint16_t)((1/(H_scale_ratio*8)) * (1<<0xc) + 0.5); + *val_OV0_P1_H_STEP_BY = 4; + *val_OV0_P23_H_INC = (uint16_t)((1/(H_scale_ratio*4*16)) * (1<<0xc) + 0.5); + *val_OV0_P23_H_STEP_BY = 5; + *P1StepSize = 8; + *P23StepSize = 16; + } + /* We step the Y, U, and V by sixteen. */ + else if ((H_scale_ratio>=(ClocksNeededFor16Pixels=.25+.0625+.0625) / 16.0) && + ((uint16_t)((1/(H_scale_ratio*16)) * (1<<0xc) + 0.5)<=0x3000) && + ((uint16_t)((1/(H_scale_ratio*4*16)) * (1<<0xc) + 0.5)<=0x2000)) + { + *P1GroupSize = 4; + *val_OV0_P1_H_INC = (uint16_t)((1/(H_scale_ratio*16)) * (1<<0xc) + 0.5); + *val_OV0_P1_H_STEP_BY = 5; + *val_OV0_P23_H_INC = (uint16_t)((1/(H_scale_ratio*4*16)) * (1<<0xc) + 0.5); + *val_OV0_P23_H_STEP_BY = 5; + *P1StepSize = 16; + *P23StepSize = 16; + } + else + { + H_scale_ratio=(ClocksNeededFor16Pixels=.25+.0625+.0625) / 16; + *P1GroupSize = 4; + *val_OV0_P1_H_INC = (uint16_t)((1/(H_scale_ratio*16)) * (1<<0xc) + 0.5); + *val_OV0_P1_H_STEP_BY = 5; + *val_OV0_P23_H_INC = (uint16_t)((1/(H_scale_ratio*4*16)) * (1<<0xc) + 0.5); + *val_OV0_P23_H_STEP_BY = 5; + *P1StepSize = 16; + *P23StepSize = 16; + } + break; + case 10: + case 11: + case 12: + case 13: + case 14: /* YUV12, VYUY422, YUYV422, YOverPkCRCB12, YWovenWithPkCRCB12 */ + /* We scale the Y, U, and V with the four tap filters */ + /* four tap on both (unless Y is too wide) */ + if ((H_scale_ratio>=(ClocksNeededFor16Pixels=8+4+4) / 16.0) && + !DisallowFourTapVertFiltering && !DisallowFourTapUVVertFiltering) + { /*0.75 */ + *P1GroupSize = 2; + *val_OV0_P1_H_INC = (uint16_t)((1/(H_scale_ratio)) * (1<<0xc) + 0.5); + *val_OV0_P1_H_STEP_BY = 0; + *val_OV0_P23_H_INC = (uint16_t)((1/(H_scale_ratio*2)) * (1<<0xc) + 0.5); + *val_OV0_P23_H_STEP_BY = 0; + *P1StepSize = 1; + *P23StepSize = 1; + } + /* two tap on Y (because it is too big for four tap), four tap on UV */ + else if ((H_scale_ratio>=(ClocksNeededFor16Pixels=4+4+4) / 16.0) && + DisallowFourTapVertFiltering && !DisallowFourTapUVVertFiltering) + { /*0.75 */ + *P1GroupSize = 4; + *val_OV0_P1_H_INC = (uint16_t)((1/(H_scale_ratio)) * (1<<0xc) + 0.5); + *val_OV0_P1_H_STEP_BY = 1; + *val_OV0_P23_H_INC = (uint16_t)((1/(H_scale_ratio*2)) * (1<<0xc) + 0.5); + *val_OV0_P23_H_STEP_BY = 0; + *P1StepSize = 1; + *P23StepSize = 1; + } + /* We scale the Y with the four tap filters, but UV's are generated + with dual two tap configuration. */ + else if ((H_scale_ratio>=(ClocksNeededFor16Pixels=8+2+2) / 16.0) && + !DisallowFourTapVertFiltering) + { /*0.625 */ + *P1GroupSize = 2; + *val_OV0_P1_H_INC = (uint16_t)((1/(H_scale_ratio)) * (1<<0xc) + 0.5); + *val_OV0_P1_H_STEP_BY = 0; + *val_OV0_P23_H_INC = (uint16_t)((1/(H_scale_ratio*2)) * (1<<0xc) + 0.5); + *val_OV0_P23_H_STEP_BY = 1; + *P1StepSize = 1; + *P23StepSize = 1; + } + /* We scale the Y, U, and V with the two tap filters */ + else if (H_scale_ratio>=(ClocksNeededFor16Pixels=4+2+2) / 16.0) + { /*0.375 */ + *P1GroupSize = 4; + *val_OV0_P1_H_INC = (uint16_t)((1/(H_scale_ratio)) * (1<<0xc) + 0.5); + *val_OV0_P1_H_STEP_BY = 1; + *val_OV0_P23_H_INC = (uint16_t)((1/(H_scale_ratio*2)) * (1<<0xc) + 0.5); + *val_OV0_P23_H_STEP_BY = 1; + *P1StepSize = 1; + *P23StepSize = 1; + } + /* We scale step the U and V by two to allow more bandwidth for + fetching Y's, thus we won't drop Y's yet. */ + else if (H_scale_ratio>=(ClocksNeededFor16Pixels=4+1+1) / 16.0) + { /*0.312 */ + *P1GroupSize = 4; + *val_OV0_P1_H_INC = (uint16_t)((1/(H_scale_ratio)) * (1<<0xc) + 0.5); + *val_OV0_P1_H_STEP_BY = 1; + *val_OV0_P23_H_INC = (uint16_t)((1/(H_scale_ratio*2*2)) * (1<<0xc) + 0.5); + *val_OV0_P23_H_STEP_BY = 2; + *P1StepSize = 1; + *P23StepSize = 2; + } + /* We step the Y, U, and V by two. */ + else if (H_scale_ratio>=(ClocksNeededFor16Pixels=2+1+1) / 16.0) + { + *P1GroupSize = 4; + *val_OV0_P1_H_INC = (uint16_t)((1/(H_scale_ratio*2)) * (1<<0xc) + 0.5); + *val_OV0_P1_H_STEP_BY = 2; + *val_OV0_P23_H_INC = (uint16_t)((1/(H_scale_ratio*2*2)) * (1<<0xc) + 0.5); + *val_OV0_P23_H_STEP_BY = 2; + *P1StepSize = 2; + *P23StepSize = 2; + } + /* We step the Y by two and the U and V by four. */ + else if (H_scale_ratio>=(ClocksNeededFor16Pixels=2+.5+.5) / 16.0) + { + *P1GroupSize = 4; + *val_OV0_P1_H_INC = (uint16_t)((1/(H_scale_ratio*2)) * (1<<0xc) + 0.5); + *val_OV0_P1_H_STEP_BY = 2; + *val_OV0_P23_H_INC = (uint16_t)((1/(H_scale_ratio*2*4)) * (1<<0xc) + 0.5); + *val_OV0_P23_H_STEP_BY = 3; + *P1StepSize = 2; + *P23StepSize = 4; + } + /* We step the Y, U, and V by four. */ + else if (H_scale_ratio>=(ClocksNeededFor16Pixels=1+.5+.5) / 16.0) + { + *P1GroupSize = 4; + *val_OV0_P1_H_INC = (uint16_t)((1/(H_scale_ratio*4)) * (1<<0xc) + 0.5); + *val_OV0_P1_H_STEP_BY = 3; + *val_OV0_P23_H_INC = (uint16_t)((1/(H_scale_ratio*2*4)) * (1<<0xc) + 0.5); + *val_OV0_P23_H_STEP_BY = 3; + *P1StepSize = 4; + *P23StepSize = 4; + } + /* We step the Y by four and the U and V by eight. */ + else if ((H_scale_ratio>=(ClocksNeededFor16Pixels=1+.25+.25) / 16.0) && + (fieldvalue_OV0_SURFACE_FORMAT==10)) + { + *P1GroupSize = 4; + /* Can't mix step by 3 and step by 4 for packed modes */ + *val_OV0_P1_H_INC = (uint16_t)((1/(H_scale_ratio*4)) * (1<<0xc) + 0.5); + *val_OV0_P1_H_STEP_BY = 3; + *val_OV0_P23_H_INC = (uint16_t)((1/(H_scale_ratio*2*8)) * (1<<0xc) + 0.5); + *val_OV0_P23_H_STEP_BY = 4; + *P1StepSize = 4; + *P23StepSize = 8; + } + /* We step the Y, U, and V by eight. */ + else if (H_scale_ratio>=(ClocksNeededFor16Pixels=.5+.25+.25) / 16.0) + { + *P1GroupSize = 4; + *val_OV0_P1_H_INC = (uint16_t)((1/(H_scale_ratio*8)) * (1<<0xc) + 0.5); + *val_OV0_P1_H_STEP_BY = 4; + *val_OV0_P23_H_INC = (uint16_t)((1/(H_scale_ratio*2*8)) * (1<<0xc) + 0.5); + *val_OV0_P23_H_STEP_BY = 4; + *P1StepSize = 8; + *P23StepSize = 8; + } + /* We step the Y by eight and the U and V by sixteen. */ + else if ((H_scale_ratio>=(ClocksNeededFor16Pixels=.5+.125+.125) / 16.0) && (fieldvalue_OV0_SURFACE_FORMAT==10)) + { + *P1GroupSize = 4; + /* Step by 5 not supported for packed modes */ + *val_OV0_P1_H_INC = (uint16_t)((1/(H_scale_ratio*8)) * (1<<0xc) + 0.5); + *val_OV0_P1_H_STEP_BY = 4; + *val_OV0_P23_H_INC = (uint16_t)((1/(H_scale_ratio*2*16)) * (1<<0xc) + 0.5); + *val_OV0_P23_H_STEP_BY = 5; + *P1StepSize = 8; + *P23StepSize = 16; + } + /* We step the Y, U, and V by sixteen. */ + else if ((H_scale_ratio>=(ClocksNeededFor16Pixels=.25+.125+.125) / 16.0) && + (fieldvalue_OV0_SURFACE_FORMAT==10)) + { + *P1GroupSize = 4; + /* Step by 5 not supported for packed modes */ + *val_OV0_P1_H_INC = (uint16_t)((1/(H_scale_ratio*16)) * (1<<0xc) + 0.5); + *val_OV0_P1_H_STEP_BY = 5; + *val_OV0_P23_H_INC = (uint16_t)((1/(H_scale_ratio*2*16)) * (1<<0xc) + 0.5); + *val_OV0_P23_H_STEP_BY = 5; + *P1StepSize = 16; + *P23StepSize = 16; + } + else + { + if (fieldvalue_OV0_SURFACE_FORMAT==10) + { + H_scale_ratio=(ClocksNeededFor16Pixels=.25+.125+.125) / 16; + *P1GroupSize = 4; + *val_OV0_P1_H_INC = (uint16_t)((1/(H_scale_ratio*16)) * (1<<0xc) + 0.5); + *val_OV0_P1_H_STEP_BY = 5; + *val_OV0_P23_H_INC = (uint16_t)((1/(H_scale_ratio*2*16)) * (1<<0xc) + 0.5); + *val_OV0_P23_H_STEP_BY = 5; + *P1StepSize = 16; + *P23StepSize = 16; + } + else + { + H_scale_ratio=(ClocksNeededFor16Pixels=.5+.25+.25) / 16; + *P1GroupSize = 4; + *val_OV0_P1_H_INC = (uint16_t)((1/(H_scale_ratio*8)) * (1<<0xc) + 0.5); + *val_OV0_P1_H_STEP_BY = 4; + *val_OV0_P23_H_INC = (uint16_t)((1/(H_scale_ratio*2*8)) * (1<<0xc) + 0.5); + *val_OV0_P23_H_STEP_BY = 4; + *P1StepSize = 8; + *P23StepSize = 8; + } + } + break; + default: break; + + } + besr.h_inc = (*(val_OV0_P1_H_INC)&0x3fff) | ((*(val_OV0_P23_H_INC)&0x3fff)<<16); + besr.step_by = (*(val_OV0_P1_H_STEP_BY)&0x7) | ((*(val_OV0_P23_H_STEP_BY)&0x7)<<8); +} + +/* ********************************************************* */ +/* ** Setup Black Bordering */ +/* ********************************************************* */ + +static void ComputeBorders( vidix_playback_t *config, int VertUVSubSample ) +{ + double tempBLANK_LINES_AT_TOP; + unsigned TopLine,BottomLine,SourceLinesUsed,TopUVLine,BottomUVLine,SourceUVLinesUsed; + uint32_t val_OV0_P1_ACTIVE_LINES_M1,val_OV0_P1_BLNK_LN_AT_TOP_M1; + uint32_t val_OV0_P23_ACTIVE_LINES_M1,val_OV0_P23_BLNK_LN_AT_TOP_M1; + + if (floor(config->src.y)<0) { + tempBLANK_LINES_AT_TOP = -floor(config->src.y); + TopLine = 0; + } + else { + tempBLANK_LINES_AT_TOP = 0; + TopLine = (int)floor(config->src.y); + } + /* Round rSrcBottom up and subtract one */ + if (ceil(config->src.y+config->src.h) > config->src.h) + { + BottomLine = config->src.h - 1; + } + else + { + BottomLine = (int)ceil(config->src.y+config->src.h) - 1; + } + + if (BottomLine >= TopLine) + { + SourceLinesUsed = BottomLine - TopLine + 1; + } + else + { + /*CYCACC_ASSERT(0, "SourceLinesUsed less than or equal to zero.") */ + SourceLinesUsed = 1; + } + + { + int SourceHeightInPixels; + SourceHeightInPixels = BottomLine - TopLine + 1; + } + + val_OV0_P1_ACTIVE_LINES_M1 = SourceLinesUsed - 1; + val_OV0_P1_BLNK_LN_AT_TOP_M1 = ((int)tempBLANK_LINES_AT_TOP-1) & 0xfff; + + TopUVLine = ((int)(config->src.y/VertUVSubSample) < 0) ? 0: (int)(config->src.y/VertUVSubSample); /* Round rSrcTop down */ + BottomUVLine = (ceil(((config->src.y+config->src.h)/VertUVSubSample)) > (config->src.h/VertUVSubSample)) + ? (config->src.h/VertUVSubSample)-1 : (u_int)ceil(((config->src.y+config->src.h)/VertUVSubSample))-1; + + if (BottomUVLine >= TopUVLine) + { + SourceUVLinesUsed = BottomUVLine - TopUVLine + 1; + } + else + { + /*CYCACC_ASSERT(0, "SourceUVLinesUsed less than or equal to zero.") */ + SourceUVLinesUsed = 1; + } + val_OV0_P23_ACTIVE_LINES_M1 = SourceUVLinesUsed - 1; + val_OV0_P23_BLNK_LN_AT_TOP_M1 = ((int)(tempBLANK_LINES_AT_TOP/VertUVSubSample)-1) & 0x7ff; + besr.p1_blank_lines_at_top = (val_OV0_P1_BLNK_LN_AT_TOP_M1 & 0xfff) | + ((val_OV0_P1_ACTIVE_LINES_M1 & 0xfff) << 16); + besr.p23_blank_lines_at_top = (val_OV0_P23_BLNK_LN_AT_TOP_M1 & 0x7ff) | + ((val_OV0_P23_ACTIVE_LINES_M1 & 0x7ff) << 16); +} + + +static void ComputeXStartEnd( + int is_400, + uint32_t LeftPixel,uint32_t LeftUVPixel, + uint32_t MemWordsInBytes,uint32_t BytesPerPixel, + uint32_t SourceWidthInPixels, uint32_t P1StepSize, + uint32_t BytesPerUVPixel,uint32_t SourceUVWidthInPixels, + uint32_t P23StepSize, uint32_t *p1_x_start, uint32_t *p2_x_start ) +{ + uint32_t val_OV0_P1_X_START,val_OV0_P2_X_START,val_OV0_P3_X_START; + uint32_t val_OV0_P1_X_END,val_OV0_P2_X_END,val_OV0_P3_X_END; + /* ToDo_Active: At the moment we are not using iOV0_VID_BUF?_START_PIX, but instead // are using iOV0_P?_X_START and iOV0_P?_X_END. We should use "start pix" and // "width" to derive the start and end. */ + + val_OV0_P1_X_START = (int)LeftPixel % (MemWordsInBytes/BytesPerPixel); + val_OV0_P1_X_END = (int)((val_OV0_P1_X_START + SourceWidthInPixels - 1) / P1StepSize) * P1StepSize; + + val_OV0_P2_X_START = val_OV0_P2_X_END = 0; + switch (besr.surf_id) + { + case 9: + case 10: + case 13: + case 14: /* ToDo_Active: The driver must insure that the initial value is */ + /* a multiple of a power of two when decimating */ + val_OV0_P2_X_START = (int)LeftUVPixel % + (MemWordsInBytes/BytesPerUVPixel); + val_OV0_P2_X_END = (int)((val_OV0_P2_X_START + + SourceUVWidthInPixels - 1) / P23StepSize) * P23StepSize; + break; + case 11: + case 12: val_OV0_P2_X_START = (int)LeftUVPixel % (MemWordsInBytes/(BytesPerPixel*2)); + val_OV0_P2_X_END = (int)((val_OV0_P2_X_START + SourceUVWidthInPixels - 1) / P23StepSize) * P23StepSize; + break; + case 3: + case 4: val_OV0_P2_X_START = val_OV0_P1_X_START; + /* This value is needed only to allow proper setting of */ + /* val_OV0_PRESHIFT_P23_TO */ + /* val_OV0_P2_X_END = 0; */ + break; + case 6: val_OV0_P2_X_START = (int)LeftPixel % (MemWordsInBytes/BytesPerPixel); + val_OV0_P2_X_END = (int)((val_OV0_P1_X_START + SourceWidthInPixels - 1) / P23StepSize) * P23StepSize; + break; + default: /* insert debug statement here. */ + RADEON_ASSERT("unknown fourcc\n"); + break; + } + val_OV0_P3_X_START = val_OV0_P2_X_START; + val_OV0_P3_X_END = val_OV0_P2_X_END; + + besr.p1_x_start_end = (val_OV0_P1_X_END&0x7ff) | ((val_OV0_P1_X_START&0x7ff)<<16); + besr.p2_x_start_end = (val_OV0_P2_X_END&0x7ff) | ((val_OV0_P2_X_START&0x7ff)<<16); + besr.p3_x_start_end = (val_OV0_P3_X_END&0x7ff) | ((val_OV0_P3_X_START&0x7ff)<<16); + if(is_400) + { + besr.p2_x_start_end = 0; + besr.p3_x_start_end = 0; + } + *p1_x_start = val_OV0_P1_X_START; + *p2_x_start = val_OV0_P2_X_START; +} + +static void ComputeAccumInit( + uint32_t val_OV0_P1_X_START,uint32_t val_OV0_P2_X_START, + uint32_t val_OV0_P1_H_INC,uint32_t val_OV0_P23_H_INC, + uint32_t val_OV0_P1_H_STEP_BY,uint32_t val_OV0_P23_H_STEP_BY, + uint32_t CRT_V_INC, + uint32_t P1GroupSize, uint32_t P23GroupSize, + uint32_t val_OV0_P1_MAX_LN_IN_PER_LN_OUT, + uint32_t val_OV0_P23_MAX_LN_IN_PER_LN_OUT) +{ + uint32_t val_OV0_P1_H_ACCUM_INIT,val_OV0_PRESHIFT_P1_TO; + uint32_t val_OV0_P23_H_ACCUM_INIT,val_OV0_PRESHIFT_P23_TO; + uint32_t val_OV0_P1_V_ACCUM_INIT,val_OV0_P23_V_ACCUM_INIT; + /* 2.5 puts the kernal 50% of the way between the source pixel that is off screen */ + /* and the first on-screen source pixel. "(float)valOV0_P?_H_INC / (1<<0xc)" is */ + /* the distance (in source pixel coordinates) to the center of the first */ + /* destination pixel. Need to add additional pixels depending on how many pixels */ + /* are fetched at a time and how many pixels in a set are masked. */ + /* P23 values are always fetched in groups of two or four. If the start */ + /* pixel does not fall on the boundary, then we need to shift preshift for */ + /* some additional pixels */ + + { + double ExtraHalfPixel; + double tempAdditionalShift; + double tempP1HStartPoint; + double tempP23HStartPoint; + double tempP1Init; + double tempP23Init; + + if (besr.horz_pick_nearest) ExtraHalfPixel = 0.5; + else ExtraHalfPixel = 0.0; + tempAdditionalShift = val_OV0_P1_X_START % P1GroupSize + ExtraHalfPixel; + tempP1HStartPoint = tempAdditionalShift + 2.5 + ((float)val_OV0_P1_H_INC / (1<<0xd)); + tempP1Init = (double)((int)(tempP1HStartPoint * (1<<0x5) + 0.5)) / (1<<0x5); + + /* P23 values are always fetched in pairs. If the start pixel is odd, then we */ + /* need to shift an additional pixel */ + /* Note that if the pitch is a multiple of two, and if we store fields using */ + /* the traditional planer format where the V plane and the U plane share the */ + /* same pitch, then OverlayRegFields->val_OV0_P2_X_START % P23Group */ + /* OverlayRegFields->val_OV0_P3_X_START % P23GroupSize. Either way */ + /* it is a requirement that the U and V start on the same polarity byte */ + /* (even or odd). */ + tempAdditionalShift = val_OV0_P2_X_START % P23GroupSize + ExtraHalfPixel; + tempP23HStartPoint = tempAdditionalShift + 2.5 + ((float)val_OV0_P23_H_INC / (1<<0xd)); + tempP23Init = (double)((int)(tempP23HStartPoint * (1<<0x5) + 0.5)) / (1 << 0x5); + val_OV0_P1_H_ACCUM_INIT = (int)((tempP1Init - (int)tempP1Init) * (1<<0x5)); + val_OV0_PRESHIFT_P1_TO = (int)tempP1Init; + val_OV0_P23_H_ACCUM_INIT = (int)((tempP23Init - (int)tempP23Init) * (1<<0x5)); + val_OV0_PRESHIFT_P23_TO = (int)tempP23Init; + } + + /* ************************************************************** */ + /* ** Calculate values for initializing the vertical accumulators */ + /* ************************************************************** */ + + { + double ExtraHalfLine; + double ExtraFullLine; + double tempP1VStartPoint; + double tempP23VStartPoint; + + if (besr.vert_pick_nearest) ExtraHalfLine = 0.5; + else ExtraHalfLine = 0.0; + + if (val_OV0_P1_H_STEP_BY==0)ExtraFullLine = 1.0; + else ExtraFullLine = 0.0; + + tempP1VStartPoint = 1.5 + ExtraFullLine + ExtraHalfLine + ((float)CRT_V_INC / (1<<0xd)); + if (tempP1VStartPoint>2.5 + 2*ExtraFullLine) + { + tempP1VStartPoint = 2.5 + 2*ExtraFullLine; + } + val_OV0_P1_V_ACCUM_INIT = (int)(tempP1VStartPoint * (1<<0x5) + 0.5); + + if (val_OV0_P23_H_STEP_BY==0)ExtraFullLine = 1.0; + else ExtraFullLine = 0.0; + + switch (besr.surf_id) + { + case 10: + case 13: + case 14: tempP23VStartPoint = 1.5 + ExtraFullLine + ExtraHalfLine + + ((float)CRT_V_INC / (1<<0xe)); + break; + case 9: tempP23VStartPoint = 1.5 + ExtraFullLine + ExtraHalfLine + + ((float)CRT_V_INC / (1<<0xf)); + break; + case 3: + case 4: + case 6: + case 11: + case 12: tempP23VStartPoint = 0; + break; + default: tempP23VStartPoint = 0xFFFF;/* insert debug statement here */ + break; + } + + if (tempP23VStartPoint>2.5 + 2*ExtraFullLine) + { + tempP23VStartPoint = 2.5 + 2*ExtraFullLine; + } + + val_OV0_P23_V_ACCUM_INIT = (int)(tempP23VStartPoint * (1<<0x5) + 0.5); + } + besr.p1_h_accum_init = ((val_OV0_P1_H_ACCUM_INIT&0x1f)<<15) |((val_OV0_PRESHIFT_P1_TO&0xf)<<28); + besr.p1_v_accum_init = (val_OV0_P1_MAX_LN_IN_PER_LN_OUT&0x3) |((val_OV0_P1_V_ACCUM_INIT&0x7ff)<<15); + besr.p23_h_accum_init= ((val_OV0_P23_H_ACCUM_INIT&0x1f)<<15) |((val_OV0_PRESHIFT_P23_TO&0xf)<<28); + besr.p23_v_accum_init= (val_OV0_P23_MAX_LN_IN_PER_LN_OUT&0x3)|((val_OV0_P23_V_ACCUM_INIT&0x3ff)<<15); +} + +typedef struct RangeAndCoefSet { + double Range; + signed char CoefSet[5][4]; +} RANGEANDCOEFSET; + +/* Filter Setup Routine */ +static void FilterSetup ( uint32_t val_OV0_P1_H_INC ) +{ + static RANGEANDCOEFSET ArrayOfSets[] = { + {0.25, {{ 7, 16, 9, 0}, { 7, 16, 9, 0}, { 5, 15, 11, 1}, { 4, 15, 12, 1}, { 3, 13, 13, 3}, }}, + {0.26, {{ 7, 16, 9, 0}, { 7, 16, 9, 0}, { 5, 15, 11, 1}, { 4, 15, 12, 1}, { 3, 13, 13, 3}, }}, + {0.27, {{ 7, 16, 9, 0}, { 7, 16, 9, 0}, { 5, 15, 11, 1}, { 4, 15, 12, 1}, { 3, 13, 13, 3}, }}, + {0.28, {{ 7, 16, 9, 0}, { 7, 16, 9, 0}, { 5, 15, 11, 1}, { 4, 15, 12, 1}, { 3, 13, 13, 3}, }}, + {0.29, {{ 7, 16, 9, 0}, { 7, 16, 9, 0}, { 5, 15, 11, 1}, { 4, 15, 12, 1}, { 3, 13, 13, 3}, }}, + {0.30, {{ 7, 16, 9, 0}, { 7, 16, 9, 0}, { 5, 15, 11, 1}, { 4, 15, 12, 1}, { 3, 13, 13, 3}, }}, + {0.31, {{ 7, 16, 9, 0}, { 7, 16, 9, 0}, { 5, 15, 11, 1}, { 4, 15, 12, 1}, { 3, 13, 13, 3}, }}, + {0.32, {{ 7, 16, 9, 0}, { 7, 16, 9, 0}, { 5, 15, 11, 1}, { 4, 15, 12, 1}, { 3, 13, 13, 3}, }}, + {0.33, {{ 7, 16, 9, 0}, { 7, 16, 9, 0}, { 5, 15, 11, 1}, { 4, 15, 12, 1}, { 3, 13, 13, 3}, }}, + {0.34, {{ 7, 16, 9, 0}, { 7, 16, 9, 0}, { 5, 15, 11, 1}, { 4, 15, 12, 1}, { 3, 13, 13, 3}, }}, + {0.35, {{ 7, 16, 9, 0}, { 7, 16, 9, 0}, { 5, 15, 11, 1}, { 4, 15, 12, 1}, { 3, 13, 13, 3}, }}, + {0.36, {{ 7, 16, 9, 0}, { 7, 16, 9, 0}, { 5, 15, 11, 1}, { 4, 15, 12, 1}, { 3, 13, 13, 3}, }}, + {0.37, {{ 7, 16, 9, 0}, { 7, 16, 9, 0}, { 5, 15, 11, 1}, { 4, 15, 12, 1}, { 3, 13, 13, 3}, }}, + {0.38, {{ 7, 16, 9, 0}, { 7, 16, 9, 0}, { 5, 15, 11, 1}, { 4, 15, 12, 1}, { 3, 13, 13, 3}, }}, + {0.39, {{ 7, 16, 9, 0}, { 7, 16, 9, 0}, { 5, 15, 11, 1}, { 4, 15, 12, 1}, { 3, 13, 13, 3}, }}, + {0.40, {{ 7, 16, 9, 0}, { 7, 16, 9, 0}, { 5, 15, 11, 1}, { 4, 15, 12, 1}, { 3, 13, 13, 3}, }}, + {0.41, {{ 7, 16, 9, 0}, { 7, 16, 9, 0}, { 5, 15, 11, 1}, { 4, 15, 12, 1}, { 3, 13, 13, 3}, }}, + {0.42, {{ 7, 16, 9, 0}, { 7, 16, 9, 0}, { 5, 15, 11, 1}, { 4, 15, 12, 1}, { 3, 13, 13, 3}, }}, + {0.43, {{ 7, 16, 9, 0}, { 7, 16, 9, 0}, { 5, 15, 11, 1}, { 4, 15, 12, 1}, { 3, 13, 13, 3}, }}, + {0.44, {{ 7, 16, 9, 0}, { 7, 16, 9, 0}, { 5, 15, 11, 1}, { 4, 15, 12, 1}, { 3, 13, 13, 3}, }}, + {0.45, {{ 7, 16, 9, 0}, { 7, 16, 9, 0}, { 5, 15, 11, 1}, { 4, 15, 12, 1}, { 3, 13, 13, 3}, }}, + {0.46, {{ 7, 16, 9, 0}, { 7, 16, 9, 0}, { 5, 15, 11, 1}, { 4, 15, 12, 1}, { 3, 13, 13, 3}, }}, + {0.47, {{ 7, 16, 9, 0}, { 7, 16, 9, 0}, { 5, 15, 11, 1}, { 4, 15, 12, 1}, { 3, 13, 13, 3}, }}, + {0.48, {{ 7, 16, 9, 0}, { 7, 16, 9, 0}, { 5, 15, 11, 1}, { 4, 15, 12, 1}, { 3, 13, 13, 3}, }}, + {0.49, {{ 7, 16, 9, 0}, { 7, 16, 9, 0}, { 5, 15, 11, 1}, { 4, 15, 12, 1}, { 3, 13, 13, 3}, }}, + {0.50, {{ 7, 16, 9, 0}, { 7, 16, 9, 0}, { 5, 15, 11, 1}, { 4, 15, 12, 1}, { 3, 13, 13, 3}, }}, + {0.51, {{ 7, 17, 8, 0}, { 6, 17, 9, 0}, { 5, 15, 11, 1}, { 4, 15, 12, 1}, { 2, 14, 14, 2}, }}, + {0.52, {{ 7, 17, 8, 0}, { 6, 17, 9, 0}, { 5, 16, 11, 0}, { 3, 15, 13, 1}, { 2, 14, 14, 2}, }}, + {0.53, {{ 7, 17, 8, 0}, { 6, 17, 9, 0}, { 5, 16, 11, 0}, { 3, 15, 13, 1}, { 2, 14, 14, 2}, }}, + {0.54, {{ 7, 17, 8, 0}, { 6, 17, 9, 0}, { 4, 17, 11, 0}, { 3, 15, 13, 1}, { 2, 14, 14, 2}, }}, + {0.55, {{ 7, 18, 7, 0}, { 6, 17, 9, 0}, { 4, 17, 11, 0}, { 3, 15, 13, 1}, { 1, 15, 15, 1}, }}, + {0.56, {{ 7, 18, 7, 0}, { 5, 18, 9, 0}, { 4, 17, 11, 0}, { 2, 17, 13, 0}, { 1, 15, 15, 1}, }}, + {0.57, {{ 7, 18, 7, 0}, { 5, 18, 9, 0}, { 4, 17, 11, 0}, { 2, 17, 13, 0}, { 1, 15, 15, 1}, }}, + {0.58, {{ 7, 18, 7, 0}, { 5, 18, 9, 0}, { 4, 17, 11, 0}, { 2, 17, 13, 0}, { 1, 15, 15, 1}, }}, + {0.59, {{ 7, 18, 7, 0}, { 5, 18, 9, 0}, { 4, 17, 11, 0}, { 2, 17, 13, 0}, { 1, 15, 15, 1}, }}, + {0.60, {{ 7, 18, 8, -1}, { 6, 17, 10, -1}, { 4, 17, 11, 0}, { 2, 17, 13, 0}, { 1, 15, 15, 1}, }}, + {0.61, {{ 7, 18, 8, -1}, { 6, 17, 10, -1}, { 4, 17, 11, 0}, { 2, 17, 13, 0}, { 1, 15, 15, 1}, }}, + {0.62, {{ 7, 18, 8, -1}, { 6, 17, 10, -1}, { 4, 17, 11, 0}, { 2, 17, 13, 0}, { 1, 15, 15, 1}, }}, + {0.63, {{ 7, 18, 8, -1}, { 6, 17, 10, -1}, { 4, 17, 11, 0}, { 2, 17, 13, 0}, { 1, 15, 15, 1}, }}, + {0.64, {{ 7, 18, 8, -1}, { 6, 17, 10, -1}, { 4, 17, 12, -1}, { 2, 17, 13, 0}, { 1, 15, 15, 1}, }}, + {0.65, {{ 7, 18, 8, -1}, { 6, 17, 10, -1}, { 4, 17, 12, -1}, { 2, 17, 13, 0}, { 0, 16, 16, 0}, }}, + {0.66, {{ 7, 18, 8, -1}, { 6, 18, 10, -2}, { 4, 17, 12, -1}, { 2, 17, 13, 0}, { 0, 16, 16, 0}, }}, + {0.67, {{ 7, 20, 7, -2}, { 5, 19, 10, -2}, { 3, 18, 12, -1}, { 2, 17, 13, 0}, { 0, 16, 16, 0}, }}, + {0.68, {{ 7, 20, 7, -2}, { 5, 19, 10, -2}, { 3, 19, 12, -2}, { 1, 18, 14, -1}, { 0, 16, 16, 0}, }}, + {0.69, {{ 7, 20, 7, -2}, { 5, 19, 10, -2}, { 3, 19, 12, -2}, { 1, 18, 14, -1}, { 0, 16, 16, 0}, }}, + {0.70, {{ 7, 20, 7, -2}, { 5, 20, 9, -2}, { 3, 19, 12, -2}, { 1, 18, 14, -1}, { 0, 16, 16, 0}, }}, + {0.71, {{ 7, 20, 7, -2}, { 5, 20, 9, -2}, { 3, 19, 12, -2}, { 1, 18, 14, -1}, { 0, 16, 16, 0}, }}, + {0.72, {{ 7, 20, 7, -2}, { 5, 20, 9, -2}, { 2, 20, 12, -2}, { 0, 19, 15, -2}, {-1, 17, 17, -1}, }}, + {0.73, {{ 7, 20, 7, -2}, { 4, 21, 9, -2}, { 2, 20, 12, -2}, { 0, 19, 15, -2}, {-1, 17, 17, -1}, }}, + {0.74, {{ 6, 22, 6, -2}, { 4, 21, 9, -2}, { 2, 20, 12, -2}, { 0, 19, 15, -2}, {-1, 17, 17, -1}, }}, + {0.75, {{ 6, 22, 6, -2}, { 4, 21, 9, -2}, { 1, 21, 12, -2}, { 0, 19, 15, -2}, {-1, 17, 17, -1}, }}, + {0.76, {{ 6, 22, 6, -2}, { 4, 21, 9, -2}, { 1, 21, 12, -2}, { 0, 19, 15, -2}, {-1, 17, 17, -1}, }}, + {0.77, {{ 6, 22, 6, -2}, { 3, 22, 9, -2}, { 1, 22, 12, -3}, { 0, 19, 15, -2}, {-2, 18, 18, -2}, }}, + {0.78, {{ 6, 21, 6, -1}, { 3, 22, 9, -2}, { 1, 22, 12, -3}, { 0, 19, 15, -2}, {-2, 18, 18, -2}, }}, + {0.79, {{ 5, 23, 5, -1}, { 3, 22, 9, -2}, { 0, 23, 12, -3}, {-1, 21, 15, -3}, {-2, 18, 18, -2}, }}, + {0.80, {{ 5, 23, 5, -1}, { 3, 23, 8, -2}, { 0, 23, 12, -3}, {-1, 21, 15, -3}, {-2, 18, 18, -2}, }}, + {0.81, {{ 5, 23, 5, -1}, { 2, 24, 8, -2}, { 0, 23, 12, -3}, {-1, 21, 15, -3}, {-2, 18, 18, -2}, }}, + {0.82, {{ 5, 23, 5, -1}, { 2, 24, 8, -2}, { 0, 23, 12, -3}, {-1, 21, 15, -3}, {-3, 19, 19, -3}, }}, + {0.83, {{ 5, 23, 5, -1}, { 2, 24, 8, -2}, { 0, 23, 11, -2}, {-2, 22, 15, -3}, {-3, 19, 19, -3}, }}, + {0.84, {{ 4, 25, 4, -1}, { 1, 25, 8, -2}, { 0, 23, 11, -2}, {-2, 22, 15, -3}, {-3, 19, 19, -3}, }}, + {0.85, {{ 4, 25, 4, -1}, { 1, 25, 8, -2}, { 0, 23, 11, -2}, {-2, 22, 15, -3}, {-3, 19, 19, -3}, }}, + {0.86, {{ 4, 24, 4, 0}, { 1, 25, 7, -1}, {-1, 24, 11, -2}, {-2, 22, 15, -3}, {-3, 19, 19, -3}, }}, + {0.87, {{ 4, 24, 4, 0}, { 1, 25, 7, -1}, {-1, 24, 11, -2}, {-2, 22, 15, -3}, {-3, 19, 19, -3}, }}, + {0.88, {{ 3, 26, 3, 0}, { 0, 26, 7, -1}, {-1, 24, 11, -2}, {-3, 23, 15, -3}, {-3, 19, 19, -3}, }}, + {0.89, {{ 3, 26, 3, 0}, { 0, 26, 7, -1}, {-1, 24, 11, -2}, {-3, 23, 15, -3}, {-3, 19, 19, -3}, }}, + {0.90, {{ 3, 26, 3, 0}, { 0, 26, 7, -1}, {-2, 25, 11, -2}, {-3, 23, 15, -3}, {-3, 19, 19, -3}, }}, + {0.91, {{ 3, 26, 3, 0}, { 0, 27, 6, -1}, {-2, 25, 11, -2}, {-3, 23, 15, -3}, {-3, 19, 19, -3}, }}, + {0.92, {{ 2, 28, 2, 0}, { 0, 27, 6, -1}, {-2, 25, 11, -2}, {-3, 23, 15, -3}, {-3, 19, 19, -3}, }}, + {0.93, {{ 2, 28, 2, 0}, { 0, 26, 6, 0}, {-2, 25, 10, -1}, {-3, 23, 15, -3}, {-3, 19, 19, -3}, }}, + {0.94, {{ 2, 28, 2, 0}, { 0, 26, 6, 0}, {-2, 25, 10, -1}, {-3, 23, 15, -3}, {-3, 19, 19, -3}, }}, + {0.95, {{ 1, 30, 1, 0}, {-1, 28, 5, 0}, {-3, 26, 10, -1}, {-3, 23, 14, -2}, {-3, 19, 19, -3}, }}, + {0.96, {{ 1, 30, 1, 0}, {-1, 28, 5, 0}, {-3, 26, 10, -1}, {-3, 23, 14, -2}, {-3, 19, 19, -3}, }}, + {0.97, {{ 1, 30, 1, 0}, {-1, 28, 5, 0}, {-3, 26, 10, -1}, {-3, 23, 14, -2}, {-3, 19, 19, -3}, }}, + {0.98, {{ 1, 30, 1, 0}, {-2, 29, 5, 0}, {-3, 27, 9, -1}, {-3, 23, 14, -2}, {-3, 19, 19, -3}, }}, + {0.99, {{ 0, 32, 0, 0}, {-2, 29, 5, 0}, {-3, 27, 9, -1}, {-4, 24, 14, -2}, {-3, 19, 19, -3}, }}, + {1.00, {{ 0, 32, 0, 0}, {-2, 29, 5, 0}, {-3, 27, 9, -1}, {-4, 24, 14, -2}, {-3, 19, 19, -3}, }} + }; + + double DSR; + + unsigned ArrayElement; + + DSR = (double)(1<<0xc)/val_OV0_P1_H_INC; + if (DSR<.25) DSR=.25; + if (DSR>1) DSR=1; + + ArrayElement = (int)((DSR-0.25) * 100); + besr.four_tap_coeff[0] = (ArrayOfSets[ArrayElement].CoefSet[0][0] & 0xf) | + ((ArrayOfSets[ArrayElement].CoefSet[0][1] & 0x7f)<<8) | + ((ArrayOfSets[ArrayElement].CoefSet[0][2] & 0x7f)<<16) | + ((ArrayOfSets[ArrayElement].CoefSet[0][3] & 0xf)<<24); + besr.four_tap_coeff[1] = (ArrayOfSets[ArrayElement].CoefSet[1][0] & 0xf) | + ((ArrayOfSets[ArrayElement].CoefSet[1][1] & 0x7f)<<8) | + ((ArrayOfSets[ArrayElement].CoefSet[1][2] & 0x7f)<<16) | + ((ArrayOfSets[ArrayElement].CoefSet[1][3] & 0xf)<<24); + besr.four_tap_coeff[2] = (ArrayOfSets[ArrayElement].CoefSet[2][0] & 0xf) | + ((ArrayOfSets[ArrayElement].CoefSet[2][1] & 0x7f)<<8) | + ((ArrayOfSets[ArrayElement].CoefSet[2][2] & 0x7f)<<16) | + ((ArrayOfSets[ArrayElement].CoefSet[2][3] & 0xf)<<24); + besr.four_tap_coeff[3] = (ArrayOfSets[ArrayElement].CoefSet[3][0] & 0xf) | + ((ArrayOfSets[ArrayElement].CoefSet[3][1] & 0x7f)<<8) | + ((ArrayOfSets[ArrayElement].CoefSet[3][2] & 0x7f)<<16) | + ((ArrayOfSets[ArrayElement].CoefSet[3][3] & 0xf)<<24); + besr.four_tap_coeff[4] = (ArrayOfSets[ArrayElement].CoefSet[4][0] & 0xf) | + ((ArrayOfSets[ArrayElement].CoefSet[4][1] & 0x7f)<<8) | + ((ArrayOfSets[ArrayElement].CoefSet[4][2] & 0x7f)<<16) | + ((ArrayOfSets[ArrayElement].CoefSet[4][3] & 0xf)<<24); +/* + For more details, refer to Microsoft's draft of PC99. +*/ +} + +/* The minimal value of horizontal scale ratio when hard coded coefficients + are suitable for the best quality. */ +/* FIXME: Should it be 0.9 for Rage128 ??? */ +const double MinHScaleHard=0.75; + +static int radeon_vid_init_video( vidix_playback_t *config ) +{ + double V_scale_ratio; + uint32_t i,src_w,src_h,dest_w,dest_h,pitch,left,leftUV,top,h_inc; + uint32_t val_OV0_P1_H_INC,val_OV0_P1_H_STEP_BY,val_OV0_P23_H_INC,val_OV0_P23_H_STEP_BY; + uint32_t val_OV0_P1_X_START,val_OV0_P2_X_START; + uint32_t val_OV0_P1_MAX_LN_IN_PER_LN_OUT,val_OV0_P23_MAX_LN_IN_PER_LN_OUT; + uint32_t CRT_V_INC; + uint32_t BytesPerOctWord,LogMemWordsInBytes,MemWordsInBytes,LogTileWidthInMemWords; + uint32_t TileWidthInMemWords,TileWidthInBytes,LogTileHeight,TileHeight; + uint32_t PageSizeInBytes,OV0LB_Rows; + uint32_t SourceWidthInMemWords,SourceUVWidthInMemWords; + uint32_t SourceWidthInPixels,SourceUVWidthInPixels; + uint32_t RightPixel,RightUVPixel,LeftPixel,LeftUVPixel; + int is_400,is_410,is_420,best_pitch,mpitch; + int horz_repl_factor,interlace_factor; + int BytesPerPixel,BytesPerUVPixel,HorzUVSubSample,VertUVSubSample; + int DisallowFourTapVertFiltering,DisallowFourTapUVVertFiltering; + + radeon_vid_stop_video(); + left = config->src.x << 16; + top = config->src.y << 16; + src_h = config->src.h; + src_w = config->src.w; + is_400 = is_410 = is_420 = 0; + if(config->fourcc == IMGFMT_YV12 || + config->fourcc == IMGFMT_I420 || + config->fourcc == IMGFMT_IYUV) is_420 = 1; + if(config->fourcc == IMGFMT_YVU9 || + config->fourcc == IMGFMT_IF09) is_410 = 1; + if(config->fourcc == IMGFMT_Y800) is_400 = 1; + best_pitch = radeon_query_pitch(config->fourcc,&config->src.pitch); + mpitch = best_pitch-1; + BytesPerOctWord = 16; + LogMemWordsInBytes = 4; + MemWordsInBytes = 1<<LogMemWordsInBytes; + LogTileWidthInMemWords = 2; + TileWidthInMemWords = 1<<LogTileWidthInMemWords; + TileWidthInBytes = 1<<(LogTileWidthInMemWords+LogMemWordsInBytes); + LogTileHeight = 4; + TileHeight = 1<<LogTileHeight; + PageSizeInBytes = 64*MemWordsInBytes; + OV0LB_Rows = 96; + h_inc = 1; + switch(config->fourcc) + { + /* 4:0:0*/ + case IMGFMT_Y800: + /* 4:1:0*/ + case IMGFMT_YVU9: + case IMGFMT_IF09: + /* 4:2:0 */ + case IMGFMT_IYUV: + case IMGFMT_YV12: + case IMGFMT_I420: pitch = (src_w + mpitch) & ~mpitch; + config->dest.pitch.y = + config->dest.pitch.u = + config->dest.pitch.v = best_pitch; + break; + /* RGB 4:4:4:4 */ + case IMGFMT_RGB32: + case IMGFMT_BGR32: pitch = (src_w*4 + mpitch) & ~mpitch; + config->dest.pitch.y = + config->dest.pitch.u = + config->dest.pitch.v = best_pitch; + break; + /* 4:2:2 */ + + default: /* RGB15, RGB16, YVYU, UYVY, YUY2 */ + pitch = ((src_w*2) + mpitch) & ~mpitch; + config->dest.pitch.y = + config->dest.pitch.u = + config->dest.pitch.v = best_pitch; + break; + } + besr.load_prg_start=0; + besr.swap_uv=0; + switch(config->fourcc) + { + case IMGFMT_RGB15: + besr.swap_uv=1; + case IMGFMT_BGR15: besr.surf_id = SCALER_SOURCE_15BPP>>8; + besr.load_prg_start = 1; + break; + case IMGFMT_RGB16: + besr.swap_uv=1; + case IMGFMT_BGR16: besr.surf_id = SCALER_SOURCE_16BPP>>8; + besr.load_prg_start = 1; + break; + case IMGFMT_RGB32: + besr.swap_uv=1; + case IMGFMT_BGR32: besr.surf_id = SCALER_SOURCE_32BPP>>8; + besr.load_prg_start = 1; + break; + /* 4:1:0*/ + case IMGFMT_IF09: + case IMGFMT_YVU9: besr.surf_id = SCALER_SOURCE_YUV9>>8; + break; + /* 4:0:0*/ + case IMGFMT_Y800: + /* 4:2:0 */ + case IMGFMT_IYUV: + case IMGFMT_I420: + case IMGFMT_YV12: besr.surf_id = SCALER_SOURCE_YUV12>>8; + break; + /* 4:2:2 */ + case IMGFMT_YVYU: + case IMGFMT_UYVY: besr.surf_id = SCALER_SOURCE_YVYU422>>8; + break; + case IMGFMT_YUY2: + default: besr.surf_id = SCALER_SOURCE_VYUY422>>8; + break; + } + switch (besr.surf_id) + { + case 3: + case 4: + case 11: + case 12: BytesPerPixel = 2; + break; + case 6: BytesPerPixel = 4; + break; + case 9: + case 10: + case 13: + case 14: BytesPerPixel = 1; + break; + default: BytesPerPixel = 0;/*insert a debug statement here. */ + break; + } + switch (besr.surf_id) + { + case 3: + case 4: BytesPerUVPixel = 0; + break;/* In RGB modes, the BytesPerUVPixel is don't care */ + case 11: + case 12: BytesPerUVPixel = 2; + break; + case 6: BytesPerUVPixel = 0; + break; /* In RGB modes, the BytesPerUVPixel is don't care */ + case 9: + case 10: BytesPerUVPixel = 1; + break; + case 13: + case 14: BytesPerUVPixel = 2; + break; + default: BytesPerUVPixel = 0;/* insert a debug statement here. */ + break; + + } + switch (besr.surf_id) + { + case 3: + case 4: + case 6: HorzUVSubSample = 1; + break; + case 9: HorzUVSubSample = 4; + break; + case 10: + case 11: + case 12: + case 13: + case 14: HorzUVSubSample = 2; + break; + default: HorzUVSubSample = 0;/* insert debug statement here. */ + break; + } + switch (besr.surf_id) + { + case 3: + case 4: + case 6: + case 11: + case 12: VertUVSubSample = 1; + break; + case 9: VertUVSubSample = 4; + break; + case 10: + case 13: + case 14: VertUVSubSample = 2; + break; + default: VertUVSubSample = 0;/* insert debug statment here. */ + break; + } + DisallowFourTapVertFiltering = 0; /* Allow it by default */ + DisallowFourTapUVVertFiltering = 0; /* Allow it by default */ + LeftPixel = config->src.x; + RightPixel = config->src.w-1; + if(floor(config->src.x/HorzUVSubSample)<0) LeftUVPixel = 0; + else LeftUVPixel = (int)floor(config->src.x/HorzUVSubSample); + if(ceil((config->src.x+config->src.w)/HorzUVSubSample) > config->src.w/HorzUVSubSample) + RightUVPixel = config->src.w/HorzUVSubSample - 1; + else RightUVPixel = (int)ceil((config->src.x+config->src.w)/HorzUVSubSample) - 1; + /* Top, Bottom and Right Crops can be out of range. The driver will program the hardware + // to create a black border at the top and bottom. This is useful for DVD letterboxing. */ + SourceWidthInPixels = (int)(config->src.w + 1); + SourceUVWidthInPixels = (int)(RightUVPixel - LeftUVPixel + 1); + + SourceWidthInMemWords = (int)(ceil(RightPixel*BytesPerPixel / MemWordsInBytes) - + floor(LeftPixel*BytesPerPixel / MemWordsInBytes) + 1); + /* SourceUVWidthInMemWords means Source_U_or_V_or_UV_WidthInMemWords depending on whether the UV is packed together of not. */ + SourceUVWidthInMemWords = (int)(ceil(RightUVPixel*BytesPerUVPixel / + MemWordsInBytes) - floor(LeftUVPixel*BytesPerUVPixel / + MemWordsInBytes) + 1); + + switch (besr.surf_id) + { + case 9: + case 10: if ((ceil(SourceWidthInMemWords/2)-1) * 2 > OV0LB_Rows-1) + { + RADEON_ASSERT("ceil(SourceWidthInMemWords/2)-1) * 2 > OV0LB_Rows-1\n"); + } + else if ((SourceWidthInMemWords-1) * 2 > OV0LB_Rows-1) + { + DisallowFourTapVertFiltering = 1; + } + + if ((ceil(SourceUVWidthInMemWords/2)-1) * 4 + 1 > OV0LB_Rows-1) + { + /*CYCACC_ASSERT(0, "Image U plane width spans more octwords than supported by hardware.") */ + } + else if ((SourceUVWidthInMemWords-1) * 4 + 1 > OV0LB_Rows-1) + { + DisallowFourTapUVVertFiltering = 1; + } + + if ((ceil(SourceUVWidthInMemWords/2)-1) * 4 + 3 > OV0LB_Rows-1) + { + /*CYCACC_ASSERT(0, "Image V plane width spans more octwords than supported by hardware.") */ + } + else if ((SourceUVWidthInMemWords-1) * 4 + 3 > OV0LB_Rows-1) + { + DisallowFourTapUVVertFiltering = 1; + } + break; + case 13: + case 14: if ((ceil(SourceWidthInMemWords/2)-1) * 2 > OV0LB_Rows-1) + { + RADEON_ASSERT("ceil(SourceWidthInMemWords/2)-1) * 2 > OV0LB_Rows-1\n"); + } + else if ((SourceWidthInMemWords-1) * 2 > OV0LB_Rows-1) + { + DisallowFourTapVertFiltering = 1; + } + + if ((ceil(SourceUVWidthInMemWords/2)-1) * 2 + 1 > OV0LB_Rows-1) + { + /*CYCACC_ASSERT(0, "Image UV plane width spans more octwords than supported by hardware.") */ + } + else if ((SourceUVWidthInMemWords-1) * 2 + 1 > OV0LB_Rows-1) + { + DisallowFourTapUVVertFiltering = 1; + } + break; + case 3: + case 4: + case 6: + case 11: + case 12: if ((ceil(SourceWidthInMemWords/2)-1) > OV0LB_Rows-1) + { + RADEON_ASSERT("(ceil(SourceWidthInMemWords/2)-1) > OV0LB_Rows-1\n") + } + else if ((SourceWidthInMemWords-1) > OV0LB_Rows-1) + { + DisallowFourTapVertFiltering = 1; + } + break; + default: /* insert debug statement here. */ + break; + } + dest_w = config->dest.w; + dest_h = config->dest.h; + if(radeon_is_dbl_scan()) dest_h *= 2; + besr.dest_bpp = radeon_vid_get_dbpp(); + besr.fourcc = config->fourcc; + if(radeon_is_interlace()) interlace_factor = 2; + else interlace_factor = 1; + /* TODO: must be checked in doublescan mode!!! */ + if((besr.chip_flags&R_INTEGRATED)==R_INTEGRATED) + { + /* Force the overlay clock on for integrated chips */ + OUTPLL(VCLK_ECP_CNTL, (INPLL(VCLK_ECP_CNTL) | (1<<18))); + } + horz_repl_factor = 1 << (uint32_t)((INPLL(VCLK_ECP_CNTL) & 0x300) >> 8); + H_scale_ratio = (double)ceil(((double)dest_w+1)/horz_repl_factor)/src_w; + V_scale_ratio = (double)(dest_h+1)/src_h; + if(H_scale_ratio < 0.5 && V_scale_ratio < 0.5) + { + val_OV0_P1_MAX_LN_IN_PER_LN_OUT = 3; + val_OV0_P23_MAX_LN_IN_PER_LN_OUT = 2; + } + else + if(H_scale_ratio < 1 && V_scale_ratio < 1) + { + val_OV0_P1_MAX_LN_IN_PER_LN_OUT = 2; + val_OV0_P23_MAX_LN_IN_PER_LN_OUT = 1; + } + else + { + val_OV0_P1_MAX_LN_IN_PER_LN_OUT = 1; + val_OV0_P23_MAX_LN_IN_PER_LN_OUT = 1; + } + /* N.B.: Indeed it has 6.12 format but shifted on 8 to the left!!! */ + besr.v_inc = (uint16_t)((1./V_scale_ratio)*(1<<12)*interlace_factor+0.5); + CRT_V_INC = besr.v_inc/interlace_factor; + besr.v_inc <<= 8; + { + int ThereIsTwoTapVerticalFiltering,DoNotUseMostRecentlyFetchedLine; + int P1GroupSize; + int P23GroupSize; + int P1StepSize; + int P23StepSize; + + Calc_H_INC_STEP_BY( + besr.surf_id, + H_scale_ratio, + DisallowFourTapVertFiltering, + DisallowFourTapUVVertFiltering, + &val_OV0_P1_H_INC, + &val_OV0_P1_H_STEP_BY, + &val_OV0_P23_H_INC, + &val_OV0_P23_H_STEP_BY, + &P1GroupSize, + &P1StepSize, + &P23StepSize); + + if(H_scale_ratio > MinHScaleHard) + { + h_inc = (src_w << 12) / dest_w; + besr.step_by = 0x0101; + switch (besr.surf_id) + { + case 3: + case 4: + case 6: + besr.h_inc = (h_inc)|(h_inc<<16); + break; + case 9: + besr.h_inc = h_inc | ((h_inc >> 2) << 16); + break; + default: + besr.h_inc = h_inc | ((h_inc >> 1) << 16); + break; + } + } + + P23GroupSize = 2; /* Current vaue for all modes */ + + besr.horz_pick_nearest=0; + DoNotUseMostRecentlyFetchedLine=0; + ThereIsTwoTapVerticalFiltering = (val_OV0_P1_H_STEP_BY!=0) || (val_OV0_P23_H_STEP_BY!=0); + if (ThereIsTwoTapVerticalFiltering && DoNotUseMostRecentlyFetchedLine) + besr.vert_pick_nearest = 1; + else + besr.vert_pick_nearest = 0; + + ComputeXStartEnd(is_400,LeftPixel,LeftUVPixel,MemWordsInBytes,BytesPerPixel, + SourceWidthInPixels,P1StepSize,BytesPerUVPixel, + SourceUVWidthInPixels,P23StepSize,&val_OV0_P1_X_START,&val_OV0_P2_X_START); + + if(H_scale_ratio > MinHScaleHard) + { + unsigned tmp; + tmp = (left & 0x0003ffff) + 0x00028000 + (h_inc << 3); + besr.p1_h_accum_init = ((tmp << 4) & 0x000f8000) | + ((tmp << 12) & 0xf0000000); + + tmp = (top & 0x0000ffff) + 0x00018000; + besr.p1_v_accum_init = ((tmp << 4) & OV0_P1_V_ACCUM_INIT_MASK) + |(OV0_P1_MAX_LN_IN_PER_LN_OUT & 1); + tmp = ((left >> 1) & 0x0001ffff) + 0x00028000 + (h_inc << 2); + besr.p23_h_accum_init = ((tmp << 4) & 0x000f8000) | + ((tmp << 12) & 0x70000000); + + tmp = ((top >> 1) & 0x0000ffff) + 0x00018000; + besr.p23_v_accum_init = (is_420||is_410) ? + ((tmp << 4) & OV0_P23_V_ACCUM_INIT_MASK) + |(OV0_P23_MAX_LN_IN_PER_LN_OUT & 1) : 0; + } + else + ComputeAccumInit( val_OV0_P1_X_START,val_OV0_P2_X_START, + val_OV0_P1_H_INC,val_OV0_P23_H_INC, + val_OV0_P1_H_STEP_BY,val_OV0_P23_H_STEP_BY, + CRT_V_INC,P1GroupSize,P23GroupSize, + val_OV0_P1_MAX_LN_IN_PER_LN_OUT, + val_OV0_P23_MAX_LN_IN_PER_LN_OUT); + } + + /* keep everything in 16.16 */ + besr.base_addr = INREG(DISPLAY_BASE_ADDR); + config->offsets[0] = 0; + for(i=1;i<besr.vid_nbufs;i++) + config->offsets[i] = config->offsets[i-1]+config->frame_size; + if(is_420 || is_410 || is_400) + { + uint32_t d1line,d2line,d3line; + d1line = top*pitch; + if(is_420) + { + d2line = src_h*pitch+(d1line>>2); + d3line = d2line+((src_h*pitch)>>2); + } + else + if(is_410) + { + d2line = src_h*pitch+(d1line>>4); + d3line = d2line+((src_h*pitch)>>4); + } + else + { + d2line = 0; + d3line = 0; + } + d1line += (left >> 16) & ~15; + if(is_420) + { + d2line += (left >> 17) & ~15; + d3line += (left >> 17) & ~15; + } + else /* is_410 */ + { + d2line += (left >> 18) & ~15; + d3line += (left >> 18) & ~15; + } + config->offset.y = d1line & VIF_BUF0_BASE_ADRS_MASK; + if(is_400) + { + config->offset.v = 0; + config->offset.u = 0; + } + else + { + config->offset.v = d2line & VIF_BUF1_BASE_ADRS_MASK; + config->offset.u = d3line & VIF_BUF2_BASE_ADRS_MASK; + } + for(i=0;i<besr.vid_nbufs;i++) + { + besr.vid_buf_base_adrs_y[i]=((radeon_overlay_off+config->offsets[i]+config->offset.y)&VIF_BUF0_BASE_ADRS_MASK); + if(is_400) + { + besr.vid_buf_base_adrs_v[i]=0; + besr.vid_buf_base_adrs_u[i]=0; + } + else + { + besr.vid_buf_base_adrs_v[i]=((radeon_overlay_off+config->offsets[i]+config->offset.v)&VIF_BUF1_BASE_ADRS_MASK)|VIF_BUF1_PITCH_SEL; + besr.vid_buf_base_adrs_u[i]=((radeon_overlay_off+config->offsets[i]+config->offset.u)&VIF_BUF2_BASE_ADRS_MASK)|VIF_BUF2_PITCH_SEL; + } + } + config->offset.y = ((besr.vid_buf_base_adrs_y[0])&VIF_BUF0_BASE_ADRS_MASK) - radeon_overlay_off; + if(is_400) + { + config->offset.v = 0; + config->offset.u = 0; + } + else + { + config->offset.v = ((besr.vid_buf_base_adrs_v[0])&VIF_BUF1_BASE_ADRS_MASK) - radeon_overlay_off; + config->offset.u = ((besr.vid_buf_base_adrs_u[0])&VIF_BUF2_BASE_ADRS_MASK) - radeon_overlay_off; + } + if(besr.fourcc == IMGFMT_I420 || besr.fourcc == IMGFMT_IYUV) + { + uint32_t tmp; + tmp = config->offset.u; + config->offset.u = config->offset.v; + config->offset.v = tmp; + } + } + else + { + config->offset.y = config->offset.u = config->offset.v = ((left & ~7) << 1)&VIF_BUF0_BASE_ADRS_MASK; + for(i=0;i<besr.vid_nbufs;i++) + { + besr.vid_buf_base_adrs_y[i] = + besr.vid_buf_base_adrs_u[i] = + besr.vid_buf_base_adrs_v[i] = radeon_overlay_off + config->offsets[i] + config->offset.y; + } + } + leftUV = (left >> (is_410?18:17)) & 15; + left = (left >> 16) & 15; + besr.y_x_start = (config->dest.x+X_ADJUST) | (config->dest.y << 16); + besr.y_x_end = (config->dest.x + dest_w+X_ADJUST) | ((config->dest.y + dest_h) << 16); + ComputeBorders(config,VertUVSubSample); + besr.vid_buf_pitch0_value = pitch; + besr.vid_buf_pitch1_value = is_410 ? pitch>>2 : is_420 ? pitch>>1 : pitch; + /* ********************************************************* */ + /* ** Calculate programmable coefficients as needed */ + /* ********************************************************* */ + + /* ToDo_Active: When in pick nearest mode, we need to program the filter tap zero */ + /* coefficients to 0, 32, 0, 0. Or use hard coded coefficients. */ + if(H_scale_ratio > MinHScaleHard) besr.filter_cntl |= FILTER_HARDCODED_COEF; + else + { + FilterSetup (val_OV0_P1_H_INC); + /* ToDo_Active: Must add the smarts into the driver to decide what type of filtering it */ + /* would like to do. For now, we let the test application decide. */ + besr.filter_cntl = FILTER_PROGRAMMABLE_COEF; + if(DisallowFourTapVertFiltering) + besr.filter_cntl |= FILTER_HARD_SCALE_VERT_Y; + if(DisallowFourTapUVVertFiltering) + besr.filter_cntl |= FILTER_HARD_SCALE_VERT_UV; + } + return 0; +} + +static void radeon_compute_framesize(vidix_playback_t *info) +{ + unsigned pitch,awidth,dbpp; + pitch = radeon_query_pitch(info->fourcc,&info->src.pitch); + dbpp = radeon_vid_get_dbpp(); + switch(info->fourcc) + { + case IMGFMT_Y800: + awidth = (info->src.w + (pitch-1)) & ~(pitch-1); + info->frame_size = awidth*info->src.h; + break; + case IMGFMT_YVU9: + case IMGFMT_IF09: + awidth = (info->src.w + (pitch-1)) & ~(pitch-1); + info->frame_size = awidth*(info->src.h+info->src.h/8); + break; + case IMGFMT_I420: + case IMGFMT_YV12: + case IMGFMT_IYUV: + awidth = (info->src.w + (pitch-1)) & ~(pitch-1); + info->frame_size = awidth*(info->src.h+info->src.h/2); + break; + case IMGFMT_RGB32: + case IMGFMT_BGR32: + awidth = (info->src.w*4 + (pitch-1)) & ~(pitch-1); + info->frame_size = awidth*info->src.h; + break; + /* YUY2 YVYU, RGB15, RGB16 */ + default: + awidth = (info->src.w*2 + (pitch-1)) & ~(pitch-1); + info->frame_size = awidth*info->src.h; + break; + } + info->frame_size = (info->frame_size+4095)&~4095; +} + +int VIDIX_NAME(vixConfigPlayback)(vidix_playback_t *info) +{ + unsigned rgb_size,nfr; + uint32_t radeon_video_size; + if(!is_supported_fourcc(info->fourcc,info->src.w)) return ENOSYS; + if(info->num_frames>VID_PLAY_MAXFRAMES) info->num_frames=VID_PLAY_MAXFRAMES; + if(info->num_frames==1) besr.double_buff=0; + else besr.double_buff=1; + radeon_compute_framesize(info); + + rgb_size = radeon_get_xres()*radeon_get_yres()*((radeon_vid_get_dbpp()+7)/8); + nfr = info->num_frames; + radeon_video_size = radeon_ram_size; +#ifdef RADEON_ENABLE_BM + if(def_cap.flags & FLAG_DMA) + { + /* every descriptor describes one 4K page and takes 16 bytes in memory + Note: probably it's ont good idea to locate them in video memory + but as initial release it's OK */ + radeon_video_size -= radeon_ram_size * sizeof(bm_list_descriptor) / 4096; + radeon_dma_desc_base = (void *) pci_info.base0 + radeon_video_size; + } +#endif + for(;nfr>0; nfr--) + { + radeon_overlay_off = radeon_video_size - info->frame_size*nfr; + radeon_overlay_off &= 0xffff0000; + if(radeon_overlay_off >= (int)rgb_size ) break; + } + if(nfr <= 3) + { + nfr = info->num_frames; + for(;nfr>0; nfr--) + { + radeon_overlay_off = radeon_video_size - info->frame_size*nfr; + radeon_overlay_off &= 0xffff0000; + if(radeon_overlay_off > 0) break; + } + } + if(nfr <= 0) return EINVAL; + info->num_frames = nfr; + besr.vid_nbufs = info->num_frames; + info->dga_addr = (char *)radeon_mem_base + radeon_overlay_off; + radeon_vid_init_video(info); + return 0; +} + +int VIDIX_NAME(vixPlaybackOn)( void ) +{ +#ifdef RAGE128 + unsigned dw,dh; +#endif + radeon_vid_display_video(); +#ifdef RAGE128 + dh = (besr.y_x_end >> 16) - (besr.y_x_start >> 16); + dw = (besr.y_x_end & 0xFFFF) - (besr.y_x_start & 0xFFFF); + if(dw == radeon_get_xres() || dh == radeon_get_yres()) radeon_vid_exclusive(); + else radeon_vid_non_exclusive(); +#endif + return 0; +} + +int VIDIX_NAME(vixPlaybackOff)( void ) +{ + radeon_vid_stop_video(); + return 0; +} + +int VIDIX_NAME(vixPlaybackFrameSelect)(unsigned frame) +{ + uint32_t off[6]; + int prev_frame= (frame-1+besr.vid_nbufs) % besr.vid_nbufs; + /* + buf3-5 always should point onto second buffer for better + deinterlacing and TV-in + */ + if(!besr.double_buff) return 0; + if(frame > besr.vid_nbufs) frame = besr.vid_nbufs-1; + if(prev_frame > (int)besr.vid_nbufs) prev_frame = besr.vid_nbufs-1; + off[0] = besr.vid_buf_base_adrs_y[frame]; + off[1] = besr.vid_buf_base_adrs_v[frame]; + off[2] = besr.vid_buf_base_adrs_u[frame]; + off[3] = besr.vid_buf_base_adrs_y[prev_frame]; + off[4] = besr.vid_buf_base_adrs_v[prev_frame]; + off[5] = besr.vid_buf_base_adrs_u[prev_frame]; + radeon_fifo_wait(8); + OUTREG(OV0_REG_LOAD_CNTL, REG_LD_CTL_LOCK); + radeon_engine_idle(); + while(!(INREG(OV0_REG_LOAD_CNTL)®_LD_CTL_LOCK_READBACK)); + OUTREG(OV0_VID_BUF0_BASE_ADRS, off[0]); + OUTREG(OV0_VID_BUF1_BASE_ADRS, off[1]); + OUTREG(OV0_VID_BUF2_BASE_ADRS, off[2]); + OUTREG(OV0_VID_BUF3_BASE_ADRS, off[3]); + OUTREG(OV0_VID_BUF4_BASE_ADRS, off[4]); + OUTREG(OV0_VID_BUF5_BASE_ADRS, off[5]); + OUTREG(OV0_REG_LOAD_CNTL, 0); + if(besr.vid_nbufs == 2) radeon_wait_vsync(); + if(__verbose > VERBOSE_LEVEL) radeon_vid_dump_regs(); + return 0; +} + +vidix_video_eq_t equal = +{ + VEQ_CAP_BRIGHTNESS | VEQ_CAP_SATURATION +#ifndef RAGE128 + | VEQ_CAP_CONTRAST | VEQ_CAP_HUE | VEQ_CAP_RGB_INTENSITY +#endif + , + 0, 0, 0, 0, 0, 0, 0, 0 }; + +int VIDIX_NAME(vixPlaybackGetEq)( vidix_video_eq_t * eq) +{ + memcpy(eq,&equal,sizeof(vidix_video_eq_t)); + return 0; +} + +#ifndef RAGE128 +#define RTFSaturation(a) (1.0 + ((a)*1.0)/1000.0) +#define RTFBrightness(a) (((a)*1.0)/2000.0) +#define RTFIntensity(a) (((a)*1.0)/2000.0) +#define RTFContrast(a) (1.0 + ((a)*1.0)/1000.0) +#define RTFHue(a) (((a)*3.1416)/1000.0) +#define RTFCheckParam(a) {if((a)<-1000) (a)=-1000; if((a)>1000) (a)=1000;} +#endif + +int VIDIX_NAME(vixPlaybackSetEq)( const vidix_video_eq_t * eq) +{ +#ifdef RAGE128 + int br,sat; +#else + int itu_space; +#endif + if(eq->cap & VEQ_CAP_BRIGHTNESS) equal.brightness = eq->brightness; + if(eq->cap & VEQ_CAP_CONTRAST) equal.contrast = eq->contrast; + if(eq->cap & VEQ_CAP_SATURATION) equal.saturation = eq->saturation; + if(eq->cap & VEQ_CAP_HUE) equal.hue = eq->hue; + if(eq->cap & VEQ_CAP_RGB_INTENSITY) + { + equal.red_intensity = eq->red_intensity; + equal.green_intensity = eq->green_intensity; + equal.blue_intensity = eq->blue_intensity; + } + equal.flags = eq->flags; +#ifdef RAGE128 + br = equal.brightness * 64 / 1000; + if(br < -64) br = -64; if(br > 63) br = 63; + sat = (equal.saturation*31 + 31000) / 2000; + if(sat < 0) sat = 0; if(sat > 31) sat = 31; + OUTREG(OV0_COLOUR_CNTL, (br & 0x7f) | (sat << 8) | (sat << 16)); +#else + itu_space = equal.flags == VEQ_FLG_ITU_R_BT_709 ? 1 : 0; + RTFCheckParam(equal.brightness); + RTFCheckParam(equal.saturation); + RTFCheckParam(equal.contrast); + RTFCheckParam(equal.hue); + RTFCheckParam(equal.red_intensity); + RTFCheckParam(equal.green_intensity); + RTFCheckParam(equal.blue_intensity); + radeon_set_transform(RTFBrightness(equal.brightness), + RTFContrast(equal.contrast), + RTFSaturation(equal.saturation), + RTFHue(equal.hue), + RTFIntensity(equal.red_intensity), + RTFIntensity(equal.green_intensity), + RTFIntensity(equal.blue_intensity), + itu_space); +#endif + return 0; +} + +int VIDIX_NAME(vixPlaybackSetDeint)( const vidix_deinterlace_t * info) +{ + unsigned sflg; + switch(info->flags) + { + default: + case CFG_NON_INTERLACED: + besr.deinterlace_on = 0; + break; + case CFG_EVEN_ODD_INTERLACING: + case CFG_INTERLACED: + besr.deinterlace_on = 1; + besr.deinterlace_pattern = 0x900AAAAA; + break; + case CFG_ODD_EVEN_INTERLACING: + besr.deinterlace_on = 1; + besr.deinterlace_pattern = 0x00055555; + break; + case CFG_UNIQUE_INTERLACING: + besr.deinterlace_on = 1; + besr.deinterlace_pattern = info->deinterlace_pattern; + break; + } + OUTREG(OV0_REG_LOAD_CNTL, REG_LD_CTL_LOCK); + radeon_engine_idle(); + while(!(INREG(OV0_REG_LOAD_CNTL)®_LD_CTL_LOCK_READBACK)); + radeon_fifo_wait(15); + sflg = INREG(OV0_SCALE_CNTL); + if(besr.deinterlace_on) + { + OUTREG(OV0_SCALE_CNTL,sflg | SCALER_ADAPTIVE_DEINT); + OUTREG(OV0_DEINTERLACE_PATTERN,besr.deinterlace_pattern); + } + else OUTREG(OV0_SCALE_CNTL,sflg & (~SCALER_ADAPTIVE_DEINT)); + OUTREG(OV0_REG_LOAD_CNTL, 0); + return 0; +} + +int VIDIX_NAME(vixPlaybackGetDeint)( vidix_deinterlace_t * info) +{ + if(!besr.deinterlace_on) info->flags = CFG_NON_INTERLACED; + else + { + info->flags = CFG_UNIQUE_INTERLACING; + info->deinterlace_pattern = besr.deinterlace_pattern; + } + return 0; +} + + +/* Graphic keys */ +static vidix_grkey_t radeon_grkey; + +static void set_gr_key( void ) +{ + if(radeon_grkey.ckey.op == CKEY_TRUE) + { + int dbpp=radeon_vid_get_dbpp(); + + switch(dbpp) + { + case 15: +#ifndef RAGE128 + besr.graphics_key_clr= + ((radeon_grkey.ckey.blue &0xF8)) + | ((radeon_grkey.ckey.green&0xF8)<<8) + | ((radeon_grkey.ckey.red &0xF8)<<16); +#else + besr.graphics_key_clr= + ((radeon_grkey.ckey.blue &0xF8)>>3) + | ((radeon_grkey.ckey.green&0xF8)<<2) + | ((radeon_grkey.ckey.red &0xF8)<<7); +#endif + break; + case 16: +#ifndef RAGE128 + besr.graphics_key_clr= + ((radeon_grkey.ckey.blue &0xF8)) + | ((radeon_grkey.ckey.green&0xFC)<<8) + | ((radeon_grkey.ckey.red &0xF8)<<16); +#else + besr.graphics_key_clr= + ((radeon_grkey.ckey.blue &0xF8)>>3) + | ((radeon_grkey.ckey.green&0xFC)<<3) + | ((radeon_grkey.ckey.red &0xF8)<<8); +#endif + break; + case 24: + case 32: + besr.graphics_key_clr= + ((radeon_grkey.ckey.blue &0xFF)) + | ((radeon_grkey.ckey.green&0xFF)<<8) + | ((radeon_grkey.ckey.red &0xFF)<<16); + break; + default: + besr.graphics_key_msk=0; + besr.graphics_key_clr=0; + } +#ifdef RAGE128 + besr.graphics_key_msk=(1<<dbpp)-1; + besr.ckey_cntl = VIDEO_KEY_FN_TRUE|GRAPHIC_KEY_FN_NE|CMP_MIX_AND; +#else + besr.graphics_key_msk=besr.graphics_key_clr; + besr.ckey_cntl = VIDEO_KEY_FN_TRUE|CMP_MIX_AND|GRAPHIC_KEY_FN_EQ; +#endif + } + else + { + besr.graphics_key_msk=0; + besr.graphics_key_clr=0; + besr.ckey_cntl = VIDEO_KEY_FN_TRUE|GRAPHIC_KEY_FN_TRUE|CMP_MIX_AND; + } + radeon_fifo_wait(3); + OUTREG(OV0_GRAPHICS_KEY_MSK, besr.graphics_key_msk); + OUTREG(OV0_GRAPHICS_KEY_CLR, besr.graphics_key_clr); + OUTREG(OV0_KEY_CNTL,besr.ckey_cntl); +} + +int VIDIX_NAME(vixGetGrKeys)(vidix_grkey_t *grkey) +{ + memcpy(grkey, &radeon_grkey, sizeof(vidix_grkey_t)); + return(0); +} + +int VIDIX_NAME(vixSetGrKeys)(const vidix_grkey_t *grkey) +{ + memcpy(&radeon_grkey, grkey, sizeof(vidix_grkey_t)); + set_gr_key(); + return(0); +} + +#ifdef RADEON_ENABLE_BM +static int radeon_setup_frame( vidix_dma_t * dmai ) +{ + bm_list_descriptor * list = (bm_list_descriptor *)radeon_dma_desc_base; + unsigned long dest_ptr; + unsigned i,n,count; + int retval; + if(dmai->dest_offset + dmai->size > radeon_ram_size) return E2BIG; + n = dmai->size / 4096; + if(dmai->size % 4096) n++; + if((retval = bm_virt_to_bus(dmai->src,dmai->size,dma_phys_addrs)) != 0) return retval; + dest_ptr = dmai->dest_offset; + count = dmai->size; + for(i=0;i<n;i++) + { + list[i].framebuf_offset = radeon_overlay_off + dest_ptr; + list[i].sys_addr = dma_phys_addrs[i]; +#ifdef RAGE128 + list[i].command = (count > 4096 ? 4096 : count | BM_END_OF_LIST)|BM_FORCE_TO_PCI; +#else + list[i].command = (count > 4096 ? 4096 : count | DMA_GUI_COMMAND__EOL); +#endif + list[i].reserved = 0; +printf("RADEON_DMA_TABLE[%i] %X %X %X %X\n",i,list[i].framebuf_offset,list[i].sys_addr,list[i].command,list[i].reserved); + dest_ptr += 4096; + count -= 4096; + } + return 0; +} + +static int radeon_transfer_frame( void ) +{ + unsigned i; + radeon_engine_idle(); + for(i=0;i<1000;i++) INREG(BUS_CNTL); /* FlushWriteCombining */ + OUTREG(BUS_CNTL,(INREG(BUS_CNTL) | BUS_STOP_REQ_DIS)&(~BUS_MASTER_DIS)); +#ifdef RAGE128 + OUTREG(BM_CHUNK_0_VAL,0x000000FF | BM_GLOBAL_FORCE_TO_PCI); + OUTREG(BM_CHUNK_1_VAL,0x0F0F0F0F); + OUTREG(BM_VIP0_BUF,bus_addr_dma_desc|SYSTEM_TRIGGER_SYSTEM_TO_VIDEO); +// OUTREG(GEN_INT_STATUS,INREG(GEN_INT_STATUS)|0x00010000); +#else + OUTREG(MC_FB_LOCATION, + ((pci_info.base0>>16)&0xffff)| + ((pci_info.base0+INREG(CONFIG_APER_SIZE)-1)&0xffff0000)); + if((INREG(MC_AGP_LOCATION)&0xffff)!= + (((pci_info.base0+INREG(CONFIG_APER_SIZE))>>16)&0xffff)) + /*Radeon memory controller is misconfigured*/ + return EINVAL; + OUTREG(DMA_VID_ACT_DSCRPTR,bus_addr_dma_desc); +// OUTREG(GEN_INT_STATUS,INREG(GEN_INT_STATUS)|(1<<30)); +#endif + OUTREG(GEN_INT_STATUS,INREG(GEN_INT_STATUS)|0x00010000); + return 0; +} + + +int VIDIX_NAME(vixPlaybackCopyFrame)( vidix_dma_t * dmai ) +{ + int retval; + if(mlock(dmai->src,dmai->size) != 0) return errno; + retval = radeon_setup_frame(dmai); + if(retval == 0) retval = radeon_transfer_frame(); + munlock(dmai->src,dmai->size); + return retval; +} + +int VIDIX_NAME(vixQueryDMAStatus)( void ) +{ + int bm_active; +#if 1 //def RAGE128 + bm_active=(INREG(GEN_INT_STATUS)&0x00010000)==0?1:0; +#else + bm_active=(INREG(GEN_INT_STATUS)&(1<<30))==0?1:0; +#endif + return bm_active?1:0; +} +#endif diff --git a/contrib/vidix/drivers/savage_regs.h b/contrib/vidix/drivers/savage_regs.h new file mode 100644 index 000000000..a8a44c7c3 --- /dev/null +++ b/contrib/vidix/drivers/savage_regs.h @@ -0,0 +1,304 @@ +/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/savage/savage_regs.h,v 1.10 2001/11/04 22:17:48 alanh Exp $ */ + +#ifndef _SAVAGE_REGS_H +#define _SAVAGE_REGS_H + +/* These are here until xf86PciInfo.h is updated. */ + +#ifndef PCI_CHIP_S3TWISTER_P +#define PCI_CHIP_S3TWISTER_P 0x8d01 +#endif +#ifndef PCI_CHIP_S3TWISTER_K +#define PCI_CHIP_S3TWISTER_K 0x8d02 +#endif +#ifndef PCI_CHIP_SUPSAV_MX128 +#define PCI_CHIP_SUPSAV_MX128 0x8c22 +#define PCI_CHIP_SUPSAV_MX64 0x8c24 +#define PCI_CHIP_SUPSAV_MX64C 0x8c26 +#define PCI_CHIP_SUPSAV_IX128SDR 0x8c2a +#define PCI_CHIP_SUPSAV_IX128DDR 0x8c2b +#define PCI_CHIP_SUPSAV_IX64SDR 0x8c2c +#define PCI_CHIP_SUPSAV_IX64DDR 0x8c2d +#define PCI_CHIP_SUPSAV_IXCSDR 0x8c2e +#define PCI_CHIP_SUPSAV_IXCDDR 0x8c2f +#endif +#ifndef PCI_CHIP_PROSAVAGE_DDR +#define PCI_CHIP_PROSAVAGE_DDR 0x8d03 +#define PCI_CHIP_PROSAVAGE_DDRK 0x8d04 +#endif + +#define S3_SAVAGE3D_SERIES(chip) ((chip>=S3_SAVAGE3D) && (chip<=S3_SAVAGE_MX)) + +#define S3_SAVAGE4_SERIES(chip) ((chip==S3_SAVAGE4) || (chip==S3_PROSAVAGE)) + +#define S3_SAVAGE_MOBILE_SERIES(chip) ((chip==S3_SAVAGE_MX) || (chip==S3_SUPERSAVAGE)) + +#define S3_SAVAGE_SERIES(chip) ((chip>=S3_SAVAGE3D) && (chip<=S3_SAVAGE2000)) + + +/* Chip tags. These are used to group the adapters into + * related families. + */ + + +enum S3CHIPTAGS { + S3_UNKNOWN = 0, + S3_SAVAGE3D, + S3_SAVAGE_MX, + S3_SAVAGE4, + S3_PROSAVAGE, + S3_SUPERSAVAGE, + S3_SAVAGE2000, + S3_LAST +}; + +typedef struct { + unsigned int mode, refresh; + unsigned char SR08, SR0E, SR0F; + unsigned char SR10, SR11, SR12, SR13, SR15, SR18, SR1B, SR29, SR30; + unsigned char SR54[8]; + unsigned char Clock; + unsigned char CR31, CR32, CR33, CR34, CR36, CR3A, CR3B, CR3C; + unsigned char CR40, CR41, CR42, CR43, CR45; + unsigned char CR50, CR51, CR53, CR55, CR58, CR5B, CR5D, CR5E; + unsigned char CR60, CR63, CR65, CR66, CR67, CR68, CR69, CR6D, CR6F; + unsigned char CR86, CR88; + unsigned char CR90, CR91, CRB0; + unsigned int STREAMS[22]; /* yuck, streams regs */ + unsigned int MMPR0, MMPR1, MMPR2, MMPR3; +} SavageRegRec, *SavageRegPtr; + + + +#define BIOS_BSIZE 1024 +#define BIOS_BASE 0xc0000 + +#define SAVAGE_NEWMMIO_REGBASE_S3 0x1000000 /* 16MB */ +#define SAVAGE_NEWMMIO_REGBASE_S4 0x0000000 +#define SAVAGE_NEWMMIO_REGSIZE 0x0080000 /* 512kb */ +#define SAVAGE_NEWMMIO_VGABASE 0x8000 + +#define BASE_FREQ 14.31818 + +#define FIFO_CONTROL_REG 0x8200 +#define MIU_CONTROL_REG 0x8204 +#define STREAMS_TIMEOUT_REG 0x8208 +#define MISC_TIMEOUT_REG 0x820c + +/* Stream Processor 1 */ + +/* Primary Stream 1 Frame Buffer Address 0 */ +#define PRI_STREAM_FBUF_ADDR0 0x81c0 +/* Primary Stream 1 Frame Buffer Address 0 */ +#define PRI_STREAM_FBUF_ADDR1 0x81c4 +/* Primary Stream 1 Stride */ +#define PRI_STREAM_STRIDE 0x81c8 +/* Primary Stream 1 Frame Buffer Size */ +#define PRI_STREAM_BUFFERSIZE 0x8214 + +/* Secondary stream 1 Color/Chroma Key Control */ +#define SEC_STREAM_CKEY_LOW 0x8184 +/* Secondary stream 1 Chroma Key Upper Bound */ +#define SEC_STREAM_CKEY_UPPER 0x8194 +/* Blend Control of Secondary Stream 1 & 2 */ +#define BLEND_CONTROL 0x8190 +/* Secondary Stream 1 Color conversion/Adjustment 1 */ +#define SEC_STREAM_COLOR_CONVERT1 0x8198 +/* Secondary Stream 1 Color conversion/Adjustment 2 */ +#define SEC_STREAM_COLOR_CONVERT2 0x819c +/* Secondary Stream 1 Color conversion/Adjustment 3 */ +#define SEC_STREAM_COLOR_CONVERT3 0x81e4 +/* Secondary Stream 1 Horizontal Scaling */ +#define SEC_STREAM_HSCALING 0x81a0 +/* Secondary Stream 1 Frame Buffer Size */ +#define SEC_STREAM_BUFFERSIZE 0x81a8 +/* Secondary Stream 1 Horizontal Scaling Normalization (2K only) */ +#define SEC_STREAM_HSCALE_NORMALIZE 0x81ac +/* Secondary Stream 1 Horizontal Scaling */ +#define SEC_STREAM_VSCALING 0x81e8 +/* Secondary Stream 1 Frame Buffer Address 0 */ +#define SEC_STREAM_FBUF_ADDR0 0x81d0 +/* Secondary Stream 1 Frame Buffer Address 1 */ +#define SEC_STREAM_FBUF_ADDR1 0x81d4 +/* Secondary Stream 1 Frame Buffer Address 2 */ +#define SEC_STREAM_FBUF_ADDR2 0x81ec +/* Secondary Stream 1 Stride */ +#define SEC_STREAM_STRIDE 0x81d8 +/* Secondary Stream 1 Window Start Coordinates */ +#define SEC_STREAM_WINDOW_START 0x81f8 +/* Secondary Stream 1 Window Size */ +#define SEC_STREAM_WINDOW_SZ 0x81fc +/* Secondary Streams Tile Offset */ +#define SEC_STREAM_TILE_OFF 0x821c +/* Secondary Stream 1 Opaque Overlay Control */ +#define SEC_STREAM_OPAQUE_OVERLAY 0x81dc + + +/* Stream Processor 2 */ + +/* Primary Stream 2 Frame Buffer Address 0 */ +#define PRI_STREAM2_FBUF_ADDR0 0x81b0 +/* Primary Stream 2 Frame Buffer Address 1 */ +#define PRI_STREAM2_FBUF_ADDR1 0x81b4 +/* Primary Stream 2 Stride */ +#define PRI_STREAM2_STRIDE 0x81b8 +/* Primary Stream 2 Frame Buffer Size */ +#define PRI_STREAM2_BUFFERSIZE 0x8218 + +/* Secondary Stream 2 Color/Chroma Key Control */ +#define SEC_STREAM2_CKEY_LOW 0x8188 +/* Secondary Stream 2 Chroma Key Upper Bound */ +#define SEC_STREAM2_CKEY_UPPER 0x818c +/* Secondary Stream 2 Horizontal Scaling */ +#define SEC_STREAM2_HSCALING 0x81a4 +/* Secondary Stream 2 Horizontal Scaling */ +#define SEC_STREAM2_VSCALING 0x8204 +/* Secondary Stream 2 Frame Buffer Size */ +#define SEC_STREAM2_BUFFERSIZE 0x81ac +/* Secondary Stream 2 Frame Buffer Address 0 */ +#define SEC_STREAM2_FBUF_ADDR0 0x81bc +/* Secondary Stream 2 Frame Buffer Address 1 */ +#define SEC_STREAM2_FBUF_ADDR1 0x81e0 +/* Secondary Stream 2 Frame Buffer Address 2 */ +#define SEC_STREAM2_FBUF_ADDR2 0x8208 +/* Multiple Buffer/LPB and Secondary Stream 2 Stride */ +#define SEC_STREAM2_STRIDE_LPB 0x81cc +/* Secondary Stream 2 Color conversion/Adjustment 1 */ +#define SEC_STREAM2_COLOR_CONVERT1 0x81f0 +/* Secondary Stream 2 Color conversion/Adjustment 2 */ +#define SEC_STREAM2_COLOR_CONVERT2 0x81f4 +/* Secondary Stream 2 Color conversion/Adjustment 3 */ +#define SEC_STREAM2_COLOR_CONVERT3 0x8200 +/* Secondary Stream 2 Window Start Coordinates */ +#define SEC_STREAM2_WINDOW_START 0x820c +/* Secondary Stream 2 Window Size */ +#define SEC_STREAM2_WINDOW_SZ 0x8210 +/* Secondary Stream 2 Opaque Overlay Control */ +#define SEC_STREAM2_OPAQUE_OVERLAY 0x8180 + + +/* savage 2000 */ +#define SEC_STREAM_COLOR_CONVERT0_2000 0x8198 +#define SEC_STREAM_COLOR_CONVERT1_2000 0x819c +#define SEC_STREAM_COLOR_CONVERT2_2000 0x81e0 +#define SEC_STREAM_COLOR_CONVERT3_2000 0x81e4 + +#define SUBSYS_STAT_REG 0x8504 + +#define SRC_BASE 0xa4d4 +#define DEST_BASE 0xa4d8 +#define CLIP_L_R 0xa4dc +#define CLIP_T_B 0xa4e0 +#define DEST_SRC_STR 0xa4e4 +#define MONO_PAT_0 0xa4e8 +#define MONO_PAT_1 0xa4ec + +/* Constants for CR69. */ + +#define CRT_ACTIVE 0x01 +#define LCD_ACTIVE 0x02 +#define TV_ACTIVE 0x04 +#define CRT_ATTACHED 0x10 +#define LCD_ATTACHED 0x20 +#define TV_ATTACHED 0x40 + + +/* + * reads from SUBSYS_STAT + */ +#define STATUS_WORD0 (INREG(0x48C00)) +#define ALT_STATUS_WORD0 (INREG(0x48C60)) +#define MAXLOOP 0xffffff +#define IN_SUBSYS_STAT() (INREG(SUBSYS_STAT_REG)) + +#define MAXFIFO 0x7f00 + +/* + * NOTE: don't remove 'VGAIN8(vgaCRIndex);'. + * If not present it will cause lockups on Savage4. + * Ask S3, why. + */ +/*#define VerticalRetraceWait() \ +{ \ + VGAIN8(0x3d0+4); \ + VGAOUT8(0x3d0+4, 0x17); \ + if (VGAIN8(0x3d0+5) & 0x80) { \ + while ((VGAIN8(0x3d0 + 0x0a) & 0x08) == 0x08) ; \ + while ((VGAIN8(0x3d0 + 0x0a) & 0x08) == 0x00) ; \ + } \ +} +*/ + +#define VerticalRetraceWait() \ +do { \ + VGAIN8(0x3d4); \ + VGAOUT8(0x3d4, 0x17); \ + if (VGAIN8(0x3d5) & 0x80) { \ + int i = 0x10000; \ + while ((VGAIN8(0x3da) & 0x08) == 0x08 && i--) ; \ + i = 0x10000; \ + while ((VGAIN8(0x3da) & 0x08) == 0x00 && i--) ; \ + } \ +} while (0) + + +#define I2C_REG 0xa0 +#define InI2CREG(a) \ +{ \ + VGAOUT8(0x3d0 + 4, I2C_REG); \ + a = VGAIN8(0x3d0 + 5); \ +} + +#define OutI2CREG(a) \ +{ \ + VGAOUT8(0x3d0 + 4, I2C_REG); \ + VGAOUT8(0x3d0 + 5, a); \ +} + +#define HZEXP_COMP_1 0x54 +#define HZEXP_BORDER 0x58 +#define HZEXP_FACTOR_IGA1 0x59 + +#define VTEXP_COMP_1 0x56 +#define VTEXP_BORDER 0x5a +#define VTEXP_FACTOR_IGA1 0x5b + +#define EC1_CENTER_ON 0x10 +#define EC1_EXPAND_ON 0x0c + +#define MODE_24 24 + +#if (MODE_24 == 32) +# define BYTES_PP24 4 +#else +# define BYTES_PP24 3 +#endif + +#define OVERLAY_DEPTH 16 + +#define STREAMS_MODE32 0x7 +#define STREAMS_MODE24 0x6 +#define STREAMS_MODE16 0x5 /* @@@ */ + + +#define DEPTH_BPP(depth) (depth == 24 ? (BYTES_PP24 << 3) : (depth + 7) & ~0x7) +#define DEPTH_2ND(depth) (depth > 8 ? depth\ + : OVERLAY_DEPTH) +#define SSTREAMS_MODE(bpp) (bpp > 16 ? (bpp > 24 ? STREAMS_MODE32 :\ + STREAMS_MODE24) : STREAMS_MODE16) + +#define HSCALING_Shift 0 +#define HSCALING_Mask (((1L << 16)-1) << HSCALING_Shift) +#define HSCALING(w0,w1) ((((unsigned int)(((double)w0/(double)w1) * (1 << 15))) \ + << HSCALING_Shift) \ + & HSCALING_Mask) + +#define VSCALING_Shift 0 +#define VSCALING_Mask (((1L << 20)-1) << VSCALING_Shift) +#define VSCALING(h0,h1) ((((unsigned int) (((double)h0/(double)h1) * (1 << 15))) \ + << VSCALING_Shift) \ + & VSCALING_Mask) + + +#endif /* _SAVAGE_REGS_H */ + diff --git a/contrib/vidix/drivers/savage_vid.c b/contrib/vidix/drivers/savage_vid.c new file mode 100644 index 000000000..2ac76198d --- /dev/null +++ b/contrib/vidix/drivers/savage_vid.c @@ -0,0 +1,1472 @@ +/* + Driver for S3 Savage Series + + Copyright (C) 2004 by Reza Jelveh + + Based on the X11 driver and nvidia vid + + Thanks to Alex Deucher for Support + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + Changes: + 2004-11-09 + Initial version + + To Do: + +*/ + + +#include <errno.h> +#include <stdio.h> +#include <stdlib.h> +#include <string.h> +#include <inttypes.h> +#include <unistd.h> +#include <math.h> + +#include "vidix.h" +#include "fourcc.h" +#include "libdha.h" +#include "pci_ids.h" +#include "pci_names.h" + +#include "savage_regs.h" + + +#define VF_STREAMS_ON 0x0001 +#define BASE_PAD 0xf +#define FRAMEBUFFER_SIZE 1024*2000*4 +/************************************** + S3 streams processor +**************************************/ + +#define EXT_MISC_CTRL2 0x67 + +/* New streams */ + +/* CR67[2] = 1 : enable stream 1 */ +#define ENABLE_STREAM1 0x04 +/* CR67[1] = 1 : enable stream 2 */ +#define ENABLE_STREAM2 0x02 +/* mask to clear CR67[2,1] */ +#define NO_STREAMS 0xF9 +/* CR67[3] = 1 : Mem-mapped regs */ +#define USE_MM_FOR_PRI_STREAM 0x08 + +#define HDM_SHIFT 16 +#define HDSCALE_4 (2 << HDM_SHIFT) +#define HDSCALE_8 (3 << HDM_SHIFT) +#define HDSCALE_16 (4 << HDM_SHIFT) +#define HDSCALE_32 (5 << HDM_SHIFT) +#define HDSCALE_64 (6 << HDM_SHIFT) + +/* Old Streams */ + +#define ENABLE_STREAMS_OLD 0x0c +#define NO_STREAMS_OLD 0xf3 +/* CR69[0] = 1 : Mem-mapped regs */ +#define USE_MM_FOR_PRI_STREAM_OLD 0x01 + +static void SavageStreamsOn(void); + +/* + * There are two different streams engines used in the Savage line. + * The old engine is in the 3D, 4, Pro, and Twister. + * The new engine is in the 2000, MX, IX, and Super. + */ + + +/* streams registers for old engine */ +#define PSTREAM_CONTROL_REG 0x8180 +#define COL_CHROMA_KEY_CONTROL_REG 0x8184 +#define SSTREAM_CONTROL_REG 0x8190 +#define CHROMA_KEY_UPPER_BOUND_REG 0x8194 +#define SSTREAM_STRETCH_REG 0x8198 +#define COLOR_ADJUSTMENT_REG 0x819C +#define BLEND_CONTROL_REG 0x81A0 +#define PSTREAM_FBADDR0_REG 0x81C0 +#define PSTREAM_FBADDR1_REG 0x81C4 +#define PSTREAM_STRIDE_REG 0x81C8 +#define DOUBLE_BUFFER_REG 0x81CC +#define SSTREAM_FBADDR0_REG 0x81D0 +#define SSTREAM_FBADDR1_REG 0x81D4 +#define SSTREAM_STRIDE_REG 0x81D8 +#define SSTREAM_VSCALE_REG 0x81E0 +#define SSTREAM_VINITIAL_REG 0x81E4 +#define SSTREAM_LINES_REG 0x81E8 +#define STREAMS_FIFO_REG 0x81EC +#define PSTREAM_WINDOW_START_REG 0x81F0 +#define PSTREAM_WINDOW_SIZE_REG 0x81F4 +#define SSTREAM_WINDOW_START_REG 0x81F8 +#define SSTREAM_WINDOW_SIZE_REG 0x81FC +#define FIFO_CONTROL 0x8200 +#define PSTREAM_FBSIZE_REG 0x8300 +#define SSTREAM_FBSIZE_REG 0x8304 +#define SSTREAM_FBADDR2_REG 0x8308 + +#define OS_XY(x,y) (((x+1)<<16)|(y+1)) +#define OS_WH(x,y) (((x-1)<<16)|(y)) + +#define PCI_COMMAND_MEM 0x2 +#define MAX_FRAMES 3 +/** + * @brief Information on PCI device. + */ +pciinfo_t pci_info; + +/** + * @brief Unichrome driver colorkey settings. + */ +/* static vidix_grkey_t savage_grkey; */ + +/* static int frames[VID_PLAY_MAXFRAMES]; */ +uint8_t *vio; +uint8_t mclk_save[3]; + +#define outb(reg,val) OUTPORT8(reg,val) +#define inb(reg) INPORT8(reg) +#define outw(reg,val) OUTPORT16(reg,val) +#define inw(reg) INPORT16(reg) +#define outl(reg,val) OUTPORT32(reg,val) +#define inl(reg) INPORT32(reg) + + +/* + * PCI-Memory IO access macros. + */ +#define VID_WR08(p,i,val) (((uint8_t *)(p))[(i)]=(val)) +#define VID_RD08(p,i) (((uint8_t *)(p))[(i)]) + +#define VID_WR32(p,i,val) (((uint32_t *)(p))[(i)/4]=(val)) +#define VID_RD32(p,i) (((uint32_t *)(p))[(i)/4]) + +#ifndef USE_RMW_CYCLES +/* + * Can be used to inhibit READ-MODIFY-WRITE cycles. On by default. + */ + +#define MEM_BARRIER() __asm__ __volatile__ ("" : : : "memory") + +#undef VID_WR08 +#define VID_WR08(p,i,val) ({ MEM_BARRIER(); ((uint8_t *)(p))[(i)]=(val); }) +#undef VID_RD08 +#define VID_RD08(p,i) ({ MEM_BARRIER(); ((uint8_t *)(p))[(i)]; }) + +#undef VID_WR16 +#define VID_WR16(p,i,val) ({ MEM_BARRIER(); ((uint16_t *)(p))[(i)/2]=(val); }) +#undef VID_RD16 +#define VID_RD16(p,i) ({ MEM_BARRIER(); ((uint16_t *)(p))[(i)/2]; }) + +#undef VID_WR32 +#define VID_WR32(p,i,val) ({ MEM_BARRIER(); ((uint32_t *)(p))[(i)/4]=(val); }) +#undef VID_RD32 +#define VID_RD32(p,i) ({ MEM_BARRIER(); ((uint32_t *)(p))[(i)/4]; }) +#endif /* USE_RMW_CYCLES */ + +#define VID_AND32(p,i,val) VID_WR32(p,i,VID_RD32(p,i)&(val)) +#define VID_OR32(p,i,val) VID_WR32(p,i,VID_RD32(p,i)|(val)) +#define VID_XOR32(p,i,val) VID_WR32(p,i,VID_RD32(p,i)^(val)) + + +/* from x driver */ + +#define VGAIN8(addr) VID_RD08(info->control_base+0x8000, addr) +#define VGAIN16(addr) VID_RD16(info->control_base+0x8000, addr) +#define VGAIN(addr) VID_RD32(info->control_base+0x8000, addr) + +#define VGAOUT8(addr,val) VID_WR08(info->control_base+0x8000, addr, val) +#define VGAOUT16(addr,val) VID_WR16(info->control_base+0x8000, addr, val) +#define VGAOUT(addr,val) VID_WR32(info->control_base+0x8000, addr, val) + +#define INREG(addr) VID_RD32(info->control_base, addr) +#define OUTREG(addr,val) VID_WR32(info->control_base, addr, val) +#define INREG8(addr) VID_RD08(info->control_base, addr) +#define OUTREG8(addr,val) VID_WR08(info->control_base, addr, val) +#define INREG16(addr) VID_RD16(info->control_base, addr) +#define OUTREG16(addr,val) VID_WR16(info->control_base, addr, val) + +#define ALIGN_TO(v, n) (((v) + (n-1)) & ~(n-1)) + + +void debugout(unsigned int addr, unsigned int val); + + +struct savage_chip { + volatile uint32_t *PMC; /* general control */ + volatile uint32_t *PME; /* multimedia port */ + volatile uint32_t *PFB; /* framebuffer control */ + volatile uint32_t *PVIDEO; /* overlay control */ + volatile uint8_t *PCIO; /* SVGA (CRTC, ATTR) registers */ + volatile uint8_t *PVIO; /* SVGA (MISC, GRAPH, SEQ) registers */ + volatile uint32_t *PRAMIN; /* instance memory */ + volatile uint32_t *PRAMHT; /* hash table */ + volatile uint32_t *PRAMFC; /* fifo context table */ + volatile uint32_t *PRAMRO; /* fifo runout table */ + volatile uint32_t *PFIFO; /* fifo control region */ + volatile uint32_t *FIFO; /* fifo channels (USER) */ + volatile uint32_t *PGRAPH; /* graphics engine */ + + int arch; /* compatible NV_ARCH_XX define */ + unsigned long fbsize; /* framebuffer size */ + void (* lock) (struct savage_chip *, int); +}; +typedef struct savage_chip savage_chip; + + +struct savage_info { + unsigned int use_colorkey; + unsigned int colorkey; /* saved xv colorkey*/ + unsigned int vidixcolorkey; /*currently used colorkey*/ + unsigned int depth; + unsigned int bpp; + unsigned int videoFlags; + unsigned int format; + unsigned int pitch; + unsigned int blendBase; + unsigned int lastKnownPitch; + unsigned int displayWidth, displayHeight; + unsigned int brightness,hue,saturation,contrast; + unsigned int src_w,src_h; + unsigned int drw_w,drw_h; /*scaled width && height*/ + unsigned int wx,wy; /*window x && y*/ + unsigned int screen_x; /*screen width*/ + unsigned int screen_y; /*screen height*/ + unsigned long buffer_size; /* size of the image buffer */ + struct savage_chip chip; /* NV architecture structure */ + void* video_base; /* virtual address of control region */ + void* control_base; /* virtual address of fb region */ + unsigned long picture_base; /* direct pointer to video picture */ + unsigned long picture_offset; /* offset of video picture in frame buffer */ +// struct savage_dma dma; /* DMA structure */ + unsigned int cur_frame; + unsigned int num_frames; /* number of buffers */ + int bps; /* bytes per line */ + void (*SavageWaitIdle) (); + void (*SavageWaitFifo) (int space); +}; +typedef struct savage_info savage_info; + + +static savage_info* info; + + +/** + * @brief Unichrome driver vidix capabilities. + */ +static vidix_capability_t savage_cap = { + "Savage/ProSavage/Twister vidix", + "Reza Jelveh <reza.jelveh@tuhh.de>", + TYPE_OUTPUT, + {0, 0, 0, 0}, + 4096, + 4096, + 4, + 4, + -1, + FLAG_UPSCALER | FLAG_DOWNSCALER, + VENDOR_S3_INC, + -1, + {0, 0, 0, 0} +}; + +struct savage_cards { + unsigned short chip_id; + unsigned short arch; +}; + + +static +unsigned int GetBlendForFourCC( int id ) +{ + switch( id ) { + case IMGFMT_YUY2: + case IMGFMT_YV12: + case IMGFMT_I420: + return 1; + case IMGFMT_Y211: + return 4; + case IMGFMT_RGB15: + return 3; + case IMGFMT_RGB16: + return 5; + default: + return 0; + } +} + +/** + * @brief list of card IDs compliant with the Unichrome driver . + */ +static struct savage_cards savage_card_ids[] = { + /*[ProSavage PN133] AGP4X VGA Controller (Twister)*/ + { PCI_CHIP_S3TWISTER_P, S3_PROSAVAGE }, + /*[ProSavage KN133] AGP4X VGA Controller (TwisterK)*/ + { PCI_CHIP_S3TWISTER_K, S3_PROSAVAGE }, + /*ProSavage DDR*/ + { PCI_CHIP_PROSAVAGE_DDR , S3_PROSAVAGE }, + /*[ProSavageDDR P4M266 K] */ + { PCI_CHIP_PROSAVAGE_DDRK , S3_PROSAVAGE }, +}; + +static void SavageSetColorOld(void) +{ + + + if( + (info->format == IMGFMT_RGB15) || + (info->format == IMGFMT_RGB16) + ) + { + OUTREG( COLOR_ADJUSTMENT_REG, 0 ); + } + else + { + /* Change 0..255 into 0..15 */ + long sat = info->saturation * 16 / 256; + double hue = info->hue * 0.017453292; + unsigned long hs1 = ((long)(sat * cos(hue))) & 0x1f; + unsigned long hs2 = ((long)(sat * sin(hue))) & 0x1f; + + OUTREG( COLOR_ADJUSTMENT_REG, + 0x80008000 | + (info->brightness + 128) | + ((info->contrast & 0xf8) << (12-7)) | + (hs1 << 16) | + (hs2 << 24) + ); + debugout( COLOR_ADJUSTMENT_REG, + 0x80008000 | + (info->brightness + 128) | + ((info->contrast & 0xf8) << (12-7)) | + (hs1 << 16) | + (hs2 << 24) + ); + + } +} + +static void SavageSetColorKeyOld(void) +{ + int red, green, blue; + + /* Here, we reset the colorkey and all the controls. */ + + red = (info->vidixcolorkey & 0x00FF0000) >> 16; + green = (info->vidixcolorkey & 0x0000FF00) >> 8; + blue = info->vidixcolorkey & 0x000000FF; + + if( !info->vidixcolorkey ) { + printf("SavageSetColorKey disabling colorkey\n"); + OUTREG( COL_CHROMA_KEY_CONTROL_REG, 0 ); + OUTREG( CHROMA_KEY_UPPER_BOUND_REG, 0 ); + OUTREG( BLEND_CONTROL_REG, 0 ); + } + else { + switch (info->depth) { + // FIXME: isnt fixed yet + case 8: + OUTREG( COL_CHROMA_KEY_CONTROL_REG, + 0x37000000 | (info->vidixcolorkey & 0xFF) ); + OUTREG( CHROMA_KEY_UPPER_BOUND_REG, + 0x00000000 | (info->vidixcolorkey & 0xFF) ); + break; + case 15: + /* 15 bpp 555 */ + red&=0x1f; + green&=0x1f; + blue&=0x1f; + OUTREG( COL_CHROMA_KEY_CONTROL_REG, + 0x05000000 | (red<<19) | (green<<11) | (blue<<3) ); + OUTREG( CHROMA_KEY_UPPER_BOUND_REG, + 0x00000000 | (red<<19) | (green<<11) | (blue<<3) ); + break; + case 16: + /* 16 bpp 565 */ + red&=0x1f; + green&=0x3f; + blue&=0x1f; + OUTREG( COL_CHROMA_KEY_CONTROL_REG, + 0x16000000 | (red<<19) | (green<<10) | (blue<<3) ); + OUTREG( CHROMA_KEY_UPPER_BOUND_REG, + 0x00020002 | (red<<19) | (green<<10) | (blue<<3) ); + break; + case 24: + /* 24 bpp 888 */ + OUTREG( COL_CHROMA_KEY_CONTROL_REG, + 0x17000000 | (red<<16) | (green<<8) | (blue) ); + OUTREG( CHROMA_KEY_UPPER_BOUND_REG, + 0x00000000 | (red<<16) | (green<<8) | (blue) ); + break; + } + + /* We use destination colorkey */ + OUTREG( BLEND_CONTROL_REG, 0x05000000 ); + } +} + + +static void SavageDisplayVideoOld(void) +{ + int vgaCRIndex, vgaCRReg, vgaIOBase; + unsigned int ssControl; + int cr92; + + + vgaIOBase = 0x3d0; + vgaCRIndex = vgaIOBase + 4; + vgaCRReg = vgaIOBase + 5; + +// if( psav->videoFourCC != id ) +// SavageStreamsOff(pScrn); + + if( !info->videoFlags & VF_STREAMS_ON ) + { + SavageStreamsOn(); + // SavageResetVideo(); + SavageSetColorOld(); + SavageSetColorKeyOld(); + } + + + + + /* Set surface format. */ + + OUTREG(SSTREAM_CONTROL_REG,GetBlendForFourCC(info->format) << 24 | info->src_w); + + debugout(SSTREAM_CONTROL_REG,GetBlendForFourCC(info->format) << 24 | info->src_w); + + /* Calculate horizontal scale factor. */ + + //FIXME: enable scaling + OUTREG(SSTREAM_STRETCH_REG, (info->src_w << 15) / info->drw_w ); +// debugout(SSTREAM_STRETCH_REG, 1 << 15); + + OUTREG(SSTREAM_LINES_REG, info->src_h ); + debugout(SSTREAM_LINES_REG, info->src_h ); + + + OUTREG(SSTREAM_VINITIAL_REG, 0 ); + debugout(SSTREAM_VINITIAL_REG, 0 ); + /* Calculate vertical scale factor. */ + +// OUTREG(SSTREAM_VSCALE_REG, 1 << 15); + OUTREG(SSTREAM_VSCALE_REG, VSCALING(info->src_h,info->drw_h) ); + debugout(SSTREAM_VSCALE_REG, VSCALING(info->src_h,info->drw_h) ); +// OUTREG(SSTREAM_VSCALE_REG, (info->src_h << 15) / info->drw_h ); + + /* Set surface location and stride. */ + + OUTREG(SSTREAM_FBADDR0_REG, info->picture_offset ); + debugout(SSTREAM_FBADDR0_REG, info->picture_offset ); + + OUTREG(SSTREAM_FBADDR1_REG, 0 ); + debugout(SSTREAM_FBADDR1_REG, 0 ); + + OUTREG(SSTREAM_STRIDE_REG, info->pitch ); + debugout(SSTREAM_STRIDE_REG, info->pitch ); + + OUTREG(SSTREAM_WINDOW_START_REG, OS_XY(info->wx, info->wy) ); + debugout(SSTREAM_WINDOW_START_REG, OS_XY(info->wx, info->wy) ); + OUTREG(SSTREAM_WINDOW_SIZE_REG, OS_WH(info->drw_w, info->drw_h) ); + debugout(SSTREAM_WINDOW_SIZE_REG, OS_WH(info->drw_w, info->drw_h) ); + + + + ssControl = 0; + + if( info->src_w > (info->drw_w << 1) ) + { + /* BUGBUG shouldn't this be >=? */ + if( info->src_w <= (info->drw_w << 2) ) + ssControl |= HDSCALE_4; + else if( info->src_w > (info->drw_w << 3) ) + ssControl |= HDSCALE_8; + else if( info->src_w > (info->drw_w << 4) ) + ssControl |= HDSCALE_16; + else if( info->src_w > (info->drw_w << 5) ) + ssControl |= HDSCALE_32; + else if( info->src_w > (info->drw_w << 6) ) + ssControl |= HDSCALE_64; + } + + ssControl |= info->src_w; + ssControl |= (1 << 24); + + //FIXME: enable scaling + OUTREG(SSTREAM_CONTROL_REG, ssControl); + debugout(SSTREAM_CONTROL_REG, ssControl); + + // FIXME: this should actually be enabled + + info->pitch = (info->pitch + 7) / 8; + VGAOUT8(vgaCRIndex, 0x92); + cr92 = VGAIN8(vgaCRReg); + VGAOUT8(vgaCRReg, (cr92 & 0x40) | (info->pitch >> 8) | 0x80); + VGAOUT8(vgaCRIndex, 0x93); + VGAOUT8(vgaCRReg, info->pitch); + OUTREG(STREAMS_FIFO_REG, 2 | 25 << 5 | 32 << 11); + + + + +} + +static void SavageInitStreamsOld() +{ + /*unsigned long jDelta;*/ + unsigned long format = 0; + + /* + * For the OLD streams engine, several of these registers + * cannot be touched unless streams are on. Seems backwards to me; + * I'd want to set 'em up, then cut 'em loose. + */ + + + /*jDelta = pScrn->displayWidth * (pScrn->bitsPerPixel + 7) / 8;*/ + switch( info->depth ) { + case 8: format = 0 << 24; break; + case 15: format = 3 << 24; break; + case 16: format = 5 << 24; break; + case 24: format = 7 << 24; break; + } +#warning enable this again + OUTREG(PSTREAM_FBSIZE_REG, + info->screen_y * info->screen_x * (info->bpp >> 3)); + + OUTREG( PSTREAM_WINDOW_START_REG, OS_XY(0,0) ); + OUTREG( PSTREAM_WINDOW_SIZE_REG, OS_WH(info->screen_x, info->screen_y) ); + OUTREG( PSTREAM_FBADDR1_REG, 0 ); + /*OUTREG( PSTREAM_STRIDE_REG, jDelta );*/ + OUTREG( PSTREAM_CONTROL_REG, format ); + OUTREG( PSTREAM_FBADDR0_REG, 0 ); + + /*OUTREG( PSTREAM_FBSIZE_REG, jDelta * pScrn->virtualY >> 3 );*/ + + OUTREG( COL_CHROMA_KEY_CONTROL_REG, 0 ); + OUTREG( SSTREAM_CONTROL_REG, 0 ); + OUTREG( CHROMA_KEY_UPPER_BOUND_REG, 0 ); + OUTREG( SSTREAM_STRETCH_REG, 0 ); + OUTREG( COLOR_ADJUSTMENT_REG, 0 ); + OUTREG( BLEND_CONTROL_REG, 1 << 24 ); + OUTREG( DOUBLE_BUFFER_REG, 0 ); + OUTREG( SSTREAM_FBADDR0_REG, 0 ); + OUTREG( SSTREAM_FBADDR1_REG, 0 ); + OUTREG( SSTREAM_FBADDR2_REG, 0 ); + OUTREG( SSTREAM_FBSIZE_REG, 0 ); + OUTREG( SSTREAM_STRIDE_REG, 0 ); + OUTREG( SSTREAM_VSCALE_REG, 0 ); + OUTREG( SSTREAM_LINES_REG, 0 ); + OUTREG( SSTREAM_VINITIAL_REG, 0 ); +#warning is this needed? + OUTREG( SSTREAM_WINDOW_START_REG, OS_XY(0xfffe, 0xfffe) ); + OUTREG( SSTREAM_WINDOW_SIZE_REG, OS_WH(10,2) ); + +} + +static void SavageStreamsOn() +{ + unsigned char jStreamsControl; + unsigned short vgaCRIndex = 0x3d0 + 4; + unsigned short vgaCRReg = 0x3d0 + 5; + +// xf86ErrorFVerb(STREAMS_TRACE, "SavageStreamsOn\n" ); + + /* Sequence stolen from streams.c in M7 NT driver */ + + + enable_app_io (); + + /* Unlock extended registers. */ + + /* FIXME: it looks like mmaped io is broken with vgaout16 */ + VGAOUT16(vgaCRIndex, 0x4838 ); + VGAOUT16(vgaCRIndex, 0xa039); + VGAOUT16(0x3c4, 0x0608); + + + + VGAOUT8( vgaCRIndex, EXT_MISC_CTRL2 ); + + if( S3_SAVAGE_MOBILE_SERIES(info->chip.arch) ) + { +// SavageInitStreamsNew( pScrn ); + + jStreamsControl = VGAIN8( vgaCRReg ) | ENABLE_STREAM1; + + /* Wait for VBLANK. */ + VerticalRetraceWait(); + /* Fire up streams! */ + VGAOUT16( vgaCRIndex, (jStreamsControl << 8) | EXT_MISC_CTRL2 ); + /* These values specify brightness, contrast, saturation and hue. */ + OUTREG( SEC_STREAM_COLOR_CONVERT1, 0x0000C892 ); + OUTREG( SEC_STREAM_COLOR_CONVERT2, 0x00039F9A ); + OUTREG( SEC_STREAM_COLOR_CONVERT3, 0x01F1547E ); + } + else if (info->chip.arch == S3_SAVAGE2000) + { +// SavageInitStreams2000( pScrn ); + + jStreamsControl = VGAIN8( vgaCRReg ) | ENABLE_STREAM1; + + /* Wait for VBLANK. */ + VerticalRetraceWait(); + /* Fire up streams! */ + VGAOUT16( vgaCRIndex, (jStreamsControl << 8) | EXT_MISC_CTRL2 ); + /* These values specify brightness, contrast, saturation and hue. */ + OUTREG( SEC_STREAM_COLOR_CONVERT0_2000, 0x0000C892 ); + OUTREG( SEC_STREAM_COLOR_CONVERT1_2000, 0x00033400 ); + OUTREG( SEC_STREAM_COLOR_CONVERT2_2000, 0x000001CF ); + OUTREG( SEC_STREAM_COLOR_CONVERT3_2000, 0x01F1547E ); + } + else + { + jStreamsControl = VGAIN8( vgaCRReg ) | ENABLE_STREAMS_OLD; + + /* Wait for VBLANK. */ + + VerticalRetraceWait(); + + /* Fire up streams! */ + + VGAOUT16( vgaCRIndex, (jStreamsControl << 8) | EXT_MISC_CTRL2 ); + + SavageInitStreamsOld( ); + } + + /* Wait for VBLANK. */ + + VerticalRetraceWait(); + + /* Turn on secondary stream TV flicker filter, once we support TV. */ + + /* SR70 |= 0x10 */ + + info->videoFlags |= VF_STREAMS_ON; + +} + + + + +static void savage_getscreenproperties(struct savage_info *info){ + unsigned char bpp=0; + /* uint32_t width=0; unused */ + + uint32_t vgaIOBase, vgaCRIndex, vgaCRReg; + + vgaIOBase = 0x3d0; + vgaCRIndex = vgaIOBase + 4; + vgaCRReg = vgaIOBase + 5; + + + /* a little reversed from x driver source code */ + VGAOUT8(vgaCRIndex, 0x67); + bpp = VGAIN8(vgaCRReg); + + + switch (bpp&0xf0) { + case 0x00: + case 0x10: + info->depth=8; + info->bpp=8; + break; + case 0x20: + case 0x30: + info->depth=15; + info->bpp=16; + break; + case 0x40: + case 0x50: + info->depth=16; + info->bpp=16; + break; + case 0x70: + case 0xd0: + info->depth=24; + info->bpp=32; + break; + + + } + + + VGAOUT8(vgaCRIndex, 0x1); + info->screen_x = (1 + VGAIN8(vgaCRReg)) <<3; + /*get screen height*/ + /* get first 8 bits in VT_DISPLAY_END*/ + VGAOUT8(0x03D4, 0x12); + info->screen_y = VGAIN8(0x03D5); + VGAOUT8(0x03D4,0x07); + /* get 9th bit in CRTC_OVERFLOW*/ + info->screen_y |= (VGAIN8(0x03D5) &0x02)<<7; + /* and the 10th in CRTC_OVERFLOW*/ + info->screen_y |=(VGAIN8(0x03D5) &0x40)<<3; + ++info->screen_y; + + printf("screen_x = %d, screen_y = %d, bpp = %d\n",info->screen_x,info->screen_y,info->bpp); +} + + +static void SavageStreamsOff() +{ + unsigned char jStreamsControl; + unsigned short vgaCRIndex = 0x3d0 + 4; + unsigned short vgaCRReg = 0x3d0 + 5; + + + /* Unlock extended registers. */ + + VGAOUT16(vgaCRIndex, 0x4838); + VGAOUT16(vgaCRIndex, 0xa039); + VGAOUT16(0x3c4, 0x0608); + + VGAOUT8( vgaCRIndex, EXT_MISC_CTRL2 ); + if( S3_SAVAGE_MOBILE_SERIES(info->chip.arch) || + (info->chip.arch == S3_SUPERSAVAGE) || + (info->chip.arch == S3_SAVAGE2000) ) + jStreamsControl = VGAIN8( vgaCRReg ) & NO_STREAMS; + else + jStreamsControl = VGAIN8( vgaCRReg ) & NO_STREAMS_OLD; + + /* Wait for VBLANK. */ + + VerticalRetraceWait(); + + /* Kill streams. */ + + VGAOUT16(vgaCRIndex, (jStreamsControl << 8) | EXT_MISC_CTRL2 ); + + VGAOUT16(vgaCRIndex, 0x0093 ); + VGAOUT8( vgaCRIndex, 0x92 ); + VGAOUT8( vgaCRReg, VGAIN8(vgaCRReg) & 0x40 ); + + info->videoFlags &= ~VF_STREAMS_ON; +} + + +/** + * @brief Check age of driver. + * + * @return vidix version number. + */ +unsigned int +vixGetVersion (void) +{ + return (VIDIX_VERSION); +} + +/** + * @brief Find chip index in Unichrome compliant devices list. + * + * @param chip_id PCI device ID. + * + * @returns index position in savage_card_ids if successful. + * -1 if chip_id is not a compliant chipset ID. + */ + +static int find_chip(unsigned chip_id){ + unsigned i; + for(i = 0;i < sizeof(savage_card_ids)/sizeof(struct savage_cards);i++) + { + if(chip_id == savage_card_ids[i].chip_id)return i; + } + return -1; +} + +/** + * @brief Probe hardware to find some useable chipset. + * + * @param verbose specifies verbose level. + * @param force specifies force mode : driver should ignore + * device_id (danger but useful for new devices) + * + * @returns 0 if it can handle something in PC. + * a negative error code otherwise. + */ + +int vixProbe(int verbose, int force){ + pciinfo_t lst[MAX_PCI_DEVICES]; + unsigned i,num_pci; + int err; + + if (force) + printf("[savage_vid]: warning: forcing not supported yet!\n"); + err = pci_scan(lst,&num_pci); + if(err){ + printf("[savage_vid] Error occurred during pci scan: %s\n",strerror(err)); + return err; + } + else { + err = ENXIO; + for(i=0; i < num_pci; i++){ + if(lst[i].vendor == VENDOR_S3_INC) { + int idx; + const char *dname; + idx = find_chip(lst[i].device); + if(idx == -1) + continue; + dname = pci_device_name(lst[i].vendor, lst[i].device); + dname = dname ? dname : "Unknown chip"; + printf("[savage_vid] Found chip: %s\n", dname); + savage_cap.device_id = lst[i].device; + err = 0; + memcpy(&pci_info, &lst[i], sizeof(pciinfo_t)); + break; + } + } + } + if(err && verbose) printf("[savage_vid] Can't find chip\n"); + return err; +} + +/** + * @brief Initializes driver. + * + * @returns 0 if ok. + * a negative error code otherwise. + */ +int +vixInit (const char *args) +{ + int mtrr; + unsigned char config1, /* m, n, n1, n2, sr8, cr3f, cr66 = 0, */ tmp; + + static unsigned char RamSavage3D[] = { 8, 4, 4, 2 }; + static unsigned char RamSavage4[] = { 2, 4, 8, 12, 16, 32, 64, 32 }; + static unsigned char RamSavageMX[] = { 2, 8, 4, 16, 8, 16, 4, 16 }; + static unsigned char RamSavageNB[] = { 0, 2, 4, 8, 16, 32, 16, 2 }; + + int videoRam /*, videoRambytes */; + + uint32_t vgaIOBase, vgaCRIndex, vgaCRReg ; + + unsigned char val; + + vgaIOBase = 0x3d0; + vgaCRIndex = vgaIOBase + 4; + vgaCRReg = vgaIOBase + 5; + + fprintf(stderr, "vixInit enter \n"); +// //getc(stdin); + + info = (savage_info*)calloc(1,sizeof(savage_info)); + + + /* need this if we want direct outb and inb access? */ + enable_app_io (); + + /* 12mb + 32kb ? */ + /* allocate some space for control registers */ + info->chip.arch = savage_card_ids[find_chip(pci_info.device)].arch; + + if (info->chip.arch == S3_SAVAGE3D) { + info->control_base = map_phys_mem(pci_info.base0+SAVAGE_NEWMMIO_REGBASE_S3, SAVAGE_NEWMMIO_REGSIZE); + } + else { + info->control_base = map_phys_mem(pci_info.base0+SAVAGE_NEWMMIO_REGBASE_S4, SAVAGE_NEWMMIO_REGSIZE); + } + +// info->chip.PCIO = (uint8_t *) (info->control_base + SAVAGE_NEWMMIO_VGABASE); + + // FIXME: enable mmio? + val = VGAIN8 (0x3c3); + VGAOUT8 (0x3c3, val | 0x01); + val = VGAIN8 (0x3cc); + VGAOUT8 (0x3c2, val | 0x01); + + if (info->chip.arch >= S3_SAVAGE4) + { + VGAOUT8 (0x3d4, 0x40); + val = VGAIN8 (0x3d5); + VGAOUT8 (0x3d5, val | 1); + } + + + + /* unprotect CRTC[0-7] */ + VGAOUT8(vgaCRIndex, 0x11); + tmp = VGAIN8(vgaCRReg); +// printf("$########## tmp = %d\n",tmp); + VGAOUT8(vgaCRReg, tmp & 0x7f); + + + /* unlock extended regs */ + VGAOUT16(vgaCRIndex, 0x4838); + VGAOUT16(vgaCRIndex, 0xa039); + VGAOUT16(0x3c4, 0x0608); + + VGAOUT8(vgaCRIndex, 0x40); + tmp = VGAIN8(vgaCRReg); + VGAOUT8(vgaCRReg, tmp & ~0x01); + + /* unlock sys regs */ + VGAOUT8(vgaCRIndex, 0x38); + VGAOUT8(vgaCRReg, 0x48); + + /* Unlock system registers. */ + VGAOUT16(vgaCRIndex, 0x4838); + + /* Next go on to detect amount of installed ram */ + + VGAOUT8(vgaCRIndex, 0x36); /* for register CR36 (CONFG_REG1), */ + config1 = VGAIN8(vgaCRReg); /* get amount of vram installed */ + + + switch( info->chip.arch ) { + case S3_SAVAGE3D: + videoRam = RamSavage3D[ (config1 & 0xC0) >> 6 ] * 1024; + break; + + case S3_SAVAGE4: + /* + * The Savage4 has one ugly special case to consider. On + * systems with 4 banks of 2Mx32 SDRAM, the BIOS says 4MB + * when it really means 8MB. Why do it the same when you + * can do it different... + */ + VGAOUT8(0x3d4, 0x68); /* memory control 1 */ + if( (VGAIN8(0x3d5) & 0xC0) == (0x01 << 6) ) + RamSavage4[1] = 8; + + /*FALLTHROUGH*/ + + case S3_SAVAGE2000: + videoRam = RamSavage4[ (config1 & 0xE0) >> 5 ] * 1024; + break; + + case S3_SAVAGE_MX: + videoRam = RamSavageMX[ (config1 & 0x0E) >> 1 ] * 1024; + break; + + case S3_PROSAVAGE: + videoRam = RamSavageNB[ (config1 & 0xE0) >> 5 ] * 1024; + break; + + default: + /* How did we get here? */ + videoRam = 0; + break; + } + + + printf("###### videoRam = %d\n",videoRam); + info->chip.fbsize = videoRam * 1024; + + + /* reset graphics engine to avoid memory corruption */ +#if 0 + VGAOUT8 (0x3d4, 0x66); + cr66 = VGAIN8 (0x3d5); + VGAOUT8 (0x3d5, cr66 | 0x02); + udelay (10000); + + VGAOUT8 (0x3d4, 0x66); + VGAOUT8 (0x3d5, cr66 & ~0x02); /* clear reset flag */ +#endif + /* udelay (10000); */ + + /* This maps framebuffer @6MB, thus 2MB are left for video. */ + if (info->chip.arch == S3_SAVAGE3D) { + info->video_base = map_phys_mem(pci_info.base0, info->chip.fbsize); + info->picture_offset = 1024*768* 4 * ((info->chip.fbsize > 4194304)?2:1); + } + else { + info->video_base = map_phys_mem(pci_info.base1, info->chip.fbsize); + info->picture_offset = info->chip.fbsize - FRAMEBUFFER_SIZE; +// info->picture_offset = 1024*1024* 4 * 2; + } + if ( info->video_base < 0 ){ + printf("errno = %s\n", strerror(errno)); + return -1; + } + + + info->picture_base = (uint32_t) info->video_base + info->picture_offset; + + if ( info->chip.arch == S3_SAVAGE3D ){ + mtrr = mtrr_set_type(pci_info.base0, info->chip.fbsize, MTRR_TYPE_WRCOMB); + } + else{ + mtrr = mtrr_set_type(pci_info.base1, info->chip.fbsize, MTRR_TYPE_WRCOMB); + } + + if (mtrr!= 0) + printf("[savage_vid] unable to setup MTRR: %s\n", strerror(mtrr)); + else + printf("[savage_vid] MTRR set up\n"); + + /* This may trash your screen for resolutions greater than 1024x768, sorry. */ + + + savage_getscreenproperties(info); +// return -1; + info->videoFlags = 0; + + SavageStreamsOn(); + //getc(stdin); + //FIXME ADD + return 0; +} + +/** + * @brief Destroys driver. + */ +void +vixDestroy (void) +{ + unmap_phys_mem(info->video_base, info->chip.fbsize); + unmap_phys_mem(info->control_base, SAVAGE_NEWMMIO_REGSIZE); + //FIXME ADD +} + +/** + * @brief Get chipset's hardware capabilities. + * + * @param to Pointer to the vidix_capability_t structure to be filled. + * + * @returns 0. + */ +int +vixGetCapability (vidix_capability_t * to) +{ + memcpy (to, &savage_cap, sizeof (vidix_capability_t)); + return 0; +} + +/** + * @brief Report if the video FourCC is supported by hardware. + * + * @param fourcc input image format. + * + * @returns 1 if the fourcc is supported. + * 0 otherwise. + */ +static int +is_supported_fourcc (uint32_t fourcc) +{ + switch (fourcc) + { +//FIXME: YV12 isnt working properly yet +// case IMGFMT_YV12: +// case IMGFMT_I420: + case IMGFMT_UYVY: + case IMGFMT_YVYU: + case IMGFMT_YUY2: + case IMGFMT_RGB15: + case IMGFMT_RGB16: +// case IMGFMT_BGR32: + return 1; + default: + return 0; + } +} + +/** + * @brief Try to configure video memory for given fourcc. + * + * @param to Pointer to the vidix_fourcc_t structure to be filled. + * + * @returns 0 if ok. + * errno otherwise. + */ +int +vixQueryFourcc (vidix_fourcc_t * to) +{ + if (is_supported_fourcc (to->fourcc)) + { + to->depth = VID_DEPTH_1BPP | VID_DEPTH_2BPP | + VID_DEPTH_4BPP | VID_DEPTH_8BPP | + VID_DEPTH_12BPP | VID_DEPTH_15BPP | + VID_DEPTH_16BPP | VID_DEPTH_24BPP | VID_DEPTH_32BPP; + to->flags = VID_CAP_EXPAND | VID_CAP_SHRINK | VID_CAP_COLORKEY; + return 0; + } + else + to->depth = to->flags = 0; + + return ENOSYS; +} + +/** + * @brief Get the GrKeys + * + * @param grkey Pointer to the vidix_grkey_t structure to be filled by driver. + * + * @return 0. + */ +/*int +vixGetGrKeys (vidix_grkey_t * grkey) +{ + +// if(info->d_width && info->d_height)savage_overlay_start(info,0); + + return (0); +} + * */ + +/** + * @brief Set the GrKeys + * + * @param grkey Colorkey to be set. + * + * @return 0. + */ +int +vixSetGrKeys (const vidix_grkey_t * grkey) +{ + if (grkey->ckey.op == CKEY_FALSE) + { + info->use_colorkey = 0; + info->vidixcolorkey=0; + printf("[savage_vid] colorkeying disabled\n"); + } + else { + info->use_colorkey = 1; + info->vidixcolorkey = ((grkey->ckey.red<<16)|(grkey->ckey.green<<8)|grkey->ckey.blue); + + printf("[savage_vid] set colorkey 0x%x\n",info->vidixcolorkey); + } + //FIXME: freezes if streams arent enabled + SavageSetColorKeyOld(); + return (0); +} + +/** + * @brief Unichrome driver equalizer capabilities. + */ +vidix_video_eq_t equal = { + VEQ_CAP_BRIGHTNESS | VEQ_CAP_SATURATION | VEQ_CAP_HUE, + 300, 100, 0, 0, 0, 0, 0, 0 +}; + + +/** + * @brief Get the equalizer capabilities. + * + * @param eq Pointer to the vidix_video_eq_t structure to be filled by driver. + * + * @return 0. + */ +int +vixPlaybackGetEq (vidix_video_eq_t * eq) +{ + memcpy (eq, &equal, sizeof (vidix_video_eq_t)); + return 0; +} + +/** + * @brief Set the equalizer capabilities for color correction + * + * @param eq equalizer capabilities to be set. + * + * @return 0. + */ +int +vixPlaybackSetEq (const vidix_video_eq_t * eq) +{ + return 0; +} + +/** + * @brief Y, U, V offsets. + */ +/* static int YOffs, UOffs, VOffs; */ + +/** + * @brief Configure driver for playback. Driver should prepare BES. + * + * @param info configuration description for playback. + * + * @returns 0 in case of success. + * -1 otherwise. + */ +int +vixConfigPlayback (vidix_playback_t * vinfo) +{ + int uv_size, swap_uv; + unsigned int i; +#if 0 + int extfifo_on; + int srcPitch,srcPitch2; + + /* Overlay register settings */ + uint32_t win_start, win_end; + uint32_t zoom, mini; + uint32_t dcount, falign, qwfetch; + uint32_t y_start, u_start, v_start; + uint32_t v_ctrl, fifo_ctrl; +#endif + + if (!is_supported_fourcc (vinfo->fourcc)) + return -1; + + + + info->src_w = vinfo->src.w; + info->src_h = vinfo->src.h; + + info->drw_w = vinfo->dest.w; + info->drw_h = vinfo->dest.h; + + info->wx = vinfo->dest.x; + info->wy = vinfo->dest.y; + info->format = vinfo->fourcc; + + info->lastKnownPitch = 0; + info->brightness = 0; + info->contrast = 128; + info->saturation = 128; + info->hue = 0; + + + vinfo->dga_addr=(void*)(info->picture_base); + + + vinfo->offset.y = 0; + vinfo->offset.v = 0; + vinfo->offset.u = 0; + + vinfo->dest.pitch.y = 32; + vinfo->dest.pitch.u = 32; + vinfo->dest.pitch.v = 32; + // vinfo->dest.pitch.u = 0; + // vinfo->dest.pitch.v = 0; + + + info->pitch = ((info->src_w << 1) + 15) & ~15; + + swap_uv = 0; + switch (vinfo->fourcc) + { + case IMGFMT_YUY2: + case IMGFMT_UYVY: + + info->pitch = ((info->src_w << 1) + (vinfo->dest.pitch.y-1)) & ~(vinfo->dest.pitch.y-1); + + info->pitch = info->src_w << 1; + info->pitch = ALIGN_TO (info->src_w << 1, 32); + uv_size = 0; + break; + case IMGFMT_YV12: + swap_uv = 1; + + + + /* + srcPitch = (info->src_w + 3) & ~3; + vinfo->offset.u = srcPitch * info->src_h; + srcPitch2 = ((info->src_w >> 1) + 3) & ~3; + vinfo->offset.v = (srcPitch2 * (info->src_h >> 1)) + vinfo->offset.v; + + vinfo->dest.pitch.y=srcPitch ; + vinfo->dest.pitch.v=srcPitch2 ; + vinfo->dest.pitch.u=srcPitch2 ; + */ + + + info->pitch = ALIGN_TO (info->src_w, 32); + uv_size = (info->pitch >> 1) * (info->src_h >> 1); + + vinfo->offset.y = 0; + vinfo->offset.v = vinfo->offset.y + info->pitch * info->src_h; + vinfo->offset.u = vinfo->offset.v + uv_size; + vinfo->frame_size = vinfo->offset.u + uv_size; +/* YOffs = info->offset.y; + UOffs = (swap_uv ? vinfo->offset.v : vinfo->offset.u); + VOffs = (swap_uv ? vinfo->offset.u : vinfo->offset.v); + */ +// vinfo->offset.y = info->src_w; +// vinfo->offset.v = vinfo->offset.y + info->src_w /2 * info->src_h; +// vinfo->offset.u = vinfo->offset.v + (info->src_w >> 1) * (info->src_h >> 1) ; + + break; + } + info->pitch |= ((info->pitch >> 1) << 16); + + vinfo->frame_size = info->pitch * info->src_h; + + printf("$#### destination pitch = %u\n", info->pitch&0xffff); + + + + + info->buffer_size = vinfo->frame_size; + info->num_frames = vinfo->num_frames= (info->chip.fbsize - info->picture_offset)/vinfo->frame_size; + if(vinfo->num_frames > MAX_FRAMES)vinfo->num_frames = MAX_FRAMES; +// vinfo->num_frames = 1; +// printf("[nvidia_vid] Number of frames %i\n",vinfo->num_frames); + for(i=0;i <vinfo->num_frames;i++)vinfo->offsets[i] = vinfo->frame_size*i; + + return 0; +} + +/** + * @brief Set playback on : driver should activate BES on this call. + * + * @return 0. + */ +int +vixPlaybackOn (void) +{ + // FIXME: enable + SavageDisplayVideoOld(); +//FIXME ADD + return 0; +} + +/** + * @brief Set playback off : driver should deactivate BES on this call. + * + * @return 0. + */ +int +vixPlaybackOff (void) +{ + // otherwise we wont disable streams properly in new xorg + // FIXME: shouldnt this be enabled? +// SavageStreamsOn(); + SavageStreamsOff(); +// info->vidixcolorkey=0x0; + +// OUTREG( SSTREAM_WINDOW_START_REG, OS_XY(0xfffe, 0xfffe) ); +// SavageSetColorKeyOld(); +//FIXME ADD + return 0; +} + +/** + * @brief Driver should prepare and activate corresponded frame. + * + * @param frame the frame index. + * + * @return 0. + * + * @note This function is used only for double and triple buffering + * and never used for single buffering playback. + */ +#if 0 +int +vixPlaybackFrameSelect (unsigned int frame) +{ +////FIXME ADD +// savage_overlay_start(info, frame); + //if (info->num_frames >= 1) +// info->cur_frame = frame//(frame+1)%info->num_frames; +// +// savage4_waitidle(info); + + printf("vixPlaybackFrameSelect Leave\n" ); + // FIXME: does this work to avoid tearing? +// VerticalRetraceWait(); + + return 0; +} + +#endif + + + +void debugout(unsigned int addr, unsigned int val){ + return ; + switch ( addr ){ + case PSTREAM_CONTROL_REG: + fprintf(stderr,"PSTREAM_CONTROL_REG"); + break; + case COL_CHROMA_KEY_CONTROL_REG: + fprintf(stderr,"COL_CHROMA_KEY_CONTROL_REG"); + break; + case SSTREAM_CONTROL_REG: + fprintf(stderr,"SSTREAM_CONTROL_REG"); + break; + case CHROMA_KEY_UPPER_BOUND_REG: + fprintf(stderr,"CHROMA_KEY_UPPER_BOUND_REG"); + break; + case SSTREAM_STRETCH_REG: + fprintf(stderr,"SSTREAM_STRETCH_REG"); + break; + case COLOR_ADJUSTMENT_REG: + fprintf(stderr,"COLOR_ADJUSTMENT_REG"); + break; + case BLEND_CONTROL_REG: + fprintf(stderr,"BLEND_CONTROL_REG"); + break; + case PSTREAM_FBADDR0_REG: + fprintf(stderr,"PSTREAM_FBADDR0_REG"); + break; + case PSTREAM_FBADDR1_REG: + fprintf(stderr,"PSTREAM_FBADDR1_REG"); + break; + case PSTREAM_STRIDE_REG: + fprintf(stderr,"PSTREAM_STRIDE_REG"); + break; + case DOUBLE_BUFFER_REG: + fprintf(stderr,"DOUBLE_BUFFER_REG"); + break; + case SSTREAM_FBADDR0_REG: + fprintf(stderr,"SSTREAM_FBADDR0_REG"); + break; + case SSTREAM_FBADDR1_REG: + fprintf(stderr,"SSTREAM_FBADDR1_REG"); + break; + case SSTREAM_STRIDE_REG: + fprintf(stderr,"SSTREAM_STRIDE_REG"); + break; + case SSTREAM_VSCALE_REG: + fprintf(stderr,"SSTREAM_VSCALE_REG"); + break; + case SSTREAM_VINITIAL_REG: + fprintf(stderr,"SSTREAM_VINITIAL_REG"); + break; + case SSTREAM_LINES_REG: + fprintf(stderr,"SSTREAM_LINES_REG"); + break; + case STREAMS_FIFO_REG: + fprintf(stderr,"STREAMS_FIFO_REG"); + break; + case PSTREAM_WINDOW_START_REG: + fprintf(stderr,"PSTREAM_WINDOW_START_REG"); + break; + case PSTREAM_WINDOW_SIZE_REG: + fprintf(stderr,"PSTREAM_WINDOW_SIZE_REG"); + break; + case SSTREAM_WINDOW_START_REG: + fprintf(stderr,"SSTREAM_WINDOW_START_REG"); + break; + case SSTREAM_WINDOW_SIZE_REG: + fprintf(stderr,"SSTREAM_WINDOW_SIZE_REG"); + break; + case FIFO_CONTROL: + fprintf(stderr,"FIFO_CONTROL"); + break; + case PSTREAM_FBSIZE_REG: + fprintf(stderr,"PSTREAM_FBSIZE_REG"); + break; + case SSTREAM_FBSIZE_REG: + fprintf(stderr,"SSTREAM_FBSIZE_REG"); + break; + case SSTREAM_FBADDR2_REG: + fprintf(stderr,"SSTREAM_FBADDR2_REG"); + break; + + } + fprintf(stderr,":\t\t 0x%08X = %u\n",val,val); +} + + + diff --git a/contrib/vidix/drivers/sis_bridge.c b/contrib/vidix/drivers/sis_bridge.c new file mode 100644 index 000000000..f6916ae87 --- /dev/null +++ b/contrib/vidix/drivers/sis_bridge.c @@ -0,0 +1,835 @@ +/** + Video bridge detection for SiS 300 and 310/325 series chips. + + Copyright 2003 Jake Page, Sugar Media. + + Based on SiS Xv driver: + Copyright 2002-2003 by Thomas Winischhofer, Vienna, Austria. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +**/ + +#include <stdio.h> +#include <stdlib.h> +#include <unistd.h> + +#include "libdha.h" + +#include "sis_regs.h" +#include "sis_defs.h" + +void sis_init_video_bridge(void); + +static void sis_ddc2_delay(unsigned short delaytime) +{ + unsigned short i; + int temp; + + for (i = 0; i < delaytime; i++) { + inSISIDXREG(SISSR, 0x05, temp); + } +} + + +static int sis_do_sense(int tempbl, int tempbh, int tempcl, int tempch) +{ + int temp; + + outSISIDXREG(SISPART4, 0x11, tempbl); + temp = tempbh | tempcl; + setSISIDXREG(SISPART4, 0x10, 0xe0, temp); + //usleep(200000); + sis_ddc2_delay(0x1000); + tempch &= 0x7f; + inSISIDXREG(SISPART4, 0x03, temp); + temp ^= 0x0e; + temp &= tempch; + return (temp == tempch); +} + + +/* sense connected devices on 30x bridge */ +static void sis_sense_30x() +{ + unsigned char backupP4_0d, backupP2_00, biosflag; + unsigned char testsvhs_tempbl, testsvhs_tempbh; + unsigned char testsvhs_tempcl, testsvhs_tempch; + unsigned char testcvbs_tempbl, testcvbs_tempbh; + unsigned char testcvbs_tempcl, testcvbs_tempch; + unsigned char testvga2_tempbl, testvga2_tempbh; + unsigned char testvga2_tempcl, testvga2_tempch; + int myflag, result = 0, i, j, haveresult; +#if 0 + unsigned short temp; +#endif + + inSISIDXREG(SISPART4, 0x0d, backupP4_0d); + outSISIDXREG(SISPART4, 0x0d, (backupP4_0d | 0x04)); + + inSISIDXREG(SISPART2, 0x00, backupP2_00); + outSISIDXREG(SISPART2, 0x00, (backupP2_00 | 0x1c)); + + sis_do_sense(0, 0, 0, 0); + + if ((sis_vga_engine == SIS_315_VGA) || + (sis_device_id == DEVICE_SIS_300)) { +#if 0 + if (0 /*pSiS->sishw_ext.UseROM */ ) { + if (sis_vga_engine == SIS_300_VGA) + temp = 0xfe; + else { + temp = 0xf3; + if (sis_device_id == DEVICE_SIS_330) + temp = 0x11b; + } + if (pSiS->BIOS[temp] & 0x08) { + if (sis_verbose > 1) { + printf + ("[SiS] SiS30x: Video bridge has DVI-I TMDS/VGA combo connector\n"); + } + orSISIDXREG(SISCR, 0x32, 0x80); + } else { + andSISIDXREG(SISCR, 0x32, 0x7f); + } + } +#endif + } + + if (sis_vga_engine == SIS_300_VGA) { + if (0 /*pSiS->sishw_ext.UseROM */ ) { +#if 0 + testvga2_tempbh = pSiS->BIOS[0xf9]; + testvga2_tempbl = pSiS->BIOS[0xf8]; + testsvhs_tempbh = pSiS->BIOS[0xfb]; + testsvhs_tempbl = pSiS->BIOS[0xfa]; + testcvbs_tempbh = pSiS->BIOS[0xfd]; + testcvbs_tempbl = pSiS->BIOS[0xfc]; + biosflag = pSiS->BIOS[0xfe]; +#endif + } else { + testvga2_tempbh = 0x00; + testvga2_tempbl = 0xd1; + testsvhs_tempbh = 0x00; + testsvhs_tempbl = 0xb9; + testcvbs_tempbh = 0x00; + testcvbs_tempbl = 0xb3; + biosflag = 0; + } + if (sis_vbflags & (VB_301B | VB_302B | VB_301LV | VB_302LV)) { + testvga2_tempbh = 0x01; + testvga2_tempbl = 0x90; + testsvhs_tempbh = 0x01; + testsvhs_tempbl = 0x6b; + testcvbs_tempbh = 0x01; + testcvbs_tempbl = 0x74; + } + inSISIDXREG(SISPART4, 0x01, myflag); + if (myflag & 0x04) { + testvga2_tempbh = 0x00; + testvga2_tempbl = 0xfd; + testsvhs_tempbh = 0x00; + testsvhs_tempbl = 0xdd; + testcvbs_tempbh = 0x00; + testcvbs_tempbl = 0xee; + } + testvga2_tempch = 0x0e; + testvga2_tempcl = 0x08; + testsvhs_tempch = 0x06; + testsvhs_tempcl = 0x04; + testcvbs_tempch = 0x08; + testcvbs_tempcl = 0x04; + + if (sis_device_id == DEVICE_SIS_300) { + inSISIDXREG(SISSR, 0x3b, myflag); + if (!(myflag & 0x01)) { + testvga2_tempbh = 0x00; + testvga2_tempbl = 0x00; + testvga2_tempch = 0x00; + testvga2_tempcl = 0x00; + } + } + } else { + if (0 /*pSiS->sishw_ext.UseROM */ ) { +#if 0 + if (sis_device_id == DEVICE_SIS_330) { + testvga2_tempbh = pSiS->BIOS[0xe6]; + testvga2_tempbl = pSiS->BIOS[0xe5]; + testsvhs_tempbh = pSiS->BIOS[0xe8]; + testsvhs_tempbl = pSiS->BIOS[0xe7]; + testcvbs_tempbh = pSiS->BIOS[0xea]; + testcvbs_tempbl = pSiS->BIOS[0xe9]; + biosflag = pSiS->BIOS[0x11b]; + } else { + testvga2_tempbh = pSiS->BIOS[0xbe]; + testvga2_tempbl = pSiS->BIOS[0xbd]; + testsvhs_tempbh = pSiS->BIOS[0xc0]; + testsvhs_tempbl = pSiS->BIOS[0xbf]; + testcvbs_tempbh = pSiS->BIOS[0xc2]; + testcvbs_tempbl = pSiS->BIOS[0xc1]; + biosflag = pSiS->BIOS[0xf3]; + } +#endif + } else { + testvga2_tempbh = 0x00; + testvga2_tempbl = 0xd1; + testsvhs_tempbh = 0x00; + testsvhs_tempbl = 0xb9; + testcvbs_tempbh = 0x00; + testcvbs_tempbl = 0xb3; + biosflag = 0; + } + + if (sis_vbflags & (VB_301B | VB_302B | VB_301LV | VB_302LV)) { + if (0 /*pSiS->sishw_ext.UseROM */ ) { +#if 0 + if (sis_device_id == DEVICE_SIS_330) { + testvga2_tempbh = pSiS->BIOS[0xec]; + testvga2_tempbl = pSiS->BIOS[0xeb]; + testsvhs_tempbh = pSiS->BIOS[0xee]; + testsvhs_tempbl = pSiS->BIOS[0xed]; + testcvbs_tempbh = pSiS->BIOS[0xf0]; + testcvbs_tempbl = pSiS->BIOS[0xef]; + } else { + testvga2_tempbh = pSiS->BIOS[0xc4]; + testvga2_tempbl = pSiS->BIOS[0xc3]; + testsvhs_tempbh = pSiS->BIOS[0xc6]; + testsvhs_tempbl = pSiS->BIOS[0xc5]; + testcvbs_tempbh = pSiS->BIOS[0xc8]; + testcvbs_tempbl = pSiS->BIOS[0xc7]; + } +#endif + } else { + if (sis_vbflags & (VB_301B | VB_302B)) { + testvga2_tempbh = 0x01; + testvga2_tempbl = 0x90; + testsvhs_tempbh = 0x01; + testsvhs_tempbl = 0x6b; + testcvbs_tempbh = 0x01; + testcvbs_tempbl = 0x74; + } else { + testvga2_tempbh = 0x00; + testvga2_tempbl = 0x00; + testsvhs_tempbh = 0x02; + testsvhs_tempbl = 0x00; + testcvbs_tempbh = 0x01; + testcvbs_tempbl = 0x00; + } + } + } + if (sis_vbflags & (VB_301 | VB_301B | VB_302B)) { + inSISIDXREG(SISPART4, 0x01, myflag); + if (myflag & 0x04) { + testvga2_tempbh = 0x00; + testvga2_tempbl = 0xfd; + testsvhs_tempbh = 0x00; + testsvhs_tempbl = 0xdd; + testcvbs_tempbh = 0x00; + testcvbs_tempbl = 0xee; + } + } + if (sis_vbflags & (VB_301LV | VB_302LV)) { + /* TW: No VGA2 or SCART on LV bridges */ + testvga2_tempbh = 0x00; + testvga2_tempbl = 0x00; + testvga2_tempch = 0x00; + testvga2_tempcl = 0x00; + testsvhs_tempch = 0x04; + testsvhs_tempcl = 0x08; + testcvbs_tempch = 0x08; + testcvbs_tempcl = 0x08; + } else { + testvga2_tempch = 0x0e; + testvga2_tempcl = 0x08; + testsvhs_tempch = 0x06; + testsvhs_tempcl = 0x04; + testcvbs_tempch = 0x08; + testcvbs_tempcl = 0x04; + } + } + + /* XXX: ?? andSISIDXREG(SISCR, 0x32, ~0x14); */ + /* pSiS->postVBCR32 &= ~0x14; */ + + /* scan for VGA2/SCART */ + if (testvga2_tempch || testvga2_tempcl || + testvga2_tempbh || testvga2_tempbl) { + + haveresult = 0; + for (j = 0; j < 10; j++) { + result = 0; + for (i = 0; i < 3; i++) { + if (sis_do_sense(testvga2_tempbl, testvga2_tempbh, + testvga2_tempcl, testvga2_tempch)) + result++; + } + if ((result == 0) || (result >= 2)) + break; + } + if (result) { + if (biosflag & 0x01) { + if (sis_verbose > 1) { + printf + ("[SiS] SiS30x: Detected TV connected to SCART output\n"); + } + sis_vbflags |= TV_SCART; + orSISIDXREG(SISCR, 0x32, 0x04); + /*pSiS->postVBCR32 |= 0x04; */ + } else { + if (sis_verbose > 1) { + printf + ("[SiS] SiS30x: Detected secondary VGA connection\n"); + } + sis_vbflags |= VGA2_CONNECTED; + orSISIDXREG(SISCR, 0x32, 0x10); + /*pSiS->postVBCR32 |= 0x10; */ + } + } + } + + /* scanning for TV */ + + /* XXX: ?? andSISIDXREG(SISCR, 0x32, ~0x03); */ + /* pSiS->postVBCR32 &= ~0x03; */ + + result = sis_do_sense(testsvhs_tempbl, testsvhs_tempbh, + testsvhs_tempcl, testsvhs_tempch); + + + haveresult = 0; + for (j = 0; j < 10; j++) { + result = 0; + for (i = 0; i < 3; i++) { + if (sis_do_sense(testsvhs_tempbl, testsvhs_tempbh, + testsvhs_tempcl, testsvhs_tempch)) + result++; + } + if ((result == 0) || (result >= 2)) + break; + } + if (result) { + if (sis_verbose > 1) { + printf + ("[SiS] SiS30x: Detected TV connected to SVIDEO output\n"); + } + /* TW: So we can be sure that there IS a SVIDEO output */ + sis_vbflags |= TV_SVIDEO; + orSISIDXREG(SISCR, 0x32, 0x02); + //pSiS->postVBCR32 |= 0x02; + } + + if ((biosflag & 0x02) || (!(result))) { + haveresult = 0; + for (j = 0; j < 10; j++) { + result = 0; + for (i = 0; i < 3; i++) { + if (sis_do_sense(testcvbs_tempbl, testcvbs_tempbh, + testcvbs_tempcl, testcvbs_tempch)) + result++; + } + if ((result == 0) || (result >= 2)) + break; + } + if (result) { + if (sis_verbose > 1) { + printf + ("[SiS] SiS30x: Detected TV connected to COMPOSITE output\n"); + } + sis_vbflags |= TV_AVIDEO; + orSISIDXREG(SISCR, 0x32, 0x01); + //pSiS->postVBCR32 |= 0x01; + } + } + + sis_do_sense(0, 0, 0, 0); + + outSISIDXREG(SISPART2, 0x00, backupP2_00); + outSISIDXREG(SISPART4, 0x0d, backupP4_0d); +} + + +static void sis_detect_crt1() +{ + unsigned char CR32; + unsigned char CRT1Detected = 0; + unsigned char OtherDevices = 0; + + if (!(sis_vbflags & VB_VIDEOBRIDGE)) { + sis_crt1_off = 0; + return; + } + + inSISIDXREG(SISCR, 0x32, CR32); + + if (CR32 & 0x20) + CRT1Detected = 1; + if (CR32 & 0x5F) + OtherDevices = 1; + + if (sis_crt1_off == -1) { + if (!CRT1Detected) { + /* BIOS detected no CRT1. */ + /* If other devices exist, switch it off */ + if (OtherDevices) + sis_crt1_off = 1; + else + sis_crt1_off = 0; + } else { + /* BIOS detected CRT1, leave/switch it on */ + sis_crt1_off = 0; + } + } + if (sis_verbose > 0) { + printf("[SiS] %sCRT1 connection detected\n", + sis_crt1_off ? "No " : ""); + } +} + +#if 0 /* not used yet */ +static void sis_detect_lcd() +{ + unsigned char CR32; +#if 0 + /* not supported yet? */ + unsigned char CR36, CR37; +#endif + + if (!(sis_vbflags & VB_VIDEOBRIDGE)) { + return; + } + + inSISIDXREG(SISCR, 0x32, CR32); + + if (CR32 & 0x08) + sis_vbflags |= CRT2_LCD; + + /* DDC detection of LCD - not supported yet */ + + /* Get other misc info about LCD - not supported */ +} +#endif + +static void sis_detect_tv() +{ + unsigned char SR16, SR38, CR32, CR38 = 0, CR79; + int temp = 0; + + if (!(sis_vbflags & VB_VIDEOBRIDGE)) + return; + + inSISIDXREG(SISCR, 0x32, CR32); + inSISIDXREG(SISSR, 0x16, SR16); + inSISIDXREG(SISSR, 0x38, SR38); + switch (sis_vga_engine) { + case SIS_300_VGA: + if (sis_device_id == DEVICE_SIS_630_VGA) + temp = 0x35; + break; + case SIS_315_VGA: + temp = 0x38; + break; + } + if (temp) { + inSISIDXREG(SISCR, temp, CR38); + } + + if (CR32 & 0x47) + sis_vbflags |= CRT2_TV; + + if (CR32 & 0x04) + sis_vbflags |= TV_SCART; + else if (CR32 & 0x02) + sis_vbflags |= TV_SVIDEO; + else if (CR32 & 0x01) + sis_vbflags |= TV_AVIDEO; + else if (CR32 & 0x40) + sis_vbflags |= (TV_SVIDEO | TV_HIVISION); + else if ((CR38 & 0x04) && (sis_vbflags & (VB_301LV | VB_302LV))) + sis_vbflags |= TV_HIVISION_LV; + else if ((CR38 & 0x04) && (sis_vbflags & VB_CHRONTEL)) + sis_vbflags |= (TV_CHSCART | TV_PAL); + else if ((CR38 & 0x08) && (sis_vbflags & VB_CHRONTEL)) + sis_vbflags |= (TV_CHHDTV | TV_NTSC); + + if (sis_vbflags & (TV_SCART | TV_SVIDEO | TV_AVIDEO | TV_HIVISION)) { + if (sis_vga_engine == SIS_300_VGA) { + /* TW: Should be SR38 here as well, but this + * does not work. Looks like a BIOS bug (2.04.5c). + */ + if (SR16 & 0x20) + sis_vbflags |= TV_PAL; + else + sis_vbflags |= TV_NTSC; + } else if ((sis_device_id == DEVICE_SIS_550_VGA)) { + inSISIDXREG(SISCR, 0x79, CR79); + if (CR79 & 0x08) { + inSISIDXREG(SISCR, 0x79, CR79); + CR79 >>= 5; + } + if (CR79 & 0x01) { + sis_vbflags |= TV_PAL; + if (CR38 & 0x40) + sis_vbflags |= TV_PALM; + else if (CR38 & 0x80) + sis_vbflags |= TV_PALN; + } else + sis_vbflags |= TV_NTSC; + } else if ((sis_device_id == DEVICE_SIS_650_VGA)) { + inSISIDXREG(SISCR, 0x79, CR79); + if (CR79 & 0x20) { + sis_vbflags |= TV_PAL; + if (CR38 & 0x40) + sis_vbflags |= TV_PALM; + else if (CR38 & 0x80) + sis_vbflags |= TV_PALN; + } else + sis_vbflags |= TV_NTSC; + } else { /* 315, 330 */ + if (SR38 & 0x01) { + sis_vbflags |= TV_PAL; + if (CR38 & 0x40) + sis_vbflags |= TV_PALM; + else if (CR38 & 0x80) + sis_vbflags |= TV_PALN; + } else + sis_vbflags |= TV_NTSC; + } + } + + if (sis_vbflags & + (TV_SCART | TV_SVIDEO | TV_AVIDEO | TV_HIVISION | TV_CHSCART | + TV_CHHDTV)) { + if (sis_verbose > 0) { + printf("[SiS] %sTV standard %s\n", + (sis_vbflags & (TV_CHSCART | TV_CHHDTV)) ? "Using " : + "Detected default ", + (sis_vbflags & TV_NTSC) ? ((sis_vbflags & TV_CHHDTV) ? + "480i HDTV" : "NTSC") + : ((sis_vbflags & TV_PALM) ? "PALM" + : ((sis_vbflags & TV_PALN) ? "PALN" : "PAL"))); + } + } + +} + + +static void sis_detect_crt2() +{ + unsigned char CR32; + + if (!(sis_vbflags & VB_VIDEOBRIDGE)) + return; + + /* CRT2-VGA not supported on LVDS and 30xLV */ + if (sis_vbflags & (VB_LVDS | VB_301LV | VB_302LV)) + return; + + inSISIDXREG(SISCR, 0x32, CR32); + + if (CR32 & 0x10) + sis_vbflags |= CRT2_VGA; + +#if 0 + if (!(pSiS->nocrt2ddcdetection)) { + if (sis_vbflags & (VB_301B | VB_302B)) { + if (!(sis_vbflags & (CRT2_VGA | CRT2_LCD))) { + printf + ("[SiS] BIOS detected no secondary VGA, sensing via DDC\n"); + if (SiS_SenseVGA2DDC(pSiS->SiS_Pr, pSiS)) { + printf + ("[SiS] DDC error during secondary VGA detection\n"); + } else { + inSISIDXREG(SISCR, 0x32, CR32); + if (CR32 & 0x10) { + sis_vbflags |= CRT2_VGA; + /*pSiS->postVBCR32 |= 0x10; */ + printf + ("[SiS] Detected secondary VGA connection\n"); + } else { + printf + ("[SiS] No secondary VGA connection detected\n"); + } + } + } + } + } +#endif + +} + + +/* Preinit: detect video bridge and sense connected devs */ +static void sis_detect_video_bridge() +{ + int temp, temp1, temp2; + + + sis_vbflags = 0; + + if (sis_vga_engine != SIS_300_VGA && sis_vga_engine != SIS_315_VGA) + return; + + inSISIDXREG(SISPART4, 0x00, temp); + temp &= 0x0F; + if (temp == 1) { + inSISIDXREG(SISPART4, 0x01, temp1); + temp1 &= 0xff; + if (temp1 >= 0xE0) { + sis_vbflags |= VB_302LV; + //pSiS->sishw_ext.ujVBChipID = VB_CHIP_302LV; + if (sis_verbose > 1) { + printf + ("[SiS] Detected SiS302LV video bridge (ID 1; Revision 0x%x)\n", + temp1); + } + + } else if (temp1 >= 0xD0) { + sis_vbflags |= VB_301LV; + //pSiS->sishw_ext.ujVBChipID = VB_CHIP_301LV; + if (sis_verbose > 1) { + printf + ("[SiS] Detected SiS301LV video bridge (ID 1; Revision 0x%x)\n", + temp1); + } + } else if (temp1 >= 0xB0) { + sis_vbflags |= VB_301B; + //pSiS->sishw_ext.ujVBChipID = VB_CHIP_301B; + inSISIDXREG(SISPART4, 0x23, temp2); + if (!(temp2 & 0x02)) + sis_vbflags |= VB_30xBDH; + if (sis_verbose > 1) { + printf + ("[SiS] Detected SiS301B%s video bridge (Revision 0x%x)\n", + (temp2 & 0x02) ? "" : " (DH)", temp1); + } + } else { + sis_vbflags |= VB_301; + //pSiS->sishw_ext.ujVBChipID = VB_CHIP_301; + if (sis_verbose > 1) { + printf + ("[SiS] Detected SiS301 video bridge (Revision 0x%x)\n", + temp1); + } + } + + sis_sense_30x(); + + } else if (temp == 2) { + + inSISIDXREG(SISPART4, 0x01, temp1); + temp1 &= 0xff; + if (temp1 >= 0xE0) { + sis_vbflags |= VB_302LV; + //pSiS->sishw_ext.ujVBChipID = VB_CHIP_302LV; + if (sis_verbose > 1) { + printf + ("[SiS] Detected SiS302LV video bridge (ID 2; Revision 0x%x)\n", + temp1); + } + } else if (temp1 >= 0xD0) { + sis_vbflags |= VB_301LV; + //pSiS->sishw_ext.ujVBChipID = VB_CHIP_301LV; + if (sis_verbose > 1) { + printf + ("[SiS] Detected SiS301LV video bridge (ID 2; Revision 0x%x)\n", + temp1); + } + } else { + sis_vbflags |= VB_302B; + //pSiS->sishw_ext.ujVBChipID = VB_CHIP_302B; + inSISIDXREG(SISPART4, 0x23, temp2); + if (!(temp & 0x02)) + sis_vbflags |= VB_30xBDH; + if (sis_verbose > 1) { + printf + ("[SiS] Detected SiS302B%s video bridge (Revision 0x%x)\n", + (temp2 & 0x02) ? "" : " (DH)", temp1); + } + } + + sis_sense_30x(); + + } else if (temp == 3) { + if (sis_verbose > 1) { + printf("[SiS] Detected SiS303 video bridge - not supported\n"); + } + } else { + /* big scary mess of code to handle unknown or Chrontel LVDS */ + /* skipping it for now */ + if (sis_verbose > 1) { + printf + ("[SiS] Detected Chrontel video bridge - not supported\n"); + } + } + + /* this is probably not relevant to video overlay driver... */ + /* detects if brdige uses LCDA for low res text modes */ + if (sis_vga_engine == SIS_315_VGA) { + if (sis_vbflags & (VB_302B | VB_301LV | VB_302LV)) { +#if 0 + if (pSiS->sisfblcda != 0xff) { + if ((pSiS->sisfblcda & 0x03) == 0x03) { + //pSiS->SiS_Pr->SiS_UseLCDA = TRUE; + sis_vbflags |= VB_USELCDA; + } + } else +#endif + { + inSISIDXREG(SISCR, 0x34, temp); + if (temp <= 0x13) { + inSISIDXREG(SISCR, 0x38, temp); + if ((temp & 0x03) == 0x03) { + //pSiS->SiS_Pr->SiS_UseLCDA = TRUE; + sis_vbflags |= VB_USELCDA; + } else { + inSISIDXREG(SISCR, 0x30, temp); + if (temp & 0x20) { + inSISIDXREG(SISPART1, 0x13, temp); + if (temp & 0x40) { + //pSiS->SiS_Pr->SiS_UseLCDA = TRUE; + sis_vbflags |= VB_USELCDA; + } + } + } + } + } + if (sis_vbflags & VB_USELCDA) { + /* printf("Bridge uses LCDA for low resolution and text modes\n"); */ + } + } + } + + +} + + +/* detect video bridge type and sense connected devices */ +void sis_init_video_bridge() +{ + + sis_detect_video_bridge(); + + sis_detect_crt1(); + //sis_detect_lcd(); /* not fully ready probably */ + sis_detect_tv(); + sis_detect_crt2(); + + sis_detected_crt2_devices = + sis_vbflags & (CRT2_LCD | CRT2_TV | CRT2_VGA); + + // force crt2 type + if (sis_force_crt2_type == CRT2_DEFAULT) { + if (sis_vbflags & CRT2_VGA) + sis_force_crt2_type = CRT2_VGA; + else if (sis_vbflags & CRT2_LCD) + sis_force_crt2_type = CRT2_LCD; + else if (sis_vbflags & CRT2_TV) + sis_force_crt2_type = CRT2_TV; + } + + switch (sis_force_crt2_type) { + case CRT2_TV: + sis_vbflags = sis_vbflags & ~(CRT2_LCD | CRT2_VGA); + if (sis_vbflags & VB_VIDEOBRIDGE) + sis_vbflags = sis_vbflags | CRT2_TV; + else + sis_vbflags = sis_vbflags & ~(CRT2_TV); + break; + case CRT2_LCD: + sis_vbflags = sis_vbflags & ~(CRT2_TV | CRT2_VGA); + if ((sis_vbflags & VB_VIDEOBRIDGE) /* XXX: && (pSiS->VBLCDFlags) */ + ) + sis_vbflags = sis_vbflags | CRT2_LCD; + else { + sis_vbflags = sis_vbflags & ~(CRT2_LCD); + if (sis_verbose > 0) { + printf + ("[SiS] Can't force CRT2 to LCD, no panel detected\n"); + } + } + break; + case CRT2_VGA: + if (sis_vbflags & VB_LVDS) { + if (sis_verbose > 0) { + printf("[SiS] LVDS does not support secondary VGA\n"); + } + break; + } + if (sis_vbflags & (VB_301LV | VB_302LV)) { + if (sis_verbose > 0) { + printf + ("[SiS] SiS30xLV bridge does not support secondary VGA\n"); + } + break; + } + sis_vbflags = sis_vbflags & ~(CRT2_TV | CRT2_LCD); + if (sis_vbflags & VB_VIDEOBRIDGE) + sis_vbflags = sis_vbflags | CRT2_VGA; + else + sis_vbflags = sis_vbflags & ~(CRT2_VGA); + break; + default: + sis_vbflags &= ~(CRT2_TV | CRT2_LCD | CRT2_VGA); + } + + /* CRT2 gamma correction?? */ + + /* other force modes: */ + /* have a 'force tv type' (svideo, composite, scart) option? */ + /* have a 'force crt1 type' (to turn it off, etc??) */ + + /* TW: Check if CRT1 used (or needed; this eg. if no CRT2 detected) */ + if (sis_vbflags & VB_VIDEOBRIDGE) { + + /* TW: No CRT2 output? Then we NEED CRT1! + * We also need CRT1 if depth = 8 and bridge=LVDS|630+301B + */ + if ((!(sis_vbflags & (CRT2_VGA | CRT2_LCD | CRT2_TV))) || ( /*(pScrn->bitsPerPixel == 8) && */ + ((sis_vbflags & (VB_LVDS | VB_CHRONTEL)) || ((sis_vga_engine == SIS_300_VGA) && (sis_vbflags & VB_301B))))) { + sis_crt1_off = 0; + } + /* TW: No CRT2 output? Then we can't use hw overlay on CRT2 */ + if (!(sis_vbflags & (CRT2_VGA | CRT2_LCD | CRT2_TV))) + sis_overlay_on_crt1 = 1; + + } else { /* TW: no video bridge? */ + + /* Then we NEED CRT1... */ + sis_crt1_off = 0; + /* ... and can't use CRT2 for overlay output */ + sis_overlay_on_crt1 = 1; + } + + /* tvstandard options ? */ + + // determine using CRT1 or CRT2? + /* -> NO dualhead right now... */ + if (sis_vbflags & DISPTYPE_DISP2) { + if (sis_crt1_off) { + sis_vbflags |= VB_DISPMODE_SINGLE; + /* TW: No CRT1? Then we use the video overlay on CRT2 */ + sis_overlay_on_crt1 = 0; + } else /* TW: CRT1 and CRT2 - mirror or dual head ----- */ + sis_vbflags |= (VB_DISPMODE_MIRROR | DISPTYPE_CRT1); + } else { /* TW: CRT1 only ------------------------------- */ + sis_vbflags |= (VB_DISPMODE_SINGLE | DISPTYPE_CRT1); + } + + if (sis_verbose > 0) { + printf("[SiS] Using hardware overlay on CRT%d\n", + sis_overlay_on_crt1 ? 1 : 2); + } + +} diff --git a/contrib/vidix/drivers/sis_defs.h b/contrib/vidix/drivers/sis_defs.h new file mode 100644 index 000000000..79a61a19b --- /dev/null +++ b/contrib/vidix/drivers/sis_defs.h @@ -0,0 +1,106 @@ +/** + SiS graphics misc definitions. + + Taken from SiS Xv driver: + Copyright 2002-2003 by Thomas Winischhofer, Vienna, Austria. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +**/ + +#ifndef VIDIX_SIS_DEFS_H +#define VIDIX_SIS_DEFS_H + +/** PCI IDs **/ +#define VENDOR_SIS 0x1039 + +#define DEVICE_SIS_300 0x0300 +#define DEVICE_SIS_315H 0x0310 +#define DEVICE_SIS_315 0x0315 +#define DEVICE_SIS_315PRO 0x0325 +#define DEVICE_SIS_330 0x0330 +#define DEVICE_SIS_540 0x0540 +#define DEVICE_SIS_540_VGA 0x5300 +#define DEVICE_SIS_550 0x0550 +#define DEVICE_SIS_550_VGA 0x5315 +#define DEVICE_SIS_630 0x0630 +#define DEVICE_SIS_630_VGA 0x6300 +#define DEVICE_SIS_650 0x0650 +#define DEVICE_SIS_650_VGA 0x6325 +#define DEVICE_SIS_730 0x0730 + + +/* TW: VBFlags */ +#define CRT2_DEFAULT 0x00000001 +#define CRT2_LCD 0x00000002 /* TW: Never change the order of the CRT2_XXX entries */ +#define CRT2_TV 0x00000004 /* (see SISCycleCRT2Type()) */ +#define CRT2_VGA 0x00000008 +#define CRT2_ENABLE (CRT2_LCD | CRT2_TV | CRT2_VGA) +#define DISPTYPE_DISP2 CRT2_ENABLE +#define TV_NTSC 0x00000010 +#define TV_PAL 0x00000020 +#define TV_HIVISION 0x00000040 +#define TV_HIVISION_LV 0x00000080 +#define TV_TYPE (TV_NTSC | TV_PAL | TV_HIVISION | TV_HIVISION_LV) +#define TV_AVIDEO 0x00000100 +#define TV_SVIDEO 0x00000200 +#define TV_SCART 0x00000400 +#define TV_INTERFACE (TV_AVIDEO | TV_SVIDEO | TV_SCART | TV_CHSCART | TV_CHHDTV) +#define VB_USELCDA 0x00000800 +#define TV_PALM 0x00001000 +#define TV_PALN 0x00002000 +#define TV_CHSCART 0x00008000 +#define TV_CHHDTV 0x00010000 +#define VGA2_CONNECTED 0x00040000 +#define DISPTYPE_CRT1 0x00080000 /* TW: CRT1 connected and used */ +#define DISPTYPE_DISP1 DISPTYPE_CRT1 +#define VB_301 0x00100000 /* Video bridge type */ +#define VB_301B 0x00200000 +#define VB_302B 0x00400000 +#define VB_30xBDH 0x00800000 /* 30xB DH version (w/o LCD support) */ +#define VB_LVDS 0x01000000 +#define VB_CHRONTEL 0x02000000 +#define VB_301LV 0x04000000 +#define VB_302LV 0x08000000 +#define VB_30xLV VB_301LV +#define VB_30xLVX VB_302LV +#define VB_TRUMPION 0x10000000 +#define VB_VIDEOBRIDGE (VB_301|VB_301B|VB_302B|VB_301LV|VB_302LV| \ + VB_LVDS|VB_CHRONTEL|VB_TRUMPION) /* TW */ +#define VB_SISBRIDGE (VB_301|VB_301B|VB_302B|VB_301LV|VB_302LV) +#define SINGLE_MODE 0x20000000 /* TW: CRT1 or CRT2; determined by DISPTYPE_CRTx */ +#define VB_DISPMODE_SINGLE SINGLE_MODE /* TW: alias */ +#define MIRROR_MODE 0x40000000 /* TW: CRT1 + CRT2 identical (mirror mode) */ +#define VB_DISPMODE_MIRROR MIRROR_MODE /* TW: alias */ +#define DUALVIEW_MODE 0x80000000 /* TW: CRT1 + CRT2 independent (dual head mode) */ +#define VB_DISPMODE_DUAL DUALVIEW_MODE /* TW: alias */ +#define DISPLAY_MODE (SINGLE_MODE | MIRROR_MODE | DUALVIEW_MODE) /* TW */ + +/* SiS vga engine type */ +#define UNKNOWN_VGA 0 +#define SIS_300_VGA 1 +#define SIS_315_VGA 2 + +extern unsigned int sis_verbose; +extern unsigned short sis_iobase; +extern unsigned int sis_vga_engine; +extern unsigned int sis_vbflags; +extern unsigned int sis_overlay_on_crt1; +extern unsigned int sis_crt1_off; +extern unsigned int sis_detected_crt2_devices; +extern unsigned int sis_force_crt2_type; +extern unsigned int sis_device_id; + +#endif /* VIDIX_SIS_DEFS_H */ diff --git a/contrib/vidix/drivers/sis_regs.h b/contrib/vidix/drivers/sis_regs.h new file mode 100644 index 000000000..0157e049a --- /dev/null +++ b/contrib/vidix/drivers/sis_regs.h @@ -0,0 +1,412 @@ +/** + SiS register definitions and access macros. + From SiS X11 driver. + + Copyright 2001-2003 by Thomas Winischhofer, Vienna, Austria. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +**/ + +#ifndef VIDIX_SIS_REGS_H +#define VIDIX_SIS_REGS_H + +#define inSISREG(base) INPORT8(base) +#define outSISREG(base,val) OUTPORT8(base, val) +#define orSISREG(base,val) do { \ + unsigned char __Temp = INPORT8(base); \ + outSISREG(base, __Temp | (val)); \ + } while (0) +#define andSISREG(base,val) do { \ + unsigned char __Temp = INPORT8(base); \ + outSISREG(base, __Temp & (val)); \ + } while (0) + +#define inSISIDXREG(base,idx,var) do { \ + OUTPORT8(base, idx); var=INPORT8((base)+1); \ + } while (0) +#define outSISIDXREG(base,idx,val) do { \ + OUTPORT8(base, idx); OUTPORT8((base)+1, val); \ + } while (0) +#define orSISIDXREG(base,idx,val) do { \ + unsigned char __Temp; \ + OUTPORT8(base, idx); \ + __Temp = INPORT8((base)+1)|(val); \ + outSISIDXREG(base,idx,__Temp); \ + } while (0) +#define andSISIDXREG(base,idx,and) do { \ + unsigned char __Temp; \ + OUTPORT8(base, idx); \ + __Temp = INPORT8((base)+1)&(and); \ + outSISIDXREG(base,idx,__Temp); \ + } while (0) +#define setSISIDXREG(base,idx,and,or) do { \ + unsigned char __Temp; \ + OUTPORT8(base, idx); \ + __Temp = (INPORT8((base)+1)&(and))|(or); \ + outSISIDXREG(base,idx,__Temp); \ + } while (0) + +#define BITMASK(h,l) (((unsigned)(1U << ((h)-(l)+1))-1)<<(l)) +#define GENMASK(mask) BITMASK(1?mask,0?mask) + +#define GETBITS(var,mask) (((var) & GENMASK(mask)) >> (0?mask)) +#define SETBITS(val,mask) ((val) << (0?mask)) +#define SETBIT(n) (1<<(n)) + +#define GETBITSTR(val,from,to) ((GETBITS(val,from)) << (0?to)) +#define SETVARBITS(var,val,from,to) (((var)&(~(GENMASK(to)))) | \ + GETBITSTR(val,from,to)) +#define GETVAR8(var) ((var)&0xFF) +#define SETVAR8(var,val) (var) = GETVAR8(val) + +/* #define VGA_RELIO_BASE 0x380 */ + +#define AROFFSET 0x40 /* VGA_ATTR_INDEX - VGA_RELIO_BASE */ +#define ARROFFSET 0x41 /* VGA_ATTR_DATA_R - VGA_RELIO_BASE */ +#define GROFFSET 0x4e /* VGA_GRAPH_INDEX - VGA_RELIO_BASE */ +#define SROFFSET 0x44 /* VGA_SEQ_INDEX - VGA_RELIO_BASE */ +#define CROFFSET 0x54 /* VGA_CRTC_INDEX_OFFSET + VGA_IOBASE_COLOR - VGA_RELIO_BASE */ +#define MISCROFFSET 0x4c /* VGA_MISC_OUT_R - VGA_RELIO_BASE */ +#define MISCWOFFSET 0x42 /* VGA_MISC_OUT_W - VGA_RELIO_BASE */ +#define INPUTSTATOFFSET 0x5A +#define PART1OFFSET 0x04 +#define PART2OFFSET 0x10 +#define PART3OFFSET 0x12 +#define PART4OFFSET 0x14 +#define PART5OFFSET 0x16 +#define VIDEOOFFSET 0x02 +#define COLREGOFFSET 0x48 + +#define SIS_IOBASE sis_iobase /* var defined in sis_vid.c */ +#define SISAR SIS_IOBASE + AROFFSET +#define SISARR SIS_IOBASE + ARROFFSET +#define SISGR SIS_IOBASE + GROFFSET +#define SISSR SIS_IOBASE + SROFFSET +#define SISCR SIS_IOBASE + CROFFSET +#define SISMISCR SIS_IOBASE + MISCROFFSET +#define SISMISCW SIS_IOBASE + MISCWOFFSET +#define SISINPSTAT SIS_IOBASE + INPUTSTATOFFSET +#define SISPART1 SIS_IOBASE + PART1OFFSET +#define SISPART2 SIS_IOBASE + PART2OFFSET +#define SISPART3 SIS_IOBASE + PART3OFFSET +#define SISPART4 SIS_IOBASE + PART4OFFSET +#define SISPART5 SIS_IOBASE + PART5OFFSET +#define SISVID SIS_IOBASE + VIDEOOFFSET +#define SISCOLIDX SIS_IOBASE + COLREGOFFSET +#define SISCOLDATA SIS_IOBASE + COLREGOFFSET + 1 +#define SISCOL2IDX SISPART5 +#define SISCOL2DATA SISPART5 + 1 + + +#define vc_index_offset 0x00 /* Video capture - unused */ +#define vc_data_offset 0x01 +#define vi_index_offset VIDEOOFFSET +#define vi_data_offset (VIDEOOFFSET + 1) +#define crt2_index_offset PART1OFFSET +#define crt2_port_offset (PART1OFFSET + 1) +#define sr_index_offset SROFFSET +#define sr_data_offset (SROFFSET + 1) +#define cr_index_offset CROFFSET +#define cr_data_offset (CROFFSET + 1) +#define input_stat INPUTSTATOFFSET + +/* For old chipsets (5597/5598, 6326, 530/620) ------------ */ +/* SR (3C4) */ +#define BankReg 0x06 +#define ClockReg 0x07 +#define CPUThreshold 0x08 +#define CRTThreshold 0x09 +#define CRTCOff 0x0A +#define DualBanks 0x0B +#define MMIOEnable 0x0B +#define RAMSize 0x0C +#define Mode64 0x0C +#define ExtConfStatus1 0x0E +#define ClockBase 0x13 +#define LinearAdd0 0x20 +#define LinearAdd1 0x21 +#define GraphEng 0x27 +#define MemClock0 0x28 +#define MemClock1 0x29 +#define XR2A 0x2A +#define XR2B 0x2B +#define TurboQueueBase 0x2C +#define FBSize 0x2F +#define ExtMiscCont5 0x34 +#define ExtMiscCont9 0x3C + +/* 3x4 */ +#define Offset 0x13 + +/* SiS Registers for 300, 540, 630, 730, 315, 550, 650, 740 */ + +/* VGA standard register */ +#define Index_SR_Graphic_Mode 0x06 +#define Index_SR_RAMDAC_Ctrl 0x07 +#define Index_SR_Threshold_Ctrl1 0x08 +#define Index_SR_Threshold_Ctrl2 0x09 +#define Index_SR_Misc_Ctrl 0x0F +#define Index_SR_DDC 0x11 +#define Index_SR_Feature_Connector_Ctrl 0x12 +#define Index_SR_DRAM_Sizing 0x14 +#define Index_SR_DRAM_State_Machine_Ctrl 0x15 +#define Index_SR_AGP_PCI_State_Machine 0x21 +#define Index_SR_Internal_MCLK0 0x28 +#define Index_SR_Internal_MCLK1 0x29 +#define Index_SR_Internal_DCLK1 0x2B +#define Index_SR_Internal_DCLK2 0x2C +#define Index_SR_Internal_DCLK3 0x2D +#define Index_SR_Ext_Clock_Sel 0x32 +#define Index_SR_Int_Status 0x34 +#define Index_SR_Int_Enable 0x35 +#define Index_SR_Int_Reset 0x36 +#define Index_SR_Power_On_Trap 0x38 +#define Index_SR_Power_On_Trap2 0x39 +#define Index_SR_Power_On_Trap3 0x3A + +/* video registers (300/630/730/315/550/650/740 only) */ +#define Index_VI_Passwd 0x00 + +/* Video overlay horizontal start/end, unit=screen pixels */ +#define Index_VI_Win_Hor_Disp_Start_Low 0x01 +#define Index_VI_Win_Hor_Disp_End_Low 0x02 +#define Index_VI_Win_Hor_Over 0x03 /* Overflow */ + +/* Video overlay vertical start/end, unit=screen pixels */ +#define Index_VI_Win_Ver_Disp_Start_Low 0x04 +#define Index_VI_Win_Ver_Disp_End_Low 0x05 +#define Index_VI_Win_Ver_Over 0x06 /* Overflow */ + +/* Y Plane (4:2:0) or YUV (4:2:2) buffer start address, unit=word */ +#define Index_VI_Disp_Y_Buf_Start_Low 0x07 +#define Index_VI_Disp_Y_Buf_Start_Middle 0x08 +#define Index_VI_Disp_Y_Buf_Start_High 0x09 + +/* U Plane (4:2:0) buffer start address, unit=word */ +#define Index_VI_U_Buf_Start_Low 0x0A +#define Index_VI_U_Buf_Start_Middle 0x0B +#define Index_VI_U_Buf_Start_High 0x0C + +/* V Plane (4:2:0) buffer start address, unit=word */ +#define Index_VI_V_Buf_Start_Low 0x0D +#define Index_VI_V_Buf_Start_Middle 0x0E +#define Index_VI_V_Buf_Start_High 0x0F + +/* Pitch for Y, UV Planes, unit=word */ +#define Index_VI_Disp_Y_Buf_Pitch_Low 0x10 +#define Index_VI_Disp_UV_Buf_Pitch_Low 0x11 +#define Index_VI_Disp_Y_UV_Buf_Pitch_Middle 0x12 + +/* What is this ? */ +#define Index_VI_Disp_Y_Buf_Preset_Low 0x13 +#define Index_VI_Disp_Y_Buf_Preset_Middle 0x14 + +#define Index_VI_UV_Buf_Preset_Low 0x15 +#define Index_VI_UV_Buf_Preset_Middle 0x16 +#define Index_VI_Disp_Y_UV_Buf_Preset_High 0x17 + +/* Scaling control registers */ +#define Index_VI_Hor_Post_Up_Scale_Low 0x18 +#define Index_VI_Hor_Post_Up_Scale_High 0x19 +#define Index_VI_Ver_Up_Scale_Low 0x1A +#define Index_VI_Ver_Up_Scale_High 0x1B +#define Index_VI_Scale_Control 0x1C + +/* Playback line buffer control */ +#define Index_VI_Play_Threshold_Low 0x1D +#define Index_VI_Play_Threshold_High 0x1E +#define Index_VI_Line_Buffer_Size 0x1F + +/* Destination color key */ +#define Index_VI_Overlay_ColorKey_Red_Min 0x20 +#define Index_VI_Overlay_ColorKey_Green_Min 0x21 +#define Index_VI_Overlay_ColorKey_Blue_Min 0x22 +#define Index_VI_Overlay_ColorKey_Red_Max 0x23 +#define Index_VI_Overlay_ColorKey_Green_Max 0x24 +#define Index_VI_Overlay_ColorKey_Blue_Max 0x25 + +/* Source color key, YUV color space */ +#define Index_VI_Overlay_ChromaKey_Red_Y_Min 0x26 +#define Index_VI_Overlay_ChromaKey_Green_U_Min 0x27 +#define Index_VI_Overlay_ChromaKey_Blue_V_Min 0x28 +#define Index_VI_Overlay_ChromaKey_Red_Y_Max 0x29 +#define Index_VI_Overlay_ChromaKey_Green_U_Max 0x2A +#define Index_VI_Overlay_ChromaKey_Blue_V_Max 0x2B + +/* Contrast enhancement and brightness control */ +#define Index_VI_Contrast_Factor 0x2C /* obviously unused/undefined */ +#define Index_VI_Brightness 0x2D +#define Index_VI_Contrast_Enh_Ctrl 0x2E + +#define Index_VI_Key_Overlay_OP 0x2F + +#define Index_VI_Control_Misc0 0x30 +#define Index_VI_Control_Misc1 0x31 +#define Index_VI_Control_Misc2 0x32 + +/* TW: Subpicture registers */ +#define Index_VI_SubPict_Buf_Start_Low 0x33 +#define Index_VI_SubPict_Buf_Start_Middle 0x34 +#define Index_VI_SubPict_Buf_Start_High 0x35 + +/* TW: What is this ? */ +#define Index_VI_SubPict_Buf_Preset_Low 0x36 +#define Index_VI_SubPict_Buf_Preset_Middle 0x37 + +/* TW: Subpicture pitch, unit=16 bytes */ +#define Index_VI_SubPict_Buf_Pitch 0x38 + +/* TW: Subpicture scaling control */ +#define Index_VI_SubPict_Hor_Scale_Low 0x39 +#define Index_VI_SubPict_Hor_Scale_High 0x3A +#define Index_VI_SubPict_Vert_Scale_Low 0x3B +#define Index_VI_SubPict_Vert_Scale_High 0x3C + +#define Index_VI_SubPict_Scale_Control 0x3D +/* (0x40 = enable/disable subpicture) */ + +/* TW: Subpicture line buffer control */ +#define Index_VI_SubPict_Threshold 0x3E + +/* TW: What is this? */ +#define Index_VI_FIFO_Max 0x3F + +/* TW: Subpicture palette; 16 colors, total 32 bytes address space */ +#define Index_VI_SubPict_Pal_Base_Low 0x40 +#define Index_VI_SubPict_Pal_Base_High 0x41 + +/* I wish I knew how to use these ... */ +#define Index_MPEG_Read_Ctrl0 0x60 /* MPEG auto flip */ +#define Index_MPEG_Read_Ctrl1 0x61 /* MPEG auto flip */ +#define Index_MPEG_Read_Ctrl2 0x62 /* MPEG auto flip */ +#define Index_MPEG_Read_Ctrl3 0x63 /* MPEG auto flip */ + +/* TW: MPEG AutoFlip scale */ +#define Index_MPEG_Ver_Up_Scale_Low 0x64 +#define Index_MPEG_Ver_Up_Scale_High 0x65 + +#define Index_MPEG_Y_Buf_Preset_Low 0x66 +#define Index_MPEG_Y_Buf_Preset_Middle 0x67 +#define Index_MPEG_UV_Buf_Preset_Low 0x68 +#define Index_MPEG_UV_Buf_Preset_Middle 0x69 +#define Index_MPEG_Y_UV_Buf_Preset_High 0x6A + +/* TW: The following registers only exist on the 310/325 series */ + +/* TW: Bit 16:24 of Y_U_V buf start address (?) */ +#define Index_VI_Y_Buf_Start_Over 0x6B +#define Index_VI_U_Buf_Start_Over 0x6C +#define Index_VI_V_Buf_Start_Over 0x6D + +#define Index_VI_Disp_Y_Buf_Pitch_High 0x6E +#define Index_VI_Disp_UV_Buf_Pitch_High 0x6F + +/* Hue and saturation */ +#define Index_VI_Hue 0x70 +#define Index_VI_Saturation 0x71 + +#define Index_VI_SubPict_Start_Over 0x72 +#define Index_VI_SubPict_Buf_Pitch_High 0x73 + +#define Index_VI_Control_Misc3 0x74 + + +/* TW: Bits (and helpers) for Index_VI_Control_Misc0 */ +#define VI_Misc0_Enable_Overlay 0x02 +#define VI_Misc0_420_Plane_Enable 0x04 /* Select Plane or Packed mode */ +#define VI_Misc0_422_Enable 0x20 /* Select 422 or 411 mode */ +#define VI_Misc0_Fmt_YVU420P 0x0C /* YUV420 Planar (I420, YV12) */ +#define VI_Misc0_Fmt_YUYV 0x28 /* YUYV Packed (YUY2) */ +#define VI_Misc0_Fmt_UYVY 0x08 /* (UYVY) */ + +/* TW: Bits for Index_VI_Control_Misc1 */ +/* #define VI_Misc1_? 0x01 */ +#define VI_Misc1_BOB_Enable 0x02 +#define VI_Misc1_Line_Merge 0x04 +#define VI_Misc1_Field_Mode 0x08 +/* #define VI_Misc1_? 0x10 */ +#define VI_Misc1_Non_Interleave 0x20 /* 300 series only? */ +#define VI_Misc1_Buf_Addr_Lock 0x20 /* 310 series only? */ +/* #define VI_Misc1_? 0x40 */ +/* #define VI_Misc1_? 0x80 */ + +/* TW: Bits for Index_VI_Control_Misc2 */ +#define VI_Misc2_Select_Video2 0x01 +#define VI_Misc2_Video2_On_Top 0x02 +/* #define VI_Misc2_? 0x04 */ +#define VI_Misc2_Vertical_Interpol 0x08 +#define VI_Misc2_Dual_Line_Merge 0x10 +#define VI_Misc2_All_Line_Merge 0x20 /* 310 series only? */ +#define VI_Misc2_Auto_Flip_Enable 0x40 /* 300 series only? */ +#define VI_Misc2_Video_Reg_Write_Enable 0x80 /* 310 series only? */ + +/* TW: Bits for Index_VI_Control_Misc3 */ +#define VI_Misc3_Submit_Video_1 0x01 /* AKA "address ready" */ +#define VI_Misc3_Submit_Video_2 0x02 /* AKA "address ready" */ +#define VI_Misc3_Submit_SubPict 0x04 /* AKA "address ready" */ + +/* TW: Values for Index_VI_Key_Overlay_OP (0x2F) */ +#define VI_ROP_Never 0x00 +#define VI_ROP_DestKey 0x03 +#define VI_ROP_Always 0x0F + +/* + * CRT_2 function control register --------------------------------- + */ +#define Index_CRT2_FC_CONTROL 0x00 +#define Index_CRT2_FC_SCREEN_HIGH 0x04 +#define Index_CRT2_FC_SCREEN_MID 0x05 +#define Index_CRT2_FC_SCREEN_LOW 0x06 +#define Index_CRT2_FC_ENABLE_WRITE 0x24 +#define Index_CRT2_FC_VR 0x25 +#define Index_CRT2_FC_VCount 0x27 +#define Index_CRT2_FC_VCount1 0x28 + +#define Index_310_CRT2_FC_VR 0x30 /* d[1] = vertical retrace */ +#define Index_310_CRT2_FC_RT 0x33 /* d[7] = retrace in progress */ + +/* video attributes - these should probably be configurable on the fly + * so users with different desktop sizes can keep + * captured data off the desktop + */ +#define _VINWID 704 +#define _VINHGT _VINHGT_NTSC +#define _VINHGT_NTSC 240 +#define _VINHGT_PAL 290 +#define _VIN_WINDOW (704 * 291 * 2) +#define _VBI_WINDOW (704 * 64 * 2) + +#define _VIN_FIELD_EVEN 1 +#define _VIN_FIELD_ODD 2 +#define _VIN_FIELD_BOTH 4 + + +/* i2c registers (TW; not on 300/310/325 series) */ +#define X_INDEXREG 0x14 +#define X_PORTREG 0x15 +#define X_DATA 0x0f +#define I2C_SCL 0x00 +#define I2C_SDA 0x01 +#define I2C_DELAY 10 + +/* mmio registers for video */ +#define REG_PRIM_CRT_COUNTER 0x8514 + +/* TW: MPEG MMIO registers (630 and later) ----------------------------*/ + +/* Not public (yet?) */ + +#endif /* VIDIX_SIS_REGS_H */ diff --git a/contrib/vidix/drivers/sis_vid.c b/contrib/vidix/drivers/sis_vid.c new file mode 100644 index 000000000..c3ef2bdcf --- /dev/null +++ b/contrib/vidix/drivers/sis_vid.c @@ -0,0 +1,1562 @@ +/** + VIDIX driver for SiS 300 and 310/325 series chips. + + Copyright 2003 Jake Page, Sugar Media. + + Based on SiS Xv driver: + Copyright 2002-2003 by Thomas Winischhofer, Vienna, Austria. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + 2003/10/08 integrated into mplayer/vidix architecture -- Alex Beregszaszi +**/ + +#include <errno.h> +#include <stdio.h> +#include <stdlib.h> +#include <string.h> +#include <inttypes.h> +#include <unistd.h> + +#include "vidix.h" +#include "fourcc.h" +#include "libdha.h" +#include "pci_ids.h" +#include "pci_names.h" + +#include "sis_regs.h" +#include "sis_defs.h" + + +/** Random defines **/ + +#define WATCHDOG_DELAY 500000 /* Watchdog counter for retrace waiting */ +#define IMAGE_MIN_WIDTH 32 /* Min and max source image sizes */ +#define IMAGE_MIN_HEIGHT 24 +#define IMAGE_MAX_WIDTH 720 +#define IMAGE_MAX_HEIGHT 576 +#define IMAGE_MAX_WIDTH_M650 1920 +#define IMAGE_MAX_HEIGHT_M650 1080 + +#define OVERLAY_MIN_WIDTH 32 /* Minimum overlay sizes */ +#define OVERLAY_MIN_HEIGHT 24 + +#define DISPMODE_SINGLE1 0x1 /* TW: CRT1 only */ +#define DISPMODE_SINGLE2 0x2 /* TW: CRT2 only */ +#define DISPMODE_MIRROR 0x4 /* TW: CRT1 + CRT2 MIRROR */ + +#define VMODE_INTERLACED 0x1 +#define VMODE_DOUBLESCAN 0x2 + +typedef struct { + short x1, y1, x2, y2; +} BoxRec; + +typedef struct { + int pixelFormat; + + uint16_t pitch; + uint16_t origPitch; + + uint8_t keyOP; + uint16_t HUSF; + uint16_t VUSF; + uint8_t IntBit; + uint8_t wHPre; + + uint16_t srcW; + uint16_t srcH; + + BoxRec dstBox; + + uint32_t PSY; + uint32_t PSV; + uint32_t PSU; + uint8_t bobEnable; + + uint8_t contrastCtrl; + uint8_t contrastFactor; + + uint8_t lineBufSize; + + uint8_t(*VBlankActiveFunc) (); + + uint16_t SCREENheight; + +} SISOverlayRec, *SISOverlayPtr; + + +/** static variable definitions **/ +static int sis_probed = 0; +static pciinfo_t pci_info; +unsigned int sis_verbose = 0; + +static void *sis_mem_base; +/* static void *sis_reg_base; */ +unsigned short sis_iobase; + +unsigned int sis_vga_engine = UNKNOWN_VGA; +static unsigned int sis_displaymode = DISPMODE_SINGLE1; +static unsigned int sis_has_two_overlays = 0; +static unsigned int sis_bridge_is_slave = 0; +static unsigned int sis_shift_value = 1; +static unsigned int sis_vmode = 0; +unsigned int sis_vbflags = DISPTYPE_DISP1; +unsigned int sis_overlay_on_crt1 = 1; +unsigned int sis_crt1_off = -1; +unsigned int sis_detected_crt2_devices; +unsigned int sis_force_crt2_type = CRT2_DEFAULT; +unsigned int sis_device_id = -1; + +static int sis_format; +static int sis_Yoff = 0; +static int sis_Voff = 0; +static int sis_Uoff = 0; +static int sis_screen_width = 640; +static int sis_screen_height = 480; + +static int sis_frames[VID_PLAY_MAXFRAMES]; + +static vidix_grkey_t sis_grkey; + +static vidix_capability_t sis_cap = { + "SiS 300/310/325 Video Driver", + "Jake Page", + TYPE_OUTPUT, + {0, 0, 0, 0}, + 2048, + 2048, + 4, + 4, + -1, + FLAG_UPSCALER | FLAG_DOWNSCALER | FLAG_EQUALIZER, + VENDOR_SIS, + -1, + {0, 0, 0, 0} +}; + +vidix_video_eq_t sis_equal = { + VEQ_CAP_BRIGHTNESS | VEQ_CAP_CONTRAST, + 200, 0, 0, 0, 0, 0, 0, 0 +}; + +static unsigned short sis_card_ids[] = { + DEVICE_SIS_300, + DEVICE_SIS_315H, + DEVICE_SIS_315, + DEVICE_SIS_315PRO, + DEVICE_SIS_330, + DEVICE_SIS_540_VGA, + DEVICE_SIS_550_VGA, + DEVICE_SIS_630_VGA, + DEVICE_SIS_650_VGA +}; + +/** function declarations **/ + +extern void sis_init_video_bridge(); + + +static void set_overlay(SISOverlayPtr pOverlay, int index); +static void close_overlay(void); +static void calc_scale_factor(SISOverlayPtr pOverlay, + int index, int iscrt2); +static void set_line_buf_size(SISOverlayPtr pOverlay); +static void merge_line_buf(int enable); +static void set_format(SISOverlayPtr pOverlay); +static void set_colorkey(void); + +static void set_brightness(uint8_t brightness); +static void set_contrast(uint8_t contrast); +static void set_saturation(char saturation); +static void set_hue(uint8_t hue); +#if 0 +static void set_alpha(uint8_t alpha); +#endif + +/* IO Port access functions */ +static uint8_t getvideoreg(uint8_t reg) +{ + uint8_t ret; + inSISIDXREG(SISVID, reg, ret); + return (ret); +} + +static void setvideoreg(uint8_t reg, uint8_t data) +{ + outSISIDXREG(SISVID, reg, data); +} + +static void setvideoregmask(uint8_t reg, uint8_t data, uint8_t mask) +{ + uint8_t old; + + inSISIDXREG(SISVID, reg, old); + data = (data & mask) | (old & (~mask)); + outSISIDXREG(SISVID, reg, data); +} + +static void setsrregmask(uint8_t reg, uint8_t data, uint8_t mask) +{ + uint8_t old; + + inSISIDXREG(SISSR, reg, old); + data = (data & mask) | (old & (~mask)); + outSISIDXREG(SISSR, reg, data); +} + +/* vblank checking*/ +static uint8_t vblank_active_CRT1() +{ + /* this may be too simplistic? */ + return (inSISREG(SISINPSTAT) & 0x08); +} + +static uint8_t vblank_active_CRT2() +{ + uint8_t ret; + if (sis_vga_engine == SIS_315_VGA) { + inSISIDXREG(SISPART1, Index_310_CRT2_FC_VR, ret); + } else { + inSISIDXREG(SISPART1, Index_CRT2_FC_VR, ret); + } + return ((ret & 0x02) ^ 0x02); +} + + +unsigned int vixGetVersion(void) +{ + return (VIDIX_VERSION); +} + +static int find_chip(unsigned chip_id) +{ + unsigned i; + for (i = 0; i < sizeof(sis_card_ids) / sizeof(unsigned short); i++) { + if (chip_id == sis_card_ids[i]) + return i; + } + return -1; +} + +int vixProbe(int verbose, int force) +{ + pciinfo_t lst[MAX_PCI_DEVICES]; + unsigned i, num_pci; + int err; + + sis_verbose = verbose; + force = force; + err = pci_scan(lst, &num_pci); + if (err) { + printf("[SiS] Error occurred during pci scan: %s\n", strerror(err)); + return err; + } else if(!enable_app_io()){ + err = ENXIO; + for (i = 0; i < num_pci; i++) { + if (lst[i].vendor == VENDOR_SIS) { + int idx; + const char *dname; + idx = find_chip(lst[i].device); + if (idx == -1) + continue; + dname = pci_device_name(VENDOR_SIS, lst[i].device); + dname = dname ? dname : "Unknown chip"; + if (sis_verbose > 0) + printf("[SiS] Found chip: %s (0x%X)\n", + dname, lst[i].device); + sis_device_id = sis_cap.device_id = lst[i].device; + err = 0; + memcpy(&pci_info, &lst[i], sizeof(pciinfo_t)); + + sis_has_two_overlays = 0; + switch (sis_cap.device_id) { + case DEVICE_SIS_300: + case DEVICE_SIS_630_VGA: + sis_has_two_overlays = 1; + case DEVICE_SIS_540_VGA: + sis_vga_engine = SIS_300_VGA; + break; + case DEVICE_SIS_330: + case DEVICE_SIS_550_VGA: + sis_has_two_overlays = 1; + case DEVICE_SIS_315H: + case DEVICE_SIS_315: + case DEVICE_SIS_315PRO: + case DEVICE_SIS_650_VGA: + /* M650 & 651 have 2 overlays */ + /* JCP: I think this works, but not really tested yet */ + { + unsigned char CR5F; + unsigned char tempreg1, tempreg2; + + inSISIDXREG(SISCR, 0x5F, CR5F); + CR5F &= 0xf0; + andSISIDXREG(SISCR, 0x5c, 0x07); + inSISIDXREG(SISCR, 0x5c, tempreg1); + tempreg1 &= 0xf8; + setSISIDXREG(SISCR, 0x5c, 0x07, 0xf8); + inSISIDXREG(SISCR, 0x5c, tempreg2); + tempreg2 &= 0xf8; + if ((!tempreg1) || (tempreg2)) { + if (CR5F & 0x80) { + sis_has_two_overlays = 1; + } + } else { + sis_has_two_overlays = 1; /* ? */ + } + if (sis_has_two_overlays) { + if (sis_verbose > 0) + printf + ("[SiS] detected M650/651 with 2 overlays\n"); + } + } + sis_vga_engine = SIS_315_VGA; + break; + default: + /* should never get here */ + sis_vga_engine = UNKNOWN_VGA; + break; + } + } + } + } else { + err = EPERM; + } + + if (err && sis_verbose) { + printf("[SiS] Can't find chip\n"); + } else { + sis_probed = 1; + } + + return err; +} + +int vixInit(const char *args) +{ + uint8_t sr_data, cr_data, cr_data2; + char *env_overlay_crt; + + if (!sis_probed) { + printf("[SiS] driver was not probed but is being initialized\n"); + return (EINTR); + } + + /* JCP: this is WRONG. Need to coordinate w/ sisfb to use correct mem */ + /* map 16MB scary hack for now. */ + sis_mem_base = map_phys_mem(pci_info.base0, 0x1000000); + /* sis_reg_base = map_phys_mem(pci_info.base1, 0x20000); */ + sis_iobase = pci_info.base2 & 0xFFFC; + + /* would like to use fb ioctl - or some other method - here to get + current resolution. */ + inSISIDXREG(SISCR, 0x12, cr_data); + inSISIDXREG(SISCR, 0x07, cr_data2); + sis_screen_height = + ((cr_data & 0xff) | ((uint16_t) (cr_data2 & 0x02) << 7) | + ((uint16_t) (cr_data2 & 0x40) << 3) | ((uint16_t) (cr_data & 0x02) + << 9)) + 1; + + inSISIDXREG(SISSR, 0x0b, sr_data); + inSISIDXREG(SISCR, 0x01, cr_data); + sis_screen_width = (((cr_data & 0xff) | + ((uint16_t) (sr_data & 0x0C) << 6)) + 1) * 8; + + inSISIDXREG(SISSR, Index_SR_Graphic_Mode, sr_data); + if (sr_data & 0x20) /* interlaced mode */ + sis_vmode |= VMODE_INTERLACED; + +#if 0 /* getting back false data here... */ + /* CR9 bit 7 set = double scan active */ + inSISIDXREG(SISCR, 0x09, cr_data); + if (cr_data & 0x40) { + sis_vmode |= VMODE_DOUBLESCAN; + } +#endif + + /* JCP: eventually I'd like to replace this with a call to sisfb + SISFB_GET_INFO ioctl to get video bridge info. Not for now, + since it requires a very new and not widely distributed version. */ + sis_init_video_bridge(); + + env_overlay_crt = getenv("VIDIX_CRT"); + if (env_overlay_crt) { + int crt = atoi(env_overlay_crt); + if (crt == 1 || crt == 2) { + sis_overlay_on_crt1 = (crt == 1); + if (sis_verbose > 0) { + printf + ("[SiS] override: using overlay on CRT%d from VIDIX_CRT\n", + crt); + } + } + } + + return 0; +} + +void vixDestroy(void) +{ + /* unmap_phys_mem(sis_reg_base, 0x20000); */ + /* JCP: see above, hence also a hack. */ + unmap_phys_mem(sis_mem_base, 0x1000000); +} + +int vixGetCapability(vidix_capability_t * to) +{ + memcpy(to, &sis_cap, sizeof(vidix_capability_t)); + return 0; +} + +static int is_supported_fourcc(uint32_t fourcc) +{ + switch (fourcc) { + case IMGFMT_YV12: + case IMGFMT_I420: + case IMGFMT_UYVY: + case IMGFMT_YUY2: + case IMGFMT_RGB15: + case IMGFMT_RGB16: + return 1; + default: + return 0; + } +} + +int vixQueryFourcc(vidix_fourcc_t * to) +{ + if (is_supported_fourcc(to->fourcc)) { + to->depth = VID_DEPTH_8BPP | VID_DEPTH_16BPP | VID_DEPTH_32BPP; + to->flags = VID_CAP_EXPAND | VID_CAP_SHRINK | VID_CAP_COLORKEY; + return 0; + } else + to->depth = to->flags = 0; + return ENOSYS; +} + +static int bridge_in_slave_mode() +{ + unsigned char usScratchP1_00; + + if (!(sis_vbflags & VB_VIDEOBRIDGE)) + return 0; + + inSISIDXREG(SISPART1, 0x00, usScratchP1_00); + if (((sis_vga_engine == SIS_300_VGA) + && (usScratchP1_00 & 0xa0) == 0x20) + || ((sis_vga_engine == SIS_315_VGA) + && (usScratchP1_00 & 0x50) == 0x10)) { + return 1; + } else { + return 0; + } +} + +/* This does not handle X dual head mode, since 1) vidix doesn't support it + and 2) it doesn't make sense for other gfx drivers */ +static void set_dispmode() +{ + sis_bridge_is_slave = 0; + + if (bridge_in_slave_mode()) + sis_bridge_is_slave = 1; + + if ((sis_vbflags & VB_DISPMODE_MIRROR) || + (sis_bridge_is_slave && (sis_vbflags & DISPTYPE_DISP2))) { + if (sis_has_two_overlays) + sis_displaymode = DISPMODE_MIRROR; /* TW: CRT1+CRT2 (2 overlays) */ + else if (!sis_overlay_on_crt1) + sis_displaymode = DISPMODE_SINGLE2; + else + sis_displaymode = DISPMODE_SINGLE1; + } else { + if (sis_vbflags & DISPTYPE_DISP1) { + sis_displaymode = DISPMODE_SINGLE1; /* TW: CRT1 only */ + } else { + sis_displaymode = DISPMODE_SINGLE2; /* TW: CRT2 only */ + } + } +} + +static void set_disptype_regs() +{ + switch (sis_displaymode) { + case DISPMODE_SINGLE1: /* TW: CRT1 only */ + if (sis_verbose > 2) { + printf("[SiS] Setting up overlay on CRT1\n"); + } + if (sis_has_two_overlays) { + setsrregmask(0x06, 0x00, 0xc0); + setsrregmask(0x32, 0x00, 0xc0); + } else { + setsrregmask(0x06, 0x00, 0xc0); + setsrregmask(0x32, 0x00, 0xc0); + } + break; + case DISPMODE_SINGLE2: /* TW: CRT2 only */ + if (sis_verbose > 2) { + printf("[SiS] Setting up overlay on CRT2\n"); + } + if (sis_has_two_overlays) { + setsrregmask(0x06, 0x80, 0xc0); + setsrregmask(0x32, 0x80, 0xc0); + } else { + setsrregmask(0x06, 0x40, 0xc0); + setsrregmask(0x32, 0x40, 0xc0); + } + break; + case DISPMODE_MIRROR: /* TW: CRT1 + CRT2 */ + default: + if (sis_verbose > 2) { + printf("[SiS] Setting up overlay on CRT1 AND CRT2!\n"); + } + setsrregmask(0x06, 0x80, 0xc0); + setsrregmask(0x32, 0x80, 0xc0); + break; + } +} + +static void init_overlay() +{ + /* Initialize first overlay (CRT1) */ + + /* Write-enable video registers */ + setvideoregmask(Index_VI_Control_Misc2, 0x80, 0x81); + + /* Disable overlay */ + setvideoregmask(Index_VI_Control_Misc0, 0x00, 0x02); + + /* Disable bobEnable */ + setvideoregmask(Index_VI_Control_Misc1, 0x02, 0x02); + + /* Reset scale control and contrast */ + setvideoregmask(Index_VI_Scale_Control, 0x60, 0x60); + setvideoregmask(Index_VI_Contrast_Enh_Ctrl, 0x04, 0x1F); + + setvideoreg(Index_VI_Disp_Y_Buf_Preset_Low, 0x00); + setvideoreg(Index_VI_Disp_Y_Buf_Preset_Middle, 0x00); + setvideoreg(Index_VI_UV_Buf_Preset_Low, 0x00); + setvideoreg(Index_VI_UV_Buf_Preset_Middle, 0x00); + setvideoreg(Index_VI_Disp_Y_UV_Buf_Preset_High, 0x00); + setvideoreg(Index_VI_Play_Threshold_Low, 0x00); + setvideoreg(Index_VI_Play_Threshold_High, 0x00); + + /* may not want to init these here, could already be set to other + values by app? */ + setvideoregmask(Index_VI_Control_Misc2, 0x00, 0x01); + setvideoregmask(Index_VI_Contrast_Enh_Ctrl, 0x04, 0x07); + setvideoreg(Index_VI_Brightness, 0x20); + if (sis_vga_engine == SIS_315_VGA) { + setvideoreg(Index_VI_Hue, 0x00); + setvideoreg(Index_VI_Saturation, 0x00); + } + + /* Initialize second overlay (CRT2) */ + if (sis_has_two_overlays) { + /* Write-enable video registers */ + setvideoregmask(Index_VI_Control_Misc2, 0x81, 0x81); + + /* Disable overlay */ + setvideoregmask(Index_VI_Control_Misc0, 0x00, 0x02); + + /* Disable bobEnable */ + setvideoregmask(Index_VI_Control_Misc1, 0x02, 0x02); + + /* Reset scale control and contrast */ + setvideoregmask(Index_VI_Scale_Control, 0x60, 0x60); + setvideoregmask(Index_VI_Contrast_Enh_Ctrl, 0x04, 0x1F); + + setvideoreg(Index_VI_Disp_Y_Buf_Preset_Low, 0x00); + setvideoreg(Index_VI_Disp_Y_Buf_Preset_Middle, 0x00); + setvideoreg(Index_VI_UV_Buf_Preset_Low, 0x00); + setvideoreg(Index_VI_UV_Buf_Preset_Middle, 0x00); + setvideoreg(Index_VI_Disp_Y_UV_Buf_Preset_High, 0x00); + setvideoreg(Index_VI_Play_Threshold_Low, 0x00); + setvideoreg(Index_VI_Play_Threshold_High, 0x00); + + setvideoregmask(Index_VI_Control_Misc2, 0x01, 0x01); + setvideoregmask(Index_VI_Contrast_Enh_Ctrl, 0x04, 0x07); + setvideoreg(Index_VI_Brightness, 0x20); + if (sis_vga_engine == SIS_315_VGA) { + setvideoreg(Index_VI_Hue, 0x00); + setvideoreg(Index_VI_Saturation, 0x00); + } + } +} + +int vixConfigPlayback(vidix_playback_t * info) +{ + SISOverlayRec overlay; + int srcOffsetX = 0, srcOffsetY = 0; + int sx, sy; + int index = 0, iscrt2 = 0; + int total_size; + + short src_w, drw_w; + short src_h, drw_h; + short src_x, drw_x; + short src_y, drw_y; + long dga_offset; + int pitch; + unsigned int i; + + if (!is_supported_fourcc(info->fourcc)) + return -1; + + /* set chipset/engine.dependent config info */ + /* which CRT to use, etc.? */ + switch (sis_vga_engine) { + case SIS_315_VGA: + sis_shift_value = 1; + sis_equal.cap |= VEQ_CAP_SATURATION | VEQ_CAP_HUE; + break; + case SIS_300_VGA: + default: + sis_shift_value = 2; + break; + } + + sis_displaymode = DISPMODE_SINGLE1; /* xV driver code in set_dispmode() */ + set_dispmode(); + + set_disptype_regs(); + + init_overlay(); + + /* get basic dimension info */ + src_x = info->src.x; + src_y = info->src.y; + src_w = info->src.w; + src_h = info->src.h; + + drw_x = info->dest.x; + drw_y = info->dest.y; + drw_w = info->dest.w; + drw_h = info->dest.h; + + switch (info->fourcc) { + case IMGFMT_YV12: + case IMGFMT_I420: + pitch = (src_w + 7) & ~7; + total_size = (pitch * src_h * 3) >> 1; + break; + case IMGFMT_YUY2: + case IMGFMT_UYVY: + case IMGFMT_RGB15: + case IMGFMT_RGB16: + pitch = ((src_w << 1) + 3) & ~3; + total_size = pitch * src_h; + break; + default: + return -1; + } + + /* "allocate" memory for overlay! */ + /* start at 8MB = sisfb's "dri reserved space" - + really shouldn't hardcode though */ + /* XXX: JCP - this can use the sisfb FBIO_ALLOC ioctl to safely + allocate "video heap" memory... */ + dga_offset = 0x800000; + + /* use 7MB for now. need to calc/get real info from sisfb? */ + /* this can result in a LOT of frames - probably not necessary */ + info->num_frames = 0x700000 / (total_size * 2); + if (info->num_frames > VID_PLAY_MAXFRAMES) + info->num_frames = VID_PLAY_MAXFRAMES; + + info->dga_addr = sis_mem_base + dga_offset; + info->dest.pitch.y = 16; + info->dest.pitch.u = 16; + info->dest.pitch.v = 16; + info->offset.y = 0; + info->offset.u = 0; + info->offset.v = 0; + info->frame_size = (total_size * 2); /* why times 2 ? */ + for (i = 0; i < info->num_frames; i++) { + info->offsets[i] = info->frame_size * i; + /* save ptrs to mem buffers */ + sis_frames[i] = (dga_offset + info->offsets[i]); + } + + memset(&overlay, 0, sizeof(overlay)); + overlay.pixelFormat = sis_format = info->fourcc; + overlay.pitch = overlay.origPitch = pitch; + + + overlay.keyOP = (sis_grkey.ckey.op == CKEY_TRUE ? + VI_ROP_DestKey : VI_ROP_Always); + + overlay.bobEnable = 0x00; + + overlay.SCREENheight = sis_screen_height; + + /* probably will not support X virtual screen > phys very well? */ + overlay.dstBox.x1 = drw_x; /* - pScrn->frameX0; */ + overlay.dstBox.x2 = drw_x + drw_w; /* - pScrn->frameX0; ??? */ + overlay.dstBox.y1 = drw_y; /* - pScrn->frameY0; */ + overlay.dstBox.y2 = drw_y + drw_h; /* - pScrn->frameY0; ??? */ + + if ((overlay.dstBox.x1 > overlay.dstBox.x2) || + (overlay.dstBox.y1 > overlay.dstBox.y2)) + return -1; + + if ((overlay.dstBox.x2 < 0) || (overlay.dstBox.y2 < 0)) + return -1; + + if (overlay.dstBox.x1 < 0) { + srcOffsetX = src_w * (-overlay.dstBox.x1) / drw_w; + overlay.dstBox.x1 = 0; + } + if (overlay.dstBox.y1 < 0) { + srcOffsetY = src_h * (-overlay.dstBox.y1) / drw_h; + overlay.dstBox.y1 = 0; + } + + switch (info->fourcc) { + case IMGFMT_YV12: + info->dest.pitch.y = 16; + sx = (src_x + srcOffsetX) & ~7; + sy = (src_y + srcOffsetY) & ~1; + info->offset.y = sis_Yoff = sx + sy * pitch; + /* JCP: NOTE reversed u & v here! Not sure why this is needed. + maybe mplayer & sis define U & V differently?? */ + info->offset.u = sis_Voff = + src_h * pitch + ((sx + sy * pitch / 2) >> 1); + info->offset.v = sis_Uoff = + src_h * pitch * 5 / 4 + ((sx + sy * pitch / 2) >> 1); + + overlay.PSY = (sis_frames[0] + sis_Yoff) >> sis_shift_value; + overlay.PSV = (sis_frames[0] + sis_Voff) >> sis_shift_value; + overlay.PSU = (sis_frames[0] + sis_Uoff) >> sis_shift_value; + break; + case IMGFMT_I420: + sx = (src_x + srcOffsetX) & ~7; + sy = (src_y + srcOffsetY) & ~1; + info->offset.y = sis_Yoff = sx + sy * pitch; + /* JCP: see above... */ + info->offset.u = sis_Voff = + src_h * pitch * 5 / 4 + ((sx + sy * pitch / 2) >> 1); + info->offset.v = sis_Uoff = + src_h * pitch + ((sx + sy * pitch / 2) >> 1); + + overlay.PSY = (sis_frames[0] + sis_Yoff) >> sis_shift_value; + overlay.PSV = (sis_frames[0] + sis_Voff) >> sis_shift_value; + overlay.PSU = (sis_frames[0] + sis_Uoff) >> sis_shift_value; + break; + case IMGFMT_YUY2: + case IMGFMT_UYVY: + case IMGFMT_RGB16: + case IMGFMT_RGB15: + default: + sx = (src_x + srcOffsetX) & ~1; + sy = (src_y + srcOffsetY); + info->offset.y = sis_Yoff = sx * 2 + sy * pitch; + + overlay.PSY = (sis_frames[0] + sis_Yoff) >> sis_shift_value; + break; + } + + /* FIXME: is it possible that srcW < 0? */ + overlay.srcW = src_w - (sx - src_x); + overlay.srcH = src_h - (sy - src_y); + + /* JCP: what to do about this? */ +#if 0 + if ((pPriv->oldx1 != overlay.dstBox.x1) || + (pPriv->oldx2 != overlay.dstBox.x2) || + (pPriv->oldy1 != overlay.dstBox.y1) || + (pPriv->oldy2 != overlay.dstBox.y2)) { + pPriv->mustwait = 1; + pPriv->oldx1 = overlay.dstBox.x1; + pPriv->oldx2 = overlay.dstBox.x2; + pPriv->oldy1 = overlay.dstBox.y1; + pPriv->oldy2 = overlay.dstBox.y2; + } +#endif + + /* set merge line buffer */ + merge_line_buf(overlay.srcW > 384); + + /* calculate line buffer length */ + set_line_buf_size(&overlay); + + if (sis_displaymode == DISPMODE_SINGLE2) { + if (sis_has_two_overlays) { + /* TW: On chips with two overlays we use + * overlay 2 for CRT2 */ + index = 1; + iscrt2 = 1; + } else { + /* TW: On chips with only one overlay we + * use that only overlay for CRT2 */ + index = 0; + iscrt2 = 1; + } + overlay.VBlankActiveFunc = vblank_active_CRT2; + /* overlay.GetScanLineFunc = get_scanline_CRT2; */ + } else { + index = 0; + iscrt2 = 0; + overlay.VBlankActiveFunc = vblank_active_CRT1; + /* overlay.GetScanLineFunc = get_scanline_CRT1; */ + } + + /* calc scale factor (to use below) */ + calc_scale_factor(&overlay, index, iscrt2); + + /* Select video1 (used for CRT1) or video2 (used for CRT2) */ + setvideoregmask(Index_VI_Control_Misc2, index, 0x01); + + set_format(&overlay); + + set_colorkey(); + + vixPlaybackSetEq(&sis_equal); + + /* set up video overlay registers */ + set_overlay(&overlay, index); + + /* prevent badness if bits are not at default setting */ + setvideoregmask(Index_VI_Control_Misc1, 0x00, 0x01); + setvideoregmask(Index_VI_Control_Misc2, 0x00, 0x04); + + /* JCP: Xv driver implementation loops back over above code to + setup mirror CRT2 */ + + return 0; +} + +int vixPlaybackOn(void) +{ + setvideoregmask(Index_VI_Control_Misc0, 0x02, 0x02); + return 0; +} + +int vixPlaybackOff(void) +{ + unsigned char sridx, cridx; + sridx = inSISREG(SISSR); + cridx = inSISREG(SISCR); + close_overlay(); + outSISREG(SISSR, sridx); + outSISREG(SISCR, cridx); + + return 0; +} + +int vixPlaybackFrameSelect(unsigned int frame) +{ + uint8_t data; + int index = 0; + uint32_t PSY; + + if (sis_displaymode == DISPMODE_SINGLE2 && sis_has_two_overlays) { + index = 1; + } + + PSY = (sis_frames[frame] + sis_Yoff) >> sis_shift_value; + + /* Unlock address registers */ + data = getvideoreg(Index_VI_Control_Misc1); + setvideoreg(Index_VI_Control_Misc1, data | 0x20); + /* TEST: Is this required? */ + setvideoreg(Index_VI_Control_Misc1, data | 0x20); + /* TEST end */ + /* TEST: Is this required? */ + if (sis_vga_engine == SIS_315_VGA) + setvideoreg(Index_VI_Control_Misc3, 0x00); + /* TEST end */ + + /* set Y start address */ + setvideoreg(Index_VI_Disp_Y_Buf_Start_Low, (uint8_t) (PSY)); + setvideoreg(Index_VI_Disp_Y_Buf_Start_Middle, (uint8_t) ((PSY) >> 8)); + setvideoreg(Index_VI_Disp_Y_Buf_Start_High, (uint8_t) ((PSY) >> 16)); + /* set 310/325 series overflow bits for Y plane */ + if (sis_vga_engine == SIS_315_VGA) { + setvideoreg(Index_VI_Y_Buf_Start_Over, + ((uint8_t) ((PSY) >> 24) & 0x01)); + } + + /* Set U/V data if using plane formats */ + if ((sis_format == IMGFMT_YV12) || (sis_format == IMGFMT_I420)) { + + uint32_t PSU, PSV; + + PSU = (sis_frames[frame] + sis_Uoff) >> sis_shift_value; + PSV = (sis_frames[frame] + sis_Voff) >> sis_shift_value; + + /* set U/V start address */ + setvideoreg(Index_VI_U_Buf_Start_Low, (uint8_t) PSU); + setvideoreg(Index_VI_U_Buf_Start_Middle, (uint8_t) (PSU >> 8)); + setvideoreg(Index_VI_U_Buf_Start_High, (uint8_t) (PSU >> 16)); + + setvideoreg(Index_VI_V_Buf_Start_Low, (uint8_t) PSV); + setvideoreg(Index_VI_V_Buf_Start_Middle, (uint8_t) (PSV >> 8)); + setvideoreg(Index_VI_V_Buf_Start_High, (uint8_t) (PSV >> 16)); + + /* 310/325 series overflow bits */ + if (sis_vga_engine == SIS_315_VGA) { + setvideoreg(Index_VI_U_Buf_Start_Over, + ((uint8_t) (PSU >> 24) & 0x01)); + setvideoreg(Index_VI_V_Buf_Start_Over, + ((uint8_t) (PSV >> 24) & 0x01)); + } + } + + if (sis_vga_engine == SIS_315_VGA) { + /* Trigger register copy for 310 series */ + setvideoreg(Index_VI_Control_Misc3, 1 << index); + } + + /* Lock the address registers */ + setvideoregmask(Index_VI_Control_Misc1, 0x00, 0x20); + + return 0; +} + +int vixGetGrKeys(vidix_grkey_t * grkey) +{ + memcpy(grkey, &sis_grkey, sizeof(vidix_grkey_t)); + return 0; +} + +int vixSetGrKeys(const vidix_grkey_t * grkey) +{ + memcpy(&sis_grkey, grkey, sizeof(vidix_grkey_t)); + set_colorkey(); + return 0; +} + +int vixPlaybackGetEq(vidix_video_eq_t * eq) +{ + memcpy(eq, &sis_equal, sizeof(vidix_video_eq_t)); + return 0; +} + +int vixPlaybackSetEq(const vidix_video_eq_t * eq) +{ + int br, sat, cr, hue; + if (eq->cap & VEQ_CAP_BRIGHTNESS) + sis_equal.brightness = eq->brightness; + if (eq->cap & VEQ_CAP_CONTRAST) + sis_equal.contrast = eq->contrast; + if (eq->cap & VEQ_CAP_SATURATION) + sis_equal.saturation = eq->saturation; + if (eq->cap & VEQ_CAP_HUE) + sis_equal.hue = eq->hue; + if (eq->cap & VEQ_CAP_RGB_INTENSITY) { + sis_equal.red_intensity = eq->red_intensity; + sis_equal.green_intensity = eq->green_intensity; + sis_equal.blue_intensity = eq->blue_intensity; + } + sis_equal.flags = eq->flags; + + cr = (sis_equal.contrast + 1000) * 7 / 2000; + if (cr < 0) + cr = 0; + if (cr > 7) + cr = 7; + + br = sis_equal.brightness * 127 / 1000; + if (br < -128) + br = -128; + if (br > 127) + br = 127; + + sat = (sis_equal.saturation * 7) / 1000; + if (sat < -7) + sat = -7; + if (sat > 7) + sat = 7; + + hue = sis_equal.hue * 7 / 1000; + if (hue < -8) + hue = -8; + if (hue > 7) + hue = 7; + + set_brightness(br); + set_contrast(cr); + if (sis_vga_engine == SIS_315_VGA) { + set_saturation(sat); + set_hue(hue); + } + + return 0; +} + +static void set_overlay(SISOverlayPtr pOverlay, int index) +{ + uint16_t pitch = 0; + uint8_t h_over = 0, v_over = 0; + uint16_t top, bottom, left, right; + uint16_t screenX = sis_screen_width; + uint16_t screenY = sis_screen_height; + uint8_t data; + uint32_t watchdog; + + top = pOverlay->dstBox.y1; + bottom = pOverlay->dstBox.y2; + if (bottom > screenY) { + bottom = screenY; + } + + left = pOverlay->dstBox.x1; + right = pOverlay->dstBox.x2; + if (right > screenX) { + right = screenX; + } + + /* JCP: these aren't really tested... */ + /* TW: DoubleScan modes require Y coordinates * 2 */ + if (sis_vmode & VMODE_DOUBLESCAN) { + top <<= 1; + bottom <<= 1; + } + /* TW: Interlace modes require Y coordinates / 2 */ + if (sis_vmode & VMODE_INTERLACED) { + top >>= 1; + bottom >>= 1; + } + + h_over = (((left >> 8) & 0x0f) | ((right >> 4) & 0xf0)); + v_over = (((top >> 8) & 0x0f) | ((bottom >> 4) & 0xf0)); + + pitch = pOverlay->pitch >> sis_shift_value; + + /* set line buffer size */ + setvideoreg(Index_VI_Line_Buffer_Size, pOverlay->lineBufSize); + + /* set color key mode */ + setvideoregmask(Index_VI_Key_Overlay_OP, pOverlay->keyOP, 0x0F); + + /* TW: We don't have to wait for vertical retrace in all cases */ + /* JCP: be safe for now. */ + if (1 /*pPriv->mustwait */ ) { + watchdog = WATCHDOG_DELAY; + while (pOverlay->VBlankActiveFunc() && --watchdog); + watchdog = WATCHDOG_DELAY; + while ((!pOverlay->VBlankActiveFunc()) && --watchdog); + if (!watchdog && sis_verbose > 0) { + printf("[SiS]: timed out waiting for vertical retrace\n"); + } + } + + /* Unlock address registers */ + data = getvideoreg(Index_VI_Control_Misc1); + setvideoreg(Index_VI_Control_Misc1, data | 0x20); + /* TEST: Is this required? */ + setvideoreg(Index_VI_Control_Misc1, data | 0x20); + /* TEST end */ + + /* TEST: Is this required? */ + if (sis_vga_engine == SIS_315_VGA) + setvideoreg(Index_VI_Control_Misc3, 0x00); + /* TEST end */ + + /* Set Y buf pitch */ + setvideoreg(Index_VI_Disp_Y_Buf_Pitch_Low, (uint8_t) (pitch)); + setvideoregmask(Index_VI_Disp_Y_UV_Buf_Pitch_Middle, + (uint8_t) (pitch >> 8), 0x0f); + + /* Set Y start address */ + setvideoreg(Index_VI_Disp_Y_Buf_Start_Low, (uint8_t) (pOverlay->PSY)); + setvideoreg(Index_VI_Disp_Y_Buf_Start_Middle, + (uint8_t) ((pOverlay->PSY) >> 8)); + setvideoreg(Index_VI_Disp_Y_Buf_Start_High, + (uint8_t) ((pOverlay->PSY) >> 16)); + + /* set 310/325 series overflow bits for Y plane */ + if (sis_vga_engine == SIS_315_VGA) { + setvideoreg(Index_VI_Disp_Y_Buf_Pitch_High, + (uint8_t) (pitch >> 12)); + setvideoreg(Index_VI_Y_Buf_Start_Over, + ((uint8_t) ((pOverlay->PSY) >> 24) & 0x01)); + } + + /* Set U/V data if using plane formats */ + if ((pOverlay->pixelFormat == IMGFMT_YV12) || + (pOverlay->pixelFormat == IMGFMT_I420)) { + + uint32_t PSU, PSV; + + PSU = pOverlay->PSU; + PSV = pOverlay->PSV; + + /* Set U/V pitch */ + setvideoreg(Index_VI_Disp_UV_Buf_Pitch_Low, + (uint8_t) (pitch >> 1)); + setvideoregmask(Index_VI_Disp_Y_UV_Buf_Pitch_Middle, + (uint8_t) (pitch >> 5), 0xf0); + + /* set U/V start address */ + setvideoreg(Index_VI_U_Buf_Start_Low, (uint8_t) PSU); + setvideoreg(Index_VI_U_Buf_Start_Middle, (uint8_t) (PSU >> 8)); + setvideoreg(Index_VI_U_Buf_Start_High, (uint8_t) (PSU >> 16)); + + setvideoreg(Index_VI_V_Buf_Start_Low, (uint8_t) PSV); + setvideoreg(Index_VI_V_Buf_Start_Middle, (uint8_t) (PSV >> 8)); + setvideoreg(Index_VI_V_Buf_Start_High, (uint8_t) (PSV >> 16)); + + /* 310/325 series overflow bits */ + if (sis_vga_engine == SIS_315_VGA) { + setvideoreg(Index_VI_Disp_UV_Buf_Pitch_High, + (uint8_t) (pitch >> 13)); + setvideoreg(Index_VI_U_Buf_Start_Over, + ((uint8_t) (PSU >> 24) & 0x01)); + setvideoreg(Index_VI_V_Buf_Start_Over, + ((uint8_t) (PSV >> 24) & 0x01)); + } + } + + if (sis_vga_engine == SIS_315_VGA) { + /* Trigger register copy for 310 series */ + setvideoreg(Index_VI_Control_Misc3, 1 << index); + } + + /* set scale factor */ + setvideoreg(Index_VI_Hor_Post_Up_Scale_Low, + (uint8_t) (pOverlay->HUSF)); + setvideoreg(Index_VI_Hor_Post_Up_Scale_High, + (uint8_t) ((pOverlay->HUSF) >> 8)); + setvideoreg(Index_VI_Ver_Up_Scale_Low, (uint8_t) (pOverlay->VUSF)); + setvideoreg(Index_VI_Ver_Up_Scale_High, + (uint8_t) ((pOverlay->VUSF) >> 8)); + + setvideoregmask(Index_VI_Scale_Control, (pOverlay->IntBit << 3) + | (pOverlay->wHPre), 0x7f); + + /* set destination window position */ + setvideoreg(Index_VI_Win_Hor_Disp_Start_Low, (uint8_t) left); + setvideoreg(Index_VI_Win_Hor_Disp_End_Low, (uint8_t) right); + setvideoreg(Index_VI_Win_Hor_Over, (uint8_t) h_over); + + setvideoreg(Index_VI_Win_Ver_Disp_Start_Low, (uint8_t) top); + setvideoreg(Index_VI_Win_Ver_Disp_End_Low, (uint8_t) bottom); + setvideoreg(Index_VI_Win_Ver_Over, (uint8_t) v_over); + + setvideoregmask(Index_VI_Control_Misc1, pOverlay->bobEnable, 0x1a); + + /* Lock the address registers */ + setvideoregmask(Index_VI_Control_Misc1, 0x00, 0x20); +} + + +/* TW: Overlay MUST NOT be switched off while beam is over it */ +static void close_overlay() +{ + uint32_t watchdog; + + if ((sis_displaymode == DISPMODE_SINGLE2) || + (sis_displaymode == DISPMODE_MIRROR)) { + if (sis_has_two_overlays) { + setvideoregmask(Index_VI_Control_Misc2, 0x01, 0x01); + watchdog = WATCHDOG_DELAY; + while (vblank_active_CRT2() && --watchdog); + watchdog = WATCHDOG_DELAY; + while ((!vblank_active_CRT2()) && --watchdog); + setvideoregmask(Index_VI_Control_Misc0, 0x00, 0x02); + watchdog = WATCHDOG_DELAY; + while (vblank_active_CRT2() && --watchdog); + watchdog = WATCHDOG_DELAY; + while ((!vblank_active_CRT2()) && --watchdog); + } else if (sis_displaymode == DISPMODE_SINGLE2) { + setvideoregmask(Index_VI_Control_Misc2, 0x00, 0x01); + watchdog = WATCHDOG_DELAY; + while (vblank_active_CRT1() && --watchdog); + watchdog = WATCHDOG_DELAY; + while ((!vblank_active_CRT1()) && --watchdog); + setvideoregmask(Index_VI_Control_Misc0, 0x00, 0x02); + watchdog = WATCHDOG_DELAY; + while (vblank_active_CRT1() && --watchdog); + watchdog = WATCHDOG_DELAY; + while ((!vblank_active_CRT1()) && --watchdog); + } + } + if ((sis_displaymode == DISPMODE_SINGLE1) || + (sis_displaymode == DISPMODE_MIRROR)) { + setvideoregmask(Index_VI_Control_Misc2, 0x00, 0x01); + watchdog = WATCHDOG_DELAY; + while (vblank_active_CRT1() && --watchdog); + watchdog = WATCHDOG_DELAY; + while ((!vblank_active_CRT1()) && --watchdog); + setvideoregmask(Index_VI_Control_Misc0, 0x00, 0x02); + watchdog = WATCHDOG_DELAY; + while (vblank_active_CRT1() && --watchdog); + watchdog = WATCHDOG_DELAY; + while ((!vblank_active_CRT1()) && --watchdog); + } +} + + +static void +calc_scale_factor(SISOverlayPtr pOverlay, int index, int iscrt2) +{ + uint32_t i = 0, mult = 0; + int flag = 0; + + int dstW = pOverlay->dstBox.x2 - pOverlay->dstBox.x1; + int dstH = pOverlay->dstBox.y2 - pOverlay->dstBox.y1; + int srcW = pOverlay->srcW; + int srcH = pOverlay->srcH; + /* uint16_t LCDheight = pSiS->LCDheight; */ + int srcPitch = pOverlay->origPitch; + int origdstH = dstH; + + /* get rid of warnings for now */ + index = index; + iscrt2 = iscrt2; + +#if 0 /* JCP: don't bother with this for now. */ + /* TW: Stretch image due to idiotic LCD "auto"-scaling on LVDS (and 630+301B) */ + if (pSiS->VBFlags & CRT2_LCD) { + if (sis_bridge_is_slave) { + if (pSiS->VBFlags & VB_LVDS) { + dstH = (dstH * LCDheight) / pOverlay->SCREENheight; + } else if ((sis_vga_engine == SIS_300_VGA) && + (pSiS-> + VBFlags & (VB_301B | VB_302B | VB_301LV | + VB_302LV))) { + dstH = (dstH * LCDheight) / pOverlay->SCREENheight; + } + } else if (iscrt2) { + if (pSiS->VBFlags & VB_LVDS) { + dstH = (dstH * LCDheight) / pOverlay->SCREENheight; + if (sis_displaymode == DISPMODE_MIRROR) + flag = 1; + } else if ((sis_vga_engine == SIS_300_VGA) && + (pSiS-> + VBFlags & (VB_301B | VB_302B | VB_301LV | + VB_302LV))) { + dstH = (dstH * LCDheight) / pOverlay->SCREENheight; + if (sis_displaymode == DISPMODE_MIRROR) + flag = 1; + } + } + } +#endif + + /* TW: For double scan modes, we need to double the height + * (Perhaps we also need to scale LVDS, but I'm not sure.) + * On 310/325 series, we need to double the width as well. + * Interlace mode vice versa. + */ + if (sis_vmode & VMODE_DOUBLESCAN) { + dstH = origdstH << 1; + flag = 0; + if (sis_vga_engine == SIS_315_VGA) { + dstW <<= 1; + } + } + if (sis_vmode & VMODE_INTERLACED) { + dstH = origdstH >> 1; + flag = 0; + } + + if (dstW < OVERLAY_MIN_WIDTH) + dstW = OVERLAY_MIN_WIDTH; + if (dstW == srcW) { + pOverlay->HUSF = 0x00; + pOverlay->IntBit = 0x05; + pOverlay->wHPre = 0; + } else if (dstW > srcW) { + dstW += 2; + pOverlay->HUSF = (srcW << 16) / dstW; + pOverlay->IntBit = 0x04; + pOverlay->wHPre = 0; + } else { + int tmpW = dstW; + + /* TW: It seems, the hardware can't scale below factor .125 (=1/8) if the + pitch isn't a multiple of 256. + TODO: Test this on the 310/325 series! + */ + if ((srcPitch % 256) || (srcPitch < 256)) { + if (((dstW * 1000) / srcW) < 125) + dstW = tmpW = ((srcW * 125) / 1000) + 1; + } + + i = 0; + pOverlay->IntBit = 0x01; + while (srcW >= tmpW) { + tmpW <<= 1; + i++; + } + pOverlay->wHPre = (uint8_t) (i - 1); + dstW <<= (i - 1); + if ((srcW % dstW)) + pOverlay->HUSF = ((srcW - dstW) << 16) / dstW; + else + pOverlay->HUSF = 0x00; + } + + if (dstH < OVERLAY_MIN_HEIGHT) + dstH = OVERLAY_MIN_HEIGHT; + if (dstH == srcH) { + pOverlay->VUSF = 0x00; + pOverlay->IntBit |= 0x0A; + } else if (dstH > srcH) { + dstH += 0x02; + pOverlay->VUSF = (srcH << 16) / dstH; + pOverlay->IntBit |= 0x08; + } else { + uint32_t realI; + + i = realI = srcH / dstH; + pOverlay->IntBit |= 0x02; + + if (i < 2) { + pOverlay->VUSF = ((srcH - dstH) << 16) / dstH; + /* TW: Needed for LCD-scaling modes */ + if ((flag) && (mult = (srcH / origdstH)) >= 2) + pOverlay->pitch /= mult; + } else { +#if 0 + if (((pOverlay->bobEnable & 0x08) == 0x00) && + (((srcPitch * i) >> 2) > 0xFFF)) { + pOverlay->bobEnable |= 0x08; + srcPitch >>= 1; + } +#endif + if (((srcPitch * i) >> 2) > 0xFFF) { + i = (0xFFF * 2 / srcPitch); + pOverlay->VUSF = 0xFFFF; + } else { + dstH = i * dstH; + if (srcH % dstH) + pOverlay->VUSF = ((srcH - dstH) << 16) / dstH; + else + pOverlay->VUSF = 0x00; + } + /* set video frame buffer offset */ + pOverlay->pitch = (uint16_t) (srcPitch * i); + } + } +} + +static void set_line_buf_size(SISOverlayPtr pOverlay) +{ + uint8_t preHIDF; + uint32_t i; + uint32_t line = pOverlay->srcW; + + if ((pOverlay->pixelFormat == IMGFMT_YV12) || + (pOverlay->pixelFormat == IMGFMT_I420)) { + preHIDF = pOverlay->wHPre & 0x07; + switch (preHIDF) { + case 3: + if ((line & 0xffffff00) == line) + i = (line >> 8); + else + i = (line >> 8) + 1; + pOverlay->lineBufSize = (uint8_t) (i * 32 - 1); + break; + case 4: + if ((line & 0xfffffe00) == line) + i = (line >> 9); + else + i = (line >> 9) + 1; + pOverlay->lineBufSize = (uint8_t) (i * 64 - 1); + break; + case 5: + if ((line & 0xfffffc00) == line) + i = (line >> 10); + else + i = (line >> 10) + 1; + pOverlay->lineBufSize = (uint8_t) (i * 128 - 1); + break; + case 6: + if ((line & 0xfffff800) == line) + i = (line >> 11); + else + i = (line >> 11) + 1; + pOverlay->lineBufSize = (uint8_t) (i * 256 - 1); + break; + default: + if ((line & 0xffffff80) == line) + i = (line >> 7); + else + i = (line >> 7) + 1; + pOverlay->lineBufSize = (uint8_t) (i * 16 - 1); + break; + } + } else { /* YUV2, UYVY */ + if ((line & 0xffffff8) == line) + i = (line >> 3); + else + i = (line >> 3) + 1; + pOverlay->lineBufSize = (uint8_t) (i - 1); + } +} + +static void merge_line_buf(int enable) +{ + if (enable) { + switch (sis_displaymode) { + case DISPMODE_SINGLE1: + if (sis_has_two_overlays) { + /* dual line merge */ + setvideoregmask(Index_VI_Control_Misc2, 0x10, 0x11); + setvideoregmask(Index_VI_Control_Misc1, 0x00, 0x04); + } else { + setvideoregmask(Index_VI_Control_Misc2, 0x10, 0x11); + setvideoregmask(Index_VI_Control_Misc1, 0x00, 0x04); + } + break; + case DISPMODE_SINGLE2: + if (sis_has_two_overlays) { + /* line merge */ + setvideoregmask(Index_VI_Control_Misc2, 0x01, 0x11); + setvideoregmask(Index_VI_Control_Misc1, 0x04, 0x04); + } else { + setvideoregmask(Index_VI_Control_Misc2, 0x10, 0x11); + setvideoregmask(Index_VI_Control_Misc1, 0x00, 0x04); + } + break; + case DISPMODE_MIRROR: + default: + /* line merge */ + setvideoregmask(Index_VI_Control_Misc2, 0x00, 0x11); + setvideoregmask(Index_VI_Control_Misc1, 0x04, 0x04); + if (sis_has_two_overlays) { + /* line merge */ + setvideoregmask(Index_VI_Control_Misc2, 0x01, 0x11); + setvideoregmask(Index_VI_Control_Misc1, 0x04, 0x04); + } + break; + } + } else { + switch (sis_displaymode) { + case DISPMODE_SINGLE1: + setvideoregmask(Index_VI_Control_Misc2, 0x00, 0x11); + setvideoregmask(Index_VI_Control_Misc1, 0x00, 0x04); + break; + case DISPMODE_SINGLE2: + if (sis_has_two_overlays) { + setvideoregmask(Index_VI_Control_Misc2, 0x01, 0x11); + setvideoregmask(Index_VI_Control_Misc1, 0x00, 0x04); + } else { + setvideoregmask(Index_VI_Control_Misc2, 0x00, 0x11); + setvideoregmask(Index_VI_Control_Misc1, 0x00, 0x04); + } + break; + case DISPMODE_MIRROR: + default: + setvideoregmask(Index_VI_Control_Misc2, 0x00, 0x11); + setvideoregmask(Index_VI_Control_Misc1, 0x00, 0x04); + if (sis_has_two_overlays) { + setvideoregmask(Index_VI_Control_Misc2, 0x01, 0x11); + setvideoregmask(Index_VI_Control_Misc1, 0x00, 0x04); + } + break; + } + } +} + + +static void set_format(SISOverlayPtr pOverlay) +{ + uint8_t fmt; + + switch (pOverlay->pixelFormat) { + case IMGFMT_YV12: + case IMGFMT_I420: + fmt = 0x0c; + break; + case IMGFMT_YUY2: + fmt = 0x28; + break; + case IMGFMT_UYVY: + fmt = 0x08; + break; + case IMGFMT_RGB15: /* D[5:4] : 00 RGB555, 01 RGB 565 */ + fmt = 0x00; + break; + case IMGFMT_RGB16: + fmt = 0x10; + break; + default: + fmt = 0x00; + break; + } + setvideoregmask(Index_VI_Control_Misc0, fmt, 0x7c); +} + +static void set_colorkey() +{ + uint8_t r, g, b; + + b = (uint8_t) sis_grkey.ckey.blue; + g = (uint8_t) sis_grkey.ckey.green; + r = (uint8_t) sis_grkey.ckey.red; + + /* set color key mode */ + setvideoregmask(Index_VI_Key_Overlay_OP, + sis_grkey.ckey.op == CKEY_TRUE ? + VI_ROP_DestKey : VI_ROP_Always, 0x0F); + + /* set colorkey values */ + setvideoreg(Index_VI_Overlay_ColorKey_Blue_Min, (uint8_t) b); + setvideoreg(Index_VI_Overlay_ColorKey_Green_Min, (uint8_t) g); + setvideoreg(Index_VI_Overlay_ColorKey_Red_Min, (uint8_t) r); + + setvideoreg(Index_VI_Overlay_ColorKey_Blue_Max, (uint8_t) b); + setvideoreg(Index_VI_Overlay_ColorKey_Green_Max, (uint8_t) g); + setvideoreg(Index_VI_Overlay_ColorKey_Red_Max, (uint8_t) r); +} + +static void set_brightness(uint8_t brightness) +{ + setvideoreg(Index_VI_Brightness, brightness); +} + +static void set_contrast(uint8_t contrast) +{ + setvideoregmask(Index_VI_Contrast_Enh_Ctrl, contrast, 0x07); +} + +/* Next 3 functions are 310/325 series only */ + +static void set_saturation(char saturation) +{ + uint8_t temp = 0; + + if (saturation < 0) { + temp |= 0x88; + saturation = -saturation; + } + temp |= (saturation & 0x07); + temp |= ((saturation & 0x07) << 4); + + setvideoreg(Index_VI_Saturation, temp); +} + +static void set_hue(uint8_t hue) +{ + setvideoreg(Index_VI_Hue, (hue & 0x08) ? (hue ^ 0x07) : hue); +} + +#if 0 +/* JCP: not used (I don't think it's correct anyway) */ +static void set_alpha(uint8_t alpha) +{ + uint8_t data; + + data = getvideoreg(Index_VI_Key_Overlay_OP); + data &= 0x0F; + setvideoreg(Index_VI_Key_Overlay_OP, data | (alpha << 4)); +} +#endif diff --git a/contrib/vidix/drivers/unichrome_regs.h b/contrib/vidix/drivers/unichrome_regs.h new file mode 100644 index 000000000..15795f126 --- /dev/null +++ b/contrib/vidix/drivers/unichrome_regs.h @@ -0,0 +1,635 @@ +/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/via/via.h,v 1.5 2004/01/05 00:34:17 dawes Exp $ */ +/* + * Copyright 1998-2003 VIA Technologies, Inc. All Rights Reserved. + * Copyright 2001-2003 S3 Graphics, Inc. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sub license, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial portions + * of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL + * VIA, S3 GRAPHICS, AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _VIA_H_ +#define _VIA_H_ 1 + +/* Video status flag */ + +#define VIDEO_SHOW 0x80000000 /*Video on*/ +#define VIDEO_HIDE 0x00000000 /*Video off*/ +#define VIDEO_MPEG_INUSE 0x08000000 /*Video is used with MPEG */ +#define VIDEO_HQV_INUSE 0x04000000 /*Video is used with HQV*/ +#define VIDEO_CAPTURE0_INUSE 0x02000000 /*Video is used with CAPTURE 0*/ +#define VIDEO_CAPTURE1_INUSE 0x00000000 /*Video is used with CAPTURE 1*/ +#define VIDEO_1_INUSE 0x01000000 /*Video 1 is used with software flip*/ +#define VIDEO_3_INUSE 0x00000000 /*Video 3 is used with software flip*/ +#define MPEG_USE_V1 0x00010000 /*[16] : 1:MPEG use V1, 0:MPEG use V3*/ +#define MPEG_USE_V3 0x00000000 /*[16] : 1:MPEG use V1, 0:MPEG use V3*/ +#define MPEG_USE_HQV 0x00020000 /*[17] : 1:MPEG use HQV,0:MPEG not use HQV*/ +#define MPEG_USE_HW_FLIP 0x00040000 /*[18] : 1:MPEG use H/W flip,0:MPEG use S/W flip*/ +#define MPEG_USE_SW_FLIP 0x00000000 /*[18] : 1:MPEG use H/W flip,0:MPEG use S/W flip*/ +#define CAP0_USE_V1 0x00001000 /*[12] : 1:Capture 0 use V1, 0:Capture 0 use V3*/ +#define CAP0_USE_V3 0x00000000 /*[12] : 1:Capture 0 use V1, 0:Capture 0 use V3*/ +#define CAP0_USE_HQV 0x00002000 /*[13] : 1:Capture 0 use HQV,0:Capture 0 not use HQV*/ +#define CAP0_USE_HW_FLIP 0x00004000 /*[14] : 1:Capture 0 use H/W flip,0:Capture 0 use S/W flip*/ +#define CAP0_USE_CCIR656 0x00008000 /*[15] : 1:Capture 0 use CCIR656,0:Capture 0 CCIR601*/ +#define CAP1_USE_V1 0x00000100 /*[ 8] : 1:Capture 1 use V1, 0:Capture 1 use V3*/ +#define CAP1_USE_V3 0x00000000 /*[ 8] : 1:Capture 1 use V1, 0:Capture 1 use V3*/ +#define CAP1_USE_HQV 0x00000200 /*[ 9] : 1:Capture 1 use HQV,0:Capture 1 not use HQV*/ +#define CAP1_USE_HW_FLIP 0x00000400 /*[10] : 1:Capture 1 use H/W flip,0:Capture 1 use S/W flip */ +#define SW_USE_V1 0x00000010 /*[ 4] : 1:Capture 1 use V1, 0:Capture 1 use V3 */ +#define SW_USE_V3 0x00000000 /*[ 4] : 1:Capture 1 use V1, 0:Capture 1 use V3 */ +#define SW_USE_HQV 0x00000020 /*[ 5] : 1:Capture 1 use HQV,0:Capture 1 not use HQV */ + +/* +#define VIDEO1_INUSE 0x00000010 //[ 4] : 1:Video 1 is used with S/W flip +#define VIDEO1_USE_HQV 0x00000020 //[ 5] : 1:Video 1 use HQV with S/W flip +#define VIDEO3_INUSE 0x00000001 //[ 0] : 1:Video 3 is used with S/W flip +#define VIDEO3_USE_HQV 0x00000002 //[ 1] : 1:Video 3 use HQV with S/W flip +*/ + +/* H/W registers for Video Engine */ + +/* + * bus master + */ +#define PCI_MASTER_ENABLE 0x01 +#define PCI_MASTER_SCATTER 0x00 +#define PCI_MASTER_SINGLE 0x02 +#define PCI_MASTER_GUI 0x00 +#define PCI_MASTER_VIDEO 0x04 +#define PCI_MASTER_INPUT 0x00 +#define PCI_MASTER_OUTPUT 0x08 + +/* + * video registers + */ +#define V_FLAGS 0x00 +#define V_CAP_STATUS 0x04 +#define V_FLIP_STATUS 0x04 +#define V_ALPHA_WIN_START 0x08 +#define V_ALPHA_WIN_END 0x0C +#define V_ALPHA_CONTROL 0x10 +#define V_CRT_STARTADDR 0x14 +#define V_CRT_STARTADDR_2 0x18 +#define V_ALPHA_STRIDE 0x1C +#define V_COLOR_KEY 0x20 +#define V_ALPHA_STARTADDR 0x24 +#define V_CHROMAKEY_LOW 0x28 +#define V_CHROMAKEY_HIGH 0x2C +#define V1_CONTROL 0x30 +#define V12_QWORD_PER_LINE 0x34 +#define V1_STARTADDR_1 0x38 +#define V1_STARTADDR_Y1 V1_STARTADDR_1 +#define V1_STRIDE 0x3C +#define V1_WIN_START_Y 0x40 +#define V1_WIN_START_X 0x42 +#define V1_WIN_END_Y 0x44 +#define V1_WIN_END_X 0x46 +#define V1_STARTADDR_2 0x48 +#define V1_STARTADDR_Y2 V1_STARTADDR_2 +#define V1_ZOOM_CONTROL 0x4C +#define V1_MINI_CONTROL 0x50 +#define V1_STARTADDR_0 0x54 +#define V1_STARTADDR_Y0 V1_STARTADDR_0 +#define V_FIFO_CONTROL 0x58 +#define V1_STARTADDR_3 0x5C +#define V1_STARTADDR_Y3 V1_STARTADDR_3 +#define HI_CONTROL 0x60 +#define SND_COLOR_KEY 0x64 +#define ALPHA_V3_PREFIFO_CONTROL 0x68 +#define V1_SOURCE_HEIGHT 0x6C +#define HI_TRANSPARENT_COLOR 0x70 +#define V_DISPLAY_TEMP 0x74 /* No use */ +#define ALPHA_V3_FIFO_CONTROL 0x78 +#define V3_SOURCE_WIDTH 0x7C +#define V3_COLOR_KEY 0x80 +#define V1_ColorSpaceReg_1 0x84 +#define V1_ColorSpaceReg_2 0x88 +#define V1_STARTADDR_CB0 0x8C +#define V1_OPAQUE_CONTROL 0x90 /* To be deleted */ +#define V3_OPAQUE_CONTROL 0x94 /* To be deleted */ +#define V_COMPOSE_MODE 0x98 +#define V3_STARTADDR_2 0x9C +#define V3_CONTROL 0xA0 +#define V3_STARTADDR_0 0xA4 +#define V3_STARTADDR_1 0xA8 +#define V3_STRIDE 0xAC +#define V3_WIN_START_Y 0xB0 +#define V3_WIN_START_X 0xB2 +#define V3_WIN_END_Y 0xB4 +#define V3_WIN_END_X 0xB6 +#define V3_ALPHA_QWORD_PER_LINE 0xB8 +#define V3_ZOOM_CONTROL 0xBC +#define V3_MINI_CONTROL 0xC0 +#define V3_ColorSpaceReg_1 0xC4 +#define V3_ColorSpaceReg_2 0xC8 +#define V3_DISPLAY_TEMP 0xCC /* No use */ +#define V1_STARTADDR_CB1 0xE4 +#define V1_STARTADDR_CB2 0xE8 +#define V1_STARTADDR_CB3 0xEC +#define V1_STARTADDR_CR0 0xF0 +#define V1_STARTADDR_CR1 0xF4 +#define V1_STARTADDR_CR2 0xF8 +#define V1_STARTADDR_CR3 0xFC + +/* Video Capture Engine Registers + * Capture Port 1 + */ +#define CAP0_MASKS 0x100 +#define CAP1_MASKS 0x104 +#define CAP0_CONTROL 0x110 +#define CAP0_H_RANGE 0x114 +#define CAP0_V_RANGE 0x118 +#define CAP0_SCAL_CONTROL 0x11C +#define CAP0_VBI_H_RANGE 0x120 +#define CAP0_VBI_V_RANGE 0x124 +#define CAP0_VBI_STARTADDR 0x128 +#define CAP0_VBI_STRIDE 0x12C +#define CAP0_ANCIL_COUNT 0x130 +#define CAP0_MAXCOUNT 0x134 +#define CAP0_VBIMAX_COUNT 0x138 +#define CAP0_DATA_COUNT 0x13C +#define CAP0_FB_STARTADDR0 0x140 +#define CAP0_FB_STARTADDR1 0x144 +#define CAP0_FB_STARTADDR2 0x148 +#define CAP0_STRIDE 0x150 +/* Capture Port 2 */ +#define CAP1_CONTROL 0x154 +#define CAP1_SCAL_CONTROL 0x160 +#define CAP1_VBI_H_RANGE 0x164 /*To be deleted*/ +#define CAP1_VBI_V_RANGE 0x168 /*To be deleted*/ +#define CAP1_VBI_STARTADDR 0x16C /*To be deleted*/ +#define CAP1_VBI_STRIDE 0x170 /*To be deleted*/ +#define CAP1_ANCIL_COUNT 0x174 /*To be deleted*/ +#define CAP1_MAXCOUNT 0x178 +#define CAP1_VBIMAX_COUNT 0x17C /*To be deleted*/ +#define CAP1_DATA_COUNT 0x180 +#define CAP1_FB_STARTADDR0 0x184 +#define CAP1_FB_STARTADDR1 0x188 +#define CAP1_STRIDE 0x18C + +/* SUBPICTURE Registers */ +#define SUBP_CONTROL_STRIDE 0x1C0 +#define SUBP_STARTADDR 0x1C4 +#define RAM_TABLE_CONTROL 0x1C8 +#define RAM_TABLE_READ 0x1CC + +/* HQV Registers */ +#define HQV_CONTROL 0x1D0 +#define HQV_SRC_STARTADDR_Y 0x1D4 +#define HQV_SRC_STARTADDR_U 0x1D8 +#define HQV_SRC_STARTADDR_V 0x1DC +#define HQV_SRC_FETCH_LINE 0x1E0 +#define HQV_FILTER_CONTROL 0x1E4 +#define HQV_MINIFY_CONTROL 0x1E8 +#define HQV_DST_STARTADDR0 0x1EC +#define HQV_DST_STARTADDR1 0x1F0 +#define HQV_DST_STARTADDR2 0x1FC +#define HQV_DST_STRIDE 0x1F4 +#define HQV_SRC_STRIDE 0x1F8 + + +/* + * Video command definition + */ +/* #define V_ALPHA_CONTROL 0x210 */ +#define ALPHA_WIN_EXPIRENUMBER_4 0x00040000 +#define ALPHA_WIN_CONSTANT_FACTOR_4 0x00004000 +#define ALPHA_WIN_CONSTANT_FACTOR_12 0x0000c000 +#define ALPHA_WIN_BLENDING_CONSTANT 0x00000000 +#define ALPHA_WIN_BLENDING_ALPHA 0x00000001 +#define ALPHA_WIN_BLENDING_GRAPHIC 0x00000002 +#define ALPHA_WIN_PREFIFO_THRESHOLD_12 0x000c0000 +#define ALPHA_WIN_FIFO_THRESHOLD_8 0x000c0000 +#define ALPHA_WIN_FIFO_DEPTH_16 0x00100000 + +/* V_CHROMAKEY_LOW 0x228 */ +#define V_CHROMAKEY_V3 0x80000000 + +/* V1_CONTROL 0x230 */ +#define V1_ENABLE 0x00000001 +#define V1_FULL_SCREEN 0x00000002 +#define V1_YUV422 0x00000000 +#define V1_RGB32 0x00000004 +#define V1_RGB15 0x00000008 +#define V1_RGB16 0x0000000C +#define V1_YCbCr420 0x00000010 +#define V1_COLORSPACE_SIGN 0x00000080 +#define V1_SRC_IS_FIELD_PIC 0x00000200 +#define V1_SRC_IS_FRAME_PIC 0x00000000 +#define V1_BOB_ENABLE 0x00400000 +#define V1_FIELD_BASE 0x00000000 +#define V1_FRAME_BASE 0x01000000 +#define V1_SWAP_SW 0x00000000 +#define V1_SWAP_HW_HQV 0x02000000 +#define V1_SWAP_HW_CAPTURE 0x04000000 +#define V1_SWAP_HW_MC 0x06000000 +/* #define V1_DOUBLE_BUFFERS 0x00000000 */ +/* #define V1_QUADRUPLE_BUFFERS 0x18000000 */ +#define V1_EXPIRE_NUM 0x00050000 +#define V1_EXPIRE_NUM_A 0x000a0000 +#define V1_EXPIRE_NUM_F 0x000f0000 /* jason */ +#define V1_FIFO_EXTENDED 0x00200000 +#define V1_ON_CRT 0x00000000 +#define V1_ON_SND_DISPLAY 0x80000000 +#define V1_FIFO_32V1_32V2 0x00000000 +#define V1_FIFO_48V1_32V2 0x00200000 + +/* V12_QWORD_PER_LINE 0x234 */ +#define V1_FETCH_COUNT 0x3ff00000 +#define V1_FETCHCOUNT_ALIGNMENT 0x0000000f +#define V1_FETCHCOUNT_UNIT 0x00000004 /* Doubld QWORD */ + +/* V1_STRIDE */ +#define V1_STRIDE_YMASK 0x00001fff +#define V1_STRIDE_UVMASK 0x1ff00000 + +/* V1_ZOOM_CONTROL 0x24C */ +#define V1_X_ZOOM_ENABLE 0x80000000 +#define V1_Y_ZOOM_ENABLE 0x00008000 + +/* V1_MINI_CONTROL 0x250 */ +#define V1_X_INTERPOLY 0x00000002 /* X interpolation */ +#define V1_Y_INTERPOLY 0x00000001 /* Y interpolation */ +#define V1_YCBCR_INTERPOLY 0x00000004 /* Y, Cb, Cr all interpolation */ +#define V1_X_DIV_2 0x01000000 +#define V1_X_DIV_4 0x03000000 +#define V1_X_DIV_8 0x05000000 +#define V1_X_DIV_16 0x07000000 +#define V1_Y_DIV_2 0x00010000 +#define V1_Y_DIV_4 0x00030000 +#define V1_Y_DIV_8 0x00050000 +#define V1_Y_DIV_16 0x00070000 + +/* V1_STARTADDR0 0x254 */ +#define SW_FLIP_ODD 0x08000000 + +/* V_FIFO_CONTROL 0x258 + * IA2 has 32 level FIFO for packet mode video format + * 32 level FIFO for planar mode video YV12. with extension reg 230 bit 21 enable + * 16 level FIFO for planar mode video YV12. with extension reg 230 bit 21 disable + * BCos of 128 bits. 1 level in IA2 = 2 level in VT3122 + */ +#define V1_FIFO_DEPTH12 0x0000000B +#define V1_FIFO_DEPTH16 0x0000000F +#define V1_FIFO_DEPTH32 0x0000001F +#define V1_FIFO_DEPTH48 0x0000002F +#define V1_FIFO_DEPTH64 0x0000003F +#define V1_FIFO_THRESHOLD6 0x00000600 +#define V1_FIFO_THRESHOLD8 0x00000800 +#define V1_FIFO_THRESHOLD12 0x00000C00 +#define V1_FIFO_THRESHOLD16 0x00001000 +#define V1_FIFO_THRESHOLD24 0x00001800 +#define V1_FIFO_THRESHOLD32 0x00002000 +#define V1_FIFO_THRESHOLD40 0x00002800 +#define V1_FIFO_THRESHOLD48 0x00003000 +#define V1_FIFO_THRESHOLD56 0x00003800 +#define V1_FIFO_THRESHOLD61 0x00003D00 +#define V1_FIFO_PRETHRESHOLD10 0x0A000000 +#define V1_FIFO_PRETHRESHOLD12 0x0C000000 +#define V1_FIFO_PRETHRESHOLD29 0x1d000000 +#define V1_FIFO_PRETHRESHOLD40 0x28000000 +#define V1_FIFO_PRETHRESHOLD44 0x2c000000 +#define V1_FIFO_PRETHRESHOLD56 0x38000000 +#define V1_FIFO_PRETHRESHOLD61 0x3D000000 + +/* ALPHA_V3_FIFO_CONTROL 0x278 + * IA2 has 32 level FIFO for packet mode video format + * 32 level FIFO for planar mode video YV12. with extension reg 230 bit 21 enable + * 16 level FIFO for planar mode video YV12. with extension reg 230 bit 21 disable + * 8 level FIFO for ALPHA + * BCos of 128 bits. 1 level in IA2 = 2 level in VT3122 + */ +#define V3_FIFO_DEPTH16 0x0000000F +#define V3_FIFO_DEPTH24 0x00000017 +#define V3_FIFO_DEPTH32 0x0000001F +#define V3_FIFO_DEPTH48 0x0000002F +#define V3_FIFO_DEPTH64 0x0000003F +#define V3_FIFO_THRESHOLD8 0x00000800 +#define V3_FIFO_THRESHOLD12 0x00000C00 +#define V3_FIFO_THRESHOLD16 0x00001000 +#define V3_FIFO_THRESHOLD24 0x00001800 +#define V3_FIFO_THRESHOLD32 0x00002000 +#define V3_FIFO_THRESHOLD40 0x00002800 +#define V3_FIFO_THRESHOLD48 0x00003000 +#define V3_FIFO_THRESHOLD56 0x00003800 +#define V3_FIFO_THRESHOLD61 0x00003D00 +#define V3_FIFO_PRETHRESHOLD10 0x0000000A +#define V3_FIFO_PRETHRESHOLD12 0x0000000C +#define V3_FIFO_PRETHRESHOLD29 0x0000001d +#define V3_FIFO_PRETHRESHOLD40 0x00000028 +#define V3_FIFO_PRETHRESHOLD44 0x0000002c +#define V3_FIFO_PRETHRESHOLD56 0x00000038 +#define V3_FIFO_PRETHRESHOLD61 0x0000003D +#define V3_FIFO_MASK 0x0000007F +#define ALPHA_FIFO_DEPTH8 0x00070000 +#define ALPHA_FIFO_THRESHOLD4 0x04000000 +#define ALPHA_FIFO_MASK 0xffff0000 +#define ALPHA_FIFO_PRETHRESHOLD4 0x00040000 + +/* IA2 */ +#define ColorSpaceValue_1 0x140020f2 +#define ColorSpaceValue_2 0x0a0a2c00 + +#define ColorSpaceValue_1_3123C0 0x13000DED +#define ColorSpaceValue_2_3123C0 0x13171000 + +/* For TV setting */ +#define ColorSpaceValue_1TV 0x140020f2 +#define ColorSpaceValue_2TV 0x0a0a2c00 + +/* V_COMPOSE_MODE 0x298 */ +#define SELECT_VIDEO_IF_COLOR_KEY 0x00000001 /* select video if (color key),otherwise select graphics */ +#define SELECT_VIDEO3_IF_COLOR_KEY 0x00000020 /* For 3123C0, select video3 if (color key),otherwise select graphics */ +#define SELECT_VIDEO_IF_CHROMA_KEY 0x00000002 /* 0x0000000a //select video if (chroma key ),otherwise select graphics */ +#define ALWAYS_SELECT_VIDEO 0x00000000 /* always select video,Chroma key and Color key disable */ +#define COMPOSE_V1_V3 0x00000000 /* V1 on top of V3 */ +#define COMPOSE_V3_V1 0x00100000 /* V3 on top of V1 */ +#define COMPOSE_V1_TOP 0x00000000 +#define COMPOSE_V3_TOP 0x00100000 +#define V1_COMMAND_FIRE 0x80000000 /* V1 commands fire */ +#define V3_COMMAND_FIRE 0x40000000 /* V3 commands fire */ +#define V_COMMAND_LOAD 0x20000000 /* Video register always loaded */ +#define V_COMMAND_LOAD_VBI 0x10000000 /* Video register always loaded at vbi without waiting source flip */ +#define V3_COMMAND_LOAD 0x08000000 /* CLE_C0 Video3 register always loaded */ +#define V3_COMMAND_LOAD_VBI 0x00000100 /* CLE_C0 Video3 register always loaded at vbi without waiting source flip */ +#define SECOND_DISPLAY_COLOR_KEY_ENABLE 0x00010000 + +/* V3_ZOOM_CONTROL 0x2bc */ +#define V3_X_ZOOM_ENABLE 0x80000000 +#define V3_Y_ZOOM_ENABLE 0x00008000 + +/* V3_MINI_CONTROL 0x2c0 */ +#define V3_X_INTERPOLY 0x00000002 /* X interpolation */ +#define V3_Y_INTERPOLY 0x00000001 /* Y interpolation */ +#define V3_YCBCR_INTERPOLY 0x00000004 /* Y, Cb, Cr all interpolation */ +#define V3_X_DIV_2 0x01000000 +#define V3_X_DIV_4 0x03000000 +#define V3_X_DIV_8 0x05000000 +#define V3_X_DIV_16 0x07000000 +#define V3_Y_DIV_2 0x00010000 +#define V3_Y_DIV_4 0x00030000 +#define V3_Y_DIV_8 0x00050000 +#define V3_Y_DIV_16 0x00070000 + +/* SUBP_CONTROL_STRIDE 0x3c0 */ +#define SUBP_HQV_ENABLE 0x00010000 +#define SUBP_IA44 0x00020000 +#define SUBP_AI44 0x00000000 +#define SUBP_STRIDE_MASK 0x00001fff +#define SUBP_CONTROL_MASK 0x00070000 + +/* RAM_TABLE_CONTROL 0x3c8 */ +#define RAM_TABLE_RGB_ENABLE 0x00000007 + +/* CAPTURE0_CONTROL 0x310 */ +#define C0_ENABLE 0x00000001 +#define BUFFER_2_MODE 0x00000000 +#define BUFFER_3_MODE 0x00000004 +#define BUFFER_4_MODE 0x00000006 +#define SWAP_YUYV 0x00000000 +#define SWAP_UYVY 0x00000100 +#define SWAP_YVYU 0x00000200 +#define SWAP_VYUY 0x00000300 +#define IN_601_8 0x00000000 +#define IN_656_8 0x00000010 +#define IN_601_16 0x00000020 +#define IN_656_16 0x00000030 +#define DEINTER_ODD 0x00000000 +#define DEINTER_EVEN 0x00001000 +#define DEINTER_ODD_EVEN 0x00002000 +#define DEINTER_FRAME 0x00003000 +#define VIP_1 0x00000000 +#define VIP_2 0x00000400 +#define H_FILTER_2 0x00010000 +#define H_FILTER_4 0x00020000 +#define H_FILTER_8_1331 0x00030000 +#define H_FILTER_8_12221 0x00040000 +#define VIP_ENABLE 0x00000008 +#define EN_FIELD_SIG 0x00000800 +#define VREF_INVERT 0x00100000 +#define FIELD_INPUT_INVERSE 0x00400000 +#define FIELD_INVERSE 0x40000000 + +#define C1_H_MINI_EN 0x00000800 +#define C0_H_MINI_EN 0x00000800 +#define C1_V_MINI_EN 0x04000000 +#define C0_V_MINI_EN 0x04000000 +#define C1_H_MINI_2 0x00000400 + +/* CAPTURE1_CONTROL 0x354 */ +#define C1_ENABLE 0x00000001 + +/* V3_CONTROL 0x2A0 */ +#define V3_ENABLE 0x00000001 +#define V3_FULL_SCREEN 0x00000002 +#define V3_YUV422 0x00000000 +#define V3_RGB32 0x00000004 +#define V3_RGB15 0x00000008 +#define V3_RGB16 0x0000000C +#define V3_COLORSPACE_SIGN 0x00000080 +#define V3_EXPIRE_NUM 0x00040000 +#define V3_EXPIRE_NUM_F 0x000f0000 +#define V3_BOB_ENABLE 0x00400000 +#define V3_FIELD_BASE 0x00000000 +#define V3_FRAME_BASE 0x01000000 +#define V3_SWAP_SW 0x00000000 +#define V3_SWAP_HW_HQV 0x02000000 +#define V3_FLIP_HW_CAPTURE0 0x04000000 +#define V3_FLIP_HW_CAPTURE1 0x06000000 + +/* V3_ALPHA_FETCH_COUNT 0x2B8 */ +#define V3_FETCH_COUNT 0x3ff00000 +#define ALPHA_FETCH_COUNT 0x000003ff + +/* HQV_CONTROL 0x3D0 */ +#define HQV_RGB32 0x00000000 +#define HQV_RGB16 0x20000000 +#define HQV_RGB15 0x30000000 +#define HQV_YUV422 0x80000000 +#define HQV_YUV420 0xC0000000 +#define HQV_ENABLE 0x08000000 +#define HQV_SRC_SW 0x00000000 +#define HQV_SRC_MC 0x01000000 +#define HQV_SRC_CAPTURE0 0x02000000 +#define HQV_SRC_CAPTURE1 0x03000000 +#define HQV_FLIP_EVEN 0x00000000 +#define HQV_FLIP_ODD 0x00000020 +#define HQV_SW_FLIP 0x00000010 /* Write 1 to flip HQV buffer */ +#define HQV_DEINTERLACE 0x00010000 /* First line of odd field will be repeated 3 times */ +#define HQV_FIELD_2_FRAME 0x00020000 /* Src is field. Display each line 2 times */ +#define HQV_FRAME_2_FIELD 0x00040000 /* Src is field. Display field */ +#define HQV_FRAME_UV 0x00000000 /* Src is Non-interleaved */ +#define HQV_FIELD_UV 0x00100000 /* Src is interleaved */ +#define HQV_IDLE 0x00000008 +#define HQV_FLIP_STATUS 0x00000001 +#define HQV_DOUBLE_BUFF 0x00000000 +#define HQV_TRIPLE_BUFF 0x04000000 +#define HQV_SUBPIC_FLIP 0x00008000 +#define HQV_FIFO_STATUS 0x00001000 + +/* HQV_FILTER_CONTROL 0x3E4 */ +#define HQV_H_LOWPASS_2TAP 0x00000001 +#define HQV_H_LOWPASS_4TAP 0x00000002 +#define HQV_H_LOWPASS_8TAP1 0x00000003 /* To be deleted */ +#define HQV_H_LOWPASS_8TAP2 0x00000004 /* To be deleted */ +#define HQV_H_HIGH_PASS 0x00000008 +#define HQV_H_LOW_PASS 0x00000000 +#define HQV_V_LOWPASS_2TAP 0x00010000 +#define HQV_V_LOWPASS_4TAP 0x00020000 +#define HQV_V_LOWPASS_8TAP1 0x00030000 +#define HQV_V_LOWPASS_8TAP2 0x00040000 +#define HQV_V_HIGH_PASS 0x00080000 +#define HQV_V_LOW_PASS 0x00000000 +#define HQV_H_HIPASS_F1_DEFAULT 0x00000040 +#define HQV_H_HIPASS_F2_DEFAULT 0x00000000 +#define HQV_V_HIPASS_F1_DEFAULT 0x00400000 +#define HQV_V_HIPASS_F2_DEFAULT 0x00000000 +#define HQV_H_HIPASS_F1_2TAP 0x00000050 +#define HQV_H_HIPASS_F2_2TAP 0x00000100 +#define HQV_V_HIPASS_F1_2TAP 0x00500000 +#define HQV_V_HIPASS_F2_2TAP 0x01000000 +#define HQV_H_HIPASS_F1_4TAP 0x00000060 +#define HQV_H_HIPASS_F2_4TAP 0x00000200 +#define HQV_V_HIPASS_F1_4TAP 0x00600000 +#define HQV_V_HIPASS_F2_4TAP 0x02000000 +#define HQV_H_HIPASS_F1_8TAP 0x00000080 +#define HQV_H_HIPASS_F2_8TAP 0x00000400 +#define HQV_V_HIPASS_F1_8TAP 0x00800000 +#define HQV_V_HIPASS_F2_8TAP 0x04000000 +/* IA2 NEW */ +#define HQV_V_FILTER2 0x00080000 +#define HQV_H_FILTER2 0x00000008 +#define HQV_H_TAP2_11 0x00000041 +#define HQV_H_TAP4_121 0x00000042 +#define HQV_H_TAP4_1111 0x00000401 +#define HQV_H_TAP8_1331 0x00000221 +#define HQV_H_TAP8_12221 0x00000402 +#define HQV_H_TAP16_1991 0x00000159 +#define HQV_H_TAP16_141041 0x0000026A +#define HQV_H_TAP32 0x0000015A +#define HQV_V_TAP2_11 0x00410000 +#define HQV_V_TAP4_121 0x00420000 +#define HQV_V_TAP4_1111 0x04010000 +#define HQV_V_TAP8_1331 0x02210000 +#define HQV_V_TAP8_12221 0x04020000 +#define HQV_V_TAP16_1991 0x01590000 +#define HQV_V_TAP16_141041 0x026A0000 +#define HQV_V_TAP32 0x015A0000 +#define HQV_V_FILTER_DEFAULT 0x00420000 +#define HQV_H_FILTER_DEFAULT 0x00000040 + + + + +/* HQV_MINI_CONTROL 0x3E8 */ +#define HQV_H_MINIFY_ENABLE 0x00000800 +#define HQV_V_MINIFY_ENABLE 0x08000000 +#define HQV_VDEBLOCK_FILTER 0x80000000 +#define HQV_HDEBLOCK_FILTER 0x00008000 + + +#define CHROMA_KEY_LOW 0x00FFFFFF +#define CHROMA_KEY_HIGH 0x00FFFFFF + +/* V_CAP_STATUS */ +#define V_ST_UPDATE_NOT_YET 0x00000003 +#define V1_ST_UPDATE_NOT_YET 0x00000001 +#define V3_ST_UPDATE_NOT_YET 0x00000008 + +#define VBI_STATUS 0x00000002 + +/* + * Macros for Video MMIO + */ +#ifndef V4L2 +#define VIDInB(port) *((volatile CARD8 *)(pVia->VidMapBase + (port))) +#define VIDInW(port) *((volatile CARD16 *)(pVia->VidMapBase + (port))) +#define VIDInD(port) *((volatile CARD32 *)(pVia->VidMapBase + (port))) +#define VIDOutB(port, data) *((volatile CARD8 *)(pVia->VidMapBase + (port))) = (data) +#define VIDOutW(port, data) *((volatile CARD16 *)(pVia->VidMapBase + (port))) = (data) +#define VIDOutD(port, data) *((volatile CARD32 *)(pVia->VidMapBase + (port))) = (data) +#define MPGOutD(port, data) *((volatile CARD32 *)(lpMPEGMMIO +(port))) = (data) +#define MPGInD(port) *((volatile CARD32 *)(lpMPEGMMIO +(port))) +#endif + +/* + * Macros for GE MMIO + */ +#define GEInW(port) *((volatile CARD16 *)(lpGEMMIO + (port))) +#define GEInD(port) *((volatile CARD32 *)(lpGEMMIO + (port))) +#define GEOutW(port, data) *((volatile CARD16 *)(lpGEMMIO + (port))) = (data) +#define GEOutD(port, data) *((volatile CARD32 *)(lpGEMMIO + (port))) = (data) + +/* + * MPEG 1/2 Slice Engine (at 0xC00 relative to base) + */ + +#define MPG_CONTROL 0x00 +#define MPG_CONTROL_STRUCT 0x03 +#define MPG_CONTROL_STRUCT_TOP 0x01 +#define MPG_CONTROL_STRUCT_BOTTOM 0x02 +#define MPG_CONTROL_STRUCT_FRAME 0x03 + /* Use TOP if interlaced */ +#define MPG_CONTROL_TYPE 0x3C +#define MPG_CONTROL_TYPE_I (0x01 << 2) +#define MPG_CONTROL_TYPE_B (0x02 << 2) +#define MPG_CONTROL_TYPE_P (0x03 << 3) +#define MPG_CONTROL_ALTSCAN 0x40 +#define MPG_BLOCK 0x08 /* Unsure */ +#define MPG_COMMAND 0x0C +#define MPG_DATA1 0x10 +#define MPG_DATA2 0x14 +#define MPG_DATA3 0x18 +#define MPG_DATA4 0x1C + +#define MPG_YPHYSICAL(x) (0x20 + 12*(x)) +#define MPG_CbPHYSICAL(x) (0x24 + 12*(x)) +#define MPG_CrPHYSICAL(x) (0x28 + 12*(x)) + +#define MPG_PITCH 0x50 +#define MPG_STATUS 0x54 + +#define MPG_MATRIX_IDX 0x5C +#define MPG_MATRIX_IDX_INTRA 0x00 +#define MPG_MATRIX_IDX_NON 0x01 +#define MPG_MATRIX_DATA 0x60 + +#define MPG_SLICE_CTRL_1 0x90 +#define MPG_SLICE_MBAMAX 0x2FFF +#define MPG_SLICE_PREDICTIVE_DCT 0x4000 +#define MPG_SLICE_TOP_FIRST 0x8000 +#define MPG_SLICE_MACROBLOCK_WIDTH(x) ((x)<<18) /* in 64's */ +#define MPG_SLICE_CTRL_2 0x94 +#define MPG_SLICE_CONCEAL_MVEC 0x0000001 +#define MPG_SLICE_QSCALE_TYPE 0x0000002 +#define MPG_SLICE_DCPRECISION 0x000000C +#define MPG_SLICE_MACROBQUOT 0x0FFFFF0 +#define MPG_SLICE_INTRAVLC 0x1000000 +#define MPG_SLICE_CTRL_3 0x98 +#define MPG_SLICE_FHMVR 0x0000003 +#define MPG_SLICE_FVMVR 0x000000C +#define MPG_SLICE_BHMVR 0x0000030 +#define MPG_SLICE_BVMVR 0x00000C0 +#define MPG_SLICE_SECOND_FIELD 0x0100000 +#define MPG_SLICE_RESET 0x0400000 +#define MPG_SLICE_LENGTH 0x9C +#define MPG_SLICE_DATA 0xA0 + + + +#endif /* _VIA_H_ */ diff --git a/contrib/vidix/drivers/unichrome_vid.c b/contrib/vidix/drivers/unichrome_vid.c new file mode 100644 index 000000000..b5ff314e6 --- /dev/null +++ b/contrib/vidix/drivers/unichrome_vid.c @@ -0,0 +1,772 @@ +/* + Driver for VIA CLE266 Unichrome - Version 0.1.0 + + Copyright (C) 2004 by Timothy Lee + + Based on Cyberblade/i driver by Alastair M. Robison. + + Thanks to Gilles Frattini for bugfixes + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + Changes: + 2004-03-10 + Initial version + + To Do: +*/ + +#include <errno.h> +#include <stdio.h> +#include <stdlib.h> +#include <string.h> +#include <inttypes.h> +#include <unistd.h> + +#include "vidix.h" +#include "fourcc.h" +#include "libdha.h" +#include "pci_ids.h" +#include "pci_names.h" + +#include "unichrome_regs.h" + +pciinfo_t pci_info; + +uint8_t *uc_mem; +static vidix_grkey_t uc_grkey; +static int frames[VID_PLAY_MAXFRAMES]; +uint8_t *vio; +uint8_t mclk_save[3]; + +#define VIA_OUT(hwregs, reg, val) *(volatile uint32_t *)((hwregs) + (reg)) = (val) +#define VIA_IN(hwregs, reg) *(volatile uint32_t *)((hwregs) + (reg)) +#define VGA_OUT8(hwregs, reg, val) *(volatile uint8_t *)((hwregs) + (reg) + 0x8000) = (val) +#define VGA_IN8(hwregs, reg) *(volatile uint8_t *)((hwregs) + (reg) + 0x8000) +#define VIDEO_OUT(hwregs, reg, val) VIA_OUT((hwregs)+0x200, reg, val) +#define VIDEO_IN(hwregs, reg) VIA_IN((hwregs)+0x200, reg) + +#define outb(val,reg) OUTPORT8(reg,val) +#define inb(reg) INPORT8(reg) + +#define ALIGN_TO(v, n) (((v) + (n-1)) & ~(n-1)) +#define UC_MAP_V1_FIFO_CONTROL(depth, pre_thr, thr) \ + (((depth)-1) | ((thr) << 8) | ((pre_thr) << 24)) + +#define FRAMEBUFFER_START 0x600000 +#define FRAMEBUFFER_SIZE 0x200000 + +#ifdef DEBUG_LOGFILE +FILE *logfile=0; +#define LOGWRITE(x) {if(logfile) fprintf(logfile,x);} +#else +#define LOGWRITE(x) +#endif + + +static vidix_capability_t uc_cap = +{ + "VIA CLE266 Unichrome driver", + "Timothy Lee <timothy@siriushk.com>", + TYPE_OUTPUT, + { 0, 0, 0, 0 }, + 4096, + 4096, + 4, + 4, + -1, + FLAG_UPSCALER|FLAG_DOWNSCALER, + VENDOR_VIA2, + -1, + { 0, 0, 0, 0 } +}; + + +unsigned int vixGetVersion(void) +{ + return(VIDIX_VERSION); +} + + +static unsigned short uc_card_ids[] = +{ + DEVICE_VIA2_VT8623_APOLLO_CLE266 +}; + + +static int find_chip(unsigned chip_id) +{ + unsigned i; + for(i = 0;i < sizeof(uc_card_ids)/sizeof(unsigned short);i++) + { + if(chip_id == uc_card_ids[i]) return i; + } + return -1; +} + + +/** + * Map hw settings for vertical scaling. + * + * @param sh source height + * @param dh destination height + * @param zoom will hold vertical setting of zoom register. + * @param mini will hold vertical setting of mini register. + * + * @returns 1 if successful. + * 0 if the zooming factor is too large or small. + * + * @note Derived from VIA's V4L driver. + * See ddover.c, DDOVER_HQVCalcZoomHeight() + */ + +static int uc_ovl_map_vzoom(int sh, int dh, uint32_t* zoom, uint32_t* mini) +{ + uint32_t sh1, tmp, d; + int zoom_ok = 1; + + if (sh == dh) { // No zoom + // Do nothing + } + else if (sh < dh) { // Zoom in + + tmp = (sh * 0x0400) / dh; + zoom_ok = !(tmp > 0x3ff); + + *zoom |= (tmp & 0x3ff) | V1_Y_ZOOM_ENABLE; + *mini |= V1_Y_INTERPOLY | V1_YCBCR_INTERPOLY; + } + else { // sw > dh - Zoom out + + // Find a suitable divider (1 << d) = {2, 4, 8 or 16} + + sh1 = sh; + for (d = 1; d < 5; d++) { + sh1 >>= 1; + if (sh1 <= dh) break; + } + if (d == 5) { // Too small. + d = 4; + zoom_ok = 0; + } + + *mini |= ((d<<1)-1) << 16; // <= {1,3,5,7} << 16 + + // Add scaling + + if (sh1 < dh) { + tmp = (sh1 * 0x400) / dh; + *zoom |= ((tmp & 0x3ff) | V1_Y_ZOOM_ENABLE); + *mini |= V1_Y_INTERPOLY | V1_YCBCR_INTERPOLY; + } + } + + return zoom_ok; +} + + +/** + * Map hw settings for horizontal scaling. + * + * @param sw source width + * @param dw destination width + * + * @param zoom will hold horizontal setting of zoom register. + * @param mini will hold horizontal setting of mini register. + * @param falign will hold fetch aligment + * @param dcount will hold display count + * + * @returns 1 if successful. + * 0 if the zooming factor is too large or small. + * + * @note Derived from VIA's V4L driver. + * See ddover.c, DDOVER_HQVCalcZoomWidth() and DDOver_GetDisplayCount() + */ +static int uc_ovl_map_hzoom(int sw, int dw, uint32_t* zoom, uint32_t* mini, + int* falign, int* dcount) +{ + uint32_t tmp, sw1, d; + int md; // Minify-divider + int zoom_ok = 1; + + md = 1; + *falign = 0; + + if (sw == dw) { // No zoom + // Do nothing + } + else if (sw < dw) { // Zoom in + + tmp = (sw * 0x0800) / dw; + zoom_ok = !(tmp > 0x7ff); + + *zoom |= ((tmp & 0x7ff) << 16) | V1_X_ZOOM_ENABLE; + *mini |= V1_X_INTERPOLY; + } + else { // sw > dw - Zoom out + + // Find a suitable divider (1 << d) = {2, 4, 8 or 16} + + sw1 = sw; + for (d = 1; d < 5; d++) { + sw1 >>= 1; + if (sw1 <= dw) break; + } + if (d == 5) { // Too small. + d = 4; + zoom_ok = 0; + } + + md = 1 << d; // <= {2,4,8,16} + *falign = ((md<<1)-1) & 0xf; // <= {3,7,15,15} + *mini |= V1_X_INTERPOLY; + *mini |= ((d<<1)-1) << 24; // <= {1,3,5,7} << 24 + + // Add scaling + + if (sw1 < dw) { + //CLE bug + //tmp = sw1*0x0800 / dw; + tmp = (sw1 - 2) * 0x0800 / dw; + *zoom |= ((tmp & 0x7ff) << 16) | V1_X_ZOOM_ENABLE; + } + } + + *dcount = sw - md; + + return zoom_ok; +} + + +/** + * @param format overlay pixel format + * @param sw source width + * + * @returns qword fetch register setting + * + * @note Derived from VIA's V4L driver. See ddover.c, DDOver_GetFetch() + * @note Only call after uc_ovl_map_hzoom() + */ +static uint32_t uc_ovl_map_qwfetch(uint32_t format, int sw) +{ + uint32_t fetch = 0; + + switch (format) { + case IMGFMT_YV12: + case IMGFMT_I420: + fetch = ALIGN_TO(sw, 32) >> 4; + break; + case IMGFMT_UYVY: + case IMGFMT_YVYU: + case IMGFMT_YUY2: + fetch = (ALIGN_TO(sw << 1, 16) >> 4) + 1; + break; + case IMGFMT_BGR15: + case IMGFMT_BGR16: + fetch = (ALIGN_TO(sw << 1, 16) >> 4) + 1; + break; + case IMGFMT_BGR32: + fetch = (ALIGN_TO(sw << 2, 16) >> 4) + 1; + break; + default: + printf("[unichrome] Unexpected pixelformat!"); + break; + } + + if (fetch < 4) + fetch = 4; + + return fetch; +} + + +/** + * Map pixel format. + * + * @note Derived from VIA's V4L driver. See ddover.c, DDOver_GetV1Format() + */ +static uint32_t uc_ovl_map_format(uint32_t format) +{ + switch (format) { + case IMGFMT_UYVY: + case IMGFMT_YVYU: + case IMGFMT_YUY2: + return V1_COLORSPACE_SIGN | V1_YUV422; + case IMGFMT_IYUV: + return V1_COLORSPACE_SIGN | V1_YCbCr420 | V1_SWAP_SW; + case IMGFMT_YV12: + case IMGFMT_I420: + return V1_COLORSPACE_SIGN | V1_YCbCr420; + case IMGFMT_BGR15: + return V1_RGB15; + case IMGFMT_BGR16: + return V1_RGB16; + case IMGFMT_BGR32: + return V1_RGB32; + default : + printf("[unichrome] Unexpected pixelformat!"); + return V1_YUV422; + } +} + + +/** + * Calculate V1 control and fifo-control register values + * @param format pixel format + * @param sw source width + * @param hwrev CLE266 hardware revision + * @param extfifo_on set this 1 if the extended FIFO is enabled + * @param control will hold value for V1_CONTROL + * @param fifo will hold value for V1_FIFO_CONTROL + */ +static void uc_ovl_map_v1_control(uint32_t format, int sw, + int hwrev, int extfifo_on, + uint32_t* control, uint32_t* fifo) +{ + *control = V1_BOB_ENABLE | uc_ovl_map_format(format); + + if (hwrev == 0x10) { + *control |= V1_EXPIRE_NUM_F; + } + else { + if (extfifo_on) { + *control |= V1_EXPIRE_NUM_A | V1_FIFO_EXTENDED; + } + else { + *control |= V1_EXPIRE_NUM; + } + } + + if ((format == IMGFMT_YV12) || (format == IMGFMT_I420)) { + //Minified video will be skewed without this workaround. + if (sw <= 80) { //Fetch count <= 5 + *fifo = UC_MAP_V1_FIFO_CONTROL(16,0,0); + } + else { + if (hwrev == 0x10) + *fifo = UC_MAP_V1_FIFO_CONTROL(64,56,56); + else + *fifo = UC_MAP_V1_FIFO_CONTROL(16,12,8); + } + } + else { + if (hwrev == 0x10) { + *fifo = UC_MAP_V1_FIFO_CONTROL(64,56,56); // Default rev 0x10 + } + else { + if (extfifo_on) + *fifo = UC_MAP_V1_FIFO_CONTROL(48,40,40); + else + *fifo = UC_MAP_V1_FIFO_CONTROL(32,29,16); // Default + } + } +} + + +static void uc_ovl_setup_fifo(int *extfifo_on, int dst_w) +{ + if (dst_w <= 1024) + { + // Disable extended FIFO + outb(0x16, 0x3c4); outb(mclk_save[0], 0x3c5); + outb(0x17, 0x3c4); outb(mclk_save[1], 0x3c5); + outb(0x18, 0x3c4); outb(mclk_save[2], 0x3c5); + *extfifo_on = 0; + } + else + { + // Enable extended FIFO + outb(0x17, 0x3c4); outb(0x2f, 0x3c5); + outb(0x16, 0x3c4); outb((mclk_save[0] & 0xf0) | 0x14, 0x3c5); + outb(0x18, 0x3c4); outb(0x56, 0x3c5); + *extfifo_on = 1; + } +} + + +static void uc_ovl_vcmd_wait(volatile uint8_t* vio) +{ + while ((VIDEO_IN(vio, V_COMPOSE_MODE) + & (V1_COMMAND_FIRE | V3_COMMAND_FIRE))); +} + + +int vixProbe(int verbose, int force) +{ + pciinfo_t lst[MAX_PCI_DEVICES]; + unsigned i,num_pci; + int err; + err = pci_scan(lst,&num_pci); + if(err) + { + printf("[unichrome] Error occurred during pci scan: %s\n",strerror(err)); + return err; + } + else + { + err = ENXIO; + for(i=0; i < num_pci; i++) + { + if(lst[i].vendor == VENDOR_VIA2) + { + int idx; + const char *dname; + idx = find_chip(lst[i].device); + if(idx == -1) + continue; + dname = pci_device_name(VENDOR_VIA2, lst[i].device); + dname = dname ? dname : "Unknown chip"; + printf("[unichrome] Found chip: %s\n", dname); + uc_cap.device_id = lst[i].device; + err = 0; + memcpy(&pci_info, &lst[i], sizeof(pciinfo_t)); + break; + } + } + } + + if(err && verbose) printf("[unichrome] Can't find chip\n"); + return err; +} + + +int vixInit(const char *args) +{ + long tmp; + uc_mem = map_phys_mem(pci_info.base0, 0x800000); + enable_app_io(); + + outb(0x2f, 0x3c4); + tmp = inb(0x3c5) << 0x18; + vio = map_phys_mem(tmp,0x1000); + + outb(0x16, 0x3c4); mclk_save[0] = inb(0x3c5); + outb(0x17, 0x3c4); mclk_save[1] = inb(0x3c5); + outb(0x18, 0x3c4); mclk_save[2] = inb(0x3c5); + + uc_grkey.ckey.blue = 0x00; + uc_grkey.ckey.green = 0x00; + uc_grkey.ckey.red = 0x00; + +#ifdef DEBUG_LOGFILE + logfile=fopen("/tmp/uc_vidix.log","w"); +#endif + return 0; +} + +void vixDestroy(void) +{ +#ifdef DEBUG_LOGFILE + if(logfile) + fclose(logfile); +#endif + outb(0x16, 0x3c4); outb(mclk_save[0], 0x3c5); + outb(0x17, 0x3c4); outb(mclk_save[1], 0x3c5); + outb(0x18, 0x3c4); outb(mclk_save[2], 0x3c5); + + disable_app_io(); + unmap_phys_mem(uc_mem, 0x800000); + unmap_phys_mem(vio, 0x1000); +} + + +int vixGetCapability(vidix_capability_t *to) +{ + memcpy(to, &uc_cap, sizeof(vidix_capability_t)); + return 0; +} + + +static int is_supported_fourcc(uint32_t fourcc) +{ + switch(fourcc) + { + case IMGFMT_YV12: + case IMGFMT_I420: + case IMGFMT_UYVY: + case IMGFMT_YVYU: + case IMGFMT_YUY2: + case IMGFMT_BGR15: + case IMGFMT_BGR16: + case IMGFMT_BGR32: + return 1; + default: + return 0; + } +} + +int vixQueryFourcc(vidix_fourcc_t *to) +{ + if(is_supported_fourcc(to->fourcc)) + { + to->depth = VID_DEPTH_1BPP | VID_DEPTH_2BPP | + VID_DEPTH_4BPP | VID_DEPTH_8BPP | + VID_DEPTH_12BPP| VID_DEPTH_15BPP| + VID_DEPTH_16BPP| VID_DEPTH_24BPP| + VID_DEPTH_32BPP; + to->flags = VID_CAP_EXPAND | VID_CAP_SHRINK | VID_CAP_COLORKEY; + return 0; + } + else + to->depth = to->flags = 0; + return ENOSYS; +} + + +int vixGetGrKeys(vidix_grkey_t *grkey) +{ + memcpy(grkey, &uc_grkey, sizeof(vidix_grkey_t)); + return(0); +} + + +int vixSetGrKeys(const vidix_grkey_t *grkey) +{ + unsigned long dwCompose = VIDEO_IN(vio, V_COMPOSE_MODE) & ~0x0f; + memcpy(&uc_grkey, grkey, sizeof(vidix_grkey_t)); + if (uc_grkey.ckey.op != CKEY_FALSE) + { + // Set colorkey + // (how do I detect BPP in hardware??) + unsigned long ckey; + if (1) // Assume 16-bit graphics + { + ckey = (grkey->ckey.blue & 0x1f) + | ((grkey->ckey.green & 0x3f) << 5) + | ((grkey->ckey.red & 0x1f) << 11); + } + else + { + ckey = (grkey->ckey.blue) + | (grkey->ckey.green << 8) + | (grkey->ckey.red << 16); + } + VIDEO_OUT(vio, V_COLOR_KEY, ckey); + dwCompose |= SELECT_VIDEO_IF_COLOR_KEY; + } + + // Execute the changes + VIDEO_OUT(vio, V_COMPOSE_MODE, dwCompose | V1_COMMAND_FIRE); + return(0); +} + + +vidix_video_eq_t equal = +{ + VEQ_CAP_BRIGHTNESS | VEQ_CAP_SATURATION | VEQ_CAP_HUE, + 300, 100, 0, 0, 0, 0, 0, 0 +}; + +int vixPlaybackGetEq( vidix_video_eq_t * eq) +{ + memcpy(eq,&equal,sizeof(vidix_video_eq_t)); + return 0; +} + +int vixPlaybackSetEq( const vidix_video_eq_t * eq) +{ + return 0; +} + + +static int YOffs,UOffs,VOffs; + +int vixConfigPlayback(vidix_playback_t *info) +{ + int src_w, drw_w; + int src_h, drw_h; + long base0, pitch; + int uv_size, swap_uv; + unsigned int i; + int extfifo_on; + + // Overlay register settings + uint32_t win_start, win_end; + uint32_t zoom, mini; + uint32_t dcount, falign, qwfetch; + uint32_t v_ctrl, fifo_ctrl; + + if(!is_supported_fourcc(info->fourcc)) + return -1; + + src_w = info->src.w; + src_h = info->src.h; + + drw_w = info->dest.w; + drw_h = info->dest.h; + + // Setup FIFO + uc_ovl_setup_fifo(&extfifo_on, src_w); + + // Get image format, FIFO size, etc. + uc_ovl_map_v1_control(info->fourcc, src_w, 3, extfifo_on, + &v_ctrl, &fifo_ctrl); + + // Setup layer window + win_start = (info->dest.x << 16) | info->dest.y; + win_end = ((info->dest.x + drw_w - 1) << 16) | + (info->dest.y + drw_h - 1); + + // Get scaling and data-fetch parameters + zoom = 0; + mini = 0; + uc_ovl_map_vzoom(src_h, drw_h, &zoom, &mini); + uc_ovl_map_hzoom(src_w, drw_w, &zoom, &mini, &falign, &dcount); + qwfetch = uc_ovl_map_qwfetch(info->fourcc, src_w); + + // Calculate buffer sizes + swap_uv = 0; + switch(info->fourcc) + { + default: + case IMGFMT_YV12: + swap_uv = 1; + case IMGFMT_I420: + case IMGFMT_UYVY: + case IMGFMT_YVYU: + pitch = ALIGN_TO (src_w, 32); + uv_size = (pitch >> 1) * (src_h >> 1); + break; + + case IMGFMT_YUY2: + case IMGFMT_BGR15: + case IMGFMT_BGR16: + pitch = ALIGN_TO (src_w << 1, 32); + uv_size = 0; + break; + + case IMGFMT_BGR32: + pitch = ALIGN_TO (src_w << 2, 32); + uv_size = 0; + break; + } + if ((src_w > 4096) || (src_h > 4096) || + (src_w < 32) || (src_h < 1) || (pitch > 0x1fff)) + { + printf("[unichrome] Layer size out of bounds\n"); + } + + // Calculate offsets + info->offset.y = 0; + info->offset.v = info->offset.y + pitch * src_h; + info->offset.u = info->offset.v + uv_size; + info->frame_size = info->offset.u + uv_size; + YOffs = info->offset.y; + UOffs = (swap_uv ? info->offset.v : info->offset.u); + VOffs = (swap_uv ? info->offset.u : info->offset.v); + + /* Assume we have 2 MB to play with */ + info->num_frames = FRAMEBUFFER_SIZE / info->frame_size; + if(info->num_frames > VID_PLAY_MAXFRAMES) + info->num_frames = VID_PLAY_MAXFRAMES; + + /* Start at 6 MB. Let's hope it's not in use. */ + base0 = FRAMEBUFFER_START; + info->dga_addr = uc_mem + base0; + + info->dest.pitch.y = 32; + info->dest.pitch.u = 32; + info->dest.pitch.v = 32; + + for(i = 0; i < info->num_frames; i++) + { + info->offsets[i] = info->frame_size * i; + frames[i] = base0+info->offsets[i]; + } + + // Write to the hardware + uc_ovl_vcmd_wait(vio); + + // Configure diy_pitchlay parameters now + if (v_ctrl & V1_COLORSPACE_SIGN) + { + VIDEO_OUT (vio, V1_ColorSpaceReg_2, ColorSpaceValue_2); + VIDEO_OUT (vio, V1_ColorSpaceReg_1, ColorSpaceValue_1); + } + + VIDEO_OUT(vio, V1_CONTROL, v_ctrl); + VIDEO_OUT(vio, V_FIFO_CONTROL, fifo_ctrl); + + VIDEO_OUT(vio, V1_WIN_START_Y, win_start); + VIDEO_OUT(vio, V1_WIN_END_Y, win_end); + + VIDEO_OUT(vio, V1_SOURCE_HEIGHT, (src_h << 16) | dcount); + + VIDEO_OUT(vio, V12_QWORD_PER_LINE, qwfetch << 20); + VIDEO_OUT(vio, V1_STRIDE, pitch | ((pitch >> 1) << 16)); + + VIDEO_OUT(vio, V1_MINI_CONTROL, mini); + VIDEO_OUT(vio, V1_ZOOM_CONTROL, zoom); + + // Configure buffer address and execute the changes now! + vixPlaybackFrameSelect(0); + + return 0; +} + + +int vixPlaybackOn(void) +{ + LOGWRITE("Enable overlay\n"); + + // Turn on overlay + VIDEO_OUT(vio, V1_CONTROL, VIDEO_IN(vio, V1_CONTROL) | V1_ENABLE); + + // Execute the changes + VIDEO_OUT(vio, V_COMPOSE_MODE, + VIDEO_IN(vio, V_COMPOSE_MODE) | V1_COMMAND_FIRE); + + return 0; +} + + +int vixPlaybackOff(void) +{ + LOGWRITE("Disable overlay\n"); + + uc_ovl_vcmd_wait(vio); + + // Restore FIFO + VIDEO_OUT(vio, V_FIFO_CONTROL, UC_MAP_V1_FIFO_CONTROL(16,12,8)); + + // Turn off overlay + VIDEO_OUT(vio, V1_CONTROL, VIDEO_IN(vio, V1_CONTROL) & ~V1_ENABLE); + + // Execute the changes + VIDEO_OUT(vio, V_COMPOSE_MODE, + VIDEO_IN(vio, V_COMPOSE_MODE) | V1_COMMAND_FIRE); + + return 0; +} + + +int vixPlaybackFrameSelect(unsigned int frame) +{ + LOGWRITE("Frame select\n"); + + uc_ovl_vcmd_wait(vio); + + // Configure buffer address + VIDEO_OUT(vio, V1_STARTADDR_Y0, frames[frame]+YOffs); + VIDEO_OUT(vio, V1_STARTADDR_CB0, frames[frame]+UOffs); + VIDEO_OUT(vio, V1_STARTADDR_CR0, frames[frame]+VOffs); + + // Execute the changes + VIDEO_OUT(vio, V_COMPOSE_MODE, + VIDEO_IN(vio, V_COMPOSE_MODE) | V1_COMMAND_FIRE); + + return 0; +} + diff --git a/contrib/vidix/fourcc.h b/contrib/vidix/fourcc.h new file mode 100644 index 000000000..891f0b6ff --- /dev/null +++ b/contrib/vidix/fourcc.h @@ -0,0 +1,70 @@ +/* + * fourcc.h + * This file is part of VIDIX + * Copyright 2002 Nick Kurshev + * Licence: GPL + * This interface is based on v4l2, fbvid.h, mga_vid.h projects + * and personally my ideas. +*/ +#ifndef FOURCC_H +#define FOURCC_H + +/* Four-character-code (FOURCC) */ +#define vid_fourcc(a,b,c,d)\ + (((unsigned)(a)<<0)|((unsigned)(b)<<8)|((unsigned)(c)<<16)|((unsigned)(d)<<24)) + +/* RGB fourcc */ +#define IMGFMT_RGB332 vid_fourcc('R','G','B','1') /* 8 RGB-3-3-2 */ +#define IMGFMT_RGB555 vid_fourcc('R','G','B','O') /* 16 RGB-5-5-5 */ +#define IMGFMT_RGB565 vid_fourcc('R','G','B','P') /* 16 RGB-5-6-5 */ +#define IMGFMT_RGB555X vid_fourcc('R','G','B','Q') /* 16 RGB-5-5-5 BE */ +#define IMGFMT_RGB565X vid_fourcc('R','G','B','R') /* 16 RGB-5-6-5 BE */ +#define IMGFMT_BGR15 vid_fourcc('B','G','R',15) /* 15 BGR-5-5-5 */ +#define IMGFMT_RGB15 vid_fourcc('R','G','B',15) /* 15 RGB-5-5-5 */ +#define IMGFMT_BGR16 vid_fourcc('B','G','R',16) /* 32 BGR-5-6-5 */ +#define IMGFMT_RGB16 vid_fourcc('R','G','B',16) /* 32 RGB-5-6-5 */ +#define IMGFMT_BGR24 vid_fourcc('B','G','R',24) /* 24 BGR-8-8-8 */ +#define IMGFMT_RGB24 vid_fourcc('R','G','B',24) /* 24 RGB-8-8-8 */ +#define IMGFMT_BGR32 vid_fourcc('B','G','R',32) /* 32 BGR-8-8-8-8 */ +#define IMGFMT_RGB32 vid_fourcc('R','G','B',32) /* 32 RGB-8-8-8-8 */ + +/* Planar YUV Formats */ +#define IMGFMT_YVU9 vid_fourcc('Y','V','U','9') /* 9 YVU 4:1:0 */ +#define IMGFMT_IF09 vid_fourcc('I','F','0','9') /* 9.5 YUV 4:1:0 */ +#define IMGFMT_YV12 vid_fourcc('Y','V','1','2') /* 12 YVU 4:2:0 */ +#define IMGFMT_I420 vid_fourcc('I','4','2','0') /* 12 YUV 4:2:0 */ +#define IMGFMT_IYUV vid_fourcc('I','Y','U','V') /* 12 YUV 4:2:0 */ +#define IMGFMT_CLPL vid_fourcc('C','L','P','L') /* 12 */ +#define IMGFMT_Y800 vid_fourcc('Y','8','0','0') /* 8 Y Grayscale */ +#define IMGFMT_NV12 vid_fourcc('N','V','1','2') /* 8 Y Grayscale */ +#define IMGFMT_Y8 vid_fourcc('Y','8',' ',' ') /* 8 Y Grayscale */ + +/* Packed YUV Formats */ +#define IMGFMT_IUYV vid_fourcc('I','U','Y','V') /* 16 line order {0,2,4,...1,3,5} */ +#define IMGFMT_IY41 vid_fourcc('I','Y','4','1') /* 12 line order {0,2,4,...1,3,5} */ +#define IMGFMT_IYU1 vid_fourcc('I','Y','U','1') /* 12 IEEE 1394 Digital Camera */ +#define IMGFMT_IYU2 vid_fourcc('I','Y','U','2') /* 24 IEEE 1394 Digital Camera */ +#define IMGFMT_UYVY vid_fourcc('U','Y','V','Y') /* 16 UYVY 4:2:2 */ +#define IMGFMT_UYNV vid_fourcc('U','Y','N','V') /* 16 UYVY 4:2:2 */ +#define IMGFMT_cyuv vid_fourcc('c','y','u','v') /* 16 */ +#define IMGFMT_Y422 vid_fourcc('Y','4','2','2') /* 16 UYVY 4:2:2 */ +#define IMGFMT_YUY2 vid_fourcc('Y','U','Y','2') /* 16 YUYV 4:2:2 */ +#define IMGFMT_YUNV vid_fourcc('Y','U','N','V') /* 16 YUYV 4:2:2 */ +#define IMGFMT_YVYU vid_fourcc('Y','V','Y','U') /* 16 YVYU 4:2:2 */ +#define IMGFMT_Y41P vid_fourcc('Y','4','1','P') /* 12 YUV 4:1:1 */ +#define IMGFMT_Y211 vid_fourcc('Y','2','1','1') /* 8.5 YUV 2:1:1 */ +#define IMGFMT_Y41T vid_fourcc('Y','4','1','T') /* 12 YUV 4:1:1 */ +#define IMGFMT_Y42T vid_fourcc('Y','4','2','T') /* 16 UYVU 4:2:2 */ +#define IMGFMT_V422 vid_fourcc('V','4','2','2') /* 16 YUY2 4:2:2 */ +#define IMGFMT_V655 vid_fourcc('V','6','5','5') /* 16 YUV 4:2:2 */ +#define IMGFMT_CLJR vid_fourcc('C','L','J','R') /* 7.9 YUV 4:1:1 */ +#define IMGFMT_YUVP vid_fourcc('Y','U','V','P') /* 24 Y0U0Y1V0 */ +#define IMGFMT_UYVP vid_fourcc('U','Y','V','P') /* 24 U0Y0V0Y1 */ +#define IMGFMT_411P vid_fourcc('4','1','1','P') /* 12 alias of Y41B */ +#define IMGFMT_422P vid_fourcc('4','2','2','P') /* 16 alias of Y42B */ +#define IMGFMT_444P vid_fourcc('4','4','4','P') /* 24 alias of Y44B */ + +/* Vendor-specific formats */ +#define IMGFMT_WNVA vid_fourcc('W','N','V','A') /* Winnov hw compress */ + +#endif diff --git a/contrib/vidix/vidix.h b/contrib/vidix/vidix.h new file mode 100644 index 000000000..bcf6b4ae0 --- /dev/null +++ b/contrib/vidix/vidix.h @@ -0,0 +1,312 @@ +/* + * vidix.h + * VIDIX - VIDeo Interface for *niX + * This interface is introduced as universal one to MPEG decoder, + * BES == Back End Scaler and YUV2RGB hw accelerators. + * In the future it may be expanded up to capturing and audio things. + * Main goal of this this interface imlpementation is providing DGA + * everywhere where it's possible (unlike X11 and other). + * Copyright 2002 Nick Kurshev + * Licence: GPL + * This interface is based on v4l2, fbvid.h, mga_vid.h projects + * and personally my ideas. + * NOTE: This interface is introduces as driver interface. + * Don't use it for APP. +*/ +#ifndef VIDIX_H +#define VIDIX_H + +#ifdef __cplusplus +extern "C" { +#endif + +#define VIDIX_VERSION 100 + + /* returns driver version */ +extern unsigned vixGetVersion( void ); + +#define PROBE_NORMAL 0 /* normal probing */ +#define PROBE_FORCE 1 /* ignore device_id but recognize device if it's known */ + /* Probes video hw. + verbose - specifies verbose level. + force - specifies force mode - driver should ignore + device_id (danger but useful for new devices) + Returns 0 if ok else errno */ +extern int vixProbe( int verbose, int force ); + /* Initializes driver. + args - specifies driver specific parameters + Returns 0 if ok else errno */ +extern int vixInit( const char *args ); + /* Destroys driver */ +extern void vixDestroy( void ); + +typedef struct vidix_capability_s +{ + char name[64]; /* Driver name */ + char author[64]; /* Author name */ +#define TYPE_OUTPUT 0x00000000 /* Is a video playback device */ +#define TYPE_CAPTURE 0x00000001 /* Is a capture device */ +#define TYPE_CODEC 0x00000002 /* Device supports hw (de)coding */ +#define TYPE_FX 0x00000004 /* Is a video effects device */ + int type; /* Device type, see below */ + unsigned reserved0[4]; + int maxwidth; + int maxheight; + int minwidth; + int minheight; + int maxframerate; /* -1 if unlimited */ +#define FLAG_NONE 0x00000000 /* No flags defined */ +#define FLAG_DMA 0x00000001 /* Card can use DMA */ +#define FLAG_EQ_DMA 0x00000002 /* Card can use DMA only if src pitch == dest pitch */ +#define FLAG_SYNC_DMA 0x00000004 /* Possible to wait for DMA + * to finish. See + * BM_DMA_SYNC and + * BM_DMA_BLOCK below */ +#define FLAG_UPSCALER 0x00000010 /* Card supports hw upscaling */ +#define FLAG_DOWNSCALER 0x00000020 /* Card supports hw downscaling */ +#define FLAG_SUBPIC 0x00001000 /* Card supports DVD subpictures */ +#define FLAG_EQUALIZER 0x00002000 /* Card supports equalizer */ + unsigned flags; /* Feature flags, see above */ + unsigned short vendor_id; + unsigned short device_id; + unsigned reserved1[4]; +}vidix_capability_t; + + /* Should fill at least type before init. + Returns 0 if ok else errno */ +extern int vixGetCapability(vidix_capability_t *); + +typedef struct vidix_fourcc_s +{ + unsigned fourcc; /* input: requested fourcc */ + unsigned srcw; /* input: hint: width of source */ + unsigned srch; /* input: hint: height of source */ +#define VID_DEPTH_NONE 0x0000 +#define VID_DEPTH_1BPP 0x0001 +#define VID_DEPTH_2BPP 0x0002 +#define VID_DEPTH_4BPP 0x0004 +#define VID_DEPTH_8BPP 0x0008 +#define VID_DEPTH_12BPP 0x0010 +#define VID_DEPTH_15BPP 0x0020 +#define VID_DEPTH_16BPP 0x0040 +#define VID_DEPTH_24BPP 0x0080 +#define VID_DEPTH_32BPP 0x0100 + unsigned depth; /* output: screen depth for given fourcc */ +#define VID_CAP_NONE 0x0000 +#define VID_CAP_EXPAND 0x0001 /* if overlay can be bigger than source */ +#define VID_CAP_SHRINK 0x0002 /* if overlay can be smaller than source */ +#define VID_CAP_BLEND 0x0004 /* if overlay can be blended with framebuffer */ +#define VID_CAP_COLORKEY 0x0008 /* if overlay can be restricted to a colorkey */ +#define VID_CAP_ALPHAKEY 0x0010 /* if overlay can be restricted to an alpha channel */ +#define VID_CAP_COLORKEY_ISRANGE 0x0020 /* if the colorkey can be a range */ +#define VID_CAP_ALPHAKEY_ISRANGE 0x0040 /* if the alphakey can be a range */ +#define VID_CAP_COLORKEY_ISMAIN 0x0080 /* colorkey is checked against framebuffer */ +#define VID_CAP_COLORKEY_ISOVERLAY 0x0100 /* colorkey is checked against overlay */ +#define VID_CAP_ALPHAKEY_ISMAIN 0x0200 /* alphakey is checked against framebuffer */ +#define VID_CAP_ALPHAKEY_ISOVERLAY 0x0400 /* alphakey is checked against overlay */ + unsigned flags; /* output: capability */ +}vidix_fourcc_t; + + /* Returns 0 if ok else errno */ +extern int vixQueryFourcc(vidix_fourcc_t *); + +typedef struct vidix_yuv_s +{ + unsigned y,u,v,a; +}vidix_yuv_t; + +typedef struct vidix_rect_s +{ + unsigned x,y,w,h; /* in pixels */ + vidix_yuv_t pitch; /* line-align in bytes */ +}vidix_rect_t; + +typedef struct vidix_color_key_s +{ +#define CKEY_FALSE 0 +#define CKEY_TRUE 1 +#define CKEY_EQ 2 +#define CKEY_NEQ 3 + unsigned op; /* defines logical operation */ + unsigned char red; + unsigned char green; + unsigned char blue; + unsigned char reserved; +}vidix_ckey_t; + +typedef struct vidix_video_key_s +{ +#define VKEY_FALSE 0 +#define VKEY_TRUE 1 +#define VKEY_EQ 2 +#define VKEY_NEQ 3 + unsigned op; /* defines logical operation */ + unsigned char key[8]; +}vidix_vkey_t; + +typedef struct vidix_playback_s +{ + unsigned fourcc; /* app -> driver: movies's fourcc */ + unsigned capability; /* app -> driver: what capability to use */ + unsigned blend_factor; /* app -> driver: blending factor */ + vidix_rect_t src; /* app -> driver: original movie size */ + vidix_rect_t dest; /* app -> driver: destinition movie size. driver->app dest_pitch */ +#define VID_PLAY_INTERLEAVED_UV 0x00000001 /* driver -> app: interleaved UV planes */ +#define INTERLEAVING_UV 0x00001000 /* UVUVUVUVUV used by Matrox G200 */ +#define INTERLEAVING_VU 0x00001001 /* VUVUVUVUVU */ + int flags; + /* memory model */ + unsigned frame_size; /* driver -> app: destinition frame size */ + unsigned num_frames; /* app -> driver: after call: driver -> app */ +#define VID_PLAY_MAXFRAMES 1024 /* unreal limitation */ + unsigned offsets[VID_PLAY_MAXFRAMES]; /* driver -> app */ + vidix_yuv_t offset; /* driver -> app: relative offsets within frame for yuv planes */ + void* dga_addr; /* driver -> app: linear address */ +}vidix_playback_t; + + /* Returns 0 if ok else errno */ +extern int vixConfigPlayback(vidix_playback_t *); + + /* Returns 0 if ok else errno */ +extern int vixPlaybackOn( void ); + + /* Returns 0 if ok else errno */ +extern int vixPlaybackOff( void ); + + /* Returns 0 if ok else errno */ +extern int vixPlaybackFrameSelect( unsigned frame_idx ); + +typedef struct vidix_grkey_s +{ + vidix_ckey_t ckey; /* app -> driver: color key */ + vidix_vkey_t vkey; /* app -> driver: video key */ +#define KEYS_PUT 0 +#define KEYS_AND 1 +#define KEYS_OR 2 +#define KEYS_XOR 3 + unsigned key_op; /* app -> driver: keys operations */ +}vidix_grkey_t; + + /* Returns 0 if ok else errno */ +extern int vixGetGrKeys( vidix_grkey_t * ); + + /* Returns 0 if ok else errno */ +extern int vixSetGrKeys( const vidix_grkey_t * ); + + +typedef struct vidix_video_eq_s +{ +#define VEQ_CAP_NONE 0x00000000UL +#define VEQ_CAP_BRIGHTNESS 0x00000001UL +#define VEQ_CAP_CONTRAST 0x00000002UL +#define VEQ_CAP_SATURATION 0x00000004UL +#define VEQ_CAP_HUE 0x00000008UL +#define VEQ_CAP_RGB_INTENSITY 0x00000010UL + int cap; /* on get_eq should contain capability of equalizer + on set_eq should contain using fields */ +/* end-user app can have presets like: cold-normal-hot picture and so on */ + int brightness; /* -1000 : +1000 */ + int contrast; /* -1000 : +1000 */ + int saturation; /* -1000 : +1000 */ + int hue; /* -1000 : +1000 */ + int red_intensity; /* -1000 : +1000 */ + int green_intensity;/* -1000 : +1000 */ + int blue_intensity; /* -1000 : +1000 */ +#define VEQ_FLG_ITU_R_BT_601 0x00000000 /* ITU-R BT.601 colour space (default) */ +#define VEQ_FLG_ITU_R_BT_709 0x00000001 /* ITU-R BT.709 colour space */ +#define VEQ_FLG_ITU_MASK 0x0000000f + int flags; /* currently specifies ITU YCrCb color space to use */ +}vidix_video_eq_t; + + /* Returns 0 if ok else errno */ +extern int vixPlaybackGetEq( vidix_video_eq_t * ); + + /* Returns 0 if ok else errno */ +extern int vixPlaybackSetEq( const vidix_video_eq_t * ); + +typedef struct vidix_deinterlace_s +{ +#define CFG_NON_INTERLACED 0x00000000 /* stream is not interlaced */ +#define CFG_INTERLACED 0x00000001 /* stream is interlaced */ +#define CFG_EVEN_ODD_INTERLACING 0x00000002 /* first frame contains even fields but second - odd */ +#define CFG_ODD_EVEN_INTERLACING 0x00000004 /* first frame contains odd fields but second - even */ +#define CFG_UNIQUE_INTERLACING 0x00000008 /* field deinterlace_pattern is valid */ +#define CFG_UNKNOWN_INTERLACING 0x0000000f /* unknown deinterlacing - use adaptive if it's possible */ + unsigned flags; + unsigned deinterlace_pattern; /* app -> driver: deinterlace pattern if flag CFG_UNIQUE_INTERLACING is set */ +}vidix_deinterlace_t; + + /* Returns 0 if ok else errno */ +extern int vixPlaybackGetDeint( vidix_deinterlace_t * ); + + /* Returns 0 if ok else errno */ +extern int vixPlaybackSetDeint( const vidix_deinterlace_t * ); + +typedef struct vidix_slice_s +{ + void* address; /* app -> driver */ + unsigned size; /* app -> driver */ + vidix_rect_t slice; /* app -> driver */ +}vidix_slice_t; + +typedef struct vidix_dma_s +{ + void * src; /* app -> driver. Virtual address of source */ + unsigned dest_offset; /* app -> driver. Destinition offset within of video memory */ + unsigned size; /* app -> driver. Size of transaction */ +#define BM_DMA_ASYNC 0 +#define BM_DMA_SYNC 1 /* await previous dma transfer completion */ +#define BM_DMA_FIXED_BUFFS 2 /* app -> driver: app uses buffers which are fixed in memory */ +#define BM_DMA_BLOCK 4 /* block until the transfer is complete */ + unsigned flags; /* app -> driver */ + unsigned idx; /* app -> driver: idx of src buffer */ + void * internal[VID_PLAY_MAXFRAMES]; /* for internal use by driver */ +}vidix_dma_t; + + /* Returns 0 if ok else errno */ +extern int vixPlaybackCopyFrame( vidix_dma_t * ); + + /* Returns 0 if DMA is available else errno (EBUSY) */ +extern int vixQueryDMAStatus( void ); +/* + This structure is introdused to support OEM effects like: + - sharpness + - exposure + - (auto)gain + - H(V)flip + - black level + - white balance + and many other +*/ +typedef struct vidix_oem_fx_s +{ +#define FX_TYPE_BOOLEAN 0x00000000 +#define FX_TYPE_INTEGER 0x00000001 + int type; /* type of effects */ + int num; /* app -> driver: effect number. From 0 to max number of effects */ + int minvalue; /* min value of effect. 0 - for boolean */ + int maxvalue; /* max value of effect. 1 - for boolean */ + int value; /* current value of effect on 'get'; required on set */ + char * name[80]; /* effect name to display */ +}vidix_oem_fx_t; + + /* Returns 0 if ok else errno */ +extern int vixQueryNumOemEffects( unsigned * number ); + + /* Returns 0 if ok else errno */ +extern int vixGetOemEffect( vidix_oem_fx_t * ); + + /* Returns 0 if ok else errno */ +extern int vixSetOemEffect( const vidix_oem_fx_t * ); + +#ifdef VIDIX_BUILD_STATIC +#define VIDIX_NAME(name) VIDIX_STATIC##name +#else +#define VIDIX_NAME(name) name +#endif + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/contrib/vidix/vidix.txt b/contrib/vidix/vidix.txt new file mode 100644 index 000000000..e642147b4 --- /dev/null +++ b/contrib/vidix/vidix.txt @@ -0,0 +1,247 @@ + VIDIX - VIDeo Interface for *niX + ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +This interface was designed and introduced as interface to userspace drivers +to provide DGA everywhere where it's possible (unline X11). +I hope that these drivers will be portable same as X11 (not only on *nix). + +What is it: +- It's portable successor of mga_vid technology which is located in user-space. +- Unlikely X11 it's provides DGA everywhere where it's possible. +- Unlikely v4l it provides interface for video playback +- Unlikely linux's drivers it uses mathematics library. + +Why it was developed: +As said Vladimir Dergachev +(http://cvs.sourceforge.net/cgi-bin/viewcvs.cgi/gatos/km/km.rfc.txt): +"0) Motivation + v4l, v4l2 and Xv are all suffering from the same problem: attempt to fit + existing multimedia devices into a fixed scheme." +Well - I tried to implement something similar by motivation. + +How it works: +~~~~~~~~~~~~~ + +This interface is almost finished. But I guess it can be expanded by developer's +requests. +So any suggestions, reports, criticism are gladly accepted. + +1) APP calls vixGetVersion to check age of driver ;) +2) APP calls vixProbe. Driver should return 0 if it can handle something in PC. +3) APP calls vixGetCapability. Driver should return filled + vidix_capability_t.type field at least. +4) If above calls were succesful then APP calls vixInit function + (Driver can have not exported this function in this case call will be + skiped). +5) After initializing of driver APP calls vixGetCapability again + (In this case driver must fill every field of struct) +6) APP calls vixQueryFourcc. Driver should answer - can it configure + video memory for given fourcc or not. +7) APP calls vixConfigPlayback. Driver should prepare BES on this call. + APP pass to driver following info: + ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + vidix_playback_t.fourcc - contains fourcc of movie + vidix_playback_t.capability - currently contsinas copy of vidix_capability_t.flags + vidix_playback_t.blend_factor- currently unused + vidix_playback_t.src - x,y,w,h fields contain original movie size + (in pixels) x and y often are nulls. + vidix_playback_t.src.pitch.y These fields contain source pitches + vidix_playback_t.src.pitch.u - for each Y,U,V plane in bytes. + vidix_playback_t.src.pitch.v (For packed fourcc only Y value is used) + They are hints for driver to use same destinition + pitches as in source memory (to speed up + memcpy process). + Note: when source pitches are unknown or + variable these field will be filled into 0. + vidix_playback_t.dest - x,y,w,h fields contains destinition rectange + on the screen in pixels. + vidix_playback_t.num_frames - maximal # of frames which can be used by APP. + (Currently 10). + Driver should fill following fields: + ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + vidix_playback_t.num_frames - real # of frames which will be used by driver. + (Should be less or equal to app's num_frames). + + vidix_playback_t.dest.pitch.y These fields should contain alignment + vidix_playback_t.dest.pitch.u - for each Y,U,V plane in bytes. + vidix_playback_t.dest.pitch.v (For packed fourcc only Y value is used) + + vidix_playback_t.frame_size - Driver should tell to app which size of + source frame (src.w and src.h) should + use APP (according to pitches and offsets) + + vidix_playback_t.offsets - offsets from begin of BES memory for each frame + + vidix_playback_t.offset.y These field should contain offset + vidix_playback_t.offset.u - for each Y,U,V plane within frame. + vidix_playback_t.offset.v (For packed fourcc only Y value is used) + + vidix_playback_t.dga_addr - Address of BES memory. + +Also see this picture: + +VIDEO MEMORY layout: + +----------- It's begin of video memory End of video memory--------------+ + | | + v v + [ RGB memory | YUV memory | UNDEF ] + ^ + | + +---- begin of BES memory + +BES MEMORY layout: + +-------- begin of BES memory + | + v + [ | | | | | + ^ ^ ^ ^ ^ + | | | | + BEGIN of second frame + | | | + BEGIN of V plane + | | + BEGIN of U plane + | +------- BEGIN of Y plane + | + +--------- BEGIN of first frame + +This means that in general case: +offset of frame != offset of BES +offset of Y plane != offset of first frame + +But often: vidix_playback_t.offsets[0] = vidix_playback_t.offset.y = 0; + +Formula: (For Y plane) copy source to: + vidix_playback_t.dga_addr + + vidix_playback_t.offsets[i] + + vidix_playback_t.offset.y + +8) APP calls vixPlaybackOn. Driver should activate BES on this call. +9) PLAYBACK. Driver should sleep here ;) + But during playback can be called: + vixFrameSelect (if this function is exported) + Driver should prepare and activate corresponded frame. + This function is used only for double and trilpe buffering and + never used for single buffering playback. + vixGet(Set)GrKeys (if this function is exported) + This interface should be tuned but intriduced for overlapped playback + and video effects (TYPE_FX) + vixPlaybackGet(Set)Eq (if this function is exported) + For color correction. +10) APP calls vixPlaybackOff. Driver should deactivate BES on this call. +11) If vixDestroy is defined APP calls this function before unloading driver + from memory. + + +What functions are mandatory: +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +vixGetVersion +vixProbe +vixGetCapability +vixQueryFourcc +vixConfigPlayback +vixPlaybackOn +vixPlaybackOff + +All other functions are optionaly. + +BUSMASTERING +************ + +Busmastering is technique to implement data transfer through DMA. +This technique is intended to free CPU for other useful work to +speedup movie playback. The speedup will be different on different +CPUs OSes and videocards. Only thing which SHOULD be implemented +it's the fact that frame should be transfered faster than 1/fps. +(I.e. faster than 33ms for 30 fps or faster than 40ms for 25 fps) +VIDIX implementation of BM (busmastering) is slightly specific. +During driver development you should keep in mind the next rules: +1. BM is implemented as parallel process which should work + simultaneously with frame decoding. +2. To have possibility to use busmastering by non-ROOT users + driver should rather call functions from libdha than from libc. + (Example: driver should call bm_lock_mem instead of mlock) +3. To speedup data transfer player will pass pointer to the DMA buffer + which will have the same structure (planes and strides) as video memory + (In this connexion driver should allocate frames in video memory + same as if BM would not be implemented). + +Interface: +~~~~~~~~~~ + +The interface of BM is implemented through 2 functions: + vixPlaybackCopyFrame + vixQueryDMAStatus + + +vixPlaybackCopyFrame + +should prepare engine to copy frame from +system memory into video framebuffer. After that driver should +send command into engine to start data transfer and return +control immediatedly. + +The structure vidix_dma_s in details: + +typedef struct vidix_dma_s +{ + /* + app -> driver. + Virtual address of source. + Note: source buffer is allocated by using malloc + or memalign(); + */ + void * src; + /* + app -> driver. + Destinition offset within of video memory. + It will point offset within of YUV memory where + destinition data should be stored. + */ + unsigned dest_offset; + /* app -> driver. Size of data to be transfered in bytes. */ + unsigned size; + /* + can accept ORed values of BM_DMA* definitions + BM_DMA_ASYNC - default value which indicates that transactiion + should work asynchronously. + BM_DMA_SYNC - may be ignored due speedup reasons + BM_DMA_FIXED_BUFFS - indicates that player was started by ROOT + and source DMA buffers were already locked in memory + through mlock(). + /* app -> driver: idx of src buffer. + if BM_DMA_FIXED_BUFFS flags is set then this field + indicates which from buffers currently is passed + into driver. This field maybe ignored by driver but + it would be better to use that for minor speedup + of engine preparing. */ + unsigned idx; + /* for internal use by driver. + Driver may use them on its opinion */ + void * internal[VID_PLAY_MAXFRAMES]; +}vidix_dma_t; + + +vixQueryDMAStatus + +should check out DMA status and return 1 if BM is busy +and 0 otherwise. Note: this function shouldn't wait any +changes in DMA state. + +A few words about of non-linux systems +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +Well, there is only one problem which stops us to use BM on +nono-linux systems: it's lacking of possibility to perform +convertion from virtual to physical address in user-space. +This problem is sloved by so-called dhahelper driver for +linux. What about of other OSes then this driver requires +to be ported first. (Of course, except of DOS and DOS32 +where these convertions are unnecessary). + +Useful links: +~~~~~~~~~~~~~ +Guide to DTV http://www.digitaltelevision.com/dtvbook/toc.shtml +Fourcc http://www.webartz.com/fourcc/ +MPEG http://www.mpeg.org/MPEG/index.html +Analog colors http://www.miranda.com/en/app_notes/TN/TN-05/TN-05.htm + +Please send your suggestions, reports, feedback to mplayerxp-general@lists.sourceforge.net + +Best regards! Nick Kurshev. diff --git a/contrib/vidix/vidixlib.c b/contrib/vidix/vidixlib.c new file mode 100644 index 000000000..37af2035b --- /dev/null +++ b/contrib/vidix/vidixlib.c @@ -0,0 +1,482 @@ +/* + * vidixlib.c + * VIDIXLib - Library for VIDeo Interface for *niX + * This interface is introduced as universal one to MPEG decoder, + * BES == Back End Scaler and YUV2RGB hw accelerators. + * In the future it may be expanded up to capturing and audio things. + * Main goal of this this interface imlpementation is providing DGA + * everywhere where it's possible (unlike X11 and other). + * Copyright 2002 Nick Kurshev + * Licence: GPL + * This interface is based on v4l2, fbvid.h, mga_vid.h projects + * and personally my ideas. + * NOTE: This interface is introduces as APP interface. + * Don't use it for driver. + * It provides multistreaming. This mean that APP can handle + * several streams simultaneously. (Example: Video capturing and video + * playback or capturing, video playback, audio encoding and so on). +*/ +#include <stdlib.h> +#include <stdio.h> +#include <errno.h> +#include <string.h> +#include <inttypes.h> + +#include <dlfcn.h> /* GLIBC specific. Exists under cygwin too! */ +#include <dirent.h> + +#include "vidixlib.h" +#include "bswap.h" + +#define t_vdl(p) (((vdl_stream_t *)p)) + +typedef struct vdl_stream_s +{ + void * handle; + int (*get_caps)(vidix_capability_t *); + int (*query_fourcc)(vidix_fourcc_t *); + int (*config_playback)(vidix_playback_t *); + int (*playback_on)( void ); + int (*playback_off)( void ); + /* Functions below can be missed in driver ;) */ + int (*init)(const char *); + void (*destroy)(void); + int (*frame_sel)( unsigned frame_idx ); + int (*get_eq)( vidix_video_eq_t * ); + int (*set_eq)( const vidix_video_eq_t * ); + int (*get_deint)( vidix_deinterlace_t * ); + int (*set_deint)( const vidix_deinterlace_t * ); + int (*copy_frame)( const vidix_dma_t * ); + int (*query_dma)( void ); + int (*get_gkey)( vidix_grkey_t * ); + int (*set_gkey)( const vidix_grkey_t * ); + int (*get_num_fx)( unsigned * ); + int (*get_fx)( vidix_oem_fx_t * ); + int (*set_fx)( const vidix_oem_fx_t * ); +}vdl_stream_t; + +static char drv_name[FILENAME_MAX]; +static int dl_idx = -1; +/* currently available driver for static linking */ +static const char* const drv_snames[] = { +#ifdef VIDIX_BUILD_STATIC + "genfb_", + "mach64_", + "mga_crtc2_", + "mga_", + "nvidia_", + "pm2_", + "pm3_", + "radeo_", + "rage128_", +#endif + NULL +}; + +extern unsigned vdlGetVersion( void ) +{ + return VIDIX_VERSION; +} + +static void* dlsymm(void* handle, const char* fce) +{ + char b[100]; +#if defined(__OpenBSD__) && !defined(__ELF__) + b[0] = '_'; + b[1] = 0; +#else + b[0] = 0; +#endif + if (dl_idx >= 0) strcat(b, drv_snames[dl_idx]); + strcat(b, fce); + //printf("Handle %p %s\n", handle, b); + return dlsym(handle, b); +} + +static int vdl_fill_driver(VDL_HANDLE stream) +{ + t_vdl(stream)->init = dlsymm(t_vdl(stream)->handle,"vixInit"); + t_vdl(stream)->destroy = dlsymm(t_vdl(stream)->handle,"vixDestroy"); + t_vdl(stream)->get_caps = dlsymm(t_vdl(stream)->handle,"vixGetCapability"); + t_vdl(stream)->query_fourcc = dlsymm(t_vdl(stream)->handle,"vixQueryFourcc"); + t_vdl(stream)->config_playback= dlsymm(t_vdl(stream)->handle,"vixConfigPlayback"); + t_vdl(stream)->playback_on = dlsymm(t_vdl(stream)->handle,"vixPlaybackOn"); + t_vdl(stream)->playback_off = dlsymm(t_vdl(stream)->handle,"vixPlaybackOff"); + t_vdl(stream)->frame_sel = dlsymm(t_vdl(stream)->handle,"vixPlaybackFrameSelect"); + t_vdl(stream)->get_eq = dlsymm(t_vdl(stream)->handle,"vixPlaybackGetEq"); + t_vdl(stream)->set_eq = dlsymm(t_vdl(stream)->handle,"vixPlaybackSetEq"); + t_vdl(stream)->get_gkey = dlsymm(t_vdl(stream)->handle,"vixGetGrKeys"); + t_vdl(stream)->set_gkey = dlsymm(t_vdl(stream)->handle,"vixSetGrKeys"); + t_vdl(stream)->get_deint = dlsymm(t_vdl(stream)->handle,"vixPlaybackGetDeint"); + t_vdl(stream)->set_deint = dlsymm(t_vdl(stream)->handle,"vixPlaybackSetDeint"); + t_vdl(stream)->copy_frame = dlsymm(t_vdl(stream)->handle,"vixPlaybackCopyFrame"); + t_vdl(stream)->query_dma = dlsymm(t_vdl(stream)->handle,"vixQueryDMAStatus"); + t_vdl(stream)->get_num_fx = dlsymm(t_vdl(stream)->handle,"vixQueryNumOemEffects"); + t_vdl(stream)->get_fx = dlsymm(t_vdl(stream)->handle,"vixGetOemEffect"); + t_vdl(stream)->set_fx = dlsymm(t_vdl(stream)->handle,"vixSetOemEffect"); + /* check driver viability */ + if(!( t_vdl(stream)->get_caps && t_vdl(stream)->query_fourcc && + t_vdl(stream)->config_playback && t_vdl(stream)->playback_on && + t_vdl(stream)->playback_off)) + { + printf("vidixlib: Incomplete driver: some of essential features are missed in it.\n"); + return 0; + } + return 1; +} + +#ifndef RTLD_GLOBAL +#define RTLD_GLOBAL RTLD_LAZY +#endif +#ifndef RTLD_NOW +#define RTLD_NOW RTLD_LAZY +#endif + +static int vdl_probe_driver(VDL_HANDLE stream,const char *path,const char *name,unsigned cap,int verbose) +{ + vidix_capability_t vid_cap; + unsigned (*_ver)(void); + int (*_probe)(int,int); + int (*_cap)(vidix_capability_t*); + strncpy(drv_name,path,sizeof(drv_name)); + drv_name[sizeof(drv_name) - 1] = '\0'; + strncat(drv_name,name,sizeof(drv_name) - strlen(drv_name) - 1); + if(verbose) printf("vidixlib: PROBING: %s\n",drv_name); + + { + const char* slash = strrchr(drv_name, '/'); + if (slash) { + for (dl_idx = 0; drv_snames[dl_idx]; dl_idx++) { + if (!strncmp(slash + 1, drv_snames[dl_idx], strlen(drv_snames[dl_idx]))) + break; // locate the name + } + if (!drv_snames[dl_idx]) dl_idx = -1; + } + } + if (dl_idx < 0) + if(!(t_vdl(stream)->handle = dlopen(drv_name,RTLD_LAZY|RTLD_GLOBAL))) { + if(verbose) printf("vidixlib: %s not driver: %s\n",drv_name,dlerror()); + return 0; + } + _ver = dlsymm(t_vdl(stream)->handle,"vixGetVersion"); + _probe = dlsymm(t_vdl(stream)->handle,"vixProbe"); + _cap = dlsymm(t_vdl(stream)->handle,"vixGetCapability"); + if(_ver) + { + if((*_ver)() != VIDIX_VERSION) + { + if(verbose) printf("vidixlib: %s has wrong version\n",drv_name); + err: + dlclose(t_vdl(stream)->handle); + t_vdl(stream)->handle = 0; + dl_idx = -1; + return 0; + } + } + else + { + fatal_err: + if(verbose) printf("vidixlib: %s has no function definition\n",drv_name); + goto err; + } + if(_probe) { if((*_probe)(verbose,PROBE_NORMAL) != 0) goto err; } + else goto fatal_err; + if(_cap) { if((*_cap)(&vid_cap) != 0) goto err; } + else goto fatal_err; + if((vid_cap.type & cap) != cap) + { + if(verbose) printf("vidixlib: Found %s but has no required capability\n",drv_name); + goto err; + } + if(verbose) printf("vidixlib: %s probed o'k\n",drv_name); + return 1; +} + +static int vdl_find_driver(VDL_HANDLE stream,const char *path,unsigned cap,int verbose) +{ + DIR *dstream; + struct dirent *name; + int done = 0; + if(!(dstream = opendir(path))) return 0; + while(!done) + { + name = readdir(dstream); + if(name) + { + if(name->d_name[0] != '.' && strstr(name->d_name, ".so")) + if(vdl_probe_driver(stream,path,name->d_name,cap,verbose)) break; + } + else done = 1; + } + closedir(dstream); + return done?0:1; +} + +VDL_HANDLE vdlOpen(const char *path,const char *name,unsigned cap,int verbose) +{ + vdl_stream_t *stream; + const char *drv_args=NULL; + int errcode; + if(!(stream = malloc(sizeof(vdl_stream_t)))) return NULL; + memset(stream,0,sizeof(vdl_stream_t)); + if(name) + { + unsigned (*ver)(void); + int (*probe)(int,int); + unsigned version = 0; + unsigned char *arg_sep; + arg_sep = strchr(name,':'); + if(arg_sep) { *arg_sep='\0'; drv_args = &arg_sep[1]; } + strncpy(drv_name,path,sizeof(drv_name)); + drv_name[sizeof(drv_name) - 1] = '\0'; + strncat(drv_name,name,sizeof(drv_name) - strlen(drv_name) - 1); + { + const char* slash = strrchr(drv_name, '/'); + if (slash) { + for (dl_idx = 0; drv_snames[dl_idx]; dl_idx++) { + if (!strncmp(slash + 1, drv_snames[dl_idx], strlen(drv_snames[dl_idx]))) + break; // locate the name + } + if (!drv_snames[dl_idx]) dl_idx = -1; + } + } + if (dl_idx < 0) + if(!(t_vdl(stream)->handle = dlopen(drv_name,RTLD_NOW|RTLD_GLOBAL))) + { + if (verbose) + printf("vidixlib: dlopen error: %s\n", dlerror()); + err: + vdlClose(stream); + return NULL; + } + ver = dlsymm(t_vdl(stream)->handle,"vixGetVersion"); + if(ver) version = (*ver)(); + if(version != VIDIX_VERSION) + goto err; + probe = dlsymm(t_vdl(stream)->handle,"vixProbe"); + if(probe) { if((*probe)(verbose,PROBE_FORCE)!=0) goto err; } + else goto err; + fill: + if(!vdl_fill_driver(stream)) goto err; + goto ok; + } + else + if(vdl_find_driver(stream,path,cap,verbose)) + { + if(verbose) printf("vidixlib: will use %s driver\n",drv_name); + goto fill; + } + else goto err; + ok: + if(t_vdl(stream)->init) + { + if(verbose) printf("vidixlib: Attempt to initialize driver at: %p\n",t_vdl(stream)->init); + if((errcode=t_vdl(stream)->init(drv_args))!=0) + { + if(verbose) printf("vidixlib: Can't init driver: %s\n",strerror(errcode)); + goto err; + } + } + if(verbose) printf("vidixlib: '%s'successfully loaded\n",drv_name); + return stream; +} + +void vdlClose(VDL_HANDLE stream) +{ + if(t_vdl(stream)->destroy) t_vdl(stream)->destroy(); + if(t_vdl(stream)->handle) dlclose(t_vdl(stream)->handle); + memset(stream,0,sizeof(vdl_stream_t)); /* <- it's not stupid */ + free(stream); + dl_idx = -1; +} + +int vdlGetCapability(VDL_HANDLE handle, vidix_capability_t *cap) +{ + return t_vdl(handle)->get_caps(cap); +} + +#define MPLAYER_IMGFMT_RGB (('R'<<24)|('G'<<16)|('B'<<8)) +#define MPLAYER_IMGFMT_BGR (('B'<<24)|('G'<<16)|('R'<<8)) +#define MPLAYER_IMGFMT_RGB_MASK 0xFFFFFF00 + +static uint32_t normalize_fourcc(uint32_t fourcc) +{ + if((fourcc & MPLAYER_IMGFMT_RGB_MASK) == (MPLAYER_IMGFMT_RGB|0) || + (fourcc & MPLAYER_IMGFMT_RGB_MASK) == (MPLAYER_IMGFMT_BGR|0)) + return bswap_32(fourcc); + else return fourcc; +} + +int vdlQueryFourcc(VDL_HANDLE handle,vidix_fourcc_t *f) +{ + f->fourcc = normalize_fourcc(f->fourcc); + return t_vdl(handle)->query_fourcc(f); +} + +int vdlConfigPlayback(VDL_HANDLE handle,vidix_playback_t *p) +{ + p->fourcc = normalize_fourcc(p->fourcc); + return t_vdl(handle)->config_playback(p); +} + +int vdlPlaybackOn(VDL_HANDLE handle) +{ + return t_vdl(handle)->playback_on(); +} + +int vdlPlaybackOff(VDL_HANDLE handle) +{ + return t_vdl(handle)->playback_off(); +} + +int vdlPlaybackFrameSelect(VDL_HANDLE handle, unsigned frame_idx ) +{ + return t_vdl(handle)->frame_sel ? t_vdl(handle)->frame_sel(frame_idx) : ENOSYS; +} + +int vdlPlaybackGetEq(VDL_HANDLE handle, vidix_video_eq_t * e) +{ + return t_vdl(handle)->get_eq ? t_vdl(handle)->get_eq(e) : ENOSYS; +} + +int vdlPlaybackSetEq(VDL_HANDLE handle, const vidix_video_eq_t * e) +{ + return t_vdl(handle)->set_eq ? t_vdl(handle)->set_eq(e) : ENOSYS; +} + +int vdlPlaybackCopyFrame(VDL_HANDLE handle, vidix_dma_t * f) +{ + return t_vdl(handle)->copy_frame ? t_vdl(handle)->copy_frame(f) : ENOSYS; +} + +int vdlQueryDMAStatus(VDL_HANDLE handle ) +{ + return t_vdl(handle)->query_dma ? t_vdl(handle)->query_dma() : ENOSYS; +} + +int vdlGetGrKeys(VDL_HANDLE handle, vidix_grkey_t * k) +{ + return t_vdl(handle)->get_gkey ? t_vdl(handle)->get_gkey(k) : ENOSYS; +} + +int vdlSetGrKeys(VDL_HANDLE handle, const vidix_grkey_t * k) +{ + return t_vdl(handle)->set_gkey ? t_vdl(handle)->set_gkey(k) : ENOSYS; +} + +int vdlPlaybackGetDeint(VDL_HANDLE handle, vidix_deinterlace_t * d) +{ + return t_vdl(handle)->get_deint ? t_vdl(handle)->get_deint(d) : ENOSYS; +} + +int vdlPlaybackSetDeint(VDL_HANDLE handle, const vidix_deinterlace_t * d) +{ + return t_vdl(handle)->set_deint ? t_vdl(handle)->set_deint(d) : ENOSYS; +} + +int vdlQueryNumOemEffects(VDL_HANDLE handle, unsigned * number ) +{ + return t_vdl(handle)->get_num_fx ? t_vdl(handle)->get_num_fx(number) : ENOSYS; +} + +int vdlGetOemEffect(VDL_HANDLE handle, vidix_oem_fx_t * f) +{ + return t_vdl(handle)->get_fx ? t_vdl(handle)->get_fx(f) : ENOSYS; +} + +int vdlSetOemEffect(VDL_HANDLE handle, const vidix_oem_fx_t * f) +{ + return t_vdl(handle)->set_fx ? t_vdl(handle)->set_fx(f) : ENOSYS; +} + +/* ABI related extensions */ +vidix_capability_t * vdlAllocCapabilityS( void ) +{ + vidix_capability_t *retval; + retval=malloc(sizeof(vidix_capability_t)); + if(retval) memset(retval,0,sizeof(vidix_capability_t)); + return retval; +} + +vidix_fourcc_t * vdlAllocFourccS( void ) +{ + vidix_fourcc_t *retval; + retval=malloc(sizeof(vidix_fourcc_t)); + if(retval) memset(retval,0,sizeof(vidix_fourcc_t)); + return retval; +} + +vidix_yuv_t * vdlAllocYUVS( void ) +{ + vidix_yuv_t *retval; + retval=malloc(sizeof(vidix_yuv_t)); + if(retval) memset(retval,0,sizeof(vidix_yuv_t)); + return retval; +} + +vidix_rect_t * vdlAllocRectS( void ) +{ + vidix_rect_t *retval; + retval=malloc(sizeof(vidix_rect_t)); + if(retval) memset(retval,0,sizeof(vidix_rect_t)); + return retval; +} + +vidix_playback_t * vdlAllocPlaybackS( void ) +{ + vidix_playback_t *retval; + retval=malloc(sizeof(vidix_playback_t)); + if(retval) memset(retval,0,sizeof(vidix_playback_t)); + return retval; +} + +vidix_grkey_t * vdlAllocGrKeyS( void ) +{ + vidix_grkey_t *retval; + retval=malloc(sizeof(vidix_grkey_t)); + if(retval) memset(retval,0,sizeof(vidix_grkey_t)); + return retval; +} + +vidix_video_eq_t * vdlAllocVideoEqS( void ) +{ + vidix_video_eq_t *retval; + retval=malloc(sizeof(vidix_video_eq_t)); + if(retval) memset(retval,0,sizeof(vidix_video_eq_t)); + return retval; +} + +vidix_deinterlace_t * vdlAllocDeinterlaceS( void ) +{ + vidix_deinterlace_t *retval; + retval=malloc(sizeof(vidix_deinterlace_t)); + if(retval) memset(retval,0,sizeof(vidix_deinterlace_t)); + return retval; +} + +vidix_dma_t * vdlAllocDmaS( void ) +{ + vidix_dma_t *retval; + retval=malloc(sizeof(vidix_dma_t)); + if(retval) memset(retval,0,sizeof(vidix_dma_t)); + return retval; +} + +vidix_oem_fx_t * vdlAllocOemFxS( void ) +{ + vidix_oem_fx_t *retval; + retval=malloc(sizeof(vidix_oem_fx_t)); + if(retval) memset(retval,0,sizeof(vidix_oem_fx_t)); + return retval; +} + +void vdlFreeCapabilityS(vidix_capability_t * _this) { free(_this); } +void vdlFreeFourccS( vidix_fourcc_t * _this ) { free(_this); } +void vdlFreePlaybackS( vidix_playback_t * _this ) { free(_this); } +void vdlFreeYUVS( vidix_yuv_t * _this) { free(_this); } +void vdlFreeRectS( vidix_rect_t * _this) { free(_this); } +void vdlFreeGrKeyS( vidix_grkey_t * _this) { free(_this); } +void vdlFreeVideoEqS( vidix_video_eq_t * _this) { free(_this); } +void vdlFreeDeinterlaceS( vidix_deinterlace_t * _this) { free(_this); } +void vdlFreeDmaS( vidix_dma_t * _this) { free(_this); } +void vdlFreeOemFxS( vidix_oem_fx_t * _this) { free(_this); } diff --git a/contrib/vidix/vidixlib.h b/contrib/vidix/vidixlib.h new file mode 100644 index 000000000..ebc3dd309 --- /dev/null +++ b/contrib/vidix/vidixlib.h @@ -0,0 +1,128 @@ +/* + * vidixlib.h + * VIDIXLib - Library for VIDeo Interface for *niX + * This interface is introduced as universal one to MPEG decoder, + * BES == Back End Scaler and YUV2RGB hw accelerators. + * In the future it may be expanded up to capturing and audio things. + * Main goal of this this interface imlpementation is providing DGA + * everywhere where it's possible (unlike X11 and other). + * Copyright 2002 Nick Kurshev + * Licence: GPL + * This interface is based on v4l2, fbvid.h, mga_vid.h projects + * and personally my ideas. + * NOTE: This interface is introduces as APP interface. + * Don't use it for driver. + * It provides multistreaming. This mean that APP can handle + * several streams simultaneously. (Example: Video capturing and video + * playback or capturing, video playback, audio encoding and so on). +*/ +#ifndef VIDIXLIB_H +#define VIDIXLIB_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "vidix.h" + +typedef void * VDL_HANDLE; + + /* returns library version */ +extern unsigned vdlGetVersion( void ); + + /* Opens corresponded video driver and returns handle + of associated stream. + path - specifies path where drivers are located. + name - specifies prefered driver name (can be NULL). + cap - specifies driver capability (TYPE_* constants). + verbose - specifies verbose level + returns !0 if ok else NULL. + */ +extern VDL_HANDLE vdlOpen(const char *path,const char *name,unsigned cap,int verbose); + /* Closes stream and corresponded driver. */ +extern void vdlClose(VDL_HANDLE stream); + + /* Queries driver capabilities. Return 0 if ok else errno */ +extern int vdlGetCapability(VDL_HANDLE, vidix_capability_t *); + + /* Queries support for given fourcc. Returns 0 if ok else errno */ +extern int vdlQueryFourcc(VDL_HANDLE,vidix_fourcc_t *); + + /* Returns 0 if ok else errno */ +extern int vdlConfigPlayback(VDL_HANDLE, vidix_playback_t *); + + /* Returns 0 if ok else errno */ +extern int vdlPlaybackOn(VDL_HANDLE); + + /* Returns 0 if ok else errno */ +extern int vdlPlaybackOff(VDL_HANDLE); + + /* Returns 0 if ok else errno */ +extern int vdlPlaybackFrameSelect(VDL_HANDLE, unsigned frame_idx ); + + /* Returns 0 if ok else errno */ +extern int vdlGetGrKeys(VDL_HANDLE, vidix_grkey_t * ); + + /* Returns 0 if ok else errno */ +extern int vdlSetGrKeys(VDL_HANDLE, const vidix_grkey_t * ); + + /* Returns 0 if ok else errno */ +extern int vdlPlaybackGetEq(VDL_HANDLE, vidix_video_eq_t * ); + + /* Returns 0 if ok else errno */ +extern int vdlPlaybackSetEq(VDL_HANDLE, const vidix_video_eq_t * ); + + /* Returns 0 if ok else errno */ +extern int vdlPlaybackGetDeint(VDL_HANDLE, vidix_deinterlace_t * ); + + /* Returns 0 if ok else errno */ +extern int vdlPlaybackSetDeint(VDL_HANDLE, const vidix_deinterlace_t * ); + + /* Returns 0 if ok else errno */ +extern int vdlQueryNumOemEffects(VDL_HANDLE, unsigned * number ); + + /* Returns 0 if ok else errno */ +extern int vdlGetOemEffect(VDL_HANDLE, vidix_oem_fx_t * ); + + /* Returns 0 if ok else errno */ +extern int vdlSetOemEffect(VDL_HANDLE, const vidix_oem_fx_t * ); + + + /* Returns 0 if ok else errno */ +extern int vdlPlaybackCopyFrame(VDL_HANDLE, vidix_dma_t * ); + + /* Returns 0 if DMA is available else errno (EBUSY) */ +extern int vdlQueryDMAStatus( VDL_HANDLE ); + +/* + ABI related extensions. + Note: you should use this functions if you are using shared version + of vidix. +*/ +extern vidix_capability_t * vdlAllocCapabilityS( void ); +extern vidix_fourcc_t * vdlAllocFourccS( void ); +extern vidix_playback_t * vdlAllocPlaybackS( void ); +extern vidix_yuv_t * vdlAllocYUVS( void ); +extern vidix_rect_t * vdlAllocRectS( void ); +extern vidix_grkey_t * vdlAllocGrKeyS( void ); +extern vidix_video_eq_t * vdlAllocVideoEqS( void ); +extern vidix_deinterlace_t * vdlAllocDeinterlaceS( void ); +extern vidix_dma_t * vdlAllocDmaS( void ); +extern vidix_oem_fx_t * vdlAllocOemFxS( void ); + +extern void vdlFreeCapabilityS(vidix_capability_t * ); +extern void vdlFreeFourccS( vidix_fourcc_t * ); +extern void vdlFreePlaybackS( vidix_playback_t * ); +extern void vdlFreeYUVS( vidix_yuv_t * ); +extern void vdlFreeRectS( vidix_rect_t * ); +extern void vdlFreeGrKeyS( vidix_grkey_t * ); +extern void vdlFreeVideoEqS( vidix_video_eq_t * ); +extern void vdlFreeDeinterlaceS( vidix_deinterlace_t * ); +extern void vdlFreeDmaS( vidix_dma_t * ); +extern void vdlFreeOemFxS( vidix_oem_fx_t * ); + +#ifdef __cplusplus +} +#endif + +#endif |