diff options
Diffstat (limited to 'src')
| -rw-r--r-- | src/video_out/vidix/drivers/genfb_vid.c | 51 | ||||
| -rw-r--r-- | src/video_out/vidix/drivers/mach64.h | 1368 | ||||
| -rw-r--r-- | src/video_out/vidix/drivers/mach64_vid.c | 358 | ||||
| -rw-r--r-- | src/video_out/vidix/drivers/mga_vid.c | 215 | ||||
| -rw-r--r-- | src/video_out/vidix/drivers/nvidia_vid.c | 50 | ||||
| -rw-r--r-- | src/video_out/vidix/drivers/pm3_regs.h | 8 | ||||
| -rw-r--r-- | src/video_out/vidix/drivers/pm3_vid.c | 60 | ||||
| -rw-r--r-- | src/video_out/vidix/drivers/radeon.h | 71 | ||||
| -rw-r--r-- | src/video_out/vidix/drivers/radeon_vid.c | 469 |
9 files changed, 1753 insertions, 897 deletions
diff --git a/src/video_out/vidix/drivers/genfb_vid.c b/src/video_out/vidix/drivers/genfb_vid.c index 40340842d..3dacd4beb 100644 --- a/src/video_out/vidix/drivers/genfb_vid.c +++ b/src/video_out/vidix/drivers/genfb_vid.c @@ -10,9 +10,12 @@ #include "../fourcc.h" #include "../../libdha/libdha.h" #include "../../libdha/pci_ids.h" +#include "../../libdha/pci_names.h" #define DEMO_DRIVER 1 +#define GENFB_MSG "[genfb-demo-driver] " + static int fd; static void *mmio_base = 0; @@ -48,32 +51,58 @@ unsigned int vixGetVersion(void) int vixProbe(int verbose,int force) { +#if 0 int err = 0; #ifdef DEMO_DRIVER err = ENOSYS; #endif - printf("[genfb] probe\n"); + printf(GENFB_MSG"probe\n"); fd = open("/dev/fb0", O_RDWR); if (fd < 0) { - printf("Error occured durint open: %s\n", strerror(errno)); + printf(GENFB_MSG"Error occured durint open: %s\n", strerror(errno)); err = errno; } probed = 1; return(err); +#else + pciinfo_t lst[MAX_PCI_DEVICES]; + unsigned i,num_pci; + int err; + err = pci_scan(lst,&num_pci); + if(err) + { + printf(GENFB_MSG"Error occured during pci scan: %s\n",strerror(err)); + return err; + } + else + { + err = ENXIO; + for(i=0;i<num_pci;i++) + { + if(verbose) + printf(GENFB_MSG" Found chip [%04X:%04X] '%s' '%s'\n" + ,lst[i].vendor + ,lst[i].device + ,pci_vendor_name(lst[i].vendor) + ,pci_device_name(lst[i].vendor,lst[i].device)); + } + } + return ENOSYS; +#endif } int vixInit(void) { - printf("[genfb] init\n"); + printf(GENFB_MSG"init\n"); if (!probed) { - printf("Driver was not probed but is being initialized\n"); + printf(GENFB_MSG"Driver was not probed but is being initialized\n"); return(EINTR); } @@ -82,7 +111,7 @@ int vixInit(void) void vixDestroy(void) { - printf("[genfb] destory\n"); + printf(GENFB_MSG"destory\n"); return; } @@ -94,7 +123,7 @@ int vixGetCapability(vidix_capability_t *to) int vixQueryFourcc(vidix_fourcc_t *to) { - printf("[genfb] query fourcc (%x)\n", to->fourcc); + printf(GENFB_MSG"query fourcc (%x)\n", to->fourcc); to->depth = VID_DEPTH_1BPP | VID_DEPTH_2BPP | VID_DEPTH_4BPP | VID_DEPTH_8BPP | @@ -108,7 +137,7 @@ int vixQueryFourcc(vidix_fourcc_t *to) int vixConfigPlayback(vidix_playback_t *info) { - printf("[genfb] config playback\n"); + printf(GENFB_MSG"config playback\n"); info->num_frames = 2; info->frame_size = info->src.w*info->src.h+(info->src.w*info->src.h)/2; @@ -120,7 +149,7 @@ int vixConfigPlayback(vidix_playback_t *info) info->offset.v = ((info->src.w+31) & ~31) * info->src.h; info->offset.u = info->offset.v+((info->src.w+31) & ~31) * info->src.h/4; info->dga_addr = malloc(info->num_frames*info->frame_size); - printf("[genfb] frame_size: %d, dga_addr: %x\n", + printf(GENFB_MSG"frame_size: %d, dga_addr: %x\n", info->frame_size, info->dga_addr); return(0); @@ -128,18 +157,18 @@ int vixConfigPlayback(vidix_playback_t *info) int vixPlaybackOn(void) { - printf("[genfb] playback on\n"); + printf(GENFB_MSG"playback on\n"); return(0); } int vixPlaybackOff(void) { - printf("[genfb] playback off\n"); + printf(GENFB_MSG"playback off\n"); return(0); } int vixPlaybackFrameSelect(unsigned int frame) { - printf("[genfb] frameselect: %d\n", frame); + printf(GENFB_MSG"frameselect: %d\n", frame); return(0); } diff --git a/src/video_out/vidix/drivers/mach64.h b/src/video_out/vidix/drivers/mach64.h index 085d40151..807efdb8d 100644 --- a/src/video_out/vidix/drivers/mach64.h +++ b/src/video_out/vidix/drivers/mach64.h @@ -484,29 +484,29 @@ This means that this sources don't support ISA and VLB cards */ /* ATI Mach64 register definitions */ #define CRTC_H_TOTAL_DISP IOPortTag(0x00u, 0x00u) -#define CRTC_H_TOTAL 0x000001fful +# define CRTC_H_TOTAL 0x000001fful /* ? 0x0000fe00ul */ -#define CRTC_H_DISP 0x01ff0000ul +# define CRTC_H_DISP 0x01ff0000ul /* ? 0xfe000000ul */ #define CRTC_H_SYNC_STRT_WID IOPortTag(0x01u, 0x01u) -#define CRTC_H_SYNC_STRT 0x000000fful -#define CRTC_H_SYNC_DLY 0x00000700ul +# define CRTC_H_SYNC_STRT 0x000000fful +# define CRTC_H_SYNC_DLY 0x00000700ul /* ? 0x00000800ul */ -#define CRTC_H_SYNC_STRT_HI 0x00001000ul +# define CRTC_H_SYNC_STRT_HI 0x00001000ul /* ? 0x0000e000ul */ -#define CRTC_H_SYNC_WID 0x001f0000ul -#define CRTC_H_SYNC_POL 0x00200000ul +# define CRTC_H_SYNC_WID 0x001f0000ul +# define CRTC_H_SYNC_POL 0x00200000ul /* ? 0xffc00000ul */ #define CRTC_V_TOTAL_DISP IOPortTag(0x02u, 0x02u) -#define CRTC_V_TOTAL 0x000007fful +# define CRTC_V_TOTAL 0x000007fful /* ? 0x0000f800ul */ -#define CRTC_V_DISP 0x07ff0000ul +# define CRTC_V_DISP 0x07ff0000ul /* ? 0xf8000000ul */ #define CRTC_V_SYNC_STRT_WID IOPortTag(0x03u, 0x03u) -#define CRTC_V_SYNC_STRT 0x000007fful +# define CRTC_V_SYNC_STRT 0x000007fful /* ? 0x0000f800ul */ -#define CRTC_V_SYNC_WID 0x001f0000ul -#define CRTC_V_SYNC_POL 0x00200000ul +# define CRTC_V_SYNC_WID 0x001f0000ul +# define CRTC_V_SYNC_POL 0x00200000ul /* ? 0xffc00000ul */ #define CRTC_VLINE_CRNT_VLINE IOPortTag(0x04u, 0x04u) #define CRTC_VLINE 0x000007fful @@ -514,45 +514,45 @@ This means that this sources don't support ISA and VLB cards */ #define CRTC_CRNT_VLINE 0x07ff0000ul /* ? 0xf8000000ul */ #define CRTC_OFF_PITCH IOPortTag(0x05u, 0x05u) -#define CRTC_OFFSET 0x000ffffful -#define CRTC_OFFSET_VGA 0x0003fffful -#define CRTC_OFFSET_LOCK 0x00100000ul /* XC/XL */ +# define CRTC_OFFSET 0x000ffffful +# define CRTC_OFFSET_VGA 0x0003fffful +# define CRTC_OFFSET_LOCK 0x00100000ul /* XC/XL */ /* ? 0x00200000ul */ -#define CRTC_PITCH 0xffc00000ul +# define CRTC_PITCH 0xffc00000ul #define CRTC_INT_CNTL IOPortTag(0x06u, 0x06u) -#define CRTC_VBLANK 0x00000001ul -#define CRTC_VBLANK_INT_EN 0x00000002ul -#define CRTC_VBLANK_INT 0x00000004ul -#define CRTC_VLINE_INT_EN 0x00000008ul -#define CRTC_VLINE_INT 0x00000010ul -#define CRTC_VLINE_SYNC 0x00000020ul -#define CRTC_FRAME 0x00000040ul -#define CRTC_SNAPSHOT_INT_EN 0x00000080ul /* GTPro */ -#define CRTC_SNAPSHOT_INT 0x00000100ul /* GTPro */ -#define CRTC_I2C_INT_EN 0x00000200ul /* GTPro */ -#define CRTC_I2C_INT 0x00000400ul /* GTPro */ -#define CRTC2_VBLANK 0x00000800ul /* LTPro */ -#define CRTC2_VBLANK_INT_EN 0x00001000ul /* LTPro */ -#define CRTC2_VBLANK_INT 0x00002000ul /* LTPro */ -#define CRTC2_VLINE_INT_EN 0x00004000ul /* LTPro */ -#define CRTC2_VLINE_INT 0x00008000ul /* LTPro */ -#define CRTC_CAPBUF0_INT_EN 0x00010000ul /* VT/GT */ -#define CRTC_CAPBUF0_INT 0x00020000ul /* VT/GT */ -#define CRTC_CAPBUF1_INT_EN 0x00040000ul /* VT/GT */ -#define CRTC_CAPBUF1_INT 0x00080000ul /* VT/GT */ -#define CRTC_OVERLAY_EOF_INT_EN 0x00100000ul /* VT/GT */ -#define CRTC_OVERLAY_EOF_INT 0x00200000ul /* VT/GT */ -#define CRTC_ONESHOT_CAP_INT_EN 0x00400000ul /* VT/GT */ -#define CRTC_ONESHOT_CAP_INT 0x00800000ul /* VT/GT */ -#define CRTC_BUSMASTER_EOL_INT_EN 0x01000000ul /* VTB/GTB/LT */ -#define CRTC_BUSMASTER_EOL_INT 0x02000000ul /* VTB/GTB/LT */ -#define CRTC_GP_INT_EN 0x04000000ul /* VTB/GTB/LT */ -#define CRTC_GP_INT 0x08000000ul /* VTB/GTB/LT */ -#define CRTC2_VLINE_SYNC 0x10000000ul /* LTPro */ -#define CRTC_SNAPSHOT2_INT_EN 0x20000000ul /* LTPro */ -#define CRTC_SNAPSHOT2_INT 0x40000000ul /* LTPro */ -#define CRTC_VBLANK_BIT2_INT 0x80000000ul /* GTPro */ -#define CRTC_INT_ENS /* *** UPDATE ME *** */ \ +# define CRTC_VBLANK 0x00000001ul +# define CRTC_VBLANK_INT_EN 0x00000002ul +# define CRTC_VBLANK_INT 0x00000004ul +# define CRTC_VLINE_INT_EN 0x00000008ul +# define CRTC_VLINE_INT 0x00000010ul +# define CRTC_VLINE_SYNC 0x00000020ul +# define CRTC_FRAME 0x00000040ul +# define CRTC_SNAPSHOT_INT_EN 0x00000080ul /* GTPro */ +# define CRTC_SNAPSHOT_INT 0x00000100ul /* GTPro */ +# define CRTC_I2C_INT_EN 0x00000200ul /* GTPro */ +# define CRTC_I2C_INT 0x00000400ul /* GTPro */ +# define CRTC2_VBLANK 0x00000800ul /* LTPro */ +# define CRTC2_VBLANK_INT_EN 0x00001000ul /* LTPro */ +# define CRTC2_VBLANK_INT 0x00002000ul /* LTPro */ +# define CRTC2_VLINE_INT_EN 0x00004000ul /* LTPro */ +# define CRTC2_VLINE_INT 0x00008000ul /* LTPro */ +# define CRTC_CAPBUF0_INT_EN 0x00010000ul /* VT/GT */ +# define CRTC_CAPBUF0_INT 0x00020000ul /* VT/GT */ +# define CRTC_CAPBUF1_INT_EN 0x00040000ul /* VT/GT */ +# define CRTC_CAPBUF1_INT 0x00080000ul /* VT/GT */ +# define CRTC_OVERLAY_EOF_INT_EN 0x00100000ul /* VT/GT */ +# define CRTC_OVERLAY_EOF_INT 0x00200000ul /* VT/GT */ +# define CRTC_ONESHOT_CAP_INT_EN 0x00400000ul /* VT/GT */ +# define CRTC_ONESHOT_CAP_INT 0x00800000ul /* VT/GT */ +# define CRTC_BUSMASTER_EOL_INT_EN 0x01000000ul /* VTB/GTB/LT */ +# define CRTC_BUSMASTER_EOL_INT 0x02000000ul /* VTB/GTB/LT */ +# define CRTC_GP_INT_EN 0x04000000ul /* VTB/GTB/LT */ +# define CRTC_GP_INT 0x08000000ul /* VTB/GTB/LT */ +# define CRTC2_VLINE_SYNC 0x10000000ul /* LTPro */ +# define CRTC_SNAPSHOT2_INT_EN 0x20000000ul /* LTPro */ +# define CRTC_SNAPSHOT2_INT 0x40000000ul /* LTPro */ +# define CRTC_VBLANK_BIT2_INT 0x80000000ul /* GTPro */ +# define CRTC_INT_ENS /* *** UPDATE ME *** */ \ ( \ CRTC_VBLANK_INT_EN | \ CRTC_VLINE_INT_EN | \ @@ -569,7 +569,7 @@ This means that this sources don't support ISA and VLB cards */ CRTC_SNAPSHOT2_INT_EN | \ 0 \ ) -#define CRTC_INT_ACKS /* *** UPDATE ME *** */ \ +# define CRTC_INT_ACKS /* *** UPDATE ME *** */ \ ( \ CRTC_VBLANK_INT | \ CRTC_VLINE_INT | \ @@ -588,62 +588,62 @@ This means that this sources don't support ISA and VLB cards */ 0 \ ) #define CRTC_GEN_CNTL IOPortTag(0x07u, 0x07u) -#define CRTC_DBL_SCAN_EN 0x00000001ul -#define CRTC_INTERLACE_EN 0x00000002ul -#define CRTC_HSYNC_DIS 0x00000004ul -#define CRTC_VSYNC_DIS 0x00000008ul -#define CRTC_CSYNC_EN 0x00000010ul -#define CRTC_PIX_BY_2_EN 0x00000020ul -#define CRTC2_DBL_SCAN_EN 0x00000020ul /* LTPro */ -#define CRTC_DISPLAY_DIS 0x00000040ul -#define CRTC_VGA_XOVERSCAN 0x00000080ul -#define CRTC_PIX_WIDTH 0x00000700ul -#define CRTC_BYTE_PIX_ORDER 0x00000800ul -#define CRTC_VSYNC_INT_EN 0x00001000ul /* XC/XL */ -#define CRTC_VSYNC_INT 0x00002000ul /* XC/XL */ -#define CRTC_FIFO_OVERFILL 0x0000c000ul /* VT/GT */ -#define CRTC2_VSYNC_INT_EN 0x00004000ul /* XC/XL */ -#define CRTC2_VSYNC_INT 0x00008000ul /* XC/XL */ -#define CRTC_FIFO_LWM 0x000f0000ul -#define CRTC_HVSYNC_IO_DRIVE 0x00010000ul /* XC/XL */ -#define CRTC2_PIX_WIDTH 0x000e0000ul /* LTPro */ -#define CRTC_VGA_128KAP_PAGING 0x00100000ul /* VT/GT */ -#define CRTC_DISPREQ_ONLY 0x00200000ul /* VT/GT */ -#define CRTC_VFC_SYNC_TRISTATE 0x00200000ul /* VTB/GTB/LT */ -#define CRTC2_EN 0x00200000ul /* LTPro */ -#define CRTC_LOCK_REGS 0x00400000ul /* VT/GT */ -#define CRTC_SYNC_TRISTATE 0x00800000ul /* VT/GT */ -#define CRTC_EXT_DISP_EN 0x01000000ul -#define CRTC_EN 0x02000000ul -#define CRTC_DISP_REQ_EN 0x04000000ul -#define CRTC_VGA_LINEAR 0x08000000ul -#define CRTC_VSYNC_FALL_EDGE 0x10000000ul -#define CRTC_VGA_TEXT_132 0x20000000ul -#define CRTC_CNT_EN 0x40000000ul -#define CRTC_CUR_B_TEST 0x80000000ul -#define CRTC_INT_ENS_X /* *** UPDATE ME *** */ \ +# define CRTC_DBL_SCAN_EN 0x00000001ul +# define CRTC_INTERLACE_EN 0x00000002ul +# define CRTC_HSYNC_DIS 0x00000004ul +# define CRTC_VSYNC_DIS 0x00000008ul +# define CRTC_CSYNC_EN 0x00000010ul +# define CRTC_PIX_BY_2_EN 0x00000020ul +# define CRTC2_DBL_SCAN_EN 0x00000020ul /* LTPro */ +# define CRTC_DISPLAY_DIS 0x00000040ul +# define CRTC_VGA_XOVERSCAN 0x00000080ul +# define CRTC_PIX_WIDTH 0x00000700ul +# define CRTC_BYTE_PIX_ORDER 0x00000800ul +# define CRTC_VSYNC_INT_EN 0x00001000ul /* XC/XL */ +# define CRTC_VSYNC_INT 0x00002000ul /* XC/XL */ +# define CRTC_FIFO_OVERFILL 0x0000c000ul /* VT/GT */ +# define CRTC2_VSYNC_INT_EN 0x00004000ul /* XC/XL */ +# define CRTC2_VSYNC_INT 0x00008000ul /* XC/XL */ +# define CRTC_FIFO_LWM 0x000f0000ul +# define CRTC_HVSYNC_IO_DRIVE 0x00010000ul /* XC/XL */ +# define CRTC2_PIX_WIDTH 0x000e0000ul /* LTPro */ +# define CRTC_VGA_128KAP_PAGING 0x00100000ul /* VT/GT */ +# define CRTC_DISPREQ_ONLY 0x00200000ul /* VT/GT */ +# define CRTC_VFC_SYNC_TRISTATE 0x00200000ul /* VTB/GTB/LT */ +# define CRTC2_EN 0x00200000ul /* LTPro */ +# define CRTC_LOCK_REGS 0x00400000ul /* VT/GT */ +# define CRTC_SYNC_TRISTATE 0x00800000ul /* VT/GT */ +# define CRTC_EXT_DISP_EN 0x01000000ul +# define CRTC_EN 0x02000000ul +# define CRTC_DISP_REQ_EN 0x04000000ul +# define CRTC_VGA_LINEAR 0x08000000ul +# define CRTC_VSYNC_FALL_EDGE 0x10000000ul +# define CRTC_VGA_TEXT_132 0x20000000ul +# define CRTC_CNT_EN 0x40000000ul +# define CRTC_CUR_B_TEST 0x80000000ul +# define CRTC_INT_ENS_X /* *** UPDATE ME *** */ \ ( \ CRTC_VSYNC_INT_EN | \ CRTC2_VSYNC_INT_EN | \ 0 \ ) -#define CRTC_INT_ACKS_X /* *** UPDATE ME *** */ \ +# define CRTC_INT_ACKS_X /* *** UPDATE ME *** */ \ ( \ CRTC_VSYNC_INT | \ CRTC2_VSYNC_INT | \ 0 \ ) #define DSP_CONFIG BlockIOTag(0x08u) /* VTB/GTB/LT */ -#define DSP_XCLKS_PER_QW 0x00003ffful +# define DSP_XCLKS_PER_QW 0x00003ffful /* ? 0x00004000ul */ -#define DSP_FLUSH_WB 0x00008000ul -#define DSP_LOOP_LATENCY 0x000f0000ul -#define DSP_PRECISION 0x00700000ul +# define DSP_FLUSH_WB 0x00008000ul +# define DSP_LOOP_LATENCY 0x000f0000ul +# define DSP_PRECISION 0x00700000ul /* ? 0xff800000ul */ #define DSP_ON_OFF BlockIOTag(0x09u) /* VTB/GTB/LT */ -#define DSP_OFF 0x000007fful +# define DSP_OFF 0x000007fful /* ? 0x0000f800ul */ -#define DSP_ON 0x07ff0000ul +# define DSP_ON 0x07ff0000ul /* ? 0xf8000000ul */ #define TIMER_CONFIG BlockIOTag(0x0au) /* VTB/GTB/LT */ #define MEM_BUF_CNTL BlockIOTag(0x0bu) /* VTB/GTB/LT */ @@ -658,31 +658,31 @@ This means that this sources don't support ISA and VLB cards */ #define DSTN_CONTROL BlockIOTag(0x0fu) /* LT */ #define I2C_CNTL_0 BlockIOTag(0x0fu) /* GTPro */ #define OVR_CLR IOPortTag(0x08u, 0x10u) -#define OVR_CLR_8 0x000000fful -#define OVR_CLR_B 0x0000ff00ul -#define OVR_CLR_G 0x00ff0000ul -#define OVR_CLR_R 0xff000000ul +# define OVR_CLR_8 0x000000fful +# define OVR_CLR_B 0x0000ff00ul +# define OVR_CLR_G 0x00ff0000ul +# define OVR_CLR_R 0xff000000ul #define OVR_WID_LEFT_RIGHT IOPortTag(0x09u, 0x11u) -#define OVR_WID_LEFT 0x0000003ful /* 0x0f on <LT */ +# define OVR_WID_LEFT 0x0000003ful /* 0x0f on <LT */ /* ? 0x0000ffc0ul */ -#define OVR_WID_RIGHT 0x003f0000ul /* 0x0f0000 on <LT */ +# define OVR_WID_RIGHT 0x003f0000ul /* 0x0f0000 on <LT */ /* ? 0xffc00000ul */ #define OVR_WID_TOP_BOTTOM IOPortTag(0x0au, 0x12u) -#define OVR_WID_TOP 0x000001fful /* 0x00ff on <LT */ +# define OVR_WID_TOP 0x000001fful /* 0x00ff on <LT */ /* ? 0x0000fe00ul */ -#define OVR_WID_BOTTOM 0x01ff0000ul /* 0x00ff0000 on <LT */ +# define OVR_WID_BOTTOM 0x01ff0000ul /* 0x00ff0000 on <LT */ /* ? 0xfe000000ul */ #define VGA_DSP_CONFIG BlockIOTag(0x13u) /* VTB/GTB/LT */ -#define VGA_DSP_XCLKS_PER_QW DSP_XCLKS_PER_QW +# define VGA_DSP_XCLKS_PER_QW DSP_XCLKS_PER_QW /* ? 0x000fc000ul */ -#define VGA_DSP_PREC_PCLKBY2 0x00700000ul +# define VGA_DSP_PREC_PCLKBY2 0x00700000ul /* ? 0x00800000ul */ -#define VGA_DSP_PREC_PCLK 0x07000000ul +# define VGA_DSP_PREC_PCLK 0x07000000ul /* ? 0xf8000000ul */ #define VGA_DSP_ON_OFF BlockIOTag(0x14u) /* VTB/GTB/LT */ -#define VGA_DSP_OFF DSP_OFF +# define VGA_DSP_OFF DSP_OFF /* ? 0x0000f800ul */ -#define VGA_DSP_ON DSP_ON +# define VGA_DSP_ON DSP_ON /* ? 0xf8000000ul */ #define DSP2_CONFIG BlockIOTag(0x15u) /* LTPro */ #define DSP2_ON_OFF BlockIOTag(0x16u) /* LTPro */ @@ -691,110 +691,110 @@ This means that this sources don't support ISA and VLB cards */ #define CUR_CLR0 IOPortTag(0x0bu, 0x18u) #define CUR_CLR1 IOPortTag(0x0cu, 0x19u) /* These are for both CUR_CLR0 and CUR_CLR1 */ -#define CUR_CLR_I 0x000000fful -#define CUR_CLR_B 0x0000ff00ul -#define CUR_CLR_G 0x00ff0000ul -#define CUR_CLR_R 0xff000000ul -#define CUR_CLR (CUR_CLR_R | CUR_CLR_G | CUR_CLR_B) +# define CUR_CLR_I 0x000000fful +# define CUR_CLR_B 0x0000ff00ul +# define CUR_CLR_G 0x00ff0000ul +# define CUR_CLR_R 0xff000000ul +# define CUR_CLR (CUR_CLR_R | CUR_CLR_G | CUR_CLR_B) #define CUR_OFFSET IOPortTag(0x0du, 0x1au) #define CUR_HORZ_VERT_POSN IOPortTag(0x0eu, 0x1bu) -#define CUR_HORZ_POSN 0x000007fful +# define CUR_HORZ_POSN 0x000007fful /* ? 0x0000f800ul */ -#define CUR_VERT_POSN 0x07ff0000ul +# define CUR_VERT_POSN 0x07ff0000ul /* ? 0xf8000000ul */ #define CUR_HORZ_VERT_OFF IOPortTag(0x0fu, 0x1cu) -#define CUR_HORZ_OFF 0x0000007ful +# define CUR_HORZ_OFF 0x0000007ful /* ? 0x0000ff80ul */ -#define CUR_VERT_OFF 0x007f0000ul +# define CUR_VERT_OFF 0x007f0000ul /* ? 0xff800000ul */ #define CONFIG_PANEL BlockIOTag(0x1du) /* LT */ -#define PANEL_FORMAT 0x00000007ul +# define PANEL_FORMAT 0x00000007ul /* ? 0x00000008ul */ -#define PANEL_TYPE 0x000000f0ul -#define NO_OF_GREY 0x00000700ul -#define MOD_GEN 0x00001800ul -#define EXT_LVDS_CLK 0x00001800ul /* LTPro */ -#define BLINK_RATE 0x00006000ul -#define BLINK_RATE_PRO 0x00002000ul /* LTPro */ -#define DONT_SHADOW_HEND 0x00004000ul /* LTPro */ -#define DONT_USE_F32KHZ 0x00008000ul -#define LCD_IO_DRIVE 0x00008000ul /* XC/XL */ -#define FP_POL 0x00010000ul -#define LP_POL 0x00020000ul -#define DTMG_POL 0x00040000ul -#define SCK_POL 0x00080000ul -#define DITHER_SEL 0x00300000ul -#define INVERSE_VIDEO_EN 0x00400000ul -#define BL_CLK_SEL 0x01800000ul -#define BL_LEVEL 0x0e000000ul -#define BL_CLK_SEL_PRO 0x00800000ul /* LTPro */ -#define BL_LEVEL_PRO 0x03000000ul /* LTPro */ -#define BIAS_LEVEL_PRO 0x0c000000ul /* LTPro */ -#define HSYNC_DELAY 0xf0000000ul +# define PANEL_TYPE 0x000000f0ul +# define NO_OF_GREY 0x00000700ul +# define MOD_GEN 0x00001800ul +# define EXT_LVDS_CLK 0x00001800ul /* LTPro */ +# define BLINK_RATE 0x00006000ul +# define BLINK_RATE_PRO 0x00002000ul /* LTPro */ +# define DONT_SHADOW_HEND 0x00004000ul /* LTPro */ +# define DONT_USE_F32KHZ 0x00008000ul +# define LCD_IO_DRIVE 0x00008000ul /* XC/XL */ +# define FP_POL 0x00010000ul +# define LP_POL 0x00020000ul +# define DTMG_POL 0x00040000ul +# define SCK_POL 0x00080000ul +# define DITHER_SEL 0x00300000ul +# define INVERSE_VIDEO_EN 0x00400000ul +# define BL_CLK_SEL 0x01800000ul +# define BL_LEVEL 0x0e000000ul +# define BL_CLK_SEL_PRO 0x00800000ul /* LTPro */ +# define BL_LEVEL_PRO 0x03000000ul /* LTPro */ +# define BIAS_LEVEL_PRO 0x0c000000ul /* LTPro */ +# define HSYNC_DELAY 0xf0000000ul #define TV_OUT_INDEX BlockIOTag(0x1du) /* LTPro */ -#define TV_REG_INDEX 0x000000fful -#define TV_ON 0x00000100ul +# define TV_REG_INDEX 0x000000fful +# define TV_ON 0x00000100ul /* ? 0xfffffe00ul */ #define GP_IO IOPortTag(0x1eu, 0x1eu) /* VT/GT */ #define GP_IO_CNTL BlockIOTag(0x1fu) /* VT/GT */ #define HW_DEBUG BlockIOTag(0x1fu) /* VTB/GTB/LT */ -#define FAST_SRCCOPY_DIS 0x00000001ul -#define BYPASS_SUBPIC_DBF 0x00000001ul /* XL/XC */ -#define SRC_AUTONA_FIX_DIS 0x00000002ul -#define SYNC_PD_EN 0x00000002ul /* Mobility */ -#define DISP_QW_FIX_DIS 0x00000004ul -#define GUIDST_WB_EXP_DIS 0x00000008ul -#define CYC_ALL_FIX_DIS 0x00000008ul /* GTPro */ -#define AGPPLL_FIX_EN 0x00000008ul /* Mobility */ -#define SRC_AUTONA_ALWAYS_EN 0x00000010ul -#define GUI_BEATS_HOST_P 0x00000010ul /* GTPro */ -#define DRV_CNTL_DQMB_WEB 0x00000020ul -#define FAST_FILL_SCISSOR_DIS 0x00000020ul /* GT2c/VT4 */ -#define INTER_BLIT_FIX_DIS 0x00000020ul /* GTPro */ -#define DRV_CNTL_MA 0x00000040ul -#define AUTO_BLKWRT_COLOR_DIS 0x00000040ul /* GT2c/VT4 */ -#define INTER_PRIM_DIS 0x00000040ul /* GTPro */ -#define DRV_CNTL_MD 0x00000080ul -#define CHG_DEV_ID 0x00000100ul -#define SRC_TRACK_DST_FIX_DIS 0x00000200ul -#define HCLK_FB_SKEW 0x00000380ul /* GT2c/VT4 */ -#define SRC_TRACK_DST_FIX_DIS_P 0x00000080ul /* GTPro */ -#define AUTO_BLKWRT_COLOR_DIS_P 0x00000100ul /* GTPro */ -#define INTER_LINE_OVERLAP_DIS 0x00000200ul /* GTPro */ -#define MEM_OE_PULLBACK 0x00000400ul -#define DBL_BUFFER_EN 0x00000400ul /* GTPro */ -#define MEM_WE_FIX_DIS 0x00000800ul -#define MEM_OE_PULLBACK_B 0x00000800ul /* GT2c/VT4 */ -#define CMDFIFO_SIZE_DIS_P 0x00000800ul /* GTPro */ -#define RD_EN_FIX_DIS 0x00001000ul -#define MEM_WE_FIX_DIS_B 0x00001000ul -#define AUTO_FF_DIS 0x00001000ul /* GTPro */ -#define CMDFIFO_SIZE_DIS 0x00002000ul /* GT2c/VT4 */ -#define AUTO_BLKWRT_DIS 0x00002000ul /* GTPro */ -#define GUI_BEATS_HOST 0x00004000ul /* GT2c/VT4 */ -#define ORED_INVLD_RB_CACHE 0x00004000ul /* GTPro */ -#define BLOCK_DBL_BUF 0x00008000ul /* GTPro */ -#define R2W_TURNAROUND_DELAY 0x00020000ul /* GT2c/VT4 */ -#define ENA_32BIT_DATA_BUS 0x00040000ul /* GT2c/VT4 */ -#define HCLK_FB_SKEW_P 0x00070000ul /* GTPro */ -#define ENA_FLASH_ROM 0x00080000ul /* GT2c/VT4 */ -#define DISABLE_SWITCH_FIX 0x00080000ul /* GTPro */ -#define MCLK_START_EN 0x00080000ul /* LTPro */ -#define SEL_VBLANK_BDL_BUF 0x00100000ul /* GTPro */ -#define CMDFIFO_64EN 0x00200000ul /* GTPro */ -#define BM_FIX_DIS 0x00400000ul /* GTPro */ -#define Z_SWITCH_EN 0x00800000ul /* LTPro */ -#define FLUSH_HOST_WB 0x01000000ul /* GTPro */ -#define HW_DEBUG_WRITE_MSK_FIX_DIS 0x02000000ul /* LTPro */ -#define Z_NO_WRITE_EN 0x04000000ul /* LTPro */ -#define DISABLE_PCLK_RESET_P 0x08000000ul /* LTPro */ -#define PM_D3_SUPPORT_ENABLE_P 0x10000000ul /* LTPro */ -#define STARTCYCLE_FIX_ENABLE 0x20000000ul /* LTPro */ -#define DONT_RST_CHAREN 0x20000000ul /* XL/XC */ -#define C3_FIX_ENABLE 0x40000000ul /* LTPro */ -#define BM_HOSTRA_EN 0x40000000ul /* XL/XC */ -#define PKGBGAb 0x80000000ul /* XL/XC */ -#define AUTOEXP_HORZ_FIX 0x80000000ul /* Mobility */ +# define FAST_SRCCOPY_DIS 0x00000001ul +# define BYPASS_SUBPIC_DBF 0x00000001ul /* XL/XC */ +# define SRC_AUTONA_FIX_DIS 0x00000002ul +# define SYNC_PD_EN 0x00000002ul /* Mobility */ +# define DISP_QW_FIX_DIS 0x00000004ul +# define GUIDST_WB_EXP_DIS 0x00000008ul +# define CYC_ALL_FIX_DIS 0x00000008ul /* GTPro */ +# define AGPPLL_FIX_EN 0x00000008ul /* Mobility */ +# define SRC_AUTONA_ALWAYS_EN 0x00000010ul +# define GUI_BEATS_HOST_P 0x00000010ul /* GTPro */ +# define DRV_CNTL_DQMB_WEB 0x00000020ul +# define FAST_FILL_SCISSOR_DIS 0x00000020ul /* GT2c/VT4 */ +# define INTER_BLIT_FIX_DIS 0x00000020ul /* GTPro */ +# define DRV_CNTL_MA 0x00000040ul +# define AUTO_BLKWRT_COLOR_DIS 0x00000040ul /* GT2c/VT4 */ +# define INTER_PRIM_DIS 0x00000040ul /* GTPro */ +# define DRV_CNTL_MD 0x00000080ul +# define CHG_DEV_ID 0x00000100ul +# define SRC_TRACK_DST_FIX_DIS 0x00000200ul +# define HCLK_FB_SKEW 0x00000380ul /* GT2c/VT4 */ +# define SRC_TRACK_DST_FIX_DIS_P 0x00000080ul /* GTPro */ +# define AUTO_BLKWRT_COLOR_DIS_P 0x00000100ul /* GTPro */ +# define INTER_LINE_OVERLAP_DIS 0x00000200ul /* GTPro */ +# define MEM_OE_PULLBACK 0x00000400ul +# define DBL_BUFFER_EN 0x00000400ul /* GTPro */ +# define MEM_WE_FIX_DIS 0x00000800ul +# define MEM_OE_PULLBACK_B 0x00000800ul /* GT2c/VT4 */ +# define CMDFIFO_SIZE_DIS_P 0x00000800ul /* GTPro */ +# define RD_EN_FIX_DIS 0x00001000ul +# define MEM_WE_FIX_DIS_B 0x00001000ul +# define AUTO_FF_DIS 0x00001000ul /* GTPro */ +# define CMDFIFO_SIZE_DIS 0x00002000ul /* GT2c/VT4 */ +# define AUTO_BLKWRT_DIS 0x00002000ul /* GTPro */ +# define GUI_BEATS_HOST 0x00004000ul /* GT2c/VT4 */ +# define ORED_INVLD_RB_CACHE 0x00004000ul /* GTPro */ +# define BLOCK_DBL_BUF 0x00008000ul /* GTPro */ +# define R2W_TURNAROUND_DELAY 0x00020000ul /* GT2c/VT4 */ +# define ENA_32BIT_DATA_BUS 0x00040000ul /* GT2c/VT4 */ +# define HCLK_FB_SKEW_P 0x00070000ul /* GTPro */ +# define ENA_FLASH_ROM 0x00080000ul /* GT2c/VT4 */ +# define DISABLE_SWITCH_FIX 0x00080000ul /* GTPro */ +# define MCLK_START_EN 0x00080000ul /* LTPro */ +# define SEL_VBLANK_BDL_BUF 0x00100000ul /* GTPro */ +# define CMDFIFO_64EN 0x00200000ul /* GTPro must be set if IDCT_EN */ +# define BM_FIX_DIS 0x00400000ul /* GTPro */ +# define Z_SWITCH_EN 0x00800000ul /* LTPro */ +# define FLUSH_HOST_WB 0x01000000ul /* GTPro */ +# define HW_DEBUG_WRITE_MSK_FIX_DIS 0x02000000ul /* LTPro */ +# define Z_NO_WRITE_EN 0x04000000ul /* LTPro */ +# define DISABLE_PCLK_RESET_P 0x08000000ul /* LTPro */ +# define PM_D3_SUPPORT_ENABLE_P 0x10000000ul /* LTPro */ +# define STARTCYCLE_FIX_ENABLE 0x20000000ul /* LTPro */ +# define DONT_RST_CHAREN 0x20000000ul /* XL/XC */ +# define C3_FIX_ENABLE 0x40000000ul /* LTPro */ +# define BM_HOSTRA_EN 0x40000000ul /* XL/XC */ +# define PKGBGAb 0x80000000ul /* XL/XC */ +# define AUTOEXP_HORZ_FIX 0x80000000ul /* Mobility */ #define SCRATCH_REG0 IOPortTag(0x10u, 0x20u) #define SCRATCH_REG1 IOPortTag(0x11u, 0x21u) /* BIOS_BASE_SEGMENT 0x0000007ful */ /* As above */ @@ -804,44 +804,44 @@ This means that this sources don't support ISA and VLB cards */ #define SCRATCH_REG2 BlockIOTag(0x22u) /* LT */ #define SCRATCH_REG3 BlockIOTag(0x23u) /* GTPro */ #define CLOCK_CNTL IOPortTag(0x12u, 0x24u) -#define CLOCK_BIT 0x00000004ul /* For ICS2595 */ -#define CLOCK_PULSE 0x00000008ul /* For ICS2595 */ -#define CLOCK_SELECT 0x0000000ful -#define CLOCK_DIVIDER 0x00000030ul -#define CLOCK_STROBE 0x00000040ul -#define CLOCK_DATA 0x00000080ul +# define CLOCK_BIT 0x00000004ul /* For ICS2595 */ +# define CLOCK_PULSE 0x00000008ul /* For ICS2595 */ +# define CLOCK_SELECT 0x0000000ful +# define CLOCK_DIVIDER 0x00000030ul +# define CLOCK_STROBE 0x00000040ul +# define CLOCK_DATA 0x00000080ul /* ? 0x00000100ul */ -#define PLL_WR_EN 0x00000200ul /* For internal PLL */ -#define PLL_ADDR 0x0000fc00ul /* For internal PLL */ -#define PLL_DATA 0x00ff0000ul /* For internal PLL */ +# define PLL_WR_EN 0x00000200ul /* For internal PLL */ +# define PLL_ADDR 0x0000fc00ul /* For internal PLL */ +# define PLL_DATA 0x00ff0000ul /* For internal PLL */ /* ? 0xff000000ul */ #define CONFIG_STAT64_1 BlockIOTag(0x25u) /* GTPro */ -#define CFG_SUBSYS_DEV_ID 0x000000fful -#define CFG_SUBSYS_VEN_ID 0x00ffff00ul +# define CFG_SUBSYS_DEV_ID 0x000000fful +# define CFG_SUBSYS_VEN_ID 0x00ffff00ul /* ? 0x1f000000ul */ -#define CFG_DIMM_TYPE 0xe0000000ul -#define CFG_PCI_SUBSYS_DEV_ID 0x0000fffful /* XC/XL */ -#define CFG_PCI_SUBSYS_VEN_ID 0xffff0000ul /* XC/XL */ +# define CFG_DIMM_TYPE 0xe0000000ul +# define CFG_PCI_SUBSYS_DEV_ID 0x0000fffful /* XC/XL */ +# define CFG_PCI_SUBSYS_VEN_ID 0xffff0000ul /* XC/XL */ #define CONFIG_STAT64_2 BlockIOTag(0x26u) /* GTPro */ -#define CFG_DIMM_TYPE_3 0x00000001ul +# define CFG_DIMM_TYPE_3 0x00000001ul /* ? 0x0000001eul */ -#define CFG_ROMWRTEN 0x00000020ul -#define CFG_AGPVCOGAIN 0x000000c0ul -#define CFG_PCI_TYPE 0x00000100ul -#define CFG_AGPSKEW 0x00000e00ul -#define CFG_X1CLKSKEW 0x00007000ul -#define CFG_PANEL_ID_P 0x000f8000ul /* LTPro */ +# define CFG_ROMWRTEN 0x00000020ul +# define CFG_AGPVCOGAIN 0x000000c0ul +# define CFG_PCI_TYPE 0x00000100ul +# define CFG_AGPSKEW 0x00000e00ul +# define CFG_X1CLKSKEW 0x00007000ul +# define CFG_PANEL_ID_P 0x000f8000ul /* LTPro */ /* ? 0x00100000ul */ -#define CFG_PREFETCH_EN 0x00200000ul -#define CFG_ID_DISABLE 0x00400000ul -#define CFG_PRE_TESTEN 0x00800000ul +# define CFG_PREFETCH_EN 0x00200000ul +# define CFG_ID_DISABLE 0x00400000ul +# define CFG_PRE_TESTEN 0x00800000ul /* ? 0x01000000ul */ -#define CFG_PCI5VEN 0x02000000ul /* LTPro */ -#define CFG_VGA_DISABLE 0x04000000ul -#define CFG_ENINTB 0x08000000ul +# define CFG_PCI5VEN 0x02000000ul /* LTPro */ +# define CFG_VGA_DISABLE 0x04000000ul +# define CFG_ENINTB 0x08000000ul /* ? 0x10000000ul */ -#define CFG_ROM_REMAP_2 0x20000000ul -#define CFG_IDSEL 0x40000000ul +# define CFG_ROM_REMAP_2 0x20000000ul +# define CFG_IDSEL 0x40000000ul /* ? 0x80000000ul */ #define TV_OUT_DATA BlockIOTag(0x27u) /* LTPro */ #define BUS_CNTL IOPortTag(0x13u, 0x28u) @@ -864,346 +864,351 @@ This means that this sources don't support ISA and VLB cards */ /* Fast metal spin (A22) - Prod. 0x00000300ul */ /* All layer spin (A31) 0x00000700ul */ /* ? 0x00000800ul */ /* LTPro */ -#define BUS_CHIP_HIDDEN_REV 0x00000300ul /* XC/XL */ +# define BUS_CHIP_HIDDEN_REV 0x00000300ul /* XC/XL */ /* ? 0x00001c00ul */ /* XC/XL */ -#define BUS_ROM_DIS 0x00001000ul -#define BUS_IO_16_EN 0x00002000ul /* GX */ -#define BUS_PCI_READ_RETRY_EN 0x00002000ul /* VTB/GTB/LT */ -#define BUS_DAC_SNOOP_EN 0x00004000ul -#define BUS_PCI_RETRY_EN 0x00008000ul /* VT/GT */ -#define BUS_PCI_WRT_RETRY_EN 0x00008000ul /* VTB/GTB/LT */ -#define BUS_FIFO_WS 0x000f0000ul -#define BUS_RETRY_WS 0x000f0000ul /* VTB/GTB/LT */ -#define BUS_FIFO_ERR_INT_EN 0x00100000ul -#define BUS_MSTR_RD_MULT 0x00100000ul /* VTB/GTB/LT */ -#define BUS_FIFO_ERR_INT 0x00200000ul -#define BUS_MSTR_RD_LINE 0x00200000ul /* VTB/GTB/LT */ -#define BUS_HOST_ERR_INT_EN 0x00400000ul -#define BUS_SUSPEND 0x00400000ul /* GTPro */ -#define BUS_HOST_ERR_INT 0x00800000ul -#define BUS_LAT16X 0x00800000ul /* GTPro */ -#define BUS_PCI_DAC_WS 0x07000000ul -#define BUS_RD_DISCARD_EN 0x01000000ul /* VTB/GTB/LT */ -#define BUS_RD_ABORT_EN 0x02000000ul /* VTB/GTB/LT */ -#define BUS_MSTR_WS 0x04000000ul /* VTB/GTB/LT */ -#define BUS_PCI_DAC_DLY 0x08000000ul -#define BUS_EXT_REG_EN 0x08000000ul /* VT/GT */ -#define BUS_PCI_MEMW_WS 0x10000000ul -#define BUS_MSTR_DISCONNECT_EN 0x10000000ul /* VTB/GTB/LT */ -#define BUS_PCI_BURST_DEC 0x20000000ul /* GX/CX */ -#define BUS_BURST 0x20000000ul /* 264xT */ -#define BUS_WRT_BURST 0x20000000ul /* VTB/GTB/LT */ -#define BUS_RDY_READ_DLY 0xc0000000ul -#define BUS_READ_BURST 0x40000000ul /* VTB/GTB/LT */ -#define BUS_RDY_READ_DLY_B 0x80000000ul /* VTB/GTB/LT */ +# define BUS_ROM_DIS 0x00001000ul +# define BUS_IO_16_EN 0x00002000ul /* GX */ +# define BUS_PCI_READ_RETRY_EN 0x00002000ul /* VTB/GTB/LT */ +# define BUS_DAC_SNOOP_EN 0x00004000ul +# define BUS_PCI_RETRY_EN 0x00008000ul /* VT/GT */ +# define BUS_PCI_WRT_RETRY_EN 0x00008000ul /* VTB/GTB/LT */ +# define BUS_FIFO_WS 0x000f0000ul +# define BUS_RETRY_WS 0x000f0000ul /* VTB/GTB/LT */ +# define BUS_FIFO_ERR_INT_EN 0x00100000ul +# define BUS_MSTR_RD_MULT 0x00100000ul /* VTB/GTB/LT */ +# define BUS_FIFO_ERR_INT 0x00200000ul +# define BUS_MSTR_RD_LINE 0x00200000ul /* VTB/GTB/LT */ +# define BUS_HOST_ERR_INT_EN 0x00400000ul +# define BUS_SUSPEND 0x00400000ul /* GTPro */ +# define BUS_HOST_ERR_INT 0x00800000ul +# define BUS_LAT16X 0x00800000ul /* GTPro */ +# define BUS_PCI_DAC_WS 0x07000000ul +# define BUS_RD_DISCARD_EN 0x01000000ul /* VTB/GTB/LT */ +# define BUS_RD_ABORT_EN 0x02000000ul /* VTB/GTB/LT */ +# define BUS_MSTR_WS 0x04000000ul /* VTB/GTB/LT */ +# define BUS_PCI_DAC_DLY 0x08000000ul +# define BUS_EXT_REG_EN 0x08000000ul /* VT/GT */ +# define BUS_PCI_MEMW_WS 0x10000000ul +# define BUS_MSTR_DISCONNECT_EN 0x10000000ul /* VTB/GTB/LT */ +# define BUS_PCI_BURST_DEC 0x20000000ul /* GX/CX */ +# define BUS_BURST 0x20000000ul /* 264xT */ +# define BUS_WRT_BURST 0x20000000ul /* VTB/GTB/LT */ +# define BUS_RDY_READ_DLY 0xc0000000ul +# define BUS_READ_BURST 0x40000000ul /* VTB/GTB/LT */ +# define BUS_RDY_READ_DLY_B 0x80000000ul /* VTB/GTB/LT */ #define LCD_INDEX BlockIOTag(0x29u) /* LTPro */ -#define LCD_REG_INDEX 0x0000003ful -/* ? 0x000000c0ul */ -#define LCD_DISPLAY_DIS 0x00000100ul -#define LCD_SRC_SEL 0x00000200ul -#define LCD_SRC_SEL_CRTC1 0x00000000ul -#define LCD_SRC_SEL_CRTC2 0x00000200ul -#define LCD_CRTC2_DISPLAY_DIS 0x00000400ul -#define LCD_GUI_ACTIVE 0x00000800ul /* XC/XL */ -/* ? 0x00fff000ul */ -#define LCD_MONDET_SENSE 0x01000000ul /* XC/XL */ -#define LCD_MONDET_INT_POL 0x02000000ul /* XC/XL */ -#define LCD_MONDET_INT_EN 0x04000000ul /* XC/XL */ -#define LCD_MONDET_INT 0x08000000ul /* XC/XL */ -#define LCD_MONDET_EN 0x10000000ul /* XC/XL */ -#define LCD_EN_PL 0x20000000ul /* XC/XL */ -/* ? 0xc0000000ul */ +# define LCD_REG_INDEX 0x0000003ful +# define LCD_DISPLAY_DIS 0x00000100ul +# define LCD_SRC_SEL 0x00000200ul +# define LCD_SRC_SEL_CRTC1 0x00000000ul +# define LCD_SRC_SEL_CRTC2 0x00000200ul +# define LCD_CRTC2_DISPLAY_DIS 0x00000400ul +# define LCD_GUI_ACTIVE 0x00000800ul /* XC/XL */ +# define LCD_MONDET_SENSE 0x01000000ul /* XC/XL */ +# define LCD_MONDET_INT_POL 0x02000000ul /* XC/XL */ +# define LCD_MONDET_INT_EN 0x04000000ul /* XC/XL */ +# define LCD_MONDET_INT 0x08000000ul /* XC/XL */ +# define LCD_MONDET_EN 0x10000000ul /* XC/XL */ +# define LCD_EN_PL 0x20000000ul /* XC/XL */ #define HFB_PITCH_ADDR BlockIOTag(0x2au) /* LT */ #define LCD_DATA BlockIOTag(0x2au) /* LTPro */ #define EXT_MEM_CNTL BlockIOTag(0x2bu) /* VTB/GTB/LT */ #define MEM_CNTL IOPortTag(0x14u, 0x2cu) -#define CTL_MEM_SIZE 0x00000007ul +# define CTL_MEM_SIZE 0x00000007ul /* ? 0x00000008ul */ -#define CTL_MEM_REFRESH 0x00000078ul /* VT/GT */ -#define CTL_MEM_SIZEB 0x0000000ful /* VTB/GTB/LT */ -#define CTL_MEM_RD_LATCH_EN 0x00000010ul -#define CTL_MEM_RD_LATCH_DLY 0x00000020ul -#define CTL_MEM_LATENCY 0x00000030ul /* VTB/GTB/LT */ -#define CTL_MEM_SD_LATCH_EN 0x00000040ul -#define CTL_MEM_SD_LATCH_DLY 0x00000080ul -#define CTL_MEM_LATCH 0x000000c0ul /* VTB/GTB/LT */ -#define CTL_MEM_WDOE_CNTL 0x000000c0ul /* XC/XL */ -#define CTL_MEM_FULL_PLS 0x00000100ul -#define CTL_MEM_CYC_LNTH_AUX 0x00000180ul /* VT/GT */ -#define CTL_MEM_TRP 0x00000300ul /* VTB/GTB/LT */ -#define CTL_MEM_CYC_LNTH 0x00000600ul -#define CTL_MEM_REFRESH_RATE 0x00001800ul /* 264xT */ -#define CTL_MEM_TRCD 0x00000c00ul /* VTB/GTB/LT */ -#define CTL_MEM_WR_RDY_SEL 0x00000800ul /* GX/CX */ -#define CTL_MEM_EXT_RMW_CYC_EN 0x00001000ul /* GX/CX */ -#define CTL_MEM_TCRD 0x00001000ul /* VTB/GTB/LT */ -#define CTL_MEM_DLL_RESET 0x00002000ul /* VT/GT */ -#define CTL_MEM_TR2W 0x00002000ul /* GTPro */ -#define CTL_MEM_ACTV_PRE 0x0000c000ul /* VT/GT */ -#define CTL_MEM_CAS_PHASE 0x00004000ul /* GTPro */ -#define CTL_MEM_OE_PULLBACK 0x00008000ul /* GTPro */ -#define CTL_MEM_TWR 0x0000c000ul /* XC/XL */ -#define CTL_MEM_BNDRY 0x00030000ul -#define CTL_MEM_BNDRY_0K 0x00000000ul -#define CTL_MEM_BNDRY_256K 0x00010000ul -#define CTL_MEM_BNDRY_512K 0x00020000ul -#define CTL_MEM_BNDRY_1024K 0x00030000ul -#define CTL_MEM_DLL_GAIN_CNTL 0x00030000ul /* VT/GT */ -#define CTL_MEM_BNDRY_EN 0x00040000ul -#define CTL_MEM_SDRAM_RESET 0x00040000ul /* VT/GT */ -#define CTL_MEM_TRAS 0x00070000ul /* VTB/GTB/LT */ -#define CTL_MEM_TILE_SELECT 0x00180000ul /* VT/GT */ -#define CTL_MEM_REFRESH_DIS 0x00080000ul /* VTB/GTB/LT */ -#define CTL_MEM_LOW_LATENCY_MODE 0x00200000ul /* VT/GT */ -#define CTL_MEM_CDE_PULLBACK 0x00400000ul /* VT/GT */ -#define CTL_MEM_REFRESH_RATE_B 0x00f00000ul /* VTB/GTB/LT */ -#define CTL_MEM_PIX_WIDTH 0x07000000ul -#define CTL_MEM_LOWER_APER_ENDIAN 0x03000000ul /* VTB/GTB/LT */ -#define CTL_MEM_OE_SELECT 0x18000000ul /* VT/GT */ -#define CTL_MEM_UPPER_APER_ENDIAN 0x0c000000ul /* VTB/GTB/LT */ +# define CTL_MEM_REFRESH 0x00000078ul /* VT/GT */ +# define CTL_MEM_SIZEB 0x0000000ful /* VTB/GTB/LT */ +# define CTL_MEM_RD_LATCH_EN 0x00000010ul +# define CTL_MEM_RD_LATCH_DLY 0x00000020ul +# define CTL_MEM_LATENCY 0x00000030ul /* VTB/GTB/LT */ +# define CTL_MEM_SD_LATCH_EN 0x00000040ul +# define CTL_MEM_SD_LATCH_DLY 0x00000080ul +# define CTL_MEM_LATCH 0x000000c0ul /* VTB/GTB/LT */ +# define CTL_MEM_WDOE_CNTL 0x000000c0ul /* XC/XL */ +# define CTL_MEM_FULL_PLS 0x00000100ul +# define CTL_MEM_CYC_LNTH_AUX 0x00000180ul /* VT/GT */ +# define CTL_MEM_TRP 0x00000300ul /* VTB/GTB/LT */ +# define CTL_MEM_CYC_LNTH 0x00000600ul +# define CTL_MEM_REFRESH_RATE 0x00001800ul /* 264xT */ +# define CTL_MEM_TRCD 0x00000c00ul /* VTB/GTB/LT */ +# define CTL_MEM_WR_RDY_SEL 0x00000800ul /* GX/CX */ +# define CTL_MEM_EXT_RMW_CYC_EN 0x00001000ul /* GX/CX */ +# define CTL_MEM_TCRD 0x00001000ul /* VTB/GTB/LT */ +# define CTL_MEM_DLL_RESET 0x00002000ul /* VT/GT */ +# define CTL_MEM_TR2W 0x00002000ul /* GTPro */ +# define CTL_MEM_ACTV_PRE 0x0000c000ul /* VT/GT */ +# define CTL_MEM_CAS_PHASE 0x00004000ul /* GTPro */ +# define CTL_MEM_OE_PULLBACK 0x00008000ul /* GTPro */ +# define CTL_MEM_TWR 0x0000c000ul /* XC/XL */ +# define CTL_MEM_BNDRY 0x00030000ul +# define CTL_MEM_BNDRY_0K 0x00000000ul +# define CTL_MEM_BNDRY_256K 0x00010000ul +# define CTL_MEM_BNDRY_512K 0x00020000ul +# define CTL_MEM_BNDRY_1024K 0x00030000ul +# define CTL_MEM_DLL_GAIN_CNTL 0x00030000ul /* VT/GT */ +# define CTL_MEM_BNDRY_EN 0x00040000ul +# define CTL_MEM_SDRAM_RESET 0x00040000ul /* VT/GT */ +# define CTL_MEM_TRAS 0x00070000ul /* VTB/GTB/LT */ +# define CTL_MEM_TILE_SELECT 0x00180000ul /* VT/GT */ +# define CTL_MEM_REFRESH_DIS 0x00080000ul /* VTB/GTB/LT */ +# define CTL_MEM_LOW_LATENCY_MODE 0x00200000ul /* VT/GT */ +# define CTL_MEM_CDE_PULLBACK 0x00400000ul /* VT/GT */ +# define CTL_MEM_REFRESH_RATE_B 0x00f00000ul /* VTB/GTB/LT */ +# define CTL_MEM_PIX_WIDTH 0x07000000ul +# define CTL_MEM_LOWER_APER_ENDIAN 0x03000000ul /* VTB/GTB/LT */ +# define CTL_MEM_OE_SELECT 0x18000000ul /* VT/GT */ +# define CTL_MEM_UPPER_APER_ENDIAN 0x0c000000ul /* VTB/GTB/LT */ /* ? 0xe0000000ul */ -#define CTL_MEM_PAGE_SIZE 0x30000000ul /* VTB/GTB/LT */ +# define CTL_MEM_PAGE_SIZE 0x30000000ul /* VTB/GTB/LT */ #define MEM_VGA_WP_SEL IOPortTag(0x15u, 0x2du) -#define MEM_VGA_WPS0 0x0000fffful -#define MEM_VGA_WPS1 0xffff0000ul +# define MEM_VGA_WPS0 0x0000fffful +# define MEM_VGA_WPS1 0xffff0000ul #define MEM_VGA_RP_SEL IOPortTag(0x16u, 0x2eu) -#define MEM_VGA_RPS0 0x0000fffful -#define MEM_VGA_RPS1 0xffff0000ul +# define MEM_VGA_RPS0 0x0000fffful +# define MEM_VGA_RPS1 0xffff0000ul #define LT_GIO BlockIOTag(0x2fu) /* LT */ #define I2C_CNTL_1 BlockIOTag(0x2fu) /* GTPro */ #define DAC_REGS IOPortTag(0x17u, 0x30u) /* 4 separate bytes */ -#define M64_DAC_WRITE (DAC_REGS + 0) -#define M64_DAC_DATA (DAC_REGS + 1) -#define M64_DAC_MASK (DAC_REGS + 2) -#define M64_DAC_READ (DAC_REGS + 3) +# define M64_DAC_WRITE (DAC_REGS + 0) +# define M64_DAC_DATA (DAC_REGS + 1) +# define M64_DAC_MASK (DAC_REGS + 2) +# define M64_DAC_READ (DAC_REGS + 3) #define DAC_CNTL IOPortTag(0x18u, 0x31u) -#define DAC_EXT_SEL 0x00000003ul -#define DAC_EXT_SEL_RS2 0x000000001ul -#define DAC_EXT_SEL_RS3 0x000000002ul -#define DAC_RANGE_CTL 0x00000003ul /* VTB/GTB/LT */ -#define DAC_BLANKING 0x00000004ul /* 264xT */ -#define DAC_CMP_DIS 0x00000008ul /* 264xT */ -#define DAC1_CLK_SEL 0x00000010ul /* LTPro */ -#define DAC_PALETTE_ACCESS_CNTL 0x00000020ul /* LTPro */ -#define DAC_PALETTE2_SNOOP_EN 0x00000040ul /* LTPro */ -#define DAC_CMP_OUTPUT 0x00000080ul /* 264xT */ -#define DAC_8BIT_EN 0x00000100ul -#define DAC_PIX_DLY 0x00000600ul -#define DAC_DIRECT 0x00000400ul /* VTB/GTB/LT */ -#define DAC_BLANK_ADJ 0x00001800ul -#define DAC_PAL_CLK_SEL 0x00000800ul /* VTB/GTB/LT */ -#define DAC_CRT_SENSE 0x00000800ul /* XC/XL */ -#define DAC_CRT_DETECTION_ON 0x00001000ul /* XC/XL */ -#define DAC_VGA_ADR_EN 0x00002000ul -#define DAC_FEA_CON_EN 0x00004000ul /* 264xT */ -#define DAC_PDMN 0x00008000ul /* 264xT */ -#define DAC_TYPE 0x00070000ul +# define DAC_EXT_SEL 0x00000003ul +# define DAC_EXT_SEL_RS2 0x00000001ul +# define DAC_EXT_SEL_RS3 0x00000002ul +# define DAC_RANGE_CTL 0x00000003ul /* VTB/GTB/LT */ +# define DAC_BLANKING 0x00000004ul /* 264xT */ +# define DAC_CMP_DIS 0x00000008ul /* 264xT */ +# define DAC1_CLK_SEL 0x00000010ul /* LTPro */ +# define DAC_PALETTE_ACCESS_CNTL 0x00000020ul /* LTPro */ +# define DAC_PALETTE2_SNOOP_EN 0x00000040ul /* LTPro */ +# define DAC_CMP_OUTPUT 0x00000080ul /* 264xT */ +# define DAC_8BIT_EN 0x00000100ul +# define DAC_PIX_DLY 0x00000600ul +# define DAC_DIRECT 0x00000400ul /* VTB/GTB/LT */ +# define DAC_BLANK_ADJ 0x00001800ul +# define DAC_PAL_CLK_SEL 0x00000800ul /* VTB/GTB/LT */ +# define DAC_CRT_SENSE 0x00000800ul /* XC/XL */ +# define DAC_CRT_DETECTION_ON 0x00001000ul /* XC/XL */ +# define DAC_VGA_ADR_EN 0x00002000ul +# define DAC_FEA_CON_EN 0x00004000ul /* 264xT */ +# define DAC_PDMN 0x00008000ul /* 264xT */ +# define DAC_TYPE 0x00070000ul /* ? 0x00f80000ul */ -#define DAC_MON_ID_STATE0 0x01000000ul /* GX-E+/CX */ -#define DAC_GIO_STATE_1 0x01000000ul /* 264xT */ -#define DAC_MON_ID_STATE1 0x02000000ul /* GX-E+/CX */ -#define DAC_GIO_STATE_0 0x02000000ul /* 264xT */ -#define DAC_MON_ID_STATE2 0x04000000ul /* GX-E+/CX */ -#define DAC_GIO_STATE_4 0x04000000ul /* 264xT */ -#define DAC_MON_ID_DIR0 0x08000000ul /* GX-E+/CX */ -#define DAC_GIO_DIR_1 0x08000000ul /* 264xT */ -#define DAC_MON_ID_DIR1 0x10000000ul /* GX-E+/CX */ -#define DAC_GIO_DIR_0 0x10000000ul /* 264xT */ -#define DAC_MON_ID_DIR2 0x20000000ul /* GX-E+/CX */ -#define DAC_GIO_DIR_4 0x20000000ul /* 264xT */ -#define DAC_MAN_CMP_STATE 0x40000000ul /* GX-E+ */ -#define DAC_RW_WS 0x80000000ul /* VT/GT */ +# define DAC_MON_ID_STATE0 0x01000000ul /* GX-E+/CX */ +# define DAC_GIO_STATE_1 0x01000000ul /* 264xT */ +# define DAC_MON_ID_STATE1 0x02000000ul /* GX-E+/CX */ +# define DAC_GIO_STATE_0 0x02000000ul /* 264xT */ +# define DAC_MON_ID_STATE2 0x04000000ul /* GX-E+/CX */ +# define DAC_GIO_STATE_4 0x04000000ul /* 264xT */ +# define DAC_MON_ID_DIR0 0x08000000ul /* GX-E+/CX */ +# define DAC_GIO_DIR_1 0x08000000ul /* 264xT */ +# define DAC_MON_ID_DIR1 0x10000000ul /* GX-E+/CX */ +# define DAC_GIO_DIR_0 0x10000000ul /* 264xT */ +# define DAC_MON_ID_DIR2 0x20000000ul /* GX-E+/CX */ +# define DAC_GIO_DIR_4 0x20000000ul /* 264xT */ +# define DAC_MAN_CMP_STATE 0x40000000ul /* GX-E+ */ +# define DAC_RW_WS 0x80000000ul /* VT/GT */ #define HORZ_STRETCHING BlockIOTag(0x32u) /* LT */ -#define HORZ_STRETCH_BLEND 0x00000ffful -#define HORZ_STRETCH_RATIO 0x0000fffful -#define HORZ_STRETCH_LOOP 0x00070000ul -#define HORZ_STRETCH_LOOP09 0x00000000ul -#define HORZ_STRETCH_LOOP11 0x00010000ul -#define HORZ_STRETCH_LOOP12 0x00020000ul -#define HORZ_STRETCH_LOOP14 0x00030000ul -#define HORZ_STRETCH_LOOP15 0x00040000ul -/* ? 0x00050000ul */ -/* ? 0x00060000ul */ -/* ? 0x00070000ul */ +# define HORZ_STRETCH_BLEND 0x00000ffful +# define HORZ_STRETCH_RATIO 0x0000fffful +# define HORZ_STRETCH_LOOP 0x00070000ul +# define HORZ_STRETCH_LOOP09 0x00000000ul +# define HORZ_STRETCH_LOOP11 0x00010000ul +# define HORZ_STRETCH_LOOP12 0x00020000ul +# define HORZ_STRETCH_LOOP14 0x00030000ul +# define HORZ_STRETCH_LOOP15 0x00040000ul +/* ? 0x00050000ul */ +/* ? 0x00060000ul */ +/* ? 0x00070000ul */ /* ? 0x00080000ul */ -#define HORZ_PANEL_SIZE 0x0ff00000ul /* XC/XL */ +# define HORZ_PANEL_SIZE 0x0ff00000ul /* XC/XL */ /* ? 0x10000000ul */ -#define AUTO_HORZ_RATIO 0x20000000ul /* XC/XL */ -#define HORZ_STRETCH_MODE 0x40000000ul -#define HORZ_STRETCH_EN 0x80000000ul +# define AUTO_HORZ_RATIO 0x20000000ul /* XC/XL */ +# define HORZ_STRETCH_MODE 0x40000000ul +# define HORZ_STRETCH_EN 0x80000000ul #define EXT_DAC_REGS BlockIOTag(0x32u) /* GTPro */ #define VERT_STRETCHING BlockIOTag(0x33u) /* LT */ -#define VERT_STRETCH_RATIO0 0x000003fful -#define VERT_STRETCH_RATIO1 0x000ffc00ul -#define VERT_STRETCH_RATIO2 0x3ff00000ul -#define VERT_STRETCH_USE0 0x40000000ul -#define VERT_STRETCH_EN 0x80000000ul +# define VERT_STRETCH_RATIO0 0x000003fful +# define VERT_STRETCH_RATIO1 0x000ffc00ul +# define VERT_STRETCH_RATIO2 0x3ff00000ul +# define VERT_STRETCH_USE0 0x40000000ul +# define VERT_STRETCH_EN 0x80000000ul #define GEN_TEST_CNTL IOPortTag(0x19u, 0x34u) -#define GEN_EE_DATA_OUT 0x00000001ul /* GX/CX */ -#define GEN_GIO2_DATA_OUT 0x00000001ul /* 264xT */ -#define GEN_EE_CLOCK 0x00000002ul /* GX/CX */ +# define GEN_EE_DATA_OUT 0x00000001ul /* GX/CX */ +# define GEN_GIO2_DATA_OUT 0x00000001ul /* 264xT */ +# define GEN_EE_CLOCK 0x00000002ul /* GX/CX */ /* ? 0x00000002ul */ /* 264xT */ -#define GEN_EE_CHIP_SEL 0x00000004ul /* GX/CX */ -#define GEN_GIO3_DATA_OUT 0x00000004ul /* 264xT */ -#define GEN_EE_DATA_IN 0x00000008ul /* GX/CX */ -#define GEN_GIO2_DATA_IN 0x00000008ul /* 264xT */ -#define GEN_EE_EN 0x00000010ul /* GX/CX */ -#define GEN_GIO2_ENABLE 0x00000010ul /* 264xT */ -#define GEN_ICON2_ENABLE 0x00000010ul /* XC/XL */ -#define GEN_OVR_OUTPUT_EN 0x00000020ul /* GX/CX */ -#define GEN_GIO2_WRITE 0x00000020ul /* 264xT */ -#define GEN_CUR2_ENABLE 0x00000020ul /* XC/XL */ -#define GEN_OVR_POLARITY 0x00000040ul /* GX/CX */ -#define GEN_ICON_ENABLE 0x00000040ul /* XC/XL */ -#define GEN_CUR_EN 0x00000080ul -#define GEN_GUI_EN 0x00000100ul /* GX/CX */ -#define GEN_GUI_RESETB 0x00000100ul /* 264xT */ -#define GEN_BLOCK_WR_EN 0x00000200ul /* GX */ +# define GEN_EE_CHIP_SEL 0x00000004ul /* GX/CX */ +# define GEN_GIO3_DATA_OUT 0x00000004ul /* 264xT */ +# define GEN_EE_DATA_IN 0x00000008ul /* GX/CX */ +# define GEN_GIO2_DATA_IN 0x00000008ul /* 264xT */ +# define GEN_EE_EN 0x00000010ul /* GX/CX */ +# define GEN_GIO2_ENABLE 0x00000010ul /* 264xT */ +# define GEN_ICON2_ENABLE 0x00000010ul /* XC/XL */ +# define GEN_OVR_OUTPUT_EN 0x00000020ul /* GX/CX */ +# define GEN_GIO2_WRITE 0x00000020ul /* 264xT */ +# define GEN_CUR2_ENABLE 0x00000020ul /* XC/XL */ +# define GEN_OVR_POLARITY 0x00000040ul /* GX/CX */ +# define GEN_ICON_ENABLE 0x00000040ul /* XC/XL */ +# define GEN_CUR_EN 0x00000080ul +# define GEN_GUI_EN 0x00000100ul /* GX/CX */ +# define GEN_GUI_RESETB 0x00000100ul /* 264xT */ +# define GEN_BLOCK_WR_EN 0x00000200ul /* GX */ /* ? 0x00000200ul */ /* CX/264xT */ -#define GEN_SOFT_RESET 0x00000200ul /* VTB/GTB/LT */ -#define GEN_MEM_TRISTATE 0x00000400ul /* GTPro */ +# define GEN_SOFT_RESET 0x00000200ul /* VTB/GTB/LT */ +# define GEN_MEM_TRISTATE 0x00000400ul /* GTPro */ /* ? 0x00000800ul */ -#define GEN_TEST_VECT_MODE 0x00003000ul /* VT/GT */ +# define GEN_TEST_VECT_MODE 0x00003000ul /* VT/GT */ /* ? 0x0000c000ul */ -#define GEN_TEST_FIFO_EN 0x00010000ul /* GX/CX */ -#define GEN_TEST_GUI_REGS_EN 0x00020000ul /* GX/CX */ -#define GEN_TEST_VECT_EN 0x00040000ul /* GX/CX */ -#define GEN_TEST_CRC_STR 0x00080000ul /* GX-C/-D */ +# define GEN_TEST_FIFO_EN 0x00010000ul /* GX/CX */ +# define GEN_TEST_GUI_REGS_EN 0x00020000ul /* GX/CX */ +# define GEN_TEST_VECT_EN 0x00040000ul /* GX/CX */ +# define GEN_TEST_CRC_STR 0x00080000ul /* GX-C/-D */ /* ? 0x00080000ul */ /* GX-E+/CX */ -#define GEN_TEST_MODE_T 0x000f0000ul /* 264xT */ -#define GEN_TEST_MODE 0x00700000ul /* GX/CX */ -#define GEN_TEST_CNT_EN 0x00100000ul /* 264xT */ -#define GEN_TEST_CRC_EN 0x00200000ul /* 264xT */ +# define GEN_TEST_MODE_T 0x000f0000ul /* 264xT */ +# define GEN_TEST_MODE 0x00700000ul /* GX/CX */ +# define GEN_TEST_CNT_EN 0x00100000ul /* 264xT */ +# define GEN_TEST_CRC_EN 0x00200000ul /* 264xT */ /* ? 0x00400000ul */ /* 264xT */ /* ? 0x00800000ul */ -#define GEN_TEST_MEM_WR 0x01000000ul /* GX-C/-D */ -#define GEN_TEST_MEM_STROBE 0x02000000ul /* GX-C/-D */ -#define GEN_TEST_DST_SS_EN 0x04000000ul /* GX/CX */ -#define GEN_TEST_DST_SS_STROBE 0x08000000ul /* GX/CX */ -#define GEN_TEST_SRC_SS_EN 0x10000000ul /* GX/CX */ -#define GEN_TEST_SRC_SS_STROBE 0x20000000ul /* GX/CX */ -#define GEN_TEST_CNT_VALUE 0x3f000000ul /* 264xT */ -#define GEN_TEST_CC_EN 0x40000000ul /* GX/CX */ -#define GEN_TEST_CC_STROBE 0x80000000ul /* GX/CX */ +# define GEN_TEST_MEM_WR 0x01000000ul /* GX-C/-D */ +# define GEN_TEST_MEM_STROBE 0x02000000ul /* GX-C/-D */ +# define GEN_TEST_DST_SS_EN 0x04000000ul /* GX/CX */ +# define GEN_TEST_DST_SS_STROBE 0x08000000ul /* GX/CX */ +# define GEN_TEST_SRC_SS_EN 0x10000000ul /* GX/CX */ +# define GEN_TEST_SRC_SS_STROBE 0x20000000ul /* GX/CX */ +# define GEN_TEST_CNT_VALUE 0x3f000000ul /* 264xT */ +# define GEN_TEST_CC_EN 0x40000000ul /* GX/CX */ +# define GEN_TEST_CC_STROBE 0x80000000ul /* GX/CX */ /* ? 0xc0000000ul */ /* 264xT */ -#define GEN_DEBUG_MODE 0xff000000ul /* VTB/GTB/LT */ +# define GEN_DEBUG_MODE 0xff000000ul /* VTB/GTB/LT */ +# define GEN_DEBUG_MC_PARSER 0x2A000000ul /* Mobility pro */ +# define GEN_DEBUG_IDCT_PARSER 0x2B000000ul /* Mobility pro */ +# define GEN_DEBUG_MC_BUFFER 0x2C000000ul /* Mobility pro */ +# define GEN_DEBUG_IDCT_BUFFER 0x2E000000ul /* Mobility pro */ +# define GEN_DEBUG_IDCT1 0x90000000ul /* Mobility pro */ +# define GEN_DEBUG_IDCT2 0x91000000ul /* Mobility pro */ +# define GEN_DEBUG_IDCT3 0x92000000ul /* Mobility pro */ #define LCD_GEN_CTRL BlockIOTag(0x35u) /* LT */ -#define CRT_ON 0x00000001ul -#define LCD_ON 0x00000002ul -#define HORZ_DIVBY2_EN 0x00000004ul -#define DONT_DS_ICON 0x00000008ul -#define LOCK_8DOT 0x00000010ul -#define ICON_ENABLE 0x00000020ul -#define DONT_SHADOW_VPAR 0x00000040ul -#define V2CLK_PM_EN 0x00000080ul -#define RST_FM 0x00000100ul -#define DISABLE_PCLK_RESET 0x00000200ul /* XC/XL */ -#define DIS_HOR_CRT_DIVBY2 0x00000400ul -#define SCLK_SEL 0x00000800ul -#define SCLK_DELAY 0x0000f000ul -#define TVCLK_PM_EN 0x00010000ul -#define VCLK_DAC_PM_EN 0x00020000ul -#define VCLK_LCD_OFF 0x00040000ul -#define SELECT_WAIT_4MS 0x00080000ul -#define XTALIN_PM_EN 0x00080000ul /* XC/XL */ -#define V2CLK_DAC_PM_EN 0x00100000ul -#define LVDS_EN 0x00200000ul -#define LVDS_PLL_EN 0x00400000ul -#define LVDS_PLL_RESET 0x00800000ul -#define LVDS_RESERVED_BITS 0x07000000ul -#define CRTC_RW_SELECT 0x08000000ul /* LTPro */ -#define USE_SHADOWED_VEND 0x10000000ul -#define USE_SHADOWED_ROWCUR 0x20000000ul -#define SHADOW_EN 0x40000000ul -#define SHADOW_RW_EN 0x80000000ul +# define CRT_ON 0x00000001ul +# define LCD_ON 0x00000002ul +# define HORZ_DIVBY2_EN 0x00000004ul +# define DONT_DS_ICON 0x00000008ul +# define LOCK_8DOT 0x00000010ul +# define ICON_ENABLE 0x00000020ul +# define DONT_SHADOW_VPAR 0x00000040ul +# define V2CLK_PM_EN 0x00000080ul +# define RST_FM 0x00000100ul +# define DISABLE_PCLK_RESET 0x00000200ul /* XC/XL */ +# define DIS_HOR_CRT_DIVBY2 0x00000400ul +# define SCLK_SEL 0x00000800ul +# define SCLK_DELAY 0x0000f000ul +# define TVCLK_PM_EN 0x00010000ul +# define VCLK_DAC_PM_EN 0x00020000ul +# define VCLK_LCD_OFF 0x00040000ul +# define SELECT_WAIT_4MS 0x00080000ul +# define XTALIN_PM_EN 0x00080000ul /* XC/XL */ +# define V2CLK_DAC_PM_EN 0x00100000ul +# define LVDS_EN 0x00200000ul +# define LVDS_PLL_EN 0x00400000ul +# define LVDS_PLL_RESET 0x00800000ul +# define LVDS_RESERVED_BITS 0x07000000ul +# define CRTC_RW_SELECT 0x08000000ul /* LTPro */ +# define USE_SHADOWED_VEND 0x10000000ul +# define USE_SHADOWED_ROWCUR 0x20000000ul +# define SHADOW_EN 0x40000000ul +# define SHADOW_RW_EN 0x80000000ul #define CUSTOM_MACRO_CNTL BlockIOTag(0x35u) /* GTPro */ +# define IDCT_FIFO_EXTENSE 0x00000001ul #define POWER_MANAGEMENT BlockIOTag(0x36u) /* LT */ -#define PWR_MGT_ON 0x00000001ul -#define PWR_MGT_MODE 0x00000006ul -#define AUTO_PWRUP_EN 0x00000008ul -#define ACTIVITY_PIN_ON 0x00000010ul -#define STANDBY_POL 0x00000020ul -#define SUSPEND_POL 0x00000040ul -#define SELF_REFRESH 0x00000080ul -#define ACTIVITY_PIN_EN 0x00000100ul -#define KEYBD_SNOOP 0x00000200ul -#define USE_F32KHZ 0x00000400ul /* LTPro */ -#define DONT_USE_XTALIN 0x00000400ul /* XC/XL */ -#define TRISTATE_MEM_EN 0x00000800ul /* LTPro */ -#define LCDENG_TEST_MODE 0x0000f000ul -#define STANDBY_COUNT 0x000f0000ul -#define SUSPEND_COUNT 0x00f00000ul -#define BAISON 0x01000000ul -#define BLON 0x02000000ul -#define DIGON 0x04000000ul -#define PM_D3_SUPPORT_ENABLE 0x08000000ul /* XC/XL */ -#define STANDBY_NOW 0x10000000ul -#define SUSPEND_NOW 0x20000000ul -#define PWR_MGT_STATUS 0xc0000000ul +# define PWR_MGT_ON 0x00000001ul +# define PWR_MGT_MODE 0x00000006ul +# define AUTO_PWRUP_EN 0x00000008ul +# define ACTIVITY_PIN_ON 0x00000010ul +# define STANDBY_POL 0x00000020ul +# define SUSPEND_POL 0x00000040ul +# define SELF_REFRESH 0x00000080ul +# define ACTIVITY_PIN_EN 0x00000100ul +# define KEYBD_SNOOP 0x00000200ul +# define USE_F32KHZ 0x00000400ul /* LTPro */ +# define DONT_USE_XTALIN 0x00000400ul /* XC/XL */ +# define TRISTATE_MEM_EN 0x00000800ul /* LTPro */ +# define LCDENG_TEST_MODE 0x0000f000ul +# define STANDBY_COUNT 0x000f0000ul +# define SUSPEND_COUNT 0x00f00000ul +# define BAISON 0x01000000ul +# define BLON 0x02000000ul +# define DIGON 0x04000000ul +# define PM_D3_SUPPORT_ENABLE 0x08000000ul /* XC/XL */ +# define STANDBY_NOW 0x10000000ul +# define SUSPEND_NOW 0x20000000ul +# define PWR_MGT_STATUS 0xc0000000ul #define CONFIG_CNTL IOPortTag(0x1au, 0x37u) -#define CFG_MEM_AP_SIZE 0x00000003ul -#define CFG_MEM_VGA_AP_EN 0x00000004ul +# define CFG_MEM_AP_SIZE 0x00000003ul +# define CFG_MEM_VGA_AP_EN 0x00000004ul /* ? 0x00000008ul */ -#define CFG_MEM_AP_LOC 0x00003ff0ul +# define CFG_MEM_AP_LOC 0x00003ff0ul /* ? 0x0000c000ul */ -#define CFG_CARD_ID 0x00070000ul -#define CFG_VGA_DIS 0x00080000ul +# define CFG_CARD_ID 0x00070000ul +# define CFG_VGA_DIS 0x00080000ul /* ? 0x00f00000ul */ -#define CFG_CDE_WINDOW 0x3f000000ul /* VT/GT */ +# define CFG_CDE_WINDOW 0x3f000000ul /* VT/GT */ /* ? 0xc0000000ul */ #define CONFIG_CHIP_ID IOPortTag(0x1bu, 0x38u) /* Read */ -#define CFG_CHIP_TYPE0 0x000000fful -#define CFG_CHIP_TYPE1 0x0000ff00ul -#define CFG_CHIP_TYPE 0x0000fffful -#define CFG_CHIP_CLASS 0x00ff0000ul -#define CFG_CHIP_REV 0xff000000ul -#define CFG_CHIP_VERSION 0x07000000ul /* 264xT */ -#define CFG_CHIP_FOUNDRY 0x38000000ul /* 264xT */ -#define CFG_CHIP_REVISION 0xc0000000ul /* 264xT */ +# define CFG_CHIP_TYPE0 0x000000fful +# define CFG_CHIP_TYPE1 0x0000ff00ul +# define CFG_CHIP_TYPE 0x0000fffful +# define CFG_CHIP_CLASS 0x00ff0000ul +# define CFG_CHIP_REV 0xff000000ul +# define CFG_CHIP_VERSION 0x07000000ul /* 264xT */ +# define CFG_CHIP_FOUNDRY 0x38000000ul /* 264xT */ +# define CFG_CHIP_REVISION 0xc0000000ul /* 264xT */ #define CONFIG_STATUS64_0 IOPortTag(0x1cu, 0x39u) /* Read (R/W (264xT)) */ -#define CFG_BUS_TYPE 0x00000007ul /* GX/CX */ -#define CFG_MEM_TYPE_T 0x00000007ul /* 264xT */ -#define CFG_MEM_TYPE 0x00000038ul /* GX/CX */ -#define CFG_DUAL_CAS_EN_T 0x00000008ul /* 264xT */ -#define CFG_ROM_128K_EN 0x00000008ul /* VTB/GTB/LT */ -#define CFG_ROM_REMAP 0x00000008ul /* GTPro */ -#define CFG_VGA_EN_T 0x00000010ul /* VT/GT */ -#define CFG_CLOCK_EN 0x00000020ul /* 264xT */ -#define CFG_DUAL_CAS_EN 0x00000040ul /* GX/CX */ -#define CFG_VMC_SENSE 0x00000040ul /* VT/GT */ -#define CFG_SHARED_MEM_EN 0x00000040ul /* VTB/GTB/LT */ -#define CFG_LOCAL_BUS_OPTION 0x00000180ul /* GX/CX */ -#define CFG_VFC_SENSE 0x00000080ul /* VT/GT */ -#define CFG_INIT_DAC_TYPE 0x00000e00ul /* GX/CX */ -#define CFG_INIT_CARD_ID 0x00007000ul /* GX-C/-D */ -#define CFG_BLK_WR_SIZE 0x00001000ul /* GX-E+ */ -#define CFG_INT_QSF_EN 0x00002000ul /* GX-E+ */ +# define CFG_BUS_TYPE 0x00000007ul /* GX/CX */ +# define CFG_MEM_TYPE_T 0x00000007ul /* 264xT */ +# define CFG_MEM_TYPE 0x00000038ul /* GX/CX */ +# define CFG_DUAL_CAS_EN_T 0x00000008ul /* 264xT */ +# define CFG_ROM_128K_EN 0x00000008ul /* VTB/GTB/LT */ +# define CFG_ROM_REMAP 0x00000008ul /* GTPro */ +# define CFG_VGA_EN_T 0x00000010ul /* VT/GT */ +# define CFG_CLOCK_EN 0x00000020ul /* 264xT */ +# define CFG_DUAL_CAS_EN 0x00000040ul /* GX/CX */ +# define CFG_VMC_SENSE 0x00000040ul /* VT/GT */ +# define CFG_SHARED_MEM_EN 0x00000040ul /* VTB/GTB/LT */ +# define CFG_LOCAL_BUS_OPTION 0x00000180ul /* GX/CX */ +# define CFG_VFC_SENSE 0x00000080ul /* VT/GT */ +# define CFG_INIT_DAC_TYPE 0x00000e00ul /* GX/CX */ +# define CFG_INIT_CARD_ID 0x00007000ul /* GX-C/-D */ +# define CFG_BLK_WR_SIZE 0x00001000ul /* GX-E+ */ +# define CFG_INT_QSF_EN 0x00002000ul /* GX-E+ */ /* ? 0x00004000ul */ /* GX-E+ */ /* ? 0x00007000ul */ /* CX */ -#define CFG_TRI_BUF_DIS 0x00008000ul /* GX/CX */ -#define CFG_BOARD_ID 0x0000ff00ul /* VT/GT */ -#define CFG_EXT_RAM_ADDR 0x003f0000ul /* GX/CX */ -#define CFG_PANEL_ID 0x001f0000ul /* LT */ -#define CFG_MACROVISION_EN 0x00200000ul /* GTPro */ -#define CFG_ROM_DIS 0x00400000ul /* GX/CX */ -#define CFG_PCI33EN 0x00400000ul /* GTPro */ -#define CFG_VGA_EN 0x00800000ul /* GX/CX */ -#define CFG_FULLAGP 0x00800000ul /* GTPro */ -#define CFG_ARITHMOS_ENABLE 0x00800000ul /* XC/XL */ -#define CFG_LOCAL_BUS_CFG 0x01000000ul /* GX/CX */ -#define CFG_CHIP_EN 0x02000000ul /* GX/CX */ -#define CFG_LOCAL_READ_DLY_DIS 0x04000000ul /* GX/CX */ -#define CFG_ROM_OPTION 0x08000000ul /* GX/CX */ -#define CFG_BUS_OPTION 0x10000000ul /* GX/CX */ -#define CFG_LOCAL_DAC_WR_EN 0x20000000ul /* GX/CX */ -#define CFG_VLB_RDY_DIS 0x40000000ul /* GX/CX */ -#define CFG_AP_4GBYTE_DIS 0x80000000ul /* GX/CX */ +# define CFG_TRI_BUF_DIS 0x00008000ul /* GX/CX */ +# define CFG_BOARD_ID 0x0000ff00ul /* VT/GT */ +# define CFG_EXT_RAM_ADDR 0x003f0000ul /* GX/CX */ +# define CFG_PANEL_ID 0x001f0000ul /* LT */ +# define CFG_MACROVISION_EN 0x00200000ul /* GTPro */ +# define CFG_ROM_DIS 0x00400000ul /* GX/CX */ +# define CFG_PCI33EN 0x00400000ul /* GTPro */ +# define CFG_VGA_EN 0x00800000ul /* GX/CX */ +# define CFG_FULLAGP 0x00800000ul /* GTPro */ +# define CFG_ARITHMOS_ENABLE 0x00800000ul /* XC/XL */ +# define CFG_LOCAL_BUS_CFG 0x01000000ul /* GX/CX */ +# define CFG_CHIP_EN 0x02000000ul /* GX/CX */ +# define CFG_LOCAL_READ_DLY_DIS 0x04000000ul /* GX/CX */ +# define CFG_ROM_OPTION 0x08000000ul /* GX/CX */ +# define CFG_BUS_OPTION 0x10000000ul /* GX/CX */ +# define CFG_LOCAL_DAC_WR_EN 0x20000000ul /* GX/CX */ +# define CFG_VLB_RDY_DIS 0x40000000ul /* GX/CX */ +# define CFG_AP_4GBYTE_DIS 0x80000000ul /* GX/CX */ #define CONFIG_STATUS64_1 IOPortTag(0x1du, 0x3au) /* Read */ -#define CFG_PCI_DAC_CFG 0x00000001ul /* GX/CX */ +# define CFG_PCI_DAC_CFG 0x00000001ul /* GX/CX */ /* ? 0x0000001eul */ /* GX/CX */ -#define CFG_1C8_IO_SEL 0x00000020ul /* GX/CX */ +# define CFG_1C8_IO_SEL 0x00000020ul /* GX/CX */ /* ? 0xffffffc0ul */ /* GX/CX */ -#define CRC_SIG 0xfffffffful /* 264xT */ +# define CRC_SIG 0xfffffffful /* 264xT */ #define MPP_CONFIG BlockIOTag(0x3bu) /* VTB/GTB/LT */ #define MPP_STROBE_CONFIG BlockIOTag(0x3cu) /* VTB/GTB/LT */ #define MPP_ADDR BlockIOTag(0x3du) /* VTB/GTB/LT */ @@ -1212,9 +1217,9 @@ This means that this sources don't support ISA and VLB cards */ /* GP_IO IOPortTag(0x1eu, 0x1eu) */ /* See above */ /* CRTC_H_TOTAL_DISP IOPortTag(0x1fu, 0x00u) */ /* Duplicate */ #define DST_OFF_PITCH BlockIOTag(0x40u) -#define DST_OFFSET 0x000ffffful +# define DST_OFFSET 0x000ffffful /* ? 0x00300000ul */ -#define DST_PITCH 0xffc00000ul +# define DST_PITCH 0xffc00000ul #define DST_X BlockIOTag(0x41u) #define DST_Y BlockIOTag(0x42u) #define DST_Y_X BlockIOTag(0x43u) @@ -1227,26 +1232,26 @@ This means that this sources don't support ISA and VLB cards */ #define DST_BRES_INC BlockIOTag(0x4au) #define DST_BRES_DEC BlockIOTag(0x4bu) #define DST_CNTL BlockIOTag(0x4cu) -#define DST_X_DIR 0x00000001ul -#define DST_Y_DIR 0x00000002ul -#define DST_Y_MAJOR 0x00000004ul -#define DST_X_TILE 0x00000008ul -#define DST_Y_TILE 0x00000010ul -#define DST_LAST_PEL 0x00000020ul -#define DST_POLYGON_EN 0x00000040ul -#define DST_24_ROT_EN 0x00000080ul -#define DST_24_ROT 0x00000700ul -#define DST_BRES_SIGN 0x00000800ul /* GX/CX */ -#define DST_BRES_ZERO 0x00000800ul /* CT */ -#define DST_POLYGON_RTEDGE_DIS 0x00001000ul /* CT */ -#define TRAIL_X_DIR 0x00002000ul /* GT */ -#define TRAP_FILL_DIR 0x00004000ul /* GT */ -#define TRAIL_BRES_SIGN 0x00008000ul /* GT */ +# define DST_X_DIR 0x00000001ul +# define DST_Y_DIR 0x00000002ul +# define DST_Y_MAJOR 0x00000004ul +# define DST_X_TILE 0x00000008ul +# define DST_Y_TILE 0x00000010ul +# define DST_LAST_PEL 0x00000020ul +# define DST_POLYGON_EN 0x00000040ul +# define DST_24_ROT_EN 0x00000080ul +# define DST_24_ROT 0x00000700ul +# define DST_BRES_SIGN 0x00000800ul /* GX/CX */ +# define DST_BRES_ZERO 0x00000800ul /* CT */ +# define DST_POLYGON_RTEDGE_DIS 0x00001000ul /* CT */ +# define TRAIL_X_DIR 0x00002000ul /* GT */ +# define TRAP_FILL_DIR 0x00004000ul /* GT */ +# define TRAIL_BRES_SIGN 0x00008000ul /* GT */ /* ? 0x00010000ul */ -#define BRES_SIGN_AUTO 0x00020000ul /* GT */ +# define BRES_SIGN_AUTO 0x00020000ul /* GT */ /* ? 0x00040000ul */ -#define ALPHA_OVERLAP_ENB 0x00080000ul /* GTPro */ -#define SUB_PIX_ON 0x00100000ul /* GTPro */ +# define ALPHA_OVERLAP_ENB 0x00080000ul /* GTPro */ +# define SUB_PIX_ON 0x00100000ul /* GTPro */ /* ? 0xffe00000ul */ /* DST_Y_X BlockIOTag(0x4du) */ /* Duplicate */ #define TRAIL_BRES_ERR BlockIOTag(0x4eu) /* GT */ @@ -1256,6 +1261,7 @@ This means that this sources don't support ISA and VLB cards */ #define Z_OFF_PITCH BlockIOTag(0x52u) /* GT */ #define Z_CNTL BlockIOTag(0x53u) /* GT */ #define ALPHA_TST_CNTL BlockIOTag(0x54u) /* GTPro */ +# define IDCT_EN 0x00008000UL /* ? BlockIOTag(0x55u) */ #define SECONDARY_STW_EXP BlockIOTag(0x56u) /* GTPro */ #define SECONDARY_S_X_INC BlockIOTag(0x57u) /* GTPro */ @@ -1268,9 +1274,9 @@ This means that this sources don't support ISA and VLB cards */ #define SECONDARY_T_Y_INC BlockIOTag(0x5eu) /* GTPro */ #define SECONDARY_T_START BlockIOTag(0x5fu) /* GTPro */ #define SRC_OFF_PITCH BlockIOTag(0x60u) -#define SRC_OFFSET 0x000ffffful +# define SRC_OFFSET 0x000ffffful /* ? 0x00300000ul */ -#define SRC_PITCH 0xffc00000ul +# define SRC_PITCH 0xffc00000ul #define SRC_X BlockIOTag(0x61u) #define SRC_Y BlockIOTag(0x62u) #define SRC_Y_X BlockIOTag(0x63u) @@ -1329,6 +1335,7 @@ This means that this sources don't support ISA and VLB cards */ #define SCALE_Y_INC BlockIOTag(0x7du) /* GT */ #define SCALE_VACC BlockIOTag(0x7eu) /* GT */ #define SCALE_3D_CNTL BlockIOTag(0x7fu) /* GT */ +# define SIGNED_DST_CLAMP 0x00008000UL /* MPEG's MC */ #define HOST_DATA_0 BlockIOTag(0x80u) #define HOST_DATA_1 BlockIOTag(0x81u) #define HOST_DATA_2 BlockIOTag(0x82u) @@ -1349,9 +1356,16 @@ This means that this sources don't support ISA and VLB cards */ #define HOST_BYTE_ALIGN 0x00000001ul #define HOST_BIG_ENDIAN_EN 0x00000002ul /* GX-E/CT */ /* ? 0xfffffffcul */ -#define BM_HOSTDATA BlockIOTag(0x91u) /* VTB/GTB */ +#define BM_HOSTDATA BlockIOTag(0x91u) /* VTB/GTB write-only */ #define BM_ADDR BlockIOTag(0x92u) /* VTB/GTB */ -#define BM_DATA BlockIOTag(0x92u) /* VTB/GTB */ +# define GUIREG_ADDR 0x000000FFUL +# define GUIREG_COUNTER 0x003F0000UL +# define IDCT_FLAGS 0x60000000UL +# define IDCT_EOB 0x00000000UL +# define IDCT_TRIPLETS 0x20000000UL /* run, level, level */ +# define IDCT_AUTOINC 0x40000000UL +# define IDCT_STREAM 0x80000000UL +#define BM_DATA BlockIOTag(0x92u) /* VTB/GTB write-only */ #define BM_GUI_TABLE_CMD BlockIOTag(0x93u) /* GTPro */ # define CIRCULAR_BUF_SIZE_16KB (0 << 0) # define CIRCULAR_BUF_SIZE_32KB (1 << 0) @@ -1373,9 +1387,9 @@ This means that this sources don't support ISA and VLB cards */ #define PAT_REG0 BlockIOTag(0xa0u) #define PAT_REG1 BlockIOTag(0xa1u) #define PAT_CNTL BlockIOTag(0xa2u) -#define PAT_MONO_EN 0x00000001ul -#define PAT_CLR_4x2_EN 0x00000002ul -#define PAT_CLR_8x1_EN 0x00000004ul +# define PAT_MONO_EN 0x00000001ul +# define PAT_CLR_4x2_EN 0x00000002ul +# define PAT_CLR_8x1_EN 0x00000004ul /* ? 0xfffffff8ul */ /* ? BlockIOTag(0xa3u) */ /* ? BlockIOTag(0xa4u) */ @@ -1394,39 +1408,39 @@ This means that this sources don't support ISA and VLB cards */ #define DP_FRGD_CLR BlockIOTag(0xb1u) #define DP_WRITE_MASK BlockIOTag(0xb2u) #define DP_CHAIN_MASK BlockIOTag(0xb3u) -#define DP_CHAIN_1BPP 0x00000000ul /* Irrelevant */ -#define DP_CHAIN_4BPP 0x00008888ul -#define DP_CHAIN_8BPP 0x00008080ul -#define DP_CHAIN_8BPP_332 0x00009292ul -#define DP_CHAIN_15BPP_1555 0x00004210ul -#define DP_CHAIN_16BPP_565 0x00008410ul -#define DP_CHAIN_24BPP_888 0x00008080ul -#define DP_CHAIN_32BPP_8888 0x00008080ul +# define DP_CHAIN_1BPP 0x00000000ul /* Irrelevant */ +# define DP_CHAIN_4BPP 0x00008888ul +# define DP_CHAIN_8BPP 0x00008080ul +# define DP_CHAIN_8BPP_332 0x00009292ul +# define DP_CHAIN_15BPP_1555 0x00004210ul +# define DP_CHAIN_16BPP_565 0x00008410ul +# define DP_CHAIN_24BPP_888 0x00008080ul +# define DP_CHAIN_32BPP_8888 0x00008080ul /* ? 0xffff0000ul */ #define DP_PIX_WIDTH BlockIOTag(0xb4u) -#define DP_DST_PIX_WIDTH 0x0000000ful -#define COMPOSITE_PIX_WIDTH 0x000000f0ul /* GTPro */ -#define DP_SRC_PIX_WIDTH 0x00000f00ul +# define DP_DST_PIX_WIDTH 0x0000000ful +# define COMPOSITE_PIX_WIDTH 0x000000f0ul /* GTPro */ +# define DP_SRC_PIX_WIDTH 0x00000f00ul /* ? 0x00001000ul */ -#define DP_HOST_TRIPLE_EN 0x00002000ul /* GT2c/VT4 */ -#define DP_SRC_AUTONA_FIX_DIS 0x00004000ul /* GTB */ -#define DP_FAST_SRCCOPY_DIS 0x00008000ul /* GTB */ -#define DP_HOST_PIX_WIDTH 0x000f0000ul -#define DP_CI4_RGB_INDEX 0x00f00000ul /* GTB */ -#define DP_BYTE_PIX_ORDER 0x01000000ul -#define DP_CONVERSION_TEMP 0x02000000ul /* GTB */ -#define DP_CI4_RGB_LOW_NIBBLE 0x04000000ul /* GTB */ -#define DP_C14_RGB_HIGH_NIBBLE 0x08000000ul /* GTB */ -#define DP_SCALE_PIX_WIDTH 0xf0000000ul /* GTB */ +# define DP_HOST_TRIPLE_EN 0x00002000ul /* GT2c/VT4 */ +# define DP_SRC_AUTONA_FIX_DIS 0x00004000ul /* GTB */ +# define DP_FAST_SRCCOPY_DIS 0x00008000ul /* GTB */ +# define DP_HOST_PIX_WIDTH 0x000f0000ul +# define DP_CI4_RGB_INDEX 0x00f00000ul /* GTB */ +# define DP_BYTE_PIX_ORDER 0x01000000ul +# define DP_CONVERSION_TEMP 0x02000000ul /* GTB */ +# define DP_CI4_RGB_LOW_NIBBLE 0x04000000ul /* GTB */ +# define DP_C14_RGB_HIGH_NIBBLE 0x08000000ul /* GTB */ +# define DP_SCALE_PIX_WIDTH 0xf0000000ul /* GTB */ #define DP_MIX BlockIOTag(0xb5u) # define BKGD_MIX_NOT_D (0 << 0) # define BKGD_MIX_ZERO (1 << 0) # define BKGD_MIX_ONE (2 << 0) -# define BKGD_MIX_D (3 << 0) +# define BKGD_MIX_D (3 << 0) # define BKGD_MIX_NOT_S (4 << 0) # define BKGD_MIX_D_XOR_S (5 << 0) # define BKGD_MIX_NOT_D_XOR_S (6 << 0) -# define BKGD_MIX_S (7 << 0) +# define BKGD_MIX_S (7 << 0) # define BKGD_MIX_NOT_D_OR_NOT_S (8 << 0) # define BKGD_MIX_D_OR_NOT_S (9 << 0) # define BKGD_MIX_NOT_D_OR_S (10 << 0) @@ -1482,27 +1496,27 @@ This means that this sources don't support ISA and VLB cards */ #define CLR_CMP_CLR BlockIOTag(0xc0u) #define CLR_CMP_MSK BlockIOTag(0xc1u) #define CLR_CMP_CNTL BlockIOTag(0xc2u) -#define CLR_CMP_FN 0x00000007ul -#define CLR_CMP_FN_FALSE 0x00000000ul -#define CLR_CMP_FN_TRUE 0x00000001ul -/* ? 0x00000002ul */ -/* ? 0x00000003ul */ -#define CLR_CMP_FN_NOT_EQUAL 0x00000004ul -#define CLR_CMP_FN_EQUAL 0x00000005ul -/* ? 0x00000006ul */ -/* ? 0x00000007ul */ +# define CLR_CMP_FN 0x00000007ul +# define CLR_CMP_FN_FALSE 0x00000000ul +# define CLR_CMP_FN_TRUE 0x00000001ul +/* ? 0x00000002ul */ +/* ? 0x00000003ul */ +# define CLR_CMP_FN_NOT_EQUAL 0x00000004ul +# define CLR_CMP_FN_EQUAL 0x00000005ul +/* ? 0x00000006ul */ +/* ? 0x00000007ul */ /* ? 0x00fffff8ul */ -#define CLR_CMP_SRC 0x03000000ul -#define CLR_CMP_SRC_DST 0x00000000ul -#define CLR_CMP_SRC_2D 0x01000000ul -#define CLR_CMP_SRC_TEXEL 0x02000000ul -/* ? 0x03000000ul */ +# define CLR_CMP_SRC 0x03000000ul +# define CLR_CMP_SRC_DST 0x00000000ul +# define CLR_CMP_SRC_2D 0x01000000ul +# define CLR_CMP_SRC_TEXEL 0x02000000ul +/* ? 0x03000000ul */ /* ? 0xfc000000ul */ /* ? BlockIOTag(0xc3u) */ #define FIFO_STAT BlockIOTag(0xc4u) -#define FIFO_STAT_BITS 0x0000fffful +# define FIFO_STAT_BITS 0x0000fffful /* ? 0x7fff0000ul */ -#define FIFO_ERR 0x80000000ul +# define FIFO_ERR 0x80000000ul /* ? BlockIOTag(0xc5u) */ /* ? BlockIOTag(0xc6u) */ /* ? BlockIOTag(0xc7u) */ @@ -1510,13 +1524,13 @@ This means that this sources don't support ISA and VLB cards */ /* ? BlockIOTag(0xc9u) */ /* ? BlockIOTag(0xcau) */ #define CONTEXT_LOAD_CNTL BlockIOTag(0xcbu) -#define CONTEXT_LOAD_PTR 0x00007ffful +# define CONTEXT_LOAD_PTR 0x00007ffful /* ? 0x00008000ul */ -#define CONTEXT_LOAD_CMD 0x00030000ul -#define CONTEXT_LOAD_NONE 0x00000000ul -#define CONTEXT_LOAD_ONLY 0x00010000ul -#define CONTEXT_LOAD_FILL 0x00020000ul -#define CONTEXT_LOAD_LINE 0x00030000ul +# define CONTEXT_LOAD_CMD 0x00030000ul +# define CONTEXT_LOAD_NONE 0x00000000ul +# define CONTEXT_LOAD_ONLY 0x00010000ul +# define CONTEXT_LOAD_FILL 0x00020000ul +# define CONTEXT_LOAD_LINE 0x00030000ul /* ? 0x7ffc0000ul */ #define CONTEXT_LOAD_DIS 0x80000000ul #define GUI_TRAJ_CNTL BlockIOTag(0xccu) @@ -1599,7 +1613,13 @@ This means that this sources don't support ISA and VLB cards */ #define ALPHA_FOG_START BlockIOTag(0xfeu) /* GTB */ /* ? BlockIOTag(0xffu) */ #define OVERLAY_Y_X_START BlockIOTag(0x100u) +# define OVERLAY_Y_START 0x000007FFUL +# define OVERLAY_X_START 0x07FF0000UL +# define OVERLAY_LOCK_START 0x80000000UL #define OVERLAY_Y_X_END BlockIOTag(0x101u) +# define OVERLAY_Y_END 0x000007FFUL +# define OVERLAY_X_END 0x07FF0000UL +# define OVERLAY_LOCK_END 0x80000000UL #define OVERLAY_VIDEO_KEY_CLR BlockIOTag(0x102u) #define OVERLAY_VIDEO_KEY_MSK BlockIOTag(0x103u) #define OVERLAY_GRAPHICS_KEY_CLR BlockIOTag(0x104u) @@ -1621,8 +1641,26 @@ This means that this sources don't support ISA and VLB cards */ /* ? BlockIOTag(0x107u) */ #define OVERLAY_SCALE_INC BlockIOTag(0x108u) #define OVERLAY_SCALE_CNTL BlockIOTag(0x109u) +# define SCALE_PIX_EXPAND 0x00000001UL +# define SCALE_Y2R_TEMP 0x00000002UL +# define SCALE_HORZ_MODE 0x00000004UL +# define SCALE_VERT_MODE 0x00000008UL +# define SCALE_SIGNED_UV 0x00000010UL +# define SCALE_GAMMA_SEL_MSK 0x00000060UL +# define SCALE_GAMMA_SEL_BRIGHT 0x00000000UL +# define SCALE_GAMMA_SEL_G22 0x00000020UL +# define SCALE_GAMMA_SEL_G18 0x00000040UL +# define SCALE_GAMMA_SEL_G14 0x00000060UL +# define SCALE_SEL_DISP2 0x00000080UL /* pro only */ +# define SCALE_BANDWIDTH 0x04000000UL +# define SCALE_DIS_LIMIT 0x08000000UL +# define SCALE_CLK_FORCE_ON 0x20000000UL +# define OVERLAY_EN 0x40000000UL +# define SCALE_EN 0x80000000UL #define SCALER_HEIGHT_WIDTH BlockIOTag(0x10au) #define OVERLAY_TEST BlockIOTag(0x10bu) +# define SCALE_SUBPIC_ONLY 0x00000001UL +# define SCALE_Y2R_DIS 0x00000002UL #define SCALER_THRESHOLD BlockIOTag(0x10cu) #define SCALER_BUF0_OFFSET BlockIOTag(0x10du) /* VTB/GTB */ #define SCALER_BUF1_OFFSET BlockIOTag(0x10eu) /* VTB/GTB */ @@ -1632,20 +1670,54 @@ This means that this sources don't support ISA and VLB cards */ #define CAPTURE_HEIGHT_WIDTH BlockIOTag(0x111u) #define CAPTURE_X_WIDTH BlockIOTag(0x111u) /* VTB/GTB */ #define VIDEO_FORMAT BlockIOTag(0x112u) +# define VIDEO_IN_MSK 0x0000000FUL +# define VIDEO_IN_VYUY422 0x0000000BUL +# define VIDEO_IN_YVYU422 0x0000000CUL +# define VIDEO_SIGNED_UV 0x00000010UL +# define SCALER_IN_MSK 0x000F0000UL +# define SCALER_IN_RGB15 0x00030000UL +# define SCALER_IN_RGB16 0x00040000UL +# define SCALER_IN_RGB32 0x00060000UL +# define SCALER_IN_YUV9 0x00090000UL +# define SCALER_IN_YUV12 0x000A0000UL +# define SCALER_IN_VYUY422 0x000B0000UL +# define SCALER_IN_YVYU422 0x000C0000UL +# define HOST_BYTE_SHIFT_EN 0x10000000UL +# define HOST_YUV_APER 0x20000000UL +# define HOST_MEM_MODE_MSK 0xC0000000UL +# define HOST_MEM_MODE_NORMAL 0x00000000UL +# define HOST_MEM_MODE_Y 0x40000000UL +# define HOST_MEM_MODE_U 0x80000000UL +# define HOST_MEM_MODE_V 0xC0000000UL #define VIDEO_CONFIG BlockIOTag(0x113u) #define VBI_START_END BlockIOTag(0x113u) /* VTB/GTB */ #define CAPTURE_CONFIG BlockIOTag(0x114u) #define TRIG_CNTL BlockIOTag(0x115u) #define VIDEO_SYNC_TEST BlockIOTag(0x116u) #define OVERLAY_EXCLUSIVE_HORZ BlockIOTag(0x116u) /* VTB/GTB */ +# define EXCLUSIVE_HORZ_START 0x000000FFUL +# define EXCLUSIVE_HORZ_END 0x0000FF00UL +# define EXCLUSIVE_BACK_PORSH 0x00FF0000UL +# define EXCLUSIVE_EN 0x80000000UL #define EXT_CRTC_GEN_CNTL_R BlockIOTag(0x117u) /* VT-A4 (R) */ #define OVERLAY_EXCLUSIVE_VERT BlockIOTag(0x117u) /* VTB/GTB */ +# define EXCLUSIVE_VERT_START 0x000007FFUL +# define EXCLUSIVE_VERT_END 0x07FF0000UL #define VMC_CONFIG BlockIOTag(0x118u) #define VBI_WIDTH BlockIOTag(0x118u) /* VTB/GTB */ #define VMC_STATUS BlockIOTag(0x119u) #define CAPTURE_DEBUG BlockIOTag(0x119u) /* VTB/GTB */ #define VMC_CMD BlockIOTag(0x11au) #define VIDEO_SYNC_TEST_B BlockIOTag(0x11au) /* VTB/GTB */ +# define TEST_CRTC_OVLSOF 0x00000001UL +# define TEST_CRTC_VOVLEN 0x00000002UL +# define TEST_VID_SOF 0x00000100UL +# define TEST_VID_EOF 0x00000200UL +# define TEST_VID_EOL 0x00000400UL +# define TEST_VID_FIELD 0x00000800UL +# define TEST_END_OF_VBI 0x00001000UL +# define TEST_BUSMASTER_EOL 0x00002000UL +# define TEST_SYNC_EN 0x80000000UL #define VMC_ARG0 BlockIOTag(0x11bu) #define VMC_ARG1 BlockIOTag(0x11cu) #define SNAPSHOT_VH_COUNTS BlockIOTag(0x11cu) /* GTPro */ @@ -1713,6 +1785,12 @@ This means that this sources don't support ISA and VLB cards */ #define AGP_BASE BlockIOTag(0x152u) /* GTPro */ #define AGP_CNTL BlockIOTag(0x153u) /* GTPro */ #define SCALER_COLOUR_CNTL BlockIOTag(0x154u) /* GTPro */ +# define COLOUR_BRIGHTNESS 0x0000007FUL +# define COLOUR_SATURATION_U 0x00001F00UL +# define COLOUR_SATURATION_V 0x001F0000UL +# define SCALER_VERT_ADJ_UV 0x0FE00000UL +/*# define SCALER_VERT_ADJ_UV 0x0F000000UL (need testing) */ +# define SCALER_HORZ_ADJ_UV 0xF0000000UL #define SCALER_H_COEFF0 BlockIOTag(0x155u) /* GTPro */ #define SCALER_H_COEFF1 BlockIOTag(0x156u) /* GTPro */ #define SCALER_H_COEFF2 BlockIOTag(0x157u) /* GTPro */ @@ -1733,10 +1811,13 @@ This means that this sources don't support ISA and VLB cards */ /* ? 0xfffc0000ul */ /* ? BlockIOTag(0x15fu) */ /* BUS MASTERING */ -#define BM_FRAME_BUF_OFFSET BlockIOTag(0x160u) /* VTB/GTB */ -#define BM_SYSTEM_MEM_ADDR BlockIOTag(0x161u) /* VTB/GTB */ -#define BM_COMMAND BlockIOTag(0x162u) /* VTB/GTB */ -#define BM_STATUS BlockIOTag(0x163u) /* VTB/GTB */ +#define BM_FRAME_BUF_OFFSET BlockIOTag(0x160u) /* VTB/GTB read-only */ +#define BM_SYSTEM_MEM_ADDR BlockIOTag(0x161u) /* VTB/GTB read-only */ +#define BM_COMMAND BlockIOTag(0x162u) /* VTB/GTB read-only */ +# define BM_CMD_BYTE_COUNT 0x00001FFFUL +# define BM_CMD_HOLD_OFFSET 0x40000000UL +# define BM_CMD_EOL 0x80000000UL +#define BM_STATUS BlockIOTag(0x163u) /* VTB/GTB read-only */ /* ? BlockIOTag(0x164u) */ /* ? BlockIOTag(0x165u) */ /* ? BlockIOTag(0x166u) */ @@ -1749,14 +1830,16 @@ This means that this sources don't support ISA and VLB cards */ /* ? BlockIOTag(0x16du) */ #define BM_GUI_TABLE BlockIOTag(0x16eu) /* VTB/GTB */ #define BM_SYSTEM_TABLE BlockIOTag(0x16fu) /* VTB/GTB */ -# define DMA_GUI_COMMAND__BYTE_COUNT_MASK 0x001fffff +# define DMA_GUI_COMMAND__BYTE_COUNT_MASK 0x001ffff0 # define DMA_GUI_COMMAND__HOLD_VIDEO_OFFSET 0x40000000 # define DMA_GUI_COMMAND__EOL 0x80000000 +# define SYSTEM_TRIGGER_MASK 0x7 # define SYSTEM_TRIGGER_SYSTEM_TO_VIDEO 0x0 # define SYSTEM_TRIGGER_VIDEO_TO_SYSTEM 0x1 # define SYSTEM_TRIGGER_VIDEO_TO_SYSTEM_AFTER_BUF0_READY 0x2 # define SYSTEM_TRIGGER_VIDEO_TO_SYSTEM_AFTER_BUF1_READY 0x3 # define SYSTEM_TRIGGER_VIDEO_TO_SYSTEM_AFTER_SNAPSHOT_READY 0x4 +# define SYSTEM_TRIGGER_SYSTEM_TO_MPP 0x5 /* ? BlockIOTag(0x170u) */ /* ? BlockIOTag(0x171u) */ /* ? BlockIOTag(0x172u) */ @@ -1853,38 +1936,85 @@ This means that this sources don't support ISA and VLB cards */ #define VERTEX_2_SECONDARY_S BlockIOTag(0x1cdu) /* GTPro */ #define VERTEX_2_SECONDARY_T BlockIOTag(0x1ceu) /* GTPro */ #define VERTEX_2_SECONDARY_W BlockIOTag(0x1cfu) /* GTPro */ -/* ? BlockIOTag(0x1d0u) */ -/* ? BlockIOTag(0x1d1u) */ +/* IDCT and DVD's subpicture direct support (Rage Mobility only) */ +#define SUBPIC_CNTL BlockIOTag(0x1d0u) +# define SUBPIC_ON 0x00000001UL +# define BTN_HLI_ON 0x00000002UL +# define SP_HORZ_MODE 0x00000010UL +# define SP_VERT_MODE 0x00000020UL +# define SP_ODD_FIELD 0x00000100UL +# define SP_BUF_SELECT 0x00000200UL +# define SP_NO_R_EDGE_BLEND 0x00000400UL +#define SUBPIC_DEFCOLON BlockIOTag(0x1d1u) +# define BKGD_PIX_CON 0x0000000FUL +# define PATT_PIX_CON 0x000000F0UL +# define EMPH_PIX1_CON 0x00000F00UL +# define EMPH_PIX2_CON 0x0000F000UL +# define BKGD_PIX_CLR 0x000F0000UL +# define PATT_PIX_CLR 0x00F00000UL +# define EMPH_PIX1_CLR 0x0F000000UL +# define EMPH_PIX2_CLR 0xF0000000UL /* ? BlockIOTag(0x1d2u) */ -/* ? BlockIOTag(0x1d3u) */ -/* ? BlockIOTag(0x1d4u) */ -/* ? BlockIOTag(0x1d5u) */ -/* ? BlockIOTag(0x1d6u) */ -/* ? BlockIOTag(0x1d7u) */ -/* ? BlockIOTag(0x1d8u) */ -/* ? BlockIOTag(0x1d9u) */ -/* ? BlockIOTag(0x1dau) */ -/* ? BlockIOTag(0x1dbu) */ -/* ? BlockIOTag(0x1dcu) */ -/* ? BlockIOTag(0x1ddu) */ -/* ? BlockIOTag(0x1deu) */ -/* ? BlockIOTag(0x1dfu) */ -/* ? BlockIOTag(0x1e0u) */ -/* ? BlockIOTag(0x1e1u) */ -/* ? BlockIOTag(0x1e2u) */ -/* ? BlockIOTag(0x1e3u) */ +#define SUBPIC_Y_X_START BlockIOTag(0x1d3u) +#define SUBPIC_Y_X_END BlockIOTag(0x1d4u) +#define SUBPIC_V_INC BlockIOTag(0x1d5u) +#define SUBPIC_H_INC BlockIOTag(0x1d6u) +#define SUBPIC_BUF0_OFFSET BlockIOTag(0x1d7u) +#define SUBPIC_BUF1_OFFSET BlockIOTag(0x1d8u) +#define SUBPIC_LC0_OFFSET BlockIOTag(0x1d9u) +#define SUBPIC_LC1_OFFSET BlockIOTag(0x1dau) +#define SUBPIC_PITCH BlockIOTag(0x1dbu) +# define SUBPIC_BUF_PITCH 0x00000FC0UL +# define SUBPIC_LC_PITCH 0x0FC00000UL +#define SUBPIC_BTN_HLI_COLCON BlockIOTag(0x1dcu) +# define BTN_HLI_BKGD_PIX_CON 0x0000000FUL +# define BTN_HLI_PATT_PIX_CON 0x000000F0UL +# define BTN_HLI_EMPH_PIX1_CON 0x00000F00UL +# define BTN_HLI_EMPH_PIX2_CON 0x0000F000UL +# define BTN_HLI_BKGD_PIX_CLR 0x000F0000UL +# define BTN_HLI_PATT_PIX_CLR 0x00F00000UL +# define BTN_HLI_EMPH_PIX1_CLR 0x0F000000UL +# define BTN_HLI_EMPH_PIX2_CLR 0xF0000000UL +#define SUBPIC_BTN_Y_X_START BlockIOTag(0x1ddu) +#define SUBPIC_BTN_Y_X_END BlockIOTag(0x1deu) +#define SUBPIC_H_ACCUM_INIT BlockIOTag(0x1dfu) +#define IDCT_RUNS BlockIOTag(0x1e0u) +# define IDCT_RUNS_3 0x000000FFUL +# define IDCT_RUNS_2 0x0000FF00UL +# define IDCT_RUNS_1 0x00FF0000UL +# define IDCT_RUNS_0 0xFF000000UL +#define IDCT_LEVELS BlockIOTag(0x1e1u) +# define IDCT_LEVELS_HI 0x0000FFFFUL +# define IDCT_LEVELS_LO 0xFFFF0000UL +#define IDCT_RESERVE_REGISTER1 BlockIOTag(0x1e2u) +#define IDCT_RESERVE_REGISTER2 BlockIOTag(0x1e3u) /* ? BlockIOTag(0x1e4u) */ /* ? BlockIOTag(0x1e5u) */ -/* ? BlockIOTag(0x1e6u) */ -/* ? BlockIOTag(0x1e7u) */ -/* ? BlockIOTag(0x1e8u) */ +#define SUBPIC_V_ACCUM_INIT BlockIOTag(0x1e6u) +#define SUBPIC_PALETTE_INDEX BlockIOTag(0x1e7u) +#define SUBPIC_PALETTE_DATA BlockIOTag(0x1e8u) /* ? BlockIOTag(0x1e9u) */ /* ? BlockIOTag(0x1eau) */ /* ? BlockIOTag(0x1ebu) */ /* ? BlockIOTag(0x1ecu) */ /* ? BlockIOTag(0x1edu) */ /* ? BlockIOTag(0x1eeu) */ -/* ? BlockIOTag(0x1efu) */ +#define IDCT_CONTROL BlockIOTag(0x1efu) +# define IDCT_LUMA_RD_FORMAT_MSK 0x00000003UL +# define IDCT_LUMA_RD_FORMAT_0123 0x00000000UL +# define IDCT_LUMA_RD_FORMAT_0246 0x00000001UL +# define IDCT_LUMA_RD_FORMAT_0819 0x00000002UL +# define IDCT_CHROMA_RD_FMT_MSK 0x0000000CUL +# define IDCT_CHROMA_RD_FMT_0123 0x00000000UL +# define IDCT_CHROMA_RD_FMT_0246 0x00000004UL +# define IDCT_CHROMA_RD_FMT_0819 0x00000008UL +# define IDCT_CTL_SCAN_PATTERN 0x00000010UL +# define IDCT_CTL_INTRA 0x00000020UL +# define IDCT_CTL_FLUSH 0x00000040UL +# define IDCT_CTL_PASSTHRU 0x00000080UL +# define IDCT_CTL_SW_RESET 0x00000100UL +# define IDCT_CONST_REQ 0x00000200UL +# define IDCT_SCRAMBLE 0x00000400UL /* ? BlockIOTag(0x1f0u) */ /* ? BlockIOTag(0x1f1u) */ /* ? BlockIOTag(0x1f2u) */ diff --git a/src/video_out/vidix/drivers/mach64_vid.c b/src/video_out/vidix/drivers/mach64_vid.c index a79471571..9b630375f 100644 --- a/src/video_out/vidix/drivers/mach64_vid.c +++ b/src/video_out/vidix/drivers/mach64_vid.c @@ -16,6 +16,14 @@ #include <math.h> #include <inttypes.h> #include <fcntl.h> +#include <sys/mman.h> /* for m(un)lock */ +#ifdef HAVE_MALLOC_H +#include <malloc.h> +#ifdef HAVE_MEMALIGN +#define MACH64_ENABLE_BM 1 +#endif +#endif + #include "../vidix.h" #include "../fourcc.h" @@ -27,20 +35,42 @@ #define UNUSED(x) ((void)(x)) /**< Removes warning about unused arguments */ + +#ifdef MACH64_ENABLE_BM + +#define cpu_to_le32(a) (a) +#define VIRT_TO_CARD(a,b,c) bm_virt_to_bus(a,b,c) +#pragma pack(1) +typedef struct +{ + uint32_t framebuf_offset; + uint32_t sys_addr; + uint32_t command; + uint32_t reserved; +} bm_list_descriptor; +#pragma pack() +static void *mach64_dma_desc_base[64]; +static unsigned long bus_addr_dma_desc = 0; +static unsigned long *dma_phys_addrs; +#endif + static void *mach64_mmio_base = 0; static void *mach64_mem_base = 0; static int32_t mach64_overlay_offset = 0; static uint32_t mach64_ram_size = 0; -static uint32_t mach64_buffer_base[10][3]; +static uint32_t mach64_buffer_base[64][3]; static int num_mach64_buffers=-1; static int supports_planar=0; +static int supports_colour_adj=0; +static int supports_idct=0; +static int supports_subpic=0; static int supports_lcd_v_stretch=0; pciinfo_t pci_info; static int probed = 0; static int __verbose = 0; -#define VERBOSE_LEVEL 1 +#define VERBOSE_LEVEL 2 typedef struct bes_registers_s { @@ -117,7 +147,23 @@ static video_registers_t vregs[] = DECLARE_VREG(VIDEO_FORMAT), DECLARE_VREG(VIDEO_CONFIG), DECLARE_VREG(VIDEO_SYNC_TEST), - DECLARE_VREG(VIDEO_SYNC_TEST_B) + DECLARE_VREG(VIDEO_SYNC_TEST_B), + DECLARE_VREG(BUS_CNTL), + DECLARE_VREG(SRC_CNTL), + DECLARE_VREG(GUI_STAT), + DECLARE_VREG(BM_ADDR), + DECLARE_VREG(BM_DATA), + DECLARE_VREG(BM_HOSTDATA), + DECLARE_VREG(BM_GUI_TABLE_CMD), + DECLARE_VREG(BM_FRAME_BUF_OFFSET), + DECLARE_VREG(BM_SYSTEM_MEM_ADDR), + DECLARE_VREG(BM_COMMAND), + DECLARE_VREG(BM_STATUS), + DECLARE_VREG(BM_GUI_TABLE), + DECLARE_VREG(BM_SYSTEM_TABLE), + DECLARE_VREG(AGP_BASE), + DECLARE_VREG(AGP_CNTL), + DECLARE_VREG(CRTC_INT_CNTL) }; /* VIDIX exports */ @@ -176,6 +222,17 @@ static __inline__ void OUTPLL(uint32_t addr,uint32_t val) _tmp |= (val); \ OUTPLL(addr, _tmp); \ } while (0) + +static void mach64_engine_reset( void ) +{ + /* Kill off bus mastering with extreme predjudice... */ + OUTREG(BUS_CNTL, INREG(BUS_CNTL) | BUS_MASTER_DIS); + /* Reset engine -- This is accomplished by setting bit 8 of the GEN_TEST_CNTL + register high, then low (per the documentation, it's on high to low transition + that the GUI engine gets reset...) */ + OUTREG( GEN_TEST_CNTL, INREG( GEN_TEST_CNTL ) | GEN_GUI_EN ); + OUTREG( GEN_TEST_CNTL, INREG( GEN_TEST_CNTL ) & ~GEN_GUI_EN ); +} static void mach64_fifo_wait(unsigned n) { @@ -184,8 +241,10 @@ static void mach64_fifo_wait(unsigned n) static void mach64_wait_for_idle( void ) { + unsigned i; mach64_fifo_wait(16); - while ((INREG(GUI_STAT) & 1)!= 0); + for (i=0; i<2000000; i++) if((INREG(GUI_STAT) & GUI_ACTIVE) == 0) break; + if((INREG(GUI_STAT) & 1) != 0) mach64_engine_reset(); /* due card lookup */ } static void mach64_wait_vsync( void ) @@ -443,10 +502,10 @@ static void reset_regs( void ) } } - int vixInit(void) { int err; + unsigned i; if(!probed) { printf("[mach64] Driver was not probed but is being initializing\n"); @@ -482,9 +541,20 @@ int vixInit(void) if(INREG(SCALER_BUF0_OFFSET_U)) supports_planar=1; } - if(supports_planar) printf("[mach64] Planar YUV formats are supported :)\n"); - else printf("[mach64] Planar YUV formats are not supported :(\n"); - + printf("[mach64] Planar YUV formats are %s supported\n",supports_planar?"":"not"); + supports_colour_adj=0; + OUTREG(SCALER_COLOUR_CNTL,-1); + if(INREG(SCALER_COLOUR_CNTL)) supports_colour_adj=1; + supports_idct=0; + OUTREG(IDCT_CONTROL,-1); + if(INREG(IDCT_CONTROL)) supports_idct=1; + OUTREG(IDCT_CONTROL,0); + printf("[mach64] IDCT is %s supported\n",supports_idct?"":"not"); + supports_subpic=0; + OUTREG(SUBPIC_CNTL,-1); + if(INREG(SUBPIC_CNTL)) supports_subpic=1; + OUTREG(SUBPIC_CNTL,0); + printf("[mach64] subpictures are %s supported\n",supports_subpic?"":"not"); if( mach64_cap.device_id==DEVICE_ATI_RAGE_MOBILITY_P_M || mach64_cap.device_id==DEVICE_ATI_RAGE_MOBILITY_P_M2 || mach64_cap.device_id==DEVICE_ATI_RAGE_MOBILITY_L @@ -495,15 +565,46 @@ int vixInit(void) reset_regs(); mach64_vid_make_default(); - if(__verbose > VERBOSE_LEVEL) mach64_vid_dump_regs(); +#ifdef MACH64_ENABLE_BM + if(bm_open() == 0) + { + mach64_cap.flags |= FLAG_DMA | FLAG_EQ_DMA; + if((dma_phys_addrs = malloc(mach64_ram_size*sizeof(unsigned long)/4096)) == 0) + { + out_mem: + printf("[mach64] Can't allocate temopary buffer for DMA\n"); + mach64_cap.flags &= ~FLAG_DMA & ~FLAG_EQ_DMA; + return 0; + } + /* + WARNING: We MUST have continigous descriptors!!! + But: (720*720*2(YUV422)*16(sizeof(bm_descriptor)))/4096=4050 + Thus one 4K page is far enough to describe max movie size. + */ + for(i=0;i<64;i++) + if((mach64_dma_desc_base[i] = memalign(4096,mach64_ram_size*sizeof(bm_list_descriptor)/4096)) == 0) + goto out_mem; + } + else + if(__verbose) printf("[mach64] Can't initialize busmastering: %s\n",strerror(errno)); +#endif return 0; } void vixDestroy(void) { + unsigned i; unmap_phys_mem(mach64_mem_base,mach64_ram_size); unmap_phys_mem(mach64_mmio_base,0x4000); +#ifdef MACH64_ENABLE_BM + bm_close(); + if(dma_phys_addrs) free(dma_phys_addrs); + for(i=0;i<64;i++) + { + if(mach64_dma_desc_base[i]) free(mach64_dma_desc_base[i]); + } +#endif } int vixGetCapability(vidix_capability_t *to) @@ -612,7 +713,7 @@ static void mach64_vid_stop_video( void ) static void mach64_vid_display_video( void ) { - uint32_t vf; + uint32_t vf,sc,width; mach64_fifo_wait(14); OUTREG(OVERLAY_Y_X_START, besr.y_x_start); @@ -627,65 +728,67 @@ static void mach64_vid_display_video( void ) OUTREG(SCALER_BUF1_OFFSET_U, mach64_buffer_base[0][1]); OUTREG(SCALER_BUF1_OFFSET_V, mach64_buffer_base[0][2]); mach64_wait_vsync(); - + width = (besr.height_width >> 16 & 0x03FF); + sc = SCALE_EN | OVERLAY_EN | + SCALE_BANDWIDTH | /* reset bandwidth status */ + SCALE_PIX_EXPAND | /* dynamic range correct */ + SCALE_Y2R_TEMP; /* use the equal temparature for every component of RGB */ + /* Force clocks of scaler. */ + if(width > 360 && !supports_planar && !mach64_is_interlace()) + sc |= SCALE_CLK_FORCE_ON; + /* Do we need that? And how we can improve the quality of 3dRageII scaler ? + 3dRageII+ (non pro) is really crapped HW :( + ^^^^^^^^^^^^^^^^^^^ + !!SCALER_WIDTH <= 360 provides full scaling functionality !!!!!!!!!!!!! + !!360 < SCALER_WIDTH <= 720 provides scaling with vertical replication (crap) + !!SCALER_WIDTH > 720 is illegal. (no comments) + + As for me - I would prefer to limit movie's width with 360 but it provides only + half of picture but with perfect quality. (NK) */ mach64_fifo_wait(4); - OUTREG(OVERLAY_SCALE_CNTL, 0xC4000003); -// OVERLAY_SCALE_CNTL bits & what they seem to affect -// bit 0 no effect -// bit 1 yuv2rgb coeff related -// bit 2 horizontal interpolation if 0 -// bit 3 vertical interpolation if 0 -// bit 4 chroma encoding (0-> 128=neutral / 1-> 0->neutral) -// bit 5-6 gamma correction -// bit 7 nothing visible if set -// bit 8-27 no effect -// bit 28-31 nothing interresting just crashed my system when i played with them :( + OUTREG(OVERLAY_SCALE_CNTL, sc); mach64_wait_for_idle(); - vf = INREG(VIDEO_FORMAT); - -// Bits 16-19 seem to select the format -// 0x0 dunno behaves strange -// 0x1 dunno behaves strange -// 0x2 dunno behaves strange -// 0x3 BGR15 -// 0x4 BGR16 -// 0x5 BGR16 (hmm, that need investigation, 2 BGR16 formats, i guess 1 will have only 5bits for green) -// 0x6 BGR32 -// 0x7 BGR32 with somehow mixed even / odd pixels ? -// 0x8 YYYYUVUV -// 0x9 YVU9 -// 0xA YV12 -// 0xB YUY2 -// 0xC UYVY -// 0xD UYVY (no difference is visible if i switch between C/D for every even/odd frame) -// 0xE dunno behaves strange -// 0xF dunno behaves strange -// Bit 28 all values are assumed to be 7 bit with chroma=64 for black (tested with YV12 & YUY2) -// the remaining bits seem to have no effect - switch(besr.fourcc) { /* BGR formats */ - case IMGFMT_BGR15: OUTREG(VIDEO_FORMAT, 0x00030000); break; - case IMGFMT_BGR16: OUTREG(VIDEO_FORMAT, 0x00040000); break; - case IMGFMT_BGR32: OUTREG(VIDEO_FORMAT, 0x00060000); break; + case IMGFMT_BGR15: vf = SCALER_IN_RGB15; break; + case IMGFMT_BGR16: vf = SCALER_IN_RGB16; break; + case IMGFMT_BGR32: vf = SCALER_IN_RGB32; break; /* 4:2:0 */ case IMGFMT_IYUV: case IMGFMT_I420: - case IMGFMT_YV12: OUTREG(VIDEO_FORMAT, 0x000A0000); break; - - case IMGFMT_YVU9: OUTREG(VIDEO_FORMAT, 0x00090000); break; + case IMGFMT_YV12: vf = SCALER_IN_YUV12; break; + /* 4:1:0 */ + case IMGFMT_YVU9: vf = SCALER_IN_YUV9; break; /* 4:2:2 */ case IMGFMT_YVYU: - case IMGFMT_UYVY: OUTREG(VIDEO_FORMAT, 0x000C0000); break; + case IMGFMT_UYVY: vf = SCALER_IN_YVYU422; break; case IMGFMT_YUY2: - default: OUTREG(VIDEO_FORMAT, 0x000B0000); break; + default: vf = SCALER_IN_VYUY422; break; } + OUTREG(VIDEO_FORMAT,vf); if(__verbose > VERBOSE_LEVEL) mach64_vid_dump_regs(); } +/* Goal of this function: hide RGB background and provide black screen around movie. + Useful in '-vo fbdev:vidix -fs -zoom' mode. + Reverse effect to colorkey */ +static void mach64_vid_exclusive( void ) +{ + unsigned screenw,screenh; + screenw = mach64_get_xres(); + screenh = mach64_get_yres(); + OUTREG(OVERLAY_EXCLUSIVE_VERT,(((screenh-1)<<16)&EXCLUSIVE_VERT_END)); + OUTREG(OVERLAY_EXCLUSIVE_HORZ,(((screenw/8+1)<<8)&EXCLUSIVE_HORZ_END)|EXCLUSIVE_EN); +} + +static void mach64_vid_non_exclusive( void ) +{ + OUTREG(OVERLAY_EXCLUSIVE_HORZ,0); +} + static int mach64_vid_init_video( vidix_playback_t *config ) { uint32_t src_w,src_h,dest_w,dest_h,pitch,h_inc,v_inc,left,leftUV,top,ecp,y_pos; @@ -751,11 +854,11 @@ for(i=0; i<32; i++){ if(mach64_is_interlace()) v_inc<<=1; if(mach64_is_dbl_scan() ) v_inc>>=1; - v_inc>>=4; // convert 16.16 -> 20.12 v_inc/= dest_h; - + v_inc>>=4; // convert 16.16 -> 4.12 + h_inc = (src_w << (12+ecp)) / dest_w; - /* keep everything in 16.16 */ + /* keep everything in 4.12 */ config->offsets[0] = 0; for(i=1; i<config->num_frames; i++) config->offsets[i] = config->offsets[i-1] + config->frame_size; @@ -870,19 +973,39 @@ int vixQueryFourcc(vidix_fourcc_t *to) int vixConfigPlayback(vidix_playback_t *info) { + unsigned rgb_size,nfr; + uint32_t mach64_video_size; if(!is_supported_fourcc(info->fourcc)) return ENOSYS; + if(info->src.h > 720 || info->src.w > 720) + { + printf("[mach64] Can't apply width or height > 720\n"); + return EINVAL; + } + if(info->num_frames>VID_PLAY_MAXFRAMES) info->num_frames=VID_PLAY_MAXFRAMES; mach64_compute_framesize(info); - - if(info->num_frames>4) info->num_frames=4; - for(;info->num_frames>0; info->num_frames--) + rgb_size = mach64_get_xres()*mach64_get_yres()*((mach64_vid_get_dbpp()+7)/8); + nfr = info->num_frames; + mach64_video_size = mach64_ram_size; + for(;nfr>0;nfr--) { - mach64_overlay_offset = mach64_ram_size - info->frame_size*info->num_frames; + mach64_overlay_offset = mach64_video_size - info->frame_size*nfr; mach64_overlay_offset &= 0xffff0000; - if(mach64_overlay_offset>0) break; + if(mach64_overlay_offset >= (int)rgb_size ) break; } - if(info->num_frames <= 0) return EINVAL; - + if(nfr <= 3) + { + nfr = info->num_frames; + for(;nfr>0;nfr--) + { + mach64_overlay_offset = mach64_video_size - info->frame_size*nfr; + mach64_overlay_offset &= 0xffff0000; + if(mach64_overlay_offset>=0) break; + } + } + if(nfr <= 0) return EINVAL; + info->num_frames=nfr; + num_mach64_buffers = info->num_frames; info->dga_addr = (char *)mach64_mem_base + mach64_overlay_offset; mach64_vid_init_video(info); return 0; @@ -890,8 +1013,20 @@ int vixConfigPlayback(vidix_playback_t *info) int vixPlaybackOn(void) { + int err; + unsigned dw,dh; + dw = (besr.y_x_end >> 16) - (besr.y_x_start >> 16); + dh = (besr.y_x_end & 0xFFFF) - (besr.y_x_start & 0xFFFF); + if(dw == mach64_get_xres() || dh == mach64_get_yres()) mach64_vid_exclusive(); + else mach64_vid_non_exclusive(); mach64_vid_display_video(); - return 0; + err = INREG(SCALER_BUF_PITCH) == besr.vid_buf_pitch ? 0 : EINTR; + if(err) + { + printf("[mach64] *** Internal fatal error ***: Detected pitch corruption\n" + "[mach64] Try decrease number of buffers\n"); + } + return err; } int vixPlaybackOff(void) @@ -905,18 +1040,17 @@ int vixPlaybackFrameSelect(unsigned int frame) uint32_t off[6]; int i; int last_frame= (frame-1+num_mach64_buffers) % num_mach64_buffers; -//printf("Selecting frame %d\n", frame); /* buf3-5 always should point onto second buffer for better deinterlacing and TV-in */ if(num_mach64_buffers==1) return 0; - for(i=0; i<3; i++) { off[i] = mach64_buffer_base[frame][i]; off[i+3]= mach64_buffer_base[last_frame][i]; } + if(__verbose > VERBOSE_LEVEL) printf("mach64_vid: flip_page = %u\n",frame); #if 0 // delay routine so the individual frames can be ssen better { @@ -949,6 +1083,7 @@ vidix_video_eq_t equal = int vixPlaybackGetEq( vidix_video_eq_t * eq) { memcpy(eq,&equal,sizeof(vidix_video_eq_t)); + if(!supports_colour_adj) eq->cap = VEQ_CAP_BRIGHTNESS; return 0; } @@ -965,12 +1100,29 @@ int vixPlaybackSetEq( const vidix_video_eq_t * eq) equal.green_intensity = eq->green_intensity; equal.blue_intensity = eq->blue_intensity; } - equal.flags = eq->flags; - br = equal.brightness * 64 / 1000; - if(br < -64) br = -64; if(br > 63) br = 63; - sat = (equal.saturation + 1000) * 16 / 1000; - if(sat < 0) sat = 0; if(sat > 31) sat = 31; - OUTREG(SCALER_COLOUR_CNTL, (br & 0x7f) | (sat << 8) | (sat << 16)); + if(supports_colour_adj) + { + equal.flags = eq->flags; + br = equal.brightness * 64 / 1000; + if(br < -64) br = -64; if(br > 63) br = 63; + sat = (equal.saturation + 1000) * 16 / 1000; + if(sat < 0) sat = 0; if(sat > 31) sat = 31; + OUTREG(SCALER_COLOUR_CNTL, (br & 0x7f) | (sat << 8) | (sat << 16)); + } + else + { + unsigned gamma; + br = equal.brightness * 3 / 1000; + if(br < 0) br = 0; + switch(br) + { + default:gamma = SCALE_GAMMA_SEL_BRIGHT; break; + case 1: gamma = SCALE_GAMMA_SEL_G14; break; + case 2: gamma = SCALE_GAMMA_SEL_G18; break; + case 3: gamma = SCALE_GAMMA_SEL_G22; break; + } + OUTREG(OVERLAY_SCALE_CNTL,(INREG(OVERLAY_SCALE_CNTL) & ~SCALE_GAMMA_SEL_MSK) | gamma); + } return 0; } @@ -1043,3 +1195,67 @@ int vixSetGrKeys(const vidix_grkey_t *grkey) return(0); } + +#ifdef MACH64_ENABLE_BM +static int mach64_setup_frame( vidix_dma_t * dmai ) +{ + if(mach64_overlay_offset + dmai->dest_offset + dmai->size > mach64_ram_size) return E2BIG; + if(dmai->idx > VID_PLAY_MAXFRAMES-1) dmai->idx=0; + if(!(dmai->internal[dmai->idx] && (dmai->flags & BM_DMA_FIXED_BUFFS))) + { + bm_list_descriptor * list = (bm_list_descriptor *)mach64_dma_desc_base[dmai->idx]; + unsigned long dest_ptr; + unsigned i,n,count; + int retval; + n = dmai->size / 4096; + if(dmai->size % 4096) n++; + if((retval = VIRT_TO_CARD(dmai->src,dmai->size,dma_phys_addrs)) != 0) return retval; + dmai->internal[dmai->idx] = mach64_dma_desc_base[dmai->idx]; + dest_ptr = dmai->dest_offset; + count = dmai->size; + for(i=0;i<n;i++) + { + list[i].framebuf_offset = mach64_overlay_offset + dest_ptr; /* offset within of video memory */ + list[i].sys_addr = dma_phys_addrs[i]; + list[i].command = (count > 4096 ? 4096 : (count | DMA_GUI_COMMAND__EOL)); + list[i].reserved = 0; +#if 0 +printf("MACH64_DMA_TABLE[%i] %X %X %X %X\n",i,list[i].framebuf_offset,list[i].sys_addr,list[i].command,list[i].reserved); +#endif + dest_ptr += 4096; + count -= 4096; + } + } + return 0; +} + +static int mach64_transfer_frame( unsigned long ba_dma_desc ) +{ + mach64_wait_for_idle(); + OUTREG(BUS_CNTL,(INREG(BUS_CNTL)|BUS_MSTR_RESET)); + OUTREG(CRTC_INT_CNTL,INREG(CRTC_INT_CNTL)|CRTC_BUSMASTER_EOL_INT|CRTC_BUSMASTER_EOL_INT_EN); + OUTREG(BUS_CNTL,(INREG(BUS_CNTL)|BUS_EXT_REG_EN|BUS_READ_BURST|BUS_PCI_READ_RETRY_EN) &(~BUS_MASTER_DIS)); + OUTREG(BM_SYSTEM_TABLE,ba_dma_desc|SYSTEM_TRIGGER_SYSTEM_TO_VIDEO); + if(__verbose > VERBOSE_LEVEL) mach64_vid_dump_regs(); + return 0; +} + + +int vixPlaybackCopyFrame( vidix_dma_t * dmai ) +{ + int retval; + if(!(dmai->flags & BM_DMA_FIXED_BUFFS)) if(bm_lock_mem(dmai->src,dmai->size) != 0) return errno; + retval = mach64_setup_frame(dmai); + VIRT_TO_CARD(mach64_dma_desc_base[dmai->idx],1,&bus_addr_dma_desc); + if(retval == 0) retval = mach64_transfer_frame(bus_addr_dma_desc); + if(!(dmai->flags & BM_DMA_FIXED_BUFFS)) bm_unlock_mem(dmai->src,dmai->size); + return retval; +} + +int vixQueryDMAStatus( void ) +{ + int bm_off; + bm_off = INREG(CRTC_INT_CNTL) & CRTC_BUSMASTER_EOL_INT; + return bm_off?0:1; +} +#endif diff --git a/src/video_out/vidix/drivers/mga_vid.c b/src/video_out/vidix/drivers/mga_vid.c index a5442bd0f..f34f5ed20 100644 --- a/src/video_out/vidix/drivers/mga_vid.c +++ b/src/video_out/vidix/drivers/mga_vid.c @@ -6,14 +6,11 @@ YUY2 support (see config.format) added by A'rpi/ESP-team double buffering added by A'rpi/ESP-team - Brightness/contrast support by Nick Kurshev + Brightness/contrast support by Nick Kurshev/Dariush Pietrzak (eyck) and me TODO: - * fix doublebuffering for vidix * fix memory size detection (current reading pci userconfig isn't working as requested - returns the max avail. ram on arch?) - * fix/complete brightness/contrast handling (Nick) - MGA users: please test this! (#define MGA_EQUALIZER) * translate all non-english comments to english */ @@ -38,7 +35,7 @@ //#define CRTC2 // Set this value, if autodetection fails! (video ram size in megabytes) -// #define MGA_MEMORY_SIZE 16 +//#define MGA_MEMORY_SIZE 16 /* No irq support in userspace implemented yet, do not enable this! */ /* disable irq */ @@ -46,11 +43,9 @@ #define MGA_VSYNC_POS 2 -#undef MGA_EQUALIZER - #undef MGA_PCICONFIG_MEMDETECT -#define MGA_DEFAULT_FRAMES 1 +#define MGA_DEFAULT_FRAMES 64 #include <errno.h> #include <stdio.h> @@ -113,20 +108,16 @@ static int mga_next_frame = 0; static vidix_capability_t mga_cap = { - "Matrox MGA G200/G400 YUV Video", + "Matrox MGA G200/G4x0/G5x0 YUV Video", "Aaron Holtzman, Arpad Gereoffy, Alex Beregszaszi, Nick Kurshev", TYPE_OUTPUT, { 0, 0, 0, 0 }, - 1600, /* 2048x2048 is supported if Pontscho is right */ - 1200, + 2048, + 2048, 4, 4, -1, - FLAG_UPSCALER | FLAG_DOWNSCALER -#ifdef MGA_EQUALIZER - | FLAG_EQUALIZER -#endif - , + FLAG_UPSCALER | FLAG_DOWNSCALER | FLAG_EQUALIZER, VENDOR_MATROX, -1, /* will be set in vixProbe */ { 0, 0, 0, 0} @@ -350,25 +341,22 @@ case 3: int vixPlaybackFrameSelect(unsigned int frame) { - printf("[mga] frameselect: %d\n", frame); + mga_next_frame = frame; + if (mga_verbose>1) printf("[mga] frameselect: %d\n", mga_next_frame); #if MGA_ALLOW_IRQ - if (mga_irq != -1) - { - mga_next_frame = frame; - } - else + if (mga_irq == -1) #endif { //we don't need the vcount protection as we're only hitting //one register (and it doesn't seem to be double buffered) - regs.besctl = (regs.besctl & ~0x07000000) + (frame << 25); + regs.besctl = (regs.besctl & ~0x07000000) + (mga_next_frame << 25); writel( regs.besctl, mga_mmio_base + BESCTL ); // writel( regs.besglobctl + ((readl(mga_mmio_base + VCOUNT)+2)<<16), writel( regs.besglobctl + (MGA_VSYNC_POS<<16), mga_mmio_base + BESGLOBCTL); #ifdef CRTC2 - crtc2_frame_sel(frame); + crtc2_frame_sel(mga_next_frame); #endif } @@ -545,15 +533,16 @@ if(!restore){ writel( regs.besglobctl + ((readl(mga_mmio_base + VCOUNT)+2)<<16), mga_mmio_base + BESGLOBCTL); -#if 0 - printf("[mga] wrote BES registers\n"); - printf("[mga] BESCTL = 0x%08x\n", + if (mga_verbose > 1) + { + printf("[mga] wrote BES registers\n"); + printf("[mga] BESCTL = 0x%08x\n", readl(mga_mmio_base + BESCTL)); - printf("[mga] BESGLOBCTL = 0x%08x\n", + printf("[mga] BESGLOBCTL = 0x%08x\n", readl(mga_mmio_base + BESGLOBCTL)); - printf("[mga] BESSTATUS= 0x%08x\n", + printf("[mga] BESSTATUS= 0x%08x\n", readl(mga_mmio_base + BESSTATUS)); -#endif + } #ifdef CRTC2 // printf("c2ctl:0x%08x c2datactl:0x%08x\n",readl(mga_mmio_base + C2CTL),readl(mga_mmio_base + C2DATACTL)); // printf("c2misc:0x%08x\n",readl(mga_mmio_base + C2MISC)); @@ -577,7 +566,7 @@ if(!restore){ // writel(cregs.c2vsync, mga_mmio_base + C2VSYNC); writel(cregs.c2misc, mga_mmio_base + C2MISC); - printf("c2offset = %d\n",cregs.c2offset); + if (mga_verbose > 1) printf("[mga] c2offset = %d\n",cregs.c2offset); writel(cregs.c2offset, mga_mmio_base + C2OFFSET); writel(cregs.c2startadd0, mga_mmio_base + C2STARTADD0); @@ -611,7 +600,7 @@ static void enable_irq(){ writeb(0x10, mga_mmio_base + CRTCD ); /* clear = 1 */ writel( regs.besglobctl , mga_mmio_base + BESGLOBCTL); - + return; } @@ -696,6 +685,7 @@ void mga_handle_irq(int irq, void *dev_id/*, struct pt_regs *pregs*/) { int vixConfigPlayback(vidix_playback_t *config) { + int i; int x, y, sw, sh, dw, dh; int besleft, bestop, ifactor, ofsleft, ofstop, baseadrofs, weight, weights; #ifdef CRTC2 @@ -716,13 +706,23 @@ int vixConfigPlayback(vidix_playback_t *config) unsigned int vtotal = vsyncend + upper_margin; #endif - if ((config->num_frames < 1) || (config->num_frames > 4)) + if ((config->num_frames < 1) || (config->num_frames > MGA_DEFAULT_FRAMES)) { printf("[mga] illegal num_frames: %d, setting to %d\n", config->num_frames, MGA_DEFAULT_FRAMES); config->num_frames = MGA_DEFAULT_FRAMES; -// return(EINVAL); } + for(;config->num_frames>0;config->num_frames--) + { + /*FIXME: this driver can use more frames but we need to apply + some tricks to avoid RGB-memory hits*/ + mga_src_base = ((mga_ram_size/2)*0x100000-config->num_frames*config->frame_size); + mga_src_base &= (~0xFFFF); /* 64k boundary */ + if(mga_src_base>=0) break; + } + if (mga_verbose > 1) printf("[mga] YUV buffer base: %p\n", mga_src_base); + + config->dga_addr = mga_mem_base + mga_src_base; x = config->dest.x; y = config->dest.y; @@ -734,7 +734,7 @@ int vixConfigPlayback(vidix_playback_t *config) config->dest.pitch.y=32; config->dest.pitch.u=config->dest.pitch.v=16; - printf("[mga] Setting up a %dx%d+%d+%d video window (src %dx%d) format %X\n", + if (mga_verbose) printf("[mga] Setting up a %dx%d-%dx%d video window (src %dx%d) format %X\n", dw, dh, x, y, sw, sh, config->fourcc); if ((sw < 4) || (sh < 4) || (dw < 4) || (dh < 4)) @@ -746,21 +746,14 @@ int vixConfigPlayback(vidix_playback_t *config) //FIXME check that window is valid and inside desktop // printf("[mga] vcount = %d\n", readl(mga_mmio_base + VCOUNT)); - - config->offsets[0] = 0; - config->offsets[1] = config->frame_size; - config->offsets[2] = 2*config->frame_size; - config->offsets[3] = 3*config->frame_size; - - config->offset.y=0; - config->offset.v=((sw + 31) & ~31) * sh; - config->offset.u=config->offset.v+((sw + 31) & ~31) * sh /4; + sw+=sw&1; switch(config->fourcc) { case IMGFMT_I420: case IMGFMT_IYUV: case IMGFMT_YV12: + sh+=sh&1; config->frame_size = ((sw + 31) & ~31) * sh + (((sw + 31) & ~31) * sh) / 2; break; case IMGFMT_YUY2: @@ -772,23 +765,22 @@ int vixConfigPlayback(vidix_playback_t *config) return(ENOTSUP); } -// config->frame_size = config->src.h*config->src.w+(config->src.w*config->src.h)/2; + config->offsets[0] = 0; +// config->offsets[1] = config->frame_size; +// config->offsets[2] = 2*config->frame_size; +// config->offsets[3] = 3*config->frame_size; + for (i = 1; i < config->num_frames+1; i++) + config->offsets[i] = i*config->frame_size; + + config->offset.y=0; + config->offset.v=((sw + 31) & ~31) * sh; + config->offset.u=config->offset.v+((sw + 31) & ~31) * sh /4; //FIXME figure out a better way to allocate memory on card //allocate 2 megs //mga_src_base = mga_mem_base + (MGA_VIDMEM_SIZE-2) * 0x100000; //mga_src_base = (MGA_VIDMEM_SIZE-3) * 0x100000; - mga_src_base = (mga_ram_size*0x100000-config->num_frames*config->frame_size); - if (mga_src_base < 0) - { - printf("[mga] not enough memory for frames!\n"); - return(EFAULT); - } - mga_src_base &= (~0xFFFF); /* 64k boundary */ - printf("[mga] YUV buffer base: %p\n", mga_src_base); - - config->dga_addr = mga_mem_base + mga_src_base; /* for G200 set Interleaved UV planes */ if (!is_g400) @@ -852,7 +844,6 @@ int vixConfigPlayback(vidix_playback_t *config) } - //Disable contrast and brightness control regs.besglobctl |= (1<<5) + (1<<7); regs.beslumactl = (0x7f << 16) + (0x80<<0); @@ -1144,7 +1135,7 @@ switch(config->fourcc){ int vixPlaybackOn(void) { - printf("[mga] playback on\n"); + if (mga_verbose) printf("[mga] playback on\n"); vid_src_ready = 1; if(vid_overlay_on) @@ -1163,7 +1154,7 @@ int vixPlaybackOn(void) int vixPlaybackOff(void) { - printf("[mga] playback off\n"); + if (mga_verbose) printf("[mga] playback off\n"); vid_src_ready = 0; #ifdef MGA_ALLOW_IRQ @@ -1183,7 +1174,7 @@ int vixProbe(int verbose,int force) unsigned int i, num_pci; int err; - printf("[mga] probe\n"); + if (verbose) printf("[mga] probe\n"); mga_verbose = verbose; @@ -1196,12 +1187,12 @@ int vixProbe(int verbose,int force) return(err); } - if (mga_verbose > 1) + if (mga_verbose) printf("[mga] found %d pci devices\n", num_pci); for (i = 0; i < num_pci; i++) { - if (mga_verbose > 2) + if (mga_verbose > 1) printf("[mga] pci[%d] vendor: %d device: %d\n", i, lst[i].vendor, lst[i].device); if (lst[i].vendor == VENDOR_MATROX) @@ -1247,11 +1238,15 @@ int vixInit(void) { unsigned int card_option = 0; int err; - printf("[mga] init\n"); + + if (mga_verbose) printf("[mga] init\n"); mga_vid_in_use = 0; printf("Matrox MGA G200/G400/G450 YUV Video interface v2.01 (c) Aaron Holtzman & A'rpi\n"); +#ifdef CRCT2 + printf("Driver compiled with TV-out (second-head) support\n"); +#endif if (!probed) { @@ -1262,12 +1257,10 @@ int vixInit(void) #ifdef MGA_PCICONFIG_MEMDETECT pci_config_read(pci_info.bus, pci_info.card, pci_info.func, 0x40, 4, &card_option); - printf("[mga] OPTION word: 0x%08X mem: 0x%02X %s\n", card_option, + if (mga_verbose > 1) printf("[mga] OPTION word: 0x%08X mem: 0x%02X %s\n", card_option, (card_option>>10)&0x17, ((card_option>>14)&1)?"SGRAM":"SDRAM"); #endif -// temp = (card_option >> 10) & 0x17; - if (mga_ram_size) { printf("[mga] RAMSIZE forced to %d MB\n", mga_ram_size); @@ -1333,13 +1326,13 @@ int vixInit(void) } } - printf("[mga] hardware addresses: mmio: %p, framebuffer: %p\n", + if (mga_verbose > 1) printf("[mga] hardware addresses: mmio: %p, framebuffer: %p\n", pci_info.base1, pci_info.base0); mga_mmio_base = map_phys_mem(pci_info.base1,0x4000); mga_mem_base = map_phys_mem(pci_info.base0,mga_ram_size*1024*1024); - printf("[mga] MMIO at %p, IRQ: %d, framebuffer: %p\n", + if (mga_verbose > 1) printf("[mga] MMIO at %p, IRQ: %d, framebuffer: %p\n", mga_mmio_base, mga_irq, mga_mem_base); err = mtrr_set_type(pci_info.base0,mga_ram_size*1024*1024,MTRR_TYPE_WRCOMB); if(!err) printf("[mga] Set write-combining type of video memory\n"); @@ -1372,8 +1365,9 @@ int vixInit(void) void vixDestroy(void) { - printf("[mga] destroy\n"); + if (mga_verbose) printf("[mga] destroy\n"); + /* FIXME turn off BES */ vid_src_ready = 0; regs.besctl &= ~1; regs.besglobctl &= ~(1<<6); // UYVY format selected @@ -1390,29 +1384,35 @@ void vixDestroy(void) unmap_phys_mem(mga_mmio_base, 0x4000); if (mga_mem_base) unmap_phys_mem(mga_mem_base, mga_ram_size); - - /* FIXME turn off BES */ - return; } int vixQueryFourcc(vidix_fourcc_t *to) { - printf("[mga] query fourcc (%x)\n", to->fourcc); + int supports=0; + if (mga_verbose) printf("[mga] query fourcc (%x)\n", to->fourcc); switch(to->fourcc) { case IMGFMT_YV12: case IMGFMT_IYUV: case IMGFMT_I420: + supports = is_g400 ? 1 : 0; + case IMGFMT_NV12: + supports = is_g400 ? 0 : 1; case IMGFMT_YUY2: case IMGFMT_UYVY: + supports = 1; break; default: - to->depth = to->flags = 0; - return(ENOTSUP); + supports = 0; } + if(!supports) + { + to->depth = to->flags = 0; + return(ENOTSUP); + } to->depth = VID_DEPTH_12BPP | VID_DEPTH_15BPP | VID_DEPTH_16BPP | VID_DEPTH_24BPP | VID_DEPTH_32BPP; @@ -1443,46 +1443,47 @@ int vixSetGrKeys(const vidix_grkey_t *grkey) return(0); } -#ifdef MGA_EQUALIZER -static vidix_video_eq_t equal = +int vixPlaybackSetEq( const vidix_video_eq_t * eq) { - VEQ_CAP_BRIGHTNESS | VEQ_CAP_CONTRAST, - 0, 0, 0, 0, 0, 0, 0, 0 }; -int vixPlaybackSetEq( const vidix_video_eq_t * eq) -{ - uint32_t beslumactl; - int brightness,contrast; + uint32_t luma = 0; + float factor = 256.0 / 2000; - /* contrast and brightness control isn't supported with G200, - don't enable c/b control and set values, just return error -- alex */ + /* contrast and brightness control isn't supported on G200 - alex */ if (!is_g400) { - if (mga_verbose > 1) - printf("[mga] equalizer isn't supported with G200\n"); - return ENOSYS; + if (mga_verbose) printf("[mga] equalizer isn't supported with G200\n"); + return(ENOTSUP); } + + if (eq->cap & VEQ_CAP_BRIGHTNESS) + luma += ((int)(eq->brightness * factor) << 16); + if (eq->cap & VEQ_CAP_CONTRAST) + luma += ((int)(eq->contrast * factor) & 0xFFFF); + + regs.beslumactl = luma+0x80; - if(eq->cap & VEQ_CAP_BRIGHTNESS) equal.brightness = eq->brightness; - if(eq->cap & VEQ_CAP_CONTRAST) equal.contrast = eq->contrast; - equal.flags = eq->flags; - - //Enable contrast and brightness control - writel(readl(mga_mmio_base + BESGLOBCTL) & ~((1<<5) + (1<<7)),mga_mmio_base + BESGLOBCTL); - brightness = (equal.brightness * 128) / 1000; - if(brightness < -128) brightness = -128; - if(brightness > 127) brightness = 127; - contrast = ((equal.contrast + 1000) * 128) / 1000; - if(contrast < 0) contrast = 0; - if(contrast > 255) contrast = 255; - beslumactl = ((brightness & 0xff) << 16) | (contrast & 0xff); - - writel(beslumactl,mga_mmio_base + BESLUMACTL); - return 0; + writel(regs.beslumactl,mga_mmio_base + BESLUMACTL); + return(0); } -int vixPlaybackGetEq( vidix_video_eq_t * eq) +int vixPlaybackGetEq( vidix_video_eq_t * eq) { - memcpy(eq,&equal,sizeof(vidix_video_eq_t)); - return 0; + uint32_t luma; + float factor = 2000.0 / 256; + + /* contrast and brightness control isn't supported on G200 - alex */ + if (!is_g400) + { + if (mga_verbose) printf("[mga] equalizer isn't supported with G200\n"); + return(ENOTSUP); + } + + regs.beslumactl = readl(mga_mmio_base + BESLUMACTL); + luma = regs.beslumactl-0x80; + + eq->brightness = (luma >> 16) * factor; + eq->contrast = (luma & 0xFFFF) * factor; + eq->cap = VEQ_CAP_BRIGHTNESS | VEQ_CAP_CONTRAST; + + return(0); } -#endif diff --git a/src/video_out/vidix/drivers/nvidia_vid.c b/src/video_out/vidix/drivers/nvidia_vid.c index 941011256..0a639e93a 100644 --- a/src/video_out/vidix/drivers/nvidia_vid.c +++ b/src/video_out/vidix/drivers/nvidia_vid.c @@ -27,6 +27,8 @@ static unsigned int *PMC; typedef unsigned char U008; +#define NVIDIA_MSG "[nvidia-unworking-driver] " + #define NV_WR08(p,i,d) (((U008 *)(p))[i]=(d)) unsigned int nv_fifo_space = 0; @@ -102,12 +104,12 @@ int vixProbe(int verbose,int force) unsigned int i, num_pci; int err; - printf("[nvidia] probe\n"); + printf(NVIDIA_MSG"probe\n"); err = pci_scan(lst, &num_pci); if (err) { - printf("Error occured during pci scan: %s\n", strerror(err)); + printf(NVIDIA_MSG"Error occured during pci scan: %s\n", strerror(err)); return err; } else @@ -125,13 +127,13 @@ int vixProbe(int verbose,int force) continue; if (nv_card_ids[idx].flags & CARD_FLAGS_NOTSUPPORTED) { - printf("Found chip: %s, but not supported!\n", + printf(NVIDIA_MSG"Found chip: %s, but not supported!\n", nv_card_ids[idx].name); continue; } else - printf("Found chip: %s\n", nv_card_ids[idx].name); + printf(NVIDIA_MSG"Found chip: %s\n", nv_card_ids[idx].name); memcpy(&nv_card_id, &nv_card_ids[idx], sizeof(struct nv_card_id_s)); nvidia_cap.device_id = nv_card_ids[idx].id; @@ -139,11 +141,11 @@ int vixProbe(int verbose,int force) memcpy(&pci_info, &lst[i], sizeof(pciinfo_t)); probed = 1; - printf("bus:card:func = %x:%x:%x\n", + printf(NVIDIA_MSG"bus:card:func = %x:%x:%x\n", pci_info.bus, pci_info.card, pci_info.func); - printf("vendor:device = %x:%x\n", + printf(NVIDIA_MSG"vendor:device = %x:%x\n", pci_info.vendor, pci_info.device); - printf("base0:base1:base2:baserom = %x:%x:%x:%x\n", + printf(NVIDIA_MSG"base0:base1:base2:baserom = %x:%x:%x:%x\n", pci_info.base0, pci_info.base1, pci_info.base2, pci_info.baserom); break; @@ -152,7 +154,7 @@ int vixProbe(int verbose,int force) } if (err) - printf("No chip found\n"); + printf(NVIDIA_MSG"No chip found\n"); return(err); } @@ -160,15 +162,15 @@ int vixInit(void) { int card_option; - printf("[nvidia] init\n"); + printf(NVIDIA_MSG"init\n"); pci_config_read(pci_info.bus, pci_info.card, pci_info.func, 0x40, 4, &card_option); - printf("card_option: %x\n", card_option); + printf(NVIDIA_MSG"card_option: %x\n", card_option); if (!probed) { - printf("Driver was not probed but is being initialized\n"); + printf(NVIDIA_MSG"Driver was not probed but is being initialized\n"); return(EINTR); } @@ -179,7 +181,7 @@ int vixInit(void) if (fb_base == (void *)-1) return(ENOMEM); - printf("ctrl_base: %p, fb_base: %p\n", ctrl_base, fb_base); + printf(NVIDIA_MSG"ctrl_base: %p, fb_base: %p\n", ctrl_base, fb_base); PFB = ctrl_base+0x00100000; PGRAPH = ctrl_base+0x00400000; @@ -187,16 +189,16 @@ int vixInit(void) FIFO = ctrl_base+0x00800000; PCIO = ctrl_base+0x00601000; PMC = ctrl_base+0x00000000; - printf("pfb: %p, pgraph: %p, pramin: %p, fifo: %p, pcio: %p\n", + printf(NVIDIA_MSG"pfb: %p, pgraph: %p, pramin: %p, fifo: %p, pcio: %p\n", PFB, PGRAPH, PRAMIN, FIFO, PCIO); ScaledImage = FIFO+0x8000/4; - printf("ScaledImage: %p\n", ScaledImage); + printf(NVIDIA_MSG"ScaledImage: %p\n", ScaledImage); /* unlock */ CRTCout(0x11, 0xff); - printf("fifo_free: %d\n", ScaledImage->fifo_free); + printf(NVIDIA_MSG"fifo_free: %d\n", ScaledImage->fifo_free); RIVA_FIFO_FREE(ScaledImage, 10); @@ -216,7 +218,7 @@ int vixInit(void) { if (*(PFB+0x0) & 0x00000100) { - printf("first ver\n"); + printf(NVIDIA_MSG"first ver\n"); ram_size = ((*(PFB+0x0) >> 12) & 0x0f) * 1024 * 2 + 1024 * 2; } else @@ -238,7 +240,7 @@ int vixInit(void) ram_size = 1024*16; break; default: - printf("Unknown ram size code: %d\n", + printf(NVIDIA_MSG"Unknown ram size code: %d\n", *(PFB+0x0) & 0x00000003); break; } @@ -246,16 +248,16 @@ int vixInit(void) break; } default: - printf("Unknown core: %d\n", nv_card_id.core); + printf(NVIDIA_MSG"Unknown core: %d\n", nv_card_id.core); } - printf("ram_size: %d\n", ram_size); + printf(NVIDIA_MSG"ram_size: %d\n", ram_size); return 0; } void vixDestroy(void) { - printf("[nvidia] destory\n"); + printf(NVIDIA_MSG"destory\n"); } int vixGetCapability(vidix_capability_t *to) @@ -266,7 +268,7 @@ int vixGetCapability(vidix_capability_t *to) int vixQueryFourcc(vidix_fourcc_t *to) { - printf("[nvidia] query fourcc (%x)\n", to->fourcc); + printf(NVIDIA_MSG"query fourcc (%x)\n", to->fourcc); to->flags = 0; to->depth = VID_DEPTH_32BPP; return 0; @@ -282,7 +284,7 @@ int vixConfigPlayback(vidix_playback_t *info) int bpp = 32 >> 3; int size; - printf("[nvidia] config playback\n"); + printf(NVIDIA_MSG"config playback\n"); x = info->src.x; y = info->src.y; @@ -315,12 +317,12 @@ int vixConfigPlayback(vidix_playback_t *info) int vixPlaybackOn(void) { - printf("[nvidia] playback on\n"); + printf(NVIDIA_MSG"playback on\n"); return 0; } int vixPlaybackOff(void) { - printf("[nvidia] playback off\n"); + printf(NVIDIA_MSG"playback off\n"); return 0; } diff --git a/src/video_out/vidix/drivers/pm3_regs.h b/src/video_out/vidix/drivers/pm3_regs.h index c976c3210..98f9b718a 100644 --- a/src/video_out/vidix/drivers/pm3_regs.h +++ b/src/video_out/vidix/drivers/pm3_regs.h @@ -80,8 +80,16 @@ #define PM3ByApertureMode_DOUBLE_WRITE_8MB (4<<22) #define PM3ByApertureMode_DOUBLE_WRITE_16MB (5<<22) #define PM3ByApertureMode_DOUBLE_WRITE_32MB (6<<22) +#define PM3Aperture1Stride 0x0308 +#define PM3Aperture1YStart 0x0310 +#define PM3Aperture1UStart 0x0318 +#define PM3Aperture1VStart 0x0320 #define PM3ByAperture2Mode 0x0328 +#define PM3Aperture2Stride 0x0330 +#define PM3Aperture2YStart 0x0338 +#define PM3Aperture2UStart 0x0340 +#define PM3Aperture2VStart 0x0348 /********************************************** * GLINT Permedia3 Memory Control (0x1000) * diff --git a/src/video_out/vidix/drivers/pm3_vid.c b/src/video_out/vidix/drivers/pm3_vid.c index 73c30c543..2078113cc 100644 --- a/src/video_out/vidix/drivers/pm3_vid.c +++ b/src/video_out/vidix/drivers/pm3_vid.c @@ -34,6 +34,9 @@ #include "pm3_regs.h" +/* MBytes of video memory to use */ +#define PM3_VIDMEM 24 + #if 0 #define TRACE_ENTER() fprintf(stderr, "%s: enter\n", __FUNCTION__) #define TRACE_EXIT() fprintf(stderr, "%s: exit\n", __FUNCTION__) @@ -47,6 +50,8 @@ pciinfo_t pci_info; void *pm3_reg_base; void *pm3_mem; +int pm3_vidmem = PM3_VIDMEM; + static vidix_capability_t pm3_cap = { "3DLabs GLINT R3/Permedia3 driver", @@ -131,8 +136,12 @@ int vixProbe(int verbose, int force) int vixInit(void) { + char *vm; pm3_reg_base = map_phys_mem(pci_info.base0, 0x20000); - pm3_mem = map_phys_mem(pci_info.base2, 0x2000000); + pm3_mem = map_phys_mem(pci_info.base1, 0x2000000); + if((vm = getenv("PM3_VIDMEM"))){ + pm3_vidmem = strtol(vm, NULL, 0); + } return 0; } @@ -235,9 +244,6 @@ int vixConfigPlayback(vidix_playback_t *info) TRACE_ENTER(); - if(!is_supported_fourcc(info->fourcc)) - return -1; - switch(info->fourcc){ case IMGFMT_YUY2: format = FORMAT_YUV422; @@ -257,22 +263,31 @@ int vixConfigPlayback(vidix_playback_t *info) pitch = src_w; - /* Assume we have 16 MB to play with */ - info->num_frames = 0x1000000 / (pitch * src_h * 2); + info->num_frames = pm3_vidmem*1024*1024 / (pitch * src_h * 2); if(info->num_frames > VID_PLAY_MAXFRAMES) info->num_frames = VID_PLAY_MAXFRAMES; - /* Start at 16 MB. Let's hope it's not in use. */ - base0 = 0x1000000; + /* Use end of video memory. Assume the card has 32 MB */ + base0 = (32-pm3_vidmem)*1024*1024; info->dga_addr = pm3_mem + base0; - info->dest.pitch.y = 2; - info->dest.pitch.u = 0; - info->dest.pitch.v = 0; - info->offset.y = 0; - info->offset.v = 0; - info->offset.u = 0; + if(info->fourcc == IMGFMT_YV12){ + info->dest.pitch.y = 2; + info->dest.pitch.u = 2; + info->dest.pitch.y = 2; + info->offset.y = 0; + info->offset.v = src_w * src_h; + info->offset.u = src_w * src_h * 3/2; + } else { + info->dest.pitch.y = 2; + info->dest.pitch.u = 0; + info->dest.pitch.v = 0; + info->offset.y = 0; + info->offset.v = 0; + info->offset.u = 0; + } info->frame_size = pitch * src_h * 2; + for(i = 0; i < info->num_frames; i++){ info->offsets[i] = info->frame_size * i; frames[i] = (base0 + info->offsets[i]) >> 1; @@ -280,6 +295,20 @@ int vixConfigPlayback(vidix_playback_t *info) compute_scale_factor(&src_w, &drw_w, &shrink, &zoom); +#if 0 + aperture_mode = READ_REG(PM3ByAperture1Mode); + if(info->fourcc == IMGFMT_YV12){ +/* WRITE_REG(PM3Aperture0, base0 >> 1); */ + WRITE_REG(PM3ByAperture1Mode, + PM3ByApertureMode_FORMAT_YUYV | + PM3ByApertureMode_PIXELSIZE_32BIT); + WRITE_REG(PM3Aperture1Stride, pitch); + WRITE_REG(PM3Aperture1YStart, base0 / 16); + WRITE_REG(PM3Aperture1VStart, (base0 + info->offset.v) / 16); + WRITE_REG(PM3Aperture1UStart, (base0 + info->offset.u) / 16); + } +#endif + WRITE_REG(PM3VideoOverlayBase0, base0 >> 1); WRITE_REG(PM3VideoOverlayStride, PM3VideoOverlayStride_STRIDE(pitch)); WRITE_REG(PM3VideoOverlayWidth, PM3VideoOverlayWidth_WIDTH(src_w)); @@ -327,7 +356,7 @@ int vixConfigPlayback(vidix_playback_t *info) overlay_control = PM3RD_VideoOverlayControl_KEY_COLOR | - PM3RD_VideoOverlayControl_MODE_MAINKEY | + PM3RD_VideoOverlayControl_MODE_OVERLAYKEY | PM3RD_VideoOverlayControl_DIRECTCOLOR_ENABLED; TRACE_EXIT(); @@ -366,5 +395,6 @@ int vixPlaybackOff(void) int vixPlaybackFrameSelect(unsigned int frame) { WRITE_REG(PM3VideoOverlayBase0, frames[frame]); +/* WRITE_REG(PM3Aperture0, frames[frame]); */ return 0; } diff --git a/src/video_out/vidix/drivers/radeon.h b/src/video_out/vidix/drivers/radeon.h index 6093356c1..82ab7a895 100644 --- a/src/video_out/vidix/drivers/radeon.h +++ b/src/video_out/vidix/drivers/radeon.h @@ -148,13 +148,23 @@ #define AIC_TLB_DATA 0x01E8 #define DAC_CNTL 0x0058 /* DAC_CNTL bit constants */ +# define DAC_RANGE_CNTL_MSK 0x00000003 +# define DAC_RANGE_PAL 0x00000000 +# define DAC_RANGE_NTSC 0x00000001 +# define DAC_RANGE_PS2 0x00000002 +# define DAC_BLANKING 0x00000004 +# define DAC_CMP_EN 0x00000008 +# define DAC_CMP_OUTPUT 0x00000080 # define DAC_8BIT_EN 0x00000100 # define DAC_4BPP_PIX_ORDER 0x00000200 +# define DAC_TVO_EN 0x00000400 +# define DAC_TVO_OVR_EXCL 0x00000800 +# define DAC_TVO_16BPP_DITH_EN 0x00001000 +# define DAC_VGA_ADR_EN (1 << 13) +# define DAC_PWDN (1 << 15) # define DAC_CRC_EN 0x00080000 # define DAC_MASK_ALL (0xff << 24) -# define DAC_VGA_ADR_EN (1 << 13) # define DAC_RANGE_CNTL (3 << 0) -# define DAC_BLANKING (1 << 2) #define DAC_CNTL2 0x007c /* DAC_CNTL2 bit constants */ # define DAC2_DAC_CLK_SEL (1 << 0) @@ -284,6 +294,19 @@ # define CRTC_DISPLAY_DIS_BYTE (1 << 2) #define RB3D_CNTL 0x1C3C #define WAIT_UNTIL 0x1720 +# define EVENT_CRTC_OFFSET 0x00000001 +# define EVENT_RE_CRTC_VLINE 0x00000002 +# define EVENT_FE_CRTC_VLINE 0x00000004 +# define EVENT_CRTC_VLINE 0x00000008 +# define EVENT_BM_VIP0_IDLE 0x00000010 +# define EVENT_BM_VIP1_IDLE 0x00000020 +# define EVENT_BM_VIP2_IDLE 0x00000040 +# define EVENT_BM_VIP3_IDLE 0x00000080 +# define EVENT_BM_VIDCAP_IDLE 0x00000100 +# define EVENT_BM_GUI_IDLE 0x00000200 +# define EVENT_CMDFIFO 0x00000400 +# define EVENT_OV0_FLIP 0x00000800 +# define EVENT_CMDFIFO_ENTRIES 0x07F00000 #define ISYNC_CNTL 0x1724 #define RBBM_GUICNTL 0x172C #define RBBM_STATUS 0x0E40 @@ -735,6 +758,12 @@ # define CMP_MIX_OR 0x00000000L # define CMP_MIX_AND 0x00000100L #define OV0_TEST 0x04F8 +#define OV0_COL_CONV 0x04FC +# define OV0_CB_TO_B 0x0000007FL +# define OV0_CB_TO_G 0x0000FF00L +# define OV0_CR_TO_G 0x00FF0000L +# define OV0_CR_TO_R 0x7F000000L +# define OV0_NEW_COL_CONV 0x80000000L #define OV0_LIN_TRANS_A 0x0D20 #define OV0_LIN_TRANS_B 0x0D24 #define OV0_LIN_TRANS_C 0x0D28 @@ -774,9 +803,25 @@ #define IDCT_CONTROL 0x1FBC #define SE_MC_SRC2_CNTL 0x19D4 +# define SECONDARY_SCALE_HACC 0x00001FFFL +# define SECONDARY_SCALE_VACC 0x0FFF0000L +# define SECONDARY_SCALE_PICTH_ADJ 0xC0000000L #define SE_MC_SRC1_CNTL 0x19D8 +# define SCALE_HACC 0x00001FFFL +# define SCALE_VACC 0x0FFF0000L +# define IDCT_EN 0x10000000L +# define SECONDARY_TEX_EN 0x20000000L +# define SCALE_PICTH_ADJ 0xC0000000L #define SE_MC_DST_CNTL 0x19DC +# define DST_Y 0x00003FFFL +# define DST_X 0x3FFF0000L +# define DST_PITCH_ADJ 0xC0000000L #define SE_MC_CNTL_START 0x19E0 +# define SCALE_OFFSET_PTR 0x0000000FL +# define DST_OFFSET 0x00FFFFF0L +# define ALPHA_EN 0x01000000L +# define SECONDARY_OFFSET_PTR 0x1E000000L +# define MC_DST_HEIGHT_WIDTH 0xE0000000L #ifndef RAGE128 #define SE_MC_BUF_BASE 0x19E4 #define PP_MC_CONTEXT 0x19E8 @@ -817,6 +862,7 @@ #define CP_CSQ_CNTL 0x0740 #define SCRATCH_UMSK 0x0770 #define SCRATCH_ADDR 0x0774 +#ifndef RAGE128 #define DMA_GUI_TABLE_ADDR 0x0780 # define DMA_GUI_COMMAND__BYTE_COUNT_MASK 0x001fffff # define DMA_GUI_COMMAND__INTDIS 0x40000000 @@ -832,6 +878,7 @@ #define DMA_VID_COMMAND 0x07AC #define DMA_VID_STATUS 0x07B0 #define DMA_VID_ACT_DSCRPTR 0x07B4 +#endif #define CP_ME_CNTL 0x07D0 #define CP_ME_RAM_ADDR 0x07D4 #define CP_ME_RAM_RADDR 0x07D8 @@ -1031,6 +1078,20 @@ #ifdef RAGE128 #define GUI_STAT 0x1740 # define GUI_FIFOCNT_MASK 0x0fff +# define PM4_BUSY (1 << 16) +# define MICRO_BUSY (1 << 17) +# define FPU_BUSY (1 << 18) +# define VC_BUSY (1 << 19) +# define IDCT_BUSY (1 << 20) +# define ENG_EV_BUSY (1 << 21) +# define SETUP_BUSY (1 << 22) +# define EDGE_WALK_BUSY (1 << 23) +# define ADDRESSING_BUSY (1 << 24) +# define ENG_3D_BUSY (1 << 25) +# define ENG_2D_SM_BUSY (1 << 26) +# define ENG_2D_BUSY (1 << 27) +# define GUI_WB_BUSY (1 << 28) +# define CACHE_BUSY (1 << 29) # define GUI_ACTIVE (1 << 31) #endif #define SRC_CLUT_ADDRESS 0x1780 @@ -1211,7 +1272,7 @@ #define RB2D_DSTCACHE_CTLSTAT 0x342C #define RB2D_DSTCACHE_MODE 0x3428 -#define BASE_CODE 0x0f0b +#define BASE_CODE 0x0f0b/*0x0f08*/ #define RADEON_BIOS_0_SCRATCH 0x0010 #define RADEON_BIOS_1_SCRATCH 0x0014 #define RADEON_BIOS_2_SCRATCH 0x0018 @@ -1303,6 +1364,7 @@ #define PPLL_POST3_DIV_MASK 0x00070000 /* BUS MASTERING */ +#ifdef RAGE128 #define BM_FRAME_BUF_OFFSET 0xA00 #define BM_SYSTEM_MEM_ADDR 0xA04 #define BM_COMMAND 0xA08 @@ -1338,7 +1400,8 @@ #define BM_VIDCAP_BUF2 0xA68 #define BM_VIDCAP_ACTIVE 0xA6c #define BM_GUI 0xA80 - +#define BM_ABORT 0xA88 +#endif /* RAGE THEATER REGISTERS */ #define DMA_VIPH0_COMMAND 0x0A00 diff --git a/src/video_out/vidix/drivers/radeon_vid.c b/src/video_out/vidix/drivers/radeon_vid.c index 1393a49e5..ed5a4ee41 100644 --- a/src/video_out/vidix/drivers/radeon_vid.c +++ b/src/video_out/vidix/drivers/radeon_vid.c @@ -11,6 +11,7 @@ #include <string.h> #include <math.h> #include <inttypes.h> +#include <sys/mman.h> #include "../../libdha/pci_ids.h" #include "../../libdha/pci_names.h" #include "../vidix.h" @@ -29,6 +30,25 @@ #endif #endif +//#undef RADEON_ENABLE_BM /* unfinished stuff. May corrupt your filesystem ever */ +#define RADEON_ENABLE_BM 1 + +#ifdef RADEON_ENABLE_BM +static void * radeon_dma_desc_base = 0; +static unsigned long bus_addr_dma_desc = 0; +static unsigned long *dma_phys_addrs = 0; +#pragma pack(1) +typedef struct +{ + uint32_t framebuf_offset; + uint32_t sys_addr; + uint32_t command; + uint32_t reserved; +} bm_list_descriptor; +#pragma pack() +#endif + +#define VERBOSE_LEVEL 0 static int __verbose = 0; typedef struct bes_registers_s @@ -187,7 +207,43 @@ static video_registers_t vregs[] = DECLARE_VREG(IDCT_LEVELS), DECLARE_VREG(IDCT_AUTH_CONTROL), DECLARE_VREG(IDCT_AUTH), - DECLARE_VREG(IDCT_CONTROL) + DECLARE_VREG(IDCT_CONTROL), +#ifdef RAGE128 + DECLARE_VREG(BM_FRAME_BUF_OFFSET), + DECLARE_VREG(BM_SYSTEM_MEM_ADDR), + DECLARE_VREG(BM_COMMAND), + DECLARE_VREG(BM_STATUS), + DECLARE_VREG(BM_QUEUE_STATUS), + DECLARE_VREG(BM_QUEUE_FREE_STATUS), + DECLARE_VREG(BM_CHUNK_0_VAL), + DECLARE_VREG(BM_CHUNK_1_VAL), + DECLARE_VREG(BM_VIP0_BUF), + DECLARE_VREG(BM_VIP0_ACTIVE), + DECLARE_VREG(BM_VIP1_BUF), + DECLARE_VREG(BM_VIP1_ACTIVE), + DECLARE_VREG(BM_VIP2_BUF), + DECLARE_VREG(BM_VIP2_ACTIVE), + DECLARE_VREG(BM_VIP3_BUF), + DECLARE_VREG(BM_VIP3_ACTIVE), + DECLARE_VREG(BM_VIDCAP_BUF0), + DECLARE_VREG(BM_VIDCAP_BUF1), + DECLARE_VREG(BM_VIDCAP_BUF2), + DECLARE_VREG(BM_VIDCAP_ACTIVE), + DECLARE_VREG(BM_GUI), + DECLARE_VREG(BM_ABORT) +#else + DECLARE_VREG(DMA_GUI_TABLE_ADDR), + DECLARE_VREG(DMA_GUI_SRC_ADDR), + DECLARE_VREG(DMA_GUI_DST_ADDR), + DECLARE_VREG(DMA_GUI_COMMAND), + DECLARE_VREG(DMA_GUI_STATUS), + DECLARE_VREG(DMA_GUI_ACT_DSCRPTR), + DECLARE_VREG(DMA_VID_SRC_ADDR), + DECLARE_VREG(DMA_VID_DST_ADDR), + DECLARE_VREG(DMA_VID_COMMAND), + DECLARE_VREG(DMA_VID_STATUS), + DECLARE_VREG(DMA_VID_ACT_DSCRPTR), +#endif }; static void * radeon_mmio_base = 0; @@ -906,6 +962,84 @@ int vixProbe( int verbose,int force ) return err; } +#ifndef RAGE128 +enum radeon_montype +{ + MT_NONE, + MT_CRT, /* CRT-(cathode ray tube) analog monitor. (15-pin VGA connector) */ + MT_LCD, /* Liquid Crystal Display */ + MT_DFP, /* DFP-digital flat panel monitor. (24-pin DVI-I connector) */ + MT_CTV, /* Composite TV out (not in VE) */ + MT_STV /* S-Video TV out (probably in VE only) */ +}; + +typedef struct radeon_info_s +{ + int hasCRTC2; + int crtDispType; + int dviDispType; +}rinfo_t; + +static rinfo_t rinfo; + +static char * GET_MON_NAME(int type) +{ + char *pret; + switch(type) + { + case MT_NONE: pret = "no"; break; + case MT_CRT: pret = "CRT"; break; + case MT_DFP: pret = "DFP"; break; + case MT_LCD: pret = "LCD"; break; + case MT_CTV: pret = "CTV"; break; + case MT_STV: pret = "STV"; break; + default: pret = "Unknown"; + } + return pret; +} + +static void radeon_get_moninfo (rinfo_t *rinfo) +{ + unsigned int tmp; + + tmp = INREG(RADEON_BIOS_4_SCRATCH); + + if (rinfo->hasCRTC2) { + /* primary DVI port */ + if (tmp & 0x08) + rinfo->dviDispType = MT_DFP; + else if (tmp & 0x4) + rinfo->dviDispType = MT_LCD; + else if (tmp & 0x200) + rinfo->dviDispType = MT_CRT; + else if (tmp & 0x10) + rinfo->dviDispType = MT_CTV; + else if (tmp & 0x20) + rinfo->dviDispType = MT_STV; + + /* secondary CRT port */ + if (tmp & 0x2) + rinfo->crtDispType = MT_CRT; + else if (tmp & 0x800) + rinfo->crtDispType = MT_DFP; + else if (tmp & 0x400) + rinfo->crtDispType = MT_LCD; + else if (tmp & 0x1000) + rinfo->crtDispType = MT_CTV; + else if (tmp & 0x2000) + rinfo->crtDispType = MT_STV; + } else { + rinfo->dviDispType = MT_NONE; + + tmp = INREG(FP_GEN_CNTL); + + if (tmp & FP_EN_TMDS) + rinfo->crtDispType = MT_DFP; + else + rinfo->crtDispType = MT_CRT; + } +} +#endif int vixInit( void ) { int err; @@ -924,6 +1058,43 @@ int vixInit( void ) printf(RADEON_MSG" Video memory = %uMb\n",radeon_ram_size/0x100000); err = mtrr_set_type(pci_info.base0,radeon_ram_size,MTRR_TYPE_WRCOMB); if(!err) printf(RADEON_MSG" Set write-combining type of video memory\n"); +#ifndef RAGE128 + { + memset(&rinfo,0,sizeof(rinfo_t)); + switch(def_cap.device_id) + { + case DEVICE_ATI_RADEON_VE_QY: + case DEVICE_ATI_RADEON_VE_QZ: + case DEVICE_ATI_RADEON_MOBILITY_M6: + case DEVICE_ATI_RADEON_MOBILITY_M62: + case DEVICE_ATI_RADEON_MOBILITY_M63: + case DEVICE_ATI_RADEON_QL: + case DEVICE_ATI_RADEON_8500_DV: + case DEVICE_ATI_RADEON_QW: + rinfo.hasCRTC2 = 1; + break; + default: break; + } + radeon_get_moninfo(&rinfo); + if(rinfo.hasCRTC2) { + printf(RADEON_MSG" DVI port has %s monitor connected\n",GET_MON_NAME(rinfo.dviDispType)); + printf(RADEON_MSG" CRT port has %s monitor connected\n",GET_MON_NAME(rinfo.crtDispType)); + } + else + printf(RADEON_MSG" CRT port has %s monitor connected\n",GET_MON_NAME(rinfo.crtDispType)); + } +#endif +#ifdef RADEON_ENABLE_BM + if(bm_open() == 0) + { + if((dma_phys_addrs = malloc(radeon_ram_size*sizeof(unsigned long)/4096)) != 0) + def_cap.flags |= FLAG_DMA | FLAG_EQ_DMA; + else + printf(RADEON_MSG" Can't allocate temopary buffer for DMA\n"); + } + else + if(__verbose) printf(RADEON_MSG" Can't initialize busmastering: %s\n",strerror(errno)); +#endif return 0; } @@ -931,6 +1102,7 @@ void vixDestroy( void ) { unmap_phys_mem(radeon_mem_base,radeon_ram_size); unmap_phys_mem(radeon_mmio_base,0xFFFF); + bm_close(); } int vixGetCapability(vidix_capability_t *to) @@ -939,8 +1111,14 @@ int vixGetCapability(vidix_capability_t *to) return 0; } +/* + Full list of fourcc which are supported by Win2K radeon driver: + YUY2, UYVY, DDES, OGLT, OGL2, OGLS, OGLB, OGNT, OGNZ, OGNS, + IF09, YVU9, IMC4, M2IA, IYUV, VBID, DXT1, DXT2, DXT3, DXT4, DXT5 +*/ uint32_t supported_fourcc[] = { + IMGFMT_Y800, IMGFMT_YVU9, IMGFMT_IF09, IMGFMT_YV12, IMGFMT_I420, IMGFMT_IYUV, IMGFMT_UYVY, IMGFMT_YUY2, IMGFMT_YVYU, IMGFMT_RGB15, IMGFMT_BGR15, @@ -1058,9 +1236,6 @@ static void radeon_vid_display_video( void ) bes_flags = SCALER_ENABLE | SCALER_SMART_SWITCH | -#ifdef RADEON - SCALER_HORZ_PICK_NEAREST | -#endif SCALER_Y2R_TEMP | SCALER_PIX_EXPAND; if(besr.double_buff) bes_flags |= SCALER_DOUBLE_BUFFER; @@ -1071,23 +1246,24 @@ static void radeon_vid_display_video( void ) switch(besr.fourcc) { case IMGFMT_RGB15: - case IMGFMT_BGR15: bes_flags |= SCALER_SOURCE_15BPP; break; + case IMGFMT_BGR15: bes_flags |= SCALER_SOURCE_15BPP | 0x10000000; break; case IMGFMT_RGB16: - case IMGFMT_BGR16: bes_flags |= SCALER_SOURCE_16BPP; break; + case IMGFMT_BGR16: bes_flags |= SCALER_SOURCE_16BPP | 0x10000000; break; /* case IMGFMT_RGB24: case IMGFMT_BGR24: bes_flags |= SCALER_SOURCE_24BPP; break; */ case IMGFMT_RGB32: - case IMGFMT_BGR32: bes_flags |= SCALER_SOURCE_32BPP; break; + case IMGFMT_BGR32: bes_flags |= SCALER_SOURCE_32BPP | 0x10000000; break; /* 4:1:0*/ case IMGFMT_IF09: case IMGFMT_YVU9: bes_flags |= SCALER_SOURCE_YUV9; break; + /* 4:0:0*/ + case IMGFMT_Y800: /* 4:2:0 */ case IMGFMT_IYUV: case IMGFMT_I420: - case IMGFMT_YV12: bes_flags |= SCALER_SOURCE_YUV12; - break; + case IMGFMT_YV12: bes_flags |= SCALER_SOURCE_YUV12; break; /* 4:2:2 */ case IMGFMT_YVYU: case IMGFMT_UYVY: bes_flags |= SCALER_SOURCE_YVYU422; break; @@ -1095,11 +1271,40 @@ static void radeon_vid_display_video( void ) default: bes_flags |= SCALER_SOURCE_VYUY422; break; } OUTREG(OV0_SCALE_CNTL, bes_flags); +#ifndef RAGE128 + if(rinfo.hasCRTC2 && + (rinfo.dviDispType == MT_CTV || rinfo.dviDispType == MT_STV)) + { + /* TODO: suppress scaler output to CRTC here and enable TVO only */ + } +#endif OUTREG(OV0_REG_LOAD_CNTL, 0); - if(__verbose > 1) printf(RADEON_MSG"we wanted: scaler=%08X\n",bes_flags); - if(__verbose > 1) radeon_vid_dump_regs(); + if(__verbose > VERBOSE_LEVEL) printf(RADEON_MSG"we wanted: scaler=%08X\n",bes_flags); + if(__verbose > VERBOSE_LEVEL) radeon_vid_dump_regs(); +} + +/* Goal of this function: hide RGB background and provide black screen around movie. + Useful in '-vo fbdev:vidix -fs -zoom' mode. + Reverse effect to colorkey */ +#ifdef RAGE128 +static void radeon_vid_exclusive( void ) +{ +/* this function works only with Rage128. + Radeon should has something the same */ + unsigned screenw,screenh; + screenw = radeon_get_xres(); + screenh = radeon_get_yres(); + radeon_fifo_wait(2); + OUTREG(OV0_EXCLUSIVE_VERT,(((screenh-1)<<16)&EXCL_VERT_END_MASK)); + OUTREG(OV0_EXCLUSIVE_HORZ,(((screenw/8+1)<<8)&EXCL_HORZ_END_MASK)|EXCL_HORZ_EXCLUSIVE_EN); } +static void radeon_vid_non_exclusive( void ) +{ + OUTREG(OV0_EXCLUSIVE_HORZ,0); +} +#endif + static unsigned radeon_query_pitch(unsigned fourcc,const vidix_yuv_t *spitch) { unsigned pitch,spy,spv,spu; @@ -1140,8 +1345,9 @@ static unsigned radeon_query_pitch(unsigned fourcc,const vidix_yuv_t *spitch) if(spy > 16 && spu == spy/2 && spv == spy/2) pitch = spy; else pitch = 32; break; + case IMGFMT_IF09: case IMGFMT_YVU9: - if(spy > 32 && spu == spy/4 && spv == spy/4) pitch = spy; + if(spy >= 64 && spu == spy/4 && spv == spy/4) pitch = spy; else pitch = 64; break; default: @@ -1155,16 +1361,19 @@ static unsigned radeon_query_pitch(unsigned fourcc,const vidix_yuv_t *spitch) static int radeon_vid_init_video( vidix_playback_t *config ) { uint32_t i,tmp,src_w,src_h,dest_w,dest_h,pitch,h_inc,step_by,left,leftUV,top; - int is_420,is_rgb32,is_rgb,best_pitch,mpitch; + int is_400,is_410,is_420,is_rgb32,is_rgb,best_pitch,mpitch; radeon_vid_stop_video(); left = config->src.x << 16; top = config->src.y << 16; src_h = config->src.h; src_w = config->src.w; - is_420 = is_rgb32 = is_rgb = 0; + is_400 = is_410 = is_420 = is_rgb32 = is_rgb = 0; if(config->fourcc == IMGFMT_YV12 || config->fourcc == IMGFMT_I420 || config->fourcc == IMGFMT_IYUV) is_420 = 1; + if(config->fourcc == IMGFMT_YVU9 || + config->fourcc == IMGFMT_IF09) is_410 = 1; + if(config->fourcc == IMGFMT_Y800) is_400 = 1; if(config->fourcc == IMGFMT_RGB32 || config->fourcc == IMGFMT_BGR32) is_rgb32 = 1; if(config->fourcc == IMGFMT_RGB32 || @@ -1179,7 +1388,11 @@ static int radeon_vid_init_video( vidix_playback_t *config ) mpitch = best_pitch-1; switch(config->fourcc) { + /* 4:0:0*/ + case IMGFMT_Y800: + /* 4:1:0*/ case IMGFMT_YVU9: + case IMGFMT_IF09: /* 4:2:0 */ case IMGFMT_IYUV: case IMGFMT_YV12: @@ -1222,27 +1435,73 @@ static int radeon_vid_init_video( vidix_playback_t *config ) config->offsets[0] = 0; for(i=1;i<besr.vid_nbufs;i++) config->offsets[i] = config->offsets[i-1]+config->frame_size; - if(is_420) + if(is_420 || is_410 || is_400) { uint32_t d1line,d2line,d3line; d1line = top*pitch; - d2line = src_h*pitch+(d1line>>2); - d3line = d2line+((src_h*pitch)>>2); + if(is_420) + { + d2line = src_h*pitch+(d1line>>2); + d3line = d2line+((src_h*pitch)>>2); + } + else + if(is_410) + { + d2line = src_h*pitch+(d1line>>4); + d3line = d2line+((src_h*pitch)>>4); + } + else + { + d2line = 0; + d3line = 0; + } d1line += (left >> 16) & ~15; - d2line += (left >> 17) & ~15; - d3line += (left >> 17) & ~15; + if(is_420) + { + d2line += (left >> 17) & ~15; + d3line += (left >> 17) & ~15; + } + else /* is_410 */ + { + d2line += (left >> 18) & ~15; + d3line += (left >> 18) & ~15; + } config->offset.y = d1line & VIF_BUF0_BASE_ADRS_MASK; - config->offset.v = d2line & VIF_BUF1_BASE_ADRS_MASK; - config->offset.u = d3line & VIF_BUF2_BASE_ADRS_MASK; + if(is_400) + { + config->offset.v = 0; + config->offset.u = 0; + } + else + { + config->offset.v = d2line & VIF_BUF1_BASE_ADRS_MASK; + config->offset.u = d3line & VIF_BUF2_BASE_ADRS_MASK; + } for(i=0;i<besr.vid_nbufs;i++) { besr.vid_buf_base_adrs_y[i]=((radeon_overlay_off+config->offsets[i]+config->offset.y)&VIF_BUF0_BASE_ADRS_MASK); - besr.vid_buf_base_adrs_v[i]=((radeon_overlay_off+config->offsets[i]+config->offset.v)&VIF_BUF1_BASE_ADRS_MASK)|VIF_BUF1_PITCH_SEL; - besr.vid_buf_base_adrs_u[i]=((radeon_overlay_off+config->offsets[i]+config->offset.u)&VIF_BUF2_BASE_ADRS_MASK)|VIF_BUF2_PITCH_SEL; + if(is_400) + { + besr.vid_buf_base_adrs_v[i]=0; + besr.vid_buf_base_adrs_u[i]=0; + } + else + { + besr.vid_buf_base_adrs_v[i]=((radeon_overlay_off+config->offsets[i]+config->offset.v)&VIF_BUF1_BASE_ADRS_MASK)|VIF_BUF1_PITCH_SEL; + besr.vid_buf_base_adrs_u[i]=((radeon_overlay_off+config->offsets[i]+config->offset.u)&VIF_BUF2_BASE_ADRS_MASK)|VIF_BUF2_PITCH_SEL; + } } config->offset.y = ((besr.vid_buf_base_adrs_y[0])&VIF_BUF0_BASE_ADRS_MASK) - radeon_overlay_off; - config->offset.v = ((besr.vid_buf_base_adrs_v[0])&VIF_BUF1_BASE_ADRS_MASK) - radeon_overlay_off; - config->offset.u = ((besr.vid_buf_base_adrs_u[0])&VIF_BUF2_BASE_ADRS_MASK) - radeon_overlay_off; + if(is_400) + { + config->offset.v = 0; + config->offset.u = 0; + } + else + { + config->offset.v = ((besr.vid_buf_base_adrs_v[0])&VIF_BUF1_BASE_ADRS_MASK) - radeon_overlay_off; + config->offset.u = ((besr.vid_buf_base_adrs_u[0])&VIF_BUF2_BASE_ADRS_MASK) - radeon_overlay_off; + } if(besr.fourcc == IMGFMT_I420 || besr.fourcc == IMGFMT_IYUV) { uint32_t tmp; @@ -1266,42 +1525,50 @@ static int radeon_vid_init_video( vidix_playback_t *config ) besr.p1_h_accum_init = ((tmp << 4) & 0x000f8000) | ((tmp << 12) & 0xf0000000); - tmp = ((left >> 1) & 0x0001ffff) + 0x00028000 + (h_inc << 2); - besr.p23_h_accum_init = ((tmp << 4) & 0x000f8000) | - ((tmp << 12) & 0x70000000); tmp = (top & 0x0000ffff) + 0x00018000; besr.p1_v_accum_init = ((tmp << 4) & OV0_P1_V_ACCUM_INIT_MASK) |(OV0_P1_MAX_LN_IN_PER_LN_OUT & 1); + tmp = ((left >> 1) & 0x0001ffff) + 0x00028000 + (h_inc << 2); + besr.p23_h_accum_init = ((tmp << 4) & 0x000f8000) | + ((tmp << 12) & 0x70000000); tmp = ((top >> 1) & 0x0000ffff) + 0x00018000; - besr.p23_v_accum_init = is_420 ? ((tmp << 4) & OV0_P23_V_ACCUM_INIT_MASK) + besr.p23_v_accum_init = (is_420||is_410) ? + ((tmp << 4) & OV0_P23_V_ACCUM_INIT_MASK) |(OV0_P23_MAX_LN_IN_PER_LN_OUT & 1) : 0; - - leftUV = (left >> 17) & 15; + leftUV = (left >> (is_410?18:17)) & 15; left = (left >> 16) & 15; - if(is_rgb && !is_rgb32) h_inc<<=1; - if(is_rgb32) - besr.h_inc = (h_inc >> 1) | ((h_inc >> 1) << 16); + if(is_rgb) + besr.h_inc = (h_inc)|(h_inc<<16); + else + if(is_410) + besr.h_inc = h_inc | ((h_inc >> 2) << 16); else besr.h_inc = h_inc | ((h_inc >> 1) << 16); besr.step_by = step_by | (step_by << 8); besr.y_x_start = (config->dest.x+X_ADJUST) | (config->dest.y << 16); besr.y_x_end = (config->dest.x + dest_w+X_ADJUST) | ((config->dest.y + dest_h) << 16); besr.p1_blank_lines_at_top = P1_BLNK_LN_AT_TOP_M1_MASK|((src_h-1)<<16); - if(is_420) + if(is_420 || is_410) { - src_h = (src_h + 1) >> 1; + src_h = (src_h + 1) >> (is_410?2:1); besr.p23_blank_lines_at_top = P23_BLNK_LN_AT_TOP_M1_MASK|((src_h-1)<<16); } else besr.p23_blank_lines_at_top = 0; besr.vid_buf_pitch0_value = pitch; - besr.vid_buf_pitch1_value = is_420 ? pitch>>1 : pitch; + besr.vid_buf_pitch1_value = is_410 ? pitch>>2 : is_420 ? pitch>>1 : pitch; besr.p1_x_start_end = (src_w+left-1)|(left<<16); - src_w>>=1; - besr.p2_x_start_end = (src_w+left-1)|(leftUV<<16); - besr.p3_x_start_end = besr.p2_x_start_end; - - + if(is_400) + { + besr.p2_x_start_end = 0; + besr.p3_x_start_end = 0; + } + else + { + if(is_410||is_420) src_w>>=is_410?2:1; + besr.p2_x_start_end = (src_w+left-1)|(leftUV<<16); + besr.p3_x_start_end = besr.p2_x_start_end; + } return 0; } @@ -1312,6 +1579,15 @@ static void radeon_compute_framesize(vidix_playback_t *info) dbpp = radeon_vid_get_dbpp(); switch(info->fourcc) { + case IMGFMT_Y800: + awidth = (info->src.w + (pitch-1)) & ~(pitch-1); + info->frame_size = awidth*info->src.h; + break; + case IMGFMT_YVU9: + case IMGFMT_IF09: + awidth = (info->src.w + (pitch-1)) & ~(pitch-1); + info->frame_size = awidth*(info->src.h+info->src.h/8); + break; case IMGFMT_I420: case IMGFMT_YV12: case IMGFMT_IYUV: @@ -1329,11 +1605,13 @@ static void radeon_compute_framesize(vidix_playback_t *info) info->frame_size = awidth*info->src.h; break; } + info->frame_size = (info->frame_size+4095)&~4095; } int vixConfigPlayback(vidix_playback_t *info) { unsigned rgb_size,nfr; + uint32_t radeon_video_size; if(!is_supported_fourcc(info->fourcc)) return ENOSYS; if(info->num_frames>VID_PLAY_MAXFRAMES) info->num_frames=VID_PLAY_MAXFRAMES; if(info->num_frames==1) besr.double_buff=0; @@ -1342,9 +1620,20 @@ int vixConfigPlayback(vidix_playback_t *info) rgb_size = radeon_get_xres()*radeon_get_yres()*((radeon_vid_get_dbpp()+7)/8); nfr = info->num_frames; + radeon_video_size = radeon_ram_size; +#ifdef RADEON_ENABLE_BM + if(def_cap.flags & FLAG_DMA) + { + /* every descriptor describes one 4K page and takes 16 bytes in memory + Note: probably it's ont good idea to locate them in video memory + but as initial release it's OK */ + radeon_video_size -= radeon_ram_size * sizeof(bm_list_descriptor) / 4096; + radeon_dma_desc_base = pci_info.base0 + radeon_video_size; + } +#endif for(;nfr>0; nfr--) { - radeon_overlay_off = radeon_ram_size - info->frame_size*nfr; + radeon_overlay_off = radeon_video_size - info->frame_size*nfr; radeon_overlay_off &= 0xffff0000; if(radeon_overlay_off >= (int)rgb_size ) break; } @@ -1353,7 +1642,7 @@ int vixConfigPlayback(vidix_playback_t *info) nfr = info->num_frames; for(;nfr>0; nfr--) { - radeon_overlay_off = radeon_ram_size - info->frame_size*nfr; + radeon_overlay_off = radeon_video_size - info->frame_size*nfr; radeon_overlay_off &= 0xffff0000; if(radeon_overlay_off > 0) break; } @@ -1368,7 +1657,16 @@ int vixConfigPlayback(vidix_playback_t *info) int vixPlaybackOn( void ) { +#ifdef RAGE128 + unsigned dw,dh; +#endif radeon_vid_display_video(); +#ifdef RAGE128 + dh = (besr.y_x_end >> 16) - (besr.y_x_start >> 16); + dw = (besr.y_x_end & 0xFFFF) - (besr.y_x_start & 0xFFFF); + if(dw == radeon_get_xres() || dh == radeon_get_yres()) radeon_vid_exclusive(); + else radeon_vid_non_exclusive(); +#endif return 0; } @@ -1407,7 +1705,7 @@ int vixPlaybackFrameSelect(unsigned frame) OUTREG(OV0_VID_BUF5_BASE_ADRS, off[5]); OUTREG(OV0_REG_LOAD_CNTL, 0); if(besr.vid_nbufs == 2) radeon_wait_vsync(); - if(__verbose > 1) radeon_vid_dump_regs(); + if(__verbose > VERBOSE_LEVEL) radeon_vid_dump_regs(); return 0; } @@ -1456,7 +1754,7 @@ int vixPlaybackSetEq( const vidix_video_eq_t * eq) #ifdef RAGE128 br = equal.brightness * 64 / 1000; if(br < -64) br = -64; if(br > 63) br = 63; - sat = (equal.saturation + 1000) * 16 / 1000; + sat = (equal.saturation*31 + 31000) / 2000; if(sat < 0) sat = 0; if(sat > 31) sat = 31; OUTREG(OV0_COLOUR_CNTL, (br & 0x7f) | (sat << 8) | (sat << 16)); #else @@ -1604,3 +1902,82 @@ int vixSetGrKeys(const vidix_grkey_t *grkey) set_gr_key(); return(0); } + +#ifdef RADEON_ENABLE_BM +static int radeon_setup_frame( vidix_dma_t * dmai ) +{ + bm_list_descriptor * list = (bm_list_descriptor *)radeon_dma_desc_base; + unsigned long dest_ptr; + unsigned i,n,count; + int retval; + if(dmai->dest_offset + dmai->size > radeon_ram_size) return E2BIG; + n = dmai->size / 4096; + if(dmai->size % 4096) n++; + if((retval = bm_virt_to_bus(dmai->src,dmai->size,dma_phys_addrs)) != 0) return retval; + dest_ptr = dmai->dest_offset; + count = dmai->size; + for(i=0;i<n;i++) + { + list[i].framebuf_offset = radeon_overlay_off + dest_ptr; + list[i].sys_addr = dma_phys_addrs[i]; +#ifdef RAGE128 + list[i].command = (count > 4096 ? 4096 : count | BM_END_OF_LIST)|BM_FORCE_TO_PCI; +#else + list[i].command = (count > 4096 ? 4096 : count | DMA_GUI_COMMAND__EOL); +#endif + list[i].reserved = 0; +printf("RADEON_DMA_TABLE[%i] %X %X %X %X\n",i,list[i].framebuf_offset,list[i].sys_addr,list[i].command,list[i].reserved); + dest_ptr += 4096; + count -= 4096; + } + return 0; +} + +static int radeon_transfer_frame( void ) +{ + unsigned i; + radeon_engine_idle(); + for(i=0;i<1000;i++) INREG(BUS_CNTL); /* FlushWriteCombining */ + OUTREG(BUS_CNTL,(INREG(BUS_CNTL) | BUS_STOP_REQ_DIS)&(~BUS_MASTER_DIS)); +#ifdef RAGE128 + OUTREG(BM_CHUNK_0_VAL,0x000000FF | BM_GLOBAL_FORCE_TO_PCI); + OUTREG(BM_CHUNK_1_VAL,0x0F0F0F0F); + OUTREG(BM_VIP0_BUF,bus_addr_dma_desc|SYSTEM_TRIGGER_SYSTEM_TO_VIDEO); +// OUTREG(GEN_INT_STATUS,INREG(GEN_INT_STATUS)|0x00010000); +#else + OUTREG(MC_FB_LOCATION, + ((pci_info.base0>>16)&0xffff)| + ((pci_info.base0+INREG(CONFIG_APER_SIZE)-1)&0xffff0000)); + if((INREG(MC_AGP_LOCATION)&0xffff)!= + (((pci_info.base0+INREG(CONFIG_APER_SIZE))>>16)&0xffff)) + /*Radeon memory controller is misconfigured*/ + return EINVAL; + OUTREG(DMA_VID_ACT_DSCRPTR,bus_addr_dma_desc); +// OUTREG(GEN_INT_STATUS,INREG(GEN_INT_STATUS)|(1<<30)); +#endif + OUTREG(GEN_INT_STATUS,INREG(GEN_INT_STATUS)|0x00010000); + return 0; +} + + +int vixPlaybackCopyFrame( vidix_dma_t * dmai ) +{ + int retval; + if(mlock(dmai->src,dmai->size) != 0) return errno; + retval = radeon_setup_frame(dmai); + if(retval == 0) retval = radeon_transfer_frame(); + munlock(dmai->src,dmai->size); + return retval; +} + +int vixQueryDMAStatus( void ) +{ + int bm_active; +#if 1 //def RAGE128 + bm_active=(INREG(GEN_INT_STATUS)&0x00010000)==0?1:0; +#else + bm_active=(INREG(GEN_INT_STATUS)&(1<<30))==0?1:0; +#endif + return bm_active?1:0; +} +#endif |