- pinnacle 300i starts working a bit.

1 files changed, 34 insertions, 79 deletions

diff --git a/linux/drivers/media/video/saa7134/saa7134-dvb.c b/linux/drivers/media/video/saa7134/saa7134-dvb.c
index 968a9080c..2d336498c 100644
--- a/linux/drivers/media/video/saa7134/saa7134-dvb.c
+++ b/linux/drivers/media/video/saa7134/saa7134-dvb.c
@@ -1,5 +1,5 @@
 /*
- * $Id: saa7134-dvb.c,v 1.8 2005/01/13 17:22:33 kraxel Exp $
+ * $Id: saa7134-dvb.c,v 1.9 2005/01/14 13:29:40 kraxel Exp $
  *
  * (c) 2004 Gerd Knorr <kraxel@bytesex.org> [SuSE Labs]
  *
@@ -39,56 +39,7 @@ MODULE_LICENSE("GPL");
 
 /* ------------------------------------------------------------------ */
 
-static int mt352_pinnacle_fixup(struct dvb_frontend* fe)
-{
-	static u8 wr[][2] = {
-		{ 0x67, 0x28 },
-		{ 0x68, 0xa0 },
-		
-		{ 0x7b, 0x04 },
-		
-		{ 0x88, 0x0d },
-		{ 0x8a, 0x28 },
-		{ 0x8c, 0x0f },
-	};
-	struct saa7134_dev *dev= fe->dvb->priv;
-	int i;
-	
-	printk("%s: %s called\n",dev->name,__FUNCTION__);
-	for (i = 0; i < ARRAY_SIZE(wr); i++) {
-		mt352_write(fe, wr[i], 2);
-	}
-}
-
-static int mt352_pinnacle_init(struct dvb_frontend* fe)
-{
-	static u8 clock_config []  = { CLOCK_CTL,  0x3d, 0x39 };
-	static u8 reset []         = { RESET,      0x80 };
-	static u8 adc_ctl_1_cfg [] = { ADC_CTL_1,  0x40 };
-	static u8 agc_cfg []       = { AGC_TARGET, 0x20, 0x20 };
-	static u8 capt_range_cfg[] = { CAPT_RANGE, 0x31 };
-#if 0
-	// general purpose port pins
-	static u8 gpp_ctl_cfg []   = { GPP_CTL,    0x33 };
-#endif
-	struct saa7134_dev *dev= fe->dvb->priv;
-
-	printk("%s: %s called\n",dev->name,__FUNCTION__);
-
-	mt352_write(fe, clock_config,   sizeof(clock_config));
-	udelay(200);
-	mt352_write(fe, reset,          sizeof(reset));
-	mt352_write(fe, adc_ctl_1_cfg,  sizeof(adc_ctl_1_cfg));
-	mt352_write(fe, agc_cfg,        sizeof(agc_cfg));
-	mt352_write(fe, capt_range_cfg, sizeof(capt_range_cfg));
-
-#if 0
-	mt352_write(fe, gpp_ctl_cfg,    sizeof(gpp_ctl_cfg));
-#endif
-	return 0;
-}
-
-static int mt352_pinnacle_antenna_pwr(struct saa7134_dev *dev, int on)
+static int pinnacle_antenna_pwr(struct saa7134_dev *dev, int on)
 {
 	u32 ok;
 
@@ -116,26 +67,41 @@ static int mt352_pinnacle_antenna_pwr(struct saa7134_dev *dev, int on)
 	return ok;
 }
 
+static int mt352_pinnacle_init(struct dvb_frontend* fe)
+{
+	static u8 clock_config []  = { CLOCK_CTL,  0x3d, 0x28 };
+	static u8 reset []         = { RESET,      0x80 };
+	static u8 adc_ctl_1_cfg [] = { ADC_CTL_1,  0x40 };
+	static u8 agc_cfg []       = { AGC_TARGET, 0x28, 0xa0 };
+	static u8 capt_range_cfg[] = { CAPT_RANGE, 0x31 };
+	static u8 fsm_ctl_cfg[]    = { 0x7b,       0x04 };
+	static u8 gpp_ctl_cfg []   = { GPP_CTL,    0x0f };
+	static u8 scan_ctl_cfg []  = { SCAN_CTL,   0x0d };
+	struct saa7134_dev *dev= fe->dvb->priv;
+
+	printk("%s: %s called\n",dev->name,__FUNCTION__);
+
+	mt352_write(fe, clock_config,   sizeof(clock_config));
+	udelay(200);
+	mt352_write(fe, reset,          sizeof(reset));
+	mt352_write(fe, adc_ctl_1_cfg,  sizeof(adc_ctl_1_cfg));
+	mt352_write(fe, agc_cfg,        sizeof(agc_cfg));
+	mt352_write(fe, capt_range_cfg, sizeof(capt_range_cfg));
+	mt352_write(fe, gpp_ctl_cfg,    sizeof(gpp_ctl_cfg));
+
+	mt352_write(fe, fsm_ctl_cfg,    sizeof(fsm_ctl_cfg));
+	mt352_write(fe, scan_ctl_cfg,   sizeof(scan_ctl_cfg));
+	return 0;
+}
+
 static int mt352_pinnacle_pll_set(struct dvb_frontend* fe,
 				  struct dvb_frontend_parameters* params,
 				  u8* pllbuf)
 {
-	static u8 buf[][3] = {
-		/* set bandwidth (ADC frequency is 20.333 MHz) */
-		[ BANDWIDTH_6_MHZ ] = { TRL_NOMINAL_RATE_1, 0x56, 0x55 },
-		[ BANDWIDTH_7_MHZ ] = { TRL_NOMINAL_RATE_1, 0x64, 0xB8 },
-		[ BANDWIDTH_8_MHZ ] = { TRL_NOMINAL_RATE_1, 0x73, 0x1C },
-	};
 	static int on  = TDA9887_PRESENT | TDA9887_PORT2_INACTIVE;
 	static int off = TDA9887_PRESENT | TDA9887_PORT2_ACTIVE;
 	struct saa7134_dev *dev = fe->dvb->priv;
 	struct v4l2_frequency f;
-	int bw = params->u.ofdm.bandwidth;
-
-	printk("%s: %s called (freq=%d,bw=%d)\n",dev->name,__FUNCTION__,
-	       params->frequency,bw);
-
-	mt352_pinnacle_antenna_pwr(dev, 0);
 
 	/* set frequency (mt2050) */
 	f.tuner     = 0;
@@ -145,34 +111,23 @@ static int mt352_pinnacle_pll_set(struct dvb_frontend* fe,
 	saa7134_i2c_call_clients(dev,VIDIOC_S_FREQUENCY,&f);
 	saa7134_i2c_call_clients(dev,TDA9887_SET_CONFIG,&off);
 
+	pinnacle_antenna_pwr(dev, 0);
+
 	/* mt352 setup */
 	mt352_pinnacle_init(fe);
-	mt352_pinnacle_fixup(fe);
-	
 	pllbuf[0] = 0xc2;
 	pllbuf[1] = 0x00;
 	pllbuf[2] = 0x00;
 	pllbuf[3] = 0x80;
 	pllbuf[4] = 0x00;
-
-	if (bw < ARRAY_SIZE(buf) && NULL != buf[bw]) {
-#if 1
-		/* dirty hack time -- fixup mt352 buffer which has
-		 * adc freq 20.48 MHz values hardcoded */
-		pllbuf[-4] = buf[bw][1];
-		pllbuf[-3] = buf[bw][2];
-		pllbuf[-2] = 0x31; /* if 36.15 + adc 20.333 */
-		pllbuf[-1] = 0xB8;
-#else
-		mt352_write(fe, buf[bw], 3);
-#endif
-	}
-		
 	return 0;
 }
 
 static struct mt352_config pinnacle_300i = {
 	.demod_address = 0x3c >> 1,
+	.adc_clock     = 20333,
+	.if2           = 36150,
+	.no_tuner      = 1,
 	.demod_init    = mt352_pinnacle_init,
 	.pll_set       = mt352_pinnacle_pll_set,
 };