diff options
Diffstat (limited to 'linux/drivers/media/video/saa711x_regs.h')
| -rw-r--r-- | linux/drivers/media/video/saa711x_regs.h | 549 |
1 files changed, 549 insertions, 0 deletions
diff --git a/linux/drivers/media/video/saa711x_regs.h b/linux/drivers/media/video/saa711x_regs.h new file mode 100644 index 000000000..5bf6b6d74 --- /dev/null +++ b/linux/drivers/media/video/saa711x_regs.h @@ -0,0 +1,549 @@ +/* saa711x - Philips SAA711x video decoder register specifications + * + * Copyright (c) 2006 Mauro Carvalho Chehab <mchehab@infradead.org> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define CHIP_VERSION 0x00 +/* Video Decoder */ + /* Video Decoder - Frontend part */ +#define INC_DELAY 0x01 +#define ANALOG_INPUT_CNTL_1 0x02 +#define ANALOG_INPUT_CNTL_2 0x03 +#define ANALOG_INPUT_CNTL_3 0x04 +#define ANALOG_INPUT_CNTL_4 0x05 + /* Video Decoder - Decoder part */ +#define HORIZ_SYNC_START 0x06 +#define HORIZ_SYNC_STOP 0x07 +#define SYNC_CNTL 0x08 +#define LUMA_CNTL 0x09 +#define LUMA_BRIGHTNESS_CNTL 0x0a +#define LUMA_CONTRAST_CNTL 0x0b +#define CHROMA_SATURATION_CNTL 0x0c +#define CHROMA_HUE_CNTL 0x0d +#define CHROMA_CNTL_1 0x0e +#define CHROMA_GAIN_CNTL 0x0f +#define CHROMA_CNTL_2 0x10 +#define MODE_DELAY_CNTL 0x11 +#define RT_SIGNAL_CNTL 0x12 +#define RT_X_PORT_OUTPUT_CNTL 0x13 +#define ANALOG_ADC_COMPAT_CNTL 0x14 +#define VGATE_START_FID_CHANGE 0x15 +#define VGATE_STOP 0x16 +#define MISC_VGATE_CONF_AND_MSBS 0x17 +#define RAW_DATA_GAIN_CNTL 0x18 +#define RAW_DATA_OFF_CNTL 0x19 +#define COLOR_KILLER_LEVEL_CNTL 0x1a +#define MISC_TVVCRDET 0x1b +#define ENHANCED_COMB_CTRL1 0x1c +#define ENHANCED_COMB_CTRL2 0x1d +#define STATUS_BYTE_1_VIDEO_DECODER 0x1e +#define STATUS_BYTE_2_VIDEO_DECODER 0x1f + +/* Component processing and interrupt masking part */ +#define ANALOG_INPUT_CNTL_5 0x23 +#define ANALOG_INPUT_CNTL_6 0x24 +#define ANALOG_INPUT_CNTL_7 0x25 +#define COMP_DELAY 0x29 +#define COMP_BRIGHTNESS_CNTL 0x2a +#define COMP_CONTRAST_CNTL 0x2b +#define COMP_SATURATION_CNTL 0x2c +#define INTERRUPT_MASK_1 0x2d +#define INTERRUPT_MASK_2 0x2e +#define INTERRUPT_MASK_3 0x2f + +/* Audio clock generator part */ +#define AUDIO_MASTER_CLOCK_CYCLES_PER_FIELD 0x30 +#define AUDIO_MASTER_CLOCK_NOMINAL_INC 0x34 +#define CLOCK_RATIO_AMXCLK_TO_ASCLK 0x38 +#define CLOCK_RATIO_ASCLK_TO_ALRCLK 0x39 +#define AUDIO_CLOCK_GENERATOR_BASIC_SETUP 0x3a + +/* General purpose VBI data slicer part */ +#define SLICER_CNTL_1 0x40 +#define LCR 0x41 +#define PROGRAMMABLE_FRAMING_CODE 0x58 +#define HORIZ_OFF_FOR_SLICER 0x59 +#define VERT_OFF_FOR_SLICER 0x5a +#define FIELD_OFF_AND_MSB_FOR_HORIZ_AND_VERT_OFF 0x5b +#define DID 0x5d +#define SDID 0x5e +#define SLICER_STATUS_BYTE_0 0x60 +#define SLICER_STATUS_BYTE_1 0x61 +#define SLICER_STATUS_BYTE_2 0x62 + +/* X port, I port and the scaler part */ + /* Task independent global settings */ +#define GLOBAL_CNTL_1 0x80 +#define VERT_SYNC_FLD_ID_SRC_SEL_AND_RETIMED_V_F 0x81 +#define X_PORT_I_O_ENABLE_AND_OUTPUT_CLOCK 0x83 +#define I_PORT_SIGNAL_DEFINITIONS 0x84 +#define I_PORT_SIGNAL_POLARITIES 0x85 +#define I_PORT_FIFO_FLAG_CNTL_AND_ARBITRATION 0x86 +#define I_PORT_I_O_ENABLE_OUTPUT_CLOCK_AND_GATED 0x87 +#define POWER_SAVE_ADC_PORT_CNTL 0x88 +#define STATUS_INFORMATION_SCALER_PART 0x8f + /* Task A definition */ + /* Basic settings and acquisition window definition */ +#define A_TASK_HANDLING_CNTL 0x90 +#define A_X_PORT_FORMATS_AND_CONF 0x91 +#define A_X_PORT_INPUT_REFERENCE_SIGNAL 0x92 +#define A_I_PORT_OUTPUT_FORMATS_AND_CONF 0x93 +#define A_HORIZ_INPUT_WINDOW_START 0x94 +#define A_HORIZ_INPUT_WINDOW_START_MSB 0x95 +#define A_HORIZ_INPUT_WINDOW_LENGTH 0x96 +#define A_HORIZ_INPUT_WINDOW_LENGTH_MSB 0x97 +#define A_VERT_INPUT_WINDOW_START 0x98 +#define A_VERT_INPUT_WINDOW_START_MSB 0x99 +#define A_VERT_INPUT_WINDOW_LENGTH 0x9a +#define A_VERT_INPUT_WINDOW_LENGTH_MSB 0x9b +#define A_HORIZ_OUTPUT_WINDOW_LENGTH 0x9c +#define A_HORIZ_OUTPUT_WINDOW_LENGTH_MSB 0x9d +#define A_VERT_OUTPUT_WINDOW_LENGTH 0x9e +#define A_VERT_OUTPUT_WINDOW_LENGTH_MSB 0x9f + /* FIR filtering and prescaling */ +#define A_HORIZ_PRESCALING 0xa0 +#define A_ACCUMULATION_LENGTH 0xa1 +#define A_PRESCALER_DC_GAIN_AND_FIR_PREFILTER 0xa2 +#define A_LUMA_BRIGHTNESS_CNTL 0xa4 +#define A_LUMA_CONTRAST_CNTL 0xa5 +#define A_CHROMA_SATURATION_CNTL 0xa6 + /* Horizontal phase scaling */ +#define A_HORIZ_LUMA_SCALING_INC 0xa8 +#define A_HORIZ_LUMA_SCALING_INC_MSB 0xa9 +#define A_HORIZ_LUMA_PHASE_OFF 0xaa +#define A_HORIZ_CHROMA_SCALING_INC 0xac +#define A_HORIZ_CHROMA_SCALING_INC_MSB 0xad +#define A_HORIZ_CHROMA_PHASE_OFF 0xae +#define A_HORIZ_CHROMA_PHASE_OFF_MSB 0xaf + /* Vertical scaling */ +#define A_VERT_LUMA_SCALING_INC 0xb0 +#define A_VERT_LUMA_SCALING_INC_MSB 0xb1 +#define A_VERT_CHROMA_SCALING_INC 0xb2 +#define A_VERT_CHROMA_SCALING_INC_MSB 0xb3 +#define A_VERT_SCALING_MODE_CNTL 0xb4 +#define A_VERT_CHROMA_PHASE_OFF_00 0xb8 +#define A_VERT_CHROMA_PHASE_OFF_01 0xb9 +#define A_VERT_CHROMA_PHASE_OFF_10 0xba +#define A_VERT_CHROMA_PHASE_OFF_11 0xbb +#define A_VERT_LUMA_PHASE_OFF_00 0xbc +#define A_VERT_LUMA_PHASE_OFF_01 0xbd +#define A_VERT_LUMA_PHASE_OFF_10 0xbe +#define A_VERT_LUMA_PHASE_OFF_11 0xbf + /* Task B definition */ + /* Basic settings and acquisition window definition */ +#define B_TASK_HANDLING_CNTL 0xc0 +#define B_X_PORT_FORMATS_AND_CONF 0xc1 +#define B_INPUT_REFERENCE_SIGNAL_DEFINITION 0xc2 +#define B_I_PORT_FORMATS_AND_CONF 0xc3 +#define B_HORIZ_INPUT_WINDOW_START 0xc4 +#define B_HORIZ_INPUT_WINDOW_START_MSB 0xc5 +#define B_HORIZ_INPUT_WINDOW_LENGTH 0xc6 +#define B_HORIZ_INPUT_WINDOW_LENGTH_MSB 0xc7 +#define B_VERT_INPUT_WINDOW_START 0xc8 +#define B_VERT_INPUT_WINDOW_START_MSB 0xc9 +#define B_VERT_INPUT_WINDOW_LENGTH 0xca +#define B_VERT_INPUT_WINDOW_LENGTH_MSB 0xcb +#define B_HORIZ_OUTPUT_WINDOW_LENGTH 0xcc +#define B_HORIZ_OUTPUT_WINDOW_LENGTH_MSB 0xcd +#define B_VERT_OUTPUT_WINDOW_LENGTH 0xce +#define B_VERT_OUTPUT_WINDOW_LENGTH_MSB 0xcf + /* FIR filtering and prescaling */ +#define B_HORIZ_PRESCALING 0xd0 +#define B_ACCUMULATION_LENGTH 0xd1 +#define B_PRESCALER_DC_GAIN_AND_FIR_PREFILTER 0xd2 +#define B_LUMA_BRIGHTNESS_CNTL 0xd4 +#define B_LUMA_CONTRAST_CNTL 0xd5 +#define B_CHROMA_SATURATION_CNTL 0xd6 + /* Horizontal phase scaling */ +#define B_HORIZ_LUMA_SCALING_INC 0xd8 +#define B_HORIZ_LUMA_SCALING_INC_MSB 0xd9 +#define B_HORIZ_LUMA_PHASE_OFF 0xda +#define B_HORIZ_CHROMA_SCALING 0xdc +#define B_HORIZ_CHROMA_SCALING_MSB 0xdd +#define B_HORIZ_PHASE_OFFSET_CRHOMA 0xde + /* Vertical scaling */ +#define B_VERT_LUMA_SCALING_INC 0xe0 +#define B_VERT_LUMA_SCALING_INC_MSB 0xe1 +#define B_VERT_CHROMA_SCALING_INC 0xe2 +#define B_VERT_CHROMA_SCALING_INC_MSB 0xe3 +#define B_VERT_SCALING_MODE_CNTL 0xe4 +#define B_VERT_CHROMA_PHASE_OFF_00 0xe8 +#define B_VERT_CHROMA_PHASE_OFF_01 0xe9 +#define B_VERT_CHROMA_PHASE_OFF_10 0xea +#define B_VERT_CHROMA_PHASE_OFF_11 0xeb +#define B_VERT_LUMA_PHASE_OFF_00 0xec +#define B_VERT_LUMA_PHASE_OFF_01 0xed +#define B_VERT_LUMA_PHASE_OFF_10 0xee +#define B_VERT_LUMA_PHASE_OFF_11 0xef + +/* second PLL (PLL2) and Pulsegenerator Programming */ +#define LFCO_PER_LINE 0xf0 +#define P_I_PARAM_SELECT 0xf1 +#define NOMINAL_PLL2_DTO 0xf2 +#define PLL_INCREMENT 0xf3 +#define PLL2_STATUS 0xf4 +#define PULSGEN_LINE_LENGTH 0xf5 +#define PULSE_A_POS_LSB_AND_PULSEGEN_CONFIG 0xf6 +#define PULSE_A_POS_MSB 0xf7 +#define PULSE_B_POS 0xf8 +#define PULSE_B_POS_MSB 0xf9 +#define PULSE_C_POS 0xfa +#define PULSE_C_POS_MSB 0xfb +#define S_PLL_MAX_PHASE_ERR_THRESH_NUM_LINES 0xff + +#if 0 /* keep */ +/* Those structs will be used in the future for debug purposes */ +struct saa711x_reg_descr { + u8 reg; + int count; + char *name; +}; + +struct saa711x_reg_descr saa711x_regs[] = { + /* REG COUNT NAME */ + {CHIP_VERSION,1, + "Chip version"}, + + /* Video Decoder: INC_DELAY to STATUS_BYTE_2_VIDEO_DECODER */ + + /* Video Decoder - Frontend part: INC_DELAY to ANALOG_INPUT_CNTL_4 */ + {INC_DELAY,1, + "Increment delay"}, + {ANALOG_INPUT_CNTL_1,1, + "Analog input control 1"}, + {ANALOG_INPUT_CNTL_2,1, + "Analog input control 2"}, + {ANALOG_INPUT_CNTL_3,1, + "Analog input control 3"}, + {ANALOG_INPUT_CNTL_4,1, + "Analog input control 4"}, + + /* Video Decoder - Decoder part: HORIZ_SYNC_START to STATUS_BYTE_2_VIDEO_DECODER */ + {HORIZ_SYNC_START,1, + "Horizontal sync start"}, + {HORIZ_SYNC_STOP,1, + "Horizontal sync stop"}, + {SYNC_CNTL,1, + "Sync control"}, + {LUMA_CNTL,1, + "Luminance control"}, + {LUMA_BRIGHTNESS_CNTL,1, + "Luminance brightness control"}, + {LUMA_CONTRAST_CNTL,1, + "Luminance contrast control"}, + {CHROMA_SATURATION_CNTL,1, + "Chrominance saturation control"}, + {CHROMA_HUE_CNTL,1, + "Chrominance hue control"}, + {CHROMA_CNTL_1,1, + "Chrominance control 1"}, + {CHROMA_GAIN_CNTL,1, + "Chrominance gain control"}, + {CHROMA_CNTL_2,1, + "Chrominance control 2"}, + {MODE_DELAY_CNTL,1, + "Mode/delay control"}, + {RT_SIGNAL_CNTL,1, + "RT signal control"}, + {RT_X_PORT_OUTPUT_CNTL,1, + "RT/X port output control"}, + {ANALOG_ADC_COMPAT_CNTL,1, + "Analog/ADC/compatibility control"}, + {VGATE_START_FID_CHANGE, 1, + "VGATE start FID change"}, + {VGATE_STOP,1, + "VGATE stop"}, + {MISC_VGATE_CONF_AND_MSBS, 1, + "Miscellaneous VGATE configuration and MSBs"}, + {RAW_DATA_GAIN_CNTL,1, + "Raw data gain control",}, + {RAW_DATA_OFF_CNTL,1, + "Raw data offset control",}, + {COLOR_KILLER_LEVEL_CNTL,1, + "Color Killer Level Control"}, + { MISC_TVVCRDET, 1, + "MISC /TVVCRDET"}, + { ENHANCED_COMB_CTRL1, 1, + "Enhanced comb ctrl1"}, + { ENHANCED_COMB_CTRL2, 1, + "Enhanced comb ctrl1"}, + {STATUS_BYTE_1_VIDEO_DECODER,1, + "Status byte 1 video decoder"}, + {STATUS_BYTE_2_VIDEO_DECODER,1, + "Status byte 2 video decoder"}, + + /* Component processing and interrupt masking part: 0x20h to INTERRUPT_MASK_3 */ + /* 0x20 to 0x22 - Reserved */ + {ANALOG_INPUT_CNTL_5,1, + "Analog input control 5"}, + {ANALOG_INPUT_CNTL_6,1, + "Analog input control 6"}, + {ANALOG_INPUT_CNTL_7,1, + "Analog input control 7"}, + /* 0x26 to 0x28 - Reserved */ + {COMP_DELAY,1, + "Component delay"}, + {COMP_BRIGHTNESS_CNTL,1, + "Component brightness control"}, + {COMP_CONTRAST_CNTL,1, + "Component contrast control"}, + {COMP_SATURATION_CNTL,1, + "Component saturation control"}, + {INTERRUPT_MASK_1,1, + "Interrupt mask 1"}, + {INTERRUPT_MASK_2,1, + "Interrupt mask 2"}, + {INTERRUPT_MASK_3,1, + "Interrupt mask 3"}, + + /* Audio clock generator part: AUDIO_MASTER_CLOCK_CYCLES_PER_FIELD to 0x3f */ + {AUDIO_MASTER_CLOCK_CYCLES_PER_FIELD,3, + "Audio master clock cycles per field"}, + /* 0x33 - Reserved */ + {AUDIO_MASTER_CLOCK_NOMINAL_INC,3, + "Audio master clock nominal increment"}, + /* 0x37 - Reserved */ + {CLOCK_RATIO_AMXCLK_TO_ASCLK,1, + "Clock ratio AMXCLK to ASCLK"}, + {CLOCK_RATIO_ASCLK_TO_ALRCLK,1, + "Clock ratio ASCLK to ALRCLK"}, + {AUDIO_CLOCK_GENERATOR_BASIC_SETUP,1, + "Audio clock generator basic setup"}, + /* 0x3b-0x3f - Reserved */ + + /* General purpose VBI data slicer part: SLICER_CNTL_1 to 0x7f */ + {SLICER_CNTL_1,1, + "Slicer control 1"}, + {LCR,23, + "LCR"}, + {PROGRAMMABLE_FRAMING_CODE,1, + "Programmable framing code"}, + {HORIZ_OFF_FOR_SLICER,1, + "Horizontal offset for slicer"}, + {VERT_OFF_FOR_SLICER,1, + "Vertical offset for slicer"}, + {FIELD_OFF_AND_MSB_FOR_HORIZ_AND_VERT_OFF,1, + "Field offset and MSBs for horizontal and vertical offset"}, + {DID,1, + "Header and data identification (DID)"}, + {SDID,1, + "Sliced data identification (SDID) code"}, + {SLICER_STATUS_BYTE_0,1, + "Slicer status byte 0"}, + {SLICER_STATUS_BYTE_1,1, + "Slicer status byte 1"}, + {SLICER_STATUS_BYTE_2,1, + "Slicer status byte 2"}, + /* 0x63-0x7f - Reserved */ + + /* X port, I port and the scaler part: GLOBAL_CNTL_1 to B_VERT_LUMA_PHASE_OFF_11 */ + /* Task independent global settings: GLOBAL_CNTL_1 to STATUS_INFORMATION_SCALER_PART */ + {GLOBAL_CNTL_1,1, + "Global control 1"}, + {VERT_SYNC_FLD_ID_SRC_SEL_AND_RETIMED_V_F,1, + "Vertical sync and Field ID source selection, retimed V and F signals"}, + /* 0x82 - Reserved */ + {X_PORT_I_O_ENABLE_AND_OUTPUT_CLOCK,1, + "X port I/O enable and output clock"}, + {I_PORT_SIGNAL_DEFINITIONS,1, + "I port signal definitions"}, + {I_PORT_SIGNAL_POLARITIES,1, + "I port signal polarities"}, + {I_PORT_FIFO_FLAG_CNTL_AND_ARBITRATION,1, + "I port FIFO flag control and arbitration"}, + {I_PORT_I_O_ENABLE_OUTPUT_CLOCK_AND_GATED, 1, + "I port I/O enable output clock and gated"}, + {POWER_SAVE_ADC_PORT_CNTL,1, + "Power save/ADC port control"}, + /* 089-0x8e - Reserved */ + {STATUS_INFORMATION_SCALER_PART,1, + "Status information scaler part"}, + + /* Task A definition: A_TASK_HANDLING_CNTL to A_VERT_LUMA_PHASE_OFF_11 */ + /* Task A: Basic settings and acquisition window definition */ + {A_TASK_HANDLING_CNTL,1, + "Task A: Task handling control"}, + {A_X_PORT_FORMATS_AND_CONF,1, + "Task A: X port formats and configuration"}, + {A_X_PORT_INPUT_REFERENCE_SIGNAL,1, + "Task A: X port input reference signal definition"}, + {A_I_PORT_OUTPUT_FORMATS_AND_CONF,1, + "Task A: I port output formats and configuration"}, + {A_HORIZ_INPUT_WINDOW_START,2, + "Task A: Horizontal input window start"}, + {A_HORIZ_INPUT_WINDOW_LENGTH,2, + "Task A: Horizontal input window length"}, + {A_VERT_INPUT_WINDOW_START,2, + "Task A: Vertical input window start"}, + {A_VERT_INPUT_WINDOW_LENGTH,2, + "Task A: Vertical input window length"}, + {A_HORIZ_OUTPUT_WINDOW_LENGTH,2, + "Task A: Horizontal output window length"}, + {A_VERT_OUTPUT_WINDOW_LENGTH,2, + "Task A: Vertical output window length"}, + + /* Task A: FIR filtering and prescaling */ + {A_HORIZ_PRESCALING,1, + "Task A: Horizontal prescaling"}, + {A_ACCUMULATION_LENGTH,1, + "Task A: Accumulation length"}, + {A_PRESCALER_DC_GAIN_AND_FIR_PREFILTER,1, + "Task A: Prescaler DC gain and FIR prefilter"}, + /* 0xa3 - Reserved */ + {A_LUMA_BRIGHTNESS_CNTL,1, + "Task A: Luminance brightness control"}, + {A_LUMA_CONTRAST_CNTL,1, + "Task A: Luminance contrast control"}, + {A_CHROMA_SATURATION_CNTL,1, + "Task A: Chrominance saturation control"}, + /* 0xa7 - Reserved */ + + /* Task A: Horizontal phase scaling */ + {A_HORIZ_LUMA_SCALING_INC,2, + "Task A: Horizontal luminance scaling increment"}, + {A_HORIZ_LUMA_PHASE_OFF,1, + "Task A: Horizontal luminance phase offset"}, + /* 0xab - Reserved */ + {A_HORIZ_CHROMA_SCALING_INC,2, + "Task A: Horizontal chrominance scaling increment"}, + {A_HORIZ_CHROMA_PHASE_OFF,1, + "Task A: Horizontal chrominance phase offset"}, + /* 0xaf - Reserved */ + + /* Task A: Vertical scaling */ + {A_VERT_LUMA_SCALING_INC,2, + "Task A: Vertical luminance scaling increment"}, + {A_VERT_CHROMA_SCALING_INC,2, + "Task A: Vertical chrominance scaling increment"}, + {A_VERT_SCALING_MODE_CNTL,1, + "Task A: Vertical scaling mode control"}, + /* 0xb5-0xb7 - Reserved */ + {A_VERT_CHROMA_PHASE_OFF_00,1, + "Task A: Vertical chrominance phase offset '00'"}, + {A_VERT_CHROMA_PHASE_OFF_01,1, + "Task A: Vertical chrominance phase offset '01'"}, + {A_VERT_CHROMA_PHASE_OFF_10,1, + "Task A: Vertical chrominance phase offset '10'"}, + {A_VERT_CHROMA_PHASE_OFF_11,1, + "Task A: Vertical chrominance phase offset '11'"}, + {A_VERT_LUMA_PHASE_OFF_00,1, + "Task A: Vertical luminance phase offset '00'"}, + {A_VERT_LUMA_PHASE_OFF_01,1, + "Task A: Vertical luminance phase offset '01'"}, + {A_VERT_LUMA_PHASE_OFF_10,1, + "Task A: Vertical luminance phase offset '10'"}, + {A_VERT_LUMA_PHASE_OFF_11,1, + "Task A: Vertical luminance phase offset '11'"}, + + /* Task B definition: B_TASK_HANDLING_CNTL to B_VERT_LUMA_PHASE_OFF_11 */ + /* Task B: Basic settings and acquisition window definition */ + {B_TASK_HANDLING_CNTL,1, + "Task B: Task handling control"}, + {B_X_PORT_FORMATS_AND_CONF,1, + "Task B: X port formats and configuration"}, + {B_INPUT_REFERENCE_SIGNAL_DEFINITION,1, + "Task B: Input reference signal definition"}, + {B_I_PORT_FORMATS_AND_CONF,1, + "Task B: I port formats and configuration"}, + {B_HORIZ_INPUT_WINDOW_START,2, + "Task B: Horizontal input window start"}, + {B_HORIZ_INPUT_WINDOW_LENGTH,2, + "Task B: Horizontal input window length"}, + {B_VERT_INPUT_WINDOW_START,2, + "Task B: Vertical input window start"}, + {B_VERT_INPUT_WINDOW_LENGTH,2, + "Task B: Vertical input window length"}, + {B_HORIZ_OUTPUT_WINDOW_LENGTH,2, + "Task B: Horizontal output window length"}, + {B_VERT_OUTPUT_WINDOW_LENGTH,2, + "Task B: Vertical output window length"}, + + /* Task B: FIR filtering and prescaling */ + {B_HORIZ_PRESCALING,1, + "Task B: Horizontal prescaling"}, + {B_ACCUMULATION_LENGTH,1, + "Task B: Accumulation length"}, + {B_PRESCALER_DC_GAIN_AND_FIR_PREFILTER,1, + "Task B: Prescaler DC gain and FIR prefilter"}, + /* 0xd3 - Reserved */ + {B_LUMA_BRIGHTNESS_CNTL,1, + "Task B: Luminance brightness control"}, + {B_LUMA_CONTRAST_CNTL,1, + "Task B: Luminance contrast control"}, + {B_CHROMA_SATURATION_CNTL,1, + "Task B: Chrominance saturation control"}, + /* 0xd7 - Reserved */ + + /* Task B: Horizontal phase scaling */ + {B_HORIZ_LUMA_SCALING_INC,2, + "Task B: Horizontal luminance scaling increment"}, + {B_HORIZ_LUMA_PHASE_OFF,1, + "Task B: Horizontal luminance phase offset"}, + /* 0xdb - Reserved */ + {B_HORIZ_CHROMA_SCALING,2, + "Task B: Horizontal chrominance scaling"}, + {B_HORIZ_PHASE_OFFSET_CRHOMA,1, + "Task B: Horizontal Phase Offset Chroma"}, + /* 0xdf - Reserved */ + + /* Task B: Vertical scaling */ + {B_VERT_LUMA_SCALING_INC,2, + "Task B: Vertical luminance scaling increment"}, + {B_VERT_CHROMA_SCALING_INC,2, + "Task B: Vertical chrominance scaling increment"}, + {B_VERT_SCALING_MODE_CNTL,1, + "Task B: Vertical scaling mode control"}, + /* 0xe5-0xe7 - Reserved */ + {B_VERT_CHROMA_PHASE_OFF_00,1, + "Task B: Vertical chrominance phase offset '00'"}, + {B_VERT_CHROMA_PHASE_OFF_01,1, + "Task B: Vertical chrominance phase offset '01'"}, + {B_VERT_CHROMA_PHASE_OFF_10,1, + "Task B: Vertical chrominance phase offset '10'"}, + {B_VERT_CHROMA_PHASE_OFF_11,1, + "Task B: Vertical chrominance phase offset '11'"}, + {B_VERT_LUMA_PHASE_OFF_00,1, + "Task B: Vertical luminance phase offset '00'"}, + {B_VERT_LUMA_PHASE_OFF_01,1, + "Task B: Vertical luminance phase offset '01'"}, + {B_VERT_LUMA_PHASE_OFF_10,1, + "Task B: Vertical luminance phase offset '10'"}, + {B_VERT_LUMA_PHASE_OFF_11,1, + "Task B: Vertical luminance phase offset '11'"}, + + /* second PLL (PLL2) and Pulsegenerator Programming */ + { LFCO_PER_LINE, 1, + "LFCO's per line"}, + { P_I_PARAM_SELECT,1, + "P-/I- Param. Select., PLL Mode, PLL H-Src., LFCO's per line"}, + { NOMINAL_PLL2_DTO,1, + "Nominal PLL2 DTO"}, + {PLL_INCREMENT,1, + "PLL2 Increment"}, + {PLL2_STATUS,1, + "PLL2 Status"}, + {PULSGEN_LINE_LENGTH,1, + "Pulsgen. line length"}, + {PULSE_A_POS_LSB_AND_PULSEGEN_CONFIG,1, + "Pulse A Position, Pulsgen Resync., Pulsgen. H-Src., Pulsgen. line length"}, + {PULSE_A_POS_MSB,1, + "Pulse A Position"}, + {PULSE_B_POS,2, + "Pulse B Position"}, + {PULSE_C_POS,2, + "Pulse C Position"}, + /* 0xfc to 0xfe - Reserved */ + {S_PLL_MAX_PHASE_ERR_THRESH_NUM_LINES,1, + "S_PLL max. phase, error threshold, PLL2 no. of lines, threshold"}, +}; +#endif |